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NVMe: Add persistent reservation ops
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
8de05535 15#include <linux/bitops.h>
b60503ba 16#include <linux/blkdev.h>
a4aea562 17#include <linux/blk-mq.h>
42f61420 18#include <linux/cpu.h>
fd63e9ce 19#include <linux/delay.h>
b60503ba
MW		 20#include <linux/errno.h>
21#include <linux/fs.h>
22#include <linux/genhd.h>
4cc09e2d 23#include <linux/hdreg.h>
5aff9382 24#include <linux/idr.h>
b60503ba
MW		 25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kdev_t.h>
1fa6aead 29#include <linux/kthread.h>
b60503ba 30#include <linux/kernel.h>
a5768aa8 31#include <linux/list_sort.h>
b60503ba
MW		 32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
e1e5e564 40#include <linux/t10-pi.h>
b60503ba 41#include <linux/types.h>
1d277a63 42#include <linux/pr.h>
5d0f6131 43#include <scsi/sg.h>
797a796a 44#include <asm-generic/io-64-nonatomic-lo-hi.h>
1d277a63 45#include <asm/unaligned.h>
797a796a 46
9d99a8dd 47#include <uapi/linux/nvme_ioctl.h>
f11bb3e2
CH		 48#include "nvme.h"
49
b3fffdef 50#define NVME_MINORS (1U << MINORBITS)
9d43cf64 51#define NVME_Q_DEPTH 1024
d31af0a3 52#define NVME_AQ_DEPTH 256
b60503ba
MW		 53#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 55#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 56#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 57
58static unsigned char admin_timeout = 60;
59module_param(admin_timeout, byte, 0644);
60MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 61
bd67608a
MW		 62unsigned char nvme_io_timeout = 30;
63module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 64MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 65
2484f407
DM		 66static unsigned char shutdown_timeout = 5;
67module_param(shutdown_timeout, byte, 0644);
68MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69
b60503ba
MW		 70static int nvme_major;
71module_param(nvme_major, int, 0);
72
b3fffdef
KB		 73static int nvme_char_major;
74module_param(nvme_char_major, int, 0);
75
58ffacb5
MW		 76static int use_threaded_interrupts;
77module_param(use_threaded_interrupts, int, 0);
78
8ffaadf7
JD		 79static bool use_cmb_sqes = true;
80module_param(use_cmb_sqes, bool, 0644);
81MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
82
1fa6aead
MW		 83static DEFINE_SPINLOCK(dev_list_lock);
84static LIST_HEAD(dev_list);
85static struct task_struct *nvme_thread;
9a6b9458 86static struct workqueue_struct *nvme_workq;
b9afca3e 87static wait_queue_head_t nvme_kthread_wait;
1fa6aead 88
b3fffdef
KB		 89static struct class *nvme_class;
90
90667892 91static int __nvme_reset(struct nvme_dev *dev);
4cc06521 92static int nvme_reset(struct nvme_dev *dev);
a4aea562 93static int nvme_process_cq(struct nvme_queue *nvmeq);
3cf519b5 94static void nvme_dead_ctrl(struct nvme_dev *dev);
d4b4ff8e 95
4d115420
KB		 96struct async_cmd_info {
97 struct kthread_work work;
98 struct kthread_worker *worker;
a4aea562 99 struct request *req;
4d115420
KB		 100 u32 result;
101 int status;
102 void *ctx;
103};
1fa6aead 104
b60503ba
MW		 105/*
106 * An NVM Express queue. Each device has at least two (one for admin
107 * commands and one for I/O commands).
108 */
109struct nvme_queue {
110 struct device *q_dmadev;
091b6092 111 struct nvme_dev *dev;
3193f07b 112 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 113 spinlock_t q_lock;
114 struct nvme_command *sq_cmds;
8ffaadf7 115 struct nvme_command __iomem *sq_cmds_io;
b60503ba 116 volatile struct nvme_completion *cqes;
42483228 117 struct blk_mq_tags **tags;
b60503ba
MW		 118 dma_addr_t sq_dma_addr;
119 dma_addr_t cq_dma_addr;
b60503ba
MW		 120 u32 __iomem *q_db;
121 u16 q_depth;
6222d172 122 s16 cq_vector;
b60503ba
MW		 123 u16 sq_head;
124 u16 sq_tail;
125 u16 cq_head;
c30341dc 126 u16 qid;
e9539f47
MW		 127 u8 cq_phase;
128 u8 cqe_seen;
4d115420 129 struct async_cmd_info cmdinfo;
b60503ba
MW		 130};
131
132/*
133 * Check we didin't inadvertently grow the command struct
134 */
135static inline void _nvme_check_size(void)
136{
137 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 142 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 143 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 144 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
145 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
146 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
147 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 148 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 149}
150
edd10d33 151typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 152 struct nvme_completion *);
153
e85248e5 154struct nvme_cmd_info {
c2f5b650
MW		 155 nvme_completion_fn fn;
156 void *ctx;
c30341dc 157 int aborted;
a4aea562 158 struct nvme_queue *nvmeq;
ac3dd5bd 159 struct nvme_iod iod[0];
e85248e5
MW		 160};
161
ac3dd5bd
JA		 162/*
163 * Max size of iod being embedded in the request payload
164 */
165#define NVME_INT_PAGES 2
166#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
fda631ff 167#define NVME_INT_MASK 0x01
ac3dd5bd
JA		 168
169/*
170 * Will slightly overestimate the number of pages needed. This is OK
171 * as it only leads to a small amount of wasted memory for the lifetime of
172 * the I/O.
173 */
174static int nvme_npages(unsigned size, struct nvme_dev *dev)
175{
176 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
177 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
178}
179
180static unsigned int nvme_cmd_size(struct nvme_dev *dev)
181{
182 unsigned int ret = sizeof(struct nvme_cmd_info);
183
184 ret += sizeof(struct nvme_iod);
185 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
186 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
187
188 return ret;
189}
190
a4aea562
MB		 191static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
192 unsigned int hctx_idx)
e85248e5 193{
a4aea562
MB		 194 struct nvme_dev *dev = data;
195 struct nvme_queue *nvmeq = dev->queues[0];
196
42483228
KB		 197 WARN_ON(hctx_idx != 0);
198 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
199 WARN_ON(nvmeq->tags);
200
a4aea562 201 hctx->driver_data = nvmeq;
42483228 202 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 203 return 0;
e85248e5
MW		 204}
205
4af0e21c
KB		 206static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
207{
208 struct nvme_queue *nvmeq = hctx->driver_data;
209
210 nvmeq->tags = NULL;
211}
212
a4aea562
MB		 213static int nvme_admin_init_request(void *data, struct request *req,
214 unsigned int hctx_idx, unsigned int rq_idx,
215 unsigned int numa_node)
22404274 216{
a4aea562
MB		 217 struct nvme_dev *dev = data;
218 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
219 struct nvme_queue *nvmeq = dev->queues[0];
220
221 BUG_ON(!nvmeq);
222 cmd->nvmeq = nvmeq;
223 return 0;
22404274
KB		 224}
225
a4aea562
MB		 226static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
227 unsigned int hctx_idx)
b60503ba 228{
a4aea562 229 struct nvme_dev *dev = data;
42483228 230 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
a4aea562 231
42483228
KB		 232 if (!nvmeq->tags)
233 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 234
42483228 235 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 236 hctx->driver_data = nvmeq;
237 return 0;
b60503ba
MW		 238}
239
a4aea562
MB		 240static int nvme_init_request(void *data, struct request *req,
241 unsigned int hctx_idx, unsigned int rq_idx,
242 unsigned int numa_node)
b60503ba 243{
a4aea562
MB		 244 struct nvme_dev *dev = data;
245 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
246 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
247
248 BUG_ON(!nvmeq);
249 cmd->nvmeq = nvmeq;
250 return 0;
251}
252
253static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
254 nvme_completion_fn handler)
255{
256 cmd->fn = handler;
257 cmd->ctx = ctx;
258 cmd->aborted = 0;
c917dfe5 259 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 260}
261
ac3dd5bd
JA		 262static void *iod_get_private(struct nvme_iod *iod)
263{
264 return (void *) (iod->private & ~0x1UL);
265}
266
267/*
268 * If bit 0 is set, the iod is embedded in the request payload.
269 */
270static bool iod_should_kfree(struct nvme_iod *iod)
271{
fda631ff 272 return (iod->private & NVME_INT_MASK) == 0;
ac3dd5bd
JA		 273}
274
c2f5b650
MW		 275/* Special values must be less than 0x1000 */
276#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 277#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
278#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
279#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 280
edd10d33 281static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 282 struct nvme_completion *cqe)
283{
284 if (ctx == CMD_CTX_CANCELLED)
285 return;
c2f5b650 286 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 287 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 288 "completed id %d twice on queue %d\n",
289 cqe->command_id, le16_to_cpup(&cqe->sq_id));
290 return;
291 }
292 if (ctx == CMD_CTX_INVALID) {
edd10d33 293 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 294 "invalid id %d completed on queue %d\n",
295 cqe->command_id, le16_to_cpup(&cqe->sq_id));
296 return;
297 }
edd10d33 298 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 299}
300
a4aea562 301static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 302{
c2f5b650 303 void *ctx;
b60503ba 304
859361a2 305 if (fn)
a4aea562
MB		 306 *fn = cmd->fn;
307 ctx = cmd->ctx;
308 cmd->fn = special_completion;
309 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 310 return ctx;
b60503ba
MW		 311}
312
a4aea562
MB		 313static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
314 struct nvme_completion *cqe)
3c0cf138 315{
a4aea562
MB		 316 u32 result = le32_to_cpup(&cqe->result);
317 u16 status = le16_to_cpup(&cqe->status) >> 1;
318
319 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
320 ++nvmeq->dev->event_limit;
a5768aa8
KB		 321 if (status != NVME_SC_SUCCESS)
322 return;
323
324 switch (result & 0xff07) {
325 case NVME_AER_NOTICE_NS_CHANGED:
326 dev_info(nvmeq->q_dmadev, "rescanning\n");
327 schedule_work(&nvmeq->dev->scan_work);
328 default:
329 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
330 }
b60503ba
MW		 331}
332
a4aea562
MB		 333static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
334 struct nvme_completion *cqe)
5a92e700 335{
a4aea562
MB		 336 struct request *req = ctx;
337
338 u16 status = le16_to_cpup(&cqe->status) >> 1;
339 u32 result = le32_to_cpup(&cqe->result);
a51afb54 340
42483228 341 blk_mq_free_request(req);
a51afb54 342
a4aea562
MB		 343 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
344 ++nvmeq->dev->abort_limit;
5a92e700
KB		 345}
346
a4aea562
MB		 347static void async_completion(struct nvme_queue *nvmeq, void *ctx,
348 struct nvme_completion *cqe)
b60503ba 349{
a4aea562
MB		 350 struct async_cmd_info *cmdinfo = ctx;
351 cmdinfo->result = le32_to_cpup(&cqe->result);
352 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
353 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
42483228 354 blk_mq_free_request(cmdinfo->req);
b60503ba
MW		 355}
356
a4aea562
MB		 357static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
358 unsigned int tag)
b60503ba 359{
42483228 360 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
a51afb54 361
a4aea562 362 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 363}
364
a4aea562
MB		 365/*
366 * Called with local interrupts disabled and the q_lock held. May not sleep.
367 */
368static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
369 nvme_completion_fn *fn)
4f5099af 370{
a4aea562
MB		 371 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
372 void *ctx;
373 if (tag >= nvmeq->q_depth) {
374 *fn = special_completion;
375 return CMD_CTX_INVALID;
376 }
377 if (fn)
378 *fn = cmd->fn;
379 ctx = cmd->ctx;
380 cmd->fn = special_completion;
381 cmd->ctx = CMD_CTX_COMPLETED;
382 return ctx;
b60503ba
MW		 383}
384
385/**
714a7a22 386 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 387 * @nvmeq: The queue to use
388 * @cmd: The command to send
389 *
390 * Safe to use from interrupt context
391 */
e3f879bf
SB		 392static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
393 struct nvme_command *cmd)
b60503ba 394{
a4aea562
MB		 395 u16 tail = nvmeq->sq_tail;
396
8ffaadf7
JD		 397 if (nvmeq->sq_cmds_io)
398 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
399 else
400 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
401
b60503ba
MW		 402 if (++tail == nvmeq->q_depth)
403 tail = 0;
7547881d 404 writel(tail, nvmeq->q_db);
b60503ba 405 nvmeq->sq_tail = tail;
b60503ba
MW		 406}
407
e3f879bf 408static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
a4aea562
MB		 409{
410 unsigned long flags;
a4aea562 411 spin_lock_irqsave(&nvmeq->q_lock, flags);
e3f879bf 412 __nvme_submit_cmd(nvmeq, cmd);
a4aea562 413 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
a4aea562
MB		 414}
415
eca18b23 416static __le64 **iod_list(struct nvme_iod *iod)
e025344c 417{
eca18b23 418 return ((void *)iod) + iod->offset;
e025344c
SMM		 419}
420
ac3dd5bd
JA		 421static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
422 unsigned nseg, unsigned long private)
eca18b23 423{
ac3dd5bd
JA		 424 iod->private = private;
425 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
426 iod->npages = -1;
427 iod->length = nbytes;
428 iod->nents = 0;
eca18b23 429}
b60503ba 430
eca18b23 431static struct nvme_iod *
ac3dd5bd
JA		 432__nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
433 unsigned long priv, gfp_t gfp)
b60503ba 434{
eca18b23 435 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
ac3dd5bd 436 sizeof(__le64 *) * nvme_npages(bytes, dev) +
eca18b23
MW		 437 sizeof(struct scatterlist) * nseg, gfp);
438
ac3dd5bd
JA		 439 if (iod)
440 iod_init(iod, bytes, nseg, priv);
eca18b23
MW		 441
442 return iod;
b60503ba
MW		 443}
444
ac3dd5bd
JA		 445static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
446 gfp_t gfp)
447{
448 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
449 sizeof(struct nvme_dsm_range);
ac3dd5bd
JA		 450 struct nvme_iod *iod;
451
452 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
453 size <= NVME_INT_BYTES(dev)) {
454 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
455
456 iod = cmd->iod;
ac3dd5bd 457 iod_init(iod, size, rq->nr_phys_segments,
fda631ff 458 (unsigned long) rq | NVME_INT_MASK);
ac3dd5bd
JA		 459 return iod;
460 }
461
462 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
463 (unsigned long) rq, gfp);
464}
465
d29ec824 466static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 467{
1d090624 468 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 469 int i;
470 __le64 **list = iod_list(iod);
471 dma_addr_t prp_dma = iod->first_dma;
472
473 if (iod->npages == 0)
474 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
475 for (i = 0; i < iod->npages; i++) {
476 __le64 *prp_list = list[i];
477 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
478 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
479 prp_dma = next_prp_dma;
480 }
ac3dd5bd
JA		 481
482 if (iod_should_kfree(iod))
483 kfree(iod);
b60503ba
MW		 484}
485
b4ff9c8d
KB		 486static int nvme_error_status(u16 status)
487{
488 switch (status & 0x7ff) {
489 case NVME_SC_SUCCESS:
490 return 0;
491 case NVME_SC_CAP_EXCEEDED:
492 return -ENOSPC;
493 default:
494 return -EIO;
495 }
496}
497
52b68d7e 498#ifdef CONFIG_BLK_DEV_INTEGRITY
e1e5e564
KB		 499static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
500{
501 if (be32_to_cpu(pi->ref_tag) == v)
502 pi->ref_tag = cpu_to_be32(p);
503}
504
505static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
506{
507 if (be32_to_cpu(pi->ref_tag) == p)
508 pi->ref_tag = cpu_to_be32(v);
509}
510
511/**
512 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
513 *
514 * The virtual start sector is the one that was originally submitted by the
515 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
516 * start sector may be different. Remap protection information to match the
517 * physical LBA on writes, and back to the original seed on reads.
518 *
519 * Type 0 and 3 do not have a ref tag, so no remapping required.
520 */
521static void nvme_dif_remap(struct request *req,
522 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
523{
524 struct nvme_ns *ns = req->rq_disk->private_data;
525 struct bio_integrity_payload *bip;
526 struct t10_pi_tuple *pi;
527 void *p, *pmap;
528 u32 i, nlb, ts, phys, virt;
529
530 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
531 return;
532
533 bip = bio_integrity(req->bio);
534 if (!bip)
535 return;
536
537 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
e1e5e564
KB		 538
539 p = pmap;
540 virt = bip_get_seed(bip);
541 phys = nvme_block_nr(ns, blk_rq_pos(req));
542 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
543 ts = ns->disk->integrity->tuple_size;
544
545 for (i = 0; i < nlb; i++, virt++, phys++) {
546 pi = (struct t10_pi_tuple *)p;
547 dif_swap(phys, virt, pi);
548 p += ts;
549 }
550 kunmap_atomic(pmap);
551}
552
52b68d7e
KB		 553static int nvme_noop_verify(struct blk_integrity_iter *iter)
554{
555 return 0;
556}
557
558static int nvme_noop_generate(struct blk_integrity_iter *iter)
559{
560 return 0;
561}
562
563struct blk_integrity nvme_meta_noop = {
564 .name = "NVME_META_NOOP",
565 .generate_fn = nvme_noop_generate,
566 .verify_fn = nvme_noop_verify,
567};
568
569static void nvme_init_integrity(struct nvme_ns *ns)
570{
571 struct blk_integrity integrity;
572
573 switch (ns->pi_type) {
574 case NVME_NS_DPS_PI_TYPE3:
575 integrity = t10_pi_type3_crc;
576 break;
577 case NVME_NS_DPS_PI_TYPE1:
578 case NVME_NS_DPS_PI_TYPE2:
579 integrity = t10_pi_type1_crc;
580 break;
581 default:
582 integrity = nvme_meta_noop;
583 break;
584 }
585 integrity.tuple_size = ns->ms;
586 blk_integrity_register(ns->disk, &integrity);
587 blk_queue_max_integrity_segments(ns->queue, 1);
588}
589#else /* CONFIG_BLK_DEV_INTEGRITY */
590static void nvme_dif_remap(struct request *req,
591 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
592{
593}
594static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
595{
596}
597static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
598{
599}
600static void nvme_init_integrity(struct nvme_ns *ns)
601{
602}
603#endif
604
a4aea562 605static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 606 struct nvme_completion *cqe)
607{
eca18b23 608 struct nvme_iod *iod = ctx;
ac3dd5bd 609 struct request *req = iod_get_private(iod);
a4aea562 610 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
b60503ba 611 u16 status = le16_to_cpup(&cqe->status) >> 1;
ef658fc2 612 int error = 0;
b60503ba 613
edd10d33 614 if (unlikely(status)) {
a4aea562
MB		 615 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
616 && (jiffies - req->start_time) < req->timeout) {
c9d3bf88
KB		 617 unsigned long flags;
618
a4aea562 619 blk_mq_requeue_request(req);
c9d3bf88
KB		 620 spin_lock_irqsave(req->q->queue_lock, flags);
621 if (!blk_queue_stopped(req->q))
622 blk_mq_kick_requeue_list(req->q);
623 spin_unlock_irqrestore(req->q->queue_lock, flags);
edd10d33
KB		 624 return;
625 }
f4829a9b 626
d29ec824 627 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
17188bb4 628 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
1951feae
CH		 629 error = -EINTR;
630 else
631 error = status;
d29ec824 632 } else {
1951feae 633 error = nvme_error_status(status);
d29ec824 634 }
f4829a9b
CH		 635 }
636
a0a931d6
KB		 637 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
638 u32 result = le32_to_cpup(&cqe->result);
639 req->special = (void *)(uintptr_t)result;
640 }
a4aea562
MB		 641
642 if (cmd_rq->aborted)
e75ec752 643 dev_warn(nvmeq->dev->dev,
a4aea562 644 "completing aborted command with status:%04x\n",
1951feae 645 error);
a4aea562 646
e1e5e564 647 if (iod->nents) {
e75ec752 648 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
a4aea562 649 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
e1e5e564
KB		 650 if (blk_integrity_rq(req)) {
651 if (!rq_data_dir(req))
652 nvme_dif_remap(req, nvme_dif_complete);
e75ec752 653 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
e1e5e564
KB		 654 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
655 }
656 }
edd10d33 657 nvme_free_iod(nvmeq->dev, iod);
3291fa57 658
1951feae 659 blk_mq_complete_request(req, error);
b60503ba
MW		 660}
661
184d2944 662/* length is in bytes. gfp flags indicates whether we may sleep. */
d29ec824
CH		 663static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
664 int total_len, gfp_t gfp)
ff22b54f 665{
99802a7a 666 struct dma_pool *pool;
eca18b23
MW		 667 int length = total_len;
668 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 669 int dma_len = sg_dma_len(sg);
670 u64 dma_addr = sg_dma_address(sg);
f137e0f1
MI		 671 u32 page_size = dev->page_size;
672 int offset = dma_addr & (page_size - 1);
e025344c 673 __le64 *prp_list;
eca18b23 674 __le64 **list = iod_list(iod);
e025344c 675 dma_addr_t prp_dma;
eca18b23 676 int nprps, i;
ff22b54f 677
1d090624 678 length -= (page_size - offset);
ff22b54f 679 if (length <= 0)
eca18b23 680 return total_len;
ff22b54f 681
1d090624 682 dma_len -= (page_size - offset);
ff22b54f 683 if (dma_len) {
1d090624 684 dma_addr += (page_size - offset);
ff22b54f
MW		 685 } else {
686 sg = sg_next(sg);
687 dma_addr = sg_dma_address(sg);
688 dma_len = sg_dma_len(sg);
689 }
690
1d090624 691 if (length <= page_size) {
edd10d33 692 iod->first_dma = dma_addr;
eca18b23 693 return total_len;
e025344c
SMM		 694 }
695
1d090624 696 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 697 if (nprps <= (256 / 8)) {
698 pool = dev->prp_small_pool;
eca18b23 699 iod->npages = 0;
99802a7a
MW		 700 } else {
701 pool = dev->prp_page_pool;
eca18b23 702 iod->npages = 1;
99802a7a
MW		 703 }
704
b77954cb
MW		 705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
706 if (!prp_list) {
edd10d33 707 iod->first_dma = dma_addr;
eca18b23 708 iod->npages = -1;
1d090624 709 return (total_len - length) + page_size;
b77954cb 710 }
eca18b23
MW		 711 list[0] = prp_list;
712 iod->first_dma = prp_dma;
e025344c
SMM		 713 i = 0;
714 for (;;) {
1d090624 715 if (i == page_size >> 3) {
e025344c 716 __le64 *old_prp_list = prp_list;
b77954cb 717 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 718 if (!prp_list)
719 return total_len - length;
720 list[iod->npages++] = prp_list;
7523d834
MW		 721 prp_list[0] = old_prp_list[i - 1];
722 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
723 i = 1;
e025344c
SMM		 724 }
725 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 726 dma_len -= page_size;
727 dma_addr += page_size;
728 length -= page_size;
e025344c
SMM		 729 if (length <= 0)
730 break;
731 if (dma_len > 0)
732 continue;
733 BUG_ON(dma_len < 0);
734 sg = sg_next(sg);
735 dma_addr = sg_dma_address(sg);
736 dma_len = sg_dma_len(sg);
ff22b54f
MW		 737 }
738
eca18b23 739 return total_len;
ff22b54f
MW		 740}
741
d29ec824
CH		 742static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
743 struct nvme_iod *iod)
744{
498c4394 745 struct nvme_command cmnd;
d29ec824 746
498c4394
JD		 747 memcpy(&cmnd, req->cmd, sizeof(cmnd));
748 cmnd.rw.command_id = req->tag;
d29ec824 749 if (req->nr_phys_segments) {
498c4394
JD		 750 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
751 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
d29ec824
CH		 752 }
753
498c4394 754 __nvme_submit_cmd(nvmeq, &cmnd);
d29ec824
CH		 755}
756
a4aea562
MB		 757/*
758 * We reuse the small pool to allocate the 16-byte range here as it is not
759 * worth having a special pool for these or additional cases to handle freeing
760 * the iod.
761 */
762static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
763 struct request *req, struct nvme_iod *iod)
0e5e4f0e 764{
edd10d33
KB		 765 struct nvme_dsm_range *range =
766 (struct nvme_dsm_range *)iod_list(iod)[0];
498c4394 767 struct nvme_command cmnd;
0e5e4f0e 768
0e5e4f0e 769 range->cattr = cpu_to_le32(0);
a4aea562
MB		 770 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
771 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e 772
498c4394
JD		 773 memset(&cmnd, 0, sizeof(cmnd));
774 cmnd.dsm.opcode = nvme_cmd_dsm;
775 cmnd.dsm.command_id = req->tag;
776 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
777 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
778 cmnd.dsm.nr = 0;
779 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
0e5e4f0e 780
498c4394 781 __nvme_submit_cmd(nvmeq, &cmnd);
0e5e4f0e
KB		 782}
783
a4aea562 784static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 785 int cmdid)
786{
498c4394 787 struct nvme_command cmnd;
00df5cb4 788
498c4394
JD		 789 memset(&cmnd, 0, sizeof(cmnd));
790 cmnd.common.opcode = nvme_cmd_flush;
791 cmnd.common.command_id = cmdid;
792 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
00df5cb4 793
498c4394 794 __nvme_submit_cmd(nvmeq, &cmnd);
00df5cb4
MW		 795}
796
a4aea562
MB		 797static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
798 struct nvme_ns *ns)
b60503ba 799{
ac3dd5bd 800 struct request *req = iod_get_private(iod);
498c4394 801 struct nvme_command cmnd;
a4aea562
MB		 802 u16 control = 0;
803 u32 dsmgmt = 0;
00df5cb4 804
a4aea562 805 if (req->cmd_flags & REQ_FUA)
b60503ba 806 control |= NVME_RW_FUA;
a4aea562 807 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 808 control |= NVME_RW_LR;
809
a4aea562 810 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 811 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
812
498c4394
JD		 813 memset(&cmnd, 0, sizeof(cmnd));
814 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
815 cmnd.rw.command_id = req->tag;
816 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
817 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
818 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
819 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
820 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
b60503ba 821
e19b127f 822 if (ns->ms) {
e1e5e564
KB		 823 switch (ns->pi_type) {
824 case NVME_NS_DPS_PI_TYPE3:
825 control |= NVME_RW_PRINFO_PRCHK_GUARD;
826 break;
827 case NVME_NS_DPS_PI_TYPE1:
828 case NVME_NS_DPS_PI_TYPE2:
829 control |= NVME_RW_PRINFO_PRCHK_GUARD |
830 NVME_RW_PRINFO_PRCHK_REF;
498c4394 831 cmnd.rw.reftag = cpu_to_le32(
e1e5e564
KB		 832 nvme_block_nr(ns, blk_rq_pos(req)));
833 break;
834 }
e19b127f
AP		 835 if (blk_integrity_rq(req))
836 cmnd.rw.metadata =
837 cpu_to_le64(sg_dma_address(iod->meta_sg));
838 else
839 control |= NVME_RW_PRINFO_PRACT;
840 }
e1e5e564 841
498c4394
JD		 842 cmnd.rw.control = cpu_to_le16(control);
843 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 844
498c4394 845 __nvme_submit_cmd(nvmeq, &cmnd);
b60503ba 846
1974b1ae 847 return 0;
edd10d33
KB		 848}
849
d29ec824
CH		 850/*
851 * NOTE: ns is NULL when called on the admin queue.
852 */
a4aea562
MB		 853static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
854 const struct blk_mq_queue_data *bd)
edd10d33 855{
a4aea562
MB		 856 struct nvme_ns *ns = hctx->queue->queuedata;
857 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 858 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 859 struct request *req = bd->rq;
860 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 861 struct nvme_iod *iod;
a4aea562 862 enum dma_data_direction dma_dir;
edd10d33 863
e1e5e564
KB		 864 /*
865 * If formated with metadata, require the block layer provide a buffer
866 * unless this namespace is formated such that the metadata can be
867 * stripped/generated by the controller with PRACT=1.
868 */
d29ec824 869 if (ns && ns->ms && !blk_integrity_rq(req)) {
71feb364
KB		 870 if (!(ns->pi_type && ns->ms == 8) &&
871 req->cmd_type != REQ_TYPE_DRV_PRIV) {
f4829a9b 872 blk_mq_complete_request(req, -EFAULT);
e1e5e564
KB		 873 return BLK_MQ_RQ_QUEUE_OK;
874 }
875 }
876
d29ec824 877 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
edd10d33 878 if (!iod)
fe54303e 879 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562 880
a4aea562 881 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 882 void *range;
883 /*
884 * We reuse the small pool to allocate the 16-byte range here
885 * as it is not worth having a special pool for these or
886 * additional cases to handle freeing the iod.
887 */
d29ec824 888 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
edd10d33 889 &iod->first_dma);
a4aea562 890 if (!range)
fe54303e 891 goto retry_cmd;
edd10d33
KB		 892 iod_list(iod)[0] = (__le64 *)range;
893 iod->npages = 0;
ac3dd5bd 894 } else if (req->nr_phys_segments) {
a4aea562
MB		 895 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
896
ac3dd5bd 897 sg_init_table(iod->sg, req->nr_phys_segments);
a4aea562 898 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 899 if (!iod->nents)
900 goto error_cmd;
a4aea562
MB		 901
902 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 903 goto retry_cmd;
a4aea562 904
fe54303e 905 if (blk_rq_bytes(req) !=
d29ec824
CH		 906 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
907 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
fe54303e
JA		 908 goto retry_cmd;
909 }
e1e5e564
KB		 910 if (blk_integrity_rq(req)) {
911 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
912 goto error_cmd;
913
914 sg_init_table(iod->meta_sg, 1);
915 if (blk_rq_map_integrity_sg(
916 req->q, req->bio, iod->meta_sg) != 1)
917 goto error_cmd;
918
919 if (rq_data_dir(req))
920 nvme_dif_remap(req, nvme_dif_prep);
921
922 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
923 goto error_cmd;
924 }
edd10d33 925 }
1974b1ae 926
9af8785a 927 nvme_set_info(cmd, iod, req_completion);
a4aea562 928 spin_lock_irq(&nvmeq->q_lock);
d29ec824
CH		 929 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
930 nvme_submit_priv(nvmeq, req, iod);
931 else if (req->cmd_flags & REQ_DISCARD)
a4aea562
MB		 932 nvme_submit_discard(nvmeq, ns, req, iod);
933 else if (req->cmd_flags & REQ_FLUSH)
934 nvme_submit_flush(nvmeq, ns, req->tag);
935 else
936 nvme_submit_iod(nvmeq, iod, ns);
937
938 nvme_process_cq(nvmeq);
939 spin_unlock_irq(&nvmeq->q_lock);
940 return BLK_MQ_RQ_QUEUE_OK;
941
fe54303e 942 error_cmd:
d29ec824 943 nvme_free_iod(dev, iod);
fe54303e
JA		 944 return BLK_MQ_RQ_QUEUE_ERROR;
945 retry_cmd:
d29ec824 946 nvme_free_iod(dev, iod);
fe54303e 947 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 948}
949
e9539f47 950static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 951{
82123460 952 u16 head, phase;
b60503ba 953
b60503ba 954 head = nvmeq->cq_head;
82123460 955 phase = nvmeq->cq_phase;
b60503ba
MW		 956
957 for (;;) {
c2f5b650
MW		 958 void *ctx;
959 nvme_completion_fn fn;
b60503ba 960 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 961 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 962 break;
963 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
964 if (++head == nvmeq->q_depth) {
965 head = 0;
82123460 966 phase = !phase;
b60503ba 967 }
a4aea562 968 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 969 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 970 }
971
972 /* If the controller ignores the cq head doorbell and continuously
973 * writes to the queue, it is theoretically possible to wrap around
974 * the queue twice and mistakenly return IRQ_NONE. Linux only
975 * requires that 0.1% of your interrupts are handled, so this isn't
976 * a big problem.
977 */
82123460 978 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 979 return 0;
b60503ba 980
b80d5ccc 981 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 982 nvmeq->cq_head = head;
82123460 983 nvmeq->cq_phase = phase;
b60503ba 984
e9539f47
MW		 985 nvmeq->cqe_seen = 1;
986 return 1;
b60503ba
MW		 987}
988
989static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 990{
991 irqreturn_t result;
992 struct nvme_queue *nvmeq = data;
993 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 994 nvme_process_cq(nvmeq);
995 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
996 nvmeq->cqe_seen = 0;
58ffacb5
MW		 997 spin_unlock(&nvmeq->q_lock);
998 return result;
999}
1000
1001static irqreturn_t nvme_irq_check(int irq, void *data)
1002{
1003 struct nvme_queue *nvmeq = data;
1004 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
1005 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
1006 return IRQ_NONE;
1007 return IRQ_WAKE_THREAD;
1008}
1009
b60503ba
MW		 1010/*
1011 * Returns 0 on success. If the result is negative, it's a Linux error code;
1012 * if the result is positive, it's an NVM Express status code
1013 */
d29ec824
CH		 1014int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1015 void *buffer, void __user *ubuffer, unsigned bufflen,
1016 u32 *result, unsigned timeout)
b60503ba 1017{
d29ec824
CH		 1018 bool write = cmd->common.opcode & 1;
1019 struct bio *bio = NULL;
f705f837 1020 struct request *req;
d29ec824 1021 int ret;
b60503ba 1022
d29ec824 1023 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
f705f837
CH		 1024 if (IS_ERR(req))
1025 return PTR_ERR(req);
b60503ba 1026
d29ec824 1027 req->cmd_type = REQ_TYPE_DRV_PRIV;
e112af0d 1028 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d29ec824
CH		 1029 req->__data_len = 0;
1030 req->__sector = (sector_t) -1;
1031 req->bio = req->biotail = NULL;
b60503ba 1032
f4ff414a 1033 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
a4aea562 1034
d29ec824
CH		 1035 req->cmd = (unsigned char *)cmd;
1036 req->cmd_len = sizeof(struct nvme_command);
a0a931d6 1037 req->special = (void *)0;
b60503ba 1038
d29ec824
CH		 1039 if (buffer && bufflen) {
1040 ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
1041 if (ret)
1042 goto out;
1043 } else if (ubuffer && bufflen) {
1044 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
1045 if (ret)
1046 goto out;
1047 bio = req->bio;
1048 }
3c0cf138 1049
d29ec824
CH		 1050 blk_execute_rq(req->q, NULL, req, 0);
1051 if (bio)
1052 blk_rq_unmap_user(bio);
b60503ba 1053 if (result)
a0a931d6 1054 *result = (u32)(uintptr_t)req->special;
d29ec824
CH		 1055 ret = req->errors;
1056 out:
f705f837 1057 blk_mq_free_request(req);
d29ec824 1058 return ret;
f705f837
CH		 1059}
1060
d29ec824
CH		 1061int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1062 void *buffer, unsigned bufflen)
f705f837 1063{
d29ec824 1064 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
b60503ba
MW		 1065}
1066
a4aea562
MB		 1067static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1068{
1069 struct nvme_queue *nvmeq = dev->queues[0];
1070 struct nvme_command c;
1071 struct nvme_cmd_info *cmd_info;
1072 struct request *req;
1073
1efccc9d 1074 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
9f173b33
DC		 1075 if (IS_ERR(req))
1076 return PTR_ERR(req);
a4aea562 1077
c917dfe5 1078 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562 1079 cmd_info = blk_mq_rq_to_pdu(req);
1efccc9d 1080 nvme_set_info(cmd_info, NULL, async_req_completion);
a4aea562
MB		 1081
1082 memset(&c, 0, sizeof(c));
1083 c.common.opcode = nvme_admin_async_event;
1084 c.common.command_id = req->tag;
1085
42483228 1086 blk_mq_free_request(req);
e3f879bf
SB		 1087 __nvme_submit_cmd(nvmeq, &c);
1088 return 0;
a4aea562
MB		 1089}
1090
1091static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 1092 struct nvme_command *cmd,
1093 struct async_cmd_info *cmdinfo, unsigned timeout)
1094{
a4aea562
MB		 1095 struct nvme_queue *nvmeq = dev->queues[0];
1096 struct request *req;
1097 struct nvme_cmd_info *cmd_rq;
4d115420 1098
a4aea562 1099 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 1100 if (IS_ERR(req))
1101 return PTR_ERR(req);
a4aea562
MB		 1102
1103 req->timeout = timeout;
1104 cmd_rq = blk_mq_rq_to_pdu(req);
1105 cmdinfo->req = req;
1106 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 1107 cmdinfo->status = -EINTR;
a4aea562
MB		 1108
1109 cmd->common.command_id = req->tag;
1110
e3f879bf
SB		 1111 nvme_submit_cmd(nvmeq, cmd);
1112 return 0;
4d115420
KB		 1113}
1114
b60503ba
MW		 1115static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1116{
b60503ba
MW		 1117 struct nvme_command c;
1118
1119 memset(&c, 0, sizeof(c));
1120 c.delete_queue.opcode = opcode;
1121 c.delete_queue.qid = cpu_to_le16(id);
1122
d29ec824 1123 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1124}
1125
1126static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1127 struct nvme_queue *nvmeq)
1128{
b60503ba
MW		 1129 struct nvme_command c;
1130 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1131
d29ec824
CH		 1132 /*
1133 * Note: we (ab)use the fact the the prp fields survive if no data
1134 * is attached to the request.
1135 */
b60503ba
MW		 1136 memset(&c, 0, sizeof(c));
1137 c.create_cq.opcode = nvme_admin_create_cq;
1138 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1139 c.create_cq.cqid = cpu_to_le16(qid);
1140 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1141 c.create_cq.cq_flags = cpu_to_le16(flags);
1142 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1143
d29ec824 1144 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1145}
1146
1147static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1148 struct nvme_queue *nvmeq)
1149{
b60503ba
MW		 1150 struct nvme_command c;
1151 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1152
d29ec824
CH		 1153 /*
1154 * Note: we (ab)use the fact the the prp fields survive if no data
1155 * is attached to the request.
1156 */
b60503ba
MW		 1157 memset(&c, 0, sizeof(c));
1158 c.create_sq.opcode = nvme_admin_create_sq;
1159 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1160 c.create_sq.sqid = cpu_to_le16(qid);
1161 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1162 c.create_sq.sq_flags = cpu_to_le16(flags);
1163 c.create_sq.cqid = cpu_to_le16(qid);
1164
d29ec824 1165 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
b60503ba
MW		 1166}
1167
1168static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1169{
1170 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1171}
1172
1173static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1174{
1175 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1176}
1177
d29ec824 1178int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
bc5fc7e4 1179{
e44ac588 1180 struct nvme_command c = { };
d29ec824 1181 int error;
bc5fc7e4 1182
e44ac588
AM		 1183 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1184 c.identify.opcode = nvme_admin_identify;
1185 c.identify.cns = cpu_to_le32(1);
1186
d29ec824
CH		 1187 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1188 if (!*id)
1189 return -ENOMEM;
bc5fc7e4 1190
d29ec824
CH		 1191 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1192 sizeof(struct nvme_id_ctrl));
1193 if (error)
1194 kfree(*id);
1195 return error;
1196}
1197
1198int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1199 struct nvme_id_ns **id)
1200{
e44ac588 1201 struct nvme_command c = { };
d29ec824 1202 int error;
bc5fc7e4 1203
e44ac588
AM		 1204 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1205 c.identify.opcode = nvme_admin_identify,
1206 c.identify.nsid = cpu_to_le32(nsid),
1207
d29ec824
CH		 1208 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1209 if (!*id)
1210 return -ENOMEM;
1211
1212 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1213 sizeof(struct nvme_id_ns));
1214 if (error)
1215 kfree(*id);
1216 return error;
bc5fc7e4
MW		 1217}
1218
5d0f6131 1219int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1220 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1221{
1222 struct nvme_command c;
1223
1224 memset(&c, 0, sizeof(c));
1225 c.features.opcode = nvme_admin_get_features;
a42cecce 1226 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1227 c.features.prp1 = cpu_to_le64(dma_addr);
1228 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1229
d29ec824
CH		 1230 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1231 result, 0);
df348139
MW		 1232}
1233
5d0f6131
VV		 1234int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1235 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1236{
1237 struct nvme_command c;
1238
1239 memset(&c, 0, sizeof(c));
1240 c.features.opcode = nvme_admin_set_features;
1241 c.features.prp1 = cpu_to_le64(dma_addr);
1242 c.features.fid = cpu_to_le32(fid);
1243 c.features.dword11 = cpu_to_le32(dword11);
1244
d29ec824
CH		 1245 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1246 result, 0);
1247}
1248
1249int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1250{
e44ac588
AM		 1251 struct nvme_command c = { };
1252 int error;
1253
1254 c.common.opcode = nvme_admin_get_log_page,
1255 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1256 c.common.cdw10[0] = cpu_to_le32(
d29ec824
CH		 1257 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1258 NVME_LOG_SMART),
d29ec824
CH		 1259
1260 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1261 if (!*log)
1262 return -ENOMEM;
1263
1264 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1265 sizeof(struct nvme_smart_log));
1266 if (error)
1267 kfree(*log);
1268 return error;
bc5fc7e4
MW		 1269}
1270
c30341dc 1271/**
a4aea562 1272 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1273 *
1274 * Schedule controller reset if the command was already aborted once before and
1275 * still hasn't been returned to the driver, or if this is the admin queue.
1276 */
a4aea562 1277static void nvme_abort_req(struct request *req)
c30341dc 1278{
a4aea562
MB		 1279 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1280 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1281 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1282 struct request *abort_req;
1283 struct nvme_cmd_info *abort_cmd;
1284 struct nvme_command cmd;
c30341dc 1285
a4aea562 1286 if (!nvmeq->qid || cmd_rq->aborted) {
90667892
CH		 1287 spin_lock(&dev_list_lock);
1288 if (!__nvme_reset(dev)) {
1289 dev_warn(dev->dev,
1290 "I/O %d QID %d timeout, reset controller\n",
1291 req->tag, nvmeq->qid);
1292 }
1293 spin_unlock(&dev_list_lock);
c30341dc
KB		 1294 return;
1295 }
1296
1297 if (!dev->abort_limit)
1298 return;
1299
a4aea562
MB		 1300 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1301 false);
9f173b33 1302 if (IS_ERR(abort_req))
c30341dc
KB		 1303 return;
1304
a4aea562
MB		 1305 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1306 nvme_set_info(abort_cmd, abort_req, abort_completion);
1307
c30341dc
KB		 1308 memset(&cmd, 0, sizeof(cmd));
1309 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1310 cmd.abort.cid = req->tag;
c30341dc 1311 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1312 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1313
1314 --dev->abort_limit;
a4aea562 1315 cmd_rq->aborted = 1;
c30341dc 1316
a4aea562 1317 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1318 nvmeq->qid);
e3f879bf 1319 nvme_submit_cmd(dev->queues[0], &cmd);
c30341dc
KB		 1320}
1321
42483228 1322static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
a09115b2 1323{
a4aea562
MB		 1324 struct nvme_queue *nvmeq = data;
1325 void *ctx;
1326 nvme_completion_fn fn;
1327 struct nvme_cmd_info *cmd;
cef6a948
KB		 1328 struct nvme_completion cqe;
1329
1330 if (!blk_mq_request_started(req))
1331 return;
a09115b2 1332
a4aea562 1333 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1334
a4aea562
MB		 1335 if (cmd->ctx == CMD_CTX_CANCELLED)
1336 return;
1337
cef6a948
KB		 1338 if (blk_queue_dying(req->q))
1339 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1340 else
1341 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1342
1343
a4aea562
MB		 1344 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1345 req->tag, nvmeq->qid);
1346 ctx = cancel_cmd_info(cmd, &fn);
1347 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1348}
1349
a4aea562 1350static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1351{
a4aea562
MB		 1352 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1353 struct nvme_queue *nvmeq = cmd->nvmeq;
1354
1355 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1356 nvmeq->qid);
7a509a6b 1357 spin_lock_irq(&nvmeq->q_lock);
07836e65 1358 nvme_abort_req(req);
7a509a6b 1359 spin_unlock_irq(&nvmeq->q_lock);
a4aea562 1360
07836e65
KB		 1361 /*
1362 * The aborted req will be completed on receiving the abort req.
1363 * We enable the timer again. If hit twice, it'll cause a device reset,
1364 * as the device then is in a faulty state.
1365 */
1366 return BLK_EH_RESET_TIMER;
a4aea562 1367}
22404274 1368
a4aea562
MB		 1369static void nvme_free_queue(struct nvme_queue *nvmeq)
1370{
9e866774
MW		 1371 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1372 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
8ffaadf7
JD		 1373 if (nvmeq->sq_cmds)
1374 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
9e866774
MW		 1375 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1376 kfree(nvmeq);
1377}
1378
a1a5ef99 1379static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1380{
1381 int i;
1382
a1a5ef99 1383 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1384 struct nvme_queue *nvmeq = dev->queues[i];
22404274 1385 dev->queue_count--;
a4aea562 1386 dev->queues[i] = NULL;
f435c282 1387 nvme_free_queue(nvmeq);
121c7ad4 1388 }
22404274
KB		 1389}
1390
4d115420
KB		 1391/**
1392 * nvme_suspend_queue - put queue into suspended state
1393 * @nvmeq - queue to suspend
4d115420
KB		 1394 */
1395static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1396{
2b25d981 1397 int vector;
b60503ba 1398
a09115b2 1399 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1400 if (nvmeq->cq_vector == -1) {
1401 spin_unlock_irq(&nvmeq->q_lock);
1402 return 1;
1403 }
1404 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1405 nvmeq->dev->online_queues--;
2b25d981 1406 nvmeq->cq_vector = -1;
a09115b2
MW		 1407 spin_unlock_irq(&nvmeq->q_lock);
1408
6df3dbc8
KB		 1409 if (!nvmeq->qid && nvmeq->dev->admin_q)
1410 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1411
aba2080f
MW		 1412 irq_set_affinity_hint(vector, NULL);
1413 free_irq(vector, nvmeq);
b60503ba 1414
4d115420
KB		 1415 return 0;
1416}
b60503ba 1417
4d115420
KB		 1418static void nvme_clear_queue(struct nvme_queue *nvmeq)
1419{
22404274 1420 spin_lock_irq(&nvmeq->q_lock);
42483228
KB		 1421 if (nvmeq->tags && *nvmeq->tags)
1422 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
22404274 1423 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1424}
1425
4d115420
KB		 1426static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1427{
a4aea562 1428 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1429
1430 if (!nvmeq)
1431 return;
1432 if (nvme_suspend_queue(nvmeq))
1433 return;
1434
0e53d180
KB		 1435 /* Don't tell the adapter to delete the admin queue.
1436 * Don't tell a removed adapter to delete IO queues. */
1437 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1438 adapter_delete_sq(dev, qid);
1439 adapter_delete_cq(dev, qid);
1440 }
07836e65
KB		 1441
1442 spin_lock_irq(&nvmeq->q_lock);
1443 nvme_process_cq(nvmeq);
1444 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1445}
1446
8ffaadf7
JD		 1447static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1448 int entry_size)
1449{
1450 int q_depth = dev->q_depth;
1451 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1452
1453 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99
JD		 1454 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1455 mem_per_q = round_down(mem_per_q, dev->page_size);
1456 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1457
1458 /*
1459 * Ensure the reduced q_depth is above some threshold where it
1460 * would be better to map queues in system memory with the
1461 * original depth
1462 */
1463 if (q_depth < 64)
1464 return -ENOMEM;
1465 }
1466
1467 return q_depth;
1468}
1469
1470static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1471 int qid, int depth)
1472{
1473 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1474 unsigned offset = (qid - 1) *
1475 roundup(SQ_SIZE(depth), dev->page_size);
1476 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1477 nvmeq->sq_cmds_io = dev->cmb + offset;
1478 } else {
1479 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1480 &nvmeq->sq_dma_addr, GFP_KERNEL);
1481 if (!nvmeq->sq_cmds)
1482 return -ENOMEM;
1483 }
1484
1485 return 0;
1486}
1487
b60503ba 1488static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1489 int depth)
b60503ba 1490{
a4aea562 1491 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1492 if (!nvmeq)
1493 return NULL;
1494
e75ec752 1495 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1496 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1497 if (!nvmeq->cqes)
1498 goto free_nvmeq;
b60503ba 1499
8ffaadf7 1500 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1501 goto free_cqdma;
1502
e75ec752 1503 nvmeq->q_dmadev = dev->dev;
091b6092 1504 nvmeq->dev = dev;
3193f07b
MW		 1505 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1506 dev->instance, qid);
b60503ba
MW		 1507 spin_lock_init(&nvmeq->q_lock);
1508 nvmeq->cq_head = 0;
82123460 1509 nvmeq->cq_phase = 1;
b80d5ccc 1510 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1511 nvmeq->q_depth = depth;
c30341dc 1512 nvmeq->qid = qid;
758dd7fd 1513 nvmeq->cq_vector = -1;
a4aea562 1514 dev->queues[qid] = nvmeq;
b60503ba 1515
36a7e993
JD		 1516 /* make sure queue descriptor is set before queue count, for kthread */
1517 mb();
1518 dev->queue_count++;
1519
b60503ba
MW		 1520 return nvmeq;
1521
1522 free_cqdma:
e75ec752 1523 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1524 nvmeq->cq_dma_addr);
1525 free_nvmeq:
1526 kfree(nvmeq);
1527 return NULL;
1528}
1529
3001082c
MW		 1530static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1531 const char *name)
1532{
58ffacb5
MW		 1533 if (use_threaded_interrupts)
1534 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1535 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1536 name, nvmeq);
3001082c 1537 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1538 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1539}
1540
22404274 1541static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1542{
22404274 1543 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1544
7be50e93 1545 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1546 nvmeq->sq_tail = 0;
1547 nvmeq->cq_head = 0;
1548 nvmeq->cq_phase = 1;
b80d5ccc 1549 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1550 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1551 dev->online_queues++;
7be50e93 1552 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1553}
1554
1555static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1556{
1557 struct nvme_dev *dev = nvmeq->dev;
1558 int result;
3f85d50b 1559
2b25d981 1560 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1561 result = adapter_alloc_cq(dev, qid, nvmeq);
1562 if (result < 0)
22404274 1563 return result;
b60503ba
MW		 1564
1565 result = adapter_alloc_sq(dev, qid, nvmeq);
1566 if (result < 0)
1567 goto release_cq;
1568
3193f07b 1569 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1570 if (result < 0)
1571 goto release_sq;
1572
22404274 1573 nvme_init_queue(nvmeq, qid);
22404274 1574 return result;
b60503ba
MW		 1575
1576 release_sq:
1577 adapter_delete_sq(dev, qid);
1578 release_cq:
1579 adapter_delete_cq(dev, qid);
22404274 1580 return result;
b60503ba
MW		 1581}
1582
ba47e386
MW		 1583static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1584{
1585 unsigned long timeout;
1586 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1587
1588 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1589
1590 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1591 msleep(100);
1592 if (fatal_signal_pending(current))
1593 return -EINTR;
1594 if (time_after(jiffies, timeout)) {
e75ec752 1595 dev_err(dev->dev,
27e8166c
MW		 1596 "Device not ready; aborting %s\n", enabled ?
1597 "initialisation" : "reset");
ba47e386
MW		 1598 return -ENODEV;
1599 }
1600 }
1601
1602 return 0;
1603}
1604
1605/*
1606 * If the device has been passed off to us in an enabled state, just clear
1607 * the enabled bit. The spec says we should set the 'shutdown notification
1608 * bits', but doing so may cause the device to complete commands to the
1609 * admin queue ... and we don't know what memory that might be pointing at!
1610 */
1611static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1612{
01079522
DM		 1613 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1614 dev->ctrl_config &= ~NVME_CC_ENABLE;
1615 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1616
ba47e386
MW		 1617 return nvme_wait_ready(dev, cap, false);
1618}
1619
1620static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1621{
01079522
DM		 1622 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1623 dev->ctrl_config |= NVME_CC_ENABLE;
1624 writel(dev->ctrl_config, &dev->bar->cc);
1625
ba47e386
MW		 1626 return nvme_wait_ready(dev, cap, true);
1627}
1628
1894d8f1
KB		 1629static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1630{
1631 unsigned long timeout;
1894d8f1 1632
01079522
DM		 1633 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1634 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1635
1636 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1637
2484f407 1638 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1639 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1640 NVME_CSTS_SHST_CMPLT) {
1641 msleep(100);
1642 if (fatal_signal_pending(current))
1643 return -EINTR;
1644 if (time_after(jiffies, timeout)) {
e75ec752 1645 dev_err(dev->dev,
1894d8f1
KB		 1646 "Device shutdown incomplete; abort shutdown\n");
1647 return -ENODEV;
1648 }
1649 }
1650
1651 return 0;
1652}
1653
a4aea562 1654static struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1655 .queue_rq = nvme_queue_rq,
a4aea562
MB		 1656 .map_queue = blk_mq_map_queue,
1657 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1658 .exit_hctx = nvme_admin_exit_hctx,
a4aea562
MB		 1659 .init_request = nvme_admin_init_request,
1660 .timeout = nvme_timeout,
1661};
1662
1663static struct blk_mq_ops nvme_mq_ops = {
1664 .queue_rq = nvme_queue_rq,
1665 .map_queue = blk_mq_map_queue,
1666 .init_hctx = nvme_init_hctx,
1667 .init_request = nvme_init_request,
1668 .timeout = nvme_timeout,
1669};
1670
ea191d2f
KB		 1671static void nvme_dev_remove_admin(struct nvme_dev *dev)
1672{
1673 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1674 blk_cleanup_queue(dev->admin_q);
1675 blk_mq_free_tag_set(&dev->admin_tagset);
1676 }
1677}
1678
a4aea562
MB		 1679static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1680{
1681 if (!dev->admin_q) {
1682 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1683 dev->admin_tagset.nr_hw_queues = 1;
1684 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1efccc9d 1685 dev->admin_tagset.reserved_tags = 1;
a4aea562 1686 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1687 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
ac3dd5bd 1688 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
a4aea562
MB		 1689 dev->admin_tagset.driver_data = dev;
1690
1691 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1692 return -ENOMEM;
1693
1694 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1695 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1696 blk_mq_free_tag_set(&dev->admin_tagset);
1697 return -ENOMEM;
1698 }
ea191d2f
KB		 1699 if (!blk_get_queue(dev->admin_q)) {
1700 nvme_dev_remove_admin(dev);
4af0e21c 1701 dev->admin_q = NULL;
ea191d2f
KB		 1702 return -ENODEV;
1703 }
0fb59cbc
KB		 1704 } else
1705 blk_mq_unfreeze_queue(dev->admin_q);
a4aea562
MB		 1706
1707 return 0;
1708}
1709
8d85fce7 1710static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1711{
ba47e386 1712 int result;
b60503ba 1713 u32 aqa;
ba47e386 1714 u64 cap = readq(&dev->bar->cap);
b60503ba 1715 struct nvme_queue *nvmeq;
1d090624
KB		 1716 unsigned page_shift = PAGE_SHIFT;
1717 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1718 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1719
1720 if (page_shift < dev_page_min) {
e75ec752 1721 dev_err(dev->dev,
1d090624
KB		 1722 "Minimum device page size (%u) too large for "
1723 "host (%u)\n", 1 << dev_page_min,
1724 1 << page_shift);
1725 return -ENODEV;
1726 }
1727 if (page_shift > dev_page_max) {
e75ec752 1728 dev_info(dev->dev,
1d090624
KB		 1729 "Device maximum page size (%u) smaller than "
1730 "host (%u); enabling work-around\n",
1731 1 << dev_page_max, 1 << page_shift);
1732 page_shift = dev_page_max;
1733 }
b60503ba 1734
dfbac8c7
KB		 1735 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1736 NVME_CAP_NSSRC(cap) : 0;
1737
1738 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1739 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1740
ba47e386
MW		 1741 result = nvme_disable_ctrl(dev, cap);
1742 if (result < 0)
1743 return result;
b60503ba 1744
a4aea562 1745 nvmeq = dev->queues[0];
cd638946 1746 if (!nvmeq) {
2b25d981 1747 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1748 if (!nvmeq)
1749 return -ENOMEM;
cd638946 1750 }
b60503ba
MW		 1751
1752 aqa = nvmeq->q_depth - 1;
1753 aqa |= aqa << 16;
1754
1d090624
KB		 1755 dev->page_size = 1 << page_shift;
1756
01079522 1757 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1758 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1759 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1760 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1761
1762 writel(aqa, &dev->bar->aqa);
1763 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1764 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1765
ba47e386 1766 result = nvme_enable_ctrl(dev, cap);
025c557a 1767 if (result)
a4aea562
MB		 1768 goto free_nvmeq;
1769
2b25d981 1770 nvmeq->cq_vector = 0;
3193f07b 1771 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
758dd7fd
JD		 1772 if (result) {
1773 nvmeq->cq_vector = -1;
0fb59cbc 1774 goto free_nvmeq;
758dd7fd 1775 }
025c557a 1776
b60503ba 1777 return result;
a4aea562 1778
a4aea562
MB		 1779 free_nvmeq:
1780 nvme_free_queues(dev, 0);
1781 return result;
b60503ba
MW		 1782}
1783
a53295b6
MW		 1784static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1785{
1786 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1787 struct nvme_user_io io;
1788 struct nvme_command c;
d29ec824 1789 unsigned length, meta_len;
a67a9513 1790 int status, write;
a67a9513
KB		 1791 dma_addr_t meta_dma = 0;
1792 void *meta = NULL;
fec558b5 1793 void __user *metadata;
a53295b6
MW		 1794
1795 if (copy_from_user(&io, uio, sizeof(io)))
1796 return -EFAULT;
6c7d4945
MW		 1797
1798 switch (io.opcode) {
1799 case nvme_cmd_write:
1800 case nvme_cmd_read:
6bbf1acd 1801 case nvme_cmd_compare:
6413214c 1802 break;
6c7d4945 1803 default:
6bbf1acd 1804 return -EINVAL;
6c7d4945
MW		 1805 }
1806
d29ec824
CH		 1807 length = (io.nblocks + 1) << ns->lba_shift;
1808 meta_len = (io.nblocks + 1) * ns->ms;
3d42e67f 1809 metadata = (void __user *)(uintptr_t)io.metadata;
d29ec824 1810 write = io.opcode & 1;
a53295b6 1811
71feb364
KB		 1812 if (ns->ext) {
1813 length += meta_len;
1814 meta_len = 0;
a67a9513
KB		 1815 }
1816 if (meta_len) {
d29ec824
CH		 1817 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1818 return -EINVAL;
1819
e75ec752 1820 meta = dma_alloc_coherent(dev->dev, meta_len,
a67a9513 1821 &meta_dma, GFP_KERNEL);
fec558b5 1822
a67a9513
KB		 1823 if (!meta) {
1824 status = -ENOMEM;
1825 goto unmap;
1826 }
1827 if (write) {
fec558b5 1828 if (copy_from_user(meta, metadata, meta_len)) {
a67a9513
KB		 1829 status = -EFAULT;
1830 goto unmap;
1831 }
1832 }
1833 }
1834
a53295b6
MW		 1835 memset(&c, 0, sizeof(c));
1836 c.rw.opcode = io.opcode;
1837 c.rw.flags = io.flags;
6c7d4945 1838 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1839 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1840 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1841 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1842 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1843 c.rw.reftag = cpu_to_le32(io.reftag);
1844 c.rw.apptag = cpu_to_le16(io.apptag);
1845 c.rw.appmask = cpu_to_le16(io.appmask);
a67a9513 1846 c.rw.metadata = cpu_to_le64(meta_dma);
d29ec824
CH		 1847
1848 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
3d42e67f 1849 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
f410c680 1850 unmap:
a67a9513
KB		 1851 if (meta) {
1852 if (status == NVME_SC_SUCCESS && !write) {
fec558b5 1853 if (copy_to_user(metadata, meta, meta_len))
a67a9513
KB		 1854 status = -EFAULT;
1855 }
e75ec752 1856 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
f410c680 1857 }
a53295b6
MW		 1858 return status;
1859}
1860
a4aea562
MB		 1861static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1862 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1863{
7963e521 1864 struct nvme_passthru_cmd cmd;
6ee44cdc 1865 struct nvme_command c;
d29ec824
CH		 1866 unsigned timeout = 0;
1867 int status;
6ee44cdc 1868
6bbf1acd
MW		 1869 if (!capable(CAP_SYS_ADMIN))
1870 return -EACCES;
1871 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1872 return -EFAULT;
6ee44cdc
MW		 1873
1874 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1875 c.common.opcode = cmd.opcode;
1876 c.common.flags = cmd.flags;
1877 c.common.nsid = cpu_to_le32(cmd.nsid);
1878 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1879 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1880 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1881 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1882 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1883 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1884 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1885 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1886
d29ec824
CH		 1887 if (cmd.timeout_ms)
1888 timeout = msecs_to_jiffies(cmd.timeout_ms);
eca18b23 1889
f705f837 1890 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
3d42e67f 1891 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
d29ec824
CH		 1892 &cmd.result, timeout);
1893 if (status >= 0) {
1894 if (put_user(cmd.result, &ucmd->result))
1895 return -EFAULT;
6bbf1acd 1896 }
f4f117f6 1897
6ee44cdc
MW		 1898 return status;
1899}
1900
81f03fed
JD		 1901static int nvme_subsys_reset(struct nvme_dev *dev)
1902{
1903 if (!dev->subsystem)
1904 return -ENOTTY;
1905
1906 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1907 return 0;
1908}
1909
b60503ba
MW		 1910static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1911 unsigned long arg)
1912{
1913 struct nvme_ns *ns = bdev->bd_disk->private_data;
1914
1915 switch (cmd) {
6bbf1acd 1916 case NVME_IOCTL_ID:
c3bfe717 1917 force_successful_syscall_return();
6bbf1acd
MW		 1918 return ns->ns_id;
1919 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1920 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1921 case NVME_IOCTL_IO_CMD:
a4aea562 1922 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1923 case NVME_IOCTL_SUBMIT_IO:
1924 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1925 case SG_GET_VERSION_NUM:
1926 return nvme_sg_get_version_num((void __user *)arg);
1927 case SG_IO:
1928 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1929 default:
1930 return -ENOTTY;
1931 }
1932}
1933
320a3827
KB		 1934#ifdef CONFIG_COMPAT
1935static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1936 unsigned int cmd, unsigned long arg)
1937{
320a3827
KB		 1938 switch (cmd) {
1939 case SG_IO:
e179729a 1940 return -ENOIOCTLCMD;
320a3827
KB		 1941 }
1942 return nvme_ioctl(bdev, mode, cmd, arg);
1943}
1944#else
1945#define nvme_compat_ioctl NULL
1946#endif
1947
5105aa55 1948static void nvme_free_dev(struct kref *kref);
188c3568
KB		 1949static void nvme_free_ns(struct kref *kref)
1950{
1951 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1952
1953 spin_lock(&dev_list_lock);
1954 ns->disk->private_data = NULL;
1955 spin_unlock(&dev_list_lock);
1956
5105aa55 1957 kref_put(&ns->dev->kref, nvme_free_dev);
188c3568
KB		 1958 put_disk(ns->disk);
1959 kfree(ns);
1960}
1961
9ac27090
KB		 1962static int nvme_open(struct block_device *bdev, fmode_t mode)
1963{
9e60352c
KB		 1964 int ret = 0;
1965 struct nvme_ns *ns;
9ac27090 1966
9e60352c
KB		 1967 spin_lock(&dev_list_lock);
1968 ns = bdev->bd_disk->private_data;
1969 if (!ns)
1970 ret = -ENXIO;
188c3568 1971 else if (!kref_get_unless_zero(&ns->kref))
9e60352c
KB		 1972 ret = -ENXIO;
1973 spin_unlock(&dev_list_lock);
1974
1975 return ret;
9ac27090
KB		 1976}
1977
9ac27090
KB		 1978static void nvme_release(struct gendisk *disk, fmode_t mode)
1979{
1980 struct nvme_ns *ns = disk->private_data;
188c3568 1981 kref_put(&ns->kref, nvme_free_ns);
9ac27090
KB		 1982}
1983
4cc09e2d
KB		 1984static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1985{
1986 /* some standard values */
1987 geo->heads = 1 << 6;
1988 geo->sectors = 1 << 5;
1989 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1990 return 0;
1991}
1992
e1e5e564
KB		 1993static void nvme_config_discard(struct nvme_ns *ns)
1994{
1995 u32 logical_block_size = queue_logical_block_size(ns->queue);
1996 ns->queue->limits.discard_zeroes_data = 0;
1997 ns->queue->limits.discard_alignment = logical_block_size;
1998 ns->queue->limits.discard_granularity = logical_block_size;
2bb4cd5c 1999 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
e1e5e564
KB		 2000 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
2001}
2002
1b9dbf7f
KB		 2003static int nvme_revalidate_disk(struct gendisk *disk)
2004{
2005 struct nvme_ns *ns = disk->private_data;
2006 struct nvme_dev *dev = ns->dev;
2007 struct nvme_id_ns *id;
a67a9513
KB		 2008 u8 lbaf, pi_type;
2009 u16 old_ms;
e1e5e564 2010 unsigned short bs;
1b9dbf7f 2011
d29ec824 2012 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
a5768aa8
KB		 2013 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2014 dev->instance, ns->ns_id);
2015 return -ENODEV;
1b9dbf7f 2016 }
a5768aa8
KB		 2017 if (id->ncap == 0) {
2018 kfree(id);
2019 return -ENODEV;
e1e5e564 2020 }
1b9dbf7f 2021
e1e5e564
KB		 2022 old_ms = ns->ms;
2023 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
1b9dbf7f 2024 ns->lba_shift = id->lbaf[lbaf].ds;
e1e5e564 2025 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
a67a9513 2026 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
e1e5e564
KB		 2027
2028 /*
2029 * If identify namespace failed, use default 512 byte block size so
2030 * block layer can use before failing read/write for 0 capacity.
2031 */
2032 if (ns->lba_shift == 0)
2033 ns->lba_shift = 9;
2034 bs = 1 << ns->lba_shift;
2035
2036 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2037 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2038 id->dps & NVME_NS_DPS_PI_MASK : 0;
2039
52b68d7e
KB		 2040 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2041 ns->ms != old_ms ||
e1e5e564 2042 bs != queue_logical_block_size(disk->queue) ||
a67a9513 2043 (ns->ms && ns->ext)))
e1e5e564
KB		 2044 blk_integrity_unregister(disk);
2045
2046 ns->pi_type = pi_type;
2047 blk_queue_logical_block_size(ns->queue, bs);
2048
52b68d7e 2049 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
a67a9513 2050 !ns->ext)
e1e5e564
KB		 2051 nvme_init_integrity(ns);
2052
e19b127f 2053 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
e1e5e564
KB		 2054 set_capacity(disk, 0);
2055 else
2056 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2057
2058 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2059 nvme_config_discard(ns);
1b9dbf7f 2060
d29ec824 2061 kfree(id);
1b9dbf7f
KB		 2062 return 0;
2063}
2064
1d277a63
KB		 2065static char nvme_pr_type(enum pr_type type)
2066{
2067 switch (type) {
2068 case PR_WRITE_EXCLUSIVE:
2069 return 1;
2070 case PR_EXCLUSIVE_ACCESS:
2071 return 2;
2072 case PR_WRITE_EXCLUSIVE_REG_ONLY:
2073 return 3;
2074 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2075 return 4;
2076 case PR_WRITE_EXCLUSIVE_ALL_REGS:
2077 return 5;
2078 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2079 return 6;
2080 default:
2081 return 0;
2082 }
2083};
2084
2085static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2086 u64 key, u64 sa_key, u8 op)
2087{
2088 struct nvme_ns *ns = bdev->bd_disk->private_data;
2089 struct nvme_command c;
2090 u8 data[16] = { 0, };
2091
2092 put_unaligned_le64(key, &data[0]);
2093 put_unaligned_le64(sa_key, &data[8]);
2094
2095 memset(&c, 0, sizeof(c));
2096 c.common.opcode = op;
2097 c.common.nsid = ns->ns_id;
2098 c.common.cdw10[0] = cdw10;
2099
2100 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2101}
2102
2103static int nvme_pr_register(struct block_device *bdev, u64 old,
2104 u64 new, unsigned flags)
2105{
2106 u32 cdw10;
2107
2108 if (flags & ~PR_FL_IGNORE_KEY)
2109 return -EOPNOTSUPP;
2110
2111 cdw10 = old ? 2 : 0;
2112 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2113 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2114 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2115}
2116
2117static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2118 enum pr_type type, unsigned flags)
2119{
2120 u32 cdw10;
2121
2122 if (flags & ~PR_FL_IGNORE_KEY)
2123 return -EOPNOTSUPP;
2124
2125 cdw10 = nvme_pr_type(type) << 8;
2126 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2127 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2128}
2129
2130static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2131 enum pr_type type, bool abort)
2132{
2133 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2134 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2135}
2136
2137static int nvme_pr_clear(struct block_device *bdev, u64 key)
2138{
2139 u32 cdw10 = 1 | key ? 1 << 3 : 0;
2140 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2141}
2142
2143static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2144{
2145 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2146 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2147}
2148
2149static const struct pr_ops nvme_pr_ops = {
2150 .pr_register = nvme_pr_register,
2151 .pr_reserve = nvme_pr_reserve,
2152 .pr_release = nvme_pr_release,
2153 .pr_preempt = nvme_pr_preempt,
2154 .pr_clear = nvme_pr_clear,
2155};
2156
b60503ba
MW		 2157static const struct block_device_operations nvme_fops = {
2158 .owner = THIS_MODULE,
2159 .ioctl = nvme_ioctl,
320a3827 2160 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 2161 .open = nvme_open,
2162 .release = nvme_release,
4cc09e2d 2163 .getgeo = nvme_getgeo,
1b9dbf7f 2164 .revalidate_disk= nvme_revalidate_disk,
1d277a63 2165 .pr_ops = &nvme_pr_ops,
b60503ba
MW		 2166};
2167
1fa6aead
MW		 2168static int nvme_kthread(void *data)
2169{
d4b4ff8e 2170 struct nvme_dev *dev, *next;
1fa6aead
MW		 2171
2172 while (!kthread_should_stop()) {
564a232c 2173 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 2174 spin_lock(&dev_list_lock);
d4b4ff8e 2175 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 2176 int i;
dfbac8c7
KB		 2177 u32 csts = readl(&dev->bar->csts);
2178
2179 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2180 csts & NVME_CSTS_CFS) {
90667892
CH		 2181 if (!__nvme_reset(dev)) {
2182 dev_warn(dev->dev,
2183 "Failed status: %x, reset controller\n",
2184 readl(&dev->bar->csts));
2185 }
d4b4ff8e
KB		 2186 continue;
2187 }
1fa6aead 2188 for (i = 0; i < dev->queue_count; i++) {
a4aea562 2189 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 2190 if (!nvmeq)
2191 continue;
1fa6aead 2192 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 2193 nvme_process_cq(nvmeq);
6fccf938
KB		 2194
2195 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 2196 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 2197 break;
2198 dev->event_limit--;
2199 }
1fa6aead
MW		 2200 spin_unlock_irq(&nvmeq->q_lock);
2201 }
2202 }
2203 spin_unlock(&dev_list_lock);
acb7aa0d 2204 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 2205 }
2206 return 0;
2207}
2208
e1e5e564 2209static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
b60503ba
MW		 2210{
2211 struct nvme_ns *ns;
2212 struct gendisk *disk;
e75ec752 2213 int node = dev_to_node(dev->dev);
b60503ba 2214
a4aea562 2215 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba 2216 if (!ns)
e1e5e564
KB		 2217 return;
2218
a4aea562 2219 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 2220 if (IS_ERR(ns->queue))
b60503ba 2221 goto out_free_ns;
4eeb9215
MW		 2222 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2223 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 2224 ns->dev = dev;
2225 ns->queue->queuedata = ns;
2226
a4aea562 2227 disk = alloc_disk_node(0, node);
b60503ba
MW		 2228 if (!disk)
2229 goto out_free_queue;
a4aea562 2230
188c3568 2231 kref_init(&ns->kref);
5aff9382 2232 ns->ns_id = nsid;
b60503ba 2233 ns->disk = disk;
e1e5e564
KB		 2234 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2235 list_add_tail(&ns->list, &dev->namespaces);
2236
e9ef4636 2237 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
e824410f 2238 if (dev->max_hw_sectors) {
8fc23e03 2239 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
e824410f
KB		 2240 blk_queue_max_segments(ns->queue,
2241 ((dev->max_hw_sectors << 9) / dev->page_size) + 1);
2242 }
a4aea562
MB		 2243 if (dev->stripe_size)
2244 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 2245 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2246 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
03100aad 2247 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
b60503ba
MW		 2248
2249 disk->major = nvme_major;
469071a3 2250 disk->first_minor = 0;
b60503ba
MW		 2251 disk->fops = &nvme_fops;
2252 disk->private_data = ns;
2253 disk->queue = ns->queue;
b3fffdef 2254 disk->driverfs_dev = dev->device;
469071a3 2255 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 2256 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba 2257
e1e5e564
KB		 2258 /*
2259 * Initialize capacity to 0 until we establish the namespace format and
2260 * setup integrity extentions if necessary. The revalidate_disk after
2261 * add_disk allows the driver to register with integrity if the format
2262 * requires it.
2263 */
2264 set_capacity(disk, 0);
a5768aa8
KB		 2265 if (nvme_revalidate_disk(ns->disk))
2266 goto out_free_disk;
2267
5105aa55 2268 kref_get(&dev->kref);
e1e5e564 2269 add_disk(ns->disk);
7bee6074
KB		 2270 if (ns->ms) {
2271 struct block_device *bd = bdget_disk(ns->disk, 0);
2272 if (!bd)
2273 return;
2274 if (blkdev_get(bd, FMODE_READ, NULL)) {
2275 bdput(bd);
2276 return;
2277 }
2278 blkdev_reread_part(bd);
2279 blkdev_put(bd, FMODE_READ);
2280 }
e1e5e564 2281 return;
a5768aa8
KB		 2282 out_free_disk:
2283 kfree(disk);
2284 list_del(&ns->list);
b60503ba
MW		 2285 out_free_queue:
2286 blk_cleanup_queue(ns->queue);
2287 out_free_ns:
2288 kfree(ns);
b60503ba
MW		 2289}
2290
2659e57b
CH		 2291/*
2292 * Create I/O queues. Failing to create an I/O queue is not an issue,
2293 * we can continue with less than the desired amount of queues, and
2294 * even a controller without I/O queues an still be used to issue
2295 * admin commands. This might be useful to upgrade a buggy firmware
2296 * for example.
2297 */
42f61420
KB		 2298static void nvme_create_io_queues(struct nvme_dev *dev)
2299{
a4aea562 2300 unsigned i;
42f61420 2301
a4aea562 2302 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 2303 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 2304 break;
2305
a4aea562 2306 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2659e57b
CH		 2307 if (nvme_create_queue(dev->queues[i], i)) {
2308 nvme_free_queues(dev, i);
42f61420 2309 break;
2659e57b 2310 }
42f61420
KB		 2311}
2312
b3b06812 2313static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2314{
2315 int status;
2316 u32 result;
b3b06812 2317 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2318
df348139 2319 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2320 &result);
27e8166c
MW		 2321 if (status < 0)
2322 return status;
2323 if (status > 0) {
e75ec752 2324 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
badc34d4 2325 return 0;
27e8166c 2326 }
b60503ba
MW		 2327 return min(result & 0xffff, result >> 16) + 1;
2328}
2329
8ffaadf7
JD		 2330static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2331{
2332 u64 szu, size, offset;
2333 u32 cmbloc;
2334 resource_size_t bar_size;
2335 struct pci_dev *pdev = to_pci_dev(dev->dev);
2336 void __iomem *cmb;
2337 dma_addr_t dma_addr;
2338
2339 if (!use_cmb_sqes)
2340 return NULL;
2341
2342 dev->cmbsz = readl(&dev->bar->cmbsz);
2343 if (!(NVME_CMB_SZ(dev->cmbsz)))
2344 return NULL;
2345
2346 cmbloc = readl(&dev->bar->cmbloc);
2347
2348 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2349 size = szu * NVME_CMB_SZ(dev->cmbsz);
2350 offset = szu * NVME_CMB_OFST(cmbloc);
2351 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2352
2353 if (offset > bar_size)
2354 return NULL;
2355
2356 /*
2357 * Controllers may support a CMB size larger than their BAR,
2358 * for example, due to being behind a bridge. Reduce the CMB to
2359 * the reported size of the BAR
2360 */
2361 if (size > bar_size - offset)
2362 size = bar_size - offset;
2363
2364 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2365 cmb = ioremap_wc(dma_addr, size);
2366 if (!cmb)
2367 return NULL;
2368
2369 dev->cmb_dma_addr = dma_addr;
2370 dev->cmb_size = size;
2371 return cmb;
2372}
2373
2374static inline void nvme_release_cmb(struct nvme_dev *dev)
2375{
2376 if (dev->cmb) {
2377 iounmap(dev->cmb);
2378 dev->cmb = NULL;
2379 }
2380}
2381
9d713c2b
KB		 2382static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2383{
b80d5ccc 2384 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2385}
2386
8d85fce7 2387static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2388{
a4aea562 2389 struct nvme_queue *adminq = dev->queues[0];
e75ec752 2390 struct pci_dev *pdev = to_pci_dev(dev->dev);
42f61420 2391 int result, i, vecs, nr_io_queues, size;
b60503ba 2392
42f61420 2393 nr_io_queues = num_possible_cpus();
b348b7d5 2394 result = set_queue_count(dev, nr_io_queues);
badc34d4 2395 if (result <= 0)
1b23484b 2396 return result;
b348b7d5
MW		 2397 if (result < nr_io_queues)
2398 nr_io_queues = result;
b60503ba 2399
8ffaadf7
JD		 2400 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2401 result = nvme_cmb_qdepth(dev, nr_io_queues,
2402 sizeof(struct nvme_command));
2403 if (result > 0)
2404 dev->q_depth = result;
2405 else
2406 nvme_release_cmb(dev);
2407 }
2408
9d713c2b
KB		 2409 size = db_bar_size(dev, nr_io_queues);
2410 if (size > 8192) {
f1938f6e 2411 iounmap(dev->bar);
9d713c2b
KB		 2412 do {
2413 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2414 if (dev->bar)
2415 break;
2416 if (!--nr_io_queues)
2417 return -ENOMEM;
2418 size = db_bar_size(dev, nr_io_queues);
2419 } while (1);
f1938f6e 2420 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2421 adminq->q_db = dev->dbs;
f1938f6e
MW		 2422 }
2423
9d713c2b 2424 /* Deregister the admin queue's interrupt */
3193f07b 2425 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2426
e32efbfc
JA		 2427 /*
2428 * If we enable msix early due to not intx, disable it again before
2429 * setting up the full range we need.
2430 */
2431 if (!pdev->irq)
2432 pci_disable_msix(pdev);
2433
be577fab 2434 for (i = 0; i < nr_io_queues; i++)
1b23484b 2435 dev->entry[i].entry = i;
be577fab
AG		 2436 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2437 if (vecs < 0) {
2438 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2439 if (vecs < 0) {
2440 vecs = 1;
2441 } else {
2442 for (i = 0; i < vecs; i++)
2443 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2444 }
2445 }
2446
063a8096
MW		 2447 /*
2448 * Should investigate if there's a performance win from allocating
2449 * more queues than interrupt vectors; it might allow the submission
2450 * path to scale better, even if the receive path is limited by the
2451 * number of interrupts.
2452 */
2453 nr_io_queues = vecs;
42f61420 2454 dev->max_qid = nr_io_queues;
063a8096 2455
3193f07b 2456 result = queue_request_irq(dev, adminq, adminq->irqname);
758dd7fd
JD		 2457 if (result) {
2458 adminq->cq_vector = -1;
22404274 2459 goto free_queues;
758dd7fd 2460 }
1b23484b 2461
cd638946 2462 /* Free previously allocated queues that are no longer usable */
42f61420 2463 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2464 nvme_create_io_queues(dev);
9ecdc946 2465
22404274 2466 return 0;
b60503ba 2467
22404274 2468 free_queues:
a1a5ef99 2469 nvme_free_queues(dev, 1);
22404274 2470 return result;
b60503ba
MW		 2471}
2472
a5768aa8
KB		 2473static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2474{
2475 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2476 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2477
2478 return nsa->ns_id - nsb->ns_id;
2479}
2480
2481static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2482{
2483 struct nvme_ns *ns;
2484
2485 list_for_each_entry(ns, &dev->namespaces, list) {
2486 if (ns->ns_id == nsid)
2487 return ns;
2488 if (ns->ns_id > nsid)
2489 break;
2490 }
2491 return NULL;
2492}
2493
2494static inline bool nvme_io_incapable(struct nvme_dev *dev)
2495{
2496 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2497 dev->online_queues < 2);
2498}
2499
2500static void nvme_ns_remove(struct nvme_ns *ns)
2501{
2502 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2503
2504 if (kill)
2505 blk_set_queue_dying(ns->queue);
2506 if (ns->disk->flags & GENHD_FL_UP) {
2507 if (blk_get_integrity(ns->disk))
2508 blk_integrity_unregister(ns->disk);
2509 del_gendisk(ns->disk);
2510 }
2511 if (kill || !blk_queue_dying(ns->queue)) {
2512 blk_mq_abort_requeue_list(ns->queue);
2513 blk_cleanup_queue(ns->queue);
5105aa55
KB		 2514 }
2515 list_del_init(&ns->list);
2516 kref_put(&ns->kref, nvme_free_ns);
a5768aa8
KB		 2517}
2518
2519static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2520{
2521 struct nvme_ns *ns, *next;
2522 unsigned i;
2523
2524 for (i = 1; i <= nn; i++) {
2525 ns = nvme_find_ns(dev, i);
2526 if (ns) {
5105aa55 2527 if (revalidate_disk(ns->disk))
a5768aa8 2528 nvme_ns_remove(ns);
a5768aa8
KB		 2529 } else
2530 nvme_alloc_ns(dev, i);
2531 }
2532 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
5105aa55 2533 if (ns->ns_id > nn)
a5768aa8 2534 nvme_ns_remove(ns);
a5768aa8
KB		 2535 }
2536 list_sort(NULL, &dev->namespaces, ns_cmp);
2537}
2538
bda4e0fb
KB		 2539static void nvme_set_irq_hints(struct nvme_dev *dev)
2540{
2541 struct nvme_queue *nvmeq;
2542 int i;
2543
2544 for (i = 0; i < dev->online_queues; i++) {
2545 nvmeq = dev->queues[i];
2546
2547 if (!nvmeq->tags || !(*nvmeq->tags))
2548 continue;
2549
2550 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2551 blk_mq_tags_cpumask(*nvmeq->tags));
2552 }
2553}
2554
a5768aa8
KB		 2555static void nvme_dev_scan(struct work_struct *work)
2556{
2557 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2558 struct nvme_id_ctrl *ctrl;
2559
2560 if (!dev->tagset.tags)
2561 return;
2562 if (nvme_identify_ctrl(dev, &ctrl))
2563 return;
2564 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2565 kfree(ctrl);
bda4e0fb 2566 nvme_set_irq_hints(dev);
a5768aa8
KB		 2567}
2568
422ef0c7
MW		 2569/*
2570 * Return: error value if an error occurred setting up the queues or calling
2571 * Identify Device. 0 if these succeeded, even if adding some of the
2572 * namespaces failed. At the moment, these failures are silent. TBD which
2573 * failures should be reported.
2574 */
8d85fce7 2575static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2576{
e75ec752 2577 struct pci_dev *pdev = to_pci_dev(dev->dev);
c3bfe717 2578 int res;
51814232 2579 struct nvme_id_ctrl *ctrl;
159b67d7 2580 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2581
d29ec824 2582 res = nvme_identify_ctrl(dev, &ctrl);
b60503ba 2583 if (res) {
e75ec752 2584 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
e1e5e564 2585 return -EIO;
b60503ba
MW		 2586 }
2587
0e5e4f0e 2588 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2589 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2590 dev->vwc = ctrl->vwc;
51814232
MW		 2591 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2592 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2593 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2594 if (ctrl->mdts)
8fc23e03 2595 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2596 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2597 (pdev->device == 0x0953) && ctrl->vs[3]) {
2598 unsigned int max_hw_sectors;
2599
159b67d7 2600 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2601 max_hw_sectors = dev->stripe_size >> (shift - 9);
2602 if (dev->max_hw_sectors) {
2603 dev->max_hw_sectors = min(max_hw_sectors,
2604 dev->max_hw_sectors);
2605 } else
2606 dev->max_hw_sectors = max_hw_sectors;
2607 }
d29ec824 2608 kfree(ctrl);
a4aea562 2609
ffe7704d
KB		 2610 if (!dev->tagset.tags) {
2611 dev->tagset.ops = &nvme_mq_ops;
2612 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2613 dev->tagset.timeout = NVME_IO_TIMEOUT;
2614 dev->tagset.numa_node = dev_to_node(dev->dev);
2615 dev->tagset.queue_depth =
a4aea562 2616 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
ffe7704d
KB		 2617 dev->tagset.cmd_size = nvme_cmd_size(dev);
2618 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2619 dev->tagset.driver_data = dev;
b60503ba 2620
ffe7704d
KB		 2621 if (blk_mq_alloc_tag_set(&dev->tagset))
2622 return 0;
2623 }
a5768aa8 2624 schedule_work(&dev->scan_work);
e1e5e564 2625 return 0;
b60503ba
MW		 2626}
2627
0877cb0d
KB		 2628static int nvme_dev_map(struct nvme_dev *dev)
2629{
42f61420 2630 u64 cap;
0877cb0d 2631 int bars, result = -ENOMEM;
e75ec752 2632 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2633
2634 if (pci_enable_device_mem(pdev))
2635 return result;
2636
2637 dev->entry[0].vector = pdev->irq;
2638 pci_set_master(pdev);
2639 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2640 if (!bars)
2641 goto disable_pci;
2642
0877cb0d
KB		 2643 if (pci_request_selected_regions(pdev, bars, "nvme"))
2644 goto disable_pci;
2645
e75ec752
CH		 2646 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2647 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2648 goto disable;
0877cb0d 2649
0877cb0d
KB		 2650 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2651 if (!dev->bar)
2652 goto disable;
e32efbfc 2653
0e53d180
KB		 2654 if (readl(&dev->bar->csts) == -1) {
2655 result = -ENODEV;
2656 goto unmap;
2657 }
e32efbfc
JA		 2658
2659 /*
2660 * Some devices don't advertse INTx interrupts, pre-enable a single
2661 * MSIX vec for setup. We'll adjust this later.
2662 */
2663 if (!pdev->irq) {
2664 result = pci_enable_msix(pdev, dev->entry, 1);
2665 if (result < 0)
2666 goto unmap;
2667 }
2668
42f61420
KB		 2669 cap = readq(&dev->bar->cap);
2670 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2671 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d 2672 dev->dbs = ((void __iomem *)dev->bar) + 4096;
8ffaadf7
JD		 2673 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2674 dev->cmb = nvme_map_cmb(dev);
0877cb0d
KB		 2675
2676 return 0;
2677
0e53d180
KB		 2678 unmap:
2679 iounmap(dev->bar);
2680 dev->bar = NULL;
0877cb0d
KB		 2681 disable:
2682 pci_release_regions(pdev);
2683 disable_pci:
2684 pci_disable_device(pdev);
2685 return result;
2686}
2687
2688static void nvme_dev_unmap(struct nvme_dev *dev)
2689{
e75ec752
CH		 2690 struct pci_dev *pdev = to_pci_dev(dev->dev);
2691
2692 if (pdev->msi_enabled)
2693 pci_disable_msi(pdev);
2694 else if (pdev->msix_enabled)
2695 pci_disable_msix(pdev);
0877cb0d
KB		 2696
2697 if (dev->bar) {
2698 iounmap(dev->bar);
2699 dev->bar = NULL;
e75ec752 2700 pci_release_regions(pdev);
0877cb0d
KB		 2701 }
2702
e75ec752
CH		 2703 if (pci_is_enabled(pdev))
2704 pci_disable_device(pdev);
0877cb0d
KB		 2705}
2706
4d115420
KB		 2707struct nvme_delq_ctx {
2708 struct task_struct *waiter;
2709 struct kthread_worker *worker;
2710 atomic_t refcount;
2711};
2712
2713static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2714{
2715 dq->waiter = current;
2716 mb();
2717
2718 for (;;) {
2719 set_current_state(TASK_KILLABLE);
2720 if (!atomic_read(&dq->refcount))
2721 break;
2722 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2723 fatal_signal_pending(current)) {
0fb59cbc
KB		 2724 /*
2725 * Disable the controller first since we can't trust it
2726 * at this point, but leave the admin queue enabled
2727 * until all queue deletion requests are flushed.
2728 * FIXME: This may take a while if there are more h/w
2729 * queues than admin tags.
2730 */
4d115420 2731 set_current_state(TASK_RUNNING);
4d115420 2732 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
0fb59cbc 2733 nvme_clear_queue(dev->queues[0]);
4d115420 2734 flush_kthread_worker(dq->worker);
0fb59cbc 2735 nvme_disable_queue(dev, 0);
4d115420
KB		 2736 return;
2737 }
2738 }
2739 set_current_state(TASK_RUNNING);
2740}
2741
2742static void nvme_put_dq(struct nvme_delq_ctx *dq)
2743{
2744 atomic_dec(&dq->refcount);
2745 if (dq->waiter)
2746 wake_up_process(dq->waiter);
2747}
2748
2749static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2750{
2751 atomic_inc(&dq->refcount);
2752 return dq;
2753}
2754
2755static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2756{
2757 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
4d115420
KB		 2758 nvme_put_dq(dq);
2759}
2760
2761static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2762 kthread_work_func_t fn)
2763{
2764 struct nvme_command c;
2765
2766 memset(&c, 0, sizeof(c));
2767 c.delete_queue.opcode = opcode;
2768 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2769
2770 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2771 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2772 ADMIN_TIMEOUT);
4d115420
KB		 2773}
2774
2775static void nvme_del_cq_work_handler(struct kthread_work *work)
2776{
2777 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2778 cmdinfo.work);
2779 nvme_del_queue_end(nvmeq);
2780}
2781
2782static int nvme_delete_cq(struct nvme_queue *nvmeq)
2783{
2784 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2785 nvme_del_cq_work_handler);
2786}
2787
2788static void nvme_del_sq_work_handler(struct kthread_work *work)
2789{
2790 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2791 cmdinfo.work);
2792 int status = nvmeq->cmdinfo.status;
2793
2794 if (!status)
2795 status = nvme_delete_cq(nvmeq);
2796 if (status)
2797 nvme_del_queue_end(nvmeq);
2798}
2799
2800static int nvme_delete_sq(struct nvme_queue *nvmeq)
2801{
2802 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2803 nvme_del_sq_work_handler);
2804}
2805
2806static void nvme_del_queue_start(struct kthread_work *work)
2807{
2808 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2809 cmdinfo.work);
4d115420
KB		 2810 if (nvme_delete_sq(nvmeq))
2811 nvme_del_queue_end(nvmeq);
2812}
2813
2814static void nvme_disable_io_queues(struct nvme_dev *dev)
2815{
2816 int i;
2817 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2818 struct nvme_delq_ctx dq;
2819 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2820 &worker, "nvme%d", dev->instance);
2821
2822 if (IS_ERR(kworker_task)) {
e75ec752 2823 dev_err(dev->dev,
4d115420
KB		 2824 "Failed to create queue del task\n");
2825 for (i = dev->queue_count - 1; i > 0; i--)
2826 nvme_disable_queue(dev, i);
2827 return;
2828 }
2829
2830 dq.waiter = NULL;
2831 atomic_set(&dq.refcount, 0);
2832 dq.worker = &worker;
2833 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2834 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2835
2836 if (nvme_suspend_queue(nvmeq))
2837 continue;
2838 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2839 nvmeq->cmdinfo.worker = dq.worker;
2840 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2841 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2842 }
2843 nvme_wait_dq(&dq, dev);
2844 kthread_stop(kworker_task);
2845}
2846
b9afca3e
DM		 2847/*
2848* Remove the node from the device list and check
2849* for whether or not we need to stop the nvme_thread.
2850*/
2851static void nvme_dev_list_remove(struct nvme_dev *dev)
2852{
2853 struct task_struct *tmp = NULL;
2854
2855 spin_lock(&dev_list_lock);
2856 list_del_init(&dev->node);
2857 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2858 tmp = nvme_thread;
2859 nvme_thread = NULL;
2860 }
2861 spin_unlock(&dev_list_lock);
2862
2863 if (tmp)
2864 kthread_stop(tmp);
2865}
2866
c9d3bf88
KB		 2867static void nvme_freeze_queues(struct nvme_dev *dev)
2868{
2869 struct nvme_ns *ns;
2870
2871 list_for_each_entry(ns, &dev->namespaces, list) {
2872 blk_mq_freeze_queue_start(ns->queue);
2873
cddcd72b 2874 spin_lock_irq(ns->queue->queue_lock);
c9d3bf88 2875 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
cddcd72b 2876 spin_unlock_irq(ns->queue->queue_lock);
c9d3bf88
KB		 2877
2878 blk_mq_cancel_requeue_work(ns->queue);
2879 blk_mq_stop_hw_queues(ns->queue);
2880 }
2881}
2882
2883static void nvme_unfreeze_queues(struct nvme_dev *dev)
2884{
2885 struct nvme_ns *ns;
2886
2887 list_for_each_entry(ns, &dev->namespaces, list) {
2888 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2889 blk_mq_unfreeze_queue(ns->queue);
2890 blk_mq_start_stopped_hw_queues(ns->queue, true);
2891 blk_mq_kick_requeue_list(ns->queue);
2892 }
2893}
2894
f0b50732 2895static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2896{
22404274 2897 int i;
7c1b2450 2898 u32 csts = -1;
22404274 2899
b9afca3e 2900 nvme_dev_list_remove(dev);
1fa6aead 2901
c9d3bf88
KB		 2902 if (dev->bar) {
2903 nvme_freeze_queues(dev);
7c1b2450 2904 csts = readl(&dev->bar->csts);
c9d3bf88 2905 }
7c1b2450 2906 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2907 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2908 struct nvme_queue *nvmeq = dev->queues[i];
4d115420 2909 nvme_suspend_queue(nvmeq);
4d115420
KB		 2910 }
2911 } else {
2912 nvme_disable_io_queues(dev);
1894d8f1 2913 nvme_shutdown_ctrl(dev);
4d115420
KB		 2914 nvme_disable_queue(dev, 0);
2915 }
f0b50732 2916 nvme_dev_unmap(dev);
07836e65
KB		 2917
2918 for (i = dev->queue_count - 1; i >= 0; i--)
2919 nvme_clear_queue(dev->queues[i]);
f0b50732
KB		 2920}
2921
2922static void nvme_dev_remove(struct nvme_dev *dev)
2923{
5105aa55 2924 struct nvme_ns *ns, *next;
f0b50732 2925
5105aa55 2926 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
a5768aa8 2927 nvme_ns_remove(ns);
b60503ba
MW		 2928}
2929
091b6092
MW		 2930static int nvme_setup_prp_pools(struct nvme_dev *dev)
2931{
e75ec752 2932 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2933 PAGE_SIZE, PAGE_SIZE, 0);
2934 if (!dev->prp_page_pool)
2935 return -ENOMEM;
2936
99802a7a 2937 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2938 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2939 256, 256, 0);
2940 if (!dev->prp_small_pool) {
2941 dma_pool_destroy(dev->prp_page_pool);
2942 return -ENOMEM;
2943 }
091b6092
MW		 2944 return 0;
2945}
2946
2947static void nvme_release_prp_pools(struct nvme_dev *dev)
2948{
2949 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2950 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2951}
2952
cd58ad7d
QSA		 2953static DEFINE_IDA(nvme_instance_ida);
2954
2955static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2956{
cd58ad7d
QSA		 2957 int instance, error;
2958
2959 do {
2960 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2961 return -ENODEV;
2962
2963 spin_lock(&dev_list_lock);
2964 error = ida_get_new(&nvme_instance_ida, &instance);
2965 spin_unlock(&dev_list_lock);
2966 } while (error == -EAGAIN);
2967
2968 if (error)
2969 return -ENODEV;
2970
2971 dev->instance = instance;
2972 return 0;
b60503ba
MW		 2973}
2974
2975static void nvme_release_instance(struct nvme_dev *dev)
2976{
cd58ad7d
QSA		 2977 spin_lock(&dev_list_lock);
2978 ida_remove(&nvme_instance_ida, dev->instance);
2979 spin_unlock(&dev_list_lock);
b60503ba
MW		 2980}
2981
5e82e952
KB		 2982static void nvme_free_dev(struct kref *kref)
2983{
2984 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2985
e75ec752 2986 put_device(dev->dev);
b3fffdef 2987 put_device(dev->device);
285dffc9 2988 nvme_release_instance(dev);
4af0e21c
KB		 2989 if (dev->tagset.tags)
2990 blk_mq_free_tag_set(&dev->tagset);
2991 if (dev->admin_q)
2992 blk_put_queue(dev->admin_q);
5e82e952
KB		 2993 kfree(dev->queues);
2994 kfree(dev->entry);
2995 kfree(dev);
2996}
2997
2998static int nvme_dev_open(struct inode *inode, struct file *f)
2999{
b3fffdef
KB		 3000 struct nvme_dev *dev;
3001 int instance = iminor(inode);
3002 int ret = -ENODEV;
3003
3004 spin_lock(&dev_list_lock);
3005 list_for_each_entry(dev, &dev_list, node) {
3006 if (dev->instance == instance) {
2e1d8448
KB		 3007 if (!dev->admin_q) {
3008 ret = -EWOULDBLOCK;
3009 break;
3010 }
b3fffdef
KB		 3011 if (!kref_get_unless_zero(&dev->kref))
3012 break;
3013 f->private_data = dev;
3014 ret = 0;
3015 break;
3016 }
3017 }
3018 spin_unlock(&dev_list_lock);
3019
3020 return ret;
5e82e952
KB		 3021}
3022
3023static int nvme_dev_release(struct inode *inode, struct file *f)
3024{
3025 struct nvme_dev *dev = f->private_data;
3026 kref_put(&dev->kref, nvme_free_dev);
3027 return 0;
3028}
3029
3030static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
3031{
3032 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 3033 struct nvme_ns *ns;
3034
5e82e952
KB		 3035 switch (cmd) {
3036 case NVME_IOCTL_ADMIN_CMD:
a4aea562 3037 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 3038 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 3039 if (list_empty(&dev->namespaces))
3040 return -ENOTTY;
3041 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
3042 return nvme_user_cmd(dev, ns, (void __user *)arg);
4cc06521
KB		 3043 case NVME_IOCTL_RESET:
3044 dev_warn(dev->dev, "resetting controller\n");
3045 return nvme_reset(dev);
81f03fed
JD		 3046 case NVME_IOCTL_SUBSYS_RESET:
3047 return nvme_subsys_reset(dev);
5e82e952
KB		 3048 default:
3049 return -ENOTTY;
3050 }
3051}
3052
3053static const struct file_operations nvme_dev_fops = {
3054 .owner = THIS_MODULE,
3055 .open = nvme_dev_open,
3056 .release = nvme_dev_release,
3057 .unlocked_ioctl = nvme_dev_ioctl,
3058 .compat_ioctl = nvme_dev_ioctl,
3059};
3060
3cf519b5 3061static void nvme_probe_work(struct work_struct *work)
f0b50732 3062{
3cf519b5 3063 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
b9afca3e 3064 bool start_thread = false;
3cf519b5 3065 int result;
f0b50732
KB		 3066
3067 result = nvme_dev_map(dev);
3068 if (result)
3cf519b5 3069 goto out;
f0b50732
KB		 3070
3071 result = nvme_configure_admin_queue(dev);
3072 if (result)
3073 goto unmap;
3074
3075 spin_lock(&dev_list_lock);
b9afca3e
DM		 3076 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3077 start_thread = true;
3078 nvme_thread = NULL;
3079 }
f0b50732
KB		 3080 list_add(&dev->node, &dev_list);
3081 spin_unlock(&dev_list_lock);
3082
b9afca3e
DM		 3083 if (start_thread) {
3084 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 3085 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 3086 } else
3087 wait_event_killable(nvme_kthread_wait, nvme_thread);
3088
3089 if (IS_ERR_OR_NULL(nvme_thread)) {
3090 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3091 goto disable;
3092 }
a4aea562
MB		 3093
3094 nvme_init_queue(dev->queues[0], 0);
0fb59cbc
KB		 3095 result = nvme_alloc_admin_tags(dev);
3096 if (result)
3097 goto disable;
b9afca3e 3098
f0b50732 3099 result = nvme_setup_io_queues(dev);
badc34d4 3100 if (result)
0fb59cbc 3101 goto free_tags;
f0b50732 3102
1efccc9d 3103 dev->event_limit = 1;
3cf519b5 3104
2659e57b
CH		 3105 /*
3106 * Keep the controller around but remove all namespaces if we don't have
3107 * any working I/O queue.
3108 */
3cf519b5
CH		 3109 if (dev->online_queues < 2) {
3110 dev_warn(dev->dev, "IO queues not created\n");
3cf519b5
CH		 3111 nvme_dev_remove(dev);
3112 } else {
3113 nvme_unfreeze_queues(dev);
3114 nvme_dev_add(dev);
3115 }
3116
3117 return;
f0b50732 3118
0fb59cbc
KB		 3119 free_tags:
3120 nvme_dev_remove_admin(dev);
4af0e21c
KB		 3121 blk_put_queue(dev->admin_q);
3122 dev->admin_q = NULL;
3123 dev->queues[0]->tags = NULL;
f0b50732 3124 disable:
a1a5ef99 3125 nvme_disable_queue(dev, 0);
b9afca3e 3126 nvme_dev_list_remove(dev);
f0b50732
KB		 3127 unmap:
3128 nvme_dev_unmap(dev);
3cf519b5
CH		 3129 out:
3130 if (!work_busy(&dev->reset_work))
3131 nvme_dead_ctrl(dev);
f0b50732
KB		 3132}
3133
9a6b9458
KB		 3134static int nvme_remove_dead_ctrl(void *arg)
3135{
3136 struct nvme_dev *dev = (struct nvme_dev *)arg;
e75ec752 3137 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 3138
3139 if (pci_get_drvdata(pdev))
c81f4975 3140 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 3141 kref_put(&dev->kref, nvme_free_dev);
3142 return 0;
3143}
3144
de3eff2b
KB		 3145static void nvme_dead_ctrl(struct nvme_dev *dev)
3146{
3147 dev_warn(dev->dev, "Device failed to resume\n");
3148 kref_get(&dev->kref);
3149 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3150 dev->instance))) {
3151 dev_err(dev->dev,
3152 "Failed to start controller remove task\n");
3153 kref_put(&dev->kref, nvme_free_dev);
3154 }
3155}
3156
77b50d9e 3157static void nvme_reset_work(struct work_struct *ws)
9a6b9458 3158{
77b50d9e 3159 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
ffe7704d
KB		 3160 bool in_probe = work_busy(&dev->probe_work);
3161
9a6b9458 3162 nvme_dev_shutdown(dev);
ffe7704d
KB		 3163
3164 /* Synchronize with device probe so that work will see failure status
3165 * and exit gracefully without trying to schedule another reset */
3166 flush_work(&dev->probe_work);
3167
3168 /* Fail this device if reset occured during probe to avoid
3169 * infinite initialization loops. */
3170 if (in_probe) {
de3eff2b 3171 nvme_dead_ctrl(dev);
ffe7704d 3172 return;
9a6b9458 3173 }
ffe7704d
KB		 3174 /* Schedule device resume asynchronously so the reset work is available
3175 * to cleanup errors that may occur during reinitialization */
3176 schedule_work(&dev->probe_work);
9a6b9458
KB		 3177}
3178
90667892
CH		 3179static int __nvme_reset(struct nvme_dev *dev)
3180{
3181 if (work_pending(&dev->reset_work))
3182 return -EBUSY;
3183 list_del_init(&dev->node);
3184 queue_work(nvme_workq, &dev->reset_work);
3185 return 0;
3186}
3187
4cc06521
KB		 3188static int nvme_reset(struct nvme_dev *dev)
3189{
90667892 3190 int ret;
4cc06521
KB		 3191
3192 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3193 return -ENODEV;
3194
3195 spin_lock(&dev_list_lock);
90667892 3196 ret = __nvme_reset(dev);
4cc06521
KB		 3197 spin_unlock(&dev_list_lock);
3198
3199 if (!ret) {
3200 flush_work(&dev->reset_work);
ffe7704d 3201 flush_work(&dev->probe_work);
4cc06521
KB		 3202 return 0;
3203 }
3204
3205 return ret;
3206}
3207
3208static ssize_t nvme_sysfs_reset(struct device *dev,
3209 struct device_attribute *attr, const char *buf,
3210 size_t count)
3211{
3212 struct nvme_dev *ndev = dev_get_drvdata(dev);
3213 int ret;
3214
3215 ret = nvme_reset(ndev);
3216 if (ret < 0)
3217 return ret;
3218
3219 return count;
3220}
3221static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3222
8d85fce7 3223static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 3224{
a4aea562 3225 int node, result = -ENOMEM;
b60503ba
MW		 3226 struct nvme_dev *dev;
3227
a4aea562
MB		 3228 node = dev_to_node(&pdev->dev);
3229 if (node == NUMA_NO_NODE)
3230 set_dev_node(&pdev->dev, 0);
3231
3232 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 3233 if (!dev)
3234 return -ENOMEM;
a4aea562
MB		 3235 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3236 GFP_KERNEL, node);
b60503ba
MW		 3237 if (!dev->entry)
3238 goto free;
a4aea562
MB		 3239 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3240 GFP_KERNEL, node);
b60503ba
MW		 3241 if (!dev->queues)
3242 goto free;
3243
3244 INIT_LIST_HEAD(&dev->namespaces);
77b50d9e 3245 INIT_WORK(&dev->reset_work, nvme_reset_work);
e75ec752 3246 dev->dev = get_device(&pdev->dev);
9a6b9458 3247 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 3248 result = nvme_set_instance(dev);
3249 if (result)
a96d4f5c 3250 goto put_pci;
b60503ba 3251
091b6092
MW		 3252 result = nvme_setup_prp_pools(dev);
3253 if (result)
0877cb0d 3254 goto release;
091b6092 3255
fb35e914 3256 kref_init(&dev->kref);
b3fffdef
KB		 3257 dev->device = device_create(nvme_class, &pdev->dev,
3258 MKDEV(nvme_char_major, dev->instance),
3259 dev, "nvme%d", dev->instance);
3260 if (IS_ERR(dev->device)) {
3261 result = PTR_ERR(dev->device);
2e1d8448 3262 goto release_pools;
b3fffdef
KB		 3263 }
3264 get_device(dev->device);
4cc06521
KB		 3265 dev_set_drvdata(dev->device, dev);
3266
3267 result = device_create_file(dev->device, &dev_attr_reset_controller);
3268 if (result)
3269 goto put_dev;
740216fc 3270
e6e96d73 3271 INIT_LIST_HEAD(&dev->node);
a5768aa8 3272 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3cf519b5 3273 INIT_WORK(&dev->probe_work, nvme_probe_work);
2e1d8448 3274 schedule_work(&dev->probe_work);
b60503ba
MW		 3275 return 0;
3276
4cc06521
KB		 3277 put_dev:
3278 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3279 put_device(dev->device);
0877cb0d 3280 release_pools:
091b6092 3281 nvme_release_prp_pools(dev);
0877cb0d
KB		 3282 release:
3283 nvme_release_instance(dev);
a96d4f5c 3284 put_pci:
e75ec752 3285 put_device(dev->dev);
b60503ba
MW		 3286 free:
3287 kfree(dev->queues);
3288 kfree(dev->entry);
3289 kfree(dev);
3290 return result;
3291}
3292
f0d54a54
KB		 3293static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3294{
a6739479 3295 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 3296
a6739479
KB		 3297 if (prepare)
3298 nvme_dev_shutdown(dev);
3299 else
0a7385ad 3300 schedule_work(&dev->probe_work);
f0d54a54
KB		 3301}
3302
09ece142
KB		 3303static void nvme_shutdown(struct pci_dev *pdev)
3304{
3305 struct nvme_dev *dev = pci_get_drvdata(pdev);
3306 nvme_dev_shutdown(dev);
3307}
3308
8d85fce7 3309static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3310{
3311 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 3312
3313 spin_lock(&dev_list_lock);
3314 list_del_init(&dev->node);
3315 spin_unlock(&dev_list_lock);
3316
3317 pci_set_drvdata(pdev, NULL);
2e1d8448 3318 flush_work(&dev->probe_work);
9a6b9458 3319 flush_work(&dev->reset_work);
a5768aa8 3320 flush_work(&dev->scan_work);
4cc06521 3321 device_remove_file(dev->device, &dev_attr_reset_controller);
c9d3bf88 3322 nvme_dev_remove(dev);
3399a3f7 3323 nvme_dev_shutdown(dev);
a4aea562 3324 nvme_dev_remove_admin(dev);
b3fffdef 3325 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
a1a5ef99 3326 nvme_free_queues(dev, 0);
8ffaadf7 3327 nvme_release_cmb(dev);
9a6b9458 3328 nvme_release_prp_pools(dev);
5e82e952 3329 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 3330}
3331
3332/* These functions are yet to be implemented */
3333#define nvme_error_detected NULL
3334#define nvme_dump_registers NULL
3335#define nvme_link_reset NULL
3336#define nvme_slot_reset NULL
3337#define nvme_error_resume NULL
cd638946 3338
671a6018 3339#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3340static int nvme_suspend(struct device *dev)
3341{
3342 struct pci_dev *pdev = to_pci_dev(dev);
3343 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3344
3345 nvme_dev_shutdown(ndev);
3346 return 0;
3347}
3348
3349static int nvme_resume(struct device *dev)
3350{
3351 struct pci_dev *pdev = to_pci_dev(dev);
3352 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3353
0a7385ad 3354 schedule_work(&ndev->probe_work);
9a6b9458 3355 return 0;
cd638946 3356}
671a6018 3357#endif
cd638946
KB		 3358
3359static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 3360
1d352035 3361static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 3362 .error_detected = nvme_error_detected,
3363 .mmio_enabled = nvme_dump_registers,
3364 .link_reset = nvme_link_reset,
3365 .slot_reset = nvme_slot_reset,
3366 .resume = nvme_error_resume,
f0d54a54 3367 .reset_notify = nvme_reset_notify,
b60503ba
MW		 3368};
3369
3370/* Move to pci_ids.h later */
3371#define PCI_CLASS_STORAGE_EXPRESS 0x010802
3372
6eb0d698 3373static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 3374 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3375 { 0, }
3376};
3377MODULE_DEVICE_TABLE(pci, nvme_id_table);
3378
3379static struct pci_driver nvme_driver = {
3380 .name = "nvme",
3381 .id_table = nvme_id_table,
3382 .probe = nvme_probe,
8d85fce7 3383 .remove = nvme_remove,
09ece142 3384 .shutdown = nvme_shutdown,
cd638946
KB		 3385 .driver = {
3386 .pm = &nvme_dev_pm_ops,
3387 },
b60503ba
MW		 3388 .err_handler = &nvme_err_handler,
3389};
3390
3391static int __init nvme_init(void)
3392{
0ac13140 3393 int result;
1fa6aead 3394
b9afca3e 3395 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 3396
9a6b9458
KB		 3397 nvme_workq = create_singlethread_workqueue("nvme");
3398 if (!nvme_workq)
b9afca3e 3399 return -ENOMEM;
9a6b9458 3400
5c42ea16
KB		 3401 result = register_blkdev(nvme_major, "nvme");
3402 if (result < 0)
9a6b9458 3403 goto kill_workq;
5c42ea16 3404 else if (result > 0)
0ac13140 3405 nvme_major = result;
b60503ba 3406
b3fffdef
KB		 3407 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3408 &nvme_dev_fops);
3409 if (result < 0)
3410 goto unregister_blkdev;
3411 else if (result > 0)
3412 nvme_char_major = result;
3413
3414 nvme_class = class_create(THIS_MODULE, "nvme");
c727040b
AK		 3415 if (IS_ERR(nvme_class)) {
3416 result = PTR_ERR(nvme_class);
b3fffdef 3417 goto unregister_chrdev;
c727040b 3418 }
b3fffdef 3419
f3db22fe
KB		 3420 result = pci_register_driver(&nvme_driver);
3421 if (result)
b3fffdef 3422 goto destroy_class;
1fa6aead 3423 return 0;
b60503ba 3424
b3fffdef
KB		 3425 destroy_class:
3426 class_destroy(nvme_class);
3427 unregister_chrdev:
3428 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
1fa6aead 3429 unregister_blkdev:
b60503ba 3430 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 3431 kill_workq:
3432 destroy_workqueue(nvme_workq);
b60503ba
MW		 3433 return result;
3434}
3435
3436static void __exit nvme_exit(void)
3437{
3438 pci_unregister_driver(&nvme_driver);
3439 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3440 destroy_workqueue(nvme_workq);
b3fffdef
KB		 3441 class_destroy(nvme_class);
3442 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
b9afca3e 3443 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3444 _nvme_check_size();
b60503ba
MW		 3445}
3446
3447MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3448MODULE_LICENSE("GPL");
c78b4713 3449MODULE_VERSION("1.0");
b60503ba
MW		 3450module_init(nvme_init);
3451module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)