Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
18119775 | 16 | #include <linux/async.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
ff5350a8 | 20 | #include <linux/dmi.h> |
b60503ba MW |
21 | #include <linux/init.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
b60503ba MW |
24 | #include <linux/mm.h> |
25 | #include <linux/module.h> | |
77bf25ea | 26 | #include <linux/mutex.h> |
d0877473 | 27 | #include <linux/once.h> |
b60503ba | 28 | #include <linux/pci.h> |
e1e5e564 | 29 | #include <linux/t10-pi.h> |
b60503ba | 30 | #include <linux/types.h> |
2f8e2c87 | 31 | #include <linux/io-64-nonatomic-lo-hi.h> |
a98e58e5 | 32 | #include <linux/sed-opal.h> |
797a796a | 33 | |
f11bb3e2 CH |
34 | #include "nvme.h" |
35 | ||
b60503ba MW |
36 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
37 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 38 | |
a7a7cbe3 | 39 | #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) |
9d43cf64 | 40 | |
58ffacb5 MW |
41 | static int use_threaded_interrupts; |
42 | module_param(use_threaded_interrupts, int, 0); | |
43 | ||
8ffaadf7 JD |
44 | static bool use_cmb_sqes = true; |
45 | module_param(use_cmb_sqes, bool, 0644); | |
46 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
47 | ||
87ad72a5 CH |
48 | static unsigned int max_host_mem_size_mb = 128; |
49 | module_param(max_host_mem_size_mb, uint, 0444); | |
50 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
51 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
1fa6aead | 52 | |
a7a7cbe3 CK |
53 | static unsigned int sgl_threshold = SZ_32K; |
54 | module_param(sgl_threshold, uint, 0644); | |
55 | MODULE_PARM_DESC(sgl_threshold, | |
56 | "Use SGLs when average request segment size is larger or equal to " | |
57 | "this size. Use 0 to disable SGLs."); | |
58 | ||
b27c1e68 | 59 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
60 | static const struct kernel_param_ops io_queue_depth_ops = { | |
61 | .set = io_queue_depth_set, | |
62 | .get = param_get_int, | |
63 | }; | |
64 | ||
65 | static int io_queue_depth = 1024; | |
66 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); | |
67 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); | |
68 | ||
1c63dc66 CH |
69 | struct nvme_dev; |
70 | struct nvme_queue; | |
b3fffdef | 71 | |
a0fa9647 | 72 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 73 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 74 | |
1c63dc66 CH |
75 | /* |
76 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
77 | */ | |
78 | struct nvme_dev { | |
147b27e4 | 79 | struct nvme_queue *queues; |
1c63dc66 CH |
80 | struct blk_mq_tag_set tagset; |
81 | struct blk_mq_tag_set admin_tagset; | |
82 | u32 __iomem *dbs; | |
83 | struct device *dev; | |
84 | struct dma_pool *prp_page_pool; | |
85 | struct dma_pool *prp_small_pool; | |
1c63dc66 CH |
86 | unsigned online_queues; |
87 | unsigned max_qid; | |
22b55601 | 88 | unsigned int num_vecs; |
1c63dc66 CH |
89 | int q_depth; |
90 | u32 db_stride; | |
1c63dc66 | 91 | void __iomem *bar; |
97f6ef64 | 92 | unsigned long bar_mapped_size; |
5c8809e6 | 93 | struct work_struct remove_work; |
77bf25ea | 94 | struct mutex shutdown_lock; |
1c63dc66 | 95 | bool subsystem; |
1c63dc66 | 96 | void __iomem *cmb; |
8969f1f8 | 97 | pci_bus_addr_t cmb_bus_addr; |
1c63dc66 CH |
98 | u64 cmb_size; |
99 | u32 cmbsz; | |
202021c1 | 100 | u32 cmbloc; |
1c63dc66 | 101 | struct nvme_ctrl ctrl; |
db3cbfff | 102 | struct completion ioq_wait; |
87ad72a5 CH |
103 | |
104 | /* shadow doorbell buffer support: */ | |
f9f38e33 HK |
105 | u32 *dbbuf_dbs; |
106 | dma_addr_t dbbuf_dbs_dma_addr; | |
107 | u32 *dbbuf_eis; | |
108 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
109 | |
110 | /* host memory buffer support: */ | |
111 | u64 host_mem_size; | |
112 | u32 nr_host_mem_descs; | |
4033f35d | 113 | dma_addr_t host_mem_descs_dma; |
87ad72a5 CH |
114 | struct nvme_host_mem_buf_desc *host_mem_descs; |
115 | void **host_mem_desc_bufs; | |
4d115420 | 116 | }; |
1fa6aead | 117 | |
b27c1e68 | 118 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
119 | { | |
120 | int n = 0, ret; | |
121 | ||
122 | ret = kstrtoint(val, 10, &n); | |
123 | if (ret != 0 || n < 2) | |
124 | return -EINVAL; | |
125 | ||
126 | return param_set_int(val, kp); | |
127 | } | |
128 | ||
f9f38e33 HK |
129 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
130 | { | |
131 | return qid * 2 * stride; | |
132 | } | |
133 | ||
134 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
135 | { | |
136 | return (qid * 2 + 1) * stride; | |
137 | } | |
138 | ||
1c63dc66 CH |
139 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
140 | { | |
141 | return container_of(ctrl, struct nvme_dev, ctrl); | |
142 | } | |
143 | ||
b60503ba MW |
144 | /* |
145 | * An NVM Express queue. Each device has at least two (one for admin | |
146 | * commands and one for I/O commands). | |
147 | */ | |
148 | struct nvme_queue { | |
149 | struct device *q_dmadev; | |
091b6092 | 150 | struct nvme_dev *dev; |
b60503ba MW |
151 | spinlock_t q_lock; |
152 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 153 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 154 | volatile struct nvme_completion *cqes; |
42483228 | 155 | struct blk_mq_tags **tags; |
b60503ba MW |
156 | dma_addr_t sq_dma_addr; |
157 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
158 | u32 __iomem *q_db; |
159 | u16 q_depth; | |
6222d172 | 160 | s16 cq_vector; |
b60503ba MW |
161 | u16 sq_tail; |
162 | u16 cq_head; | |
c30341dc | 163 | u16 qid; |
e9539f47 MW |
164 | u8 cq_phase; |
165 | u8 cqe_seen; | |
f9f38e33 HK |
166 | u32 *dbbuf_sq_db; |
167 | u32 *dbbuf_cq_db; | |
168 | u32 *dbbuf_sq_ei; | |
169 | u32 *dbbuf_cq_ei; | |
b60503ba MW |
170 | }; |
171 | ||
71bd150c CH |
172 | /* |
173 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
174 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 175 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
176 | * allocated to store the PRP list. |
177 | */ | |
178 | struct nvme_iod { | |
d49187e9 | 179 | struct nvme_request req; |
f4800d6d | 180 | struct nvme_queue *nvmeq; |
a7a7cbe3 | 181 | bool use_sgl; |
f4800d6d | 182 | int aborted; |
71bd150c | 183 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
184 | int nents; /* Used in scatterlist */ |
185 | int length; /* Of data, in bytes */ | |
186 | dma_addr_t first_dma; | |
bf684057 | 187 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
188 | struct scatterlist *sg; |
189 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
190 | }; |
191 | ||
192 | /* | |
193 | * Check we didin't inadvertently grow the command struct | |
194 | */ | |
195 | static inline void _nvme_check_size(void) | |
196 | { | |
197 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
198 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
199 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
200 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
201 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 202 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 203 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba | 204 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
0add5e8e JT |
205 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); |
206 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); | |
b60503ba | 207 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); |
6ecec745 | 208 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
f9f38e33 HK |
209 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); |
210 | } | |
211 | ||
212 | static inline unsigned int nvme_dbbuf_size(u32 stride) | |
213 | { | |
214 | return ((num_possible_cpus() + 1) * 8 * stride); | |
215 | } | |
216 | ||
217 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
218 | { | |
219 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
220 | ||
221 | if (dev->dbbuf_dbs) | |
222 | return 0; | |
223 | ||
224 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
225 | &dev->dbbuf_dbs_dma_addr, | |
226 | GFP_KERNEL); | |
227 | if (!dev->dbbuf_dbs) | |
228 | return -ENOMEM; | |
229 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
230 | &dev->dbbuf_eis_dma_addr, | |
231 | GFP_KERNEL); | |
232 | if (!dev->dbbuf_eis) { | |
233 | dma_free_coherent(dev->dev, mem_size, | |
234 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
235 | dev->dbbuf_dbs = NULL; | |
236 | return -ENOMEM; | |
237 | } | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
242 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
243 | { | |
244 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
245 | ||
246 | if (dev->dbbuf_dbs) { | |
247 | dma_free_coherent(dev->dev, mem_size, | |
248 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
249 | dev->dbbuf_dbs = NULL; | |
250 | } | |
251 | if (dev->dbbuf_eis) { | |
252 | dma_free_coherent(dev->dev, mem_size, | |
253 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
254 | dev->dbbuf_eis = NULL; | |
255 | } | |
256 | } | |
257 | ||
258 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
259 | struct nvme_queue *nvmeq, int qid) | |
260 | { | |
261 | if (!dev->dbbuf_dbs || !qid) | |
262 | return; | |
263 | ||
264 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
265 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
266 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
267 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
268 | } | |
269 | ||
270 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
271 | { | |
272 | struct nvme_command c; | |
273 | ||
274 | if (!dev->dbbuf_dbs) | |
275 | return; | |
276 | ||
277 | memset(&c, 0, sizeof(c)); | |
278 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
279 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
280 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
281 | ||
282 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 283 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
284 | /* Free memory and continue on */ |
285 | nvme_dbbuf_dma_free(dev); | |
286 | } | |
287 | } | |
288 | ||
289 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
290 | { | |
291 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
292 | } | |
293 | ||
294 | /* Update dbbuf and return true if an MMIO is required */ | |
295 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
296 | volatile u32 *dbbuf_ei) | |
297 | { | |
298 | if (dbbuf_db) { | |
299 | u16 old_value; | |
300 | ||
301 | /* | |
302 | * Ensure that the queue is written before updating | |
303 | * the doorbell in memory | |
304 | */ | |
305 | wmb(); | |
306 | ||
307 | old_value = *dbbuf_db; | |
308 | *dbbuf_db = value; | |
309 | ||
310 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) | |
311 | return false; | |
312 | } | |
313 | ||
314 | return true; | |
b60503ba MW |
315 | } |
316 | ||
ac3dd5bd JA |
317 | /* |
318 | * Max size of iod being embedded in the request payload | |
319 | */ | |
320 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 321 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
322 | |
323 | /* | |
324 | * Will slightly overestimate the number of pages needed. This is OK | |
325 | * as it only leads to a small amount of wasted memory for the lifetime of | |
326 | * the I/O. | |
327 | */ | |
328 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
329 | { | |
5fd4ce1b CH |
330 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
331 | dev->ctrl.page_size); | |
ac3dd5bd JA |
332 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
333 | } | |
334 | ||
a7a7cbe3 CK |
335 | /* |
336 | * Calculates the number of pages needed for the SGL segments. For example a 4k | |
337 | * page can accommodate 256 SGL descriptors. | |
338 | */ | |
339 | static int nvme_pci_npages_sgl(unsigned int num_seg) | |
ac3dd5bd | 340 | { |
a7a7cbe3 | 341 | return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); |
f4800d6d | 342 | } |
ac3dd5bd | 343 | |
a7a7cbe3 CK |
344 | static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, |
345 | unsigned int size, unsigned int nseg, bool use_sgl) | |
f4800d6d | 346 | { |
a7a7cbe3 CK |
347 | size_t alloc_size; |
348 | ||
349 | if (use_sgl) | |
350 | alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); | |
351 | else | |
352 | alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); | |
353 | ||
354 | return alloc_size + sizeof(struct scatterlist) * nseg; | |
f4800d6d | 355 | } |
ac3dd5bd | 356 | |
a7a7cbe3 | 357 | static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) |
f4800d6d | 358 | { |
a7a7cbe3 CK |
359 | unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, |
360 | NVME_INT_BYTES(dev), NVME_INT_PAGES, | |
361 | use_sgl); | |
362 | ||
363 | return sizeof(struct nvme_iod) + alloc_size; | |
ac3dd5bd JA |
364 | } |
365 | ||
a4aea562 MB |
366 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
367 | unsigned int hctx_idx) | |
e85248e5 | 368 | { |
a4aea562 | 369 | struct nvme_dev *dev = data; |
147b27e4 | 370 | struct nvme_queue *nvmeq = &dev->queues[0]; |
a4aea562 | 371 | |
42483228 KB |
372 | WARN_ON(hctx_idx != 0); |
373 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
374 | WARN_ON(nvmeq->tags); | |
375 | ||
a4aea562 | 376 | hctx->driver_data = nvmeq; |
42483228 | 377 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 378 | return 0; |
e85248e5 MW |
379 | } |
380 | ||
4af0e21c KB |
381 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
382 | { | |
383 | struct nvme_queue *nvmeq = hctx->driver_data; | |
384 | ||
385 | nvmeq->tags = NULL; | |
386 | } | |
387 | ||
a4aea562 MB |
388 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
389 | unsigned int hctx_idx) | |
b60503ba | 390 | { |
a4aea562 | 391 | struct nvme_dev *dev = data; |
147b27e4 | 392 | struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; |
a4aea562 | 393 | |
42483228 KB |
394 | if (!nvmeq->tags) |
395 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 396 | |
42483228 | 397 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
398 | hctx->driver_data = nvmeq; |
399 | return 0; | |
b60503ba MW |
400 | } |
401 | ||
d6296d39 CH |
402 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
403 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 404 | { |
d6296d39 | 405 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 406 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a | 407 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
147b27e4 | 408 | struct nvme_queue *nvmeq = &dev->queues[queue_idx]; |
a4aea562 MB |
409 | |
410 | BUG_ON(!nvmeq); | |
f4800d6d | 411 | iod->nvmeq = nvmeq; |
a4aea562 MB |
412 | return 0; |
413 | } | |
414 | ||
dca51e78 CH |
415 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
416 | { | |
417 | struct nvme_dev *dev = set->driver_data; | |
418 | ||
22b55601 KB |
419 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), |
420 | dev->num_vecs > 1 ? 1 /* admin queue */ : 0); | |
dca51e78 CH |
421 | } |
422 | ||
b60503ba | 423 | /** |
adf68f21 | 424 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
425 | * @nvmeq: The queue to use |
426 | * @cmd: The command to send | |
427 | * | |
428 | * Safe to use from interrupt context | |
429 | */ | |
e3f879bf SB |
430 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
431 | struct nvme_command *cmd) | |
b60503ba | 432 | { |
a4aea562 MB |
433 | u16 tail = nvmeq->sq_tail; |
434 | ||
8ffaadf7 JD |
435 | if (nvmeq->sq_cmds_io) |
436 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
437 | else | |
438 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
439 | ||
b60503ba MW |
440 | if (++tail == nvmeq->q_depth) |
441 | tail = 0; | |
f9f38e33 HK |
442 | if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, |
443 | nvmeq->dbbuf_sq_ei)) | |
444 | writel(tail, nvmeq->q_db); | |
b60503ba | 445 | nvmeq->sq_tail = tail; |
b60503ba MW |
446 | } |
447 | ||
a7a7cbe3 | 448 | static void **nvme_pci_iod_list(struct request *req) |
b60503ba | 449 | { |
f4800d6d | 450 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a7a7cbe3 | 451 | return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
452 | } |
453 | ||
955b1b5a MI |
454 | static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) |
455 | { | |
456 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
20469a37 | 457 | int nseg = blk_rq_nr_phys_segments(req); |
955b1b5a MI |
458 | unsigned int avg_seg_size; |
459 | ||
20469a37 KB |
460 | if (nseg == 0) |
461 | return false; | |
462 | ||
463 | avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); | |
955b1b5a MI |
464 | |
465 | if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) | |
466 | return false; | |
467 | if (!iod->nvmeq->qid) | |
468 | return false; | |
469 | if (!sgl_threshold || avg_seg_size < sgl_threshold) | |
470 | return false; | |
471 | return true; | |
472 | } | |
473 | ||
fc17b653 | 474 | static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 475 | { |
f4800d6d | 476 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 477 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 478 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 479 | |
955b1b5a MI |
480 | iod->use_sgl = nvme_pci_use_sgls(dev, rq); |
481 | ||
f4800d6d | 482 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
a7a7cbe3 CK |
483 | size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg, |
484 | iod->use_sgl); | |
485 | ||
486 | iod->sg = kmalloc(alloc_size, GFP_ATOMIC); | |
f4800d6d | 487 | if (!iod->sg) |
fc17b653 | 488 | return BLK_STS_RESOURCE; |
f4800d6d CH |
489 | } else { |
490 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
491 | } |
492 | ||
f4800d6d CH |
493 | iod->aborted = 0; |
494 | iod->npages = -1; | |
495 | iod->nents = 0; | |
496 | iod->length = size; | |
f80ec966 | 497 | |
fc17b653 | 498 | return BLK_STS_OK; |
ac3dd5bd JA |
499 | } |
500 | ||
f4800d6d | 501 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 502 | { |
f4800d6d | 503 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a7a7cbe3 CK |
504 | const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; |
505 | dma_addr_t dma_addr = iod->first_dma, next_dma_addr; | |
506 | ||
eca18b23 | 507 | int i; |
eca18b23 MW |
508 | |
509 | if (iod->npages == 0) | |
a7a7cbe3 CK |
510 | dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], |
511 | dma_addr); | |
512 | ||
eca18b23 | 513 | for (i = 0; i < iod->npages; i++) { |
a7a7cbe3 CK |
514 | void *addr = nvme_pci_iod_list(req)[i]; |
515 | ||
516 | if (iod->use_sgl) { | |
517 | struct nvme_sgl_desc *sg_list = addr; | |
518 | ||
519 | next_dma_addr = | |
520 | le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); | |
521 | } else { | |
522 | __le64 *prp_list = addr; | |
523 | ||
524 | next_dma_addr = le64_to_cpu(prp_list[last_prp]); | |
525 | } | |
526 | ||
527 | dma_pool_free(dev->prp_page_pool, addr, dma_addr); | |
528 | dma_addr = next_dma_addr; | |
eca18b23 | 529 | } |
ac3dd5bd | 530 | |
f4800d6d CH |
531 | if (iod->sg != iod->inline_sg) |
532 | kfree(iod->sg); | |
b4ff9c8d KB |
533 | } |
534 | ||
52b68d7e | 535 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
536 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
537 | { | |
538 | if (be32_to_cpu(pi->ref_tag) == v) | |
539 | pi->ref_tag = cpu_to_be32(p); | |
540 | } | |
541 | ||
542 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
543 | { | |
544 | if (be32_to_cpu(pi->ref_tag) == p) | |
545 | pi->ref_tag = cpu_to_be32(v); | |
546 | } | |
547 | ||
548 | /** | |
549 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
550 | * | |
551 | * The virtual start sector is the one that was originally submitted by the | |
552 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
553 | * start sector may be different. Remap protection information to match the | |
554 | * physical LBA on writes, and back to the original seed on reads. | |
555 | * | |
556 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
557 | */ | |
558 | static void nvme_dif_remap(struct request *req, | |
559 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
560 | { | |
561 | struct nvme_ns *ns = req->rq_disk->private_data; | |
562 | struct bio_integrity_payload *bip; | |
563 | struct t10_pi_tuple *pi; | |
564 | void *p, *pmap; | |
565 | u32 i, nlb, ts, phys, virt; | |
566 | ||
567 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
568 | return; | |
569 | ||
570 | bip = bio_integrity(req->bio); | |
571 | if (!bip) | |
572 | return; | |
573 | ||
574 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
575 | |
576 | p = pmap; | |
577 | virt = bip_get_seed(bip); | |
578 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
579 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 580 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
581 | |
582 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
583 | pi = (struct t10_pi_tuple *)p; | |
584 | dif_swap(phys, virt, pi); | |
585 | p += ts; | |
586 | } | |
587 | kunmap_atomic(pmap); | |
588 | } | |
52b68d7e KB |
589 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
590 | static void nvme_dif_remap(struct request *req, | |
591 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
592 | { | |
593 | } | |
594 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
595 | { | |
596 | } | |
597 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
598 | { | |
599 | } | |
52b68d7e KB |
600 | #endif |
601 | ||
d0877473 KB |
602 | static void nvme_print_sgl(struct scatterlist *sgl, int nents) |
603 | { | |
604 | int i; | |
605 | struct scatterlist *sg; | |
606 | ||
607 | for_each_sg(sgl, sg, nents, i) { | |
608 | dma_addr_t phys = sg_phys(sg); | |
609 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " | |
610 | "dma_address:%pad dma_length:%d\n", | |
611 | i, &phys, sg->offset, sg->length, &sg_dma_address(sg), | |
612 | sg_dma_len(sg)); | |
613 | } | |
614 | } | |
615 | ||
a7a7cbe3 CK |
616 | static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, |
617 | struct request *req, struct nvme_rw_command *cmnd) | |
ff22b54f | 618 | { |
f4800d6d | 619 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 620 | struct dma_pool *pool; |
b131c61d | 621 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 622 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
623 | int dma_len = sg_dma_len(sg); |
624 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 625 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 626 | int offset = dma_addr & (page_size - 1); |
e025344c | 627 | __le64 *prp_list; |
a7a7cbe3 | 628 | void **list = nvme_pci_iod_list(req); |
e025344c | 629 | dma_addr_t prp_dma; |
eca18b23 | 630 | int nprps, i; |
ff22b54f | 631 | |
1d090624 | 632 | length -= (page_size - offset); |
5228b328 JS |
633 | if (length <= 0) { |
634 | iod->first_dma = 0; | |
a7a7cbe3 | 635 | goto done; |
5228b328 | 636 | } |
ff22b54f | 637 | |
1d090624 | 638 | dma_len -= (page_size - offset); |
ff22b54f | 639 | if (dma_len) { |
1d090624 | 640 | dma_addr += (page_size - offset); |
ff22b54f MW |
641 | } else { |
642 | sg = sg_next(sg); | |
643 | dma_addr = sg_dma_address(sg); | |
644 | dma_len = sg_dma_len(sg); | |
645 | } | |
646 | ||
1d090624 | 647 | if (length <= page_size) { |
edd10d33 | 648 | iod->first_dma = dma_addr; |
a7a7cbe3 | 649 | goto done; |
e025344c SMM |
650 | } |
651 | ||
1d090624 | 652 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
653 | if (nprps <= (256 / 8)) { |
654 | pool = dev->prp_small_pool; | |
eca18b23 | 655 | iod->npages = 0; |
99802a7a MW |
656 | } else { |
657 | pool = dev->prp_page_pool; | |
eca18b23 | 658 | iod->npages = 1; |
99802a7a MW |
659 | } |
660 | ||
69d2b571 | 661 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 662 | if (!prp_list) { |
edd10d33 | 663 | iod->first_dma = dma_addr; |
eca18b23 | 664 | iod->npages = -1; |
86eea289 | 665 | return BLK_STS_RESOURCE; |
b77954cb | 666 | } |
eca18b23 MW |
667 | list[0] = prp_list; |
668 | iod->first_dma = prp_dma; | |
e025344c SMM |
669 | i = 0; |
670 | for (;;) { | |
1d090624 | 671 | if (i == page_size >> 3) { |
e025344c | 672 | __le64 *old_prp_list = prp_list; |
69d2b571 | 673 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 674 | if (!prp_list) |
86eea289 | 675 | return BLK_STS_RESOURCE; |
eca18b23 | 676 | list[iod->npages++] = prp_list; |
7523d834 MW |
677 | prp_list[0] = old_prp_list[i - 1]; |
678 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
679 | i = 1; | |
e025344c SMM |
680 | } |
681 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
682 | dma_len -= page_size; |
683 | dma_addr += page_size; | |
684 | length -= page_size; | |
e025344c SMM |
685 | if (length <= 0) |
686 | break; | |
687 | if (dma_len > 0) | |
688 | continue; | |
86eea289 KB |
689 | if (unlikely(dma_len < 0)) |
690 | goto bad_sgl; | |
e025344c SMM |
691 | sg = sg_next(sg); |
692 | dma_addr = sg_dma_address(sg); | |
693 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
694 | } |
695 | ||
a7a7cbe3 CK |
696 | done: |
697 | cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
698 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); | |
699 | ||
86eea289 KB |
700 | return BLK_STS_OK; |
701 | ||
702 | bad_sgl: | |
d0877473 KB |
703 | WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), |
704 | "Invalid SGL for payload:%d nents:%d\n", | |
705 | blk_rq_payload_bytes(req), iod->nents); | |
86eea289 | 706 | return BLK_STS_IOERR; |
ff22b54f MW |
707 | } |
708 | ||
a7a7cbe3 CK |
709 | static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, |
710 | struct scatterlist *sg) | |
711 | { | |
712 | sge->addr = cpu_to_le64(sg_dma_address(sg)); | |
713 | sge->length = cpu_to_le32(sg_dma_len(sg)); | |
714 | sge->type = NVME_SGL_FMT_DATA_DESC << 4; | |
715 | } | |
716 | ||
717 | static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, | |
718 | dma_addr_t dma_addr, int entries) | |
719 | { | |
720 | sge->addr = cpu_to_le64(dma_addr); | |
721 | if (entries < SGES_PER_PAGE) { | |
722 | sge->length = cpu_to_le32(entries * sizeof(*sge)); | |
723 | sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; | |
724 | } else { | |
725 | sge->length = cpu_to_le32(PAGE_SIZE); | |
726 | sge->type = NVME_SGL_FMT_SEG_DESC << 4; | |
727 | } | |
728 | } | |
729 | ||
730 | static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, | |
b0f2853b | 731 | struct request *req, struct nvme_rw_command *cmd, int entries) |
a7a7cbe3 CK |
732 | { |
733 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 CK |
734 | struct dma_pool *pool; |
735 | struct nvme_sgl_desc *sg_list; | |
736 | struct scatterlist *sg = iod->sg; | |
a7a7cbe3 | 737 | dma_addr_t sgl_dma; |
b0f2853b | 738 | int i = 0; |
a7a7cbe3 | 739 | |
a7a7cbe3 CK |
740 | /* setting the transfer type as SGL */ |
741 | cmd->flags = NVME_CMD_SGL_METABUF; | |
742 | ||
b0f2853b | 743 | if (entries == 1) { |
a7a7cbe3 CK |
744 | nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); |
745 | return BLK_STS_OK; | |
746 | } | |
747 | ||
748 | if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { | |
749 | pool = dev->prp_small_pool; | |
750 | iod->npages = 0; | |
751 | } else { | |
752 | pool = dev->prp_page_pool; | |
753 | iod->npages = 1; | |
754 | } | |
755 | ||
756 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
757 | if (!sg_list) { | |
758 | iod->npages = -1; | |
759 | return BLK_STS_RESOURCE; | |
760 | } | |
761 | ||
762 | nvme_pci_iod_list(req)[0] = sg_list; | |
763 | iod->first_dma = sgl_dma; | |
764 | ||
765 | nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); | |
766 | ||
767 | do { | |
768 | if (i == SGES_PER_PAGE) { | |
769 | struct nvme_sgl_desc *old_sg_desc = sg_list; | |
770 | struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; | |
771 | ||
772 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
773 | if (!sg_list) | |
774 | return BLK_STS_RESOURCE; | |
775 | ||
776 | i = 0; | |
777 | nvme_pci_iod_list(req)[iod->npages++] = sg_list; | |
778 | sg_list[i++] = *link; | |
779 | nvme_pci_sgl_set_seg(link, sgl_dma, entries); | |
780 | } | |
781 | ||
782 | nvme_pci_sgl_set_data(&sg_list[i++], sg); | |
a7a7cbe3 | 783 | sg = sg_next(sg); |
b0f2853b | 784 | } while (--entries > 0); |
a7a7cbe3 | 785 | |
a7a7cbe3 CK |
786 | return BLK_STS_OK; |
787 | } | |
788 | ||
fc17b653 | 789 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 790 | struct nvme_command *cmnd) |
d29ec824 | 791 | { |
f4800d6d | 792 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
793 | struct request_queue *q = req->q; |
794 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
795 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
fc17b653 | 796 | blk_status_t ret = BLK_STS_IOERR; |
b0f2853b | 797 | int nr_mapped; |
d29ec824 | 798 | |
f9d03f96 | 799 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
800 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
801 | if (!iod->nents) | |
802 | goto out; | |
d29ec824 | 803 | |
fc17b653 | 804 | ret = BLK_STS_RESOURCE; |
b0f2853b CH |
805 | nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
806 | DMA_ATTR_NO_WARN); | |
807 | if (!nr_mapped) | |
ba1ca37e | 808 | goto out; |
d29ec824 | 809 | |
955b1b5a | 810 | if (iod->use_sgl) |
b0f2853b | 811 | ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); |
a7a7cbe3 CK |
812 | else |
813 | ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); | |
814 | ||
86eea289 | 815 | if (ret != BLK_STS_OK) |
ba1ca37e | 816 | goto out_unmap; |
0e5e4f0e | 817 | |
fc17b653 | 818 | ret = BLK_STS_IOERR; |
ba1ca37e CH |
819 | if (blk_integrity_rq(req)) { |
820 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
821 | goto out_unmap; | |
0e5e4f0e | 822 | |
bf684057 CH |
823 | sg_init_table(&iod->meta_sg, 1); |
824 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 825 | goto out_unmap; |
0e5e4f0e | 826 | |
b5d8af5b | 827 | if (req_op(req) == REQ_OP_WRITE) |
ba1ca37e | 828 | nvme_dif_remap(req, nvme_dif_prep); |
0e5e4f0e | 829 | |
bf684057 | 830 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 831 | goto out_unmap; |
d29ec824 | 832 | } |
00df5cb4 | 833 | |
ba1ca37e | 834 | if (blk_integrity_rq(req)) |
bf684057 | 835 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
fc17b653 | 836 | return BLK_STS_OK; |
00df5cb4 | 837 | |
ba1ca37e CH |
838 | out_unmap: |
839 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
840 | out: | |
841 | return ret; | |
00df5cb4 MW |
842 | } |
843 | ||
f4800d6d | 844 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 845 | { |
f4800d6d | 846 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
847 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
848 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
849 | ||
850 | if (iod->nents) { | |
851 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
852 | if (blk_integrity_rq(req)) { | |
b5d8af5b | 853 | if (req_op(req) == REQ_OP_READ) |
d4f6c3ab | 854 | nvme_dif_remap(req, nvme_dif_complete); |
bf684057 | 855 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 856 | } |
e19b127f | 857 | } |
e1e5e564 | 858 | |
f9d03f96 | 859 | nvme_cleanup_cmd(req); |
f4800d6d | 860 | nvme_free_iod(dev, req); |
d4f6c3ab | 861 | } |
b60503ba | 862 | |
d29ec824 CH |
863 | /* |
864 | * NOTE: ns is NULL when called on the admin queue. | |
865 | */ | |
fc17b653 | 866 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
a4aea562 | 867 | const struct blk_mq_queue_data *bd) |
edd10d33 | 868 | { |
a4aea562 MB |
869 | struct nvme_ns *ns = hctx->queue->queuedata; |
870 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 871 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 872 | struct request *req = bd->rq; |
ba1ca37e | 873 | struct nvme_command cmnd; |
ebe6d874 | 874 | blk_status_t ret; |
e1e5e564 | 875 | |
f9d03f96 | 876 | ret = nvme_setup_cmd(ns, req, &cmnd); |
fc17b653 | 877 | if (ret) |
f4800d6d | 878 | return ret; |
a4aea562 | 879 | |
b131c61d | 880 | ret = nvme_init_iod(req, dev); |
fc17b653 | 881 | if (ret) |
f9d03f96 | 882 | goto out_free_cmd; |
a4aea562 | 883 | |
fc17b653 | 884 | if (blk_rq_nr_phys_segments(req)) { |
b131c61d | 885 | ret = nvme_map_data(dev, req, &cmnd); |
fc17b653 CH |
886 | if (ret) |
887 | goto out_cleanup_iod; | |
888 | } | |
a4aea562 | 889 | |
aae239e1 | 890 | blk_mq_start_request(req); |
a4aea562 | 891 | |
ba1ca37e | 892 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 893 | if (unlikely(nvmeq->cq_vector < 0)) { |
fc17b653 | 894 | ret = BLK_STS_IOERR; |
ae1fba20 | 895 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 896 | goto out_cleanup_iod; |
ae1fba20 | 897 | } |
ba1ca37e | 898 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
899 | nvme_process_cq(nvmeq); |
900 | spin_unlock_irq(&nvmeq->q_lock); | |
fc17b653 | 901 | return BLK_STS_OK; |
f9d03f96 | 902 | out_cleanup_iod: |
f4800d6d | 903 | nvme_free_iod(dev, req); |
f9d03f96 CH |
904 | out_free_cmd: |
905 | nvme_cleanup_cmd(req); | |
ba1ca37e | 906 | return ret; |
b60503ba | 907 | } |
e1e5e564 | 908 | |
77f02a7a | 909 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 910 | { |
f4800d6d | 911 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 | 912 | |
77f02a7a CH |
913 | nvme_unmap_data(iod->nvmeq->dev, req); |
914 | nvme_complete_rq(req); | |
b60503ba MW |
915 | } |
916 | ||
d783e0bd MR |
917 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
918 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
919 | u16 phase) | |
920 | { | |
921 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
922 | } | |
923 | ||
eb281c82 | 924 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
b60503ba | 925 | { |
eb281c82 | 926 | u16 head = nvmeq->cq_head; |
adf68f21 | 927 | |
eb281c82 SG |
928 | if (likely(nvmeq->cq_vector >= 0)) { |
929 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, | |
930 | nvmeq->dbbuf_cq_ei)) | |
931 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
932 | } | |
933 | } | |
aae239e1 | 934 | |
83a12fb7 SG |
935 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, |
936 | struct nvme_completion *cqe) | |
937 | { | |
938 | struct request *req; | |
adf68f21 | 939 | |
83a12fb7 SG |
940 | if (unlikely(cqe->command_id >= nvmeq->q_depth)) { |
941 | dev_warn(nvmeq->dev->ctrl.device, | |
942 | "invalid id %d completed on queue %d\n", | |
943 | cqe->command_id, le16_to_cpu(cqe->sq_id)); | |
944 | return; | |
b60503ba MW |
945 | } |
946 | ||
83a12fb7 SG |
947 | /* |
948 | * AEN requests are special as they don't time out and can | |
949 | * survive any kind of queue freeze and often don't respond to | |
950 | * aborts. We don't even bother to allocate a struct request | |
951 | * for them but rather special case them here. | |
952 | */ | |
953 | if (unlikely(nvmeq->qid == 0 && | |
38dabe21 | 954 | cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { |
83a12fb7 SG |
955 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
956 | cqe->status, &cqe->result); | |
a0fa9647 | 957 | return; |
83a12fb7 | 958 | } |
b60503ba | 959 | |
e9d8a0fd | 960 | nvmeq->cqe_seen = 1; |
83a12fb7 SG |
961 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); |
962 | nvme_end_request(req, cqe->status, cqe->result); | |
963 | } | |
b60503ba | 964 | |
920d13a8 SG |
965 | static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, |
966 | struct nvme_completion *cqe) | |
b60503ba | 967 | { |
920d13a8 SG |
968 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
969 | *cqe = nvmeq->cqes[nvmeq->cq_head]; | |
adf68f21 | 970 | |
920d13a8 SG |
971 | if (++nvmeq->cq_head == nvmeq->q_depth) { |
972 | nvmeq->cq_head = 0; | |
973 | nvmeq->cq_phase = !nvmeq->cq_phase; | |
b60503ba | 974 | } |
920d13a8 | 975 | return true; |
b60503ba | 976 | } |
920d13a8 | 977 | return false; |
a0fa9647 JA |
978 | } |
979 | ||
980 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
981 | { | |
920d13a8 SG |
982 | struct nvme_completion cqe; |
983 | int consumed = 0; | |
b60503ba | 984 | |
920d13a8 SG |
985 | while (nvme_read_cqe(nvmeq, &cqe)) { |
986 | nvme_handle_cqe(nvmeq, &cqe); | |
987 | consumed++; | |
920d13a8 | 988 | } |
eb281c82 | 989 | |
e9d8a0fd | 990 | if (consumed) |
920d13a8 | 991 | nvme_ring_cq_doorbell(nvmeq); |
b60503ba MW |
992 | } |
993 | ||
994 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
995 | { |
996 | irqreturn_t result; | |
997 | struct nvme_queue *nvmeq = data; | |
998 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
999 | nvme_process_cq(nvmeq); |
1000 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
1001 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
1002 | spin_unlock(&nvmeq->q_lock); |
1003 | return result; | |
1004 | } | |
1005 | ||
1006 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
1007 | { | |
1008 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
1009 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
1010 | return IRQ_WAKE_THREAD; | |
1011 | return IRQ_NONE; | |
58ffacb5 MW |
1012 | } |
1013 | ||
7776db1c | 1014 | static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) |
a0fa9647 | 1015 | { |
442e19b7 SG |
1016 | struct nvme_completion cqe; |
1017 | int found = 0, consumed = 0; | |
a0fa9647 | 1018 | |
442e19b7 SG |
1019 | if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
1020 | return 0; | |
a0fa9647 | 1021 | |
442e19b7 SG |
1022 | spin_lock_irq(&nvmeq->q_lock); |
1023 | while (nvme_read_cqe(nvmeq, &cqe)) { | |
1024 | nvme_handle_cqe(nvmeq, &cqe); | |
1025 | consumed++; | |
1026 | ||
1027 | if (tag == cqe.command_id) { | |
1028 | found = 1; | |
1029 | break; | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | if (consumed) | |
1034 | nvme_ring_cq_doorbell(nvmeq); | |
1035 | spin_unlock_irq(&nvmeq->q_lock); | |
1036 | ||
1037 | return found; | |
a0fa9647 JA |
1038 | } |
1039 | ||
7776db1c KB |
1040 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
1041 | { | |
1042 | struct nvme_queue *nvmeq = hctx->driver_data; | |
1043 | ||
1044 | return __nvme_poll(nvmeq, tag); | |
1045 | } | |
1046 | ||
ad22c355 | 1047 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) |
b60503ba | 1048 | { |
f866fc42 | 1049 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
147b27e4 | 1050 | struct nvme_queue *nvmeq = &dev->queues[0]; |
a4aea562 | 1051 | struct nvme_command c; |
b60503ba | 1052 | |
a4aea562 MB |
1053 | memset(&c, 0, sizeof(c)); |
1054 | c.common.opcode = nvme_admin_async_event; | |
ad22c355 | 1055 | c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; |
3c0cf138 | 1056 | |
9396dec9 | 1057 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 1058 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 1059 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
1060 | } |
1061 | ||
b60503ba | 1062 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 1063 | { |
b60503ba MW |
1064 | struct nvme_command c; |
1065 | ||
1066 | memset(&c, 0, sizeof(c)); | |
1067 | c.delete_queue.opcode = opcode; | |
1068 | c.delete_queue.qid = cpu_to_le16(id); | |
1069 | ||
1c63dc66 | 1070 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1071 | } |
1072 | ||
b60503ba MW |
1073 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
1074 | struct nvme_queue *nvmeq) | |
1075 | { | |
b60503ba MW |
1076 | struct nvme_command c; |
1077 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1078 | ||
d29ec824 | 1079 | /* |
16772ae6 | 1080 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1081 | * is attached to the request. |
1082 | */ | |
b60503ba MW |
1083 | memset(&c, 0, sizeof(c)); |
1084 | c.create_cq.opcode = nvme_admin_create_cq; | |
1085 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1086 | c.create_cq.cqid = cpu_to_le16(qid); | |
1087 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1088 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1089 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1090 | ||
1c63dc66 | 1091 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1092 | } |
1093 | ||
1094 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1095 | struct nvme_queue *nvmeq) | |
1096 | { | |
b60503ba | 1097 | struct nvme_command c; |
81c1cd98 | 1098 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 1099 | |
d29ec824 | 1100 | /* |
16772ae6 | 1101 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1102 | * is attached to the request. |
1103 | */ | |
b60503ba MW |
1104 | memset(&c, 0, sizeof(c)); |
1105 | c.create_sq.opcode = nvme_admin_create_sq; | |
1106 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1107 | c.create_sq.sqid = cpu_to_le16(qid); | |
1108 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1109 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1110 | c.create_sq.cqid = cpu_to_le16(qid); | |
1111 | ||
1c63dc66 | 1112 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1113 | } |
1114 | ||
1115 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1116 | { | |
1117 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1118 | } | |
1119 | ||
1120 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1121 | { | |
1122 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1123 | } | |
1124 | ||
2a842aca | 1125 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 1126 | { |
f4800d6d CH |
1127 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1128 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 1129 | |
27fa9bc5 CH |
1130 | dev_warn(nvmeq->dev->ctrl.device, |
1131 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 1132 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 1133 | blk_mq_free_request(req); |
bc5fc7e4 MW |
1134 | } |
1135 | ||
b2a0eb1a KB |
1136 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1137 | { | |
1138 | ||
1139 | /* If true, indicates loss of adapter communication, possibly by a | |
1140 | * NVMe Subsystem reset. | |
1141 | */ | |
1142 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1143 | ||
ad70062c JW |
1144 | /* If there is a reset/reinit ongoing, we shouldn't reset again. */ |
1145 | switch (dev->ctrl.state) { | |
1146 | case NVME_CTRL_RESETTING: | |
ad6a0a52 | 1147 | case NVME_CTRL_CONNECTING: |
b2a0eb1a | 1148 | return false; |
ad70062c JW |
1149 | default: |
1150 | break; | |
1151 | } | |
b2a0eb1a KB |
1152 | |
1153 | /* We shouldn't reset unless the controller is on fatal error state | |
1154 | * _or_ if we lost the communication with it. | |
1155 | */ | |
1156 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1157 | return false; | |
1158 | ||
b2a0eb1a KB |
1159 | return true; |
1160 | } | |
1161 | ||
1162 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
1163 | { | |
1164 | /* Read a config register to help see what died. */ | |
1165 | u16 pci_status; | |
1166 | int result; | |
1167 | ||
1168 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1169 | &pci_status); | |
1170 | if (result == PCIBIOS_SUCCESSFUL) | |
1171 | dev_warn(dev->ctrl.device, | |
1172 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1173 | csts, pci_status); | |
1174 | else | |
1175 | dev_warn(dev->ctrl.device, | |
1176 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1177 | csts, result); | |
1178 | } | |
1179 | ||
31c7c7d2 | 1180 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 1181 | { |
f4800d6d CH |
1182 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1183 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 1184 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 1185 | struct request *abort_req; |
a4aea562 | 1186 | struct nvme_command cmd; |
b2a0eb1a KB |
1187 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
1188 | ||
651438bb WX |
1189 | /* If PCI error recovery process is happening, we cannot reset or |
1190 | * the recovery mechanism will surely fail. | |
1191 | */ | |
1192 | mb(); | |
1193 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1194 | return BLK_EH_RESET_TIMER; | |
1195 | ||
b2a0eb1a KB |
1196 | /* |
1197 | * Reset immediately if the controller is failed | |
1198 | */ | |
1199 | if (nvme_should_reset(dev, csts)) { | |
1200 | nvme_warn_reset(dev, csts); | |
1201 | nvme_dev_disable(dev, false); | |
d86c4d8e | 1202 | nvme_reset_ctrl(&dev->ctrl); |
b2a0eb1a KB |
1203 | return BLK_EH_HANDLED; |
1204 | } | |
c30341dc | 1205 | |
7776db1c KB |
1206 | /* |
1207 | * Did we miss an interrupt? | |
1208 | */ | |
1209 | if (__nvme_poll(nvmeq, req->tag)) { | |
1210 | dev_warn(dev->ctrl.device, | |
1211 | "I/O %d QID %d timeout, completion polled\n", | |
1212 | req->tag, nvmeq->qid); | |
1213 | return BLK_EH_HANDLED; | |
1214 | } | |
1215 | ||
31c7c7d2 | 1216 | /* |
fd634f41 CH |
1217 | * Shutdown immediately if controller times out while starting. The |
1218 | * reset work will see the pci device disabled when it gets the forced | |
1219 | * cancellation error. All outstanding requests are completed on | |
1220 | * shutdown, so we return BLK_EH_HANDLED. | |
1221 | */ | |
4244140d KB |
1222 | switch (dev->ctrl.state) { |
1223 | case NVME_CTRL_CONNECTING: | |
1224 | case NVME_CTRL_RESETTING: | |
1b3c47c1 | 1225 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
1226 | "I/O %d QID %d timeout, disable controller\n", |
1227 | req->tag, nvmeq->qid); | |
a5cdb68c | 1228 | nvme_dev_disable(dev, false); |
27fa9bc5 | 1229 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
fd634f41 | 1230 | return BLK_EH_HANDLED; |
4244140d KB |
1231 | default: |
1232 | break; | |
c30341dc KB |
1233 | } |
1234 | ||
fd634f41 CH |
1235 | /* |
1236 | * Shutdown the controller immediately and schedule a reset if the | |
1237 | * command was already aborted once before and still hasn't been | |
1238 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1239 | */ |
f4800d6d | 1240 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1241 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1242 | "I/O %d QID %d timeout, reset controller\n", |
1243 | req->tag, nvmeq->qid); | |
a5cdb68c | 1244 | nvme_dev_disable(dev, false); |
d86c4d8e | 1245 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1246 | |
e1569a16 KB |
1247 | /* |
1248 | * Mark the request as handled, since the inline shutdown | |
1249 | * forces all outstanding requests to complete. | |
1250 | */ | |
27fa9bc5 | 1251 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
e1569a16 | 1252 | return BLK_EH_HANDLED; |
c30341dc | 1253 | } |
c30341dc | 1254 | |
e7a2a87d | 1255 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1256 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1257 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1258 | } |
7bf7d778 | 1259 | iod->aborted = 1; |
a4aea562 | 1260 | |
c30341dc KB |
1261 | memset(&cmd, 0, sizeof(cmd)); |
1262 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1263 | cmd.abort.cid = req->tag; |
c30341dc | 1264 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1265 | |
1b3c47c1 SG |
1266 | dev_warn(nvmeq->dev->ctrl.device, |
1267 | "I/O %d QID %d timeout, aborting\n", | |
1268 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1269 | |
1270 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1271 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1272 | if (IS_ERR(abort_req)) { |
1273 | atomic_inc(&dev->ctrl.abort_limit); | |
1274 | return BLK_EH_RESET_TIMER; | |
1275 | } | |
1276 | ||
1277 | abort_req->timeout = ADMIN_TIMEOUT; | |
1278 | abort_req->end_io_data = NULL; | |
1279 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1280 | |
31c7c7d2 CH |
1281 | /* |
1282 | * The aborted req will be completed on receiving the abort req. | |
1283 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1284 | * as the device then is in a faulty state. | |
1285 | */ | |
1286 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1287 | } |
1288 | ||
a4aea562 MB |
1289 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1290 | { | |
9e866774 MW |
1291 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1292 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1293 | if (nvmeq->sq_cmds) |
1294 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 | 1295 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
9e866774 MW |
1296 | } |
1297 | ||
a1a5ef99 | 1298 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1299 | { |
1300 | int i; | |
1301 | ||
d858e5f0 | 1302 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
d858e5f0 | 1303 | dev->ctrl.queue_count--; |
147b27e4 | 1304 | nvme_free_queue(&dev->queues[i]); |
121c7ad4 | 1305 | } |
22404274 KB |
1306 | } |
1307 | ||
4d115420 KB |
1308 | /** |
1309 | * nvme_suspend_queue - put queue into suspended state | |
1310 | * @nvmeq - queue to suspend | |
4d115420 KB |
1311 | */ |
1312 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1313 | { |
2b25d981 | 1314 | int vector; |
b60503ba | 1315 | |
a09115b2 | 1316 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1317 | if (nvmeq->cq_vector == -1) { |
1318 | spin_unlock_irq(&nvmeq->q_lock); | |
1319 | return 1; | |
1320 | } | |
0ff199cb | 1321 | vector = nvmeq->cq_vector; |
42f61420 | 1322 | nvmeq->dev->online_queues--; |
2b25d981 | 1323 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1324 | spin_unlock_irq(&nvmeq->q_lock); |
1325 | ||
1c63dc66 | 1326 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
c81545f9 | 1327 | blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1328 | |
0ff199cb | 1329 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); |
b60503ba | 1330 | |
4d115420 KB |
1331 | return 0; |
1332 | } | |
b60503ba | 1333 | |
a5cdb68c | 1334 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1335 | { |
147b27e4 | 1336 | struct nvme_queue *nvmeq = &dev->queues[0]; |
4d115420 | 1337 | |
a5cdb68c KB |
1338 | if (shutdown) |
1339 | nvme_shutdown_ctrl(&dev->ctrl); | |
1340 | else | |
20d0dfe6 | 1341 | nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
07836e65 KB |
1342 | |
1343 | spin_lock_irq(&nvmeq->q_lock); | |
1344 | nvme_process_cq(nvmeq); | |
1345 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1346 | } |
1347 | ||
8ffaadf7 JD |
1348 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1349 | int entry_size) | |
1350 | { | |
1351 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1352 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1353 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1354 | |
1355 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1356 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1357 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1358 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1359 | |
1360 | /* | |
1361 | * Ensure the reduced q_depth is above some threshold where it | |
1362 | * would be better to map queues in system memory with the | |
1363 | * original depth | |
1364 | */ | |
1365 | if (q_depth < 64) | |
1366 | return -ENOMEM; | |
1367 | } | |
1368 | ||
1369 | return q_depth; | |
1370 | } | |
1371 | ||
1372 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1373 | int qid, int depth) | |
1374 | { | |
815c6704 KB |
1375 | /* CMB SQEs will be mapped before creation */ |
1376 | if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) | |
1377 | return 0; | |
8ffaadf7 | 1378 | |
815c6704 KB |
1379 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), |
1380 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1381 | if (!nvmeq->sq_cmds) | |
1382 | return -ENOMEM; | |
8ffaadf7 JD |
1383 | return 0; |
1384 | } | |
1385 | ||
a6ff7262 | 1386 | static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) |
b60503ba | 1387 | { |
147b27e4 | 1388 | struct nvme_queue *nvmeq = &dev->queues[qid]; |
b60503ba | 1389 | |
62314e40 KB |
1390 | if (dev->ctrl.queue_count > qid) |
1391 | return 0; | |
b60503ba | 1392 | |
e75ec752 | 1393 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1394 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1395 | if (!nvmeq->cqes) |
1396 | goto free_nvmeq; | |
b60503ba | 1397 | |
8ffaadf7 | 1398 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1399 | goto free_cqdma; |
1400 | ||
e75ec752 | 1401 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1402 | nvmeq->dev = dev; |
b60503ba MW |
1403 | spin_lock_init(&nvmeq->q_lock); |
1404 | nvmeq->cq_head = 0; | |
82123460 | 1405 | nvmeq->cq_phase = 1; |
b80d5ccc | 1406 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1407 | nvmeq->q_depth = depth; |
c30341dc | 1408 | nvmeq->qid = qid; |
758dd7fd | 1409 | nvmeq->cq_vector = -1; |
d858e5f0 | 1410 | dev->ctrl.queue_count++; |
36a7e993 | 1411 | |
147b27e4 | 1412 | return 0; |
b60503ba MW |
1413 | |
1414 | free_cqdma: | |
e75ec752 | 1415 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1416 | nvmeq->cq_dma_addr); |
1417 | free_nvmeq: | |
147b27e4 | 1418 | return -ENOMEM; |
b60503ba MW |
1419 | } |
1420 | ||
dca51e78 | 1421 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1422 | { |
0ff199cb CH |
1423 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1424 | int nr = nvmeq->dev->ctrl.instance; | |
1425 | ||
1426 | if (use_threaded_interrupts) { | |
1427 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1428 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1429 | } else { | |
1430 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1431 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1432 | } | |
3001082c MW |
1433 | } |
1434 | ||
22404274 | 1435 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1436 | { |
22404274 | 1437 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1438 | |
7be50e93 | 1439 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1440 | nvmeq->sq_tail = 0; |
1441 | nvmeq->cq_head = 0; | |
1442 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1443 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1444 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1445 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1446 | dev->online_queues++; |
7be50e93 | 1447 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1448 | } |
1449 | ||
1450 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1451 | { | |
1452 | struct nvme_dev *dev = nvmeq->dev; | |
1453 | int result; | |
3f85d50b | 1454 | |
815c6704 KB |
1455 | if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { |
1456 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), | |
1457 | dev->ctrl.page_size); | |
1458 | nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; | |
1459 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1460 | } | |
1461 | ||
22b55601 KB |
1462 | /* |
1463 | * A queue's vector matches the queue identifier unless the controller | |
1464 | * has only one vector available. | |
1465 | */ | |
1466 | nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid; | |
b60503ba MW |
1467 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1468 | if (result < 0) | |
f25a2dfc | 1469 | goto release_vector; |
b60503ba MW |
1470 | |
1471 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1472 | if (result < 0) | |
1473 | goto release_cq; | |
1474 | ||
161b8be2 | 1475 | nvme_init_queue(nvmeq, qid); |
dca51e78 | 1476 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1477 | if (result < 0) |
1478 | goto release_sq; | |
1479 | ||
22404274 | 1480 | return result; |
b60503ba MW |
1481 | |
1482 | release_sq: | |
f25a2dfc | 1483 | dev->online_queues--; |
b60503ba MW |
1484 | adapter_delete_sq(dev, qid); |
1485 | release_cq: | |
1486 | adapter_delete_cq(dev, qid); | |
f25a2dfc JW |
1487 | release_vector: |
1488 | nvmeq->cq_vector = -1; | |
22404274 | 1489 | return result; |
b60503ba MW |
1490 | } |
1491 | ||
f363b089 | 1492 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1493 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1494 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1495 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1496 | .exit_hctx = nvme_admin_exit_hctx, |
0350815a | 1497 | .init_request = nvme_init_request, |
a4aea562 MB |
1498 | .timeout = nvme_timeout, |
1499 | }; | |
1500 | ||
f363b089 | 1501 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1502 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1503 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1504 | .init_hctx = nvme_init_hctx, |
1505 | .init_request = nvme_init_request, | |
dca51e78 | 1506 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1507 | .timeout = nvme_timeout, |
a0fa9647 | 1508 | .poll = nvme_poll, |
a4aea562 MB |
1509 | }; |
1510 | ||
ea191d2f KB |
1511 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1512 | { | |
1c63dc66 | 1513 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1514 | /* |
1515 | * If the controller was reset during removal, it's possible | |
1516 | * user requests may be waiting on a stopped queue. Start the | |
1517 | * queue to flush these to completion. | |
1518 | */ | |
c81545f9 | 1519 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
1c63dc66 | 1520 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1521 | blk_mq_free_tag_set(&dev->admin_tagset); |
1522 | } | |
1523 | } | |
1524 | ||
a4aea562 MB |
1525 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1526 | { | |
1c63dc66 | 1527 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1528 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1529 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c | 1530 | |
38dabe21 | 1531 | dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; |
a4aea562 | 1532 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1533 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
a7a7cbe3 | 1534 | dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); |
d3484991 | 1535 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1536 | dev->admin_tagset.driver_data = dev; |
1537 | ||
1538 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1539 | return -ENOMEM; | |
34b6c231 | 1540 | dev->ctrl.admin_tagset = &dev->admin_tagset; |
a4aea562 | 1541 | |
1c63dc66 CH |
1542 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1543 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1544 | blk_mq_free_tag_set(&dev->admin_tagset); |
1545 | return -ENOMEM; | |
1546 | } | |
1c63dc66 | 1547 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1548 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1549 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1550 | return -ENODEV; |
1551 | } | |
0fb59cbc | 1552 | } else |
c81545f9 | 1553 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1554 | |
1555 | return 0; | |
1556 | } | |
1557 | ||
97f6ef64 XY |
1558 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1559 | { | |
1560 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1561 | } | |
1562 | ||
1563 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1564 | { | |
1565 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1566 | ||
1567 | if (size <= dev->bar_mapped_size) | |
1568 | return 0; | |
1569 | if (size > pci_resource_len(pdev, 0)) | |
1570 | return -ENOMEM; | |
1571 | if (dev->bar) | |
1572 | iounmap(dev->bar); | |
1573 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1574 | if (!dev->bar) { | |
1575 | dev->bar_mapped_size = 0; | |
1576 | return -ENOMEM; | |
1577 | } | |
1578 | dev->bar_mapped_size = size; | |
1579 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1580 | ||
1581 | return 0; | |
1582 | } | |
1583 | ||
01ad0990 | 1584 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1585 | { |
ba47e386 | 1586 | int result; |
b60503ba MW |
1587 | u32 aqa; |
1588 | struct nvme_queue *nvmeq; | |
1589 | ||
97f6ef64 XY |
1590 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1591 | if (result < 0) | |
1592 | return result; | |
1593 | ||
8ef2074d | 1594 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
20d0dfe6 | 1595 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
dfbac8c7 | 1596 | |
7a67cbea CH |
1597 | if (dev->subsystem && |
1598 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1599 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1600 | |
20d0dfe6 | 1601 | result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
ba47e386 MW |
1602 | if (result < 0) |
1603 | return result; | |
b60503ba | 1604 | |
a6ff7262 | 1605 | result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
147b27e4 SG |
1606 | if (result) |
1607 | return result; | |
b60503ba | 1608 | |
147b27e4 | 1609 | nvmeq = &dev->queues[0]; |
b60503ba MW |
1610 | aqa = nvmeq->q_depth - 1; |
1611 | aqa |= aqa << 16; | |
1612 | ||
7a67cbea CH |
1613 | writel(aqa, dev->bar + NVME_REG_AQA); |
1614 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1615 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1616 | |
20d0dfe6 | 1617 | result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); |
025c557a | 1618 | if (result) |
d4875622 | 1619 | return result; |
a4aea562 | 1620 | |
2b25d981 | 1621 | nvmeq->cq_vector = 0; |
161b8be2 | 1622 | nvme_init_queue(nvmeq, 0); |
dca51e78 | 1623 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1624 | if (result) { |
1625 | nvmeq->cq_vector = -1; | |
d4875622 | 1626 | return result; |
758dd7fd | 1627 | } |
025c557a | 1628 | |
b60503ba MW |
1629 | return result; |
1630 | } | |
1631 | ||
749941f2 | 1632 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1633 | { |
949928c1 | 1634 | unsigned i, max; |
749941f2 | 1635 | int ret = 0; |
42f61420 | 1636 | |
d858e5f0 | 1637 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
a6ff7262 | 1638 | if (nvme_alloc_queue(dev, i, dev->q_depth)) { |
749941f2 | 1639 | ret = -ENOMEM; |
42f61420 | 1640 | break; |
749941f2 CH |
1641 | } |
1642 | } | |
42f61420 | 1643 | |
d858e5f0 | 1644 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
949928c1 | 1645 | for (i = dev->online_queues; i <= max; i++) { |
147b27e4 | 1646 | ret = nvme_create_queue(&dev->queues[i], i); |
d4875622 | 1647 | if (ret) |
42f61420 | 1648 | break; |
27e8166c | 1649 | } |
749941f2 CH |
1650 | |
1651 | /* | |
1652 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
8adb8c14 MI |
1653 | * than the desired amount of queues, and even a controller without |
1654 | * I/O queues can still be used to issue admin commands. This might | |
749941f2 CH |
1655 | * be useful to upgrade a buggy firmware for example. |
1656 | */ | |
1657 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1658 | } |
1659 | ||
202021c1 SB |
1660 | static ssize_t nvme_cmb_show(struct device *dev, |
1661 | struct device_attribute *attr, | |
1662 | char *buf) | |
1663 | { | |
1664 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1665 | ||
c965809c | 1666 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1667 | ndev->cmbloc, ndev->cmbsz); |
1668 | } | |
1669 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1670 | ||
88de4598 | 1671 | static u64 nvme_cmb_size_unit(struct nvme_dev *dev) |
8ffaadf7 | 1672 | { |
88de4598 CH |
1673 | u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; |
1674 | ||
1675 | return 1ULL << (12 + 4 * szu); | |
1676 | } | |
1677 | ||
1678 | static u32 nvme_cmb_size(struct nvme_dev *dev) | |
1679 | { | |
1680 | return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; | |
1681 | } | |
1682 | ||
f65efd6d | 1683 | static void nvme_map_cmb(struct nvme_dev *dev) |
8ffaadf7 | 1684 | { |
88de4598 | 1685 | u64 size, offset; |
8ffaadf7 JD |
1686 | resource_size_t bar_size; |
1687 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
8969f1f8 | 1688 | int bar; |
8ffaadf7 | 1689 | |
7a67cbea | 1690 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
f65efd6d CH |
1691 | if (!dev->cmbsz) |
1692 | return; | |
202021c1 | 1693 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1694 | |
202021c1 | 1695 | if (!use_cmb_sqes) |
f65efd6d | 1696 | return; |
8ffaadf7 | 1697 | |
88de4598 CH |
1698 | size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); |
1699 | offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); | |
8969f1f8 CH |
1700 | bar = NVME_CMB_BIR(dev->cmbloc); |
1701 | bar_size = pci_resource_len(pdev, bar); | |
8ffaadf7 JD |
1702 | |
1703 | if (offset > bar_size) | |
f65efd6d | 1704 | return; |
8ffaadf7 JD |
1705 | |
1706 | /* | |
1707 | * Controllers may support a CMB size larger than their BAR, | |
1708 | * for example, due to being behind a bridge. Reduce the CMB to | |
1709 | * the reported size of the BAR | |
1710 | */ | |
1711 | if (size > bar_size - offset) | |
1712 | size = bar_size - offset; | |
1713 | ||
f65efd6d CH |
1714 | dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); |
1715 | if (!dev->cmb) | |
1716 | return; | |
8969f1f8 | 1717 | dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; |
8ffaadf7 | 1718 | dev->cmb_size = size; |
f65efd6d CH |
1719 | |
1720 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, | |
1721 | &dev_attr_cmb.attr, NULL)) | |
1722 | dev_warn(dev->ctrl.device, | |
1723 | "failed to add sysfs attribute for CMB\n"); | |
8ffaadf7 JD |
1724 | } |
1725 | ||
1726 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1727 | { | |
1728 | if (dev->cmb) { | |
1729 | iounmap(dev->cmb); | |
1730 | dev->cmb = NULL; | |
1c78f773 MG |
1731 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, |
1732 | &dev_attr_cmb.attr, NULL); | |
1733 | dev->cmbsz = 0; | |
8ffaadf7 JD |
1734 | } |
1735 | } | |
1736 | ||
87ad72a5 CH |
1737 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1738 | { | |
4033f35d | 1739 | u64 dma_addr = dev->host_mem_descs_dma; |
87ad72a5 | 1740 | struct nvme_command c; |
87ad72a5 CH |
1741 | int ret; |
1742 | ||
87ad72a5 CH |
1743 | memset(&c, 0, sizeof(c)); |
1744 | c.features.opcode = nvme_admin_set_features; | |
1745 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1746 | c.features.dword11 = cpu_to_le32(bits); | |
1747 | c.features.dword12 = cpu_to_le32(dev->host_mem_size >> | |
1748 | ilog2(dev->ctrl.page_size)); | |
1749 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); | |
1750 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1751 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1752 | ||
1753 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1754 | if (ret) { | |
1755 | dev_warn(dev->ctrl.device, | |
1756 | "failed to set host mem (err %d, flags %#x).\n", | |
1757 | ret, bits); | |
1758 | } | |
87ad72a5 CH |
1759 | return ret; |
1760 | } | |
1761 | ||
1762 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1763 | { | |
1764 | int i; | |
1765 | ||
1766 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1767 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
1768 | size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; | |
1769 | ||
1770 | dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], | |
1771 | le64_to_cpu(desc->addr)); | |
1772 | } | |
1773 | ||
1774 | kfree(dev->host_mem_desc_bufs); | |
1775 | dev->host_mem_desc_bufs = NULL; | |
4033f35d CH |
1776 | dma_free_coherent(dev->dev, |
1777 | dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), | |
1778 | dev->host_mem_descs, dev->host_mem_descs_dma); | |
87ad72a5 | 1779 | dev->host_mem_descs = NULL; |
7e5dd57e | 1780 | dev->nr_host_mem_descs = 0; |
87ad72a5 CH |
1781 | } |
1782 | ||
92dc6895 CH |
1783 | static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, |
1784 | u32 chunk_size) | |
9d713c2b | 1785 | { |
87ad72a5 | 1786 | struct nvme_host_mem_buf_desc *descs; |
92dc6895 | 1787 | u32 max_entries, len; |
4033f35d | 1788 | dma_addr_t descs_dma; |
2ee0e4ed | 1789 | int i = 0; |
87ad72a5 | 1790 | void **bufs; |
6fbcde66 | 1791 | u64 size, tmp; |
87ad72a5 | 1792 | |
87ad72a5 CH |
1793 | tmp = (preferred + chunk_size - 1); |
1794 | do_div(tmp, chunk_size); | |
1795 | max_entries = tmp; | |
044a9df1 CH |
1796 | |
1797 | if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) | |
1798 | max_entries = dev->ctrl.hmmaxd; | |
1799 | ||
4033f35d CH |
1800 | descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), |
1801 | &descs_dma, GFP_KERNEL); | |
87ad72a5 CH |
1802 | if (!descs) |
1803 | goto out; | |
1804 | ||
1805 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
1806 | if (!bufs) | |
1807 | goto out_free_descs; | |
1808 | ||
244a8fe4 | 1809 | for (size = 0; size < preferred && i < max_entries; size += len) { |
87ad72a5 CH |
1810 | dma_addr_t dma_addr; |
1811 | ||
50cdb7c6 | 1812 | len = min_t(u64, chunk_size, preferred - size); |
87ad72a5 CH |
1813 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, |
1814 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
1815 | if (!bufs[i]) | |
1816 | break; | |
1817 | ||
1818 | descs[i].addr = cpu_to_le64(dma_addr); | |
1819 | descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); | |
1820 | i++; | |
1821 | } | |
1822 | ||
92dc6895 | 1823 | if (!size) |
87ad72a5 | 1824 | goto out_free_bufs; |
87ad72a5 | 1825 | |
87ad72a5 CH |
1826 | dev->nr_host_mem_descs = i; |
1827 | dev->host_mem_size = size; | |
1828 | dev->host_mem_descs = descs; | |
4033f35d | 1829 | dev->host_mem_descs_dma = descs_dma; |
87ad72a5 CH |
1830 | dev->host_mem_desc_bufs = bufs; |
1831 | return 0; | |
1832 | ||
1833 | out_free_bufs: | |
1834 | while (--i >= 0) { | |
1835 | size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; | |
1836 | ||
1837 | dma_free_coherent(dev->dev, size, bufs[i], | |
1838 | le64_to_cpu(descs[i].addr)); | |
1839 | } | |
1840 | ||
1841 | kfree(bufs); | |
1842 | out_free_descs: | |
4033f35d CH |
1843 | dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, |
1844 | descs_dma); | |
87ad72a5 | 1845 | out: |
87ad72a5 CH |
1846 | dev->host_mem_descs = NULL; |
1847 | return -ENOMEM; | |
1848 | } | |
1849 | ||
92dc6895 CH |
1850 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) |
1851 | { | |
1852 | u32 chunk_size; | |
1853 | ||
1854 | /* start big and work our way down */ | |
30f92d62 | 1855 | for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); |
044a9df1 | 1856 | chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); |
92dc6895 CH |
1857 | chunk_size /= 2) { |
1858 | if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { | |
1859 | if (!min || dev->host_mem_size >= min) | |
1860 | return 0; | |
1861 | nvme_free_host_mem(dev); | |
1862 | } | |
1863 | } | |
1864 | ||
1865 | return -ENOMEM; | |
1866 | } | |
1867 | ||
9620cfba | 1868 | static int nvme_setup_host_mem(struct nvme_dev *dev) |
87ad72a5 CH |
1869 | { |
1870 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
1871 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
1872 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
1873 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
6fbcde66 | 1874 | int ret; |
87ad72a5 CH |
1875 | |
1876 | preferred = min(preferred, max); | |
1877 | if (min > max) { | |
1878 | dev_warn(dev->ctrl.device, | |
1879 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
1880 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
1881 | nvme_free_host_mem(dev); | |
9620cfba | 1882 | return 0; |
87ad72a5 CH |
1883 | } |
1884 | ||
1885 | /* | |
1886 | * If we already have a buffer allocated check if we can reuse it. | |
1887 | */ | |
1888 | if (dev->host_mem_descs) { | |
1889 | if (dev->host_mem_size >= min) | |
1890 | enable_bits |= NVME_HOST_MEM_RETURN; | |
1891 | else | |
1892 | nvme_free_host_mem(dev); | |
1893 | } | |
1894 | ||
1895 | if (!dev->host_mem_descs) { | |
92dc6895 CH |
1896 | if (nvme_alloc_host_mem(dev, min, preferred)) { |
1897 | dev_warn(dev->ctrl.device, | |
1898 | "failed to allocate host memory buffer.\n"); | |
9620cfba | 1899 | return 0; /* controller must work without HMB */ |
92dc6895 CH |
1900 | } |
1901 | ||
1902 | dev_info(dev->ctrl.device, | |
1903 | "allocated %lld MiB host memory buffer.\n", | |
1904 | dev->host_mem_size >> ilog2(SZ_1M)); | |
87ad72a5 CH |
1905 | } |
1906 | ||
9620cfba CH |
1907 | ret = nvme_set_host_mem(dev, enable_bits); |
1908 | if (ret) | |
87ad72a5 | 1909 | nvme_free_host_mem(dev); |
9620cfba | 1910 | return ret; |
9d713c2b KB |
1911 | } |
1912 | ||
8d85fce7 | 1913 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1914 | { |
147b27e4 | 1915 | struct nvme_queue *adminq = &dev->queues[0]; |
e75ec752 | 1916 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
97f6ef64 XY |
1917 | int result, nr_io_queues; |
1918 | unsigned long size; | |
b60503ba | 1919 | |
22b55601 KB |
1920 | struct irq_affinity affd = { |
1921 | .pre_vectors = 1 | |
1922 | }; | |
1923 | ||
16ccfff2 | 1924 | nr_io_queues = num_possible_cpus(); |
9a0be7ab CH |
1925 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1926 | if (result < 0) | |
1b23484b | 1927 | return result; |
9a0be7ab | 1928 | |
f5fa90dc | 1929 | if (nr_io_queues == 0) |
a5229050 | 1930 | return 0; |
b60503ba | 1931 | |
88de4598 | 1932 | if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) { |
8ffaadf7 JD |
1933 | result = nvme_cmb_qdepth(dev, nr_io_queues, |
1934 | sizeof(struct nvme_command)); | |
1935 | if (result > 0) | |
1936 | dev->q_depth = result; | |
1937 | else | |
1938 | nvme_release_cmb(dev); | |
1939 | } | |
1940 | ||
97f6ef64 XY |
1941 | do { |
1942 | size = db_bar_size(dev, nr_io_queues); | |
1943 | result = nvme_remap_bar(dev, size); | |
1944 | if (!result) | |
1945 | break; | |
1946 | if (!--nr_io_queues) | |
1947 | return -ENOMEM; | |
1948 | } while (1); | |
1949 | adminq->q_db = dev->dbs; | |
f1938f6e | 1950 | |
9d713c2b | 1951 | /* Deregister the admin queue's interrupt */ |
0ff199cb | 1952 | pci_free_irq(pdev, 0, adminq); |
9d713c2b | 1953 | |
e32efbfc JA |
1954 | /* |
1955 | * If we enable msix early due to not intx, disable it again before | |
1956 | * setting up the full range we need. | |
1957 | */ | |
dca51e78 | 1958 | pci_free_irq_vectors(pdev); |
22b55601 KB |
1959 | result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, |
1960 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); | |
1961 | if (result <= 0) | |
dca51e78 | 1962 | return -EIO; |
22b55601 KB |
1963 | dev->num_vecs = result; |
1964 | dev->max_qid = max(result - 1, 1); | |
fa08a396 | 1965 | |
063a8096 MW |
1966 | /* |
1967 | * Should investigate if there's a performance win from allocating | |
1968 | * more queues than interrupt vectors; it might allow the submission | |
1969 | * path to scale better, even if the receive path is limited by the | |
1970 | * number of interrupts. | |
1971 | */ | |
063a8096 | 1972 | |
dca51e78 | 1973 | result = queue_request_irq(adminq); |
758dd7fd JD |
1974 | if (result) { |
1975 | adminq->cq_vector = -1; | |
d4875622 | 1976 | return result; |
758dd7fd | 1977 | } |
749941f2 | 1978 | return nvme_create_io_queues(dev); |
b60503ba MW |
1979 | } |
1980 | ||
2a842aca | 1981 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 1982 | { |
db3cbfff | 1983 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1984 | |
db3cbfff KB |
1985 | blk_mq_free_request(req); |
1986 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1987 | } |
1988 | ||
2a842aca | 1989 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 1990 | { |
db3cbfff | 1991 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1992 | |
db3cbfff KB |
1993 | if (!error) { |
1994 | unsigned long flags; | |
1995 | ||
2e39e0f6 ML |
1996 | /* |
1997 | * We might be called with the AQ q_lock held | |
1998 | * and the I/O queue q_lock should always | |
1999 | * nest inside the AQ one. | |
2000 | */ | |
2001 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
2002 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
2003 | nvme_process_cq(nvmeq); |
2004 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 2005 | } |
db3cbfff KB |
2006 | |
2007 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
2008 | } |
2009 | ||
db3cbfff | 2010 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 2011 | { |
db3cbfff KB |
2012 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
2013 | struct request *req; | |
2014 | struct nvme_command cmd; | |
bda4e0fb | 2015 | |
db3cbfff KB |
2016 | memset(&cmd, 0, sizeof(cmd)); |
2017 | cmd.delete_queue.opcode = opcode; | |
2018 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 2019 | |
eb71f435 | 2020 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
2021 | if (IS_ERR(req)) |
2022 | return PTR_ERR(req); | |
bda4e0fb | 2023 | |
db3cbfff KB |
2024 | req->timeout = ADMIN_TIMEOUT; |
2025 | req->end_io_data = nvmeq; | |
2026 | ||
2027 | blk_execute_rq_nowait(q, NULL, req, false, | |
2028 | opcode == nvme_admin_delete_cq ? | |
2029 | nvme_del_cq_end : nvme_del_queue_end); | |
2030 | return 0; | |
bda4e0fb KB |
2031 | } |
2032 | ||
ee9aebb2 | 2033 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
a5768aa8 | 2034 | { |
ee9aebb2 | 2035 | int pass, queues = dev->online_queues - 1; |
db3cbfff KB |
2036 | unsigned long timeout; |
2037 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 2038 | |
db3cbfff | 2039 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 2040 | int sent = 0, i = queues; |
db3cbfff KB |
2041 | |
2042 | reinit_completion(&dev->ioq_wait); | |
2043 | retry: | |
2044 | timeout = ADMIN_TIMEOUT; | |
c21377f8 | 2045 | for (; i > 0; i--, sent++) |
147b27e4 | 2046 | if (nvme_delete_queue(&dev->queues[i], opcode)) |
db3cbfff | 2047 | break; |
c21377f8 | 2048 | |
db3cbfff KB |
2049 | while (sent--) { |
2050 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
2051 | if (timeout == 0) | |
2052 | return; | |
2053 | if (i) | |
2054 | goto retry; | |
2055 | } | |
2056 | opcode = nvme_admin_delete_cq; | |
2057 | } | |
a5768aa8 KB |
2058 | } |
2059 | ||
422ef0c7 | 2060 | /* |
2b1b7e78 | 2061 | * return error value only when tagset allocation failed |
422ef0c7 | 2062 | */ |
8d85fce7 | 2063 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2064 | { |
2b1b7e78 JW |
2065 | int ret; |
2066 | ||
5bae7f73 | 2067 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
2068 | dev->tagset.ops = &nvme_mq_ops; |
2069 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
2070 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
2071 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
2072 | dev->tagset.queue_depth = | |
a4aea562 | 2073 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
a7a7cbe3 CK |
2074 | dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); |
2075 | if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { | |
2076 | dev->tagset.cmd_size = max(dev->tagset.cmd_size, | |
2077 | nvme_pci_cmd_size(dev, true)); | |
2078 | } | |
ffe7704d KB |
2079 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; |
2080 | dev->tagset.driver_data = dev; | |
b60503ba | 2081 | |
2b1b7e78 JW |
2082 | ret = blk_mq_alloc_tag_set(&dev->tagset); |
2083 | if (ret) { | |
2084 | dev_warn(dev->ctrl.device, | |
2085 | "IO queues tagset allocation failed %d\n", ret); | |
2086 | return ret; | |
2087 | } | |
5bae7f73 | 2088 | dev->ctrl.tagset = &dev->tagset; |
f9f38e33 HK |
2089 | |
2090 | nvme_dbbuf_set(dev); | |
949928c1 KB |
2091 | } else { |
2092 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
2093 | ||
2094 | /* Free previously allocated queues that are no longer usable */ | |
2095 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 2096 | } |
949928c1 | 2097 | |
e1e5e564 | 2098 | return 0; |
b60503ba MW |
2099 | } |
2100 | ||
b00a726a | 2101 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 2102 | { |
b00a726a | 2103 | int result = -ENOMEM; |
e75ec752 | 2104 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
2105 | |
2106 | if (pci_enable_device_mem(pdev)) | |
2107 | return result; | |
2108 | ||
0877cb0d | 2109 | pci_set_master(pdev); |
0877cb0d | 2110 | |
e75ec752 CH |
2111 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
2112 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 2113 | goto disable; |
0877cb0d | 2114 | |
7a67cbea | 2115 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 2116 | result = -ENODEV; |
b00a726a | 2117 | goto disable; |
0e53d180 | 2118 | } |
e32efbfc JA |
2119 | |
2120 | /* | |
a5229050 KB |
2121 | * Some devices and/or platforms don't advertise or work with INTx |
2122 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
2123 | * adjust this later. | |
e32efbfc | 2124 | */ |
dca51e78 CH |
2125 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
2126 | if (result < 0) | |
2127 | return result; | |
e32efbfc | 2128 | |
20d0dfe6 | 2129 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
7a67cbea | 2130 | |
20d0dfe6 | 2131 | dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
b27c1e68 | 2132 | io_queue_depth); |
20d0dfe6 | 2133 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
7a67cbea | 2134 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
2135 | |
2136 | /* | |
2137 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
2138 | * some MacBook7,1 to avoid controller resets and data loss. | |
2139 | */ | |
2140 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
2141 | dev->q_depth = 2; | |
9bdcfb10 CH |
2142 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
2143 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f | 2144 | dev->q_depth); |
d554b5e1 MP |
2145 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
2146 | (pdev->device == 0xa821 || pdev->device == 0xa822) && | |
20d0dfe6 | 2147 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
d554b5e1 MP |
2148 | dev->q_depth = 64; |
2149 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " | |
2150 | "set queue depth=%u\n", dev->q_depth); | |
1f390c1f SG |
2151 | } |
2152 | ||
f65efd6d | 2153 | nvme_map_cmb(dev); |
202021c1 | 2154 | |
a0a3408e KB |
2155 | pci_enable_pcie_error_reporting(pdev); |
2156 | pci_save_state(pdev); | |
0877cb0d KB |
2157 | return 0; |
2158 | ||
2159 | disable: | |
0877cb0d KB |
2160 | pci_disable_device(pdev); |
2161 | return result; | |
2162 | } | |
2163 | ||
2164 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
2165 | { |
2166 | if (dev->bar) | |
2167 | iounmap(dev->bar); | |
a1f447b3 | 2168 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
2169 | } |
2170 | ||
2171 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 2172 | { |
e75ec752 CH |
2173 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2174 | ||
f63572df | 2175 | nvme_release_cmb(dev); |
dca51e78 | 2176 | pci_free_irq_vectors(pdev); |
0877cb0d | 2177 | |
a0a3408e KB |
2178 | if (pci_is_enabled(pdev)) { |
2179 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 2180 | pci_disable_device(pdev); |
4d115420 | 2181 | } |
4d115420 KB |
2182 | } |
2183 | ||
a5cdb68c | 2184 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 2185 | { |
ee9aebb2 | 2186 | int i; |
302ad8cc KB |
2187 | bool dead = true; |
2188 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 2189 | |
77bf25ea | 2190 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
2191 | if (pci_is_enabled(pdev)) { |
2192 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
2193 | ||
ebef7368 KB |
2194 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
2195 | dev->ctrl.state == NVME_CTRL_RESETTING) | |
302ad8cc KB |
2196 | nvme_start_freeze(&dev->ctrl); |
2197 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
2198 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 2199 | } |
c21377f8 | 2200 | |
302ad8cc KB |
2201 | /* |
2202 | * Give the controller a chance to complete all entered requests if | |
2203 | * doing a safe shutdown. | |
2204 | */ | |
87ad72a5 CH |
2205 | if (!dead) { |
2206 | if (shutdown) | |
2207 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
9a915a5b JW |
2208 | } |
2209 | ||
2210 | nvme_stop_queues(&dev->ctrl); | |
87ad72a5 | 2211 | |
64ee0ac0 | 2212 | if (!dead && dev->ctrl.queue_count > 0) { |
87ad72a5 CH |
2213 | /* |
2214 | * If the controller is still alive tell it to stop using the | |
2215 | * host memory buffer. In theory the shutdown / reset should | |
2216 | * make sure that it doesn't access the host memoery anymore, | |
2217 | * but I'd rather be safe than sorry.. | |
2218 | */ | |
2219 | if (dev->host_mem_descs) | |
2220 | nvme_set_host_mem(dev, 0); | |
ee9aebb2 | 2221 | nvme_disable_io_queues(dev); |
a5cdb68c | 2222 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 2223 | } |
ee9aebb2 KB |
2224 | for (i = dev->ctrl.queue_count - 1; i >= 0; i--) |
2225 | nvme_suspend_queue(&dev->queues[i]); | |
2226 | ||
b00a726a | 2227 | nvme_pci_disable(dev); |
07836e65 | 2228 | |
e1958e65 ML |
2229 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
2230 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
2231 | |
2232 | /* | |
2233 | * The driver will not be starting up queues again if shutting down so | |
2234 | * must flush all entered requests to their failed completion to avoid | |
2235 | * deadlocking blk-mq hot-cpu notifier. | |
2236 | */ | |
2237 | if (shutdown) | |
2238 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 2239 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2240 | } |
2241 | ||
091b6092 MW |
2242 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2243 | { | |
e75ec752 | 2244 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2245 | PAGE_SIZE, PAGE_SIZE, 0); |
2246 | if (!dev->prp_page_pool) | |
2247 | return -ENOMEM; | |
2248 | ||
99802a7a | 2249 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2250 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2251 | 256, 256, 0); |
2252 | if (!dev->prp_small_pool) { | |
2253 | dma_pool_destroy(dev->prp_page_pool); | |
2254 | return -ENOMEM; | |
2255 | } | |
091b6092 MW |
2256 | return 0; |
2257 | } | |
2258 | ||
2259 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2260 | { | |
2261 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2262 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2263 | } |
2264 | ||
1673f1f0 | 2265 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2266 | { |
1673f1f0 | 2267 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2268 | |
f9f38e33 | 2269 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 2270 | put_device(dev->dev); |
4af0e21c KB |
2271 | if (dev->tagset.tags) |
2272 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2273 | if (dev->ctrl.admin_q) |
2274 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 2275 | kfree(dev->queues); |
e286bcfc | 2276 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
2277 | kfree(dev); |
2278 | } | |
2279 | ||
f58944e2 KB |
2280 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
2281 | { | |
237045fc | 2282 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 | 2283 | |
d22524a4 | 2284 | nvme_get_ctrl(&dev->ctrl); |
69d9a99c | 2285 | nvme_dev_disable(dev, false); |
03e0f3a6 | 2286 | if (!queue_work(nvme_wq, &dev->remove_work)) |
f58944e2 KB |
2287 | nvme_put_ctrl(&dev->ctrl); |
2288 | } | |
2289 | ||
fd634f41 | 2290 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2291 | { |
d86c4d8e CH |
2292 | struct nvme_dev *dev = |
2293 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2294 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 2295 | int result = -ENODEV; |
2b1b7e78 | 2296 | enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; |
5e82e952 | 2297 | |
82b057ca | 2298 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) |
fd634f41 | 2299 | goto out; |
5e82e952 | 2300 | |
fd634f41 CH |
2301 | /* |
2302 | * If we're called to reset a live controller first shut it down before | |
2303 | * moving on. | |
2304 | */ | |
b00a726a | 2305 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2306 | nvme_dev_disable(dev, false); |
5e82e952 | 2307 | |
ad70062c | 2308 | /* |
ad6a0a52 | 2309 | * Introduce CONNECTING state from nvme-fc/rdma transports to mark the |
ad70062c JW |
2310 | * initializing procedure here. |
2311 | */ | |
ad6a0a52 | 2312 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { |
ad70062c | 2313 | dev_warn(dev->ctrl.device, |
ad6a0a52 | 2314 | "failed to mark controller CONNECTING\n"); |
ad70062c JW |
2315 | goto out; |
2316 | } | |
2317 | ||
b00a726a | 2318 | result = nvme_pci_enable(dev); |
f0b50732 | 2319 | if (result) |
3cf519b5 | 2320 | goto out; |
f0b50732 | 2321 | |
01ad0990 | 2322 | result = nvme_pci_configure_admin_queue(dev); |
f0b50732 | 2323 | if (result) |
f58944e2 | 2324 | goto out; |
f0b50732 | 2325 | |
0fb59cbc KB |
2326 | result = nvme_alloc_admin_tags(dev); |
2327 | if (result) | |
f58944e2 | 2328 | goto out; |
b9afca3e | 2329 | |
ce4541f4 CH |
2330 | result = nvme_init_identify(&dev->ctrl); |
2331 | if (result) | |
f58944e2 | 2332 | goto out; |
ce4541f4 | 2333 | |
e286bcfc SB |
2334 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2335 | if (!dev->ctrl.opal_dev) | |
2336 | dev->ctrl.opal_dev = | |
2337 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2338 | else if (was_suspend) | |
2339 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2340 | } else { | |
2341 | free_opal_dev(dev->ctrl.opal_dev); | |
2342 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2343 | } |
a98e58e5 | 2344 | |
f9f38e33 HK |
2345 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2346 | result = nvme_dbbuf_dma_alloc(dev); | |
2347 | if (result) | |
2348 | dev_warn(dev->dev, | |
2349 | "unable to allocate dma for dbbuf\n"); | |
2350 | } | |
2351 | ||
9620cfba CH |
2352 | if (dev->ctrl.hmpre) { |
2353 | result = nvme_setup_host_mem(dev); | |
2354 | if (result < 0) | |
2355 | goto out; | |
2356 | } | |
87ad72a5 | 2357 | |
f0b50732 | 2358 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2359 | if (result) |
f58944e2 | 2360 | goto out; |
f0b50732 | 2361 | |
2659e57b CH |
2362 | /* |
2363 | * Keep the controller around but remove all namespaces if we don't have | |
2364 | * any working I/O queue. | |
2365 | */ | |
3cf519b5 | 2366 | if (dev->online_queues < 2) { |
1b3c47c1 | 2367 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2368 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2369 | nvme_remove_namespaces(&dev->ctrl); |
2b1b7e78 | 2370 | new_state = NVME_CTRL_ADMIN_ONLY; |
3cf519b5 | 2371 | } else { |
25646264 | 2372 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2373 | nvme_wait_freeze(&dev->ctrl); |
2b1b7e78 JW |
2374 | /* hit this only when allocate tagset fails */ |
2375 | if (nvme_dev_add(dev)) | |
2376 | new_state = NVME_CTRL_ADMIN_ONLY; | |
302ad8cc | 2377 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2378 | } |
2379 | ||
2b1b7e78 JW |
2380 | /* |
2381 | * If only admin queue live, keep it to do further investigation or | |
2382 | * recovery. | |
2383 | */ | |
2384 | if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { | |
2385 | dev_warn(dev->ctrl.device, | |
2386 | "failed to mark controller state %d\n", new_state); | |
bb8d261e CH |
2387 | goto out; |
2388 | } | |
92911a55 | 2389 | |
d09f2b45 | 2390 | nvme_start_ctrl(&dev->ctrl); |
3cf519b5 | 2391 | return; |
f0b50732 | 2392 | |
3cf519b5 | 2393 | out: |
f58944e2 | 2394 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
2395 | } |
2396 | ||
5c8809e6 | 2397 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2398 | { |
5c8809e6 | 2399 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2400 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 2401 | |
69d9a99c | 2402 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 2403 | if (pci_get_drvdata(pdev)) |
921920ab | 2404 | device_release_driver(&pdev->dev); |
1673f1f0 | 2405 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2406 | } |
2407 | ||
1c63dc66 | 2408 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2409 | { |
1c63dc66 | 2410 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2411 | return 0; |
9ca97374 TH |
2412 | } |
2413 | ||
5fd4ce1b | 2414 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2415 | { |
5fd4ce1b CH |
2416 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2417 | return 0; | |
2418 | } | |
4cc06521 | 2419 | |
7fd8930f CH |
2420 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2421 | { | |
2422 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2423 | return 0; | |
4cc06521 KB |
2424 | } |
2425 | ||
97c12223 KB |
2426 | static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) |
2427 | { | |
2428 | struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); | |
2429 | ||
2430 | return snprintf(buf, size, "%s", dev_name(&pdev->dev)); | |
2431 | } | |
2432 | ||
1c63dc66 | 2433 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2434 | .name = "pcie", |
e439bb12 | 2435 | .module = THIS_MODULE, |
c81bfba9 | 2436 | .flags = NVME_F_METADATA_SUPPORTED, |
1c63dc66 | 2437 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2438 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2439 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 2440 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2441 | .submit_async_event = nvme_pci_submit_async_event, |
97c12223 | 2442 | .get_address = nvme_pci_get_address, |
1c63dc66 | 2443 | }; |
4cc06521 | 2444 | |
b00a726a KB |
2445 | static int nvme_dev_map(struct nvme_dev *dev) |
2446 | { | |
b00a726a KB |
2447 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2448 | ||
a1f447b3 | 2449 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2450 | return -ENODEV; |
2451 | ||
97f6ef64 | 2452 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
2453 | goto release; |
2454 | ||
9fa196e7 | 2455 | return 0; |
b00a726a | 2456 | release: |
9fa196e7 MG |
2457 | pci_release_mem_regions(pdev); |
2458 | return -ENODEV; | |
b00a726a KB |
2459 | } |
2460 | ||
8427bbc2 | 2461 | static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) |
ff5350a8 AL |
2462 | { |
2463 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2464 | /* | |
2465 | * Several Samsung devices seem to drop off the PCIe bus | |
2466 | * randomly when APST is on and uses the deepest sleep state. | |
2467 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2468 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2469 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2470 | * laptops. | |
2471 | */ | |
2472 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2473 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2474 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2475 | return NVME_QUIRK_NO_DEEPEST_PS; | |
8427bbc2 KHF |
2476 | } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { |
2477 | /* | |
2478 | * Samsung SSD 960 EVO drops off the PCIe bus after system | |
467c77d4 JJ |
2479 | * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as |
2480 | * within few minutes after bootup on a Coffee Lake board - | |
2481 | * ASUS PRIME Z370-A | |
8427bbc2 KHF |
2482 | */ |
2483 | if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && | |
467c77d4 JJ |
2484 | (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || |
2485 | dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) | |
8427bbc2 | 2486 | return NVME_QUIRK_NO_APST; |
ff5350a8 AL |
2487 | } |
2488 | ||
2489 | return 0; | |
2490 | } | |
2491 | ||
18119775 KB |
2492 | static void nvme_async_probe(void *data, async_cookie_t cookie) |
2493 | { | |
2494 | struct nvme_dev *dev = data; | |
2495 | nvme_reset_ctrl_sync(&dev->ctrl); | |
2496 | flush_work(&dev->ctrl.scan_work); | |
2497 | } | |
2498 | ||
8d85fce7 | 2499 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2500 | { |
a4aea562 | 2501 | int node, result = -ENOMEM; |
b60503ba | 2502 | struct nvme_dev *dev; |
ff5350a8 | 2503 | unsigned long quirks = id->driver_data; |
b60503ba | 2504 | |
a4aea562 MB |
2505 | node = dev_to_node(&pdev->dev); |
2506 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2507 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2508 | |
2509 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2510 | if (!dev) |
2511 | return -ENOMEM; | |
147b27e4 SG |
2512 | |
2513 | dev->queues = kcalloc_node(num_possible_cpus() + 1, | |
2514 | sizeof(struct nvme_queue), GFP_KERNEL, node); | |
b60503ba MW |
2515 | if (!dev->queues) |
2516 | goto free; | |
2517 | ||
e75ec752 | 2518 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2519 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2520 | |
b00a726a KB |
2521 | result = nvme_dev_map(dev); |
2522 | if (result) | |
b00c9b7a | 2523 | goto put_pci; |
b00a726a | 2524 | |
d86c4d8e | 2525 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 2526 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2527 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2528 | init_completion(&dev->ioq_wait); |
b60503ba | 2529 | |
091b6092 MW |
2530 | result = nvme_setup_prp_pools(dev); |
2531 | if (result) | |
b00c9b7a | 2532 | goto unmap; |
4cc06521 | 2533 | |
8427bbc2 | 2534 | quirks |= check_vendor_combination_bug(pdev); |
ff5350a8 | 2535 | |
f3ca80fc | 2536 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
ff5350a8 | 2537 | quirks); |
4cc06521 | 2538 | if (result) |
2e1d8448 | 2539 | goto release_pools; |
740216fc | 2540 | |
1b3c47c1 SG |
2541 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2542 | ||
18119775 | 2543 | async_schedule(nvme_async_probe, dev); |
4caff8fc | 2544 | |
b60503ba MW |
2545 | return 0; |
2546 | ||
0877cb0d | 2547 | release_pools: |
091b6092 | 2548 | nvme_release_prp_pools(dev); |
b00c9b7a CJ |
2549 | unmap: |
2550 | nvme_dev_unmap(dev); | |
a96d4f5c | 2551 | put_pci: |
e75ec752 | 2552 | put_device(dev->dev); |
b60503ba MW |
2553 | free: |
2554 | kfree(dev->queues); | |
b60503ba MW |
2555 | kfree(dev); |
2556 | return result; | |
2557 | } | |
2558 | ||
775755ed | 2559 | static void nvme_reset_prepare(struct pci_dev *pdev) |
f0d54a54 | 2560 | { |
a6739479 | 2561 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f263fbb8 | 2562 | nvme_dev_disable(dev, false); |
775755ed | 2563 | } |
f0d54a54 | 2564 | |
775755ed CH |
2565 | static void nvme_reset_done(struct pci_dev *pdev) |
2566 | { | |
f263fbb8 | 2567 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
79c48ccf | 2568 | nvme_reset_ctrl_sync(&dev->ctrl); |
f0d54a54 KB |
2569 | } |
2570 | ||
09ece142 KB |
2571 | static void nvme_shutdown(struct pci_dev *pdev) |
2572 | { | |
2573 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2574 | nvme_dev_disable(dev, true); |
09ece142 KB |
2575 | } |
2576 | ||
f58944e2 KB |
2577 | /* |
2578 | * The driver's remove may be called on a device in a partially initialized | |
2579 | * state. This function must not have any dependencies on the device state in | |
2580 | * order to proceed. | |
2581 | */ | |
8d85fce7 | 2582 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2583 | { |
2584 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2585 | |
bb8d261e CH |
2586 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2587 | ||
d86c4d8e | 2588 | cancel_work_sync(&dev->ctrl.reset_work); |
9a6b9458 | 2589 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2590 | |
6db28eda | 2591 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2592 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2593 | nvme_dev_disable(dev, false); |
2594 | } | |
0ff9d4e1 | 2595 | |
d86c4d8e | 2596 | flush_work(&dev->ctrl.reset_work); |
d09f2b45 SG |
2597 | nvme_stop_ctrl(&dev->ctrl); |
2598 | nvme_remove_namespaces(&dev->ctrl); | |
a5cdb68c | 2599 | nvme_dev_disable(dev, true); |
87ad72a5 | 2600 | nvme_free_host_mem(dev); |
a4aea562 | 2601 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2602 | nvme_free_queues(dev, 0); |
d09f2b45 | 2603 | nvme_uninit_ctrl(&dev->ctrl); |
9a6b9458 | 2604 | nvme_release_prp_pools(dev); |
b00a726a | 2605 | nvme_dev_unmap(dev); |
1673f1f0 | 2606 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2607 | } |
2608 | ||
13880f5b KB |
2609 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2610 | { | |
2611 | int ret = 0; | |
2612 | ||
2613 | if (numvfs == 0) { | |
2614 | if (pci_vfs_assigned(pdev)) { | |
2615 | dev_warn(&pdev->dev, | |
2616 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2617 | return -EPERM; | |
2618 | } | |
2619 | pci_disable_sriov(pdev); | |
2620 | return 0; | |
2621 | } | |
2622 | ||
2623 | ret = pci_enable_sriov(pdev, numvfs); | |
2624 | return ret ? ret : numvfs; | |
2625 | } | |
2626 | ||
671a6018 | 2627 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2628 | static int nvme_suspend(struct device *dev) |
2629 | { | |
2630 | struct pci_dev *pdev = to_pci_dev(dev); | |
2631 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2632 | ||
a5cdb68c | 2633 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2634 | return 0; |
2635 | } | |
2636 | ||
2637 | static int nvme_resume(struct device *dev) | |
2638 | { | |
2639 | struct pci_dev *pdev = to_pci_dev(dev); | |
2640 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2641 | |
d86c4d8e | 2642 | nvme_reset_ctrl(&ndev->ctrl); |
9a6b9458 | 2643 | return 0; |
cd638946 | 2644 | } |
671a6018 | 2645 | #endif |
cd638946 KB |
2646 | |
2647 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2648 | |
a0a3408e KB |
2649 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2650 | pci_channel_state_t state) | |
2651 | { | |
2652 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2653 | ||
2654 | /* | |
2655 | * A frozen channel requires a reset. When detected, this method will | |
2656 | * shutdown the controller to quiesce. The controller will be restarted | |
2657 | * after the slot reset through driver's slot_reset callback. | |
2658 | */ | |
a0a3408e KB |
2659 | switch (state) { |
2660 | case pci_channel_io_normal: | |
2661 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2662 | case pci_channel_io_frozen: | |
d011fb31 KB |
2663 | dev_warn(dev->ctrl.device, |
2664 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2665 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2666 | return PCI_ERS_RESULT_NEED_RESET; |
2667 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2668 | dev_warn(dev->ctrl.device, |
2669 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2670 | return PCI_ERS_RESULT_DISCONNECT; |
2671 | } | |
2672 | return PCI_ERS_RESULT_NEED_RESET; | |
2673 | } | |
2674 | ||
2675 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2676 | { | |
2677 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2678 | ||
1b3c47c1 | 2679 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2680 | pci_restore_state(pdev); |
d86c4d8e | 2681 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
2682 | return PCI_ERS_RESULT_RECOVERED; |
2683 | } | |
2684 | ||
2685 | static void nvme_error_resume(struct pci_dev *pdev) | |
2686 | { | |
2687 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2688 | } | |
2689 | ||
1d352035 | 2690 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2691 | .error_detected = nvme_error_detected, |
b60503ba MW |
2692 | .slot_reset = nvme_slot_reset, |
2693 | .resume = nvme_error_resume, | |
775755ed CH |
2694 | .reset_prepare = nvme_reset_prepare, |
2695 | .reset_done = nvme_reset_done, | |
b60503ba MW |
2696 | }; |
2697 | ||
6eb0d698 | 2698 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2699 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2700 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2701 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2702 | { PCI_VDEVICE(INTEL, 0x0a53), |
2703 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2704 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2705 | { PCI_VDEVICE(INTEL, 0x0a54), |
2706 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2707 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
f99cb7af DWF |
2708 | { PCI_VDEVICE(INTEL, 0x0a55), |
2709 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2710 | NVME_QUIRK_DEALLOCATE_ZEROES, }, | |
50af47d0 AL |
2711 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
2712 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, | |
540c801c KB |
2713 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2714 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
0302ae60 MP |
2715 | { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ |
2716 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
54adc010 GP |
2717 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2718 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
8c97eecc JL |
2719 | { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ |
2720 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2721 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2722 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
d554b5e1 MP |
2723 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
2724 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
2725 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ | |
2726 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
608cc4b1 CH |
2727 | { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ |
2728 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
2729 | { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ | |
2730 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
ea48e877 WX |
2731 | { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ |
2732 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
b60503ba | 2733 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2734 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2735 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2736 | { 0, } |
2737 | }; | |
2738 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2739 | ||
2740 | static struct pci_driver nvme_driver = { | |
2741 | .name = "nvme", | |
2742 | .id_table = nvme_id_table, | |
2743 | .probe = nvme_probe, | |
8d85fce7 | 2744 | .remove = nvme_remove, |
09ece142 | 2745 | .shutdown = nvme_shutdown, |
cd638946 KB |
2746 | .driver = { |
2747 | .pm = &nvme_dev_pm_ops, | |
2748 | }, | |
13880f5b | 2749 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2750 | .err_handler = &nvme_err_handler, |
2751 | }; | |
2752 | ||
2753 | static int __init nvme_init(void) | |
2754 | { | |
9a6327d2 | 2755 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
2756 | } |
2757 | ||
2758 | static void __exit nvme_exit(void) | |
2759 | { | |
2760 | pci_unregister_driver(&nvme_driver); | |
03e0f3a6 | 2761 | flush_workqueue(nvme_wq); |
21bd78bc | 2762 | _nvme_check_size(); |
b60503ba MW |
2763 | } |
2764 | ||
2765 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2766 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2767 | MODULE_VERSION("1.0"); |
b60503ba MW |
2768 | module_init(nvme_init); |
2769 | module_exit(nvme_exit); |