Commit | Line | Data |
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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
a0a3408e | 15 | #include <linux/aer.h> |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
dca51e78 | 19 | #include <linux/blk-mq-pci.h> |
ff5350a8 | 20 | #include <linux/dmi.h> |
b60503ba MW |
21 | #include <linux/init.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
b60503ba MW |
24 | #include <linux/mm.h> |
25 | #include <linux/module.h> | |
77bf25ea | 26 | #include <linux/mutex.h> |
b60503ba | 27 | #include <linux/pci.h> |
be7b6275 | 28 | #include <linux/poison.h> |
e1e5e564 | 29 | #include <linux/t10-pi.h> |
2d55cd5f | 30 | #include <linux/timer.h> |
b60503ba | 31 | #include <linux/types.h> |
2f8e2c87 | 32 | #include <linux/io-64-nonatomic-lo-hi.h> |
1d277a63 | 33 | #include <asm/unaligned.h> |
a98e58e5 | 34 | #include <linux/sed-opal.h> |
797a796a | 35 | |
f11bb3e2 CH |
36 | #include "nvme.h" |
37 | ||
b60503ba MW |
38 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
39 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
c965809c | 40 | |
adf68f21 CH |
41 | /* |
42 | * We handle AEN commands ourselves and don't even let the | |
43 | * block layer know about them. | |
44 | */ | |
f866fc42 | 45 | #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) |
9d43cf64 | 46 | |
58ffacb5 MW |
47 | static int use_threaded_interrupts; |
48 | module_param(use_threaded_interrupts, int, 0); | |
49 | ||
8ffaadf7 JD |
50 | static bool use_cmb_sqes = true; |
51 | module_param(use_cmb_sqes, bool, 0644); | |
52 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); | |
53 | ||
87ad72a5 CH |
54 | static unsigned int max_host_mem_size_mb = 128; |
55 | module_param(max_host_mem_size_mb, uint, 0444); | |
56 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
57 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
1fa6aead | 58 | |
b27c1e68 | 59 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
60 | static const struct kernel_param_ops io_queue_depth_ops = { | |
61 | .set = io_queue_depth_set, | |
62 | .get = param_get_int, | |
63 | }; | |
64 | ||
65 | static int io_queue_depth = 1024; | |
66 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); | |
67 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); | |
68 | ||
1c63dc66 CH |
69 | struct nvme_dev; |
70 | struct nvme_queue; | |
b3fffdef | 71 | |
a0fa9647 | 72 | static void nvme_process_cq(struct nvme_queue *nvmeq); |
a5cdb68c | 73 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
d4b4ff8e | 74 | |
1c63dc66 CH |
75 | /* |
76 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
77 | */ | |
78 | struct nvme_dev { | |
1c63dc66 CH |
79 | struct nvme_queue **queues; |
80 | struct blk_mq_tag_set tagset; | |
81 | struct blk_mq_tag_set admin_tagset; | |
82 | u32 __iomem *dbs; | |
83 | struct device *dev; | |
84 | struct dma_pool *prp_page_pool; | |
85 | struct dma_pool *prp_small_pool; | |
1c63dc66 CH |
86 | unsigned online_queues; |
87 | unsigned max_qid; | |
88 | int q_depth; | |
89 | u32 db_stride; | |
1c63dc66 | 90 | void __iomem *bar; |
97f6ef64 | 91 | unsigned long bar_mapped_size; |
5c8809e6 | 92 | struct work_struct remove_work; |
77bf25ea | 93 | struct mutex shutdown_lock; |
1c63dc66 | 94 | bool subsystem; |
1c63dc66 CH |
95 | void __iomem *cmb; |
96 | dma_addr_t cmb_dma_addr; | |
97 | u64 cmb_size; | |
98 | u32 cmbsz; | |
202021c1 | 99 | u32 cmbloc; |
1c63dc66 | 100 | struct nvme_ctrl ctrl; |
db3cbfff | 101 | struct completion ioq_wait; |
87ad72a5 CH |
102 | |
103 | /* shadow doorbell buffer support: */ | |
f9f38e33 HK |
104 | u32 *dbbuf_dbs; |
105 | dma_addr_t dbbuf_dbs_dma_addr; | |
106 | u32 *dbbuf_eis; | |
107 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
108 | |
109 | /* host memory buffer support: */ | |
110 | u64 host_mem_size; | |
111 | u32 nr_host_mem_descs; | |
4033f35d | 112 | dma_addr_t host_mem_descs_dma; |
87ad72a5 CH |
113 | struct nvme_host_mem_buf_desc *host_mem_descs; |
114 | void **host_mem_desc_bufs; | |
4d115420 | 115 | }; |
1fa6aead | 116 | |
b27c1e68 | 117 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
118 | { | |
119 | int n = 0, ret; | |
120 | ||
121 | ret = kstrtoint(val, 10, &n); | |
122 | if (ret != 0 || n < 2) | |
123 | return -EINVAL; | |
124 | ||
125 | return param_set_int(val, kp); | |
126 | } | |
127 | ||
f9f38e33 HK |
128 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
129 | { | |
130 | return qid * 2 * stride; | |
131 | } | |
132 | ||
133 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
134 | { | |
135 | return (qid * 2 + 1) * stride; | |
136 | } | |
137 | ||
1c63dc66 CH |
138 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
139 | { | |
140 | return container_of(ctrl, struct nvme_dev, ctrl); | |
141 | } | |
142 | ||
b60503ba MW |
143 | /* |
144 | * An NVM Express queue. Each device has at least two (one for admin | |
145 | * commands and one for I/O commands). | |
146 | */ | |
147 | struct nvme_queue { | |
148 | struct device *q_dmadev; | |
091b6092 | 149 | struct nvme_dev *dev; |
b60503ba MW |
150 | spinlock_t q_lock; |
151 | struct nvme_command *sq_cmds; | |
8ffaadf7 | 152 | struct nvme_command __iomem *sq_cmds_io; |
b60503ba | 153 | volatile struct nvme_completion *cqes; |
42483228 | 154 | struct blk_mq_tags **tags; |
b60503ba MW |
155 | dma_addr_t sq_dma_addr; |
156 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
157 | u32 __iomem *q_db; |
158 | u16 q_depth; | |
6222d172 | 159 | s16 cq_vector; |
b60503ba MW |
160 | u16 sq_tail; |
161 | u16 cq_head; | |
c30341dc | 162 | u16 qid; |
e9539f47 MW |
163 | u8 cq_phase; |
164 | u8 cqe_seen; | |
f9f38e33 HK |
165 | u32 *dbbuf_sq_db; |
166 | u32 *dbbuf_cq_db; | |
167 | u32 *dbbuf_sq_ei; | |
168 | u32 *dbbuf_cq_ei; | |
b60503ba MW |
169 | }; |
170 | ||
71bd150c CH |
171 | /* |
172 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
173 | * entries. You can't see it in this data structure because C doesn't let | |
f4800d6d | 174 | * me express that. Use nvme_init_iod to ensure there's enough space |
71bd150c CH |
175 | * allocated to store the PRP list. |
176 | */ | |
177 | struct nvme_iod { | |
d49187e9 | 178 | struct nvme_request req; |
f4800d6d CH |
179 | struct nvme_queue *nvmeq; |
180 | int aborted; | |
71bd150c | 181 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c CH |
182 | int nents; /* Used in scatterlist */ |
183 | int length; /* Of data, in bytes */ | |
184 | dma_addr_t first_dma; | |
bf684057 | 185 | struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ |
f4800d6d CH |
186 | struct scatterlist *sg; |
187 | struct scatterlist inline_sg[0]; | |
b60503ba MW |
188 | }; |
189 | ||
190 | /* | |
191 | * Check we didin't inadvertently grow the command struct | |
192 | */ | |
193 | static inline void _nvme_check_size(void) | |
194 | { | |
195 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
196 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
197 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
198 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
199 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 200 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 201 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba | 202 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
0add5e8e JT |
203 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); |
204 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); | |
b60503ba | 205 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); |
6ecec745 | 206 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
f9f38e33 HK |
207 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); |
208 | } | |
209 | ||
210 | static inline unsigned int nvme_dbbuf_size(u32 stride) | |
211 | { | |
212 | return ((num_possible_cpus() + 1) * 8 * stride); | |
213 | } | |
214 | ||
215 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
216 | { | |
217 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
218 | ||
219 | if (dev->dbbuf_dbs) | |
220 | return 0; | |
221 | ||
222 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
223 | &dev->dbbuf_dbs_dma_addr, | |
224 | GFP_KERNEL); | |
225 | if (!dev->dbbuf_dbs) | |
226 | return -ENOMEM; | |
227 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
228 | &dev->dbbuf_eis_dma_addr, | |
229 | GFP_KERNEL); | |
230 | if (!dev->dbbuf_eis) { | |
231 | dma_free_coherent(dev->dev, mem_size, | |
232 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
233 | dev->dbbuf_dbs = NULL; | |
234 | return -ENOMEM; | |
235 | } | |
236 | ||
237 | return 0; | |
238 | } | |
239 | ||
240 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
241 | { | |
242 | unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); | |
243 | ||
244 | if (dev->dbbuf_dbs) { | |
245 | dma_free_coherent(dev->dev, mem_size, | |
246 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
247 | dev->dbbuf_dbs = NULL; | |
248 | } | |
249 | if (dev->dbbuf_eis) { | |
250 | dma_free_coherent(dev->dev, mem_size, | |
251 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
252 | dev->dbbuf_eis = NULL; | |
253 | } | |
254 | } | |
255 | ||
256 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
257 | struct nvme_queue *nvmeq, int qid) | |
258 | { | |
259 | if (!dev->dbbuf_dbs || !qid) | |
260 | return; | |
261 | ||
262 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
263 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
264 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
265 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
266 | } | |
267 | ||
268 | static void nvme_dbbuf_set(struct nvme_dev *dev) | |
269 | { | |
270 | struct nvme_command c; | |
271 | ||
272 | if (!dev->dbbuf_dbs) | |
273 | return; | |
274 | ||
275 | memset(&c, 0, sizeof(c)); | |
276 | c.dbbuf.opcode = nvme_admin_dbbuf; | |
277 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
278 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
279 | ||
280 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 281 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
282 | /* Free memory and continue on */ |
283 | nvme_dbbuf_dma_free(dev); | |
284 | } | |
285 | } | |
286 | ||
287 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
288 | { | |
289 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
290 | } | |
291 | ||
292 | /* Update dbbuf and return true if an MMIO is required */ | |
293 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
294 | volatile u32 *dbbuf_ei) | |
295 | { | |
296 | if (dbbuf_db) { | |
297 | u16 old_value; | |
298 | ||
299 | /* | |
300 | * Ensure that the queue is written before updating | |
301 | * the doorbell in memory | |
302 | */ | |
303 | wmb(); | |
304 | ||
305 | old_value = *dbbuf_db; | |
306 | *dbbuf_db = value; | |
307 | ||
308 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) | |
309 | return false; | |
310 | } | |
311 | ||
312 | return true; | |
b60503ba MW |
313 | } |
314 | ||
ac3dd5bd JA |
315 | /* |
316 | * Max size of iod being embedded in the request payload | |
317 | */ | |
318 | #define NVME_INT_PAGES 2 | |
5fd4ce1b | 319 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) |
ac3dd5bd JA |
320 | |
321 | /* | |
322 | * Will slightly overestimate the number of pages needed. This is OK | |
323 | * as it only leads to a small amount of wasted memory for the lifetime of | |
324 | * the I/O. | |
325 | */ | |
326 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
327 | { | |
5fd4ce1b CH |
328 | unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, |
329 | dev->ctrl.page_size); | |
ac3dd5bd JA |
330 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
331 | } | |
332 | ||
f4800d6d CH |
333 | static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, |
334 | unsigned int size, unsigned int nseg) | |
ac3dd5bd | 335 | { |
f4800d6d CH |
336 | return sizeof(__le64 *) * nvme_npages(size, dev) + |
337 | sizeof(struct scatterlist) * nseg; | |
338 | } | |
ac3dd5bd | 339 | |
f4800d6d CH |
340 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) |
341 | { | |
342 | return sizeof(struct nvme_iod) + | |
343 | nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); | |
ac3dd5bd JA |
344 | } |
345 | ||
a4aea562 MB |
346 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
347 | unsigned int hctx_idx) | |
e85248e5 | 348 | { |
a4aea562 MB |
349 | struct nvme_dev *dev = data; |
350 | struct nvme_queue *nvmeq = dev->queues[0]; | |
351 | ||
42483228 KB |
352 | WARN_ON(hctx_idx != 0); |
353 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
354 | WARN_ON(nvmeq->tags); | |
355 | ||
a4aea562 | 356 | hctx->driver_data = nvmeq; |
42483228 | 357 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 358 | return 0; |
e85248e5 MW |
359 | } |
360 | ||
4af0e21c KB |
361 | static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) |
362 | { | |
363 | struct nvme_queue *nvmeq = hctx->driver_data; | |
364 | ||
365 | nvmeq->tags = NULL; | |
366 | } | |
367 | ||
a4aea562 MB |
368 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
369 | unsigned int hctx_idx) | |
b60503ba | 370 | { |
a4aea562 | 371 | struct nvme_dev *dev = data; |
42483228 | 372 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 373 | |
42483228 KB |
374 | if (!nvmeq->tags) |
375 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 376 | |
42483228 | 377 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
378 | hctx->driver_data = nvmeq; |
379 | return 0; | |
b60503ba MW |
380 | } |
381 | ||
d6296d39 CH |
382 | static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, |
383 | unsigned int hctx_idx, unsigned int numa_node) | |
b60503ba | 384 | { |
d6296d39 | 385 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 386 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a CH |
387 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
388 | struct nvme_queue *nvmeq = dev->queues[queue_idx]; | |
a4aea562 MB |
389 | |
390 | BUG_ON(!nvmeq); | |
f4800d6d | 391 | iod->nvmeq = nvmeq; |
a4aea562 MB |
392 | return 0; |
393 | } | |
394 | ||
dca51e78 CH |
395 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
396 | { | |
397 | struct nvme_dev *dev = set->driver_data; | |
398 | ||
399 | return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); | |
400 | } | |
401 | ||
b60503ba | 402 | /** |
adf68f21 | 403 | * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
404 | * @nvmeq: The queue to use |
405 | * @cmd: The command to send | |
406 | * | |
407 | * Safe to use from interrupt context | |
408 | */ | |
e3f879bf SB |
409 | static void __nvme_submit_cmd(struct nvme_queue *nvmeq, |
410 | struct nvme_command *cmd) | |
b60503ba | 411 | { |
a4aea562 MB |
412 | u16 tail = nvmeq->sq_tail; |
413 | ||
8ffaadf7 JD |
414 | if (nvmeq->sq_cmds_io) |
415 | memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); | |
416 | else | |
417 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
418 | ||
b60503ba MW |
419 | if (++tail == nvmeq->q_depth) |
420 | tail = 0; | |
f9f38e33 HK |
421 | if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, |
422 | nvmeq->dbbuf_sq_ei)) | |
423 | writel(tail, nvmeq->q_db); | |
b60503ba | 424 | nvmeq->sq_tail = tail; |
b60503ba MW |
425 | } |
426 | ||
f4800d6d | 427 | static __le64 **iod_list(struct request *req) |
b60503ba | 428 | { |
f4800d6d | 429 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
f9d03f96 | 430 | return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
431 | } |
432 | ||
fc17b653 | 433 | static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) |
ac3dd5bd | 434 | { |
f4800d6d | 435 | struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); |
f9d03f96 | 436 | int nseg = blk_rq_nr_phys_segments(rq); |
b131c61d | 437 | unsigned int size = blk_rq_payload_bytes(rq); |
ac3dd5bd | 438 | |
f4800d6d CH |
439 | if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { |
440 | iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); | |
441 | if (!iod->sg) | |
fc17b653 | 442 | return BLK_STS_RESOURCE; |
f4800d6d CH |
443 | } else { |
444 | iod->sg = iod->inline_sg; | |
ac3dd5bd JA |
445 | } |
446 | ||
f4800d6d CH |
447 | iod->aborted = 0; |
448 | iod->npages = -1; | |
449 | iod->nents = 0; | |
450 | iod->length = size; | |
f80ec966 | 451 | |
fc17b653 | 452 | return BLK_STS_OK; |
ac3dd5bd JA |
453 | } |
454 | ||
f4800d6d | 455 | static void nvme_free_iod(struct nvme_dev *dev, struct request *req) |
b60503ba | 456 | { |
f4800d6d | 457 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
5fd4ce1b | 458 | const int last_prp = dev->ctrl.page_size / 8 - 1; |
eca18b23 | 459 | int i; |
f4800d6d | 460 | __le64 **list = iod_list(req); |
eca18b23 MW |
461 | dma_addr_t prp_dma = iod->first_dma; |
462 | ||
463 | if (iod->npages == 0) | |
464 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
465 | for (i = 0; i < iod->npages; i++) { | |
466 | __le64 *prp_list = list[i]; | |
467 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
468 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
469 | prp_dma = next_prp_dma; | |
470 | } | |
ac3dd5bd | 471 | |
f4800d6d CH |
472 | if (iod->sg != iod->inline_sg) |
473 | kfree(iod->sg); | |
b4ff9c8d KB |
474 | } |
475 | ||
52b68d7e | 476 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
477 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
478 | { | |
479 | if (be32_to_cpu(pi->ref_tag) == v) | |
480 | pi->ref_tag = cpu_to_be32(p); | |
481 | } | |
482 | ||
483 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
484 | { | |
485 | if (be32_to_cpu(pi->ref_tag) == p) | |
486 | pi->ref_tag = cpu_to_be32(v); | |
487 | } | |
488 | ||
489 | /** | |
490 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
491 | * | |
492 | * The virtual start sector is the one that was originally submitted by the | |
493 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
494 | * start sector may be different. Remap protection information to match the | |
495 | * physical LBA on writes, and back to the original seed on reads. | |
496 | * | |
497 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
498 | */ | |
499 | static void nvme_dif_remap(struct request *req, | |
500 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
501 | { | |
502 | struct nvme_ns *ns = req->rq_disk->private_data; | |
503 | struct bio_integrity_payload *bip; | |
504 | struct t10_pi_tuple *pi; | |
505 | void *p, *pmap; | |
506 | u32 i, nlb, ts, phys, virt; | |
507 | ||
508 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
509 | return; | |
510 | ||
511 | bip = bio_integrity(req->bio); | |
512 | if (!bip) | |
513 | return; | |
514 | ||
515 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
516 | |
517 | p = pmap; | |
518 | virt = bip_get_seed(bip); | |
519 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
520 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
ac6fc48c | 521 | ts = ns->disk->queue->integrity.tuple_size; |
e1e5e564 KB |
522 | |
523 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
524 | pi = (struct t10_pi_tuple *)p; | |
525 | dif_swap(phys, virt, pi); | |
526 | p += ts; | |
527 | } | |
528 | kunmap_atomic(pmap); | |
529 | } | |
52b68d7e KB |
530 | #else /* CONFIG_BLK_DEV_INTEGRITY */ |
531 | static void nvme_dif_remap(struct request *req, | |
532 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
533 | { | |
534 | } | |
535 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
536 | { | |
537 | } | |
538 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
539 | { | |
540 | } | |
52b68d7e KB |
541 | #endif |
542 | ||
86eea289 | 543 | static blk_status_t nvme_setup_prps(struct nvme_dev *dev, struct request *req) |
ff22b54f | 544 | { |
f4800d6d | 545 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 546 | struct dma_pool *pool; |
b131c61d | 547 | int length = blk_rq_payload_bytes(req); |
eca18b23 | 548 | struct scatterlist *sg = iod->sg; |
ff22b54f MW |
549 | int dma_len = sg_dma_len(sg); |
550 | u64 dma_addr = sg_dma_address(sg); | |
5fd4ce1b | 551 | u32 page_size = dev->ctrl.page_size; |
f137e0f1 | 552 | int offset = dma_addr & (page_size - 1); |
e025344c | 553 | __le64 *prp_list; |
f4800d6d | 554 | __le64 **list = iod_list(req); |
e025344c | 555 | dma_addr_t prp_dma; |
eca18b23 | 556 | int nprps, i; |
ff22b54f | 557 | |
1d090624 | 558 | length -= (page_size - offset); |
5228b328 JS |
559 | if (length <= 0) { |
560 | iod->first_dma = 0; | |
86eea289 | 561 | return BLK_STS_OK; |
5228b328 | 562 | } |
ff22b54f | 563 | |
1d090624 | 564 | dma_len -= (page_size - offset); |
ff22b54f | 565 | if (dma_len) { |
1d090624 | 566 | dma_addr += (page_size - offset); |
ff22b54f MW |
567 | } else { |
568 | sg = sg_next(sg); | |
569 | dma_addr = sg_dma_address(sg); | |
570 | dma_len = sg_dma_len(sg); | |
571 | } | |
572 | ||
1d090624 | 573 | if (length <= page_size) { |
edd10d33 | 574 | iod->first_dma = dma_addr; |
86eea289 | 575 | return BLK_STS_OK; |
e025344c SMM |
576 | } |
577 | ||
1d090624 | 578 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
579 | if (nprps <= (256 / 8)) { |
580 | pool = dev->prp_small_pool; | |
eca18b23 | 581 | iod->npages = 0; |
99802a7a MW |
582 | } else { |
583 | pool = dev->prp_page_pool; | |
eca18b23 | 584 | iod->npages = 1; |
99802a7a MW |
585 | } |
586 | ||
69d2b571 | 587 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 588 | if (!prp_list) { |
edd10d33 | 589 | iod->first_dma = dma_addr; |
eca18b23 | 590 | iod->npages = -1; |
86eea289 | 591 | return BLK_STS_RESOURCE; |
b77954cb | 592 | } |
eca18b23 MW |
593 | list[0] = prp_list; |
594 | iod->first_dma = prp_dma; | |
e025344c SMM |
595 | i = 0; |
596 | for (;;) { | |
1d090624 | 597 | if (i == page_size >> 3) { |
e025344c | 598 | __le64 *old_prp_list = prp_list; |
69d2b571 | 599 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 600 | if (!prp_list) |
86eea289 | 601 | return BLK_STS_RESOURCE; |
eca18b23 | 602 | list[iod->npages++] = prp_list; |
7523d834 MW |
603 | prp_list[0] = old_prp_list[i - 1]; |
604 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
605 | i = 1; | |
e025344c SMM |
606 | } |
607 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
608 | dma_len -= page_size; |
609 | dma_addr += page_size; | |
610 | length -= page_size; | |
e025344c SMM |
611 | if (length <= 0) |
612 | break; | |
613 | if (dma_len > 0) | |
614 | continue; | |
86eea289 KB |
615 | if (unlikely(dma_len < 0)) |
616 | goto bad_sgl; | |
e025344c SMM |
617 | sg = sg_next(sg); |
618 | dma_addr = sg_dma_address(sg); | |
619 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
620 | } |
621 | ||
86eea289 KB |
622 | return BLK_STS_OK; |
623 | ||
624 | bad_sgl: | |
625 | if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n", | |
626 | blk_rq_payload_bytes(req), iod->nents)) { | |
627 | for_each_sg(iod->sg, sg, iod->nents, i) { | |
628 | dma_addr_t phys = sg_phys(sg); | |
629 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " | |
630 | "dma_address:%pad dma_length:%d\n", i, &phys, | |
631 | sg->offset, sg->length, | |
632 | &sg_dma_address(sg), | |
633 | sg_dma_len(sg)); | |
634 | } | |
635 | } | |
636 | return BLK_STS_IOERR; | |
637 | ||
ff22b54f MW |
638 | } |
639 | ||
fc17b653 | 640 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 641 | struct nvme_command *cmnd) |
d29ec824 | 642 | { |
f4800d6d | 643 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ba1ca37e CH |
644 | struct request_queue *q = req->q; |
645 | enum dma_data_direction dma_dir = rq_data_dir(req) ? | |
646 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
fc17b653 | 647 | blk_status_t ret = BLK_STS_IOERR; |
d29ec824 | 648 | |
f9d03f96 | 649 | sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); |
ba1ca37e CH |
650 | iod->nents = blk_rq_map_sg(q, req, iod->sg); |
651 | if (!iod->nents) | |
652 | goto out; | |
d29ec824 | 653 | |
fc17b653 | 654 | ret = BLK_STS_RESOURCE; |
2b6b535d MFO |
655 | if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, |
656 | DMA_ATTR_NO_WARN)) | |
ba1ca37e | 657 | goto out; |
d29ec824 | 658 | |
86eea289 KB |
659 | ret = nvme_setup_prps(dev, req); |
660 | if (ret != BLK_STS_OK) | |
ba1ca37e | 661 | goto out_unmap; |
0e5e4f0e | 662 | |
fc17b653 | 663 | ret = BLK_STS_IOERR; |
ba1ca37e CH |
664 | if (blk_integrity_rq(req)) { |
665 | if (blk_rq_count_integrity_sg(q, req->bio) != 1) | |
666 | goto out_unmap; | |
0e5e4f0e | 667 | |
bf684057 CH |
668 | sg_init_table(&iod->meta_sg, 1); |
669 | if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) | |
ba1ca37e | 670 | goto out_unmap; |
0e5e4f0e | 671 | |
b5d8af5b | 672 | if (req_op(req) == REQ_OP_WRITE) |
ba1ca37e | 673 | nvme_dif_remap(req, nvme_dif_prep); |
0e5e4f0e | 674 | |
bf684057 | 675 | if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) |
ba1ca37e | 676 | goto out_unmap; |
d29ec824 | 677 | } |
00df5cb4 | 678 | |
eb793e2c CH |
679 | cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
680 | cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); | |
ba1ca37e | 681 | if (blk_integrity_rq(req)) |
bf684057 | 682 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); |
fc17b653 | 683 | return BLK_STS_OK; |
00df5cb4 | 684 | |
ba1ca37e CH |
685 | out_unmap: |
686 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
687 | out: | |
688 | return ret; | |
00df5cb4 MW |
689 | } |
690 | ||
f4800d6d | 691 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
b60503ba | 692 | { |
f4800d6d | 693 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
d4f6c3ab CH |
694 | enum dma_data_direction dma_dir = rq_data_dir(req) ? |
695 | DMA_TO_DEVICE : DMA_FROM_DEVICE; | |
696 | ||
697 | if (iod->nents) { | |
698 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
699 | if (blk_integrity_rq(req)) { | |
b5d8af5b | 700 | if (req_op(req) == REQ_OP_READ) |
d4f6c3ab | 701 | nvme_dif_remap(req, nvme_dif_complete); |
bf684057 | 702 | dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); |
e1e5e564 | 703 | } |
e19b127f | 704 | } |
e1e5e564 | 705 | |
f9d03f96 | 706 | nvme_cleanup_cmd(req); |
f4800d6d | 707 | nvme_free_iod(dev, req); |
d4f6c3ab | 708 | } |
b60503ba | 709 | |
d29ec824 CH |
710 | /* |
711 | * NOTE: ns is NULL when called on the admin queue. | |
712 | */ | |
fc17b653 | 713 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
a4aea562 | 714 | const struct blk_mq_queue_data *bd) |
edd10d33 | 715 | { |
a4aea562 MB |
716 | struct nvme_ns *ns = hctx->queue->queuedata; |
717 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 718 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 719 | struct request *req = bd->rq; |
ba1ca37e | 720 | struct nvme_command cmnd; |
ebe6d874 | 721 | blk_status_t ret; |
e1e5e564 | 722 | |
f9d03f96 | 723 | ret = nvme_setup_cmd(ns, req, &cmnd); |
fc17b653 | 724 | if (ret) |
f4800d6d | 725 | return ret; |
a4aea562 | 726 | |
b131c61d | 727 | ret = nvme_init_iod(req, dev); |
fc17b653 | 728 | if (ret) |
f9d03f96 | 729 | goto out_free_cmd; |
a4aea562 | 730 | |
fc17b653 | 731 | if (blk_rq_nr_phys_segments(req)) { |
b131c61d | 732 | ret = nvme_map_data(dev, req, &cmnd); |
fc17b653 CH |
733 | if (ret) |
734 | goto out_cleanup_iod; | |
735 | } | |
a4aea562 | 736 | |
aae239e1 | 737 | blk_mq_start_request(req); |
a4aea562 | 738 | |
ba1ca37e | 739 | spin_lock_irq(&nvmeq->q_lock); |
ae1fba20 | 740 | if (unlikely(nvmeq->cq_vector < 0)) { |
fc17b653 | 741 | ret = BLK_STS_IOERR; |
ae1fba20 | 742 | spin_unlock_irq(&nvmeq->q_lock); |
f9d03f96 | 743 | goto out_cleanup_iod; |
ae1fba20 | 744 | } |
ba1ca37e | 745 | __nvme_submit_cmd(nvmeq, &cmnd); |
a4aea562 MB |
746 | nvme_process_cq(nvmeq); |
747 | spin_unlock_irq(&nvmeq->q_lock); | |
fc17b653 | 748 | return BLK_STS_OK; |
f9d03f96 | 749 | out_cleanup_iod: |
f4800d6d | 750 | nvme_free_iod(dev, req); |
f9d03f96 CH |
751 | out_free_cmd: |
752 | nvme_cleanup_cmd(req); | |
ba1ca37e | 753 | return ret; |
b60503ba | 754 | } |
e1e5e564 | 755 | |
77f02a7a | 756 | static void nvme_pci_complete_rq(struct request *req) |
eee417b0 | 757 | { |
f4800d6d | 758 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
a4aea562 | 759 | |
77f02a7a CH |
760 | nvme_unmap_data(iod->nvmeq->dev, req); |
761 | nvme_complete_rq(req); | |
b60503ba MW |
762 | } |
763 | ||
d783e0bd MR |
764 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
765 | static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, | |
766 | u16 phase) | |
767 | { | |
768 | return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; | |
769 | } | |
770 | ||
eb281c82 | 771 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
b60503ba | 772 | { |
eb281c82 | 773 | u16 head = nvmeq->cq_head; |
adf68f21 | 774 | |
eb281c82 SG |
775 | if (likely(nvmeq->cq_vector >= 0)) { |
776 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, | |
777 | nvmeq->dbbuf_cq_ei)) | |
778 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
779 | } | |
780 | } | |
aae239e1 | 781 | |
83a12fb7 SG |
782 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, |
783 | struct nvme_completion *cqe) | |
784 | { | |
785 | struct request *req; | |
adf68f21 | 786 | |
83a12fb7 SG |
787 | if (unlikely(cqe->command_id >= nvmeq->q_depth)) { |
788 | dev_warn(nvmeq->dev->ctrl.device, | |
789 | "invalid id %d completed on queue %d\n", | |
790 | cqe->command_id, le16_to_cpu(cqe->sq_id)); | |
791 | return; | |
b60503ba MW |
792 | } |
793 | ||
83a12fb7 SG |
794 | /* |
795 | * AEN requests are special as they don't time out and can | |
796 | * survive any kind of queue freeze and often don't respond to | |
797 | * aborts. We don't even bother to allocate a struct request | |
798 | * for them but rather special case them here. | |
799 | */ | |
800 | if (unlikely(nvmeq->qid == 0 && | |
801 | cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) { | |
802 | nvme_complete_async_event(&nvmeq->dev->ctrl, | |
803 | cqe->status, &cqe->result); | |
a0fa9647 | 804 | return; |
83a12fb7 | 805 | } |
b60503ba | 806 | |
e9d8a0fd | 807 | nvmeq->cqe_seen = 1; |
83a12fb7 SG |
808 | req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); |
809 | nvme_end_request(req, cqe->status, cqe->result); | |
810 | } | |
b60503ba | 811 | |
920d13a8 SG |
812 | static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, |
813 | struct nvme_completion *cqe) | |
b60503ba | 814 | { |
920d13a8 SG |
815 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { |
816 | *cqe = nvmeq->cqes[nvmeq->cq_head]; | |
adf68f21 | 817 | |
920d13a8 SG |
818 | if (++nvmeq->cq_head == nvmeq->q_depth) { |
819 | nvmeq->cq_head = 0; | |
820 | nvmeq->cq_phase = !nvmeq->cq_phase; | |
b60503ba | 821 | } |
920d13a8 | 822 | return true; |
b60503ba | 823 | } |
920d13a8 | 824 | return false; |
a0fa9647 JA |
825 | } |
826 | ||
827 | static void nvme_process_cq(struct nvme_queue *nvmeq) | |
828 | { | |
920d13a8 SG |
829 | struct nvme_completion cqe; |
830 | int consumed = 0; | |
b60503ba | 831 | |
920d13a8 SG |
832 | while (nvme_read_cqe(nvmeq, &cqe)) { |
833 | nvme_handle_cqe(nvmeq, &cqe); | |
834 | consumed++; | |
920d13a8 | 835 | } |
eb281c82 | 836 | |
e9d8a0fd | 837 | if (consumed) |
920d13a8 | 838 | nvme_ring_cq_doorbell(nvmeq); |
b60503ba MW |
839 | } |
840 | ||
841 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
842 | { |
843 | irqreturn_t result; | |
844 | struct nvme_queue *nvmeq = data; | |
845 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
846 | nvme_process_cq(nvmeq); |
847 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
848 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
849 | spin_unlock(&nvmeq->q_lock); |
850 | return result; | |
851 | } | |
852 | ||
853 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
854 | { | |
855 | struct nvme_queue *nvmeq = data; | |
d783e0bd MR |
856 | if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
857 | return IRQ_WAKE_THREAD; | |
858 | return IRQ_NONE; | |
58ffacb5 MW |
859 | } |
860 | ||
7776db1c | 861 | static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) |
a0fa9647 | 862 | { |
442e19b7 SG |
863 | struct nvme_completion cqe; |
864 | int found = 0, consumed = 0; | |
a0fa9647 | 865 | |
442e19b7 SG |
866 | if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) |
867 | return 0; | |
a0fa9647 | 868 | |
442e19b7 SG |
869 | spin_lock_irq(&nvmeq->q_lock); |
870 | while (nvme_read_cqe(nvmeq, &cqe)) { | |
871 | nvme_handle_cqe(nvmeq, &cqe); | |
872 | consumed++; | |
873 | ||
874 | if (tag == cqe.command_id) { | |
875 | found = 1; | |
876 | break; | |
877 | } | |
878 | } | |
879 | ||
880 | if (consumed) | |
881 | nvme_ring_cq_doorbell(nvmeq); | |
882 | spin_unlock_irq(&nvmeq->q_lock); | |
883 | ||
884 | return found; | |
a0fa9647 JA |
885 | } |
886 | ||
7776db1c KB |
887 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) |
888 | { | |
889 | struct nvme_queue *nvmeq = hctx->driver_data; | |
890 | ||
891 | return __nvme_poll(nvmeq, tag); | |
892 | } | |
893 | ||
f866fc42 | 894 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) |
b60503ba | 895 | { |
f866fc42 | 896 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9396dec9 | 897 | struct nvme_queue *nvmeq = dev->queues[0]; |
a4aea562 | 898 | struct nvme_command c; |
b60503ba | 899 | |
a4aea562 MB |
900 | memset(&c, 0, sizeof(c)); |
901 | c.common.opcode = nvme_admin_async_event; | |
f866fc42 | 902 | c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; |
3c0cf138 | 903 | |
9396dec9 | 904 | spin_lock_irq(&nvmeq->q_lock); |
f866fc42 | 905 | __nvme_submit_cmd(nvmeq, &c); |
9396dec9 | 906 | spin_unlock_irq(&nvmeq->q_lock); |
f705f837 CH |
907 | } |
908 | ||
b60503ba | 909 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 910 | { |
b60503ba MW |
911 | struct nvme_command c; |
912 | ||
913 | memset(&c, 0, sizeof(c)); | |
914 | c.delete_queue.opcode = opcode; | |
915 | c.delete_queue.qid = cpu_to_le16(id); | |
916 | ||
1c63dc66 | 917 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
918 | } |
919 | ||
b60503ba MW |
920 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
921 | struct nvme_queue *nvmeq) | |
922 | { | |
b60503ba MW |
923 | struct nvme_command c; |
924 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
925 | ||
d29ec824 CH |
926 | /* |
927 | * Note: we (ab)use the fact the the prp fields survive if no data | |
928 | * is attached to the request. | |
929 | */ | |
b60503ba MW |
930 | memset(&c, 0, sizeof(c)); |
931 | c.create_cq.opcode = nvme_admin_create_cq; | |
932 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
933 | c.create_cq.cqid = cpu_to_le16(qid); | |
934 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
935 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
936 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
937 | ||
1c63dc66 | 938 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
939 | } |
940 | ||
941 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
942 | struct nvme_queue *nvmeq) | |
943 | { | |
b60503ba | 944 | struct nvme_command c; |
81c1cd98 | 945 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 946 | |
d29ec824 CH |
947 | /* |
948 | * Note: we (ab)use the fact the the prp fields survive if no data | |
949 | * is attached to the request. | |
950 | */ | |
b60503ba MW |
951 | memset(&c, 0, sizeof(c)); |
952 | c.create_sq.opcode = nvme_admin_create_sq; | |
953 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
954 | c.create_sq.sqid = cpu_to_le16(qid); | |
955 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
956 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
957 | c.create_sq.cqid = cpu_to_le16(qid); | |
958 | ||
1c63dc66 | 959 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
960 | } |
961 | ||
962 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
963 | { | |
964 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
965 | } | |
966 | ||
967 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
968 | { | |
969 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
970 | } | |
971 | ||
2a842aca | 972 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 973 | { |
f4800d6d CH |
974 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
975 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 976 | |
27fa9bc5 CH |
977 | dev_warn(nvmeq->dev->ctrl.device, |
978 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 979 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 980 | blk_mq_free_request(req); |
bc5fc7e4 MW |
981 | } |
982 | ||
b2a0eb1a KB |
983 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
984 | { | |
985 | ||
986 | /* If true, indicates loss of adapter communication, possibly by a | |
987 | * NVMe Subsystem reset. | |
988 | */ | |
989 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
990 | ||
991 | /* If there is a reset ongoing, we shouldn't reset again. */ | |
992 | if (dev->ctrl.state == NVME_CTRL_RESETTING) | |
993 | return false; | |
994 | ||
995 | /* We shouldn't reset unless the controller is on fatal error state | |
996 | * _or_ if we lost the communication with it. | |
997 | */ | |
998 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
999 | return false; | |
1000 | ||
1001 | /* If PCI error recovery process is happening, we cannot reset or | |
1002 | * the recovery mechanism will surely fail. | |
1003 | */ | |
1004 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1005 | return false; | |
1006 | ||
1007 | return true; | |
1008 | } | |
1009 | ||
1010 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
1011 | { | |
1012 | /* Read a config register to help see what died. */ | |
1013 | u16 pci_status; | |
1014 | int result; | |
1015 | ||
1016 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1017 | &pci_status); | |
1018 | if (result == PCIBIOS_SUCCESSFUL) | |
1019 | dev_warn(dev->ctrl.device, | |
1020 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1021 | csts, pci_status); | |
1022 | else | |
1023 | dev_warn(dev->ctrl.device, | |
1024 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1025 | csts, result); | |
1026 | } | |
1027 | ||
31c7c7d2 | 1028 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
c30341dc | 1029 | { |
f4800d6d CH |
1030 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1031 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 1032 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 1033 | struct request *abort_req; |
a4aea562 | 1034 | struct nvme_command cmd; |
b2a0eb1a KB |
1035 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
1036 | ||
1037 | /* | |
1038 | * Reset immediately if the controller is failed | |
1039 | */ | |
1040 | if (nvme_should_reset(dev, csts)) { | |
1041 | nvme_warn_reset(dev, csts); | |
1042 | nvme_dev_disable(dev, false); | |
d86c4d8e | 1043 | nvme_reset_ctrl(&dev->ctrl); |
b2a0eb1a KB |
1044 | return BLK_EH_HANDLED; |
1045 | } | |
c30341dc | 1046 | |
7776db1c KB |
1047 | /* |
1048 | * Did we miss an interrupt? | |
1049 | */ | |
1050 | if (__nvme_poll(nvmeq, req->tag)) { | |
1051 | dev_warn(dev->ctrl.device, | |
1052 | "I/O %d QID %d timeout, completion polled\n", | |
1053 | req->tag, nvmeq->qid); | |
1054 | return BLK_EH_HANDLED; | |
1055 | } | |
1056 | ||
31c7c7d2 | 1057 | /* |
fd634f41 CH |
1058 | * Shutdown immediately if controller times out while starting. The |
1059 | * reset work will see the pci device disabled when it gets the forced | |
1060 | * cancellation error. All outstanding requests are completed on | |
1061 | * shutdown, so we return BLK_EH_HANDLED. | |
1062 | */ | |
bb8d261e | 1063 | if (dev->ctrl.state == NVME_CTRL_RESETTING) { |
1b3c47c1 | 1064 | dev_warn(dev->ctrl.device, |
fd634f41 CH |
1065 | "I/O %d QID %d timeout, disable controller\n", |
1066 | req->tag, nvmeq->qid); | |
a5cdb68c | 1067 | nvme_dev_disable(dev, false); |
27fa9bc5 | 1068 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
fd634f41 | 1069 | return BLK_EH_HANDLED; |
c30341dc KB |
1070 | } |
1071 | ||
fd634f41 CH |
1072 | /* |
1073 | * Shutdown the controller immediately and schedule a reset if the | |
1074 | * command was already aborted once before and still hasn't been | |
1075 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1076 | */ |
f4800d6d | 1077 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1078 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1079 | "I/O %d QID %d timeout, reset controller\n", |
1080 | req->tag, nvmeq->qid); | |
a5cdb68c | 1081 | nvme_dev_disable(dev, false); |
d86c4d8e | 1082 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1083 | |
e1569a16 KB |
1084 | /* |
1085 | * Mark the request as handled, since the inline shutdown | |
1086 | * forces all outstanding requests to complete. | |
1087 | */ | |
27fa9bc5 | 1088 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
e1569a16 | 1089 | return BLK_EH_HANDLED; |
c30341dc | 1090 | } |
c30341dc | 1091 | |
e7a2a87d | 1092 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1093 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1094 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1095 | } |
7bf7d778 | 1096 | iod->aborted = 1; |
a4aea562 | 1097 | |
c30341dc KB |
1098 | memset(&cmd, 0, sizeof(cmd)); |
1099 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1100 | cmd.abort.cid = req->tag; |
c30341dc | 1101 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1102 | |
1b3c47c1 SG |
1103 | dev_warn(nvmeq->dev->ctrl.device, |
1104 | "I/O %d QID %d timeout, aborting\n", | |
1105 | req->tag, nvmeq->qid); | |
e7a2a87d CH |
1106 | |
1107 | abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, | |
eb71f435 | 1108 | BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
e7a2a87d CH |
1109 | if (IS_ERR(abort_req)) { |
1110 | atomic_inc(&dev->ctrl.abort_limit); | |
1111 | return BLK_EH_RESET_TIMER; | |
1112 | } | |
1113 | ||
1114 | abort_req->timeout = ADMIN_TIMEOUT; | |
1115 | abort_req->end_io_data = NULL; | |
1116 | blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); | |
c30341dc | 1117 | |
31c7c7d2 CH |
1118 | /* |
1119 | * The aborted req will be completed on receiving the abort req. | |
1120 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1121 | * as the device then is in a faulty state. | |
1122 | */ | |
1123 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1124 | } |
1125 | ||
a4aea562 MB |
1126 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1127 | { | |
9e866774 MW |
1128 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1129 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
8ffaadf7 JD |
1130 | if (nvmeq->sq_cmds) |
1131 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
9e866774 MW |
1132 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
1133 | kfree(nvmeq); | |
1134 | } | |
1135 | ||
a1a5ef99 | 1136 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1137 | { |
1138 | int i; | |
1139 | ||
d858e5f0 | 1140 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1141 | struct nvme_queue *nvmeq = dev->queues[i]; |
d858e5f0 | 1142 | dev->ctrl.queue_count--; |
a4aea562 | 1143 | dev->queues[i] = NULL; |
f435c282 | 1144 | nvme_free_queue(nvmeq); |
121c7ad4 | 1145 | } |
22404274 KB |
1146 | } |
1147 | ||
4d115420 KB |
1148 | /** |
1149 | * nvme_suspend_queue - put queue into suspended state | |
1150 | * @nvmeq - queue to suspend | |
4d115420 KB |
1151 | */ |
1152 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1153 | { |
2b25d981 | 1154 | int vector; |
b60503ba | 1155 | |
a09115b2 | 1156 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1157 | if (nvmeq->cq_vector == -1) { |
1158 | spin_unlock_irq(&nvmeq->q_lock); | |
1159 | return 1; | |
1160 | } | |
0ff199cb | 1161 | vector = nvmeq->cq_vector; |
42f61420 | 1162 | nvmeq->dev->online_queues--; |
2b25d981 | 1163 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1164 | spin_unlock_irq(&nvmeq->q_lock); |
1165 | ||
1c63dc66 | 1166 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
c81545f9 | 1167 | blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); |
6df3dbc8 | 1168 | |
0ff199cb | 1169 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); |
b60503ba | 1170 | |
4d115420 KB |
1171 | return 0; |
1172 | } | |
b60503ba | 1173 | |
a5cdb68c | 1174 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1175 | { |
a5cdb68c | 1176 | struct nvme_queue *nvmeq = dev->queues[0]; |
4d115420 KB |
1177 | |
1178 | if (!nvmeq) | |
1179 | return; | |
1180 | if (nvme_suspend_queue(nvmeq)) | |
1181 | return; | |
1182 | ||
a5cdb68c KB |
1183 | if (shutdown) |
1184 | nvme_shutdown_ctrl(&dev->ctrl); | |
1185 | else | |
20d0dfe6 | 1186 | nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
07836e65 KB |
1187 | |
1188 | spin_lock_irq(&nvmeq->q_lock); | |
1189 | nvme_process_cq(nvmeq); | |
1190 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1191 | } |
1192 | ||
8ffaadf7 JD |
1193 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1194 | int entry_size) | |
1195 | { | |
1196 | int q_depth = dev->q_depth; | |
5fd4ce1b CH |
1197 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
1198 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1199 | |
1200 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1201 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
5fd4ce1b | 1202 | mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); |
c45f5c99 | 1203 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1204 | |
1205 | /* | |
1206 | * Ensure the reduced q_depth is above some threshold where it | |
1207 | * would be better to map queues in system memory with the | |
1208 | * original depth | |
1209 | */ | |
1210 | if (q_depth < 64) | |
1211 | return -ENOMEM; | |
1212 | } | |
1213 | ||
1214 | return q_depth; | |
1215 | } | |
1216 | ||
1217 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
1218 | int qid, int depth) | |
1219 | { | |
1220 | if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { | |
5fd4ce1b CH |
1221 | unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), |
1222 | dev->ctrl.page_size); | |
8ffaadf7 JD |
1223 | nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; |
1224 | nvmeq->sq_cmds_io = dev->cmb + offset; | |
1225 | } else { | |
1226 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), | |
1227 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
1228 | if (!nvmeq->sq_cmds) | |
1229 | return -ENOMEM; | |
1230 | } | |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
b60503ba | 1235 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, |
d3af3ecd | 1236 | int depth, int node) |
b60503ba | 1237 | { |
d3af3ecd SL |
1238 | struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, |
1239 | node); | |
b60503ba MW |
1240 | if (!nvmeq) |
1241 | return NULL; | |
1242 | ||
e75ec752 | 1243 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1244 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1245 | if (!nvmeq->cqes) |
1246 | goto free_nvmeq; | |
b60503ba | 1247 | |
8ffaadf7 | 1248 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) |
b60503ba MW |
1249 | goto free_cqdma; |
1250 | ||
e75ec752 | 1251 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1252 | nvmeq->dev = dev; |
b60503ba MW |
1253 | spin_lock_init(&nvmeq->q_lock); |
1254 | nvmeq->cq_head = 0; | |
82123460 | 1255 | nvmeq->cq_phase = 1; |
b80d5ccc | 1256 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1257 | nvmeq->q_depth = depth; |
c30341dc | 1258 | nvmeq->qid = qid; |
758dd7fd | 1259 | nvmeq->cq_vector = -1; |
a4aea562 | 1260 | dev->queues[qid] = nvmeq; |
d858e5f0 | 1261 | dev->ctrl.queue_count++; |
36a7e993 | 1262 | |
b60503ba MW |
1263 | return nvmeq; |
1264 | ||
1265 | free_cqdma: | |
e75ec752 | 1266 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1267 | nvmeq->cq_dma_addr); |
1268 | free_nvmeq: | |
1269 | kfree(nvmeq); | |
1270 | return NULL; | |
1271 | } | |
1272 | ||
dca51e78 | 1273 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1274 | { |
0ff199cb CH |
1275 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1276 | int nr = nvmeq->dev->ctrl.instance; | |
1277 | ||
1278 | if (use_threaded_interrupts) { | |
1279 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1280 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1281 | } else { | |
1282 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1283 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1284 | } | |
3001082c MW |
1285 | } |
1286 | ||
22404274 | 1287 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1288 | { |
22404274 | 1289 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1290 | |
7be50e93 | 1291 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1292 | nvmeq->sq_tail = 0; |
1293 | nvmeq->cq_head = 0; | |
1294 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1295 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1296 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
f9f38e33 | 1297 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1298 | dev->online_queues++; |
7be50e93 | 1299 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1300 | } |
1301 | ||
1302 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1303 | { | |
1304 | struct nvme_dev *dev = nvmeq->dev; | |
1305 | int result; | |
3f85d50b | 1306 | |
2b25d981 | 1307 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1308 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1309 | if (result < 0) | |
22404274 | 1310 | return result; |
b60503ba MW |
1311 | |
1312 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1313 | if (result < 0) | |
1314 | goto release_cq; | |
1315 | ||
161b8be2 | 1316 | nvme_init_queue(nvmeq, qid); |
dca51e78 | 1317 | result = queue_request_irq(nvmeq); |
b60503ba MW |
1318 | if (result < 0) |
1319 | goto release_sq; | |
1320 | ||
22404274 | 1321 | return result; |
b60503ba MW |
1322 | |
1323 | release_sq: | |
1324 | adapter_delete_sq(dev, qid); | |
1325 | release_cq: | |
1326 | adapter_delete_cq(dev, qid); | |
22404274 | 1327 | return result; |
b60503ba MW |
1328 | } |
1329 | ||
f363b089 | 1330 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1331 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1332 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1333 | .init_hctx = nvme_admin_init_hctx, |
4af0e21c | 1334 | .exit_hctx = nvme_admin_exit_hctx, |
0350815a | 1335 | .init_request = nvme_init_request, |
a4aea562 MB |
1336 | .timeout = nvme_timeout, |
1337 | }; | |
1338 | ||
f363b089 | 1339 | static const struct blk_mq_ops nvme_mq_ops = { |
a4aea562 | 1340 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1341 | .complete = nvme_pci_complete_rq, |
a4aea562 MB |
1342 | .init_hctx = nvme_init_hctx, |
1343 | .init_request = nvme_init_request, | |
dca51e78 | 1344 | .map_queues = nvme_pci_map_queues, |
a4aea562 | 1345 | .timeout = nvme_timeout, |
a0fa9647 | 1346 | .poll = nvme_poll, |
a4aea562 MB |
1347 | }; |
1348 | ||
ea191d2f KB |
1349 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1350 | { | |
1c63dc66 | 1351 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1352 | /* |
1353 | * If the controller was reset during removal, it's possible | |
1354 | * user requests may be waiting on a stopped queue. Start the | |
1355 | * queue to flush these to completion. | |
1356 | */ | |
c81545f9 | 1357 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
1c63dc66 | 1358 | blk_cleanup_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1359 | blk_mq_free_tag_set(&dev->admin_tagset); |
1360 | } | |
1361 | } | |
1362 | ||
a4aea562 MB |
1363 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1364 | { | |
1c63dc66 | 1365 | if (!dev->ctrl.admin_q) { |
a4aea562 MB |
1366 | dev->admin_tagset.ops = &nvme_mq_admin_ops; |
1367 | dev->admin_tagset.nr_hw_queues = 1; | |
e3e9d50c KB |
1368 | |
1369 | /* | |
1370 | * Subtract one to leave an empty queue entry for 'Full Queue' | |
1371 | * condition. See NVM-Express 1.2 specification, section 4.1.2. | |
1372 | */ | |
1373 | dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; | |
a4aea562 | 1374 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1375 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1376 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
d3484991 | 1377 | dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; |
a4aea562 MB |
1378 | dev->admin_tagset.driver_data = dev; |
1379 | ||
1380 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1381 | return -ENOMEM; | |
34b6c231 | 1382 | dev->ctrl.admin_tagset = &dev->admin_tagset; |
a4aea562 | 1383 | |
1c63dc66 CH |
1384 | dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); |
1385 | if (IS_ERR(dev->ctrl.admin_q)) { | |
a4aea562 MB |
1386 | blk_mq_free_tag_set(&dev->admin_tagset); |
1387 | return -ENOMEM; | |
1388 | } | |
1c63dc66 | 1389 | if (!blk_get_queue(dev->ctrl.admin_q)) { |
ea191d2f | 1390 | nvme_dev_remove_admin(dev); |
1c63dc66 | 1391 | dev->ctrl.admin_q = NULL; |
ea191d2f KB |
1392 | return -ENODEV; |
1393 | } | |
0fb59cbc | 1394 | } else |
c81545f9 | 1395 | blk_mq_unquiesce_queue(dev->ctrl.admin_q); |
a4aea562 MB |
1396 | |
1397 | return 0; | |
1398 | } | |
1399 | ||
97f6ef64 XY |
1400 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1401 | { | |
1402 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1403 | } | |
1404 | ||
1405 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1406 | { | |
1407 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1408 | ||
1409 | if (size <= dev->bar_mapped_size) | |
1410 | return 0; | |
1411 | if (size > pci_resource_len(pdev, 0)) | |
1412 | return -ENOMEM; | |
1413 | if (dev->bar) | |
1414 | iounmap(dev->bar); | |
1415 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1416 | if (!dev->bar) { | |
1417 | dev->bar_mapped_size = 0; | |
1418 | return -ENOMEM; | |
1419 | } | |
1420 | dev->bar_mapped_size = size; | |
1421 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1422 | ||
1423 | return 0; | |
1424 | } | |
1425 | ||
01ad0990 | 1426 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1427 | { |
ba47e386 | 1428 | int result; |
b60503ba MW |
1429 | u32 aqa; |
1430 | struct nvme_queue *nvmeq; | |
1431 | ||
97f6ef64 XY |
1432 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1433 | if (result < 0) | |
1434 | return result; | |
1435 | ||
8ef2074d | 1436 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
20d0dfe6 | 1437 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
dfbac8c7 | 1438 | |
7a67cbea CH |
1439 | if (dev->subsystem && |
1440 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1441 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1442 | |
20d0dfe6 | 1443 | result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); |
ba47e386 MW |
1444 | if (result < 0) |
1445 | return result; | |
b60503ba | 1446 | |
a4aea562 | 1447 | nvmeq = dev->queues[0]; |
cd638946 | 1448 | if (!nvmeq) { |
d3af3ecd SL |
1449 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, |
1450 | dev_to_node(dev->dev)); | |
cd638946 KB |
1451 | if (!nvmeq) |
1452 | return -ENOMEM; | |
cd638946 | 1453 | } |
b60503ba MW |
1454 | |
1455 | aqa = nvmeq->q_depth - 1; | |
1456 | aqa |= aqa << 16; | |
1457 | ||
7a67cbea CH |
1458 | writel(aqa, dev->bar + NVME_REG_AQA); |
1459 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1460 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1461 | |
20d0dfe6 | 1462 | result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); |
025c557a | 1463 | if (result) |
d4875622 | 1464 | return result; |
a4aea562 | 1465 | |
2b25d981 | 1466 | nvmeq->cq_vector = 0; |
161b8be2 | 1467 | nvme_init_queue(nvmeq, 0); |
dca51e78 | 1468 | result = queue_request_irq(nvmeq); |
758dd7fd JD |
1469 | if (result) { |
1470 | nvmeq->cq_vector = -1; | |
d4875622 | 1471 | return result; |
758dd7fd | 1472 | } |
025c557a | 1473 | |
b60503ba MW |
1474 | return result; |
1475 | } | |
1476 | ||
749941f2 | 1477 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1478 | { |
949928c1 | 1479 | unsigned i, max; |
749941f2 | 1480 | int ret = 0; |
42f61420 | 1481 | |
d858e5f0 | 1482 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
d3af3ecd SL |
1483 | /* vector == qid - 1, match nvme_create_queue */ |
1484 | if (!nvme_alloc_queue(dev, i, dev->q_depth, | |
1485 | pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { | |
749941f2 | 1486 | ret = -ENOMEM; |
42f61420 | 1487 | break; |
749941f2 CH |
1488 | } |
1489 | } | |
42f61420 | 1490 | |
d858e5f0 | 1491 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
949928c1 | 1492 | for (i = dev->online_queues; i <= max; i++) { |
749941f2 | 1493 | ret = nvme_create_queue(dev->queues[i], i); |
d4875622 | 1494 | if (ret) |
42f61420 | 1495 | break; |
27e8166c | 1496 | } |
749941f2 CH |
1497 | |
1498 | /* | |
1499 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
1500 | * than the desired aount of queues, and even a controller without | |
1501 | * I/O queues an still be used to issue admin commands. This might | |
1502 | * be useful to upgrade a buggy firmware for example. | |
1503 | */ | |
1504 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1505 | } |
1506 | ||
202021c1 SB |
1507 | static ssize_t nvme_cmb_show(struct device *dev, |
1508 | struct device_attribute *attr, | |
1509 | char *buf) | |
1510 | { | |
1511 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
1512 | ||
c965809c | 1513 | return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", |
202021c1 SB |
1514 | ndev->cmbloc, ndev->cmbsz); |
1515 | } | |
1516 | static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); | |
1517 | ||
8ffaadf7 JD |
1518 | static void __iomem *nvme_map_cmb(struct nvme_dev *dev) |
1519 | { | |
1520 | u64 szu, size, offset; | |
8ffaadf7 JD |
1521 | resource_size_t bar_size; |
1522 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1523 | void __iomem *cmb; | |
1524 | dma_addr_t dma_addr; | |
1525 | ||
7a67cbea | 1526 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
8ffaadf7 JD |
1527 | if (!(NVME_CMB_SZ(dev->cmbsz))) |
1528 | return NULL; | |
202021c1 | 1529 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1530 | |
202021c1 SB |
1531 | if (!use_cmb_sqes) |
1532 | return NULL; | |
8ffaadf7 JD |
1533 | |
1534 | szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); | |
1535 | size = szu * NVME_CMB_SZ(dev->cmbsz); | |
202021c1 SB |
1536 | offset = szu * NVME_CMB_OFST(dev->cmbloc); |
1537 | bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); | |
8ffaadf7 JD |
1538 | |
1539 | if (offset > bar_size) | |
1540 | return NULL; | |
1541 | ||
1542 | /* | |
1543 | * Controllers may support a CMB size larger than their BAR, | |
1544 | * for example, due to being behind a bridge. Reduce the CMB to | |
1545 | * the reported size of the BAR | |
1546 | */ | |
1547 | if (size > bar_size - offset) | |
1548 | size = bar_size - offset; | |
1549 | ||
202021c1 | 1550 | dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; |
8ffaadf7 JD |
1551 | cmb = ioremap_wc(dma_addr, size); |
1552 | if (!cmb) | |
1553 | return NULL; | |
1554 | ||
1555 | dev->cmb_dma_addr = dma_addr; | |
1556 | dev->cmb_size = size; | |
1557 | return cmb; | |
1558 | } | |
1559 | ||
1560 | static inline void nvme_release_cmb(struct nvme_dev *dev) | |
1561 | { | |
1562 | if (dev->cmb) { | |
1563 | iounmap(dev->cmb); | |
1564 | dev->cmb = NULL; | |
1c78f773 MG |
1565 | sysfs_remove_file_from_group(&dev->ctrl.device->kobj, |
1566 | &dev_attr_cmb.attr, NULL); | |
1567 | dev->cmbsz = 0; | |
8ffaadf7 JD |
1568 | } |
1569 | } | |
1570 | ||
87ad72a5 CH |
1571 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1572 | { | |
4033f35d | 1573 | u64 dma_addr = dev->host_mem_descs_dma; |
87ad72a5 | 1574 | struct nvme_command c; |
87ad72a5 CH |
1575 | int ret; |
1576 | ||
87ad72a5 CH |
1577 | memset(&c, 0, sizeof(c)); |
1578 | c.features.opcode = nvme_admin_set_features; | |
1579 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1580 | c.features.dword11 = cpu_to_le32(bits); | |
1581 | c.features.dword12 = cpu_to_le32(dev->host_mem_size >> | |
1582 | ilog2(dev->ctrl.page_size)); | |
1583 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); | |
1584 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1585 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1586 | ||
1587 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1588 | if (ret) { | |
1589 | dev_warn(dev->ctrl.device, | |
1590 | "failed to set host mem (err %d, flags %#x).\n", | |
1591 | ret, bits); | |
1592 | } | |
87ad72a5 CH |
1593 | return ret; |
1594 | } | |
1595 | ||
1596 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
1597 | { | |
1598 | int i; | |
1599 | ||
1600 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
1601 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
1602 | size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; | |
1603 | ||
1604 | dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], | |
1605 | le64_to_cpu(desc->addr)); | |
1606 | } | |
1607 | ||
1608 | kfree(dev->host_mem_desc_bufs); | |
1609 | dev->host_mem_desc_bufs = NULL; | |
4033f35d CH |
1610 | dma_free_coherent(dev->dev, |
1611 | dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), | |
1612 | dev->host_mem_descs, dev->host_mem_descs_dma); | |
87ad72a5 CH |
1613 | dev->host_mem_descs = NULL; |
1614 | } | |
1615 | ||
92dc6895 CH |
1616 | static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, |
1617 | u32 chunk_size) | |
9d713c2b | 1618 | { |
87ad72a5 | 1619 | struct nvme_host_mem_buf_desc *descs; |
92dc6895 | 1620 | u32 max_entries, len; |
4033f35d | 1621 | dma_addr_t descs_dma; |
2ee0e4ed | 1622 | int i = 0; |
87ad72a5 | 1623 | void **bufs; |
2ee0e4ed | 1624 | u64 size = 0, tmp; |
87ad72a5 | 1625 | |
87ad72a5 CH |
1626 | tmp = (preferred + chunk_size - 1); |
1627 | do_div(tmp, chunk_size); | |
1628 | max_entries = tmp; | |
044a9df1 CH |
1629 | |
1630 | if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) | |
1631 | max_entries = dev->ctrl.hmmaxd; | |
1632 | ||
4033f35d CH |
1633 | descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), |
1634 | &descs_dma, GFP_KERNEL); | |
87ad72a5 CH |
1635 | if (!descs) |
1636 | goto out; | |
1637 | ||
1638 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
1639 | if (!bufs) | |
1640 | goto out_free_descs; | |
1641 | ||
50cdb7c6 | 1642 | for (size = 0; size < preferred; size += len) { |
87ad72a5 CH |
1643 | dma_addr_t dma_addr; |
1644 | ||
50cdb7c6 | 1645 | len = min_t(u64, chunk_size, preferred - size); |
87ad72a5 CH |
1646 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, |
1647 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
1648 | if (!bufs[i]) | |
1649 | break; | |
1650 | ||
1651 | descs[i].addr = cpu_to_le64(dma_addr); | |
1652 | descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); | |
1653 | i++; | |
1654 | } | |
1655 | ||
92dc6895 | 1656 | if (!size) |
87ad72a5 | 1657 | goto out_free_bufs; |
87ad72a5 | 1658 | |
87ad72a5 CH |
1659 | dev->nr_host_mem_descs = i; |
1660 | dev->host_mem_size = size; | |
1661 | dev->host_mem_descs = descs; | |
4033f35d | 1662 | dev->host_mem_descs_dma = descs_dma; |
87ad72a5 CH |
1663 | dev->host_mem_desc_bufs = bufs; |
1664 | return 0; | |
1665 | ||
1666 | out_free_bufs: | |
1667 | while (--i >= 0) { | |
1668 | size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; | |
1669 | ||
1670 | dma_free_coherent(dev->dev, size, bufs[i], | |
1671 | le64_to_cpu(descs[i].addr)); | |
1672 | } | |
1673 | ||
1674 | kfree(bufs); | |
1675 | out_free_descs: | |
4033f35d CH |
1676 | dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, |
1677 | descs_dma); | |
87ad72a5 | 1678 | out: |
87ad72a5 CH |
1679 | dev->host_mem_descs = NULL; |
1680 | return -ENOMEM; | |
1681 | } | |
1682 | ||
92dc6895 CH |
1683 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) |
1684 | { | |
1685 | u32 chunk_size; | |
1686 | ||
1687 | /* start big and work our way down */ | |
30f92d62 | 1688 | for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); |
044a9df1 | 1689 | chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); |
92dc6895 CH |
1690 | chunk_size /= 2) { |
1691 | if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { | |
1692 | if (!min || dev->host_mem_size >= min) | |
1693 | return 0; | |
1694 | nvme_free_host_mem(dev); | |
1695 | } | |
1696 | } | |
1697 | ||
1698 | return -ENOMEM; | |
1699 | } | |
1700 | ||
9620cfba | 1701 | static int nvme_setup_host_mem(struct nvme_dev *dev) |
87ad72a5 CH |
1702 | { |
1703 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
1704 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
1705 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
1706 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
9620cfba | 1707 | int ret = 0; |
87ad72a5 CH |
1708 | |
1709 | preferred = min(preferred, max); | |
1710 | if (min > max) { | |
1711 | dev_warn(dev->ctrl.device, | |
1712 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
1713 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
1714 | nvme_free_host_mem(dev); | |
9620cfba | 1715 | return 0; |
87ad72a5 CH |
1716 | } |
1717 | ||
1718 | /* | |
1719 | * If we already have a buffer allocated check if we can reuse it. | |
1720 | */ | |
1721 | if (dev->host_mem_descs) { | |
1722 | if (dev->host_mem_size >= min) | |
1723 | enable_bits |= NVME_HOST_MEM_RETURN; | |
1724 | else | |
1725 | nvme_free_host_mem(dev); | |
1726 | } | |
1727 | ||
1728 | if (!dev->host_mem_descs) { | |
92dc6895 CH |
1729 | if (nvme_alloc_host_mem(dev, min, preferred)) { |
1730 | dev_warn(dev->ctrl.device, | |
1731 | "failed to allocate host memory buffer.\n"); | |
9620cfba | 1732 | return 0; /* controller must work without HMB */ |
92dc6895 CH |
1733 | } |
1734 | ||
1735 | dev_info(dev->ctrl.device, | |
1736 | "allocated %lld MiB host memory buffer.\n", | |
1737 | dev->host_mem_size >> ilog2(SZ_1M)); | |
87ad72a5 CH |
1738 | } |
1739 | ||
9620cfba CH |
1740 | ret = nvme_set_host_mem(dev, enable_bits); |
1741 | if (ret) | |
87ad72a5 | 1742 | nvme_free_host_mem(dev); |
9620cfba | 1743 | return ret; |
9d713c2b KB |
1744 | } |
1745 | ||
8d85fce7 | 1746 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 1747 | { |
a4aea562 | 1748 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 1749 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
97f6ef64 XY |
1750 | int result, nr_io_queues; |
1751 | unsigned long size; | |
b60503ba | 1752 | |
425a17cb | 1753 | nr_io_queues = num_present_cpus(); |
9a0be7ab CH |
1754 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
1755 | if (result < 0) | |
1b23484b | 1756 | return result; |
9a0be7ab | 1757 | |
f5fa90dc | 1758 | if (nr_io_queues == 0) |
a5229050 | 1759 | return 0; |
b60503ba | 1760 | |
8ffaadf7 JD |
1761 | if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { |
1762 | result = nvme_cmb_qdepth(dev, nr_io_queues, | |
1763 | sizeof(struct nvme_command)); | |
1764 | if (result > 0) | |
1765 | dev->q_depth = result; | |
1766 | else | |
1767 | nvme_release_cmb(dev); | |
1768 | } | |
1769 | ||
97f6ef64 XY |
1770 | do { |
1771 | size = db_bar_size(dev, nr_io_queues); | |
1772 | result = nvme_remap_bar(dev, size); | |
1773 | if (!result) | |
1774 | break; | |
1775 | if (!--nr_io_queues) | |
1776 | return -ENOMEM; | |
1777 | } while (1); | |
1778 | adminq->q_db = dev->dbs; | |
f1938f6e | 1779 | |
9d713c2b | 1780 | /* Deregister the admin queue's interrupt */ |
0ff199cb | 1781 | pci_free_irq(pdev, 0, adminq); |
9d713c2b | 1782 | |
e32efbfc JA |
1783 | /* |
1784 | * If we enable msix early due to not intx, disable it again before | |
1785 | * setting up the full range we need. | |
1786 | */ | |
dca51e78 CH |
1787 | pci_free_irq_vectors(pdev); |
1788 | nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, | |
1789 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); | |
1790 | if (nr_io_queues <= 0) | |
1791 | return -EIO; | |
1792 | dev->max_qid = nr_io_queues; | |
fa08a396 | 1793 | |
063a8096 MW |
1794 | /* |
1795 | * Should investigate if there's a performance win from allocating | |
1796 | * more queues than interrupt vectors; it might allow the submission | |
1797 | * path to scale better, even if the receive path is limited by the | |
1798 | * number of interrupts. | |
1799 | */ | |
063a8096 | 1800 | |
dca51e78 | 1801 | result = queue_request_irq(adminq); |
758dd7fd JD |
1802 | if (result) { |
1803 | adminq->cq_vector = -1; | |
d4875622 | 1804 | return result; |
758dd7fd | 1805 | } |
749941f2 | 1806 | return nvme_create_io_queues(dev); |
b60503ba MW |
1807 | } |
1808 | ||
2a842aca | 1809 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 1810 | { |
db3cbfff | 1811 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 1812 | |
db3cbfff KB |
1813 | blk_mq_free_request(req); |
1814 | complete(&nvmeq->dev->ioq_wait); | |
a5768aa8 KB |
1815 | } |
1816 | ||
2a842aca | 1817 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 1818 | { |
db3cbfff | 1819 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 1820 | |
db3cbfff KB |
1821 | if (!error) { |
1822 | unsigned long flags; | |
1823 | ||
2e39e0f6 ML |
1824 | /* |
1825 | * We might be called with the AQ q_lock held | |
1826 | * and the I/O queue q_lock should always | |
1827 | * nest inside the AQ one. | |
1828 | */ | |
1829 | spin_lock_irqsave_nested(&nvmeq->q_lock, flags, | |
1830 | SINGLE_DEPTH_NESTING); | |
db3cbfff KB |
1831 | nvme_process_cq(nvmeq); |
1832 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
a5768aa8 | 1833 | } |
db3cbfff KB |
1834 | |
1835 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
1836 | } |
1837 | ||
db3cbfff | 1838 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 1839 | { |
db3cbfff KB |
1840 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
1841 | struct request *req; | |
1842 | struct nvme_command cmd; | |
bda4e0fb | 1843 | |
db3cbfff KB |
1844 | memset(&cmd, 0, sizeof(cmd)); |
1845 | cmd.delete_queue.opcode = opcode; | |
1846 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 1847 | |
eb71f435 | 1848 | req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); |
db3cbfff KB |
1849 | if (IS_ERR(req)) |
1850 | return PTR_ERR(req); | |
bda4e0fb | 1851 | |
db3cbfff KB |
1852 | req->timeout = ADMIN_TIMEOUT; |
1853 | req->end_io_data = nvmeq; | |
1854 | ||
1855 | blk_execute_rq_nowait(q, NULL, req, false, | |
1856 | opcode == nvme_admin_delete_cq ? | |
1857 | nvme_del_cq_end : nvme_del_queue_end); | |
1858 | return 0; | |
bda4e0fb KB |
1859 | } |
1860 | ||
70659060 | 1861 | static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) |
a5768aa8 | 1862 | { |
70659060 | 1863 | int pass; |
db3cbfff KB |
1864 | unsigned long timeout; |
1865 | u8 opcode = nvme_admin_delete_sq; | |
a5768aa8 | 1866 | |
db3cbfff | 1867 | for (pass = 0; pass < 2; pass++) { |
014a0d60 | 1868 | int sent = 0, i = queues; |
db3cbfff KB |
1869 | |
1870 | reinit_completion(&dev->ioq_wait); | |
1871 | retry: | |
1872 | timeout = ADMIN_TIMEOUT; | |
c21377f8 GKB |
1873 | for (; i > 0; i--, sent++) |
1874 | if (nvme_delete_queue(dev->queues[i], opcode)) | |
db3cbfff | 1875 | break; |
c21377f8 | 1876 | |
db3cbfff KB |
1877 | while (sent--) { |
1878 | timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); | |
1879 | if (timeout == 0) | |
1880 | return; | |
1881 | if (i) | |
1882 | goto retry; | |
1883 | } | |
1884 | opcode = nvme_admin_delete_cq; | |
1885 | } | |
a5768aa8 KB |
1886 | } |
1887 | ||
422ef0c7 MW |
1888 | /* |
1889 | * Return: error value if an error occurred setting up the queues or calling | |
1890 | * Identify Device. 0 if these succeeded, even if adding some of the | |
1891 | * namespaces failed. At the moment, these failures are silent. TBD which | |
1892 | * failures should be reported. | |
1893 | */ | |
8d85fce7 | 1894 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 1895 | { |
5bae7f73 | 1896 | if (!dev->ctrl.tagset) { |
ffe7704d KB |
1897 | dev->tagset.ops = &nvme_mq_ops; |
1898 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
1899 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
1900 | dev->tagset.numa_node = dev_to_node(dev->dev); | |
1901 | dev->tagset.queue_depth = | |
a4aea562 | 1902 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; |
ffe7704d KB |
1903 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
1904 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; | |
1905 | dev->tagset.driver_data = dev; | |
b60503ba | 1906 | |
ffe7704d KB |
1907 | if (blk_mq_alloc_tag_set(&dev->tagset)) |
1908 | return 0; | |
5bae7f73 | 1909 | dev->ctrl.tagset = &dev->tagset; |
f9f38e33 HK |
1910 | |
1911 | nvme_dbbuf_set(dev); | |
949928c1 KB |
1912 | } else { |
1913 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
1914 | ||
1915 | /* Free previously allocated queues that are no longer usable */ | |
1916 | nvme_free_queues(dev, dev->online_queues); | |
ffe7704d | 1917 | } |
949928c1 | 1918 | |
e1e5e564 | 1919 | return 0; |
b60503ba MW |
1920 | } |
1921 | ||
b00a726a | 1922 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 1923 | { |
b00a726a | 1924 | int result = -ENOMEM; |
e75ec752 | 1925 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
1926 | |
1927 | if (pci_enable_device_mem(pdev)) | |
1928 | return result; | |
1929 | ||
0877cb0d | 1930 | pci_set_master(pdev); |
0877cb0d | 1931 | |
e75ec752 CH |
1932 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
1933 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 1934 | goto disable; |
0877cb0d | 1935 | |
7a67cbea | 1936 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 1937 | result = -ENODEV; |
b00a726a | 1938 | goto disable; |
0e53d180 | 1939 | } |
e32efbfc JA |
1940 | |
1941 | /* | |
a5229050 KB |
1942 | * Some devices and/or platforms don't advertise or work with INTx |
1943 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
1944 | * adjust this later. | |
e32efbfc | 1945 | */ |
dca51e78 CH |
1946 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
1947 | if (result < 0) | |
1948 | return result; | |
e32efbfc | 1949 | |
20d0dfe6 | 1950 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
7a67cbea | 1951 | |
20d0dfe6 | 1952 | dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
b27c1e68 | 1953 | io_queue_depth); |
20d0dfe6 | 1954 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
7a67cbea | 1955 | dev->dbs = dev->bar + 4096; |
1f390c1f SG |
1956 | |
1957 | /* | |
1958 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
1959 | * some MacBook7,1 to avoid controller resets and data loss. | |
1960 | */ | |
1961 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
1962 | dev->q_depth = 2; | |
9bdcfb10 CH |
1963 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
1964 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f | 1965 | dev->q_depth); |
d554b5e1 MP |
1966 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
1967 | (pdev->device == 0xa821 || pdev->device == 0xa822) && | |
20d0dfe6 | 1968 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
d554b5e1 MP |
1969 | dev->q_depth = 64; |
1970 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " | |
1971 | "set queue depth=%u\n", dev->q_depth); | |
1f390c1f SG |
1972 | } |
1973 | ||
202021c1 SB |
1974 | /* |
1975 | * CMBs can currently only exist on >=1.2 PCIe devices. We only | |
1c78f773 MG |
1976 | * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group |
1977 | * has no name we can pass NULL as final argument to | |
1978 | * sysfs_add_file_to_group. | |
202021c1 SB |
1979 | */ |
1980 | ||
8ef2074d | 1981 | if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { |
8ffaadf7 | 1982 | dev->cmb = nvme_map_cmb(dev); |
1c78f773 | 1983 | if (dev->cmb) { |
202021c1 SB |
1984 | if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, |
1985 | &dev_attr_cmb.attr, NULL)) | |
9bdcfb10 | 1986 | dev_warn(dev->ctrl.device, |
202021c1 SB |
1987 | "failed to add sysfs attribute for CMB\n"); |
1988 | } | |
1989 | } | |
1990 | ||
a0a3408e KB |
1991 | pci_enable_pcie_error_reporting(pdev); |
1992 | pci_save_state(pdev); | |
0877cb0d KB |
1993 | return 0; |
1994 | ||
1995 | disable: | |
0877cb0d KB |
1996 | pci_disable_device(pdev); |
1997 | return result; | |
1998 | } | |
1999 | ||
2000 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
2001 | { |
2002 | if (dev->bar) | |
2003 | iounmap(dev->bar); | |
a1f447b3 | 2004 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
2005 | } |
2006 | ||
2007 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 2008 | { |
e75ec752 CH |
2009 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2010 | ||
f63572df | 2011 | nvme_release_cmb(dev); |
dca51e78 | 2012 | pci_free_irq_vectors(pdev); |
0877cb0d | 2013 | |
a0a3408e KB |
2014 | if (pci_is_enabled(pdev)) { |
2015 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 2016 | pci_disable_device(pdev); |
4d115420 | 2017 | } |
4d115420 KB |
2018 | } |
2019 | ||
a5cdb68c | 2020 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 2021 | { |
70659060 | 2022 | int i, queues; |
302ad8cc KB |
2023 | bool dead = true; |
2024 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
22404274 | 2025 | |
77bf25ea | 2026 | mutex_lock(&dev->shutdown_lock); |
302ad8cc KB |
2027 | if (pci_is_enabled(pdev)) { |
2028 | u32 csts = readl(dev->bar + NVME_REG_CSTS); | |
2029 | ||
ebef7368 KB |
2030 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
2031 | dev->ctrl.state == NVME_CTRL_RESETTING) | |
302ad8cc KB |
2032 | nvme_start_freeze(&dev->ctrl); |
2033 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || | |
2034 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 2035 | } |
c21377f8 | 2036 | |
302ad8cc KB |
2037 | /* |
2038 | * Give the controller a chance to complete all entered requests if | |
2039 | * doing a safe shutdown. | |
2040 | */ | |
87ad72a5 CH |
2041 | if (!dead) { |
2042 | if (shutdown) | |
2043 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
2044 | ||
2045 | /* | |
2046 | * If the controller is still alive tell it to stop using the | |
2047 | * host memory buffer. In theory the shutdown / reset should | |
2048 | * make sure that it doesn't access the host memoery anymore, | |
2049 | * but I'd rather be safe than sorry.. | |
2050 | */ | |
2051 | if (dev->host_mem_descs) | |
2052 | nvme_set_host_mem(dev, 0); | |
2053 | ||
2054 | } | |
302ad8cc KB |
2055 | nvme_stop_queues(&dev->ctrl); |
2056 | ||
70659060 | 2057 | queues = dev->online_queues - 1; |
d858e5f0 | 2058 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) |
c21377f8 GKB |
2059 | nvme_suspend_queue(dev->queues[i]); |
2060 | ||
302ad8cc | 2061 | if (dead) { |
82469c59 GKB |
2062 | /* A device might become IO incapable very soon during |
2063 | * probe, before the admin queue is configured. Thus, | |
2064 | * queue_count can be 0 here. | |
2065 | */ | |
d858e5f0 | 2066 | if (dev->ctrl.queue_count) |
82469c59 | 2067 | nvme_suspend_queue(dev->queues[0]); |
4d115420 | 2068 | } else { |
70659060 | 2069 | nvme_disable_io_queues(dev, queues); |
a5cdb68c | 2070 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 2071 | } |
b00a726a | 2072 | nvme_pci_disable(dev); |
07836e65 | 2073 | |
e1958e65 ML |
2074 | blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); |
2075 | blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); | |
302ad8cc KB |
2076 | |
2077 | /* | |
2078 | * The driver will not be starting up queues again if shutting down so | |
2079 | * must flush all entered requests to their failed completion to avoid | |
2080 | * deadlocking blk-mq hot-cpu notifier. | |
2081 | */ | |
2082 | if (shutdown) | |
2083 | nvme_start_queues(&dev->ctrl); | |
77bf25ea | 2084 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2085 | } |
2086 | ||
091b6092 MW |
2087 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2088 | { | |
e75ec752 | 2089 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2090 | PAGE_SIZE, PAGE_SIZE, 0); |
2091 | if (!dev->prp_page_pool) | |
2092 | return -ENOMEM; | |
2093 | ||
99802a7a | 2094 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2095 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2096 | 256, 256, 0); |
2097 | if (!dev->prp_small_pool) { | |
2098 | dma_pool_destroy(dev->prp_page_pool); | |
2099 | return -ENOMEM; | |
2100 | } | |
091b6092 MW |
2101 | return 0; |
2102 | } | |
2103 | ||
2104 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2105 | { | |
2106 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2107 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2108 | } |
2109 | ||
1673f1f0 | 2110 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2111 | { |
1673f1f0 | 2112 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2113 | |
f9f38e33 | 2114 | nvme_dbbuf_dma_free(dev); |
e75ec752 | 2115 | put_device(dev->dev); |
4af0e21c KB |
2116 | if (dev->tagset.tags) |
2117 | blk_mq_free_tag_set(&dev->tagset); | |
1c63dc66 CH |
2118 | if (dev->ctrl.admin_q) |
2119 | blk_put_queue(dev->ctrl.admin_q); | |
5e82e952 | 2120 | kfree(dev->queues); |
e286bcfc | 2121 | free_opal_dev(dev->ctrl.opal_dev); |
5e82e952 KB |
2122 | kfree(dev); |
2123 | } | |
2124 | ||
f58944e2 KB |
2125 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) |
2126 | { | |
237045fc | 2127 | dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); |
f58944e2 KB |
2128 | |
2129 | kref_get(&dev->ctrl.kref); | |
69d9a99c | 2130 | nvme_dev_disable(dev, false); |
f58944e2 KB |
2131 | if (!schedule_work(&dev->remove_work)) |
2132 | nvme_put_ctrl(&dev->ctrl); | |
2133 | } | |
2134 | ||
fd634f41 | 2135 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2136 | { |
d86c4d8e CH |
2137 | struct nvme_dev *dev = |
2138 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2139 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
f58944e2 | 2140 | int result = -ENODEV; |
5e82e952 | 2141 | |
82b057ca | 2142 | if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) |
fd634f41 | 2143 | goto out; |
5e82e952 | 2144 | |
fd634f41 CH |
2145 | /* |
2146 | * If we're called to reset a live controller first shut it down before | |
2147 | * moving on. | |
2148 | */ | |
b00a726a | 2149 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2150 | nvme_dev_disable(dev, false); |
5e82e952 | 2151 | |
b00a726a | 2152 | result = nvme_pci_enable(dev); |
f0b50732 | 2153 | if (result) |
3cf519b5 | 2154 | goto out; |
f0b50732 | 2155 | |
01ad0990 | 2156 | result = nvme_pci_configure_admin_queue(dev); |
f0b50732 | 2157 | if (result) |
f58944e2 | 2158 | goto out; |
f0b50732 | 2159 | |
0fb59cbc KB |
2160 | result = nvme_alloc_admin_tags(dev); |
2161 | if (result) | |
f58944e2 | 2162 | goto out; |
b9afca3e | 2163 | |
ce4541f4 CH |
2164 | result = nvme_init_identify(&dev->ctrl); |
2165 | if (result) | |
f58944e2 | 2166 | goto out; |
ce4541f4 | 2167 | |
e286bcfc SB |
2168 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2169 | if (!dev->ctrl.opal_dev) | |
2170 | dev->ctrl.opal_dev = | |
2171 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2172 | else if (was_suspend) | |
2173 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2174 | } else { | |
2175 | free_opal_dev(dev->ctrl.opal_dev); | |
2176 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2177 | } |
a98e58e5 | 2178 | |
f9f38e33 HK |
2179 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2180 | result = nvme_dbbuf_dma_alloc(dev); | |
2181 | if (result) | |
2182 | dev_warn(dev->dev, | |
2183 | "unable to allocate dma for dbbuf\n"); | |
2184 | } | |
2185 | ||
9620cfba CH |
2186 | if (dev->ctrl.hmpre) { |
2187 | result = nvme_setup_host_mem(dev); | |
2188 | if (result < 0) | |
2189 | goto out; | |
2190 | } | |
87ad72a5 | 2191 | |
f0b50732 | 2192 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2193 | if (result) |
f58944e2 | 2194 | goto out; |
f0b50732 | 2195 | |
2659e57b CH |
2196 | /* |
2197 | * Keep the controller around but remove all namespaces if we don't have | |
2198 | * any working I/O queue. | |
2199 | */ | |
3cf519b5 | 2200 | if (dev->online_queues < 2) { |
1b3c47c1 | 2201 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2202 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2203 | nvme_remove_namespaces(&dev->ctrl); |
3cf519b5 | 2204 | } else { |
25646264 | 2205 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2206 | nvme_wait_freeze(&dev->ctrl); |
3cf519b5 | 2207 | nvme_dev_add(dev); |
302ad8cc | 2208 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2209 | } |
2210 | ||
bb8d261e CH |
2211 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
2212 | dev_warn(dev->ctrl.device, "failed to mark controller live\n"); | |
2213 | goto out; | |
2214 | } | |
92911a55 | 2215 | |
d09f2b45 | 2216 | nvme_start_ctrl(&dev->ctrl); |
3cf519b5 | 2217 | return; |
f0b50732 | 2218 | |
3cf519b5 | 2219 | out: |
f58944e2 | 2220 | nvme_remove_dead_ctrl(dev, result); |
f0b50732 KB |
2221 | } |
2222 | ||
5c8809e6 | 2223 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2224 | { |
5c8809e6 | 2225 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2226 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 | 2227 | |
69d9a99c | 2228 | nvme_kill_queues(&dev->ctrl); |
9a6b9458 | 2229 | if (pci_get_drvdata(pdev)) |
921920ab | 2230 | device_release_driver(&pdev->dev); |
1673f1f0 | 2231 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2232 | } |
2233 | ||
1c63dc66 | 2234 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2235 | { |
1c63dc66 | 2236 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2237 | return 0; |
9ca97374 TH |
2238 | } |
2239 | ||
5fd4ce1b | 2240 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2241 | { |
5fd4ce1b CH |
2242 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2243 | return 0; | |
2244 | } | |
4cc06521 | 2245 | |
7fd8930f CH |
2246 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2247 | { | |
2248 | *val = readq(to_nvme_dev(ctrl)->bar + off); | |
2249 | return 0; | |
4cc06521 KB |
2250 | } |
2251 | ||
1c63dc66 | 2252 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 2253 | .name = "pcie", |
e439bb12 | 2254 | .module = THIS_MODULE, |
c81bfba9 | 2255 | .flags = NVME_F_METADATA_SUPPORTED, |
1c63dc66 | 2256 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 2257 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 2258 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 2259 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 2260 | .submit_async_event = nvme_pci_submit_async_event, |
1c63dc66 | 2261 | }; |
4cc06521 | 2262 | |
b00a726a KB |
2263 | static int nvme_dev_map(struct nvme_dev *dev) |
2264 | { | |
b00a726a KB |
2265 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2266 | ||
a1f447b3 | 2267 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
2268 | return -ENODEV; |
2269 | ||
97f6ef64 | 2270 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
2271 | goto release; |
2272 | ||
9fa196e7 | 2273 | return 0; |
b00a726a | 2274 | release: |
9fa196e7 MG |
2275 | pci_release_mem_regions(pdev); |
2276 | return -ENODEV; | |
b00a726a KB |
2277 | } |
2278 | ||
ff5350a8 AL |
2279 | static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) |
2280 | { | |
2281 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
2282 | /* | |
2283 | * Several Samsung devices seem to drop off the PCIe bus | |
2284 | * randomly when APST is on and uses the deepest sleep state. | |
2285 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
2286 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
2287 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
2288 | * laptops. | |
2289 | */ | |
2290 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
2291 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
2292 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
2293 | return NVME_QUIRK_NO_DEEPEST_PS; | |
2294 | } | |
2295 | ||
2296 | return 0; | |
2297 | } | |
2298 | ||
8d85fce7 | 2299 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2300 | { |
a4aea562 | 2301 | int node, result = -ENOMEM; |
b60503ba | 2302 | struct nvme_dev *dev; |
ff5350a8 | 2303 | unsigned long quirks = id->driver_data; |
b60503ba | 2304 | |
a4aea562 MB |
2305 | node = dev_to_node(&pdev->dev); |
2306 | if (node == NUMA_NO_NODE) | |
2fa84351 | 2307 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
2308 | |
2309 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2310 | if (!dev) |
2311 | return -ENOMEM; | |
a4aea562 MB |
2312 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2313 | GFP_KERNEL, node); | |
b60503ba MW |
2314 | if (!dev->queues) |
2315 | goto free; | |
2316 | ||
e75ec752 | 2317 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 2318 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 2319 | |
b00a726a KB |
2320 | result = nvme_dev_map(dev); |
2321 | if (result) | |
b00c9b7a | 2322 | goto put_pci; |
b00a726a | 2323 | |
d86c4d8e | 2324 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 2325 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 2326 | mutex_init(&dev->shutdown_lock); |
db3cbfff | 2327 | init_completion(&dev->ioq_wait); |
b60503ba | 2328 | |
091b6092 MW |
2329 | result = nvme_setup_prp_pools(dev); |
2330 | if (result) | |
b00c9b7a | 2331 | goto unmap; |
4cc06521 | 2332 | |
ff5350a8 AL |
2333 | quirks |= check_dell_samsung_bug(pdev); |
2334 | ||
f3ca80fc | 2335 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
ff5350a8 | 2336 | quirks); |
4cc06521 | 2337 | if (result) |
2e1d8448 | 2338 | goto release_pools; |
740216fc | 2339 | |
82b057ca | 2340 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); |
1b3c47c1 SG |
2341 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
2342 | ||
d86c4d8e | 2343 | queue_work(nvme_wq, &dev->ctrl.reset_work); |
b60503ba MW |
2344 | return 0; |
2345 | ||
0877cb0d | 2346 | release_pools: |
091b6092 | 2347 | nvme_release_prp_pools(dev); |
b00c9b7a CJ |
2348 | unmap: |
2349 | nvme_dev_unmap(dev); | |
a96d4f5c | 2350 | put_pci: |
e75ec752 | 2351 | put_device(dev->dev); |
b60503ba MW |
2352 | free: |
2353 | kfree(dev->queues); | |
b60503ba MW |
2354 | kfree(dev); |
2355 | return result; | |
2356 | } | |
2357 | ||
775755ed | 2358 | static void nvme_reset_prepare(struct pci_dev *pdev) |
f0d54a54 | 2359 | { |
a6739479 | 2360 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f263fbb8 | 2361 | nvme_dev_disable(dev, false); |
775755ed | 2362 | } |
f0d54a54 | 2363 | |
775755ed CH |
2364 | static void nvme_reset_done(struct pci_dev *pdev) |
2365 | { | |
f263fbb8 LT |
2366 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
2367 | nvme_reset_ctrl(&dev->ctrl); | |
f0d54a54 KB |
2368 | } |
2369 | ||
09ece142 KB |
2370 | static void nvme_shutdown(struct pci_dev *pdev) |
2371 | { | |
2372 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
a5cdb68c | 2373 | nvme_dev_disable(dev, true); |
09ece142 KB |
2374 | } |
2375 | ||
f58944e2 KB |
2376 | /* |
2377 | * The driver's remove may be called on a device in a partially initialized | |
2378 | * state. This function must not have any dependencies on the device state in | |
2379 | * order to proceed. | |
2380 | */ | |
8d85fce7 | 2381 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
2382 | { |
2383 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 2384 | |
bb8d261e CH |
2385 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
2386 | ||
d86c4d8e | 2387 | cancel_work_sync(&dev->ctrl.reset_work); |
9a6b9458 | 2388 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 2389 | |
6db28eda | 2390 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 2391 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
6db28eda KB |
2392 | nvme_dev_disable(dev, false); |
2393 | } | |
0ff9d4e1 | 2394 | |
d86c4d8e | 2395 | flush_work(&dev->ctrl.reset_work); |
d09f2b45 SG |
2396 | nvme_stop_ctrl(&dev->ctrl); |
2397 | nvme_remove_namespaces(&dev->ctrl); | |
a5cdb68c | 2398 | nvme_dev_disable(dev, true); |
87ad72a5 | 2399 | nvme_free_host_mem(dev); |
a4aea562 | 2400 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 2401 | nvme_free_queues(dev, 0); |
d09f2b45 | 2402 | nvme_uninit_ctrl(&dev->ctrl); |
9a6b9458 | 2403 | nvme_release_prp_pools(dev); |
b00a726a | 2404 | nvme_dev_unmap(dev); |
1673f1f0 | 2405 | nvme_put_ctrl(&dev->ctrl); |
b60503ba MW |
2406 | } |
2407 | ||
13880f5b KB |
2408 | static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) |
2409 | { | |
2410 | int ret = 0; | |
2411 | ||
2412 | if (numvfs == 0) { | |
2413 | if (pci_vfs_assigned(pdev)) { | |
2414 | dev_warn(&pdev->dev, | |
2415 | "Cannot disable SR-IOV VFs while assigned\n"); | |
2416 | return -EPERM; | |
2417 | } | |
2418 | pci_disable_sriov(pdev); | |
2419 | return 0; | |
2420 | } | |
2421 | ||
2422 | ret = pci_enable_sriov(pdev, numvfs); | |
2423 | return ret ? ret : numvfs; | |
2424 | } | |
2425 | ||
671a6018 | 2426 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
2427 | static int nvme_suspend(struct device *dev) |
2428 | { | |
2429 | struct pci_dev *pdev = to_pci_dev(dev); | |
2430 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
2431 | ||
a5cdb68c | 2432 | nvme_dev_disable(ndev, true); |
cd638946 KB |
2433 | return 0; |
2434 | } | |
2435 | ||
2436 | static int nvme_resume(struct device *dev) | |
2437 | { | |
2438 | struct pci_dev *pdev = to_pci_dev(dev); | |
2439 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 2440 | |
d86c4d8e | 2441 | nvme_reset_ctrl(&ndev->ctrl); |
9a6b9458 | 2442 | return 0; |
cd638946 | 2443 | } |
671a6018 | 2444 | #endif |
cd638946 KB |
2445 | |
2446 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 2447 | |
a0a3408e KB |
2448 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
2449 | pci_channel_state_t state) | |
2450 | { | |
2451 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2452 | ||
2453 | /* | |
2454 | * A frozen channel requires a reset. When detected, this method will | |
2455 | * shutdown the controller to quiesce. The controller will be restarted | |
2456 | * after the slot reset through driver's slot_reset callback. | |
2457 | */ | |
a0a3408e KB |
2458 | switch (state) { |
2459 | case pci_channel_io_normal: | |
2460 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2461 | case pci_channel_io_frozen: | |
d011fb31 KB |
2462 | dev_warn(dev->ctrl.device, |
2463 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 2464 | nvme_dev_disable(dev, false); |
a0a3408e KB |
2465 | return PCI_ERS_RESULT_NEED_RESET; |
2466 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
2467 | dev_warn(dev->ctrl.device, |
2468 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
2469 | return PCI_ERS_RESULT_DISCONNECT; |
2470 | } | |
2471 | return PCI_ERS_RESULT_NEED_RESET; | |
2472 | } | |
2473 | ||
2474 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
2475 | { | |
2476 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
2477 | ||
1b3c47c1 | 2478 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 2479 | pci_restore_state(pdev); |
d86c4d8e | 2480 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
2481 | return PCI_ERS_RESULT_RECOVERED; |
2482 | } | |
2483 | ||
2484 | static void nvme_error_resume(struct pci_dev *pdev) | |
2485 | { | |
2486 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
2487 | } | |
2488 | ||
1d352035 | 2489 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 2490 | .error_detected = nvme_error_detected, |
b60503ba MW |
2491 | .slot_reset = nvme_slot_reset, |
2492 | .resume = nvme_error_resume, | |
775755ed CH |
2493 | .reset_prepare = nvme_reset_prepare, |
2494 | .reset_done = nvme_reset_done, | |
b60503ba MW |
2495 | }; |
2496 | ||
6eb0d698 | 2497 | static const struct pci_device_id nvme_id_table[] = { |
106198ed | 2498 | { PCI_VDEVICE(INTEL, 0x0953), |
08095e70 | 2499 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 2500 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2501 | { PCI_VDEVICE(INTEL, 0x0a53), |
2502 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2503 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
99466e70 KB |
2504 | { PCI_VDEVICE(INTEL, 0x0a54), |
2505 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
e850fd16 | 2506 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
f99cb7af DWF |
2507 | { PCI_VDEVICE(INTEL, 0x0a55), |
2508 | .driver_data = NVME_QUIRK_STRIPE_SIZE | | |
2509 | NVME_QUIRK_DEALLOCATE_ZEROES, }, | |
50af47d0 AL |
2510 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
2511 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, | |
540c801c KB |
2512 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
2513 | .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, | |
54adc010 GP |
2514 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
2515 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
2516 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
2517 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
d554b5e1 MP |
2518 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
2519 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
2520 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ | |
2521 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
608cc4b1 CH |
2522 | { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ |
2523 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
2524 | { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ | |
2525 | .driver_data = NVME_QUIRK_LIGHTNVM, }, | |
b60503ba | 2526 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
c74dc780 | 2527 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, |
124298bd | 2528 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
b60503ba MW |
2529 | { 0, } |
2530 | }; | |
2531 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
2532 | ||
2533 | static struct pci_driver nvme_driver = { | |
2534 | .name = "nvme", | |
2535 | .id_table = nvme_id_table, | |
2536 | .probe = nvme_probe, | |
8d85fce7 | 2537 | .remove = nvme_remove, |
09ece142 | 2538 | .shutdown = nvme_shutdown, |
cd638946 KB |
2539 | .driver = { |
2540 | .pm = &nvme_dev_pm_ops, | |
2541 | }, | |
13880f5b | 2542 | .sriov_configure = nvme_pci_sriov_configure, |
b60503ba MW |
2543 | .err_handler = &nvme_err_handler, |
2544 | }; | |
2545 | ||
2546 | static int __init nvme_init(void) | |
2547 | { | |
9a6327d2 | 2548 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
2549 | } |
2550 | ||
2551 | static void __exit nvme_exit(void) | |
2552 | { | |
2553 | pci_unregister_driver(&nvme_driver); | |
21bd78bc | 2554 | _nvme_check_size(); |
b60503ba MW |
2555 | } |
2556 | ||
2557 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
2558 | MODULE_LICENSE("GPL"); | |
c78b4713 | 2559 | MODULE_VERSION("1.0"); |
b60503ba MW |
2560 | module_init(nvme_init); |
2561 | module_exit(nvme_exit); |