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[linux-2.6-block.git] / drivers / nvme / host / pci.c
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b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
0f238ff5 33#include <linux/pci-p2pdma.h>
797a796a 34
f11bb3e2
CH		 35#include "nvme.h"
36
b60503ba
MW		 37#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
38#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 39
a7a7cbe3 40#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 41
943e942e
JA		 42/*
43 * These can be higher, but we need to ensure that any command doesn't
44 * require an sg allocation that needs more than a page of data.
45 */
46#define NVME_MAX_KB_SZ 4096
47#define NVME_MAX_SEGS 127
48
58ffacb5
MW		 49static int use_threaded_interrupts;
50module_param(use_threaded_interrupts, int, 0);
51
8ffaadf7 52static bool use_cmb_sqes = true;
69f4eb9f 53module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 54MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55
87ad72a5
CH		 56static unsigned int max_host_mem_size_mb = 128;
57module_param(max_host_mem_size_mb, uint, 0444);
58MODULE_PARM_DESC(max_host_mem_size_mb,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 60
a7a7cbe3
CK		 61static unsigned int sgl_threshold = SZ_32K;
62module_param(sgl_threshold, uint, 0644);
63MODULE_PARM_DESC(sgl_threshold,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
66
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
70 .get = param_get_int,
71};
72
73static int io_queue_depth = 1024;
74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
76
3b6592f7
JA		 77static int queue_count_set(const char *val, const struct kernel_param *kp);
78static const struct kernel_param_ops queue_count_ops = {
79 .set = queue_count_set,
80 .get = param_get_int,
81};
82
83static int write_queues;
84module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
85MODULE_PARM_DESC(write_queues,
86 "Number of queues to use for writes. If not set, reads and writes "
87 "will share a queue set.");
88
a4668d9b 89static int poll_queues = 0;
4b04cc6a
JA		 90module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
91MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
92
1c63dc66
CH		 93struct nvme_dev;
94struct nvme_queue;
b3fffdef 95
a5cdb68c 96static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 97
3b6592f7
JA		 98enum {
99 NVMEQ_TYPE_READ,
100 NVMEQ_TYPE_WRITE,
4b04cc6a 101 NVMEQ_TYPE_POLL,
3b6592f7
JA		 102 NVMEQ_TYPE_NR,
103};
104
1c63dc66
CH		 105/*
106 * Represents an NVM Express device. Each nvme_dev is a PCI function.
107 */
108struct nvme_dev {
147b27e4 109 struct nvme_queue *queues;
1c63dc66
CH		 110 struct blk_mq_tag_set tagset;
111 struct blk_mq_tag_set admin_tagset;
112 u32 __iomem *dbs;
113 struct device *dev;
114 struct dma_pool *prp_page_pool;
115 struct dma_pool *prp_small_pool;
1c63dc66
CH		 116 unsigned online_queues;
117 unsigned max_qid;
3b6592f7 118 unsigned io_queues[NVMEQ_TYPE_NR];
22b55601 119 unsigned int num_vecs;
1c63dc66
CH		 120 int q_depth;
121 u32 db_stride;
1c63dc66 122 void __iomem *bar;
97f6ef64 123 unsigned long bar_mapped_size;
5c8809e6 124 struct work_struct remove_work;
77bf25ea 125 struct mutex shutdown_lock;
1c63dc66 126 bool subsystem;
1c63dc66 127 u64 cmb_size;
0f238ff5 128 bool cmb_use_sqes;
1c63dc66 129 u32 cmbsz;
202021c1 130 u32 cmbloc;
1c63dc66 131 struct nvme_ctrl ctrl;
db3cbfff 132 struct completion ioq_wait;
87ad72a5 133
943e942e
JA		 134 mempool_t *iod_mempool;
135
87ad72a5 136 /* shadow doorbell buffer support: */
f9f38e33
HK		 137 u32 *dbbuf_dbs;
138 dma_addr_t dbbuf_dbs_dma_addr;
139 u32 *dbbuf_eis;
140 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 141
142 /* host memory buffer support: */
143 u64 host_mem_size;
144 u32 nr_host_mem_descs;
4033f35d 145 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 146 struct nvme_host_mem_buf_desc *host_mem_descs;
147 void **host_mem_desc_bufs;
4d115420 148};
1fa6aead 149
b27c1e68 150static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
151{
152 int n = 0, ret;
153
154 ret = kstrtoint(val, 10, &n);
155 if (ret != 0 || n < 2)
156 return -EINVAL;
157
158 return param_set_int(val, kp);
159}
160
3b6592f7
JA		 161static int queue_count_set(const char *val, const struct kernel_param *kp)
162{
163 int n = 0, ret;
164
165 ret = kstrtoint(val, 10, &n);
166 if (n > num_possible_cpus())
167 n = num_possible_cpus();
168
169 return param_set_int(val, kp);
170}
171
f9f38e33
HK		 172static inline unsigned int sq_idx(unsigned int qid, u32 stride)
173{
174 return qid * 2 * stride;
175}
176
177static inline unsigned int cq_idx(unsigned int qid, u32 stride)
178{
179 return (qid * 2 + 1) * stride;
180}
181
1c63dc66
CH		 182static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
183{
184 return container_of(ctrl, struct nvme_dev, ctrl);
185}
186
b60503ba
MW		 187/*
188 * An NVM Express queue. Each device has at least two (one for admin
189 * commands and one for I/O commands).
190 */
191struct nvme_queue {
192 struct device *q_dmadev;
091b6092 193 struct nvme_dev *dev;
1ab0cd69 194 spinlock_t sq_lock;
b60503ba 195 struct nvme_command *sq_cmds;
0f238ff5 196 bool sq_cmds_is_io;
1ab0cd69 197 spinlock_t cq_lock ____cacheline_aligned_in_smp;
b60503ba 198 volatile struct nvme_completion *cqes;
42483228 199 struct blk_mq_tags **tags;
b60503ba
MW		 200 dma_addr_t sq_dma_addr;
201 dma_addr_t cq_dma_addr;
b60503ba
MW		 202 u32 __iomem *q_db;
203 u16 q_depth;
6222d172 204 s16 cq_vector;
b60503ba 205 u16 sq_tail;
04f3eafd 206 u16 last_sq_tail;
b60503ba 207 u16 cq_head;
68fa9dbe 208 u16 last_cq_head;
c30341dc 209 u16 qid;
e9539f47 210 u8 cq_phase;
4b04cc6a 211 u8 polled;
f9f38e33
HK		 212 u32 *dbbuf_sq_db;
213 u32 *dbbuf_cq_db;
214 u32 *dbbuf_sq_ei;
215 u32 *dbbuf_cq_ei;
b60503ba
MW		 216};
217
71bd150c
CH		 218/*
219 * The nvme_iod describes the data in an I/O, including the list of PRP
220 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 221 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 222 * allocated to store the PRP list.
223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
f4800d6d 226 struct nvme_queue *nvmeq;
a7a7cbe3 227 bool use_sgl;
f4800d6d 228 int aborted;
71bd150c 229 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 230 int nents; /* Used in scatterlist */
231 int length; /* Of data, in bytes */
232 dma_addr_t first_dma;
bf684057 233 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 234 struct scatterlist *sg;
235 struct scatterlist inline_sg[0];
b60503ba
MW		 236};
237
238/*
239 * Check we didin't inadvertently grow the command struct
240 */
241static inline void _nvme_check_size(void)
242{
243 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
244 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
245 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
246 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
247 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 248 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 249 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 250 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 251 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
252 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 253 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 254 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 255 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
256}
257
3b6592f7
JA		 258static unsigned int max_io_queues(void)
259{
4b04cc6a 260 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 261}
262
263static unsigned int max_queue_count(void)
264{
265 /* IO queues + admin queue */
266 return 1 + max_io_queues();
267}
268
f9f38e33
HK		 269static inline unsigned int nvme_dbbuf_size(u32 stride)
270{
3b6592f7 271 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 272}
273
274static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
275{
276 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
277
278 if (dev->dbbuf_dbs)
279 return 0;
280
281 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
282 &dev->dbbuf_dbs_dma_addr,
283 GFP_KERNEL);
284 if (!dev->dbbuf_dbs)
285 return -ENOMEM;
286 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
287 &dev->dbbuf_eis_dma_addr,
288 GFP_KERNEL);
289 if (!dev->dbbuf_eis) {
290 dma_free_coherent(dev->dev, mem_size,
291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
292 dev->dbbuf_dbs = NULL;
293 return -ENOMEM;
294 }
295
296 return 0;
297}
298
299static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
300{
301 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
302
303 if (dev->dbbuf_dbs) {
304 dma_free_coherent(dev->dev, mem_size,
305 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
306 dev->dbbuf_dbs = NULL;
307 }
308 if (dev->dbbuf_eis) {
309 dma_free_coherent(dev->dev, mem_size,
310 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
311 dev->dbbuf_eis = NULL;
312 }
313}
314
315static void nvme_dbbuf_init(struct nvme_dev *dev,
316 struct nvme_queue *nvmeq, int qid)
317{
318 if (!dev->dbbuf_dbs || !qid)
319 return;
320
321 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
322 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
323 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
324 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
325}
326
327static void nvme_dbbuf_set(struct nvme_dev *dev)
328{
329 struct nvme_command c;
330
331 if (!dev->dbbuf_dbs)
332 return;
333
334 memset(&c, 0, sizeof(c));
335 c.dbbuf.opcode = nvme_admin_dbbuf;
336 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
337 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
338
339 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 340 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 341 /* Free memory and continue on */
342 nvme_dbbuf_dma_free(dev);
343 }
344}
345
346static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347{
348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349}
350
351/* Update dbbuf and return true if an MMIO is required */
352static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
353 volatile u32 *dbbuf_ei)
354{
355 if (dbbuf_db) {
356 u16 old_value;
357
358 /*
359 * Ensure that the queue is written before updating
360 * the doorbell in memory
361 */
362 wmb();
363
364 old_value = *dbbuf_db;
365 *dbbuf_db = value;
366
f1ed3df2
MW		 367 /*
368 * Ensure that the doorbell is updated before reading the event
369 * index from memory. The controller needs to provide similar
370 * ordering to ensure the envent index is updated before reading
371 * the doorbell.
372 */
373 mb();
374
f9f38e33
HK		 375 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
376 return false;
377 }
378
379 return true;
b60503ba
MW		 380}
381
ac3dd5bd
JA		 382/*
383 * Max size of iod being embedded in the request payload
384 */
385#define NVME_INT_PAGES 2
5fd4ce1b 386#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 387
388/*
389 * Will slightly overestimate the number of pages needed. This is OK
390 * as it only leads to a small amount of wasted memory for the lifetime of
391 * the I/O.
392 */
393static int nvme_npages(unsigned size, struct nvme_dev *dev)
394{
5fd4ce1b
CH		 395 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
396 dev->ctrl.page_size);
ac3dd5bd
JA		 397 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
398}
399
a7a7cbe3
CK		 400/*
401 * Calculates the number of pages needed for the SGL segments. For example a 4k
402 * page can accommodate 256 SGL descriptors.
403 */
404static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 405{
a7a7cbe3 406 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 407}
ac3dd5bd 408
a7a7cbe3
CK		 409static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
410 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 411{
a7a7cbe3
CK		 412 size_t alloc_size;
413
414 if (use_sgl)
415 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
416 else
417 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
418
419 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 420}
ac3dd5bd 421
a7a7cbe3 422static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 423{
a7a7cbe3
CK		 424 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
425 NVME_INT_BYTES(dev), NVME_INT_PAGES,
426 use_sgl);
427
428 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 429}
430
a4aea562
MB		 431static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
432 unsigned int hctx_idx)
e85248e5 433{
a4aea562 434 struct nvme_dev *dev = data;
147b27e4 435 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 436
42483228
KB		 437 WARN_ON(hctx_idx != 0);
438 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
439 WARN_ON(nvmeq->tags);
440
a4aea562 441 hctx->driver_data = nvmeq;
42483228 442 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 443 return 0;
e85248e5
MW		 444}
445
4af0e21c
KB		 446static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
447{
448 struct nvme_queue *nvmeq = hctx->driver_data;
449
450 nvmeq->tags = NULL;
451}
452
a4aea562
MB		 453static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
454 unsigned int hctx_idx)
b60503ba 455{
a4aea562 456 struct nvme_dev *dev = data;
147b27e4 457 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 458
42483228
KB		 459 if (!nvmeq->tags)
460 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 461
42483228 462 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 463 hctx->driver_data = nvmeq;
464 return 0;
b60503ba
MW		 465}
466
d6296d39
CH		 467static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
468 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 469{
d6296d39 470 struct nvme_dev *dev = set->driver_data;
f4800d6d 471 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 472 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 473 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 474
475 BUG_ON(!nvmeq);
f4800d6d 476 iod->nvmeq = nvmeq;
59e29ce6
SG		 477
478 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 479 return 0;
480}
481
3b6592f7
JA		 482static int queue_irq_offset(struct nvme_dev *dev)
483{
484 /* if we have more than 1 vec, admin queue offsets us by 1 */
485 if (dev->num_vecs > 1)
486 return 1;
487
488 return 0;
489}
490
dca51e78
CH		 491static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
492{
493 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 494 int i, qoff, offset;
495
496 offset = queue_irq_offset(dev);
497 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
498 struct blk_mq_queue_map *map = &set->map[i];
499
500 map->nr_queues = dev->io_queues[i];
501 if (!map->nr_queues) {
502 BUG_ON(i == NVMEQ_TYPE_READ);
dca51e78 503
3b6592f7
JA		 504 /* shared set, resuse read set parameters */
505 map->nr_queues = dev->io_queues[NVMEQ_TYPE_READ];
506 qoff = 0;
507 offset = queue_irq_offset(dev);
508 }
509
4b04cc6a
JA		 510 /*
511 * The poll queue(s) doesn't have an IRQ (and hence IRQ
512 * affinity), so use the regular blk-mq cpu mapping
513 */
3b6592f7 514 map->queue_offset = qoff;
4b04cc6a
JA		 515 if (i != NVMEQ_TYPE_POLL)
516 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
517 else
518 blk_mq_map_queues(map);
3b6592f7
JA		 519 qoff += map->nr_queues;
520 offset += map->nr_queues;
521 }
522
523 return 0;
dca51e78
CH		 524}
525
04f3eafd
JA		 526/*
527 * Write sq tail if we are asked to, or if the next command would wrap.
528 */
529static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
530{
531 if (!write_sq) {
532 u16 next_tail = nvmeq->sq_tail + 1;
533
534 if (next_tail == nvmeq->q_depth)
535 next_tail = 0;
536 if (next_tail != nvmeq->last_sq_tail)
537 return;
538 }
539
540 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
541 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
542 writel(nvmeq->sq_tail, nvmeq->q_db);
543 nvmeq->last_sq_tail = nvmeq->sq_tail;
544}
545
b60503ba 546/**
90ea5ca4 547 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 548 * @nvmeq: The queue to use
549 * @cmd: The command to send
04f3eafd 550 * @write_sq: whether to write to the SQ doorbell
b60503ba 551 */
04f3eafd
JA		 552static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
553 bool write_sq)
b60503ba 554{
90ea5ca4 555 spin_lock(&nvmeq->sq_lock);
0f238ff5 556 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 557 if (++nvmeq->sq_tail == nvmeq->q_depth)
558 nvmeq->sq_tail = 0;
04f3eafd
JA		 559 nvme_write_sq_db(nvmeq, write_sq);
560 spin_unlock(&nvmeq->sq_lock);
561}
562
563static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
564{
565 struct nvme_queue *nvmeq = hctx->driver_data;
566
567 spin_lock(&nvmeq->sq_lock);
568 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
569 nvme_write_sq_db(nvmeq, true);
90ea5ca4 570 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 571}
572
a7a7cbe3 573static void **nvme_pci_iod_list(struct request *req)
b60503ba 574{
f4800d6d 575 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 576 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 577}
578
955b1b5a
MI		 579static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
580{
581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 582 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 583 unsigned int avg_seg_size;
584
20469a37
KB		 585 if (nseg == 0)
586 return false;
587
588 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 589
590 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
591 return false;
592 if (!iod->nvmeq->qid)
593 return false;
594 if (!sgl_threshold || avg_seg_size < sgl_threshold)
595 return false;
596 return true;
597}
598
fc17b653 599static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 600{
f4800d6d 601 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 602 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 603 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 604
955b1b5a
MI		 605 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
606
f4800d6d 607 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
943e942e 608 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
f4800d6d 609 if (!iod->sg)
fc17b653 610 return BLK_STS_RESOURCE;
f4800d6d
CH		 611 } else {
612 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 613 }
614
f4800d6d
CH		 615 iod->aborted = 0;
616 iod->npages = -1;
617 iod->nents = 0;
618 iod->length = size;
f80ec966 619
fc17b653 620 return BLK_STS_OK;
ac3dd5bd
JA		 621}
622
f4800d6d 623static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 624{
f4800d6d 625 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 626 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
627 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
628
eca18b23 629 int i;
eca18b23
MW		 630
631 if (iod->npages == 0)
a7a7cbe3
CK		 632 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
633 dma_addr);
634
eca18b23 635 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 636 void *addr = nvme_pci_iod_list(req)[i];
637
638 if (iod->use_sgl) {
639 struct nvme_sgl_desc *sg_list = addr;
640
641 next_dma_addr =
642 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
643 } else {
644 __le64 *prp_list = addr;
645
646 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
647 }
648
649 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
650 dma_addr = next_dma_addr;
eca18b23 651 }
ac3dd5bd 652
f4800d6d 653 if (iod->sg != iod->inline_sg)
943e942e 654 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 655}
656
d0877473
KB		 657static void nvme_print_sgl(struct scatterlist *sgl, int nents)
658{
659 int i;
660 struct scatterlist *sg;
661
662 for_each_sg(sgl, sg, nents, i) {
663 dma_addr_t phys = sg_phys(sg);
664 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
665 "dma_address:%pad dma_length:%d\n",
666 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
667 sg_dma_len(sg));
668 }
669}
670
a7a7cbe3
CK		 671static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
672 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 673{
f4800d6d 674 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 675 struct dma_pool *pool;
b131c61d 676 int length = blk_rq_payload_bytes(req);
eca18b23 677 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 678 int dma_len = sg_dma_len(sg);
679 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 680 u32 page_size = dev->ctrl.page_size;
f137e0f1 681 int offset = dma_addr & (page_size - 1);
e025344c 682 __le64 *prp_list;
a7a7cbe3 683 void **list = nvme_pci_iod_list(req);
e025344c 684 dma_addr_t prp_dma;
eca18b23 685 int nprps, i;
ff22b54f 686
1d090624 687 length -= (page_size - offset);
5228b328
JS		 688 if (length <= 0) {
689 iod->first_dma = 0;
a7a7cbe3 690 goto done;
5228b328 691 }
ff22b54f 692
1d090624 693 dma_len -= (page_size - offset);
ff22b54f 694 if (dma_len) {
1d090624 695 dma_addr += (page_size - offset);
ff22b54f
MW		 696 } else {
697 sg = sg_next(sg);
698 dma_addr = sg_dma_address(sg);
699 dma_len = sg_dma_len(sg);
700 }
701
1d090624 702 if (length <= page_size) {
edd10d33 703 iod->first_dma = dma_addr;
a7a7cbe3 704 goto done;
e025344c
SMM		 705 }
706
1d090624 707 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 708 if (nprps <= (256 / 8)) {
709 pool = dev->prp_small_pool;
eca18b23 710 iod->npages = 0;
99802a7a
MW		 711 } else {
712 pool = dev->prp_page_pool;
eca18b23 713 iod->npages = 1;
99802a7a
MW		 714 }
715
69d2b571 716 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 717 if (!prp_list) {
edd10d33 718 iod->first_dma = dma_addr;
eca18b23 719 iod->npages = -1;
86eea289 720 return BLK_STS_RESOURCE;
b77954cb 721 }
eca18b23
MW		 722 list[0] = prp_list;
723 iod->first_dma = prp_dma;
e025344c
SMM		 724 i = 0;
725 for (;;) {
1d090624 726 if (i == page_size >> 3) {
e025344c 727 __le64 *old_prp_list = prp_list;
69d2b571 728 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 729 if (!prp_list)
86eea289 730 return BLK_STS_RESOURCE;
eca18b23 731 list[iod->npages++] = prp_list;
7523d834
MW		 732 prp_list[0] = old_prp_list[i - 1];
733 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
734 i = 1;
e025344c
SMM		 735 }
736 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 737 dma_len -= page_size;
738 dma_addr += page_size;
739 length -= page_size;
e025344c
SMM		 740 if (length <= 0)
741 break;
742 if (dma_len > 0)
743 continue;
86eea289
KB		 744 if (unlikely(dma_len < 0))
745 goto bad_sgl;
e025344c
SMM		 746 sg = sg_next(sg);
747 dma_addr = sg_dma_address(sg);
748 dma_len = sg_dma_len(sg);
ff22b54f
MW		 749 }
750
a7a7cbe3
CK		 751done:
752 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
753 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
754
86eea289
KB		 755 return BLK_STS_OK;
756
757 bad_sgl:
d0877473
KB		 758 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
759 "Invalid SGL for payload:%d nents:%d\n",
760 blk_rq_payload_bytes(req), iod->nents);
86eea289 761 return BLK_STS_IOERR;
ff22b54f
MW		 762}
763
a7a7cbe3
CK		 764static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
765 struct scatterlist *sg)
766{
767 sge->addr = cpu_to_le64(sg_dma_address(sg));
768 sge->length = cpu_to_le32(sg_dma_len(sg));
769 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
770}
771
772static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
773 dma_addr_t dma_addr, int entries)
774{
775 sge->addr = cpu_to_le64(dma_addr);
776 if (entries < SGES_PER_PAGE) {
777 sge->length = cpu_to_le32(entries * sizeof(*sge));
778 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
779 } else {
780 sge->length = cpu_to_le32(PAGE_SIZE);
781 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
782 }
783}
784
785static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 786 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 787{
788 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 789 struct dma_pool *pool;
790 struct nvme_sgl_desc *sg_list;
791 struct scatterlist *sg = iod->sg;
a7a7cbe3 792 dma_addr_t sgl_dma;
b0f2853b 793 int i = 0;
a7a7cbe3 794
a7a7cbe3
CK		 795 /* setting the transfer type as SGL */
796 cmd->flags = NVME_CMD_SGL_METABUF;
797
b0f2853b 798 if (entries == 1) {
a7a7cbe3
CK		 799 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
800 return BLK_STS_OK;
801 }
802
803 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
804 pool = dev->prp_small_pool;
805 iod->npages = 0;
806 } else {
807 pool = dev->prp_page_pool;
808 iod->npages = 1;
809 }
810
811 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
812 if (!sg_list) {
813 iod->npages = -1;
814 return BLK_STS_RESOURCE;
815 }
816
817 nvme_pci_iod_list(req)[0] = sg_list;
818 iod->first_dma = sgl_dma;
819
820 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
821
822 do {
823 if (i == SGES_PER_PAGE) {
824 struct nvme_sgl_desc *old_sg_desc = sg_list;
825 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
826
827 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
828 if (!sg_list)
829 return BLK_STS_RESOURCE;
830
831 i = 0;
832 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
833 sg_list[i++] = *link;
834 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
835 }
836
837 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 838 sg = sg_next(sg);
b0f2853b 839 } while (--entries > 0);
a7a7cbe3 840
a7a7cbe3
CK		 841 return BLK_STS_OK;
842}
843
fc17b653 844static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 845 struct nvme_command *cmnd)
d29ec824 846{
f4800d6d 847 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 848 struct request_queue *q = req->q;
849 enum dma_data_direction dma_dir = rq_data_dir(req) ?
850 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 851 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 852 int nr_mapped;
d29ec824 853
f9d03f96 854 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 855 iod->nents = blk_rq_map_sg(q, req, iod->sg);
856 if (!iod->nents)
857 goto out;
d29ec824 858
fc17b653 859 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 860
861 if (is_pci_p2pdma_page(sg_page(iod->sg)))
862 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
863 dma_dir);
864 else
865 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
866 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 867 if (!nr_mapped)
ba1ca37e 868 goto out;
d29ec824 869
955b1b5a 870 if (iod->use_sgl)
b0f2853b 871 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 872 else
873 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
874
86eea289 875 if (ret != BLK_STS_OK)
ba1ca37e 876 goto out_unmap;
0e5e4f0e 877
fc17b653 878 ret = BLK_STS_IOERR;
ba1ca37e
CH		 879 if (blk_integrity_rq(req)) {
880 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
881 goto out_unmap;
0e5e4f0e 882
bf684057
CH		 883 sg_init_table(&iod->meta_sg, 1);
884 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 885 goto out_unmap;
0e5e4f0e 886
bf684057 887 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 888 goto out_unmap;
00df5cb4 889
bf684057 890 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK		 891 }
892
fc17b653 893 return BLK_STS_OK;
00df5cb4 894
ba1ca37e
CH		 895out_unmap:
896 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
897out:
898 return ret;
00df5cb4
MW		 899}
900
f4800d6d 901static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 902{
f4800d6d 903 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 904 enum dma_data_direction dma_dir = rq_data_dir(req) ?
905 DMA_TO_DEVICE : DMA_FROM_DEVICE;
906
907 if (iod->nents) {
e0596ab2
LG		 908 /* P2PDMA requests do not need to be unmapped */
909 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
910 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
911
f7f1fc36 912 if (blk_integrity_rq(req))
bf684057 913 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e19b127f 914 }
e1e5e564 915
f9d03f96 916 nvme_cleanup_cmd(req);
f4800d6d 917 nvme_free_iod(dev, req);
d4f6c3ab 918}
b60503ba 919
d29ec824
CH		 920/*
921 * NOTE: ns is NULL when called on the admin queue.
922 */
fc17b653 923static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 924 const struct blk_mq_queue_data *bd)
edd10d33 925{
a4aea562
MB		 926 struct nvme_ns *ns = hctx->queue->queuedata;
927 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 928 struct nvme_dev *dev = nvmeq->dev;
a4aea562 929 struct request *req = bd->rq;
ba1ca37e 930 struct nvme_command cmnd;
ebe6d874 931 blk_status_t ret;
e1e5e564 932
d1f06f4a
JA		 933 /*
934 * We should not need to do this, but we're still using this to
935 * ensure we can drain requests on a dying queue.
936 */
4b04cc6a 937 if (unlikely(nvmeq->cq_vector < 0 && !nvmeq->polled))
d1f06f4a
JA		 938 return BLK_STS_IOERR;
939
f9d03f96 940 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 941 if (ret)
f4800d6d 942 return ret;
a4aea562 943
b131c61d 944 ret = nvme_init_iod(req, dev);
fc17b653 945 if (ret)
f9d03f96 946 goto out_free_cmd;
a4aea562 947
fc17b653 948 if (blk_rq_nr_phys_segments(req)) {
b131c61d 949 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 950 if (ret)
951 goto out_cleanup_iod;
952 }
a4aea562 953
aae239e1 954 blk_mq_start_request(req);
04f3eafd 955 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 956 return BLK_STS_OK;
f9d03f96 957out_cleanup_iod:
f4800d6d 958 nvme_free_iod(dev, req);
f9d03f96
CH		 959out_free_cmd:
960 nvme_cleanup_cmd(req);
ba1ca37e 961 return ret;
b60503ba 962}
e1e5e564 963
3b6592f7
JA		 964static int nvme_rq_flags_to_type(struct request_queue *q, unsigned int flags)
965{
4b04cc6a
JA		 966 if ((flags & REQ_HIPRI) && test_bit(QUEUE_FLAG_POLL, &q->queue_flags))
967 return NVMEQ_TYPE_POLL;
3b6592f7
JA		 968 if ((flags & REQ_OP_MASK) == REQ_OP_READ)
969 return NVMEQ_TYPE_READ;
970
971 return NVMEQ_TYPE_WRITE;
972}
973
77f02a7a 974static void nvme_pci_complete_rq(struct request *req)
eee417b0 975{
f4800d6d 976 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 977
77f02a7a
CH		 978 nvme_unmap_data(iod->nvmeq->dev, req);
979 nvme_complete_rq(req);
b60503ba
MW		 980}
981
d783e0bd 982/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 983static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 984{
750dde44
CH		 985 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
986 nvmeq->cq_phase;
d783e0bd
MR		 987}
988
eb281c82 989static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 990{
eb281c82 991 u16 head = nvmeq->cq_head;
adf68f21 992
397c699f
KB		 993 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
994 nvmeq->dbbuf_cq_ei))
995 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 996}
aae239e1 997
5cb525c8 998static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 999{
5cb525c8 1000 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 1001 struct request *req;
adf68f21 1002
83a12fb7
SG		 1003 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
1004 dev_warn(nvmeq->dev->ctrl.device,
1005 "invalid id %d completed on queue %d\n",
1006 cqe->command_id, le16_to_cpu(cqe->sq_id));
1007 return;
b60503ba
MW		 1008 }
1009
83a12fb7
SG		 1010 /*
1011 * AEN requests are special as they don't time out and can
1012 * survive any kind of queue freeze and often don't respond to
1013 * aborts. We don't even bother to allocate a struct request
1014 * for them but rather special case them here.
1015 */
1016 if (unlikely(nvmeq->qid == 0 &&
38dabe21 1017 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 1018 nvme_complete_async_event(&nvmeq->dev->ctrl,
1019 cqe->status, &cqe->result);
a0fa9647 1020 return;
83a12fb7 1021 }
b60503ba 1022
83a12fb7
SG		 1023 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1024 nvme_end_request(req, cqe->status, cqe->result);
1025}
b60503ba 1026
5cb525c8 1027static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1028{
5cb525c8
JA		 1029 while (start != end) {
1030 nvme_handle_cqe(nvmeq, start);
1031 if (++start == nvmeq->q_depth)
1032 start = 0;
1033 }
1034}
adf68f21 1035
5cb525c8
JA		 1036static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1037{
1038 if (++nvmeq->cq_head == nvmeq->q_depth) {
1039 nvmeq->cq_head = 0;
1040 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 1041 }
a0fa9647
JA		 1042}
1043
1052b8ac
JA		 1044static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1045 u16 *end, unsigned int tag)
a0fa9647 1046{
1052b8ac 1047 int found = 0;
b60503ba 1048
5cb525c8 1049 *start = nvmeq->cq_head;
1052b8ac
JA		 1050 while (nvme_cqe_pending(nvmeq)) {
1051 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1052 found++;
5cb525c8 1053 nvme_update_cq_head(nvmeq);
920d13a8 1054 }
5cb525c8 1055 *end = nvmeq->cq_head;
eb281c82 1056
5cb525c8 1057 if (*start != *end)
920d13a8 1058 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1059 return found;
b60503ba
MW		 1060}
1061
1062static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1063{
58ffacb5 1064 struct nvme_queue *nvmeq = data;
68fa9dbe 1065 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1066 u16 start, end;
1067
1ab0cd69 1068 spin_lock(&nvmeq->cq_lock);
68fa9dbe
JA		 1069 if (nvmeq->cq_head != nvmeq->last_cq_head)
1070 ret = IRQ_HANDLED;
5cb525c8 1071 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1072 nvmeq->last_cq_head = nvmeq->cq_head;
1ab0cd69 1073 spin_unlock(&nvmeq->cq_lock);
5cb525c8 1074
68fa9dbe
JA		 1075 if (start != end) {
1076 nvme_complete_cqes(nvmeq, start, end);
1077 return IRQ_HANDLED;
1078 }
1079
1080 return ret;
58ffacb5
MW		 1081}
1082
1083static irqreturn_t nvme_irq_check(int irq, void *data)
1084{
1085 struct nvme_queue *nvmeq = data;
750dde44 1086 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1087 return IRQ_WAKE_THREAD;
1088 return IRQ_NONE;
58ffacb5
MW		 1089}
1090
7776db1c 1091static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1092{
5cb525c8 1093 u16 start, end;
1052b8ac 1094 int found;
a0fa9647 1095
750dde44 1096 if (!nvme_cqe_pending(nvmeq))
442e19b7 1097 return 0;
a0fa9647 1098
1ab0cd69 1099 spin_lock_irq(&nvmeq->cq_lock);
5cb525c8 1100 found = nvme_process_cq(nvmeq, &start, &end, tag);
1ab0cd69 1101 spin_unlock_irq(&nvmeq->cq_lock);
442e19b7 1102
5cb525c8 1103 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1104 return found;
a0fa9647
JA		 1105}
1106
9743139c 1107static int nvme_poll(struct blk_mq_hw_ctx *hctx)
7776db1c
KB		 1108{
1109 struct nvme_queue *nvmeq = hctx->driver_data;
1110
9743139c 1111 return __nvme_poll(nvmeq, -1);
7776db1c
KB		 1112}
1113
9743139c 1114static int nvme_poll_noirq(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1115{
1116 struct nvme_queue *nvmeq = hctx->driver_data;
1117 u16 start, end;
1118 bool found;
1119
1120 if (!nvme_cqe_pending(nvmeq))
1121 return 0;
1122
1123 spin_lock(&nvmeq->cq_lock);
9743139c 1124 found = nvme_process_cq(nvmeq, &start, &end, -1);
dabcefab
JA		 1125 spin_unlock(&nvmeq->cq_lock);
1126
1127 nvme_complete_cqes(nvmeq, start, end);
1128 return found;
1129}
1130
ad22c355 1131static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1132{
f866fc42 1133 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1134 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1135 struct nvme_command c;
b60503ba 1136
a4aea562
MB		 1137 memset(&c, 0, sizeof(c));
1138 c.common.opcode = nvme_admin_async_event;
ad22c355 1139 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1140 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1141}
1142
b60503ba 1143static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1144{
b60503ba
MW		 1145 struct nvme_command c;
1146
1147 memset(&c, 0, sizeof(c));
1148 c.delete_queue.opcode = opcode;
1149 c.delete_queue.qid = cpu_to_le16(id);
1150
1c63dc66 1151 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1152}
1153
b60503ba 1154static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1155 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1156{
b60503ba 1157 struct nvme_command c;
4b04cc6a
JA		 1158 int flags = NVME_QUEUE_PHYS_CONTIG;
1159
1160 if (vector != -1)
1161 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1162
d29ec824 1163 /*
16772ae6 1164 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1165 * is attached to the request.
1166 */
b60503ba
MW		 1167 memset(&c, 0, sizeof(c));
1168 c.create_cq.opcode = nvme_admin_create_cq;
1169 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1170 c.create_cq.cqid = cpu_to_le16(qid);
1171 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1172 c.create_cq.cq_flags = cpu_to_le16(flags);
4b04cc6a
JA		 1173 if (vector != -1)
1174 c.create_cq.irq_vector = cpu_to_le16(vector);
1175 else
1176 c.create_cq.irq_vector = 0;
b60503ba 1177
1c63dc66 1178 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1179}
1180
1181static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1182 struct nvme_queue *nvmeq)
1183{
9abd68ef 1184 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1185 struct nvme_command c;
81c1cd98 1186 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1187
9abd68ef
JA		 1188 /*
1189 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1190 * set. Since URGENT priority is zeroes, it makes all queues
1191 * URGENT.
1192 */
1193 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1194 flags |= NVME_SQ_PRIO_MEDIUM;
1195
d29ec824 1196 /*
16772ae6 1197 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1198 * is attached to the request.
1199 */
b60503ba
MW		 1200 memset(&c, 0, sizeof(c));
1201 c.create_sq.opcode = nvme_admin_create_sq;
1202 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1203 c.create_sq.sqid = cpu_to_le16(qid);
1204 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1205 c.create_sq.sq_flags = cpu_to_le16(flags);
1206 c.create_sq.cqid = cpu_to_le16(qid);
1207
1c63dc66 1208 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1209}
1210
1211static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1212{
1213 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1214}
1215
1216static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1217{
1218 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1219}
1220
2a842aca 1221static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1222{
f4800d6d
CH		 1223 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1224 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1225
27fa9bc5
CH		 1226 dev_warn(nvmeq->dev->ctrl.device,
1227 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1228 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1229 blk_mq_free_request(req);
bc5fc7e4
MW		 1230}
1231
b2a0eb1a
KB		 1232static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1233{
1234
1235 /* If true, indicates loss of adapter communication, possibly by a
1236 * NVMe Subsystem reset.
1237 */
1238 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1239
ad70062c
JW		 1240 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1241 switch (dev->ctrl.state) {
1242 case NVME_CTRL_RESETTING:
ad6a0a52 1243 case NVME_CTRL_CONNECTING:
b2a0eb1a 1244 return false;
ad70062c
JW		 1245 default:
1246 break;
1247 }
b2a0eb1a
KB		 1248
1249 /* We shouldn't reset unless the controller is on fatal error state
1250 * _or_ if we lost the communication with it.
1251 */
1252 if (!(csts & NVME_CSTS_CFS) && !nssro)
1253 return false;
1254
b2a0eb1a
KB		 1255 return true;
1256}
1257
1258static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1259{
1260 /* Read a config register to help see what died. */
1261 u16 pci_status;
1262 int result;
1263
1264 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1265 &pci_status);
1266 if (result == PCIBIOS_SUCCESSFUL)
1267 dev_warn(dev->ctrl.device,
1268 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1269 csts, pci_status);
1270 else
1271 dev_warn(dev->ctrl.device,
1272 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1273 csts, result);
1274}
1275
31c7c7d2 1276static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1277{
f4800d6d
CH		 1278 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1279 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1280 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1281 struct request *abort_req;
a4aea562 1282 struct nvme_command cmd;
b2a0eb1a
KB		 1283 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1284
651438bb
WX		 1285 /* If PCI error recovery process is happening, we cannot reset or
1286 * the recovery mechanism will surely fail.
1287 */
1288 mb();
1289 if (pci_channel_offline(to_pci_dev(dev->dev)))
1290 return BLK_EH_RESET_TIMER;
1291
b2a0eb1a
KB		 1292 /*
1293 * Reset immediately if the controller is failed
1294 */
1295 if (nvme_should_reset(dev, csts)) {
1296 nvme_warn_reset(dev, csts);
1297 nvme_dev_disable(dev, false);
d86c4d8e 1298 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1299 return BLK_EH_DONE;
b2a0eb1a 1300 }
c30341dc 1301
7776db1c
KB		 1302 /*
1303 * Did we miss an interrupt?
1304 */
1305 if (__nvme_poll(nvmeq, req->tag)) {
1306 dev_warn(dev->ctrl.device,
1307 "I/O %d QID %d timeout, completion polled\n",
1308 req->tag, nvmeq->qid);
db8c48e4 1309 return BLK_EH_DONE;
7776db1c
KB		 1310 }
1311
31c7c7d2 1312 /*
fd634f41
CH		 1313 * Shutdown immediately if controller times out while starting. The
1314 * reset work will see the pci device disabled when it gets the forced
1315 * cancellation error. All outstanding requests are completed on
db8c48e4 1316 * shutdown, so we return BLK_EH_DONE.
fd634f41 1317 */
4244140d
KB		 1318 switch (dev->ctrl.state) {
1319 case NVME_CTRL_CONNECTING:
1320 case NVME_CTRL_RESETTING:
b9cac43c 1321 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1322 "I/O %d QID %d timeout, disable controller\n",
1323 req->tag, nvmeq->qid);
a5cdb68c 1324 nvme_dev_disable(dev, false);
27fa9bc5 1325 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1326 return BLK_EH_DONE;
4244140d
KB		 1327 default:
1328 break;
c30341dc
KB		 1329 }
1330
fd634f41
CH		 1331 /*
1332 * Shutdown the controller immediately and schedule a reset if the
1333 * command was already aborted once before and still hasn't been
1334 * returned to the driver, or if this is the admin queue.
31c7c7d2 1335 */
f4800d6d 1336 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1337 dev_warn(dev->ctrl.device,
e1569a16
KB		 1338 "I/O %d QID %d timeout, reset controller\n",
1339 req->tag, nvmeq->qid);
a5cdb68c 1340 nvme_dev_disable(dev, false);
d86c4d8e 1341 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1342
27fa9bc5 1343 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1344 return BLK_EH_DONE;
c30341dc 1345 }
c30341dc 1346
e7a2a87d 1347 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1348 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1349 return BLK_EH_RESET_TIMER;
6bf25d16 1350 }
7bf7d778 1351 iod->aborted = 1;
a4aea562 1352
c30341dc
KB		 1353 memset(&cmd, 0, sizeof(cmd));
1354 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1355 cmd.abort.cid = req->tag;
c30341dc 1356 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1357
1b3c47c1
SG		 1358 dev_warn(nvmeq->dev->ctrl.device,
1359 "I/O %d QID %d timeout, aborting\n",
1360 req->tag, nvmeq->qid);
e7a2a87d
CH		 1361
1362 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1363 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1364 if (IS_ERR(abort_req)) {
1365 atomic_inc(&dev->ctrl.abort_limit);
1366 return BLK_EH_RESET_TIMER;
1367 }
1368
1369 abort_req->timeout = ADMIN_TIMEOUT;
1370 abort_req->end_io_data = NULL;
1371 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1372
31c7c7d2
CH		 1373 /*
1374 * The aborted req will be completed on receiving the abort req.
1375 * We enable the timer again. If hit twice, it'll cause a device reset,
1376 * as the device then is in a faulty state.
1377 */
1378 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1379}
1380
a4aea562
MB		 1381static void nvme_free_queue(struct nvme_queue *nvmeq)
1382{
9e866774
MW		 1383 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1384 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
0f238ff5
LG		 1385
1386 if (nvmeq->sq_cmds) {
1387 if (nvmeq->sq_cmds_is_io)
1388 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1389 nvmeq->sq_cmds,
1390 SQ_SIZE(nvmeq->q_depth));
1391 else
1392 dma_free_coherent(nvmeq->q_dmadev,
1393 SQ_SIZE(nvmeq->q_depth),
1394 nvmeq->sq_cmds,
1395 nvmeq->sq_dma_addr);
1396 }
9e866774
MW		 1397}
1398
a1a5ef99 1399static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1400{
1401 int i;
1402
d858e5f0 1403 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1404 dev->ctrl.queue_count--;
147b27e4 1405 nvme_free_queue(&dev->queues[i]);
121c7ad4 1406 }
22404274
KB		 1407}
1408
4d115420
KB		 1409/**
1410 * nvme_suspend_queue - put queue into suspended state
40581d1a 1411 * @nvmeq: queue to suspend
4d115420
KB		 1412 */
1413static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1414{
2b25d981 1415 int vector;
b60503ba 1416
1ab0cd69 1417 spin_lock_irq(&nvmeq->cq_lock);
4b04cc6a 1418 if (nvmeq->cq_vector == -1 && !nvmeq->polled) {
1ab0cd69 1419 spin_unlock_irq(&nvmeq->cq_lock);
2b25d981
KB		 1420 return 1;
1421 }
0ff199cb 1422 vector = nvmeq->cq_vector;
42f61420 1423 nvmeq->dev->online_queues--;
2b25d981 1424 nvmeq->cq_vector = -1;
4b04cc6a 1425 nvmeq->polled = false;
1ab0cd69 1426 spin_unlock_irq(&nvmeq->cq_lock);
a09115b2 1427
d1f06f4a
JA		 1428 /*
1429 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1430 * having to grab the lock.
1431 */
1432 mb();
a09115b2 1433
1c63dc66 1434 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1435 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
6df3dbc8 1436
4b04cc6a
JA		 1437 if (vector != -1)
1438 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
b60503ba 1439
4d115420
KB		 1440 return 0;
1441}
b60503ba 1442
a5cdb68c 1443static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1444{
147b27e4 1445 struct nvme_queue *nvmeq = &dev->queues[0];
5cb525c8 1446 u16 start, end;
4d115420 1447
a5cdb68c
KB		 1448 if (shutdown)
1449 nvme_shutdown_ctrl(&dev->ctrl);
1450 else
20d0dfe6 1451 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1452
1ab0cd69 1453 spin_lock_irq(&nvmeq->cq_lock);
5cb525c8 1454 nvme_process_cq(nvmeq, &start, &end, -1);
1ab0cd69 1455 spin_unlock_irq(&nvmeq->cq_lock);
5cb525c8
JA		 1456
1457 nvme_complete_cqes(nvmeq, start, end);
b60503ba
MW		 1458}
1459
8ffaadf7
JD		 1460static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1461 int entry_size)
1462{
1463 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1464 unsigned q_size_aligned = roundup(q_depth * entry_size,
1465 dev->ctrl.page_size);
8ffaadf7
JD		 1466
1467 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1468 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1469 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1470 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1471
1472 /*
1473 * Ensure the reduced q_depth is above some threshold where it
1474 * would be better to map queues in system memory with the
1475 * original depth
1476 */
1477 if (q_depth < 64)
1478 return -ENOMEM;
1479 }
1480
1481 return q_depth;
1482}
1483
1484static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1485 int qid, int depth)
1486{
0f238ff5
LG		 1487 struct pci_dev *pdev = to_pci_dev(dev->dev);
1488
1489 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1490 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1491 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1492 nvmeq->sq_cmds);
1493 nvmeq->sq_cmds_is_io = true;
1494 }
1495
1496 if (!nvmeq->sq_cmds) {
1497 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1498 &nvmeq->sq_dma_addr, GFP_KERNEL);
1499 nvmeq->sq_cmds_is_io = false;
1500 }
8ffaadf7 1501
815c6704
KB		 1502 if (!nvmeq->sq_cmds)
1503 return -ENOMEM;
8ffaadf7
JD		 1504 return 0;
1505}
1506
a6ff7262 1507static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1508{
147b27e4 1509 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1510
62314e40
KB		 1511 if (dev->ctrl.queue_count > qid)
1512 return 0;
b60503ba 1513
e75ec752 1514 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1515 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1516 if (!nvmeq->cqes)
1517 goto free_nvmeq;
b60503ba 1518
8ffaadf7 1519 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1520 goto free_cqdma;
1521
e75ec752 1522 nvmeq->q_dmadev = dev->dev;
091b6092 1523 nvmeq->dev = dev;
1ab0cd69
JA		 1524 spin_lock_init(&nvmeq->sq_lock);
1525 spin_lock_init(&nvmeq->cq_lock);
b60503ba 1526 nvmeq->cq_head = 0;
82123460 1527 nvmeq->cq_phase = 1;
b80d5ccc 1528 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1529 nvmeq->q_depth = depth;
c30341dc 1530 nvmeq->qid = qid;
758dd7fd 1531 nvmeq->cq_vector = -1;
d858e5f0 1532 dev->ctrl.queue_count++;
36a7e993 1533
147b27e4 1534 return 0;
b60503ba
MW		 1535
1536 free_cqdma:
e75ec752 1537 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1538 nvmeq->cq_dma_addr);
1539 free_nvmeq:
147b27e4 1540 return -ENOMEM;
b60503ba
MW		 1541}
1542
dca51e78 1543static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1544{
0ff199cb
CH		 1545 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1546 int nr = nvmeq->dev->ctrl.instance;
1547
1548 if (use_threaded_interrupts) {
1549 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1550 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1551 } else {
1552 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1553 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1554 }
3001082c
MW		 1555}
1556
22404274 1557static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1558{
22404274 1559 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1560
1ab0cd69 1561 spin_lock_irq(&nvmeq->cq_lock);
22404274 1562 nvmeq->sq_tail = 0;
04f3eafd 1563 nvmeq->last_sq_tail = 0;
22404274
KB		 1564 nvmeq->cq_head = 0;
1565 nvmeq->cq_phase = 1;
b80d5ccc 1566 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1567 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1568 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1569 dev->online_queues++;
1ab0cd69 1570 spin_unlock_irq(&nvmeq->cq_lock);
22404274
KB		 1571}
1572
4b04cc6a 1573static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1574{
1575 struct nvme_dev *dev = nvmeq->dev;
1576 int result;
a8e3e0bb 1577 s16 vector;
3f85d50b 1578
22b55601
KB		 1579 /*
1580 * A queue's vector matches the queue identifier unless the controller
1581 * has only one vector available.
1582 */
4b04cc6a
JA		 1583 if (!polled)
1584 vector = dev->num_vecs == 1 ? 0 : qid;
1585 else
1586 vector = -1;
1587
a8e3e0bb 1588 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1589 if (result)
1590 return result;
b60503ba
MW		 1591
1592 result = adapter_alloc_sq(dev, qid, nvmeq);
1593 if (result < 0)
ded45505
KB		 1594 return result;
1595 else if (result)
b60503ba
MW		 1596 goto release_cq;
1597
a8e3e0bb
JW		 1598 /*
1599 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1600 * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1601 * xxx' warning if the create CQ/SQ command times out.
1602 */
1603 nvmeq->cq_vector = vector;
4b04cc6a 1604 nvmeq->polled = polled;
161b8be2 1605 nvme_init_queue(nvmeq, qid);
4b04cc6a
JA		 1606
1607 if (vector != -1) {
1608 result = queue_request_irq(nvmeq);
1609 if (result < 0)
1610 goto release_sq;
1611 }
b60503ba 1612
22404274 1613 return result;
b60503ba 1614
a8e3e0bb
JW		 1615release_sq:
1616 nvmeq->cq_vector = -1;
4b04cc6a 1617 nvmeq->polled = false;
f25a2dfc 1618 dev->online_queues--;
b60503ba 1619 adapter_delete_sq(dev, qid);
a8e3e0bb 1620release_cq:
b60503ba 1621 adapter_delete_cq(dev, qid);
22404274 1622 return result;
b60503ba
MW		 1623}
1624
f363b089 1625static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1626 .queue_rq = nvme_queue_rq,
77f02a7a 1627 .complete = nvme_pci_complete_rq,
a4aea562 1628 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1629 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1630 .init_request = nvme_init_request,
a4aea562
MB		 1631 .timeout = nvme_timeout,
1632};
1633
dabcefab
JA		 1634#define NVME_SHARED_MQ_OPS \
1635 .queue_rq = nvme_queue_rq, \
04f3eafd 1636 .commit_rqs = nvme_commit_rqs, \
dabcefab
JA		 1637 .rq_flags_to_type = nvme_rq_flags_to_type, \
1638 .complete = nvme_pci_complete_rq, \
1639 .init_hctx = nvme_init_hctx, \
1640 .init_request = nvme_init_request, \
1641 .map_queues = nvme_pci_map_queues, \
1642 .timeout = nvme_timeout \
1643
f363b089 1644static const struct blk_mq_ops nvme_mq_ops = {
dabcefab 1645 NVME_SHARED_MQ_OPS,
3b6592f7 1646 .poll = nvme_poll,
a4aea562
MB		 1647};
1648
dabcefab
JA		 1649static const struct blk_mq_ops nvme_mq_poll_noirq_ops = {
1650 NVME_SHARED_MQ_OPS,
1651 .poll = nvme_poll_noirq,
1652};
1653
ea191d2f
KB		 1654static void nvme_dev_remove_admin(struct nvme_dev *dev)
1655{
1c63dc66 1656 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1657 /*
1658 * If the controller was reset during removal, it's possible
1659 * user requests may be waiting on a stopped queue. Start the
1660 * queue to flush these to completion.
1661 */
c81545f9 1662 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1663 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1664 blk_mq_free_tag_set(&dev->admin_tagset);
1665 }
1666}
1667
a4aea562
MB		 1668static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1669{
1c63dc66 1670 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1671 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1672 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1673
38dabe21 1674 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1675 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1676 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1677 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1678 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1679 dev->admin_tagset.driver_data = dev;
1680
1681 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1682 return -ENOMEM;
34b6c231 1683 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1684
1c63dc66
CH		 1685 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1686 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1687 blk_mq_free_tag_set(&dev->admin_tagset);
1688 return -ENOMEM;
1689 }
1c63dc66 1690 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1691 nvme_dev_remove_admin(dev);
1c63dc66 1692 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1693 return -ENODEV;
1694 }
0fb59cbc 1695 } else
c81545f9 1696 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1697
1698 return 0;
1699}
1700
97f6ef64
XY		 1701static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1702{
1703 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1704}
1705
1706static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1707{
1708 struct pci_dev *pdev = to_pci_dev(dev->dev);
1709
1710 if (size <= dev->bar_mapped_size)
1711 return 0;
1712 if (size > pci_resource_len(pdev, 0))
1713 return -ENOMEM;
1714 if (dev->bar)
1715 iounmap(dev->bar);
1716 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1717 if (!dev->bar) {
1718 dev->bar_mapped_size = 0;
1719 return -ENOMEM;
1720 }
1721 dev->bar_mapped_size = size;
1722 dev->dbs = dev->bar + NVME_REG_DBS;
1723
1724 return 0;
1725}
1726
01ad0990 1727static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1728{
ba47e386 1729 int result;
b60503ba
MW		 1730 u32 aqa;
1731 struct nvme_queue *nvmeq;
1732
97f6ef64
XY		 1733 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1734 if (result < 0)
1735 return result;
1736
8ef2074d 1737 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1738 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1739
7a67cbea
CH		 1740 if (dev->subsystem &&
1741 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1742 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1743
20d0dfe6 1744 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1745 if (result < 0)
1746 return result;
b60503ba 1747
a6ff7262 1748 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1749 if (result)
1750 return result;
b60503ba 1751
147b27e4 1752 nvmeq = &dev->queues[0];
b60503ba
MW		 1753 aqa = nvmeq->q_depth - 1;
1754 aqa |= aqa << 16;
1755
7a67cbea
CH		 1756 writel(aqa, dev->bar + NVME_REG_AQA);
1757 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1758 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1759
20d0dfe6 1760 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1761 if (result)
d4875622 1762 return result;
a4aea562 1763
2b25d981 1764 nvmeq->cq_vector = 0;
161b8be2 1765 nvme_init_queue(nvmeq, 0);
dca51e78 1766 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1767 if (result) {
1768 nvmeq->cq_vector = -1;
d4875622 1769 return result;
758dd7fd 1770 }
025c557a 1771
b60503ba
MW		 1772 return result;
1773}
1774
749941f2 1775static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1776{
4b04cc6a 1777 unsigned i, max, rw_queues;
749941f2 1778 int ret = 0;
42f61420 1779
d858e5f0 1780 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1781 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1782 ret = -ENOMEM;
42f61420 1783 break;
749941f2
CH		 1784 }
1785 }
42f61420 1786
d858e5f0 1787 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
4b04cc6a
JA		 1788 if (max != 1 && dev->io_queues[NVMEQ_TYPE_POLL]) {
1789 rw_queues = dev->io_queues[NVMEQ_TYPE_READ] +
1790 dev->io_queues[NVMEQ_TYPE_WRITE];
1791 } else {
1792 rw_queues = max;
1793 }
1794
949928c1 1795 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1796 bool polled = i > rw_queues;
1797
1798 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1799 if (ret)
42f61420 1800 break;
27e8166c 1801 }
749941f2
CH		 1802
1803 /*
1804 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1805 * than the desired amount of queues, and even a controller without
1806 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1807 * be useful to upgrade a buggy firmware for example.
1808 */
1809 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1810}
1811
202021c1
SB		 1812static ssize_t nvme_cmb_show(struct device *dev,
1813 struct device_attribute *attr,
1814 char *buf)
1815{
1816 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1817
c965809c 1818 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1819 ndev->cmbloc, ndev->cmbsz);
1820}
1821static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1822
88de4598 1823static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1824{
88de4598
CH		 1825 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1826
1827 return 1ULL << (12 + 4 * szu);
1828}
1829
1830static u32 nvme_cmb_size(struct nvme_dev *dev)
1831{
1832 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1833}
1834
f65efd6d 1835static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1836{
88de4598 1837 u64 size, offset;
8ffaadf7
JD		 1838 resource_size_t bar_size;
1839 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1840 int bar;
8ffaadf7 1841
9fe5c59f
KB		 1842 if (dev->cmb_size)
1843 return;
1844
7a67cbea 1845 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1846 if (!dev->cmbsz)
1847 return;
202021c1 1848 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1849
88de4598
CH		 1850 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1851 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1852 bar = NVME_CMB_BIR(dev->cmbloc);
1853 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1854
1855 if (offset > bar_size)
f65efd6d 1856 return;
8ffaadf7
JD		 1857
1858 /*
1859 * Controllers may support a CMB size larger than their BAR,
1860 * for example, due to being behind a bridge. Reduce the CMB to
1861 * the reported size of the BAR
1862 */
1863 if (size > bar_size - offset)
1864 size = bar_size - offset;
1865
0f238ff5
LG		 1866 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1867 dev_warn(dev->ctrl.device,
1868 "failed to register the CMB\n");
f65efd6d 1869 return;
0f238ff5
LG		 1870 }
1871
8ffaadf7 1872 dev->cmb_size = size;
0f238ff5
LG		 1873 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1874
1875 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1876 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1877 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1878
1879 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1880 &dev_attr_cmb.attr, NULL))
1881 dev_warn(dev->ctrl.device,
1882 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1883}
1884
1885static inline void nvme_release_cmb(struct nvme_dev *dev)
1886{
0f238ff5 1887 if (dev->cmb_size) {
1c78f773
MG		 1888 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1889 &dev_attr_cmb.attr, NULL);
0f238ff5 1890 dev->cmb_size = 0;
8ffaadf7
JD		 1891 }
1892}
1893
87ad72a5
CH		 1894static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1895{
4033f35d 1896 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1897 struct nvme_command c;
87ad72a5
CH		 1898 int ret;
1899
87ad72a5
CH		 1900 memset(&c, 0, sizeof(c));
1901 c.features.opcode = nvme_admin_set_features;
1902 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1903 c.features.dword11 = cpu_to_le32(bits);
1904 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1905 ilog2(dev->ctrl.page_size));
1906 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1907 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1908 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1909
1910 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1911 if (ret) {
1912 dev_warn(dev->ctrl.device,
1913 "failed to set host mem (err %d, flags %#x).\n",
1914 ret, bits);
1915 }
87ad72a5
CH		 1916 return ret;
1917}
1918
1919static void nvme_free_host_mem(struct nvme_dev *dev)
1920{
1921 int i;
1922
1923 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1924 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1925 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1926
1927 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1928 le64_to_cpu(desc->addr));
1929 }
1930
1931 kfree(dev->host_mem_desc_bufs);
1932 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1933 dma_free_coherent(dev->dev,
1934 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1935 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1936 dev->host_mem_descs = NULL;
7e5dd57e 1937 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1938}
1939
92dc6895
CH		 1940static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1941 u32 chunk_size)
9d713c2b 1942{
87ad72a5 1943 struct nvme_host_mem_buf_desc *descs;
92dc6895 1944 u32 max_entries, len;
4033f35d 1945 dma_addr_t descs_dma;
2ee0e4ed 1946 int i = 0;
87ad72a5 1947 void **bufs;
6fbcde66 1948 u64 size, tmp;
87ad72a5 1949
87ad72a5
CH		 1950 tmp = (preferred + chunk_size - 1);
1951 do_div(tmp, chunk_size);
1952 max_entries = tmp;
044a9df1
CH		 1953
1954 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1955 max_entries = dev->ctrl.hmmaxd;
1956
4033f35d
CH		 1957 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1958 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1959 if (!descs)
1960 goto out;
1961
1962 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1963 if (!bufs)
1964 goto out_free_descs;
1965
244a8fe4 1966 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1967 dma_addr_t dma_addr;
1968
50cdb7c6 1969 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1970 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1971 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1972 if (!bufs[i])
1973 break;
1974
1975 descs[i].addr = cpu_to_le64(dma_addr);
1976 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1977 i++;
1978 }
1979
92dc6895 1980 if (!size)
87ad72a5 1981 goto out_free_bufs;
87ad72a5 1982
87ad72a5
CH		 1983 dev->nr_host_mem_descs = i;
1984 dev->host_mem_size = size;
1985 dev->host_mem_descs = descs;
4033f35d 1986 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1987 dev->host_mem_desc_bufs = bufs;
1988 return 0;
1989
1990out_free_bufs:
1991 while (--i >= 0) {
1992 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1993
1994 dma_free_coherent(dev->dev, size, bufs[i],
1995 le64_to_cpu(descs[i].addr));
1996 }
1997
1998 kfree(bufs);
1999out_free_descs:
4033f35d
CH		 2000 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2001 descs_dma);
87ad72a5 2002out:
87ad72a5
CH		 2003 dev->host_mem_descs = NULL;
2004 return -ENOMEM;
2005}
2006
92dc6895
CH		 2007static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2008{
2009 u32 chunk_size;
2010
2011 /* start big and work our way down */
30f92d62 2012 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 2013 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 2014 chunk_size /= 2) {
2015 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2016 if (!min || dev->host_mem_size >= min)
2017 return 0;
2018 nvme_free_host_mem(dev);
2019 }
2020 }
2021
2022 return -ENOMEM;
2023}
2024
9620cfba 2025static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2026{
2027 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2028 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2029 u64 min = (u64)dev->ctrl.hmmin * 4096;
2030 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2031 int ret;
87ad72a5
CH		 2032
2033 preferred = min(preferred, max);
2034 if (min > max) {
2035 dev_warn(dev->ctrl.device,
2036 "min host memory (%lld MiB) above limit (%d MiB).\n",
2037 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2038 nvme_free_host_mem(dev);
9620cfba 2039 return 0;
87ad72a5
CH		 2040 }
2041
2042 /*
2043 * If we already have a buffer allocated check if we can reuse it.
2044 */
2045 if (dev->host_mem_descs) {
2046 if (dev->host_mem_size >= min)
2047 enable_bits |= NVME_HOST_MEM_RETURN;
2048 else
2049 nvme_free_host_mem(dev);
2050 }
2051
2052 if (!dev->host_mem_descs) {
92dc6895
CH		 2053 if (nvme_alloc_host_mem(dev, min, preferred)) {
2054 dev_warn(dev->ctrl.device,
2055 "failed to allocate host memory buffer.\n");
9620cfba 2056 return 0; /* controller must work without HMB */
92dc6895
CH		 2057 }
2058
2059 dev_info(dev->ctrl.device,
2060 "allocated %lld MiB host memory buffer.\n",
2061 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2062 }
2063
9620cfba
CH		 2064 ret = nvme_set_host_mem(dev, enable_bits);
2065 if (ret)
87ad72a5 2066 nvme_free_host_mem(dev);
9620cfba 2067 return ret;
9d713c2b
KB		 2068}
2069
3b6592f7
JA		 2070static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int nr_io_queues)
2071{
2072 unsigned int this_w_queues = write_queues;
4b04cc6a 2073 unsigned int this_p_queues = poll_queues;
3b6592f7
JA		 2074
2075 /*
2076 * Setup read/write queue split
2077 */
2078 if (nr_io_queues == 1) {
2079 dev->io_queues[NVMEQ_TYPE_READ] = 1;
2080 dev->io_queues[NVMEQ_TYPE_WRITE] = 0;
4b04cc6a 2081 dev->io_queues[NVMEQ_TYPE_POLL] = 0;
3b6592f7
JA		 2082 return;
2083 }
2084
4b04cc6a
JA		 2085 /*
2086 * Configure number of poll queues, if set
2087 */
2088 if (this_p_queues) {
2089 /*
2090 * We need at least one queue left. With just one queue, we'll
2091 * have a single shared read/write set.
2092 */
2093 if (this_p_queues >= nr_io_queues) {
2094 this_w_queues = 0;
2095 this_p_queues = nr_io_queues - 1;
2096 }
2097
2098 dev->io_queues[NVMEQ_TYPE_POLL] = this_p_queues;
2099 nr_io_queues -= this_p_queues;
2100 } else
2101 dev->io_queues[NVMEQ_TYPE_POLL] = 0;
2102
3b6592f7
JA		 2103 /*
2104 * If 'write_queues' is set, ensure it leaves room for at least
2105 * one read queue
2106 */
2107 if (this_w_queues >= nr_io_queues)
2108 this_w_queues = nr_io_queues - 1;
2109
2110 /*
2111 * If 'write_queues' is set to zero, reads and writes will share
2112 * a queue set.
2113 */
2114 if (!this_w_queues) {
2115 dev->io_queues[NVMEQ_TYPE_WRITE] = 0;
2116 dev->io_queues[NVMEQ_TYPE_READ] = nr_io_queues;
2117 } else {
2118 dev->io_queues[NVMEQ_TYPE_WRITE] = this_w_queues;
2119 dev->io_queues[NVMEQ_TYPE_READ] = nr_io_queues - this_w_queues;
2120 }
2121}
2122
2123static int nvme_setup_irqs(struct nvme_dev *dev, int nr_io_queues)
2124{
2125 struct pci_dev *pdev = to_pci_dev(dev->dev);
2126 int irq_sets[2];
2127 struct irq_affinity affd = {
2128 .pre_vectors = 1,
2129 .nr_sets = ARRAY_SIZE(irq_sets),
2130 .sets = irq_sets,
2131 };
30e06628 2132 int result = 0;
3b6592f7
JA		 2133
2134 /*
2135 * For irq sets, we have to ask for minvec == maxvec. This passes
2136 * any reduction back to us, so we can adjust our queue counts and
2137 * IRQ vector needs.
2138 */
2139 do {
2140 nvme_calc_io_queues(dev, nr_io_queues);
2141 irq_sets[0] = dev->io_queues[NVMEQ_TYPE_READ];
2142 irq_sets[1] = dev->io_queues[NVMEQ_TYPE_WRITE];
2143 if (!irq_sets[1])
2144 affd.nr_sets = 1;
2145
2146 /*
db29eb05
JA		 2147 * If we got a failure and we're down to asking for just
2148 * 1 + 1 queues, just ask for a single vector. We'll share
2149 * that between the single IO queue and the admin queue.
3b6592f7 2150 */
db29eb05 2151 if (!(result < 0 && nr_io_queues == 1))
30e06628 2152 nr_io_queues = irq_sets[0] + irq_sets[1] + 1;
3b6592f7
JA		 2153
2154 result = pci_alloc_irq_vectors_affinity(pdev, nr_io_queues,
2155 nr_io_queues,
2156 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2157
2158 /*
db29eb05
JA		 2159 * Need to reduce our vec counts. If we get ENOSPC, the
2160 * platform should support mulitple vecs, we just need
2161 * to decrease our ask. If we get EINVAL, the platform
2162 * likely does not. Back down to ask for just one vector.
3b6592f7
JA		 2163 */
2164 if (result == -ENOSPC) {
2165 nr_io_queues--;
2166 if (!nr_io_queues)
2167 return result;
2168 continue;
db29eb05
JA		 2169 } else if (result == -EINVAL) {
2170 nr_io_queues = 1;
2171 continue;
3b6592f7
JA		 2172 } else if (result <= 0)
2173 return -EIO;
2174 break;
2175 } while (1);
2176
2177 return result;
2178}
2179
8d85fce7 2180static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2181{
147b27e4 2182 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2183 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2184 int result, nr_io_queues;
2185 unsigned long size;
b60503ba 2186
3b6592f7 2187 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2188 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2189 if (result < 0)
1b23484b 2190 return result;
9a0be7ab 2191
f5fa90dc 2192 if (nr_io_queues == 0)
a5229050 2193 return 0;
b60503ba 2194
0f238ff5 2195 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2196 result = nvme_cmb_qdepth(dev, nr_io_queues,
2197 sizeof(struct nvme_command));
2198 if (result > 0)
2199 dev->q_depth = result;
2200 else
0f238ff5 2201 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2202 }
2203
97f6ef64
XY		 2204 do {
2205 size = db_bar_size(dev, nr_io_queues);
2206 result = nvme_remap_bar(dev, size);
2207 if (!result)
2208 break;
2209 if (!--nr_io_queues)
2210 return -ENOMEM;
2211 } while (1);
2212 adminq->q_db = dev->dbs;
f1938f6e 2213
9d713c2b 2214 /* Deregister the admin queue's interrupt */
0ff199cb 2215 pci_free_irq(pdev, 0, adminq);
9d713c2b 2216
e32efbfc
JA		 2217 /*
2218 * If we enable msix early due to not intx, disable it again before
2219 * setting up the full range we need.
2220 */
dca51e78 2221 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2222
2223 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2224 if (result <= 0)
dca51e78 2225 return -EIO;
3b6592f7 2226
22b55601 2227 dev->num_vecs = result;
4b04cc6a
JA		 2228 result = max(result - 1, 1);
2229 dev->max_qid = result + dev->io_queues[NVMEQ_TYPE_POLL];
fa08a396 2230
4b04cc6a 2231 dev_info(dev->ctrl.device, "%d/%d/%d read/write/poll queues\n",
3b6592f7 2232 dev->io_queues[NVMEQ_TYPE_READ],
4b04cc6a
JA		 2233 dev->io_queues[NVMEQ_TYPE_WRITE],
2234 dev->io_queues[NVMEQ_TYPE_POLL]);
3b6592f7 2235
063a8096
MW		 2236 /*
2237 * Should investigate if there's a performance win from allocating
2238 * more queues than interrupt vectors; it might allow the submission
2239 * path to scale better, even if the receive path is limited by the
2240 * number of interrupts.
2241 */
063a8096 2242
dca51e78 2243 result = queue_request_irq(adminq);
758dd7fd
JD		 2244 if (result) {
2245 adminq->cq_vector = -1;
d4875622 2246 return result;
758dd7fd 2247 }
749941f2 2248 return nvme_create_io_queues(dev);
b60503ba
MW		 2249}
2250
2a842aca 2251static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2252{
db3cbfff 2253 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2254
db3cbfff
KB		 2255 blk_mq_free_request(req);
2256 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 2257}
2258
2a842aca 2259static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2260{
db3cbfff 2261 struct nvme_queue *nvmeq = req->end_io_data;
5cb525c8 2262 u16 start, end;
a5768aa8 2263
db3cbfff
KB		 2264 if (!error) {
2265 unsigned long flags;
2266
0bc88192 2267 spin_lock_irqsave(&nvmeq->cq_lock, flags);
5cb525c8 2268 nvme_process_cq(nvmeq, &start, &end, -1);
1ab0cd69 2269 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
5cb525c8
JA		 2270
2271 nvme_complete_cqes(nvmeq, start, end);
a5768aa8 2272 }
db3cbfff
KB		 2273
2274 nvme_del_queue_end(req, error);
a5768aa8
KB		 2275}
2276
db3cbfff 2277static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2278{
db3cbfff
KB		 2279 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2280 struct request *req;
2281 struct nvme_command cmd;
bda4e0fb 2282
db3cbfff
KB		 2283 memset(&cmd, 0, sizeof(cmd));
2284 cmd.delete_queue.opcode = opcode;
2285 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2286
eb71f435 2287 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2288 if (IS_ERR(req))
2289 return PTR_ERR(req);
bda4e0fb 2290
db3cbfff
KB		 2291 req->timeout = ADMIN_TIMEOUT;
2292 req->end_io_data = nvmeq;
2293
2294 blk_execute_rq_nowait(q, NULL, req, false,
2295 opcode == nvme_admin_delete_cq ?
2296 nvme_del_cq_end : nvme_del_queue_end);
2297 return 0;
bda4e0fb
KB		 2298}
2299
ee9aebb2 2300static void nvme_disable_io_queues(struct nvme_dev *dev)
a5768aa8 2301{
ee9aebb2 2302 int pass, queues = dev->online_queues - 1;
db3cbfff
KB		 2303 unsigned long timeout;
2304 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2305
db3cbfff 2306 for (pass = 0; pass < 2; pass++) {
014a0d60 2307 int sent = 0, i = queues;
db3cbfff
KB		 2308
2309 reinit_completion(&dev->ioq_wait);
2310 retry:
2311 timeout = ADMIN_TIMEOUT;
c21377f8 2312 for (; i > 0; i--, sent++)
147b27e4 2313 if (nvme_delete_queue(&dev->queues[i], opcode))
db3cbfff 2314 break;
c21377f8 2315
db3cbfff
KB		 2316 while (sent--) {
2317 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2318 if (timeout == 0)
2319 return;
2320 if (i)
2321 goto retry;
2322 }
2323 opcode = nvme_admin_delete_cq;
2324 }
a5768aa8
KB		 2325}
2326
422ef0c7 2327/*
2b1b7e78 2328 * return error value only when tagset allocation failed
422ef0c7 2329 */
8d85fce7 2330static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2331{
2b1b7e78
JW		 2332 int ret;
2333
5bae7f73 2334 if (!dev->ctrl.tagset) {
dabcefab
JA		 2335 if (!dev->io_queues[NVMEQ_TYPE_POLL])
2336 dev->tagset.ops = &nvme_mq_ops;
2337 else
2338 dev->tagset.ops = &nvme_mq_poll_noirq_ops;
2339
ffe7704d 2340 dev->tagset.nr_hw_queues = dev->online_queues - 1;
3b6592f7 2341 dev->tagset.nr_maps = NVMEQ_TYPE_NR;
ffe7704d
KB		 2342 dev->tagset.timeout = NVME_IO_TIMEOUT;
2343 dev->tagset.numa_node = dev_to_node(dev->dev);
2344 dev->tagset.queue_depth =
a4aea562 2345 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2346 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2347 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2348 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2349 nvme_pci_cmd_size(dev, true));
2350 }
ffe7704d
KB		 2351 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2352 dev->tagset.driver_data = dev;
b60503ba 2353
2b1b7e78
JW		 2354 ret = blk_mq_alloc_tag_set(&dev->tagset);
2355 if (ret) {
2356 dev_warn(dev->ctrl.device,
2357 "IO queues tagset allocation failed %d\n", ret);
2358 return ret;
2359 }
5bae7f73 2360 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2361
2362 nvme_dbbuf_set(dev);
949928c1
KB		 2363 } else {
2364 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2365
2366 /* Free previously allocated queues that are no longer usable */
2367 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2368 }
949928c1 2369
e1e5e564 2370 return 0;
b60503ba
MW		 2371}
2372
b00a726a 2373static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2374{
b00a726a 2375 int result = -ENOMEM;
e75ec752 2376 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2377
2378 if (pci_enable_device_mem(pdev))
2379 return result;
2380
0877cb0d 2381 pci_set_master(pdev);
0877cb0d 2382
e75ec752
CH		 2383 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2384 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2385 goto disable;
0877cb0d 2386
7a67cbea 2387 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2388 result = -ENODEV;
b00a726a 2389 goto disable;
0e53d180 2390 }
e32efbfc
JA		 2391
2392 /*
a5229050
KB		 2393 * Some devices and/or platforms don't advertise or work with INTx
2394 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2395 * adjust this later.
e32efbfc 2396 */
dca51e78
CH		 2397 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2398 if (result < 0)
2399 return result;
e32efbfc 2400
20d0dfe6 2401 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2402
20d0dfe6 2403 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2404 io_queue_depth);
20d0dfe6 2405 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2406 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2407
2408 /*
2409 * Temporary fix for the Apple controller found in the MacBook8,1 and
2410 * some MacBook7,1 to avoid controller resets and data loss.
2411 */
2412 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2413 dev->q_depth = 2;
9bdcfb10
CH		 2414 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2415 "set queue depth=%u to work around controller resets\n",
1f390c1f 2416 dev->q_depth);
d554b5e1
MP		 2417 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2418 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2419 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2420 dev->q_depth = 64;
2421 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2422 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2423 }
2424
f65efd6d 2425 nvme_map_cmb(dev);
202021c1 2426
a0a3408e
KB		 2427 pci_enable_pcie_error_reporting(pdev);
2428 pci_save_state(pdev);
0877cb0d
KB		 2429 return 0;
2430
2431 disable:
0877cb0d
KB		 2432 pci_disable_device(pdev);
2433 return result;
2434}
2435
2436static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2437{
2438 if (dev->bar)
2439 iounmap(dev->bar);
a1f447b3 2440 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2441}
2442
2443static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2444{
e75ec752
CH		 2445 struct pci_dev *pdev = to_pci_dev(dev->dev);
2446
dca51e78 2447 pci_free_irq_vectors(pdev);
0877cb0d 2448
a0a3408e
KB		 2449 if (pci_is_enabled(pdev)) {
2450 pci_disable_pcie_error_reporting(pdev);
e75ec752 2451 pci_disable_device(pdev);
4d115420 2452 }
4d115420
KB		 2453}
2454
a5cdb68c 2455static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2456{
ee9aebb2 2457 int i;
302ad8cc
KB		 2458 bool dead = true;
2459 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2460
77bf25ea 2461 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2462 if (pci_is_enabled(pdev)) {
2463 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2464
ebef7368
KB		 2465 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2466 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2467 nvme_start_freeze(&dev->ctrl);
2468 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2469 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2470 }
c21377f8 2471
302ad8cc
KB		 2472 /*
2473 * Give the controller a chance to complete all entered requests if
2474 * doing a safe shutdown.
2475 */
87ad72a5
CH		 2476 if (!dead) {
2477 if (shutdown)
2478 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2479 }
2480
2481 nvme_stop_queues(&dev->ctrl);
87ad72a5 2482
64ee0ac0 2483 if (!dead && dev->ctrl.queue_count > 0) {
ee9aebb2 2484 nvme_disable_io_queues(dev);
a5cdb68c 2485 nvme_disable_admin_queue(dev, shutdown);
4d115420 2486 }
ee9aebb2
KB		 2487 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2488 nvme_suspend_queue(&dev->queues[i]);
2489
b00a726a 2490 nvme_pci_disable(dev);
07836e65 2491
e1958e65
ML		 2492 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2493 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2494
2495 /*
2496 * The driver will not be starting up queues again if shutting down so
2497 * must flush all entered requests to their failed completion to avoid
2498 * deadlocking blk-mq hot-cpu notifier.
2499 */
2500 if (shutdown)
2501 nvme_start_queues(&dev->ctrl);
77bf25ea 2502 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2503}
2504
091b6092
MW		 2505static int nvme_setup_prp_pools(struct nvme_dev *dev)
2506{
e75ec752 2507 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2508 PAGE_SIZE, PAGE_SIZE, 0);
2509 if (!dev->prp_page_pool)
2510 return -ENOMEM;
2511
99802a7a 2512 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2513 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2514 256, 256, 0);
2515 if (!dev->prp_small_pool) {
2516 dma_pool_destroy(dev->prp_page_pool);
2517 return -ENOMEM;
2518 }
091b6092
MW		 2519 return 0;
2520}
2521
2522static void nvme_release_prp_pools(struct nvme_dev *dev)
2523{
2524 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2525 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2526}
2527
1673f1f0 2528static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2529{
1673f1f0 2530 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2531
f9f38e33 2532 nvme_dbbuf_dma_free(dev);
e75ec752 2533 put_device(dev->dev);
4af0e21c
KB		 2534 if (dev->tagset.tags)
2535 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2536 if (dev->ctrl.admin_q)
2537 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2538 kfree(dev->queues);
e286bcfc 2539 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2540 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2541 kfree(dev);
2542}
2543
f58944e2
KB		 2544static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2545{
237045fc 2546 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2547
d22524a4 2548 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2549 nvme_dev_disable(dev, false);
9f9cafc1 2550 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2551 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2552 nvme_put_ctrl(&dev->ctrl);
2553}
2554
fd634f41 2555static void nvme_reset_work(struct work_struct *work)
5e82e952 2556{
d86c4d8e
CH		 2557 struct nvme_dev *dev =
2558 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2559 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2560 int result = -ENODEV;
2b1b7e78 2561 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2562
82b057ca 2563 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2564 goto out;
5e82e952 2565
fd634f41
CH		 2566 /*
2567 * If we're called to reset a live controller first shut it down before
2568 * moving on.
2569 */
b00a726a 2570 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2571 nvme_dev_disable(dev, false);
5e82e952 2572
ad70062c 2573 /*
ad6a0a52 2574 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2575 * initializing procedure here.
2576 */
ad6a0a52 2577 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2578 dev_warn(dev->ctrl.device,
ad6a0a52 2579 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2580 goto out;
2581 }
2582
b00a726a 2583 result = nvme_pci_enable(dev);
f0b50732 2584 if (result)
3cf519b5 2585 goto out;
f0b50732 2586
01ad0990 2587 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2588 if (result)
f58944e2 2589 goto out;
f0b50732 2590
0fb59cbc
KB		 2591 result = nvme_alloc_admin_tags(dev);
2592 if (result)
f58944e2 2593 goto out;
b9afca3e 2594
943e942e
JA		 2595 /*
2596 * Limit the max command size to prevent iod->sg allocations going
2597 * over a single page.
2598 */
2599 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2600 dev->ctrl.max_segments = NVME_MAX_SEGS;
2601
ce4541f4
CH		 2602 result = nvme_init_identify(&dev->ctrl);
2603 if (result)
f58944e2 2604 goto out;
ce4541f4 2605
e286bcfc
SB		 2606 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2607 if (!dev->ctrl.opal_dev)
2608 dev->ctrl.opal_dev =
2609 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2610 else if (was_suspend)
2611 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2612 } else {
2613 free_opal_dev(dev->ctrl.opal_dev);
2614 dev->ctrl.opal_dev = NULL;
4f1244c8 2615 }
a98e58e5 2616
f9f38e33
HK		 2617 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2618 result = nvme_dbbuf_dma_alloc(dev);
2619 if (result)
2620 dev_warn(dev->dev,
2621 "unable to allocate dma for dbbuf\n");
2622 }
2623
9620cfba
CH		 2624 if (dev->ctrl.hmpre) {
2625 result = nvme_setup_host_mem(dev);
2626 if (result < 0)
2627 goto out;
2628 }
87ad72a5 2629
f0b50732 2630 result = nvme_setup_io_queues(dev);
badc34d4 2631 if (result)
f58944e2 2632 goto out;
f0b50732 2633
2659e57b
CH		 2634 /*
2635 * Keep the controller around but remove all namespaces if we don't have
2636 * any working I/O queue.
2637 */
3cf519b5 2638 if (dev->online_queues < 2) {
1b3c47c1 2639 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2640 nvme_kill_queues(&dev->ctrl);
5bae7f73 2641 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2642 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2643 } else {
25646264 2644 nvme_start_queues(&dev->ctrl);
302ad8cc 2645 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2646 /* hit this only when allocate tagset fails */
2647 if (nvme_dev_add(dev))
2648 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2649 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2650 }
2651
2b1b7e78
JW		 2652 /*
2653 * If only admin queue live, keep it to do further investigation or
2654 * recovery.
2655 */
2656 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2657 dev_warn(dev->ctrl.device,
2658 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2659 goto out;
2660 }
92911a55 2661
d09f2b45 2662 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2663 return;
f0b50732 2664
3cf519b5 2665 out:
f58944e2 2666 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2667}
2668
5c8809e6 2669static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2670{
5c8809e6 2671 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2672 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2673
2674 if (pci_get_drvdata(pdev))
921920ab 2675 device_release_driver(&pdev->dev);
1673f1f0 2676 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2677}
2678
1c63dc66 2679static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2680{
1c63dc66 2681 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2682 return 0;
9ca97374
TH		 2683}
2684
5fd4ce1b 2685static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2686{
5fd4ce1b
CH		 2687 writel(val, to_nvme_dev(ctrl)->bar + off);
2688 return 0;
2689}
4cc06521 2690
7fd8930f
CH		 2691static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2692{
2693 *val = readq(to_nvme_dev(ctrl)->bar + off);
2694 return 0;
4cc06521
KB		 2695}
2696
97c12223
KB		 2697static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2698{
2699 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2700
2701 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2702}
2703
1c63dc66 2704static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2705 .name = "pcie",
e439bb12 2706 .module = THIS_MODULE,
e0596ab2
LG		 2707 .flags = NVME_F_METADATA_SUPPORTED |
2708 NVME_F_PCI_P2PDMA,
1c63dc66 2709 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2710 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2711 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2712 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2713 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2714 .get_address = nvme_pci_get_address,
1c63dc66 2715};
4cc06521 2716
b00a726a
KB		 2717static int nvme_dev_map(struct nvme_dev *dev)
2718{
b00a726a
KB		 2719 struct pci_dev *pdev = to_pci_dev(dev->dev);
2720
a1f447b3 2721 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2722 return -ENODEV;
2723
97f6ef64 2724 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2725 goto release;
2726
9fa196e7 2727 return 0;
b00a726a 2728 release:
9fa196e7
MG		 2729 pci_release_mem_regions(pdev);
2730 return -ENODEV;
b00a726a
KB		 2731}
2732
8427bbc2 2733static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2734{
2735 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2736 /*
2737 * Several Samsung devices seem to drop off the PCIe bus
2738 * randomly when APST is on and uses the deepest sleep state.
2739 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2740 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2741 * 950 PRO 256GB", but it seems to be restricted to two Dell
2742 * laptops.
2743 */
2744 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2745 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2746 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2747 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2748 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2749 /*
2750 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2751 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2752 * within few minutes after bootup on a Coffee Lake board -
2753 * ASUS PRIME Z370-A
8427bbc2
KHF		 2754 */
2755 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2756 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2757 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2758 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2759 }
2760
2761 return 0;
2762}
2763
18119775
KB		 2764static void nvme_async_probe(void *data, async_cookie_t cookie)
2765{
2766 struct nvme_dev *dev = data;
80f513b5 2767
18119775
KB		 2768 nvme_reset_ctrl_sync(&dev->ctrl);
2769 flush_work(&dev->ctrl.scan_work);
80f513b5 2770 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2771}
2772
8d85fce7 2773static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2774{
a4aea562 2775 int node, result = -ENOMEM;
b60503ba 2776 struct nvme_dev *dev;
ff5350a8 2777 unsigned long quirks = id->driver_data;
943e942e 2778 size_t alloc_size;
b60503ba 2779
a4aea562
MB		 2780 node = dev_to_node(&pdev->dev);
2781 if (node == NUMA_NO_NODE)
2fa84351 2782 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2783
2784 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2785 if (!dev)
2786 return -ENOMEM;
147b27e4 2787
3b6592f7
JA		 2788 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2789 GFP_KERNEL, node);
b60503ba
MW		 2790 if (!dev->queues)
2791 goto free;
2792
e75ec752 2793 dev->dev = get_device(&pdev->dev);
9a6b9458 2794 pci_set_drvdata(pdev, dev);
1c63dc66 2795
b00a726a
KB		 2796 result = nvme_dev_map(dev);
2797 if (result)
b00c9b7a 2798 goto put_pci;
b00a726a 2799
d86c4d8e 2800 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2801 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2802 mutex_init(&dev->shutdown_lock);
db3cbfff 2803 init_completion(&dev->ioq_wait);
b60503ba 2804
091b6092
MW		 2805 result = nvme_setup_prp_pools(dev);
2806 if (result)
b00c9b7a 2807 goto unmap;
4cc06521 2808
8427bbc2 2809 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2810
943e942e
JA		 2811 /*
2812 * Double check that our mempool alloc size will cover the biggest
2813 * command we support.
2814 */
2815 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2816 NVME_MAX_SEGS, true);
2817 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2818
2819 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2820 mempool_kfree,
2821 (void *) alloc_size,
2822 GFP_KERNEL, node);
2823 if (!dev->iod_mempool) {
2824 result = -ENOMEM;
2825 goto release_pools;
2826 }
2827
b6e44b4c
KB		 2828 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2829 quirks);
2830 if (result)
2831 goto release_mempool;
2832
1b3c47c1
SG		 2833 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2834
80f513b5 2835 nvme_get_ctrl(&dev->ctrl);
18119775 2836 async_schedule(nvme_async_probe, dev);
4caff8fc 2837
b60503ba
MW		 2838 return 0;
2839
b6e44b4c
KB		 2840 release_mempool:
2841 mempool_destroy(dev->iod_mempool);
0877cb0d 2842 release_pools:
091b6092 2843 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2844 unmap:
2845 nvme_dev_unmap(dev);
a96d4f5c 2846 put_pci:
e75ec752 2847 put_device(dev->dev);
b60503ba
MW		 2848 free:
2849 kfree(dev->queues);
b60503ba
MW		 2850 kfree(dev);
2851 return result;
2852}
2853
775755ed 2854static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2855{
a6739479 2856 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2857 nvme_dev_disable(dev, false);
775755ed 2858}
f0d54a54 2859
775755ed
CH		 2860static void nvme_reset_done(struct pci_dev *pdev)
2861{
f263fbb8 2862 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2863 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2864}
2865
09ece142
KB		 2866static void nvme_shutdown(struct pci_dev *pdev)
2867{
2868 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2869 nvme_dev_disable(dev, true);
09ece142
KB		 2870}
2871
f58944e2
KB		 2872/*
2873 * The driver's remove may be called on a device in a partially initialized
2874 * state. This function must not have any dependencies on the device state in
2875 * order to proceed.
2876 */
8d85fce7 2877static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2878{
2879 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2880
bb8d261e 2881 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2882 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2883
6db28eda 2884 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2885 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2886 nvme_dev_disable(dev, true);
cb4bfda6 2887 nvme_dev_remove_admin(dev);
6db28eda 2888 }
0ff9d4e1 2889
d86c4d8e 2890 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2891 nvme_stop_ctrl(&dev->ctrl);
2892 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2893 nvme_dev_disable(dev, true);
9fe5c59f 2894 nvme_release_cmb(dev);
87ad72a5 2895 nvme_free_host_mem(dev);
a4aea562 2896 nvme_dev_remove_admin(dev);
a1a5ef99 2897 nvme_free_queues(dev, 0);
d09f2b45 2898 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2899 nvme_release_prp_pools(dev);
b00a726a 2900 nvme_dev_unmap(dev);
1673f1f0 2901 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2902}
2903
671a6018 2904#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2905static int nvme_suspend(struct device *dev)
2906{
2907 struct pci_dev *pdev = to_pci_dev(dev);
2908 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2909
a5cdb68c 2910 nvme_dev_disable(ndev, true);
cd638946
KB		 2911 return 0;
2912}
2913
2914static int nvme_resume(struct device *dev)
2915{
2916 struct pci_dev *pdev = to_pci_dev(dev);
2917 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2918
d86c4d8e 2919 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2920 return 0;
cd638946 2921}
671a6018 2922#endif
cd638946
KB		 2923
2924static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2925
a0a3408e
KB		 2926static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2927 pci_channel_state_t state)
2928{
2929 struct nvme_dev *dev = pci_get_drvdata(pdev);
2930
2931 /*
2932 * A frozen channel requires a reset. When detected, this method will
2933 * shutdown the controller to quiesce. The controller will be restarted
2934 * after the slot reset through driver's slot_reset callback.
2935 */
a0a3408e
KB		 2936 switch (state) {
2937 case pci_channel_io_normal:
2938 return PCI_ERS_RESULT_CAN_RECOVER;
2939 case pci_channel_io_frozen:
d011fb31
KB		 2940 dev_warn(dev->ctrl.device,
2941 "frozen state error detected, reset controller\n");
a5cdb68c 2942 nvme_dev_disable(dev, false);
a0a3408e
KB		 2943 return PCI_ERS_RESULT_NEED_RESET;
2944 case pci_channel_io_perm_failure:
d011fb31
KB		 2945 dev_warn(dev->ctrl.device,
2946 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2947 return PCI_ERS_RESULT_DISCONNECT;
2948 }
2949 return PCI_ERS_RESULT_NEED_RESET;
2950}
2951
2952static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2953{
2954 struct nvme_dev *dev = pci_get_drvdata(pdev);
2955
1b3c47c1 2956 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2957 pci_restore_state(pdev);
d86c4d8e 2958 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2959 return PCI_ERS_RESULT_RECOVERED;
2960}
2961
2962static void nvme_error_resume(struct pci_dev *pdev)
2963{
72cd4cc2
KB		 2964 struct nvme_dev *dev = pci_get_drvdata(pdev);
2965
2966 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2967}
2968
1d352035 2969static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2970 .error_detected = nvme_error_detected,
b60503ba
MW		 2971 .slot_reset = nvme_slot_reset,
2972 .resume = nvme_error_resume,
775755ed
CH		 2973 .reset_prepare = nvme_reset_prepare,
2974 .reset_done = nvme_reset_done,
b60503ba
MW		 2975};
2976
6eb0d698 2977static const struct pci_device_id nvme_id_table[] = {
106198ed 2978 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2979 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2980 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2981 { PCI_VDEVICE(INTEL, 0x0a53),
2982 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2983 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2984 { PCI_VDEVICE(INTEL, 0x0a54),
2985 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2986 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2987 { PCI_VDEVICE(INTEL, 0x0a55),
2988 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2989 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2990 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2991 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2992 NVME_QUIRK_MEDIUM_PRIO_SQ },
540c801c
KB		 2993 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2994 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2995 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2996 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2997 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2998 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2999 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3000 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3001 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3002 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3003 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3004 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3005 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3006 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3007 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3008 .driver_data = NVME_QUIRK_LIGHTNVM, },
3009 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3010 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3011 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3012 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 3013 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 3014 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 3015 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 3016 { 0, }
3017};
3018MODULE_DEVICE_TABLE(pci, nvme_id_table);
3019
3020static struct pci_driver nvme_driver = {
3021 .name = "nvme",
3022 .id_table = nvme_id_table,
3023 .probe = nvme_probe,
8d85fce7 3024 .remove = nvme_remove,
09ece142 3025 .shutdown = nvme_shutdown,
cd638946
KB		 3026 .driver = {
3027 .pm = &nvme_dev_pm_ops,
3028 },
74d986ab 3029 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3030 .err_handler = &nvme_err_handler,
3031};
3032
3033static int __init nvme_init(void)
3034{
9a6327d2 3035 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3036}
3037
3038static void __exit nvme_exit(void)
3039{
3040 pci_unregister_driver(&nvme_driver);
03e0f3a6 3041 flush_workqueue(nvme_wq);
21bd78bc 3042 _nvme_check_size();
b60503ba
MW		 3043}
3044
3045MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3046MODULE_LICENSE("GPL");
c78b4713 3047MODULE_VERSION("1.0");
b60503ba
MW		 3048module_init(nvme_init);
3049module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)