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nvme-lightnvm: convert to SPDX identifiers
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
0f238ff5 33#include <linux/pci-p2pdma.h>
797a796a 34
604c01d5 35#include "trace.h"
f11bb3e2
CH		 36#include "nvme.h"
37
b60503ba
MW		 38#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
39#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 40
a7a7cbe3 41#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 42
943e942e
JA		 43/*
44 * These can be higher, but we need to ensure that any command doesn't
45 * require an sg allocation that needs more than a page of data.
46 */
47#define NVME_MAX_KB_SZ 4096
48#define NVME_MAX_SEGS 127
49
58ffacb5
MW		 50static int use_threaded_interrupts;
51module_param(use_threaded_interrupts, int, 0);
52
8ffaadf7 53static bool use_cmb_sqes = true;
69f4eb9f 54module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 55MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
56
87ad72a5
CH		 57static unsigned int max_host_mem_size_mb = 128;
58module_param(max_host_mem_size_mb, uint, 0444);
59MODULE_PARM_DESC(max_host_mem_size_mb,
60 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 61
a7a7cbe3
CK		 62static unsigned int sgl_threshold = SZ_32K;
63module_param(sgl_threshold, uint, 0644);
64MODULE_PARM_DESC(sgl_threshold,
65 "Use SGLs when average request segment size is larger or equal to "
66 "this size. Use 0 to disable SGLs.");
67
b27c1e68 68static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
71 .get = param_get_int,
72};
73
74static int io_queue_depth = 1024;
75module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
77
3b6592f7
JA		 78static int queue_count_set(const char *val, const struct kernel_param *kp);
79static const struct kernel_param_ops queue_count_ops = {
80 .set = queue_count_set,
81 .get = param_get_int,
82};
83
84static int write_queues;
85module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
86MODULE_PARM_DESC(write_queues,
87 "Number of queues to use for writes. If not set, reads and writes "
88 "will share a queue set.");
89
a4668d9b 90static int poll_queues = 0;
4b04cc6a
JA		 91module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
92MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
93
1c63dc66
CH		 94struct nvme_dev;
95struct nvme_queue;
b3fffdef 96
a5cdb68c 97static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 98static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 99
1c63dc66
CH		 100/*
101 * Represents an NVM Express device. Each nvme_dev is a PCI function.
102 */
103struct nvme_dev {
147b27e4 104 struct nvme_queue *queues;
1c63dc66
CH		 105 struct blk_mq_tag_set tagset;
106 struct blk_mq_tag_set admin_tagset;
107 u32 __iomem *dbs;
108 struct device *dev;
109 struct dma_pool *prp_page_pool;
110 struct dma_pool *prp_small_pool;
1c63dc66
CH		 111 unsigned online_queues;
112 unsigned max_qid;
e20ba6e1 113 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 114 unsigned int num_vecs;
1c63dc66
CH		 115 int q_depth;
116 u32 db_stride;
1c63dc66 117 void __iomem *bar;
97f6ef64 118 unsigned long bar_mapped_size;
5c8809e6 119 struct work_struct remove_work;
77bf25ea 120 struct mutex shutdown_lock;
1c63dc66 121 bool subsystem;
1c63dc66 122 u64 cmb_size;
0f238ff5 123 bool cmb_use_sqes;
1c63dc66 124 u32 cmbsz;
202021c1 125 u32 cmbloc;
1c63dc66 126 struct nvme_ctrl ctrl;
87ad72a5 127
943e942e
JA		 128 mempool_t *iod_mempool;
129
87ad72a5 130 /* shadow doorbell buffer support: */
f9f38e33
HK		 131 u32 *dbbuf_dbs;
132 dma_addr_t dbbuf_dbs_dma_addr;
133 u32 *dbbuf_eis;
134 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 135
136 /* host memory buffer support: */
137 u64 host_mem_size;
138 u32 nr_host_mem_descs;
4033f35d 139 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 140 struct nvme_host_mem_buf_desc *host_mem_descs;
141 void **host_mem_desc_bufs;
4d115420 142};
1fa6aead 143
b27c1e68 144static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
145{
146 int n = 0, ret;
147
148 ret = kstrtoint(val, 10, &n);
149 if (ret != 0 || n < 2)
150 return -EINVAL;
151
152 return param_set_int(val, kp);
153}
154
3b6592f7
JA		 155static int queue_count_set(const char *val, const struct kernel_param *kp)
156{
157 int n = 0, ret;
158
159 ret = kstrtoint(val, 10, &n);
e895fedf
BVA		 160 if (ret)
161 return ret;
3b6592f7
JA		 162 if (n > num_possible_cpus())
163 n = num_possible_cpus();
164
165 return param_set_int(val, kp);
166}
167
f9f38e33
HK		 168static inline unsigned int sq_idx(unsigned int qid, u32 stride)
169{
170 return qid * 2 * stride;
171}
172
173static inline unsigned int cq_idx(unsigned int qid, u32 stride)
174{
175 return (qid * 2 + 1) * stride;
176}
177
1c63dc66
CH		 178static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
179{
180 return container_of(ctrl, struct nvme_dev, ctrl);
181}
182
b60503ba
MW		 183/*
184 * An NVM Express queue. Each device has at least two (one for admin
185 * commands and one for I/O commands).
186 */
187struct nvme_queue {
188 struct device *q_dmadev;
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
b60503ba 191 struct nvme_command *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
b60503ba 194 volatile struct nvme_completion *cqes;
42483228 195 struct blk_mq_tags **tags;
b60503ba
MW		 196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
b60503ba
MW		 198 u32 __iomem *q_db;
199 u16 q_depth;
6222d172 200 s16 cq_vector;
b60503ba 201 u16 sq_tail;
04f3eafd 202 u16 last_sq_tail;
b60503ba 203 u16 cq_head;
68fa9dbe 204 u16 last_cq_head;
c30341dc 205 u16 qid;
e9539f47 206 u8 cq_phase;
4e224106
CH		 207 unsigned long flags;
208#define NVMEQ_ENABLED 0
63223078 209#define NVMEQ_SQ_CMB 1
d1ed6aa1 210#define NVMEQ_DELETE_ERROR 2
f9f38e33
HK		 211 u32 *dbbuf_sq_db;
212 u32 *dbbuf_cq_db;
213 u32 *dbbuf_sq_ei;
214 u32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c
CH		 218/*
219 * The nvme_iod describes the data in an I/O, including the list of PRP
220 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 221 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 222 * allocated to store the PRP list.
223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
f4800d6d 226 struct nvme_queue *nvmeq;
a7a7cbe3 227 bool use_sgl;
f4800d6d 228 int aborted;
71bd150c 229 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 230 int nents; /* Used in scatterlist */
231 int length; /* Of data, in bytes */
232 dma_addr_t first_dma;
bf684057 233 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 234 struct scatterlist *sg;
235 struct scatterlist inline_sg[0];
b60503ba
MW		 236};
237
238/*
239 * Check we didin't inadvertently grow the command struct
240 */
241static inline void _nvme_check_size(void)
242{
243 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
244 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
245 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
246 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
247 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 248 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 249 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 250 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 251 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
252 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 253 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 254 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 255 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
256}
257
3b6592f7
JA		 258static unsigned int max_io_queues(void)
259{
4b04cc6a 260 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 261}
262
263static unsigned int max_queue_count(void)
264{
265 /* IO queues + admin queue */
266 return 1 + max_io_queues();
267}
268
f9f38e33
HK		 269static inline unsigned int nvme_dbbuf_size(u32 stride)
270{
3b6592f7 271 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 272}
273
274static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
275{
276 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
277
278 if (dev->dbbuf_dbs)
279 return 0;
280
281 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
282 &dev->dbbuf_dbs_dma_addr,
283 GFP_KERNEL);
284 if (!dev->dbbuf_dbs)
285 return -ENOMEM;
286 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
287 &dev->dbbuf_eis_dma_addr,
288 GFP_KERNEL);
289 if (!dev->dbbuf_eis) {
290 dma_free_coherent(dev->dev, mem_size,
291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
292 dev->dbbuf_dbs = NULL;
293 return -ENOMEM;
294 }
295
296 return 0;
297}
298
299static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
300{
301 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
302
303 if (dev->dbbuf_dbs) {
304 dma_free_coherent(dev->dev, mem_size,
305 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
306 dev->dbbuf_dbs = NULL;
307 }
308 if (dev->dbbuf_eis) {
309 dma_free_coherent(dev->dev, mem_size,
310 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
311 dev->dbbuf_eis = NULL;
312 }
313}
314
315static void nvme_dbbuf_init(struct nvme_dev *dev,
316 struct nvme_queue *nvmeq, int qid)
317{
318 if (!dev->dbbuf_dbs || !qid)
319 return;
320
321 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
322 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
323 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
324 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
325}
326
327static void nvme_dbbuf_set(struct nvme_dev *dev)
328{
329 struct nvme_command c;
330
331 if (!dev->dbbuf_dbs)
332 return;
333
334 memset(&c, 0, sizeof(c));
335 c.dbbuf.opcode = nvme_admin_dbbuf;
336 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
337 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
338
339 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 340 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 341 /* Free memory and continue on */
342 nvme_dbbuf_dma_free(dev);
343 }
344}
345
346static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347{
348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349}
350
351/* Update dbbuf and return true if an MMIO is required */
352static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
353 volatile u32 *dbbuf_ei)
354{
355 if (dbbuf_db) {
356 u16 old_value;
357
358 /*
359 * Ensure that the queue is written before updating
360 * the doorbell in memory
361 */
362 wmb();
363
364 old_value = *dbbuf_db;
365 *dbbuf_db = value;
366
f1ed3df2
MW		 367 /*
368 * Ensure that the doorbell is updated before reading the event
369 * index from memory. The controller needs to provide similar
370 * ordering to ensure the envent index is updated before reading
371 * the doorbell.
372 */
373 mb();
374
f9f38e33
HK		 375 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
376 return false;
377 }
378
379 return true;
b60503ba
MW		 380}
381
ac3dd5bd
JA		 382/*
383 * Max size of iod being embedded in the request payload
384 */
385#define NVME_INT_PAGES 2
5fd4ce1b 386#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 387
388/*
389 * Will slightly overestimate the number of pages needed. This is OK
390 * as it only leads to a small amount of wasted memory for the lifetime of
391 * the I/O.
392 */
393static int nvme_npages(unsigned size, struct nvme_dev *dev)
394{
5fd4ce1b
CH		 395 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
396 dev->ctrl.page_size);
ac3dd5bd
JA		 397 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
398}
399
a7a7cbe3
CK		 400/*
401 * Calculates the number of pages needed for the SGL segments. For example a 4k
402 * page can accommodate 256 SGL descriptors.
403 */
404static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 405{
a7a7cbe3 406 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 407}
ac3dd5bd 408
a7a7cbe3
CK		 409static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
410 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 411{
a7a7cbe3
CK		 412 size_t alloc_size;
413
414 if (use_sgl)
415 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
416 else
417 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
418
419 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 420}
ac3dd5bd 421
a7a7cbe3 422static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 423{
a7a7cbe3
CK		 424 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
425 NVME_INT_BYTES(dev), NVME_INT_PAGES,
426 use_sgl);
427
428 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 429}
430
a4aea562
MB		 431static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
432 unsigned int hctx_idx)
e85248e5 433{
a4aea562 434 struct nvme_dev *dev = data;
147b27e4 435 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 436
42483228
KB		 437 WARN_ON(hctx_idx != 0);
438 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
439 WARN_ON(nvmeq->tags);
440
a4aea562 441 hctx->driver_data = nvmeq;
42483228 442 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 443 return 0;
e85248e5
MW		 444}
445
4af0e21c
KB		 446static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
447{
448 struct nvme_queue *nvmeq = hctx->driver_data;
449
450 nvmeq->tags = NULL;
451}
452
a4aea562
MB		 453static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
454 unsigned int hctx_idx)
b60503ba 455{
a4aea562 456 struct nvme_dev *dev = data;
147b27e4 457 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 458
42483228
KB		 459 if (!nvmeq->tags)
460 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 461
42483228 462 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 463 hctx->driver_data = nvmeq;
464 return 0;
b60503ba
MW		 465}
466
d6296d39
CH		 467static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
468 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 469{
d6296d39 470 struct nvme_dev *dev = set->driver_data;
f4800d6d 471 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 472 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 473 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 474
475 BUG_ON(!nvmeq);
f4800d6d 476 iod->nvmeq = nvmeq;
59e29ce6
SG		 477
478 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 479 return 0;
480}
481
3b6592f7
JA		 482static int queue_irq_offset(struct nvme_dev *dev)
483{
484 /* if we have more than 1 vec, admin queue offsets us by 1 */
485 if (dev->num_vecs > 1)
486 return 1;
487
488 return 0;
489}
490
dca51e78
CH		 491static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
492{
493 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 494 int i, qoff, offset;
495
496 offset = queue_irq_offset(dev);
497 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
498 struct blk_mq_queue_map *map = &set->map[i];
499
500 map->nr_queues = dev->io_queues[i];
501 if (!map->nr_queues) {
e20ba6e1 502 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 503 continue;
3b6592f7
JA		 504 }
505
4b04cc6a
JA		 506 /*
507 * The poll queue(s) doesn't have an IRQ (and hence IRQ
508 * affinity), so use the regular blk-mq cpu mapping
509 */
3b6592f7 510 map->queue_offset = qoff;
e20ba6e1 511 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 512 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
513 else
514 blk_mq_map_queues(map);
3b6592f7
JA		 515 qoff += map->nr_queues;
516 offset += map->nr_queues;
517 }
518
519 return 0;
dca51e78
CH		 520}
521
04f3eafd
JA		 522/*
523 * Write sq tail if we are asked to, or if the next command would wrap.
524 */
525static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
526{
527 if (!write_sq) {
528 u16 next_tail = nvmeq->sq_tail + 1;
529
530 if (next_tail == nvmeq->q_depth)
531 next_tail = 0;
532 if (next_tail != nvmeq->last_sq_tail)
533 return;
534 }
535
536 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
537 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
538 writel(nvmeq->sq_tail, nvmeq->q_db);
539 nvmeq->last_sq_tail = nvmeq->sq_tail;
540}
541
b60503ba 542/**
90ea5ca4 543 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 544 * @nvmeq: The queue to use
545 * @cmd: The command to send
04f3eafd 546 * @write_sq: whether to write to the SQ doorbell
b60503ba 547 */
04f3eafd
JA		 548static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
549 bool write_sq)
b60503ba 550{
90ea5ca4 551 spin_lock(&nvmeq->sq_lock);
0f238ff5 552 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 553 if (++nvmeq->sq_tail == nvmeq->q_depth)
554 nvmeq->sq_tail = 0;
04f3eafd
JA		 555 nvme_write_sq_db(nvmeq, write_sq);
556 spin_unlock(&nvmeq->sq_lock);
557}
558
559static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
560{
561 struct nvme_queue *nvmeq = hctx->driver_data;
562
563 spin_lock(&nvmeq->sq_lock);
564 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
565 nvme_write_sq_db(nvmeq, true);
90ea5ca4 566 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 567}
568
a7a7cbe3 569static void **nvme_pci_iod_list(struct request *req)
b60503ba 570{
f4800d6d 571 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 572 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 573}
574
955b1b5a
MI		 575static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
576{
577 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 578 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 579 unsigned int avg_seg_size;
580
20469a37
KB		 581 if (nseg == 0)
582 return false;
583
584 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 585
586 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
587 return false;
588 if (!iod->nvmeq->qid)
589 return false;
590 if (!sgl_threshold || avg_seg_size < sgl_threshold)
591 return false;
592 return true;
593}
594
fc17b653 595static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 596{
f4800d6d 597 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 598 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 599 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 600
955b1b5a
MI		 601 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
602
f4800d6d 603 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
943e942e 604 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
f4800d6d 605 if (!iod->sg)
fc17b653 606 return BLK_STS_RESOURCE;
f4800d6d
CH		 607 } else {
608 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 609 }
610
f4800d6d
CH		 611 iod->aborted = 0;
612 iod->npages = -1;
613 iod->nents = 0;
614 iod->length = size;
f80ec966 615
fc17b653 616 return BLK_STS_OK;
ac3dd5bd
JA		 617}
618
f4800d6d 619static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 620{
f4800d6d 621 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 622 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
623 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
624
eca18b23 625 int i;
eca18b23
MW		 626
627 if (iod->npages == 0)
a7a7cbe3
CK		 628 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
629 dma_addr);
630
eca18b23 631 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 632 void *addr = nvme_pci_iod_list(req)[i];
633
634 if (iod->use_sgl) {
635 struct nvme_sgl_desc *sg_list = addr;
636
637 next_dma_addr =
638 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
639 } else {
640 __le64 *prp_list = addr;
641
642 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
643 }
644
645 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
646 dma_addr = next_dma_addr;
eca18b23 647 }
ac3dd5bd 648
f4800d6d 649 if (iod->sg != iod->inline_sg)
943e942e 650 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 651}
652
d0877473
KB		 653static void nvme_print_sgl(struct scatterlist *sgl, int nents)
654{
655 int i;
656 struct scatterlist *sg;
657
658 for_each_sg(sgl, sg, nents, i) {
659 dma_addr_t phys = sg_phys(sg);
660 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
661 "dma_address:%pad dma_length:%d\n",
662 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
663 sg_dma_len(sg));
664 }
665}
666
a7a7cbe3
CK		 667static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
668 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 669{
f4800d6d 670 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 671 struct dma_pool *pool;
b131c61d 672 int length = blk_rq_payload_bytes(req);
eca18b23 673 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 674 int dma_len = sg_dma_len(sg);
675 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 676 u32 page_size = dev->ctrl.page_size;
f137e0f1 677 int offset = dma_addr & (page_size - 1);
e025344c 678 __le64 *prp_list;
a7a7cbe3 679 void **list = nvme_pci_iod_list(req);
e025344c 680 dma_addr_t prp_dma;
eca18b23 681 int nprps, i;
ff22b54f 682
1d090624 683 length -= (page_size - offset);
5228b328
JS		 684 if (length <= 0) {
685 iod->first_dma = 0;
a7a7cbe3 686 goto done;
5228b328 687 }
ff22b54f 688
1d090624 689 dma_len -= (page_size - offset);
ff22b54f 690 if (dma_len) {
1d090624 691 dma_addr += (page_size - offset);
ff22b54f
MW		 692 } else {
693 sg = sg_next(sg);
694 dma_addr = sg_dma_address(sg);
695 dma_len = sg_dma_len(sg);
696 }
697
1d090624 698 if (length <= page_size) {
edd10d33 699 iod->first_dma = dma_addr;
a7a7cbe3 700 goto done;
e025344c
SMM		 701 }
702
1d090624 703 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 704 if (nprps <= (256 / 8)) {
705 pool = dev->prp_small_pool;
eca18b23 706 iod->npages = 0;
99802a7a
MW		 707 } else {
708 pool = dev->prp_page_pool;
eca18b23 709 iod->npages = 1;
99802a7a
MW		 710 }
711
69d2b571 712 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 713 if (!prp_list) {
edd10d33 714 iod->first_dma = dma_addr;
eca18b23 715 iod->npages = -1;
86eea289 716 return BLK_STS_RESOURCE;
b77954cb 717 }
eca18b23
MW		 718 list[0] = prp_list;
719 iod->first_dma = prp_dma;
e025344c
SMM		 720 i = 0;
721 for (;;) {
1d090624 722 if (i == page_size >> 3) {
e025344c 723 __le64 *old_prp_list = prp_list;
69d2b571 724 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 725 if (!prp_list)
86eea289 726 return BLK_STS_RESOURCE;
eca18b23 727 list[iod->npages++] = prp_list;
7523d834
MW		 728 prp_list[0] = old_prp_list[i - 1];
729 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
730 i = 1;
e025344c
SMM		 731 }
732 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 733 dma_len -= page_size;
734 dma_addr += page_size;
735 length -= page_size;
e025344c
SMM		 736 if (length <= 0)
737 break;
738 if (dma_len > 0)
739 continue;
86eea289
KB		 740 if (unlikely(dma_len < 0))
741 goto bad_sgl;
e025344c
SMM		 742 sg = sg_next(sg);
743 dma_addr = sg_dma_address(sg);
744 dma_len = sg_dma_len(sg);
ff22b54f
MW		 745 }
746
a7a7cbe3
CK		 747done:
748 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
749 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
750
86eea289
KB		 751 return BLK_STS_OK;
752
753 bad_sgl:
d0877473
KB		 754 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
755 "Invalid SGL for payload:%d nents:%d\n",
756 blk_rq_payload_bytes(req), iod->nents);
86eea289 757 return BLK_STS_IOERR;
ff22b54f
MW		 758}
759
a7a7cbe3
CK		 760static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
761 struct scatterlist *sg)
762{
763 sge->addr = cpu_to_le64(sg_dma_address(sg));
764 sge->length = cpu_to_le32(sg_dma_len(sg));
765 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
766}
767
768static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
769 dma_addr_t dma_addr, int entries)
770{
771 sge->addr = cpu_to_le64(dma_addr);
772 if (entries < SGES_PER_PAGE) {
773 sge->length = cpu_to_le32(entries * sizeof(*sge));
774 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
775 } else {
776 sge->length = cpu_to_le32(PAGE_SIZE);
777 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
778 }
779}
780
781static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 782 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 783{
784 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 785 struct dma_pool *pool;
786 struct nvme_sgl_desc *sg_list;
787 struct scatterlist *sg = iod->sg;
a7a7cbe3 788 dma_addr_t sgl_dma;
b0f2853b 789 int i = 0;
a7a7cbe3 790
a7a7cbe3
CK		 791 /* setting the transfer type as SGL */
792 cmd->flags = NVME_CMD_SGL_METABUF;
793
b0f2853b 794 if (entries == 1) {
a7a7cbe3
CK		 795 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
796 return BLK_STS_OK;
797 }
798
799 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
800 pool = dev->prp_small_pool;
801 iod->npages = 0;
802 } else {
803 pool = dev->prp_page_pool;
804 iod->npages = 1;
805 }
806
807 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
808 if (!sg_list) {
809 iod->npages = -1;
810 return BLK_STS_RESOURCE;
811 }
812
813 nvme_pci_iod_list(req)[0] = sg_list;
814 iod->first_dma = sgl_dma;
815
816 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
817
818 do {
819 if (i == SGES_PER_PAGE) {
820 struct nvme_sgl_desc *old_sg_desc = sg_list;
821 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
822
823 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
824 if (!sg_list)
825 return BLK_STS_RESOURCE;
826
827 i = 0;
828 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
829 sg_list[i++] = *link;
830 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
831 }
832
833 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 834 sg = sg_next(sg);
b0f2853b 835 } while (--entries > 0);
a7a7cbe3 836
a7a7cbe3
CK		 837 return BLK_STS_OK;
838}
839
fc17b653 840static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 841 struct nvme_command *cmnd)
d29ec824 842{
f4800d6d 843 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 844 struct request_queue *q = req->q;
845 enum dma_data_direction dma_dir = rq_data_dir(req) ?
846 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 847 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 848 int nr_mapped;
d29ec824 849
f9d03f96 850 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 851 iod->nents = blk_rq_map_sg(q, req, iod->sg);
852 if (!iod->nents)
853 goto out;
d29ec824 854
fc17b653 855 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 856
857 if (is_pci_p2pdma_page(sg_page(iod->sg)))
858 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
859 dma_dir);
860 else
861 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
862 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 863 if (!nr_mapped)
ba1ca37e 864 goto out;
d29ec824 865
955b1b5a 866 if (iod->use_sgl)
b0f2853b 867 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 868 else
869 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
870
86eea289 871 if (ret != BLK_STS_OK)
ba1ca37e 872 goto out_unmap;
0e5e4f0e 873
fc17b653 874 ret = BLK_STS_IOERR;
ba1ca37e
CH		 875 if (blk_integrity_rq(req)) {
876 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
877 goto out_unmap;
0e5e4f0e 878
bf684057
CH		 879 sg_init_table(&iod->meta_sg, 1);
880 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 881 goto out_unmap;
0e5e4f0e 882
bf684057 883 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 884 goto out_unmap;
00df5cb4 885
bf684057 886 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK		 887 }
888
fc17b653 889 return BLK_STS_OK;
00df5cb4 890
ba1ca37e
CH		 891out_unmap:
892 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
893out:
894 return ret;
00df5cb4
MW		 895}
896
f4800d6d 897static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 898{
f4800d6d 899 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 900 enum dma_data_direction dma_dir = rq_data_dir(req) ?
901 DMA_TO_DEVICE : DMA_FROM_DEVICE;
902
903 if (iod->nents) {
e0596ab2
LG		 904 /* P2PDMA requests do not need to be unmapped */
905 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
906 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
907
f7f1fc36 908 if (blk_integrity_rq(req))
bf684057 909 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e19b127f 910 }
e1e5e564 911
f9d03f96 912 nvme_cleanup_cmd(req);
f4800d6d 913 nvme_free_iod(dev, req);
d4f6c3ab 914}
b60503ba 915
d29ec824
CH		 916/*
917 * NOTE: ns is NULL when called on the admin queue.
918 */
fc17b653 919static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 920 const struct blk_mq_queue_data *bd)
edd10d33 921{
a4aea562
MB		 922 struct nvme_ns *ns = hctx->queue->queuedata;
923 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 924 struct nvme_dev *dev = nvmeq->dev;
a4aea562 925 struct request *req = bd->rq;
ba1ca37e 926 struct nvme_command cmnd;
ebe6d874 927 blk_status_t ret;
e1e5e564 928
d1f06f4a
JA		 929 /*
930 * We should not need to do this, but we're still using this to
931 * ensure we can drain requests on a dying queue.
932 */
4e224106 933 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 934 return BLK_STS_IOERR;
935
f9d03f96 936 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 937 if (ret)
f4800d6d 938 return ret;
a4aea562 939
b131c61d 940 ret = nvme_init_iod(req, dev);
fc17b653 941 if (ret)
f9d03f96 942 goto out_free_cmd;
a4aea562 943
fc17b653 944 if (blk_rq_nr_phys_segments(req)) {
b131c61d 945 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 946 if (ret)
947 goto out_cleanup_iod;
948 }
a4aea562 949
aae239e1 950 blk_mq_start_request(req);
04f3eafd 951 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 952 return BLK_STS_OK;
f9d03f96 953out_cleanup_iod:
f4800d6d 954 nvme_free_iod(dev, req);
f9d03f96
CH		 955out_free_cmd:
956 nvme_cleanup_cmd(req);
ba1ca37e 957 return ret;
b60503ba 958}
e1e5e564 959
77f02a7a 960static void nvme_pci_complete_rq(struct request *req)
eee417b0 961{
f4800d6d 962 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 963
77f02a7a
CH		 964 nvme_unmap_data(iod->nvmeq->dev, req);
965 nvme_complete_rq(req);
b60503ba
MW		 966}
967
d783e0bd 968/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 969static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 970{
750dde44
CH		 971 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
972 nvmeq->cq_phase;
d783e0bd
MR		 973}
974
eb281c82 975static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 976{
eb281c82 977 u16 head = nvmeq->cq_head;
adf68f21 978
397c699f
KB		 979 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
980 nvmeq->dbbuf_cq_ei))
981 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 982}
aae239e1 983
5cb525c8 984static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 985{
5cb525c8 986 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 987 struct request *req;
adf68f21 988
83a12fb7
SG		 989 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
990 dev_warn(nvmeq->dev->ctrl.device,
991 "invalid id %d completed on queue %d\n",
992 cqe->command_id, le16_to_cpu(cqe->sq_id));
993 return;
b60503ba
MW		 994 }
995
83a12fb7
SG		 996 /*
997 * AEN requests are special as they don't time out and can
998 * survive any kind of queue freeze and often don't respond to
999 * aborts. We don't even bother to allocate a struct request
1000 * for them but rather special case them here.
1001 */
1002 if (unlikely(nvmeq->qid == 0 &&
38dabe21 1003 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 1004 nvme_complete_async_event(&nvmeq->dev->ctrl,
1005 cqe->status, &cqe->result);
a0fa9647 1006 return;
83a12fb7 1007 }
b60503ba 1008
83a12fb7 1009 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
604c01d5 1010 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
83a12fb7
SG		 1011 nvme_end_request(req, cqe->status, cqe->result);
1012}
b60503ba 1013
5cb525c8 1014static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1015{
5cb525c8
JA		 1016 while (start != end) {
1017 nvme_handle_cqe(nvmeq, start);
1018 if (++start == nvmeq->q_depth)
1019 start = 0;
1020 }
1021}
adf68f21 1022
5cb525c8
JA		 1023static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1024{
dcca1662 1025 if (nvmeq->cq_head == nvmeq->q_depth - 1) {
5cb525c8
JA		 1026 nvmeq->cq_head = 0;
1027 nvmeq->cq_phase = !nvmeq->cq_phase;
dcca1662
HY		 1028 } else {
1029 nvmeq->cq_head++;
b60503ba 1030 }
a0fa9647
JA		 1031}
1032
1052b8ac
JA		 1033static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1034 u16 *end, unsigned int tag)
a0fa9647 1035{
1052b8ac 1036 int found = 0;
b60503ba 1037
5cb525c8 1038 *start = nvmeq->cq_head;
1052b8ac
JA		 1039 while (nvme_cqe_pending(nvmeq)) {
1040 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1041 found++;
5cb525c8 1042 nvme_update_cq_head(nvmeq);
920d13a8 1043 }
5cb525c8 1044 *end = nvmeq->cq_head;
eb281c82 1045
5cb525c8 1046 if (*start != *end)
920d13a8 1047 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1048 return found;
b60503ba
MW		 1049}
1050
1051static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1052{
58ffacb5 1053 struct nvme_queue *nvmeq = data;
68fa9dbe 1054 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1055 u16 start, end;
1056
3a7afd8e
CH		 1057 /*
1058 * The rmb/wmb pair ensures we see all updates from a previous run of
1059 * the irq handler, even if that was on another CPU.
1060 */
1061 rmb();
68fa9dbe
JA		 1062 if (nvmeq->cq_head != nvmeq->last_cq_head)
1063 ret = IRQ_HANDLED;
5cb525c8 1064 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1065 nvmeq->last_cq_head = nvmeq->cq_head;
3a7afd8e 1066 wmb();
5cb525c8 1067
68fa9dbe
JA		 1068 if (start != end) {
1069 nvme_complete_cqes(nvmeq, start, end);
1070 return IRQ_HANDLED;
1071 }
1072
1073 return ret;
58ffacb5
MW		 1074}
1075
1076static irqreturn_t nvme_irq_check(int irq, void *data)
1077{
1078 struct nvme_queue *nvmeq = data;
750dde44 1079 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1080 return IRQ_WAKE_THREAD;
1081 return IRQ_NONE;
58ffacb5
MW		 1082}
1083
0b2a8a9f
CH		 1084/*
1085 * Poll for completions any queue, including those not dedicated to polling.
1086 * Can be called from any context.
1087 */
1088static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1089{
3a7afd8e 1090 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
5cb525c8 1091 u16 start, end;
1052b8ac 1092 int found;
a0fa9647 1093
3a7afd8e
CH		 1094 /*
1095 * For a poll queue we need to protect against the polling thread
1096 * using the CQ lock. For normal interrupt driven threads we have
1097 * to disable the interrupt to avoid racing with it.
1098 */
91a509f8 1099 if (nvmeq->cq_vector == -1) {
3a7afd8e 1100 spin_lock(&nvmeq->cq_poll_lock);
91a509f8 1101 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1102 spin_unlock(&nvmeq->cq_poll_lock);
91a509f8
CH		 1103 } else {
1104 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1105 found = nvme_process_cq(nvmeq, &start, &end, tag);
3a7afd8e 1106 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
91a509f8 1107 }
442e19b7 1108
5cb525c8 1109 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1110 return found;
a0fa9647
JA		 1111}
1112
9743139c 1113static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1114{
1115 struct nvme_queue *nvmeq = hctx->driver_data;
1116 u16 start, end;
1117 bool found;
1118
1119 if (!nvme_cqe_pending(nvmeq))
1120 return 0;
1121
3a7afd8e 1122 spin_lock(&nvmeq->cq_poll_lock);
9743139c 1123 found = nvme_process_cq(nvmeq, &start, &end, -1);
3a7afd8e 1124 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab
JA		 1125
1126 nvme_complete_cqes(nvmeq, start, end);
1127 return found;
1128}
1129
ad22c355 1130static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1131{
f866fc42 1132 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1133 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1134 struct nvme_command c;
b60503ba 1135
a4aea562
MB		 1136 memset(&c, 0, sizeof(c));
1137 c.common.opcode = nvme_admin_async_event;
ad22c355 1138 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1139 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1140}
1141
b60503ba 1142static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1143{
b60503ba
MW		 1144 struct nvme_command c;
1145
1146 memset(&c, 0, sizeof(c));
1147 c.delete_queue.opcode = opcode;
1148 c.delete_queue.qid = cpu_to_le16(id);
1149
1c63dc66 1150 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1151}
1152
b60503ba 1153static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1154 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1155{
b60503ba 1156 struct nvme_command c;
4b04cc6a
JA		 1157 int flags = NVME_QUEUE_PHYS_CONTIG;
1158
1159 if (vector != -1)
1160 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1161
d29ec824 1162 /*
16772ae6 1163 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1164 * is attached to the request.
1165 */
b60503ba
MW		 1166 memset(&c, 0, sizeof(c));
1167 c.create_cq.opcode = nvme_admin_create_cq;
1168 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1169 c.create_cq.cqid = cpu_to_le16(qid);
1170 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1171 c.create_cq.cq_flags = cpu_to_le16(flags);
4b04cc6a
JA		 1172 if (vector != -1)
1173 c.create_cq.irq_vector = cpu_to_le16(vector);
1174 else
1175 c.create_cq.irq_vector = 0;
b60503ba 1176
1c63dc66 1177 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1178}
1179
1180static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1181 struct nvme_queue *nvmeq)
1182{
9abd68ef 1183 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1184 struct nvme_command c;
81c1cd98 1185 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1186
9abd68ef
JA		 1187 /*
1188 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1189 * set. Since URGENT priority is zeroes, it makes all queues
1190 * URGENT.
1191 */
1192 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1193 flags |= NVME_SQ_PRIO_MEDIUM;
1194
d29ec824 1195 /*
16772ae6 1196 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1197 * is attached to the request.
1198 */
b60503ba
MW		 1199 memset(&c, 0, sizeof(c));
1200 c.create_sq.opcode = nvme_admin_create_sq;
1201 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1202 c.create_sq.sqid = cpu_to_le16(qid);
1203 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1204 c.create_sq.sq_flags = cpu_to_le16(flags);
1205 c.create_sq.cqid = cpu_to_le16(qid);
1206
1c63dc66 1207 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1208}
1209
1210static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1211{
1212 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1213}
1214
1215static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1216{
1217 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1218}
1219
2a842aca 1220static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1221{
f4800d6d
CH		 1222 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1223 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1224
27fa9bc5
CH		 1225 dev_warn(nvmeq->dev->ctrl.device,
1226 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1227 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1228 blk_mq_free_request(req);
bc5fc7e4
MW		 1229}
1230
b2a0eb1a
KB		 1231static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1232{
1233
1234 /* If true, indicates loss of adapter communication, possibly by a
1235 * NVMe Subsystem reset.
1236 */
1237 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1238
ad70062c
JW		 1239 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1240 switch (dev->ctrl.state) {
1241 case NVME_CTRL_RESETTING:
ad6a0a52 1242 case NVME_CTRL_CONNECTING:
b2a0eb1a 1243 return false;
ad70062c
JW		 1244 default:
1245 break;
1246 }
b2a0eb1a
KB		 1247
1248 /* We shouldn't reset unless the controller is on fatal error state
1249 * _or_ if we lost the communication with it.
1250 */
1251 if (!(csts & NVME_CSTS_CFS) && !nssro)
1252 return false;
1253
b2a0eb1a
KB		 1254 return true;
1255}
1256
1257static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1258{
1259 /* Read a config register to help see what died. */
1260 u16 pci_status;
1261 int result;
1262
1263 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1264 &pci_status);
1265 if (result == PCIBIOS_SUCCESSFUL)
1266 dev_warn(dev->ctrl.device,
1267 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1268 csts, pci_status);
1269 else
1270 dev_warn(dev->ctrl.device,
1271 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1272 csts, result);
1273}
1274
31c7c7d2 1275static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1276{
f4800d6d
CH		 1277 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1278 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1279 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1280 struct request *abort_req;
a4aea562 1281 struct nvme_command cmd;
b2a0eb1a
KB		 1282 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1283
651438bb
WX		 1284 /* If PCI error recovery process is happening, we cannot reset or
1285 * the recovery mechanism will surely fail.
1286 */
1287 mb();
1288 if (pci_channel_offline(to_pci_dev(dev->dev)))
1289 return BLK_EH_RESET_TIMER;
1290
b2a0eb1a
KB		 1291 /*
1292 * Reset immediately if the controller is failed
1293 */
1294 if (nvme_should_reset(dev, csts)) {
1295 nvme_warn_reset(dev, csts);
1296 nvme_dev_disable(dev, false);
d86c4d8e 1297 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1298 return BLK_EH_DONE;
b2a0eb1a 1299 }
c30341dc 1300
7776db1c
KB		 1301 /*
1302 * Did we miss an interrupt?
1303 */
0b2a8a9f 1304 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1305 dev_warn(dev->ctrl.device,
1306 "I/O %d QID %d timeout, completion polled\n",
1307 req->tag, nvmeq->qid);
db8c48e4 1308 return BLK_EH_DONE;
7776db1c
KB		 1309 }
1310
31c7c7d2 1311 /*
fd634f41
CH		 1312 * Shutdown immediately if controller times out while starting. The
1313 * reset work will see the pci device disabled when it gets the forced
1314 * cancellation error. All outstanding requests are completed on
db8c48e4 1315 * shutdown, so we return BLK_EH_DONE.
fd634f41 1316 */
4244140d
KB		 1317 switch (dev->ctrl.state) {
1318 case NVME_CTRL_CONNECTING:
1319 case NVME_CTRL_RESETTING:
b9cac43c 1320 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1321 "I/O %d QID %d timeout, disable controller\n",
1322 req->tag, nvmeq->qid);
a5cdb68c 1323 nvme_dev_disable(dev, false);
27fa9bc5 1324 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1325 return BLK_EH_DONE;
4244140d
KB		 1326 default:
1327 break;
c30341dc
KB		 1328 }
1329
fd634f41
CH		 1330 /*
1331 * Shutdown the controller immediately and schedule a reset if the
1332 * command was already aborted once before and still hasn't been
1333 * returned to the driver, or if this is the admin queue.
31c7c7d2 1334 */
f4800d6d 1335 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1336 dev_warn(dev->ctrl.device,
e1569a16
KB		 1337 "I/O %d QID %d timeout, reset controller\n",
1338 req->tag, nvmeq->qid);
a5cdb68c 1339 nvme_dev_disable(dev, false);
d86c4d8e 1340 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1341
27fa9bc5 1342 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1343 return BLK_EH_DONE;
c30341dc 1344 }
c30341dc 1345
e7a2a87d 1346 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1347 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1348 return BLK_EH_RESET_TIMER;
6bf25d16 1349 }
7bf7d778 1350 iod->aborted = 1;
a4aea562 1351
c30341dc
KB		 1352 memset(&cmd, 0, sizeof(cmd));
1353 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1354 cmd.abort.cid = req->tag;
c30341dc 1355 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1356
1b3c47c1
SG		 1357 dev_warn(nvmeq->dev->ctrl.device,
1358 "I/O %d QID %d timeout, aborting\n",
1359 req->tag, nvmeq->qid);
e7a2a87d
CH		 1360
1361 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1362 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1363 if (IS_ERR(abort_req)) {
1364 atomic_inc(&dev->ctrl.abort_limit);
1365 return BLK_EH_RESET_TIMER;
1366 }
1367
1368 abort_req->timeout = ADMIN_TIMEOUT;
1369 abort_req->end_io_data = NULL;
1370 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1371
31c7c7d2
CH		 1372 /*
1373 * The aborted req will be completed on receiving the abort req.
1374 * We enable the timer again. If hit twice, it'll cause a device reset,
1375 * as the device then is in a faulty state.
1376 */
1377 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1378}
1379
a4aea562
MB		 1380static void nvme_free_queue(struct nvme_queue *nvmeq)
1381{
9e866774
MW		 1382 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1383 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1384 if (!nvmeq->sq_cmds)
1385 return;
0f238ff5 1386
63223078
CH		 1387 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1388 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1389 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1390 } else {
1391 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1392 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1393 }
9e866774
MW		 1394}
1395
a1a5ef99 1396static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1397{
1398 int i;
1399
d858e5f0 1400 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1401 dev->ctrl.queue_count--;
147b27e4 1402 nvme_free_queue(&dev->queues[i]);
121c7ad4 1403 }
22404274
KB		 1404}
1405
4d115420
KB		 1406/**
1407 * nvme_suspend_queue - put queue into suspended state
40581d1a 1408 * @nvmeq: queue to suspend
4d115420
KB		 1409 */
1410static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1411{
4e224106 1412 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1413 return 1;
a09115b2 1414
4e224106 1415 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1416 mb();
a09115b2 1417
4e224106 1418 nvmeq->dev->online_queues--;
1c63dc66 1419 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1420 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
4e224106
CH		 1421 if (nvmeq->cq_vector == -1)
1422 return 0;
1423 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1424 nvmeq->cq_vector = -1;
4d115420
KB		 1425 return 0;
1426}
b60503ba 1427
8fae268b
KB		 1428static void nvme_suspend_io_queues(struct nvme_dev *dev)
1429{
1430 int i;
1431
1432 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1433 nvme_suspend_queue(&dev->queues[i]);
1434}
1435
a5cdb68c 1436static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1437{
147b27e4 1438 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1439
a5cdb68c
KB		 1440 if (shutdown)
1441 nvme_shutdown_ctrl(&dev->ctrl);
1442 else
20d0dfe6 1443 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1444
0b2a8a9f 1445 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1446}
1447
8ffaadf7
JD		 1448static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1449 int entry_size)
1450{
1451 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1452 unsigned q_size_aligned = roundup(q_depth * entry_size,
1453 dev->ctrl.page_size);
8ffaadf7
JD		 1454
1455 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1456 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1457 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1458 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1459
1460 /*
1461 * Ensure the reduced q_depth is above some threshold where it
1462 * would be better to map queues in system memory with the
1463 * original depth
1464 */
1465 if (q_depth < 64)
1466 return -ENOMEM;
1467 }
1468
1469 return q_depth;
1470}
1471
1472static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1473 int qid, int depth)
1474{
0f238ff5
LG		 1475 struct pci_dev *pdev = to_pci_dev(dev->dev);
1476
1477 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1478 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1479 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1480 nvmeq->sq_cmds);
63223078
CH		 1481 if (nvmeq->sq_dma_addr) {
1482 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1483 return 0;
1484 }
0f238ff5 1485 }
8ffaadf7 1486
63223078
CH		 1487 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1488 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1489 if (!nvmeq->sq_cmds)
1490 return -ENOMEM;
8ffaadf7
JD		 1491 return 0;
1492}
1493
a6ff7262 1494static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1495{
147b27e4 1496 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1497
62314e40
KB		 1498 if (dev->ctrl.queue_count > qid)
1499 return 0;
b60503ba 1500
750afb08
LC		 1501 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
1502 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1503 if (!nvmeq->cqes)
1504 goto free_nvmeq;
b60503ba 1505
8ffaadf7 1506 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1507 goto free_cqdma;
1508
e75ec752 1509 nvmeq->q_dmadev = dev->dev;
091b6092 1510 nvmeq->dev = dev;
1ab0cd69 1511 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1512 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1513 nvmeq->cq_head = 0;
82123460 1514 nvmeq->cq_phase = 1;
b80d5ccc 1515 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1516 nvmeq->q_depth = depth;
c30341dc 1517 nvmeq->qid = qid;
758dd7fd 1518 nvmeq->cq_vector = -1;
d858e5f0 1519 dev->ctrl.queue_count++;
36a7e993 1520
147b27e4 1521 return 0;
b60503ba
MW		 1522
1523 free_cqdma:
e75ec752 1524 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1525 nvmeq->cq_dma_addr);
1526 free_nvmeq:
147b27e4 1527 return -ENOMEM;
b60503ba
MW		 1528}
1529
dca51e78 1530static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1531{
0ff199cb
CH		 1532 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1533 int nr = nvmeq->dev->ctrl.instance;
1534
1535 if (use_threaded_interrupts) {
1536 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1537 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1538 } else {
1539 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1540 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1541 }
3001082c
MW		 1542}
1543
22404274 1544static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1545{
22404274 1546 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1547
22404274 1548 nvmeq->sq_tail = 0;
04f3eafd 1549 nvmeq->last_sq_tail = 0;
22404274
KB		 1550 nvmeq->cq_head = 0;
1551 nvmeq->cq_phase = 1;
b80d5ccc 1552 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1553 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1554 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1555 dev->online_queues++;
3a7afd8e 1556 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1557}
1558
4b04cc6a 1559static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1560{
1561 struct nvme_dev *dev = nvmeq->dev;
1562 int result;
a8e3e0bb 1563 s16 vector;
3f85d50b 1564
d1ed6aa1
CH		 1565 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1566
22b55601
KB		 1567 /*
1568 * A queue's vector matches the queue identifier unless the controller
1569 * has only one vector available.
1570 */
4b04cc6a
JA		 1571 if (!polled)
1572 vector = dev->num_vecs == 1 ? 0 : qid;
1573 else
1574 vector = -1;
1575
a8e3e0bb 1576 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1577 if (result)
1578 return result;
b60503ba
MW		 1579
1580 result = adapter_alloc_sq(dev, qid, nvmeq);
1581 if (result < 0)
ded45505
KB		 1582 return result;
1583 else if (result)
b60503ba
MW		 1584 goto release_cq;
1585
a8e3e0bb 1586 nvmeq->cq_vector = vector;
161b8be2 1587 nvme_init_queue(nvmeq, qid);
4b04cc6a
JA		 1588
1589 if (vector != -1) {
1590 result = queue_request_irq(nvmeq);
1591 if (result < 0)
1592 goto release_sq;
1593 }
b60503ba 1594
4e224106 1595 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1596 return result;
b60503ba 1597
a8e3e0bb
JW		 1598release_sq:
1599 nvmeq->cq_vector = -1;
f25a2dfc 1600 dev->online_queues--;
b60503ba 1601 adapter_delete_sq(dev, qid);
a8e3e0bb 1602release_cq:
b60503ba 1603 adapter_delete_cq(dev, qid);
22404274 1604 return result;
b60503ba
MW		 1605}
1606
f363b089 1607static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1608 .queue_rq = nvme_queue_rq,
77f02a7a 1609 .complete = nvme_pci_complete_rq,
a4aea562 1610 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1611 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1612 .init_request = nvme_init_request,
a4aea562
MB		 1613 .timeout = nvme_timeout,
1614};
1615
f363b089 1616static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1617 .queue_rq = nvme_queue_rq,
1618 .complete = nvme_pci_complete_rq,
1619 .commit_rqs = nvme_commit_rqs,
1620 .init_hctx = nvme_init_hctx,
1621 .init_request = nvme_init_request,
1622 .map_queues = nvme_pci_map_queues,
1623 .timeout = nvme_timeout,
1624 .poll = nvme_poll,
dabcefab
JA		 1625};
1626
ea191d2f
KB		 1627static void nvme_dev_remove_admin(struct nvme_dev *dev)
1628{
1c63dc66 1629 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1630 /*
1631 * If the controller was reset during removal, it's possible
1632 * user requests may be waiting on a stopped queue. Start the
1633 * queue to flush these to completion.
1634 */
c81545f9 1635 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1636 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1637 blk_mq_free_tag_set(&dev->admin_tagset);
1638 }
1639}
1640
a4aea562
MB		 1641static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1642{
1c63dc66 1643 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1644 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1645 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1646
38dabe21 1647 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1648 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1649 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1650 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1651 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1652 dev->admin_tagset.driver_data = dev;
1653
1654 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1655 return -ENOMEM;
34b6c231 1656 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1657
1c63dc66
CH		 1658 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1659 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1660 blk_mq_free_tag_set(&dev->admin_tagset);
1661 return -ENOMEM;
1662 }
1c63dc66 1663 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1664 nvme_dev_remove_admin(dev);
1c63dc66 1665 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1666 return -ENODEV;
1667 }
0fb59cbc 1668 } else
c81545f9 1669 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1670
1671 return 0;
1672}
1673
97f6ef64
XY		 1674static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1675{
1676 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1677}
1678
1679static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1680{
1681 struct pci_dev *pdev = to_pci_dev(dev->dev);
1682
1683 if (size <= dev->bar_mapped_size)
1684 return 0;
1685 if (size > pci_resource_len(pdev, 0))
1686 return -ENOMEM;
1687 if (dev->bar)
1688 iounmap(dev->bar);
1689 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1690 if (!dev->bar) {
1691 dev->bar_mapped_size = 0;
1692 return -ENOMEM;
1693 }
1694 dev->bar_mapped_size = size;
1695 dev->dbs = dev->bar + NVME_REG_DBS;
1696
1697 return 0;
1698}
1699
01ad0990 1700static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1701{
ba47e386 1702 int result;
b60503ba
MW		 1703 u32 aqa;
1704 struct nvme_queue *nvmeq;
1705
97f6ef64
XY		 1706 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1707 if (result < 0)
1708 return result;
1709
8ef2074d 1710 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1711 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1712
7a67cbea
CH		 1713 if (dev->subsystem &&
1714 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1715 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1716
20d0dfe6 1717 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1718 if (result < 0)
1719 return result;
b60503ba 1720
a6ff7262 1721 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1722 if (result)
1723 return result;
b60503ba 1724
147b27e4 1725 nvmeq = &dev->queues[0];
b60503ba
MW		 1726 aqa = nvmeq->q_depth - 1;
1727 aqa |= aqa << 16;
1728
7a67cbea
CH		 1729 writel(aqa, dev->bar + NVME_REG_AQA);
1730 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1731 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1732
20d0dfe6 1733 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1734 if (result)
d4875622 1735 return result;
a4aea562 1736
2b25d981 1737 nvmeq->cq_vector = 0;
161b8be2 1738 nvme_init_queue(nvmeq, 0);
dca51e78 1739 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1740 if (result) {
1741 nvmeq->cq_vector = -1;
d4875622 1742 return result;
758dd7fd 1743 }
025c557a 1744
4e224106 1745 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1746 return result;
1747}
1748
749941f2 1749static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1750{
4b04cc6a 1751 unsigned i, max, rw_queues;
749941f2 1752 int ret = 0;
42f61420 1753
d858e5f0 1754 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1755 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1756 ret = -ENOMEM;
42f61420 1757 break;
749941f2
CH		 1758 }
1759 }
42f61420 1760
d858e5f0 1761 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1762 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1763 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1764 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1765 } else {
1766 rw_queues = max;
1767 }
1768
949928c1 1769 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1770 bool polled = i > rw_queues;
1771
1772 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1773 if (ret)
42f61420 1774 break;
27e8166c 1775 }
749941f2
CH		 1776
1777 /*
1778 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1779 * than the desired amount of queues, and even a controller without
1780 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1781 * be useful to upgrade a buggy firmware for example.
1782 */
1783 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1784}
1785
202021c1
SB		 1786static ssize_t nvme_cmb_show(struct device *dev,
1787 struct device_attribute *attr,
1788 char *buf)
1789{
1790 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1791
c965809c 1792 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1793 ndev->cmbloc, ndev->cmbsz);
1794}
1795static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1796
88de4598 1797static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1798{
88de4598
CH		 1799 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1800
1801 return 1ULL << (12 + 4 * szu);
1802}
1803
1804static u32 nvme_cmb_size(struct nvme_dev *dev)
1805{
1806 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1807}
1808
f65efd6d 1809static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1810{
88de4598 1811 u64 size, offset;
8ffaadf7
JD		 1812 resource_size_t bar_size;
1813 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1814 int bar;
8ffaadf7 1815
9fe5c59f
KB		 1816 if (dev->cmb_size)
1817 return;
1818
7a67cbea 1819 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1820 if (!dev->cmbsz)
1821 return;
202021c1 1822 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1823
88de4598
CH		 1824 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1825 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1826 bar = NVME_CMB_BIR(dev->cmbloc);
1827 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1828
1829 if (offset > bar_size)
f65efd6d 1830 return;
8ffaadf7
JD		 1831
1832 /*
1833 * Controllers may support a CMB size larger than their BAR,
1834 * for example, due to being behind a bridge. Reduce the CMB to
1835 * the reported size of the BAR
1836 */
1837 if (size > bar_size - offset)
1838 size = bar_size - offset;
1839
0f238ff5
LG		 1840 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1841 dev_warn(dev->ctrl.device,
1842 "failed to register the CMB\n");
f65efd6d 1843 return;
0f238ff5
LG		 1844 }
1845
8ffaadf7 1846 dev->cmb_size = size;
0f238ff5
LG		 1847 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1848
1849 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1850 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1851 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1852
1853 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1854 &dev_attr_cmb.attr, NULL))
1855 dev_warn(dev->ctrl.device,
1856 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1857}
1858
1859static inline void nvme_release_cmb(struct nvme_dev *dev)
1860{
0f238ff5 1861 if (dev->cmb_size) {
1c78f773
MG		 1862 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1863 &dev_attr_cmb.attr, NULL);
0f238ff5 1864 dev->cmb_size = 0;
8ffaadf7
JD		 1865 }
1866}
1867
87ad72a5
CH		 1868static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1869{
4033f35d 1870 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1871 struct nvme_command c;
87ad72a5
CH		 1872 int ret;
1873
87ad72a5
CH		 1874 memset(&c, 0, sizeof(c));
1875 c.features.opcode = nvme_admin_set_features;
1876 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1877 c.features.dword11 = cpu_to_le32(bits);
1878 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1879 ilog2(dev->ctrl.page_size));
1880 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1881 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1882 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1883
1884 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1885 if (ret) {
1886 dev_warn(dev->ctrl.device,
1887 "failed to set host mem (err %d, flags %#x).\n",
1888 ret, bits);
1889 }
87ad72a5
CH		 1890 return ret;
1891}
1892
1893static void nvme_free_host_mem(struct nvme_dev *dev)
1894{
1895 int i;
1896
1897 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1898 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1899 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1900
cc667f6d
LD		 1901 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1902 le64_to_cpu(desc->addr),
1903 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1904 }
1905
1906 kfree(dev->host_mem_desc_bufs);
1907 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1908 dma_free_coherent(dev->dev,
1909 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1910 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1911 dev->host_mem_descs = NULL;
7e5dd57e 1912 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1913}
1914
92dc6895
CH		 1915static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1916 u32 chunk_size)
9d713c2b 1917{
87ad72a5 1918 struct nvme_host_mem_buf_desc *descs;
92dc6895 1919 u32 max_entries, len;
4033f35d 1920 dma_addr_t descs_dma;
2ee0e4ed 1921 int i = 0;
87ad72a5 1922 void **bufs;
6fbcde66 1923 u64 size, tmp;
87ad72a5 1924
87ad72a5
CH		 1925 tmp = (preferred + chunk_size - 1);
1926 do_div(tmp, chunk_size);
1927 max_entries = tmp;
044a9df1
CH		 1928
1929 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1930 max_entries = dev->ctrl.hmmaxd;
1931
750afb08
LC		 1932 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1933 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1934 if (!descs)
1935 goto out;
1936
1937 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1938 if (!bufs)
1939 goto out_free_descs;
1940
244a8fe4 1941 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1942 dma_addr_t dma_addr;
1943
50cdb7c6 1944 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1945 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1946 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1947 if (!bufs[i])
1948 break;
1949
1950 descs[i].addr = cpu_to_le64(dma_addr);
1951 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1952 i++;
1953 }
1954
92dc6895 1955 if (!size)
87ad72a5 1956 goto out_free_bufs;
87ad72a5 1957
87ad72a5
CH		 1958 dev->nr_host_mem_descs = i;
1959 dev->host_mem_size = size;
1960 dev->host_mem_descs = descs;
4033f35d 1961 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1962 dev->host_mem_desc_bufs = bufs;
1963 return 0;
1964
1965out_free_bufs:
1966 while (--i >= 0) {
1967 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1968
cc667f6d
LD		 1969 dma_free_attrs(dev->dev, size, bufs[i],
1970 le64_to_cpu(descs[i].addr),
1971 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1972 }
1973
1974 kfree(bufs);
1975out_free_descs:
4033f35d
CH		 1976 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1977 descs_dma);
87ad72a5 1978out:
87ad72a5
CH		 1979 dev->host_mem_descs = NULL;
1980 return -ENOMEM;
1981}
1982
92dc6895
CH		 1983static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1984{
1985 u32 chunk_size;
1986
1987 /* start big and work our way down */
30f92d62 1988 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1989 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1990 chunk_size /= 2) {
1991 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1992 if (!min || dev->host_mem_size >= min)
1993 return 0;
1994 nvme_free_host_mem(dev);
1995 }
1996 }
1997
1998 return -ENOMEM;
1999}
2000
9620cfba 2001static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2002{
2003 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2004 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2005 u64 min = (u64)dev->ctrl.hmmin * 4096;
2006 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2007 int ret;
87ad72a5
CH		 2008
2009 preferred = min(preferred, max);
2010 if (min > max) {
2011 dev_warn(dev->ctrl.device,
2012 "min host memory (%lld MiB) above limit (%d MiB).\n",
2013 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2014 nvme_free_host_mem(dev);
9620cfba 2015 return 0;
87ad72a5
CH		 2016 }
2017
2018 /*
2019 * If we already have a buffer allocated check if we can reuse it.
2020 */
2021 if (dev->host_mem_descs) {
2022 if (dev->host_mem_size >= min)
2023 enable_bits |= NVME_HOST_MEM_RETURN;
2024 else
2025 nvme_free_host_mem(dev);
2026 }
2027
2028 if (!dev->host_mem_descs) {
92dc6895
CH		 2029 if (nvme_alloc_host_mem(dev, min, preferred)) {
2030 dev_warn(dev->ctrl.device,
2031 "failed to allocate host memory buffer.\n");
9620cfba 2032 return 0; /* controller must work without HMB */
92dc6895
CH		 2033 }
2034
2035 dev_info(dev->ctrl.device,
2036 "allocated %lld MiB host memory buffer.\n",
2037 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2038 }
2039
9620cfba
CH		 2040 ret = nvme_set_host_mem(dev, enable_bits);
2041 if (ret)
87ad72a5 2042 nvme_free_host_mem(dev);
9620cfba 2043 return ret;
9d713c2b
KB		 2044}
2045
c45b1fa2 2046/* irq_queues covers admin queue */
6451fe73 2047static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues)
3b6592f7
JA		 2048{
2049 unsigned int this_w_queues = write_queues;
2050
c45b1fa2
ML		 2051 WARN_ON(!irq_queues);
2052
3b6592f7 2053 /*
c45b1fa2
ML		 2054 * Setup read/write queue split, assign admin queue one independent
2055 * irq vector if irq_queues is > 1.
3b6592f7 2056 */
c45b1fa2 2057 if (irq_queues <= 2) {
e20ba6e1
CH		 2058 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2059 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7
JA		 2060 return;
2061 }
2062
2063 /*
2064 * If 'write_queues' is set, ensure it leaves room for at least
c45b1fa2 2065 * one read queue and one admin queue
3b6592f7 2066 */
6451fe73 2067 if (this_w_queues >= irq_queues)
c45b1fa2 2068 this_w_queues = irq_queues - 2;
3b6592f7
JA		 2069
2070 /*
2071 * If 'write_queues' is set to zero, reads and writes will share
2072 * a queue set.
2073 */
2074 if (!this_w_queues) {
c45b1fa2 2075 dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues - 1;
e20ba6e1 2076 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2077 } else {
e20ba6e1 2078 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues;
c45b1fa2 2079 dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues - 1;
3b6592f7
JA		 2080 }
2081}
2082
6451fe73 2083static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2084{
2085 struct pci_dev *pdev = to_pci_dev(dev->dev);
2086 int irq_sets[2];
2087 struct irq_affinity affd = {
2088 .pre_vectors = 1,
2089 .nr_sets = ARRAY_SIZE(irq_sets),
2090 .sets = irq_sets,
2091 };
30e06628 2092 int result = 0;
6451fe73
JA		 2093 unsigned int irq_queues, this_p_queues;
2094
2095 /*
2096 * Poll queues don't need interrupts, but we need at least one IO
2097 * queue left over for non-polled IO.
2098 */
2099 this_p_queues = poll_queues;
2100 if (this_p_queues >= nr_io_queues) {
2101 this_p_queues = nr_io_queues - 1;
2102 irq_queues = 1;
2103 } else {
c45b1fa2 2104 irq_queues = nr_io_queues - this_p_queues + 1;
6451fe73
JA		 2105 }
2106 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
3b6592f7
JA		 2107
2108 /*
2109 * For irq sets, we have to ask for minvec == maxvec. This passes
2110 * any reduction back to us, so we can adjust our queue counts and
2111 * IRQ vector needs.
2112 */
2113 do {
6451fe73 2114 nvme_calc_io_queues(dev, irq_queues);
e20ba6e1
CH		 2115 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT];
2116 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ];
3b6592f7
JA		 2117 if (!irq_sets[1])
2118 affd.nr_sets = 1;
2119
2120 /*
db29eb05
JA		 2121 * If we got a failure and we're down to asking for just
2122 * 1 + 1 queues, just ask for a single vector. We'll share
2123 * that between the single IO queue and the admin queue.
c45b1fa2 2124 * Otherwise, we assign one independent vector to admin queue.
3b6592f7 2125 */
c45b1fa2 2126 if (irq_queues > 1)
6451fe73 2127 irq_queues = irq_sets[0] + irq_sets[1] + 1;
3b6592f7 2128
6451fe73
JA		 2129 result = pci_alloc_irq_vectors_affinity(pdev, irq_queues,
2130 irq_queues,
3b6592f7
JA		 2131 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2132
2133 /*
db29eb05
JA		 2134 * Need to reduce our vec counts. If we get ENOSPC, the
2135 * platform should support mulitple vecs, we just need
2136 * to decrease our ask. If we get EINVAL, the platform
2137 * likely does not. Back down to ask for just one vector.
3b6592f7
JA		 2138 */
2139 if (result == -ENOSPC) {
6451fe73
JA		 2140 irq_queues--;
2141 if (!irq_queues)
3b6592f7
JA		 2142 return result;
2143 continue;
db29eb05 2144 } else if (result == -EINVAL) {
6451fe73 2145 irq_queues = 1;
db29eb05 2146 continue;
3b6592f7
JA		 2147 } else if (result <= 0)
2148 return -EIO;
2149 break;
2150 } while (1);
2151
2152 return result;
2153}
2154
8fae268b
KB		 2155static void nvme_disable_io_queues(struct nvme_dev *dev)
2156{
2157 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2158 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2159}
2160
8d85fce7 2161static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2162{
147b27e4 2163 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2164 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2165 int result, nr_io_queues;
2166 unsigned long size;
b60503ba 2167
3b6592f7 2168 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2169 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2170 if (result < 0)
1b23484b 2171 return result;
9a0be7ab 2172
f5fa90dc 2173 if (nr_io_queues == 0)
a5229050 2174 return 0;
4e224106
CH		 2175
2176 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2177
0f238ff5 2178 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2179 result = nvme_cmb_qdepth(dev, nr_io_queues,
2180 sizeof(struct nvme_command));
2181 if (result > 0)
2182 dev->q_depth = result;
2183 else
0f238ff5 2184 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2185 }
2186
97f6ef64
XY		 2187 do {
2188 size = db_bar_size(dev, nr_io_queues);
2189 result = nvme_remap_bar(dev, size);
2190 if (!result)
2191 break;
2192 if (!--nr_io_queues)
2193 return -ENOMEM;
2194 } while (1);
2195 adminq->q_db = dev->dbs;
f1938f6e 2196
8fae268b 2197 retry:
9d713c2b 2198 /* Deregister the admin queue's interrupt */
0ff199cb 2199 pci_free_irq(pdev, 0, adminq);
9d713c2b 2200
e32efbfc
JA		 2201 /*
2202 * If we enable msix early due to not intx, disable it again before
2203 * setting up the full range we need.
2204 */
dca51e78 2205 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2206
2207 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2208 if (result <= 0)
dca51e78 2209 return -EIO;
3b6592f7 2210
22b55601 2211 dev->num_vecs = result;
4b04cc6a 2212 result = max(result - 1, 1);
e20ba6e1 2213 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2214
063a8096
MW		 2215 /*
2216 * Should investigate if there's a performance win from allocating
2217 * more queues than interrupt vectors; it might allow the submission
2218 * path to scale better, even if the receive path is limited by the
2219 * number of interrupts.
2220 */
dca51e78 2221 result = queue_request_irq(adminq);
758dd7fd
JD		 2222 if (result) {
2223 adminq->cq_vector = -1;
d4875622 2224 return result;
758dd7fd 2225 }
4e224106 2226 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2227
2228 result = nvme_create_io_queues(dev);
2229 if (result || dev->online_queues < 2)
2230 return result;
2231
2232 if (dev->online_queues - 1 < dev->max_qid) {
2233 nr_io_queues = dev->online_queues - 1;
2234 nvme_disable_io_queues(dev);
2235 nvme_suspend_io_queues(dev);
2236 goto retry;
2237 }
2238 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2239 dev->io_queues[HCTX_TYPE_DEFAULT],
2240 dev->io_queues[HCTX_TYPE_READ],
2241 dev->io_queues[HCTX_TYPE_POLL]);
2242 return 0;
b60503ba
MW		 2243}
2244
2a842aca 2245static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2246{
db3cbfff 2247 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2248
db3cbfff 2249 blk_mq_free_request(req);
d1ed6aa1 2250 complete(&nvmeq->delete_done);
a5768aa8
KB		 2251}
2252
2a842aca 2253static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2254{
db3cbfff 2255 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2256
d1ed6aa1
CH		 2257 if (error)
2258 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2259
2260 nvme_del_queue_end(req, error);
a5768aa8
KB		 2261}
2262
db3cbfff 2263static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2264{
db3cbfff
KB		 2265 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2266 struct request *req;
2267 struct nvme_command cmd;
bda4e0fb 2268
db3cbfff
KB		 2269 memset(&cmd, 0, sizeof(cmd));
2270 cmd.delete_queue.opcode = opcode;
2271 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2272
eb71f435 2273 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2274 if (IS_ERR(req))
2275 return PTR_ERR(req);
bda4e0fb 2276
db3cbfff
KB		 2277 req->timeout = ADMIN_TIMEOUT;
2278 req->end_io_data = nvmeq;
2279
d1ed6aa1 2280 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2281 blk_execute_rq_nowait(q, NULL, req, false,
2282 opcode == nvme_admin_delete_cq ?
2283 nvme_del_cq_end : nvme_del_queue_end);
2284 return 0;
bda4e0fb
KB		 2285}
2286
8fae268b 2287static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2288{
5271edd4 2289 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2290 unsigned long timeout;
a5768aa8 2291
db3cbfff 2292 retry:
5271edd4
CH		 2293 timeout = ADMIN_TIMEOUT;
2294 while (nr_queues > 0) {
2295 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2296 break;
2297 nr_queues--;
2298 sent++;
db3cbfff 2299 }
d1ed6aa1
CH		 2300 while (sent) {
2301 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2302
2303 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2304 timeout);
2305 if (timeout == 0)
2306 return false;
d1ed6aa1
CH		 2307
2308 /* handle any remaining CQEs */
2309 if (opcode == nvme_admin_delete_cq &&
2310 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags))
2311 nvme_poll_irqdisable(nvmeq, -1);
2312
2313 sent--;
5271edd4
CH		 2314 if (nr_queues)
2315 goto retry;
2316 }
2317 return true;
a5768aa8
KB		 2318}
2319
422ef0c7 2320/*
2b1b7e78 2321 * return error value only when tagset allocation failed
422ef0c7 2322 */
8d85fce7 2323static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2324{
2b1b7e78
JW		 2325 int ret;
2326
5bae7f73 2327 if (!dev->ctrl.tagset) {
376f7ef8 2328 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2329 dev->tagset.nr_hw_queues = dev->online_queues - 1;
ed92ad37
CH		 2330 dev->tagset.nr_maps = 2; /* default + read */
2331 if (dev->io_queues[HCTX_TYPE_POLL])
2332 dev->tagset.nr_maps++;
ffe7704d
KB		 2333 dev->tagset.timeout = NVME_IO_TIMEOUT;
2334 dev->tagset.numa_node = dev_to_node(dev->dev);
2335 dev->tagset.queue_depth =
a4aea562 2336 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2337 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2338 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2339 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2340 nvme_pci_cmd_size(dev, true));
2341 }
ffe7704d
KB		 2342 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2343 dev->tagset.driver_data = dev;
b60503ba 2344
2b1b7e78
JW		 2345 ret = blk_mq_alloc_tag_set(&dev->tagset);
2346 if (ret) {
2347 dev_warn(dev->ctrl.device,
2348 "IO queues tagset allocation failed %d\n", ret);
2349 return ret;
2350 }
5bae7f73 2351 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2352
2353 nvme_dbbuf_set(dev);
949928c1
KB		 2354 } else {
2355 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2356
2357 /* Free previously allocated queues that are no longer usable */
2358 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2359 }
949928c1 2360
e1e5e564 2361 return 0;
b60503ba
MW		 2362}
2363
b00a726a 2364static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2365{
b00a726a 2366 int result = -ENOMEM;
e75ec752 2367 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2368
2369 if (pci_enable_device_mem(pdev))
2370 return result;
2371
0877cb0d 2372 pci_set_master(pdev);
0877cb0d 2373
e75ec752
CH		 2374 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2375 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2376 goto disable;
0877cb0d 2377
7a67cbea 2378 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2379 result = -ENODEV;
b00a726a 2380 goto disable;
0e53d180 2381 }
e32efbfc
JA		 2382
2383 /*
a5229050
KB		 2384 * Some devices and/or platforms don't advertise or work with INTx
2385 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2386 * adjust this later.
e32efbfc 2387 */
dca51e78
CH		 2388 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2389 if (result < 0)
2390 return result;
e32efbfc 2391
20d0dfe6 2392 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2393
20d0dfe6 2394 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2395 io_queue_depth);
20d0dfe6 2396 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2397 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2398
2399 /*
2400 * Temporary fix for the Apple controller found in the MacBook8,1 and
2401 * some MacBook7,1 to avoid controller resets and data loss.
2402 */
2403 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2404 dev->q_depth = 2;
9bdcfb10
CH		 2405 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2406 "set queue depth=%u to work around controller resets\n",
1f390c1f 2407 dev->q_depth);
d554b5e1
MP		 2408 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2409 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2410 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2411 dev->q_depth = 64;
2412 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2413 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2414 }
2415
f65efd6d 2416 nvme_map_cmb(dev);
202021c1 2417
a0a3408e
KB		 2418 pci_enable_pcie_error_reporting(pdev);
2419 pci_save_state(pdev);
0877cb0d
KB		 2420 return 0;
2421
2422 disable:
0877cb0d
KB		 2423 pci_disable_device(pdev);
2424 return result;
2425}
2426
2427static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2428{
2429 if (dev->bar)
2430 iounmap(dev->bar);
a1f447b3 2431 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2432}
2433
2434static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2435{
e75ec752
CH		 2436 struct pci_dev *pdev = to_pci_dev(dev->dev);
2437
dca51e78 2438 pci_free_irq_vectors(pdev);
0877cb0d 2439
a0a3408e
KB		 2440 if (pci_is_enabled(pdev)) {
2441 pci_disable_pcie_error_reporting(pdev);
e75ec752 2442 pci_disable_device(pdev);
4d115420 2443 }
4d115420
KB		 2444}
2445
a5cdb68c 2446static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2447{
302ad8cc
KB		 2448 bool dead = true;
2449 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2450
77bf25ea 2451 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2452 if (pci_is_enabled(pdev)) {
2453 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2454
ebef7368
KB		 2455 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2456 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2457 nvme_start_freeze(&dev->ctrl);
2458 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2459 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2460 }
c21377f8 2461
302ad8cc
KB		 2462 /*
2463 * Give the controller a chance to complete all entered requests if
2464 * doing a safe shutdown.
2465 */
87ad72a5
CH		 2466 if (!dead) {
2467 if (shutdown)
2468 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2469 }
2470
2471 nvme_stop_queues(&dev->ctrl);
87ad72a5 2472
64ee0ac0 2473 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2474 nvme_disable_io_queues(dev);
a5cdb68c 2475 nvme_disable_admin_queue(dev, shutdown);
4d115420 2476 }
8fae268b
KB		 2477 nvme_suspend_io_queues(dev);
2478 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2479 nvme_pci_disable(dev);
07836e65 2480
e1958e65
ML		 2481 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2482 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2483
2484 /*
2485 * The driver will not be starting up queues again if shutting down so
2486 * must flush all entered requests to their failed completion to avoid
2487 * deadlocking blk-mq hot-cpu notifier.
2488 */
2489 if (shutdown)
2490 nvme_start_queues(&dev->ctrl);
77bf25ea 2491 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2492}
2493
091b6092
MW		 2494static int nvme_setup_prp_pools(struct nvme_dev *dev)
2495{
e75ec752 2496 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2497 PAGE_SIZE, PAGE_SIZE, 0);
2498 if (!dev->prp_page_pool)
2499 return -ENOMEM;
2500
99802a7a 2501 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2502 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2503 256, 256, 0);
2504 if (!dev->prp_small_pool) {
2505 dma_pool_destroy(dev->prp_page_pool);
2506 return -ENOMEM;
2507 }
091b6092
MW		 2508 return 0;
2509}
2510
2511static void nvme_release_prp_pools(struct nvme_dev *dev)
2512{
2513 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2514 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2515}
2516
1673f1f0 2517static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2518{
1673f1f0 2519 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2520
f9f38e33 2521 nvme_dbbuf_dma_free(dev);
e75ec752 2522 put_device(dev->dev);
4af0e21c
KB		 2523 if (dev->tagset.tags)
2524 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2525 if (dev->ctrl.admin_q)
2526 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2527 kfree(dev->queues);
e286bcfc 2528 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2529 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2530 kfree(dev);
2531}
2532
f58944e2
KB		 2533static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2534{
237045fc 2535 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2536
d22524a4 2537 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2538 nvme_dev_disable(dev, false);
9f9cafc1 2539 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2540 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2541 nvme_put_ctrl(&dev->ctrl);
2542}
2543
fd634f41 2544static void nvme_reset_work(struct work_struct *work)
5e82e952 2545{
d86c4d8e
CH		 2546 struct nvme_dev *dev =
2547 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2548 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2549 int result = -ENODEV;
2b1b7e78 2550 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2551
82b057ca 2552 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2553 goto out;
5e82e952 2554
fd634f41
CH		 2555 /*
2556 * If we're called to reset a live controller first shut it down before
2557 * moving on.
2558 */
b00a726a 2559 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2560 nvme_dev_disable(dev, false);
5e82e952 2561
5c959d73 2562 mutex_lock(&dev->shutdown_lock);
b00a726a 2563 result = nvme_pci_enable(dev);
f0b50732 2564 if (result)
3cf519b5 2565 goto out;
f0b50732 2566
01ad0990 2567 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2568 if (result)
f58944e2 2569 goto out;
f0b50732 2570
0fb59cbc
KB		 2571 result = nvme_alloc_admin_tags(dev);
2572 if (result)
f58944e2 2573 goto out;
b9afca3e 2574
943e942e
JA		 2575 /*
2576 * Limit the max command size to prevent iod->sg allocations going
2577 * over a single page.
2578 */
2579 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2580 dev->ctrl.max_segments = NVME_MAX_SEGS;
5c959d73
KB		 2581 mutex_unlock(&dev->shutdown_lock);
2582
2583 /*
2584 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2585 * initializing procedure here.
2586 */
2587 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2588 dev_warn(dev->ctrl.device,
2589 "failed to mark controller CONNECTING\n");
2590 goto out;
2591 }
943e942e 2592
ce4541f4
CH		 2593 result = nvme_init_identify(&dev->ctrl);
2594 if (result)
f58944e2 2595 goto out;
ce4541f4 2596
e286bcfc
SB		 2597 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2598 if (!dev->ctrl.opal_dev)
2599 dev->ctrl.opal_dev =
2600 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2601 else if (was_suspend)
2602 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2603 } else {
2604 free_opal_dev(dev->ctrl.opal_dev);
2605 dev->ctrl.opal_dev = NULL;
4f1244c8 2606 }
a98e58e5 2607
f9f38e33
HK		 2608 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2609 result = nvme_dbbuf_dma_alloc(dev);
2610 if (result)
2611 dev_warn(dev->dev,
2612 "unable to allocate dma for dbbuf\n");
2613 }
2614
9620cfba
CH		 2615 if (dev->ctrl.hmpre) {
2616 result = nvme_setup_host_mem(dev);
2617 if (result < 0)
2618 goto out;
2619 }
87ad72a5 2620
f0b50732 2621 result = nvme_setup_io_queues(dev);
badc34d4 2622 if (result)
f58944e2 2623 goto out;
f0b50732 2624
2659e57b
CH		 2625 /*
2626 * Keep the controller around but remove all namespaces if we don't have
2627 * any working I/O queue.
2628 */
3cf519b5 2629 if (dev->online_queues < 2) {
1b3c47c1 2630 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2631 nvme_kill_queues(&dev->ctrl);
5bae7f73 2632 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2633 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2634 } else {
25646264 2635 nvme_start_queues(&dev->ctrl);
302ad8cc 2636 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2637 /* hit this only when allocate tagset fails */
2638 if (nvme_dev_add(dev))
2639 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2640 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2641 }
2642
2b1b7e78
JW		 2643 /*
2644 * If only admin queue live, keep it to do further investigation or
2645 * recovery.
2646 */
2647 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2648 dev_warn(dev->ctrl.device,
2649 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2650 goto out;
2651 }
92911a55 2652
d09f2b45 2653 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2654 return;
f0b50732 2655
3cf519b5 2656 out:
f58944e2 2657 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2658}
2659
5c8809e6 2660static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2661{
5c8809e6 2662 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2663 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2664
2665 if (pci_get_drvdata(pdev))
921920ab 2666 device_release_driver(&pdev->dev);
1673f1f0 2667 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2668}
2669
1c63dc66 2670static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2671{
1c63dc66 2672 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2673 return 0;
9ca97374
TH		 2674}
2675
5fd4ce1b 2676static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2677{
5fd4ce1b
CH		 2678 writel(val, to_nvme_dev(ctrl)->bar + off);
2679 return 0;
2680}
4cc06521 2681
7fd8930f
CH		 2682static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2683{
2684 *val = readq(to_nvme_dev(ctrl)->bar + off);
2685 return 0;
4cc06521
KB		 2686}
2687
97c12223
KB		 2688static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2689{
2690 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2691
2692 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2693}
2694
1c63dc66 2695static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2696 .name = "pcie",
e439bb12 2697 .module = THIS_MODULE,
e0596ab2
LG		 2698 .flags = NVME_F_METADATA_SUPPORTED |
2699 NVME_F_PCI_P2PDMA,
1c63dc66 2700 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2701 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2702 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2703 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2704 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2705 .get_address = nvme_pci_get_address,
1c63dc66 2706};
4cc06521 2707
b00a726a
KB		 2708static int nvme_dev_map(struct nvme_dev *dev)
2709{
b00a726a
KB		 2710 struct pci_dev *pdev = to_pci_dev(dev->dev);
2711
a1f447b3 2712 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2713 return -ENODEV;
2714
97f6ef64 2715 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2716 goto release;
2717
9fa196e7 2718 return 0;
b00a726a 2719 release:
9fa196e7
MG		 2720 pci_release_mem_regions(pdev);
2721 return -ENODEV;
b00a726a
KB		 2722}
2723
8427bbc2 2724static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2725{
2726 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2727 /*
2728 * Several Samsung devices seem to drop off the PCIe bus
2729 * randomly when APST is on and uses the deepest sleep state.
2730 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2731 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2732 * 950 PRO 256GB", but it seems to be restricted to two Dell
2733 * laptops.
2734 */
2735 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2736 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2737 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2738 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2739 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2740 /*
2741 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2742 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2743 * within few minutes after bootup on a Coffee Lake board -
2744 * ASUS PRIME Z370-A
8427bbc2
KHF		 2745 */
2746 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2747 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2748 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2749 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2750 }
2751
2752 return 0;
2753}
2754
18119775
KB		 2755static void nvme_async_probe(void *data, async_cookie_t cookie)
2756{
2757 struct nvme_dev *dev = data;
80f513b5 2758
18119775
KB		 2759 nvme_reset_ctrl_sync(&dev->ctrl);
2760 flush_work(&dev->ctrl.scan_work);
80f513b5 2761 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2762}
2763
8d85fce7 2764static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2765{
a4aea562 2766 int node, result = -ENOMEM;
b60503ba 2767 struct nvme_dev *dev;
ff5350a8 2768 unsigned long quirks = id->driver_data;
943e942e 2769 size_t alloc_size;
b60503ba 2770
a4aea562
MB		 2771 node = dev_to_node(&pdev->dev);
2772 if (node == NUMA_NO_NODE)
2fa84351 2773 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2774
2775 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2776 if (!dev)
2777 return -ENOMEM;
147b27e4 2778
3b6592f7
JA		 2779 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2780 GFP_KERNEL, node);
b60503ba
MW		 2781 if (!dev->queues)
2782 goto free;
2783
e75ec752 2784 dev->dev = get_device(&pdev->dev);
9a6b9458 2785 pci_set_drvdata(pdev, dev);
1c63dc66 2786
b00a726a
KB		 2787 result = nvme_dev_map(dev);
2788 if (result)
b00c9b7a 2789 goto put_pci;
b00a726a 2790
d86c4d8e 2791 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2792 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2793 mutex_init(&dev->shutdown_lock);
b60503ba 2794
091b6092
MW		 2795 result = nvme_setup_prp_pools(dev);
2796 if (result)
b00c9b7a 2797 goto unmap;
4cc06521 2798
8427bbc2 2799 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2800
943e942e
JA		 2801 /*
2802 * Double check that our mempool alloc size will cover the biggest
2803 * command we support.
2804 */
2805 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2806 NVME_MAX_SEGS, true);
2807 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2808
2809 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2810 mempool_kfree,
2811 (void *) alloc_size,
2812 GFP_KERNEL, node);
2813 if (!dev->iod_mempool) {
2814 result = -ENOMEM;
2815 goto release_pools;
2816 }
2817
b6e44b4c
KB		 2818 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2819 quirks);
2820 if (result)
2821 goto release_mempool;
2822
1b3c47c1
SG		 2823 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2824
80f513b5 2825 nvme_get_ctrl(&dev->ctrl);
18119775 2826 async_schedule(nvme_async_probe, dev);
4caff8fc 2827
b60503ba
MW		 2828 return 0;
2829
b6e44b4c
KB		 2830 release_mempool:
2831 mempool_destroy(dev->iod_mempool);
0877cb0d 2832 release_pools:
091b6092 2833 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2834 unmap:
2835 nvme_dev_unmap(dev);
a96d4f5c 2836 put_pci:
e75ec752 2837 put_device(dev->dev);
b60503ba
MW		 2838 free:
2839 kfree(dev->queues);
b60503ba
MW		 2840 kfree(dev);
2841 return result;
2842}
2843
775755ed 2844static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2845{
a6739479 2846 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2847 nvme_dev_disable(dev, false);
775755ed 2848}
f0d54a54 2849
775755ed
CH		 2850static void nvme_reset_done(struct pci_dev *pdev)
2851{
f263fbb8 2852 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2853 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2854}
2855
09ece142
KB		 2856static void nvme_shutdown(struct pci_dev *pdev)
2857{
2858 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2859 nvme_dev_disable(dev, true);
09ece142
KB		 2860}
2861
f58944e2
KB		 2862/*
2863 * The driver's remove may be called on a device in a partially initialized
2864 * state. This function must not have any dependencies on the device state in
2865 * order to proceed.
2866 */
8d85fce7 2867static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2868{
2869 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2870
bb8d261e 2871 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2872 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2873
6db28eda 2874 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2875 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2876 nvme_dev_disable(dev, true);
cb4bfda6 2877 nvme_dev_remove_admin(dev);
6db28eda 2878 }
0ff9d4e1 2879
d86c4d8e 2880 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2881 nvme_stop_ctrl(&dev->ctrl);
2882 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2883 nvme_dev_disable(dev, true);
9fe5c59f 2884 nvme_release_cmb(dev);
87ad72a5 2885 nvme_free_host_mem(dev);
a4aea562 2886 nvme_dev_remove_admin(dev);
a1a5ef99 2887 nvme_free_queues(dev, 0);
d09f2b45 2888 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2889 nvme_release_prp_pools(dev);
b00a726a 2890 nvme_dev_unmap(dev);
1673f1f0 2891 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2892}
2893
671a6018 2894#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2895static int nvme_suspend(struct device *dev)
2896{
2897 struct pci_dev *pdev = to_pci_dev(dev);
2898 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2899
a5cdb68c 2900 nvme_dev_disable(ndev, true);
cd638946
KB		 2901 return 0;
2902}
2903
2904static int nvme_resume(struct device *dev)
2905{
2906 struct pci_dev *pdev = to_pci_dev(dev);
2907 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2908
d86c4d8e 2909 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2910 return 0;
cd638946 2911}
671a6018 2912#endif
cd638946
KB		 2913
2914static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2915
a0a3408e
KB		 2916static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2917 pci_channel_state_t state)
2918{
2919 struct nvme_dev *dev = pci_get_drvdata(pdev);
2920
2921 /*
2922 * A frozen channel requires a reset. When detected, this method will
2923 * shutdown the controller to quiesce. The controller will be restarted
2924 * after the slot reset through driver's slot_reset callback.
2925 */
a0a3408e
KB		 2926 switch (state) {
2927 case pci_channel_io_normal:
2928 return PCI_ERS_RESULT_CAN_RECOVER;
2929 case pci_channel_io_frozen:
d011fb31
KB		 2930 dev_warn(dev->ctrl.device,
2931 "frozen state error detected, reset controller\n");
a5cdb68c 2932 nvme_dev_disable(dev, false);
a0a3408e
KB		 2933 return PCI_ERS_RESULT_NEED_RESET;
2934 case pci_channel_io_perm_failure:
d011fb31
KB		 2935 dev_warn(dev->ctrl.device,
2936 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2937 return PCI_ERS_RESULT_DISCONNECT;
2938 }
2939 return PCI_ERS_RESULT_NEED_RESET;
2940}
2941
2942static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2943{
2944 struct nvme_dev *dev = pci_get_drvdata(pdev);
2945
1b3c47c1 2946 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2947 pci_restore_state(pdev);
d86c4d8e 2948 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2949 return PCI_ERS_RESULT_RECOVERED;
2950}
2951
2952static void nvme_error_resume(struct pci_dev *pdev)
2953{
72cd4cc2
KB		 2954 struct nvme_dev *dev = pci_get_drvdata(pdev);
2955
2956 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2957}
2958
1d352035 2959static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2960 .error_detected = nvme_error_detected,
b60503ba
MW		 2961 .slot_reset = nvme_slot_reset,
2962 .resume = nvme_error_resume,
775755ed
CH		 2963 .reset_prepare = nvme_reset_prepare,
2964 .reset_done = nvme_reset_done,
b60503ba
MW		 2965};
2966
6eb0d698 2967static const struct pci_device_id nvme_id_table[] = {
106198ed 2968 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2969 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2970 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2971 { PCI_VDEVICE(INTEL, 0x0a53),
2972 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2973 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2974 { PCI_VDEVICE(INTEL, 0x0a54),
2975 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2976 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2977 { PCI_VDEVICE(INTEL, 0x0a55),
2978 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2979 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2980 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2981 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2982 NVME_QUIRK_MEDIUM_PRIO_SQ },
6299358d
JD		 2983 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
2984 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c
KB		 2985 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2986 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2987 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2988 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2989 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2990 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2991 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2992 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2993 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2994 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2995 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2996 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2997 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2998 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2999 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3000 .driver_data = NVME_QUIRK_LIGHTNVM, },
3001 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3002 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3003 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3004 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 3005 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 3006 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 3007 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 3008 { 0, }
3009};
3010MODULE_DEVICE_TABLE(pci, nvme_id_table);
3011
3012static struct pci_driver nvme_driver = {
3013 .name = "nvme",
3014 .id_table = nvme_id_table,
3015 .probe = nvme_probe,
8d85fce7 3016 .remove = nvme_remove,
09ece142 3017 .shutdown = nvme_shutdown,
cd638946
KB		 3018 .driver = {
3019 .pm = &nvme_dev_pm_ops,
3020 },
74d986ab 3021 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3022 .err_handler = &nvme_err_handler,
3023};
3024
3025static int __init nvme_init(void)
3026{
9a6327d2 3027 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3028}
3029
3030static void __exit nvme_exit(void)
3031{
3032 pci_unregister_driver(&nvme_driver);
03e0f3a6 3033 flush_workqueue(nvme_wq);
21bd78bc 3034 _nvme_check_size();
b60503ba
MW		 3035}
3036
3037MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3038MODULE_LICENSE("GPL");
c78b4713 3039MODULE_VERSION("1.0");
b60503ba
MW		 3040module_init(nvme_init);
3041module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)