Commit | Line | Data |
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5f37396d | 1 | // SPDX-License-Identifier: GPL-2.0 |
b60503ba MW |
2 | /* |
3 | * NVM Express device driver | |
6eb0d698 | 4 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
5 | */ |
6 | ||
df4f9bc4 | 7 | #include <linux/acpi.h> |
a0a3408e | 8 | #include <linux/aer.h> |
18119775 | 9 | #include <linux/async.h> |
b60503ba | 10 | #include <linux/blkdev.h> |
a4aea562 | 11 | #include <linux/blk-mq.h> |
dca51e78 | 12 | #include <linux/blk-mq-pci.h> |
fe45e630 | 13 | #include <linux/blk-integrity.h> |
ff5350a8 | 14 | #include <linux/dmi.h> |
b60503ba MW |
15 | #include <linux/init.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
dc90f084 | 18 | #include <linux/memremap.h> |
b60503ba MW |
19 | #include <linux/mm.h> |
20 | #include <linux/module.h> | |
77bf25ea | 21 | #include <linux/mutex.h> |
d0877473 | 22 | #include <linux/once.h> |
b60503ba | 23 | #include <linux/pci.h> |
d916b1be | 24 | #include <linux/suspend.h> |
e1e5e564 | 25 | #include <linux/t10-pi.h> |
b60503ba | 26 | #include <linux/types.h> |
2f8e2c87 | 27 | #include <linux/io-64-nonatomic-lo-hi.h> |
20d3bb92 | 28 | #include <linux/io-64-nonatomic-hi-lo.h> |
a98e58e5 | 29 | #include <linux/sed-opal.h> |
0f238ff5 | 30 | #include <linux/pci-p2pdma.h> |
797a796a | 31 | |
604c01d5 | 32 | #include "trace.h" |
f11bb3e2 CH |
33 | #include "nvme.h" |
34 | ||
c1e0cc7e | 35 | #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) |
8a1d09a6 | 36 | #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) |
c965809c | 37 | |
a7a7cbe3 | 38 | #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) |
9d43cf64 | 39 | |
943e942e JA |
40 | /* |
41 | * These can be higher, but we need to ensure that any command doesn't | |
42 | * require an sg allocation that needs more than a page of data. | |
43 | */ | |
44 | #define NVME_MAX_KB_SZ 4096 | |
45 | #define NVME_MAX_SEGS 127 | |
46 | ||
58ffacb5 | 47 | static int use_threaded_interrupts; |
2e21e445 | 48 | module_param(use_threaded_interrupts, int, 0444); |
58ffacb5 | 49 | |
8ffaadf7 | 50 | static bool use_cmb_sqes = true; |
69f4eb9f | 51 | module_param(use_cmb_sqes, bool, 0444); |
8ffaadf7 JD |
52 | MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); |
53 | ||
87ad72a5 CH |
54 | static unsigned int max_host_mem_size_mb = 128; |
55 | module_param(max_host_mem_size_mb, uint, 0444); | |
56 | MODULE_PARM_DESC(max_host_mem_size_mb, | |
57 | "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); | |
1fa6aead | 58 | |
a7a7cbe3 CK |
59 | static unsigned int sgl_threshold = SZ_32K; |
60 | module_param(sgl_threshold, uint, 0644); | |
61 | MODULE_PARM_DESC(sgl_threshold, | |
62 | "Use SGLs when average request segment size is larger or equal to " | |
63 | "this size. Use 0 to disable SGLs."); | |
64 | ||
27453b45 SG |
65 | #define NVME_PCI_MIN_QUEUE_SIZE 2 |
66 | #define NVME_PCI_MAX_QUEUE_SIZE 4095 | |
b27c1e68 | 67 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp); |
68 | static const struct kernel_param_ops io_queue_depth_ops = { | |
69 | .set = io_queue_depth_set, | |
61f3b896 | 70 | .get = param_get_uint, |
b27c1e68 | 71 | }; |
72 | ||
61f3b896 | 73 | static unsigned int io_queue_depth = 1024; |
b27c1e68 | 74 | module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); |
27453b45 | 75 | MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); |
b27c1e68 | 76 | |
9c9e76d5 WZ |
77 | static int io_queue_count_set(const char *val, const struct kernel_param *kp) |
78 | { | |
79 | unsigned int n; | |
80 | int ret; | |
81 | ||
82 | ret = kstrtouint(val, 10, &n); | |
83 | if (ret != 0 || n > num_possible_cpus()) | |
84 | return -EINVAL; | |
85 | return param_set_uint(val, kp); | |
86 | } | |
87 | ||
88 | static const struct kernel_param_ops io_queue_count_ops = { | |
89 | .set = io_queue_count_set, | |
90 | .get = param_get_uint, | |
91 | }; | |
92 | ||
3f68baf7 | 93 | static unsigned int write_queues; |
9c9e76d5 | 94 | module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); |
3b6592f7 JA |
95 | MODULE_PARM_DESC(write_queues, |
96 | "Number of queues to use for writes. If not set, reads and writes " | |
97 | "will share a queue set."); | |
98 | ||
3f68baf7 | 99 | static unsigned int poll_queues; |
9c9e76d5 | 100 | module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); |
4b04cc6a JA |
101 | MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); |
102 | ||
df4f9bc4 DB |
103 | static bool noacpi; |
104 | module_param(noacpi, bool, 0444); | |
105 | MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); | |
106 | ||
1c63dc66 CH |
107 | struct nvme_dev; |
108 | struct nvme_queue; | |
b3fffdef | 109 | |
a5cdb68c | 110 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); |
8fae268b | 111 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); |
d4b4ff8e | 112 | |
1c63dc66 CH |
113 | /* |
114 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
115 | */ | |
116 | struct nvme_dev { | |
147b27e4 | 117 | struct nvme_queue *queues; |
1c63dc66 CH |
118 | struct blk_mq_tag_set tagset; |
119 | struct blk_mq_tag_set admin_tagset; | |
120 | u32 __iomem *dbs; | |
121 | struct device *dev; | |
122 | struct dma_pool *prp_page_pool; | |
123 | struct dma_pool *prp_small_pool; | |
1c63dc66 CH |
124 | unsigned online_queues; |
125 | unsigned max_qid; | |
e20ba6e1 | 126 | unsigned io_queues[HCTX_MAX_TYPES]; |
22b55601 | 127 | unsigned int num_vecs; |
7442ddce | 128 | u32 q_depth; |
c1e0cc7e | 129 | int io_sqes; |
1c63dc66 | 130 | u32 db_stride; |
1c63dc66 | 131 | void __iomem *bar; |
97f6ef64 | 132 | unsigned long bar_mapped_size; |
5c8809e6 | 133 | struct work_struct remove_work; |
77bf25ea | 134 | struct mutex shutdown_lock; |
1c63dc66 | 135 | bool subsystem; |
1c63dc66 | 136 | u64 cmb_size; |
0f238ff5 | 137 | bool cmb_use_sqes; |
1c63dc66 | 138 | u32 cmbsz; |
202021c1 | 139 | u32 cmbloc; |
1c63dc66 | 140 | struct nvme_ctrl ctrl; |
d916b1be | 141 | u32 last_ps; |
a5df5e79 | 142 | bool hmb; |
87ad72a5 | 143 | |
943e942e JA |
144 | mempool_t *iod_mempool; |
145 | ||
87ad72a5 | 146 | /* shadow doorbell buffer support: */ |
f9f38e33 HK |
147 | u32 *dbbuf_dbs; |
148 | dma_addr_t dbbuf_dbs_dma_addr; | |
149 | u32 *dbbuf_eis; | |
150 | dma_addr_t dbbuf_eis_dma_addr; | |
87ad72a5 CH |
151 | |
152 | /* host memory buffer support: */ | |
153 | u64 host_mem_size; | |
154 | u32 nr_host_mem_descs; | |
4033f35d | 155 | dma_addr_t host_mem_descs_dma; |
87ad72a5 CH |
156 | struct nvme_host_mem_buf_desc *host_mem_descs; |
157 | void **host_mem_desc_bufs; | |
2a5bcfdd WZ |
158 | unsigned int nr_allocated_queues; |
159 | unsigned int nr_write_queues; | |
160 | unsigned int nr_poll_queues; | |
0521905e KB |
161 | |
162 | bool attrs_added; | |
4d115420 | 163 | }; |
1fa6aead | 164 | |
b27c1e68 | 165 | static int io_queue_depth_set(const char *val, const struct kernel_param *kp) |
166 | { | |
27453b45 SG |
167 | return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, |
168 | NVME_PCI_MAX_QUEUE_SIZE); | |
b27c1e68 | 169 | } |
170 | ||
f9f38e33 HK |
171 | static inline unsigned int sq_idx(unsigned int qid, u32 stride) |
172 | { | |
173 | return qid * 2 * stride; | |
174 | } | |
175 | ||
176 | static inline unsigned int cq_idx(unsigned int qid, u32 stride) | |
177 | { | |
178 | return (qid * 2 + 1) * stride; | |
179 | } | |
180 | ||
1c63dc66 CH |
181 | static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) |
182 | { | |
183 | return container_of(ctrl, struct nvme_dev, ctrl); | |
184 | } | |
185 | ||
b60503ba MW |
186 | /* |
187 | * An NVM Express queue. Each device has at least two (one for admin | |
188 | * commands and one for I/O commands). | |
189 | */ | |
190 | struct nvme_queue { | |
091b6092 | 191 | struct nvme_dev *dev; |
1ab0cd69 | 192 | spinlock_t sq_lock; |
c1e0cc7e | 193 | void *sq_cmds; |
3a7afd8e CH |
194 | /* only used for poll queues: */ |
195 | spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; | |
74943d45 | 196 | struct nvme_completion *cqes; |
b60503ba MW |
197 | dma_addr_t sq_dma_addr; |
198 | dma_addr_t cq_dma_addr; | |
b60503ba | 199 | u32 __iomem *q_db; |
7442ddce | 200 | u32 q_depth; |
7c349dde | 201 | u16 cq_vector; |
b60503ba | 202 | u16 sq_tail; |
38210800 | 203 | u16 last_sq_tail; |
b60503ba | 204 | u16 cq_head; |
c30341dc | 205 | u16 qid; |
e9539f47 | 206 | u8 cq_phase; |
c1e0cc7e | 207 | u8 sqes; |
4e224106 CH |
208 | unsigned long flags; |
209 | #define NVMEQ_ENABLED 0 | |
63223078 | 210 | #define NVMEQ_SQ_CMB 1 |
d1ed6aa1 | 211 | #define NVMEQ_DELETE_ERROR 2 |
7c349dde | 212 | #define NVMEQ_POLLED 3 |
f9f38e33 HK |
213 | u32 *dbbuf_sq_db; |
214 | u32 *dbbuf_cq_db; | |
215 | u32 *dbbuf_sq_ei; | |
216 | u32 *dbbuf_cq_ei; | |
d1ed6aa1 | 217 | struct completion delete_done; |
b60503ba MW |
218 | }; |
219 | ||
71bd150c | 220 | /* |
9b048119 CH |
221 | * The nvme_iod describes the data in an I/O. |
222 | * | |
223 | * The sg pointer contains the list of PRP/SGL chunk allocations in addition | |
224 | * to the actual struct scatterlist. | |
71bd150c CH |
225 | */ |
226 | struct nvme_iod { | |
d49187e9 | 227 | struct nvme_request req; |
af7fae85 | 228 | struct nvme_command cmd; |
f4800d6d | 229 | struct nvme_queue *nvmeq; |
a7a7cbe3 | 230 | bool use_sgl; |
f4800d6d | 231 | int aborted; |
71bd150c | 232 | int npages; /* In the PRP list. 0 means small pool in use */ |
71bd150c | 233 | dma_addr_t first_dma; |
dff824b2 | 234 | unsigned int dma_len; /* length of single DMA segment mapping */ |
783b94bd | 235 | dma_addr_t meta_dma; |
91fb2b60 | 236 | struct sg_table sgt; |
b60503ba MW |
237 | }; |
238 | ||
2a5bcfdd | 239 | static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) |
3b6592f7 | 240 | { |
2a5bcfdd | 241 | return dev->nr_allocated_queues * 8 * dev->db_stride; |
f9f38e33 HK |
242 | } |
243 | ||
244 | static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) | |
245 | { | |
2a5bcfdd | 246 | unsigned int mem_size = nvme_dbbuf_size(dev); |
f9f38e33 | 247 | |
58847f12 KB |
248 | if (dev->dbbuf_dbs) { |
249 | /* | |
250 | * Clear the dbbuf memory so the driver doesn't observe stale | |
251 | * values from the previous instantiation. | |
252 | */ | |
253 | memset(dev->dbbuf_dbs, 0, mem_size); | |
254 | memset(dev->dbbuf_eis, 0, mem_size); | |
f9f38e33 | 255 | return 0; |
58847f12 | 256 | } |
f9f38e33 HK |
257 | |
258 | dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, | |
259 | &dev->dbbuf_dbs_dma_addr, | |
260 | GFP_KERNEL); | |
261 | if (!dev->dbbuf_dbs) | |
262 | return -ENOMEM; | |
263 | dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, | |
264 | &dev->dbbuf_eis_dma_addr, | |
265 | GFP_KERNEL); | |
266 | if (!dev->dbbuf_eis) { | |
267 | dma_free_coherent(dev->dev, mem_size, | |
268 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
269 | dev->dbbuf_dbs = NULL; | |
270 | return -ENOMEM; | |
271 | } | |
272 | ||
273 | return 0; | |
274 | } | |
275 | ||
276 | static void nvme_dbbuf_dma_free(struct nvme_dev *dev) | |
277 | { | |
2a5bcfdd | 278 | unsigned int mem_size = nvme_dbbuf_size(dev); |
f9f38e33 HK |
279 | |
280 | if (dev->dbbuf_dbs) { | |
281 | dma_free_coherent(dev->dev, mem_size, | |
282 | dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); | |
283 | dev->dbbuf_dbs = NULL; | |
284 | } | |
285 | if (dev->dbbuf_eis) { | |
286 | dma_free_coherent(dev->dev, mem_size, | |
287 | dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); | |
288 | dev->dbbuf_eis = NULL; | |
289 | } | |
290 | } | |
291 | ||
292 | static void nvme_dbbuf_init(struct nvme_dev *dev, | |
293 | struct nvme_queue *nvmeq, int qid) | |
294 | { | |
295 | if (!dev->dbbuf_dbs || !qid) | |
296 | return; | |
297 | ||
298 | nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; | |
299 | nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; | |
300 | nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; | |
301 | nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; | |
302 | } | |
303 | ||
0f0d2c87 MI |
304 | static void nvme_dbbuf_free(struct nvme_queue *nvmeq) |
305 | { | |
306 | if (!nvmeq->qid) | |
307 | return; | |
308 | ||
309 | nvmeq->dbbuf_sq_db = NULL; | |
310 | nvmeq->dbbuf_cq_db = NULL; | |
311 | nvmeq->dbbuf_sq_ei = NULL; | |
312 | nvmeq->dbbuf_cq_ei = NULL; | |
313 | } | |
314 | ||
f9f38e33 HK |
315 | static void nvme_dbbuf_set(struct nvme_dev *dev) |
316 | { | |
f66e2804 | 317 | struct nvme_command c = { }; |
0f0d2c87 | 318 | unsigned int i; |
f9f38e33 HK |
319 | |
320 | if (!dev->dbbuf_dbs) | |
321 | return; | |
322 | ||
f9f38e33 HK |
323 | c.dbbuf.opcode = nvme_admin_dbbuf; |
324 | c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); | |
325 | c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); | |
326 | ||
327 | if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { | |
9bdcfb10 | 328 | dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); |
f9f38e33 HK |
329 | /* Free memory and continue on */ |
330 | nvme_dbbuf_dma_free(dev); | |
0f0d2c87 MI |
331 | |
332 | for (i = 1; i <= dev->online_queues; i++) | |
333 | nvme_dbbuf_free(&dev->queues[i]); | |
f9f38e33 HK |
334 | } |
335 | } | |
336 | ||
337 | static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) | |
338 | { | |
339 | return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); | |
340 | } | |
341 | ||
342 | /* Update dbbuf and return true if an MMIO is required */ | |
343 | static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, | |
344 | volatile u32 *dbbuf_ei) | |
345 | { | |
346 | if (dbbuf_db) { | |
347 | u16 old_value; | |
348 | ||
349 | /* | |
350 | * Ensure that the queue is written before updating | |
351 | * the doorbell in memory | |
352 | */ | |
353 | wmb(); | |
354 | ||
355 | old_value = *dbbuf_db; | |
356 | *dbbuf_db = value; | |
357 | ||
f1ed3df2 MW |
358 | /* |
359 | * Ensure that the doorbell is updated before reading the event | |
360 | * index from memory. The controller needs to provide similar | |
361 | * ordering to ensure the envent index is updated before reading | |
362 | * the doorbell. | |
363 | */ | |
364 | mb(); | |
365 | ||
f9f38e33 HK |
366 | if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) |
367 | return false; | |
368 | } | |
369 | ||
370 | return true; | |
b60503ba MW |
371 | } |
372 | ||
ac3dd5bd JA |
373 | /* |
374 | * Will slightly overestimate the number of pages needed. This is OK | |
375 | * as it only leads to a small amount of wasted memory for the lifetime of | |
376 | * the I/O. | |
377 | */ | |
b13c6393 | 378 | static int nvme_pci_npages_prp(void) |
ac3dd5bd | 379 | { |
b13c6393 | 380 | unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, |
6c3c05b0 | 381 | NVME_CTRL_PAGE_SIZE); |
ac3dd5bd JA |
382 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
383 | } | |
384 | ||
a7a7cbe3 CK |
385 | /* |
386 | * Calculates the number of pages needed for the SGL segments. For example a 4k | |
387 | * page can accommodate 256 SGL descriptors. | |
388 | */ | |
b13c6393 | 389 | static int nvme_pci_npages_sgl(void) |
ac3dd5bd | 390 | { |
b13c6393 CK |
391 | return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), |
392 | PAGE_SIZE); | |
f4800d6d | 393 | } |
ac3dd5bd | 394 | |
b13c6393 | 395 | static size_t nvme_pci_iod_alloc_size(void) |
f4800d6d | 396 | { |
b13c6393 | 397 | size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); |
a7a7cbe3 | 398 | |
b13c6393 CK |
399 | return sizeof(__le64 *) * npages + |
400 | sizeof(struct scatterlist) * NVME_MAX_SEGS; | |
f4800d6d | 401 | } |
ac3dd5bd | 402 | |
a4aea562 MB |
403 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
404 | unsigned int hctx_idx) | |
e85248e5 | 405 | { |
a4aea562 | 406 | struct nvme_dev *dev = data; |
147b27e4 | 407 | struct nvme_queue *nvmeq = &dev->queues[0]; |
a4aea562 | 408 | |
42483228 KB |
409 | WARN_ON(hctx_idx != 0); |
410 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
42483228 | 411 | |
a4aea562 MB |
412 | hctx->driver_data = nvmeq; |
413 | return 0; | |
e85248e5 MW |
414 | } |
415 | ||
a4aea562 MB |
416 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
417 | unsigned int hctx_idx) | |
b60503ba | 418 | { |
a4aea562 | 419 | struct nvme_dev *dev = data; |
147b27e4 | 420 | struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; |
a4aea562 | 421 | |
42483228 | 422 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
423 | hctx->driver_data = nvmeq; |
424 | return 0; | |
b60503ba MW |
425 | } |
426 | ||
e559398f CH |
427 | static int nvme_pci_init_request(struct blk_mq_tag_set *set, |
428 | struct request *req, unsigned int hctx_idx, | |
429 | unsigned int numa_node) | |
b60503ba | 430 | { |
d6296d39 | 431 | struct nvme_dev *dev = set->driver_data; |
f4800d6d | 432 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
0350815a | 433 | int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; |
147b27e4 | 434 | struct nvme_queue *nvmeq = &dev->queues[queue_idx]; |
a4aea562 MB |
435 | |
436 | BUG_ON(!nvmeq); | |
f4800d6d | 437 | iod->nvmeq = nvmeq; |
59e29ce6 SG |
438 | |
439 | nvme_req(req)->ctrl = &dev->ctrl; | |
f4b9e6c9 | 440 | nvme_req(req)->cmd = &iod->cmd; |
a4aea562 MB |
441 | return 0; |
442 | } | |
443 | ||
3b6592f7 JA |
444 | static int queue_irq_offset(struct nvme_dev *dev) |
445 | { | |
446 | /* if we have more than 1 vec, admin queue offsets us by 1 */ | |
447 | if (dev->num_vecs > 1) | |
448 | return 1; | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
dca51e78 CH |
453 | static int nvme_pci_map_queues(struct blk_mq_tag_set *set) |
454 | { | |
455 | struct nvme_dev *dev = set->driver_data; | |
3b6592f7 JA |
456 | int i, qoff, offset; |
457 | ||
458 | offset = queue_irq_offset(dev); | |
459 | for (i = 0, qoff = 0; i < set->nr_maps; i++) { | |
460 | struct blk_mq_queue_map *map = &set->map[i]; | |
461 | ||
462 | map->nr_queues = dev->io_queues[i]; | |
463 | if (!map->nr_queues) { | |
e20ba6e1 | 464 | BUG_ON(i == HCTX_TYPE_DEFAULT); |
7e849dd9 | 465 | continue; |
3b6592f7 JA |
466 | } |
467 | ||
4b04cc6a JA |
468 | /* |
469 | * The poll queue(s) doesn't have an IRQ (and hence IRQ | |
470 | * affinity), so use the regular blk-mq cpu mapping | |
471 | */ | |
3b6592f7 | 472 | map->queue_offset = qoff; |
cb9e0e50 | 473 | if (i != HCTX_TYPE_POLL && offset) |
4b04cc6a JA |
474 | blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); |
475 | else | |
476 | blk_mq_map_queues(map); | |
3b6592f7 JA |
477 | qoff += map->nr_queues; |
478 | offset += map->nr_queues; | |
479 | } | |
480 | ||
481 | return 0; | |
dca51e78 CH |
482 | } |
483 | ||
38210800 KB |
484 | /* |
485 | * Write sq tail if we are asked to, or if the next command would wrap. | |
486 | */ | |
487 | static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) | |
04f3eafd | 488 | { |
38210800 KB |
489 | if (!write_sq) { |
490 | u16 next_tail = nvmeq->sq_tail + 1; | |
491 | ||
492 | if (next_tail == nvmeq->q_depth) | |
493 | next_tail = 0; | |
494 | if (next_tail != nvmeq->last_sq_tail) | |
495 | return; | |
496 | } | |
497 | ||
04f3eafd JA |
498 | if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, |
499 | nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) | |
500 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
38210800 | 501 | nvmeq->last_sq_tail = nvmeq->sq_tail; |
04f3eafd JA |
502 | } |
503 | ||
3233b94c JA |
504 | static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, |
505 | struct nvme_command *cmd) | |
b60503ba | 506 | { |
c1e0cc7e | 507 | memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), |
3233b94c | 508 | absolute_pointer(cmd), sizeof(*cmd)); |
90ea5ca4 CH |
509 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
510 | nvmeq->sq_tail = 0; | |
04f3eafd JA |
511 | } |
512 | ||
513 | static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) | |
514 | { | |
515 | struct nvme_queue *nvmeq = hctx->driver_data; | |
516 | ||
517 | spin_lock(&nvmeq->sq_lock); | |
38210800 KB |
518 | if (nvmeq->sq_tail != nvmeq->last_sq_tail) |
519 | nvme_write_sq_db(nvmeq, true); | |
90ea5ca4 | 520 | spin_unlock(&nvmeq->sq_lock); |
b60503ba MW |
521 | } |
522 | ||
a7a7cbe3 | 523 | static void **nvme_pci_iod_list(struct request *req) |
b60503ba | 524 | { |
f4800d6d | 525 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
91fb2b60 | 526 | return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); |
b60503ba MW |
527 | } |
528 | ||
955b1b5a MI |
529 | static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) |
530 | { | |
531 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
20469a37 | 532 | int nseg = blk_rq_nr_phys_segments(req); |
955b1b5a MI |
533 | unsigned int avg_seg_size; |
534 | ||
20469a37 | 535 | avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); |
955b1b5a | 536 | |
253a0b76 | 537 | if (!nvme_ctrl_sgl_supported(&dev->ctrl)) |
955b1b5a MI |
538 | return false; |
539 | if (!iod->nvmeq->qid) | |
540 | return false; | |
541 | if (!sgl_threshold || avg_seg_size < sgl_threshold) | |
542 | return false; | |
543 | return true; | |
544 | } | |
545 | ||
9275c206 | 546 | static void nvme_free_prps(struct nvme_dev *dev, struct request *req) |
b60503ba | 547 | { |
6c3c05b0 | 548 | const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; |
9275c206 CH |
549 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
550 | dma_addr_t dma_addr = iod->first_dma; | |
eca18b23 | 551 | int i; |
eca18b23 | 552 | |
9275c206 CH |
553 | for (i = 0; i < iod->npages; i++) { |
554 | __le64 *prp_list = nvme_pci_iod_list(req)[i]; | |
555 | dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); | |
556 | ||
557 | dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); | |
558 | dma_addr = next_dma_addr; | |
7fe07d14 | 559 | } |
9275c206 | 560 | } |
dff824b2 | 561 | |
9275c206 CH |
562 | static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) |
563 | { | |
564 | const int last_sg = SGES_PER_PAGE - 1; | |
565 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
566 | dma_addr_t dma_addr = iod->first_dma; | |
567 | int i; | |
dff824b2 | 568 | |
9275c206 CH |
569 | for (i = 0; i < iod->npages; i++) { |
570 | struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; | |
571 | dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); | |
dff824b2 | 572 | |
9275c206 CH |
573 | dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); |
574 | dma_addr = next_dma_addr; | |
575 | } | |
9275c206 | 576 | } |
a7a7cbe3 | 577 | |
9275c206 CH |
578 | static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) |
579 | { | |
580 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 | 581 | |
9275c206 CH |
582 | if (iod->dma_len) { |
583 | dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, | |
584 | rq_dma_dir(req)); | |
585 | return; | |
eca18b23 | 586 | } |
ac3dd5bd | 587 | |
91fb2b60 LG |
588 | WARN_ON_ONCE(!iod->sgt.nents); |
589 | ||
590 | dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); | |
9275c206 | 591 | |
9275c206 CH |
592 | if (iod->npages == 0) |
593 | dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], | |
594 | iod->first_dma); | |
595 | else if (iod->use_sgl) | |
596 | nvme_free_sgls(dev, req); | |
597 | else | |
598 | nvme_free_prps(dev, req); | |
91fb2b60 | 599 | mempool_free(iod->sgt.sgl, dev->iod_mempool); |
b4ff9c8d KB |
600 | } |
601 | ||
d0877473 KB |
602 | static void nvme_print_sgl(struct scatterlist *sgl, int nents) |
603 | { | |
604 | int i; | |
605 | struct scatterlist *sg; | |
606 | ||
607 | for_each_sg(sgl, sg, nents, i) { | |
608 | dma_addr_t phys = sg_phys(sg); | |
609 | pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " | |
610 | "dma_address:%pad dma_length:%d\n", | |
611 | i, &phys, sg->offset, sg->length, &sg_dma_address(sg), | |
612 | sg_dma_len(sg)); | |
613 | } | |
614 | } | |
615 | ||
a7a7cbe3 CK |
616 | static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, |
617 | struct request *req, struct nvme_rw_command *cmnd) | |
ff22b54f | 618 | { |
f4800d6d | 619 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
99802a7a | 620 | struct dma_pool *pool; |
b131c61d | 621 | int length = blk_rq_payload_bytes(req); |
91fb2b60 | 622 | struct scatterlist *sg = iod->sgt.sgl; |
ff22b54f MW |
623 | int dma_len = sg_dma_len(sg); |
624 | u64 dma_addr = sg_dma_address(sg); | |
6c3c05b0 | 625 | int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); |
e025344c | 626 | __le64 *prp_list; |
a7a7cbe3 | 627 | void **list = nvme_pci_iod_list(req); |
e025344c | 628 | dma_addr_t prp_dma; |
eca18b23 | 629 | int nprps, i; |
ff22b54f | 630 | |
6c3c05b0 | 631 | length -= (NVME_CTRL_PAGE_SIZE - offset); |
5228b328 JS |
632 | if (length <= 0) { |
633 | iod->first_dma = 0; | |
a7a7cbe3 | 634 | goto done; |
5228b328 | 635 | } |
ff22b54f | 636 | |
6c3c05b0 | 637 | dma_len -= (NVME_CTRL_PAGE_SIZE - offset); |
ff22b54f | 638 | if (dma_len) { |
6c3c05b0 | 639 | dma_addr += (NVME_CTRL_PAGE_SIZE - offset); |
ff22b54f MW |
640 | } else { |
641 | sg = sg_next(sg); | |
642 | dma_addr = sg_dma_address(sg); | |
643 | dma_len = sg_dma_len(sg); | |
644 | } | |
645 | ||
6c3c05b0 | 646 | if (length <= NVME_CTRL_PAGE_SIZE) { |
edd10d33 | 647 | iod->first_dma = dma_addr; |
a7a7cbe3 | 648 | goto done; |
e025344c SMM |
649 | } |
650 | ||
6c3c05b0 | 651 | nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); |
99802a7a MW |
652 | if (nprps <= (256 / 8)) { |
653 | pool = dev->prp_small_pool; | |
eca18b23 | 654 | iod->npages = 0; |
99802a7a MW |
655 | } else { |
656 | pool = dev->prp_page_pool; | |
eca18b23 | 657 | iod->npages = 1; |
99802a7a MW |
658 | } |
659 | ||
69d2b571 | 660 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
b77954cb | 661 | if (!prp_list) { |
eca18b23 | 662 | iod->npages = -1; |
86eea289 | 663 | return BLK_STS_RESOURCE; |
b77954cb | 664 | } |
eca18b23 MW |
665 | list[0] = prp_list; |
666 | iod->first_dma = prp_dma; | |
e025344c SMM |
667 | i = 0; |
668 | for (;;) { | |
6c3c05b0 | 669 | if (i == NVME_CTRL_PAGE_SIZE >> 3) { |
e025344c | 670 | __le64 *old_prp_list = prp_list; |
69d2b571 | 671 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
eca18b23 | 672 | if (!prp_list) |
fa073216 | 673 | goto free_prps; |
eca18b23 | 674 | list[iod->npages++] = prp_list; |
7523d834 MW |
675 | prp_list[0] = old_prp_list[i - 1]; |
676 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
677 | i = 1; | |
e025344c SMM |
678 | } |
679 | prp_list[i++] = cpu_to_le64(dma_addr); | |
6c3c05b0 CK |
680 | dma_len -= NVME_CTRL_PAGE_SIZE; |
681 | dma_addr += NVME_CTRL_PAGE_SIZE; | |
682 | length -= NVME_CTRL_PAGE_SIZE; | |
e025344c SMM |
683 | if (length <= 0) |
684 | break; | |
685 | if (dma_len > 0) | |
686 | continue; | |
86eea289 KB |
687 | if (unlikely(dma_len < 0)) |
688 | goto bad_sgl; | |
e025344c SMM |
689 | sg = sg_next(sg); |
690 | dma_addr = sg_dma_address(sg); | |
691 | dma_len = sg_dma_len(sg); | |
ff22b54f | 692 | } |
a7a7cbe3 | 693 | done: |
91fb2b60 | 694 | cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); |
a7a7cbe3 | 695 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); |
86eea289 | 696 | return BLK_STS_OK; |
fa073216 CH |
697 | free_prps: |
698 | nvme_free_prps(dev, req); | |
699 | return BLK_STS_RESOURCE; | |
700 | bad_sgl: | |
91fb2b60 | 701 | WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), |
d0877473 | 702 | "Invalid SGL for payload:%d nents:%d\n", |
91fb2b60 | 703 | blk_rq_payload_bytes(req), iod->sgt.nents); |
86eea289 | 704 | return BLK_STS_IOERR; |
ff22b54f MW |
705 | } |
706 | ||
a7a7cbe3 CK |
707 | static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, |
708 | struct scatterlist *sg) | |
709 | { | |
710 | sge->addr = cpu_to_le64(sg_dma_address(sg)); | |
711 | sge->length = cpu_to_le32(sg_dma_len(sg)); | |
712 | sge->type = NVME_SGL_FMT_DATA_DESC << 4; | |
713 | } | |
714 | ||
715 | static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, | |
716 | dma_addr_t dma_addr, int entries) | |
717 | { | |
718 | sge->addr = cpu_to_le64(dma_addr); | |
719 | if (entries < SGES_PER_PAGE) { | |
720 | sge->length = cpu_to_le32(entries * sizeof(*sge)); | |
721 | sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; | |
722 | } else { | |
723 | sge->length = cpu_to_le32(PAGE_SIZE); | |
724 | sge->type = NVME_SGL_FMT_SEG_DESC << 4; | |
725 | } | |
726 | } | |
727 | ||
728 | static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, | |
91fb2b60 | 729 | struct request *req, struct nvme_rw_command *cmd) |
a7a7cbe3 CK |
730 | { |
731 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
a7a7cbe3 CK |
732 | struct dma_pool *pool; |
733 | struct nvme_sgl_desc *sg_list; | |
91fb2b60 LG |
734 | struct scatterlist *sg = iod->sgt.sgl; |
735 | unsigned int entries = iod->sgt.nents; | |
a7a7cbe3 | 736 | dma_addr_t sgl_dma; |
b0f2853b | 737 | int i = 0; |
a7a7cbe3 | 738 | |
a7a7cbe3 CK |
739 | /* setting the transfer type as SGL */ |
740 | cmd->flags = NVME_CMD_SGL_METABUF; | |
741 | ||
b0f2853b | 742 | if (entries == 1) { |
a7a7cbe3 CK |
743 | nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); |
744 | return BLK_STS_OK; | |
745 | } | |
746 | ||
747 | if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { | |
748 | pool = dev->prp_small_pool; | |
749 | iod->npages = 0; | |
750 | } else { | |
751 | pool = dev->prp_page_pool; | |
752 | iod->npages = 1; | |
753 | } | |
754 | ||
755 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
756 | if (!sg_list) { | |
757 | iod->npages = -1; | |
758 | return BLK_STS_RESOURCE; | |
759 | } | |
760 | ||
761 | nvme_pci_iod_list(req)[0] = sg_list; | |
762 | iod->first_dma = sgl_dma; | |
763 | ||
764 | nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); | |
765 | ||
766 | do { | |
767 | if (i == SGES_PER_PAGE) { | |
768 | struct nvme_sgl_desc *old_sg_desc = sg_list; | |
769 | struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; | |
770 | ||
771 | sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); | |
772 | if (!sg_list) | |
fa073216 | 773 | goto free_sgls; |
a7a7cbe3 CK |
774 | |
775 | i = 0; | |
776 | nvme_pci_iod_list(req)[iod->npages++] = sg_list; | |
777 | sg_list[i++] = *link; | |
778 | nvme_pci_sgl_set_seg(link, sgl_dma, entries); | |
779 | } | |
780 | ||
781 | nvme_pci_sgl_set_data(&sg_list[i++], sg); | |
a7a7cbe3 | 782 | sg = sg_next(sg); |
b0f2853b | 783 | } while (--entries > 0); |
a7a7cbe3 | 784 | |
a7a7cbe3 | 785 | return BLK_STS_OK; |
fa073216 CH |
786 | free_sgls: |
787 | nvme_free_sgls(dev, req); | |
788 | return BLK_STS_RESOURCE; | |
a7a7cbe3 CK |
789 | } |
790 | ||
dff824b2 CH |
791 | static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, |
792 | struct request *req, struct nvme_rw_command *cmnd, | |
793 | struct bio_vec *bv) | |
794 | { | |
795 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
6c3c05b0 CK |
796 | unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); |
797 | unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; | |
dff824b2 CH |
798 | |
799 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); | |
800 | if (dma_mapping_error(dev->dev, iod->first_dma)) | |
801 | return BLK_STS_RESOURCE; | |
802 | iod->dma_len = bv->bv_len; | |
803 | ||
804 | cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); | |
805 | if (bv->bv_len > first_prp_len) | |
806 | cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); | |
359c1f88 | 807 | return BLK_STS_OK; |
dff824b2 CH |
808 | } |
809 | ||
29791057 CH |
810 | static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, |
811 | struct request *req, struct nvme_rw_command *cmnd, | |
812 | struct bio_vec *bv) | |
813 | { | |
814 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
815 | ||
816 | iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); | |
817 | if (dma_mapping_error(dev->dev, iod->first_dma)) | |
818 | return BLK_STS_RESOURCE; | |
819 | iod->dma_len = bv->bv_len; | |
820 | ||
049bf372 | 821 | cmnd->flags = NVME_CMD_SGL_METABUF; |
29791057 CH |
822 | cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); |
823 | cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); | |
824 | cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; | |
359c1f88 | 825 | return BLK_STS_OK; |
29791057 CH |
826 | } |
827 | ||
fc17b653 | 828 | static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, |
b131c61d | 829 | struct nvme_command *cmnd) |
d29ec824 | 830 | { |
f4800d6d | 831 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
70479b71 | 832 | blk_status_t ret = BLK_STS_RESOURCE; |
91fb2b60 | 833 | int rc; |
d29ec824 | 834 | |
dff824b2 CH |
835 | if (blk_rq_nr_phys_segments(req) == 1) { |
836 | struct bio_vec bv = req_bvec(req); | |
837 | ||
838 | if (!is_pci_p2pdma_page(bv.bv_page)) { | |
6c3c05b0 | 839 | if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) |
dff824b2 CH |
840 | return nvme_setup_prp_simple(dev, req, |
841 | &cmnd->rw, &bv); | |
29791057 | 842 | |
e51183be | 843 | if (iod->nvmeq->qid && sgl_threshold && |
253a0b76 | 844 | nvme_ctrl_sgl_supported(&dev->ctrl)) |
29791057 CH |
845 | return nvme_setup_sgl_simple(dev, req, |
846 | &cmnd->rw, &bv); | |
dff824b2 CH |
847 | } |
848 | } | |
849 | ||
850 | iod->dma_len = 0; | |
91fb2b60 LG |
851 | iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); |
852 | if (!iod->sgt.sgl) | |
d43f1ccf | 853 | return BLK_STS_RESOURCE; |
91fb2b60 LG |
854 | sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); |
855 | iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); | |
856 | if (!iod->sgt.orig_nents) | |
fa073216 | 857 | goto out_free_sg; |
d29ec824 | 858 | |
91fb2b60 LG |
859 | rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), |
860 | DMA_ATTR_NO_WARN); | |
861 | if (rc) { | |
862 | if (rc == -EREMOTEIO) | |
863 | ret = BLK_STS_TARGET; | |
fa073216 | 864 | goto out_free_sg; |
91fb2b60 | 865 | } |
d29ec824 | 866 | |
70479b71 | 867 | iod->use_sgl = nvme_pci_use_sgls(dev, req); |
955b1b5a | 868 | if (iod->use_sgl) |
91fb2b60 | 869 | ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); |
a7a7cbe3 CK |
870 | else |
871 | ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); | |
86eea289 | 872 | if (ret != BLK_STS_OK) |
fa073216 CH |
873 | goto out_unmap_sg; |
874 | return BLK_STS_OK; | |
875 | ||
876 | out_unmap_sg: | |
91fb2b60 | 877 | dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); |
fa073216 | 878 | out_free_sg: |
91fb2b60 | 879 | mempool_free(iod->sgt.sgl, dev->iod_mempool); |
4aedb705 CH |
880 | return ret; |
881 | } | |
3045c0d0 | 882 | |
4aedb705 CH |
883 | static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, |
884 | struct nvme_command *cmnd) | |
885 | { | |
886 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
00df5cb4 | 887 | |
4aedb705 CH |
888 | iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), |
889 | rq_dma_dir(req), 0); | |
890 | if (dma_mapping_error(dev->dev, iod->meta_dma)) | |
891 | return BLK_STS_IOERR; | |
892 | cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); | |
359c1f88 | 893 | return BLK_STS_OK; |
00df5cb4 MW |
894 | } |
895 | ||
62451a2b | 896 | static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) |
edd10d33 | 897 | { |
9b048119 | 898 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
ebe6d874 | 899 | blk_status_t ret; |
e1e5e564 | 900 | |
9b048119 CH |
901 | iod->aborted = 0; |
902 | iod->npages = -1; | |
91fb2b60 | 903 | iod->sgt.nents = 0; |
9b048119 | 904 | |
62451a2b | 905 | ret = nvme_setup_cmd(req->q->queuedata, req); |
fc17b653 | 906 | if (ret) |
f4800d6d | 907 | return ret; |
a4aea562 | 908 | |
fc17b653 | 909 | if (blk_rq_nr_phys_segments(req)) { |
62451a2b | 910 | ret = nvme_map_data(dev, req, &iod->cmd); |
fc17b653 | 911 | if (ret) |
9b048119 | 912 | goto out_free_cmd; |
fc17b653 | 913 | } |
a4aea562 | 914 | |
4aedb705 | 915 | if (blk_integrity_rq(req)) { |
62451a2b | 916 | ret = nvme_map_metadata(dev, req, &iod->cmd); |
4aedb705 CH |
917 | if (ret) |
918 | goto out_unmap_data; | |
919 | } | |
920 | ||
aae239e1 | 921 | blk_mq_start_request(req); |
fc17b653 | 922 | return BLK_STS_OK; |
4aedb705 CH |
923 | out_unmap_data: |
924 | nvme_unmap_data(dev, req); | |
f9d03f96 CH |
925 | out_free_cmd: |
926 | nvme_cleanup_cmd(req); | |
ba1ca37e | 927 | return ret; |
b60503ba | 928 | } |
e1e5e564 | 929 | |
62451a2b JA |
930 | /* |
931 | * NOTE: ns is NULL when called on the admin queue. | |
932 | */ | |
933 | static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, | |
934 | const struct blk_mq_queue_data *bd) | |
935 | { | |
936 | struct nvme_queue *nvmeq = hctx->driver_data; | |
937 | struct nvme_dev *dev = nvmeq->dev; | |
938 | struct request *req = bd->rq; | |
939 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
940 | blk_status_t ret; | |
941 | ||
942 | /* | |
943 | * We should not need to do this, but we're still using this to | |
944 | * ensure we can drain requests on a dying queue. | |
945 | */ | |
946 | if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) | |
947 | return BLK_STS_IOERR; | |
948 | ||
949 | if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) | |
950 | return nvme_fail_nonready_command(&dev->ctrl, req); | |
951 | ||
952 | ret = nvme_prep_rq(dev, req); | |
953 | if (unlikely(ret)) | |
954 | return ret; | |
955 | spin_lock(&nvmeq->sq_lock); | |
956 | nvme_sq_copy_cmd(nvmeq, &iod->cmd); | |
957 | nvme_write_sq_db(nvmeq, bd->last); | |
958 | spin_unlock(&nvmeq->sq_lock); | |
959 | return BLK_STS_OK; | |
960 | } | |
961 | ||
d62cbcf6 JA |
962 | static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) |
963 | { | |
964 | spin_lock(&nvmeq->sq_lock); | |
965 | while (!rq_list_empty(*rqlist)) { | |
966 | struct request *req = rq_list_pop(rqlist); | |
967 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); | |
968 | ||
969 | nvme_sq_copy_cmd(nvmeq, &iod->cmd); | |
970 | } | |
971 | nvme_write_sq_db(nvmeq, true); | |
972 | spin_unlock(&nvmeq->sq_lock); | |
973 | } | |
974 | ||
975 | static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) | |
976 | { | |
977 | /* | |
978 | * We should not need to do this, but we're still using this to | |
979 | * ensure we can drain requests on a dying queue. | |
980 | */ | |
981 | if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) | |
982 | return false; | |
983 | if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) | |
984 | return false; | |
985 | ||
986 | req->mq_hctx->tags->rqs[req->tag] = req; | |
987 | return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; | |
988 | } | |
989 | ||
990 | static void nvme_queue_rqs(struct request **rqlist) | |
991 | { | |
6bfec799 | 992 | struct request *req, *next, *prev = NULL; |
d62cbcf6 JA |
993 | struct request *requeue_list = NULL; |
994 | ||
6bfec799 | 995 | rq_list_for_each_safe(rqlist, req, next) { |
d62cbcf6 JA |
996 | struct nvme_queue *nvmeq = req->mq_hctx->driver_data; |
997 | ||
998 | if (!nvme_prep_rq_batch(nvmeq, req)) { | |
999 | /* detach 'req' and add to remainder list */ | |
6bfec799 KB |
1000 | rq_list_move(rqlist, &requeue_list, req, prev); |
1001 | ||
1002 | req = prev; | |
1003 | if (!req) | |
1004 | continue; | |
d62cbcf6 JA |
1005 | } |
1006 | ||
6bfec799 | 1007 | if (!next || req->mq_hctx != next->mq_hctx) { |
d62cbcf6 | 1008 | /* detach rest of list, and submit */ |
6bfec799 | 1009 | req->rq_next = NULL; |
d62cbcf6 | 1010 | nvme_submit_cmds(nvmeq, rqlist); |
6bfec799 KB |
1011 | *rqlist = next; |
1012 | prev = NULL; | |
1013 | } else | |
1014 | prev = req; | |
1015 | } | |
d62cbcf6 JA |
1016 | |
1017 | *rqlist = requeue_list; | |
1018 | } | |
1019 | ||
c234a653 | 1020 | static __always_inline void nvme_pci_unmap_rq(struct request *req) |
eee417b0 | 1021 | { |
f4800d6d | 1022 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
4aedb705 | 1023 | struct nvme_dev *dev = iod->nvmeq->dev; |
a4aea562 | 1024 | |
4aedb705 CH |
1025 | if (blk_integrity_rq(req)) |
1026 | dma_unmap_page(dev->dev, iod->meta_dma, | |
1027 | rq_integrity_vec(req)->bv_len, rq_data_dir(req)); | |
b15c592d | 1028 | if (blk_rq_nr_phys_segments(req)) |
4aedb705 | 1029 | nvme_unmap_data(dev, req); |
c234a653 JA |
1030 | } |
1031 | ||
1032 | static void nvme_pci_complete_rq(struct request *req) | |
1033 | { | |
1034 | nvme_pci_unmap_rq(req); | |
77f02a7a | 1035 | nvme_complete_rq(req); |
b60503ba MW |
1036 | } |
1037 | ||
c234a653 JA |
1038 | static void nvme_pci_complete_batch(struct io_comp_batch *iob) |
1039 | { | |
1040 | nvme_complete_batch(iob, nvme_pci_unmap_rq); | |
1041 | } | |
1042 | ||
d783e0bd | 1043 | /* We read the CQE phase first to check if the rest of the entry is valid */ |
750dde44 | 1044 | static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) |
d783e0bd | 1045 | { |
74943d45 KB |
1046 | struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; |
1047 | ||
1048 | return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; | |
d783e0bd MR |
1049 | } |
1050 | ||
eb281c82 | 1051 | static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) |
b60503ba | 1052 | { |
eb281c82 | 1053 | u16 head = nvmeq->cq_head; |
adf68f21 | 1054 | |
397c699f KB |
1055 | if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, |
1056 | nvmeq->dbbuf_cq_ei)) | |
1057 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); | |
eb281c82 | 1058 | } |
aae239e1 | 1059 | |
cfa27356 CH |
1060 | static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) |
1061 | { | |
1062 | if (!nvmeq->qid) | |
1063 | return nvmeq->dev->admin_tagset.tags[0]; | |
1064 | return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; | |
1065 | } | |
1066 | ||
c234a653 JA |
1067 | static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, |
1068 | struct io_comp_batch *iob, u16 idx) | |
83a12fb7 | 1069 | { |
74943d45 | 1070 | struct nvme_completion *cqe = &nvmeq->cqes[idx]; |
62df8016 | 1071 | __u16 command_id = READ_ONCE(cqe->command_id); |
83a12fb7 | 1072 | struct request *req; |
adf68f21 | 1073 | |
83a12fb7 SG |
1074 | /* |
1075 | * AEN requests are special as they don't time out and can | |
1076 | * survive any kind of queue freeze and often don't respond to | |
1077 | * aborts. We don't even bother to allocate a struct request | |
1078 | * for them but rather special case them here. | |
1079 | */ | |
62df8016 | 1080 | if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { |
83a12fb7 SG |
1081 | nvme_complete_async_event(&nvmeq->dev->ctrl, |
1082 | cqe->status, &cqe->result); | |
a0fa9647 | 1083 | return; |
83a12fb7 | 1084 | } |
b60503ba | 1085 | |
e7006de6 | 1086 | req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); |
50b7c243 XT |
1087 | if (unlikely(!req)) { |
1088 | dev_warn(nvmeq->dev->ctrl.device, | |
1089 | "invalid id %d completed on queue %d\n", | |
62df8016 | 1090 | command_id, le16_to_cpu(cqe->sq_id)); |
50b7c243 XT |
1091 | return; |
1092 | } | |
1093 | ||
604c01d5 | 1094 | trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); |
c234a653 JA |
1095 | if (!nvme_try_complete_req(req, cqe->status, cqe->result) && |
1096 | !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, | |
1097 | nvme_pci_complete_batch)) | |
ff029451 | 1098 | nvme_pci_complete_rq(req); |
83a12fb7 | 1099 | } |
b60503ba | 1100 | |
5cb525c8 JA |
1101 | static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) |
1102 | { | |
a0aac973 | 1103 | u32 tmp = nvmeq->cq_head + 1; |
a8de6639 AD |
1104 | |
1105 | if (tmp == nvmeq->q_depth) { | |
5cb525c8 | 1106 | nvmeq->cq_head = 0; |
e2a366a4 | 1107 | nvmeq->cq_phase ^= 1; |
a8de6639 AD |
1108 | } else { |
1109 | nvmeq->cq_head = tmp; | |
b60503ba | 1110 | } |
a0fa9647 JA |
1111 | } |
1112 | ||
c234a653 JA |
1113 | static inline int nvme_poll_cq(struct nvme_queue *nvmeq, |
1114 | struct io_comp_batch *iob) | |
a0fa9647 | 1115 | { |
1052b8ac | 1116 | int found = 0; |
b60503ba | 1117 | |
1052b8ac | 1118 | while (nvme_cqe_pending(nvmeq)) { |
bf392a5d | 1119 | found++; |
b69e2ef2 KB |
1120 | /* |
1121 | * load-load control dependency between phase and the rest of | |
1122 | * the cqe requires a full read memory barrier | |
1123 | */ | |
1124 | dma_rmb(); | |
c234a653 | 1125 | nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); |
5cb525c8 | 1126 | nvme_update_cq_head(nvmeq); |
920d13a8 | 1127 | } |
eb281c82 | 1128 | |
324b494c | 1129 | if (found) |
920d13a8 | 1130 | nvme_ring_cq_doorbell(nvmeq); |
5cb525c8 | 1131 | return found; |
b60503ba MW |
1132 | } |
1133 | ||
1134 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 | 1135 | { |
58ffacb5 | 1136 | struct nvme_queue *nvmeq = data; |
4f502245 | 1137 | DEFINE_IO_COMP_BATCH(iob); |
5cb525c8 | 1138 | |
4f502245 JA |
1139 | if (nvme_poll_cq(nvmeq, &iob)) { |
1140 | if (!rq_list_empty(iob.req_list)) | |
1141 | nvme_pci_complete_batch(&iob); | |
05fae499 | 1142 | return IRQ_HANDLED; |
4f502245 | 1143 | } |
05fae499 | 1144 | return IRQ_NONE; |
58ffacb5 MW |
1145 | } |
1146 | ||
1147 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
1148 | { | |
1149 | struct nvme_queue *nvmeq = data; | |
4e523547 | 1150 | |
750dde44 | 1151 | if (nvme_cqe_pending(nvmeq)) |
d783e0bd MR |
1152 | return IRQ_WAKE_THREAD; |
1153 | return IRQ_NONE; | |
58ffacb5 MW |
1154 | } |
1155 | ||
0b2a8a9f | 1156 | /* |
fa059b85 | 1157 | * Poll for completions for any interrupt driven queue |
0b2a8a9f CH |
1158 | * Can be called from any context. |
1159 | */ | |
fa059b85 | 1160 | static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) |
a0fa9647 | 1161 | { |
3a7afd8e | 1162 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
a0fa9647 | 1163 | |
fa059b85 | 1164 | WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); |
442e19b7 | 1165 | |
fa059b85 | 1166 | disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); |
c234a653 | 1167 | nvme_poll_cq(nvmeq, NULL); |
fa059b85 | 1168 | enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); |
a0fa9647 JA |
1169 | } |
1170 | ||
5a72e899 | 1171 | static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) |
dabcefab JA |
1172 | { |
1173 | struct nvme_queue *nvmeq = hctx->driver_data; | |
dabcefab JA |
1174 | bool found; |
1175 | ||
1176 | if (!nvme_cqe_pending(nvmeq)) | |
1177 | return 0; | |
1178 | ||
3a7afd8e | 1179 | spin_lock(&nvmeq->cq_poll_lock); |
c234a653 | 1180 | found = nvme_poll_cq(nvmeq, iob); |
3a7afd8e | 1181 | spin_unlock(&nvmeq->cq_poll_lock); |
dabcefab | 1182 | |
dabcefab JA |
1183 | return found; |
1184 | } | |
1185 | ||
ad22c355 | 1186 | static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) |
b60503ba | 1187 | { |
f866fc42 | 1188 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
147b27e4 | 1189 | struct nvme_queue *nvmeq = &dev->queues[0]; |
f66e2804 | 1190 | struct nvme_command c = { }; |
b60503ba | 1191 | |
a4aea562 | 1192 | c.common.opcode = nvme_admin_async_event; |
ad22c355 | 1193 | c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; |
3233b94c JA |
1194 | |
1195 | spin_lock(&nvmeq->sq_lock); | |
1196 | nvme_sq_copy_cmd(nvmeq, &c); | |
1197 | nvme_write_sq_db(nvmeq, true); | |
1198 | spin_unlock(&nvmeq->sq_lock); | |
f705f837 CH |
1199 | } |
1200 | ||
b60503ba | 1201 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
f705f837 | 1202 | { |
f66e2804 | 1203 | struct nvme_command c = { }; |
b60503ba | 1204 | |
b60503ba MW |
1205 | c.delete_queue.opcode = opcode; |
1206 | c.delete_queue.qid = cpu_to_le16(id); | |
1207 | ||
1c63dc66 | 1208 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1209 | } |
1210 | ||
b60503ba | 1211 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, |
a8e3e0bb | 1212 | struct nvme_queue *nvmeq, s16 vector) |
b60503ba | 1213 | { |
f66e2804 | 1214 | struct nvme_command c = { }; |
4b04cc6a JA |
1215 | int flags = NVME_QUEUE_PHYS_CONTIG; |
1216 | ||
7c349dde | 1217 | if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
4b04cc6a | 1218 | flags |= NVME_CQ_IRQ_ENABLED; |
b60503ba | 1219 | |
d29ec824 | 1220 | /* |
16772ae6 | 1221 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1222 | * is attached to the request. |
1223 | */ | |
b60503ba MW |
1224 | c.create_cq.opcode = nvme_admin_create_cq; |
1225 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1226 | c.create_cq.cqid = cpu_to_le16(qid); | |
1227 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1228 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
7c349dde | 1229 | c.create_cq.irq_vector = cpu_to_le16(vector); |
b60503ba | 1230 | |
1c63dc66 | 1231 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1232 | } |
1233 | ||
1234 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1235 | struct nvme_queue *nvmeq) | |
1236 | { | |
9abd68ef | 1237 | struct nvme_ctrl *ctrl = &dev->ctrl; |
f66e2804 | 1238 | struct nvme_command c = { }; |
81c1cd98 | 1239 | int flags = NVME_QUEUE_PHYS_CONTIG; |
b60503ba | 1240 | |
9abd68ef JA |
1241 | /* |
1242 | * Some drives have a bug that auto-enables WRRU if MEDIUM isn't | |
1243 | * set. Since URGENT priority is zeroes, it makes all queues | |
1244 | * URGENT. | |
1245 | */ | |
1246 | if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) | |
1247 | flags |= NVME_SQ_PRIO_MEDIUM; | |
1248 | ||
d29ec824 | 1249 | /* |
16772ae6 | 1250 | * Note: we (ab)use the fact that the prp fields survive if no data |
d29ec824 CH |
1251 | * is attached to the request. |
1252 | */ | |
b60503ba MW |
1253 | c.create_sq.opcode = nvme_admin_create_sq; |
1254 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1255 | c.create_sq.sqid = cpu_to_le16(qid); | |
1256 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1257 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1258 | c.create_sq.cqid = cpu_to_le16(qid); | |
1259 | ||
1c63dc66 | 1260 | return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); |
b60503ba MW |
1261 | } |
1262 | ||
1263 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1264 | { | |
1265 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1266 | } | |
1267 | ||
1268 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1269 | { | |
1270 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1271 | } | |
1272 | ||
2a842aca | 1273 | static void abort_endio(struct request *req, blk_status_t error) |
bc5fc7e4 | 1274 | { |
f4800d6d CH |
1275 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1276 | struct nvme_queue *nvmeq = iod->nvmeq; | |
e44ac588 | 1277 | |
27fa9bc5 CH |
1278 | dev_warn(nvmeq->dev->ctrl.device, |
1279 | "Abort status: 0x%x", nvme_req(req)->status); | |
e7a2a87d | 1280 | atomic_inc(&nvmeq->dev->ctrl.abort_limit); |
e7a2a87d | 1281 | blk_mq_free_request(req); |
bc5fc7e4 MW |
1282 | } |
1283 | ||
b2a0eb1a KB |
1284 | static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) |
1285 | { | |
b2a0eb1a KB |
1286 | /* If true, indicates loss of adapter communication, possibly by a |
1287 | * NVMe Subsystem reset. | |
1288 | */ | |
1289 | bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); | |
1290 | ||
ad70062c JW |
1291 | /* If there is a reset/reinit ongoing, we shouldn't reset again. */ |
1292 | switch (dev->ctrl.state) { | |
1293 | case NVME_CTRL_RESETTING: | |
ad6a0a52 | 1294 | case NVME_CTRL_CONNECTING: |
b2a0eb1a | 1295 | return false; |
ad70062c JW |
1296 | default: |
1297 | break; | |
1298 | } | |
b2a0eb1a KB |
1299 | |
1300 | /* We shouldn't reset unless the controller is on fatal error state | |
1301 | * _or_ if we lost the communication with it. | |
1302 | */ | |
1303 | if (!(csts & NVME_CSTS_CFS) && !nssro) | |
1304 | return false; | |
1305 | ||
b2a0eb1a KB |
1306 | return true; |
1307 | } | |
1308 | ||
1309 | static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) | |
1310 | { | |
1311 | /* Read a config register to help see what died. */ | |
1312 | u16 pci_status; | |
1313 | int result; | |
1314 | ||
1315 | result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, | |
1316 | &pci_status); | |
1317 | if (result == PCIBIOS_SUCCESSFUL) | |
1318 | dev_warn(dev->ctrl.device, | |
1319 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", | |
1320 | csts, pci_status); | |
1321 | else | |
1322 | dev_warn(dev->ctrl.device, | |
1323 | "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", | |
1324 | csts, result); | |
4641a8e6 KB |
1325 | |
1326 | if (csts != ~0) | |
1327 | return; | |
1328 | ||
1329 | dev_warn(dev->ctrl.device, | |
1330 | "Does your device have a faulty power saving mode enabled?\n"); | |
1331 | dev_warn(dev->ctrl.device, | |
1332 | "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); | |
b2a0eb1a KB |
1333 | } |
1334 | ||
9bdb4833 | 1335 | static enum blk_eh_timer_return nvme_timeout(struct request *req) |
c30341dc | 1336 | { |
f4800d6d CH |
1337 | struct nvme_iod *iod = blk_mq_rq_to_pdu(req); |
1338 | struct nvme_queue *nvmeq = iod->nvmeq; | |
c30341dc | 1339 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 | 1340 | struct request *abort_req; |
f66e2804 | 1341 | struct nvme_command cmd = { }; |
b2a0eb1a KB |
1342 | u32 csts = readl(dev->bar + NVME_REG_CSTS); |
1343 | ||
651438bb WX |
1344 | /* If PCI error recovery process is happening, we cannot reset or |
1345 | * the recovery mechanism will surely fail. | |
1346 | */ | |
1347 | mb(); | |
1348 | if (pci_channel_offline(to_pci_dev(dev->dev))) | |
1349 | return BLK_EH_RESET_TIMER; | |
1350 | ||
b2a0eb1a KB |
1351 | /* |
1352 | * Reset immediately if the controller is failed | |
1353 | */ | |
1354 | if (nvme_should_reset(dev, csts)) { | |
1355 | nvme_warn_reset(dev, csts); | |
1356 | nvme_dev_disable(dev, false); | |
d86c4d8e | 1357 | nvme_reset_ctrl(&dev->ctrl); |
db8c48e4 | 1358 | return BLK_EH_DONE; |
b2a0eb1a | 1359 | } |
c30341dc | 1360 | |
7776db1c KB |
1361 | /* |
1362 | * Did we miss an interrupt? | |
1363 | */ | |
fa059b85 | 1364 | if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) |
5a72e899 | 1365 | nvme_poll(req->mq_hctx, NULL); |
fa059b85 KB |
1366 | else |
1367 | nvme_poll_irqdisable(nvmeq); | |
1368 | ||
bf392a5d | 1369 | if (blk_mq_request_completed(req)) { |
7776db1c KB |
1370 | dev_warn(dev->ctrl.device, |
1371 | "I/O %d QID %d timeout, completion polled\n", | |
1372 | req->tag, nvmeq->qid); | |
db8c48e4 | 1373 | return BLK_EH_DONE; |
7776db1c KB |
1374 | } |
1375 | ||
31c7c7d2 | 1376 | /* |
fd634f41 CH |
1377 | * Shutdown immediately if controller times out while starting. The |
1378 | * reset work will see the pci device disabled when it gets the forced | |
1379 | * cancellation error. All outstanding requests are completed on | |
db8c48e4 | 1380 | * shutdown, so we return BLK_EH_DONE. |
fd634f41 | 1381 | */ |
4244140d KB |
1382 | switch (dev->ctrl.state) { |
1383 | case NVME_CTRL_CONNECTING: | |
2036f726 | 1384 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
df561f66 | 1385 | fallthrough; |
2036f726 | 1386 | case NVME_CTRL_DELETING: |
b9cac43c | 1387 | dev_warn_ratelimited(dev->ctrl.device, |
fd634f41 CH |
1388 | "I/O %d QID %d timeout, disable controller\n", |
1389 | req->tag, nvmeq->qid); | |
27fa9bc5 | 1390 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
7ad92f65 | 1391 | nvme_dev_disable(dev, true); |
db8c48e4 | 1392 | return BLK_EH_DONE; |
39a9dd81 KB |
1393 | case NVME_CTRL_RESETTING: |
1394 | return BLK_EH_RESET_TIMER; | |
4244140d KB |
1395 | default: |
1396 | break; | |
c30341dc KB |
1397 | } |
1398 | ||
fd634f41 | 1399 | /* |
ee0d96d3 BW |
1400 | * Shutdown the controller immediately and schedule a reset if the |
1401 | * command was already aborted once before and still hasn't been | |
1402 | * returned to the driver, or if this is the admin queue. | |
31c7c7d2 | 1403 | */ |
f4800d6d | 1404 | if (!nvmeq->qid || iod->aborted) { |
1b3c47c1 | 1405 | dev_warn(dev->ctrl.device, |
e1569a16 KB |
1406 | "I/O %d QID %d timeout, reset controller\n", |
1407 | req->tag, nvmeq->qid); | |
7ad92f65 | 1408 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
a5cdb68c | 1409 | nvme_dev_disable(dev, false); |
d86c4d8e | 1410 | nvme_reset_ctrl(&dev->ctrl); |
c30341dc | 1411 | |
db8c48e4 | 1412 | return BLK_EH_DONE; |
c30341dc | 1413 | } |
c30341dc | 1414 | |
e7a2a87d | 1415 | if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { |
6bf25d16 | 1416 | atomic_inc(&dev->ctrl.abort_limit); |
31c7c7d2 | 1417 | return BLK_EH_RESET_TIMER; |
6bf25d16 | 1418 | } |
7bf7d778 | 1419 | iod->aborted = 1; |
a4aea562 | 1420 | |
c30341dc | 1421 | cmd.abort.opcode = nvme_admin_abort_cmd; |
85f74acf | 1422 | cmd.abort.cid = nvme_cid(req); |
c30341dc | 1423 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
c30341dc | 1424 | |
1b3c47c1 | 1425 | dev_warn(nvmeq->dev->ctrl.device, |
86141440 CH |
1426 | "I/O %d (%s) QID %d timeout, aborting\n", |
1427 | req->tag, | |
1428 | nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), | |
1429 | nvmeq->qid); | |
e7a2a87d | 1430 | |
e559398f CH |
1431 | abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), |
1432 | BLK_MQ_REQ_NOWAIT); | |
e7a2a87d CH |
1433 | if (IS_ERR(abort_req)) { |
1434 | atomic_inc(&dev->ctrl.abort_limit); | |
1435 | return BLK_EH_RESET_TIMER; | |
1436 | } | |
e559398f | 1437 | nvme_init_request(abort_req, &cmd); |
e7a2a87d | 1438 | |
e2e53086 | 1439 | abort_req->end_io = abort_endio; |
e7a2a87d | 1440 | abort_req->end_io_data = NULL; |
128126a7 | 1441 | abort_req->rq_flags |= RQF_QUIET; |
e2e53086 | 1442 | blk_execute_rq_nowait(abort_req, false); |
c30341dc | 1443 | |
31c7c7d2 CH |
1444 | /* |
1445 | * The aborted req will be completed on receiving the abort req. | |
1446 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1447 | * as the device then is in a faulty state. | |
1448 | */ | |
1449 | return BLK_EH_RESET_TIMER; | |
c30341dc KB |
1450 | } |
1451 | ||
a4aea562 MB |
1452 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1453 | { | |
8a1d09a6 | 1454 | dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), |
9e866774 | 1455 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); |
63223078 CH |
1456 | if (!nvmeq->sq_cmds) |
1457 | return; | |
0f238ff5 | 1458 | |
63223078 | 1459 | if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { |
88a041f4 | 1460 | pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), |
8a1d09a6 | 1461 | nvmeq->sq_cmds, SQ_SIZE(nvmeq)); |
63223078 | 1462 | } else { |
8a1d09a6 | 1463 | dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), |
63223078 | 1464 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); |
0f238ff5 | 1465 | } |
9e866774 MW |
1466 | } |
1467 | ||
a1a5ef99 | 1468 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1469 | { |
1470 | int i; | |
1471 | ||
d858e5f0 | 1472 | for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { |
d858e5f0 | 1473 | dev->ctrl.queue_count--; |
147b27e4 | 1474 | nvme_free_queue(&dev->queues[i]); |
121c7ad4 | 1475 | } |
22404274 KB |
1476 | } |
1477 | ||
4d115420 KB |
1478 | /** |
1479 | * nvme_suspend_queue - put queue into suspended state | |
40581d1a | 1480 | * @nvmeq: queue to suspend |
4d115420 KB |
1481 | */ |
1482 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1483 | { |
4e224106 | 1484 | if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) |
2b25d981 | 1485 | return 1; |
a09115b2 | 1486 | |
4e224106 | 1487 | /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ |
d1f06f4a | 1488 | mb(); |
a09115b2 | 1489 | |
4e224106 | 1490 | nvmeq->dev->online_queues--; |
1c63dc66 | 1491 | if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) |
6ca1d902 | 1492 | nvme_stop_admin_queue(&nvmeq->dev->ctrl); |
7c349dde KB |
1493 | if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) |
1494 | pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); | |
4d115420 KB |
1495 | return 0; |
1496 | } | |
b60503ba | 1497 | |
8fae268b KB |
1498 | static void nvme_suspend_io_queues(struct nvme_dev *dev) |
1499 | { | |
1500 | int i; | |
1501 | ||
1502 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) | |
1503 | nvme_suspend_queue(&dev->queues[i]); | |
1504 | } | |
1505 | ||
a5cdb68c | 1506 | static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) |
4d115420 | 1507 | { |
147b27e4 | 1508 | struct nvme_queue *nvmeq = &dev->queues[0]; |
4d115420 | 1509 | |
a5cdb68c KB |
1510 | if (shutdown) |
1511 | nvme_shutdown_ctrl(&dev->ctrl); | |
1512 | else | |
b5b05048 | 1513 | nvme_disable_ctrl(&dev->ctrl); |
07836e65 | 1514 | |
bf392a5d | 1515 | nvme_poll_irqdisable(nvmeq); |
b60503ba MW |
1516 | } |
1517 | ||
fa46c6fb KB |
1518 | /* |
1519 | * Called only on a device that has been disabled and after all other threads | |
9210c075 DZ |
1520 | * that can check this device's completion queues have synced, except |
1521 | * nvme_poll(). This is the last chance for the driver to see a natural | |
1522 | * completion before nvme_cancel_request() terminates all incomplete requests. | |
fa46c6fb KB |
1523 | */ |
1524 | static void nvme_reap_pending_cqes(struct nvme_dev *dev) | |
1525 | { | |
fa46c6fb KB |
1526 | int i; |
1527 | ||
9210c075 DZ |
1528 | for (i = dev->ctrl.queue_count - 1; i > 0; i--) { |
1529 | spin_lock(&dev->queues[i].cq_poll_lock); | |
c234a653 | 1530 | nvme_poll_cq(&dev->queues[i], NULL); |
9210c075 DZ |
1531 | spin_unlock(&dev->queues[i].cq_poll_lock); |
1532 | } | |
fa46c6fb KB |
1533 | } |
1534 | ||
8ffaadf7 JD |
1535 | static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, |
1536 | int entry_size) | |
1537 | { | |
1538 | int q_depth = dev->q_depth; | |
5fd4ce1b | 1539 | unsigned q_size_aligned = roundup(q_depth * entry_size, |
6c3c05b0 | 1540 | NVME_CTRL_PAGE_SIZE); |
8ffaadf7 JD |
1541 | |
1542 | if (q_size_aligned * nr_io_queues > dev->cmb_size) { | |
c45f5c99 | 1543 | u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); |
4e523547 | 1544 | |
6c3c05b0 | 1545 | mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); |
c45f5c99 | 1546 | q_depth = div_u64(mem_per_q, entry_size); |
8ffaadf7 JD |
1547 | |
1548 | /* | |
1549 | * Ensure the reduced q_depth is above some threshold where it | |
1550 | * would be better to map queues in system memory with the | |
1551 | * original depth | |
1552 | */ | |
1553 | if (q_depth < 64) | |
1554 | return -ENOMEM; | |
1555 | } | |
1556 | ||
1557 | return q_depth; | |
1558 | } | |
1559 | ||
1560 | static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, | |
8a1d09a6 | 1561 | int qid) |
8ffaadf7 | 1562 | { |
0f238ff5 LG |
1563 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
1564 | ||
1565 | if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { | |
8a1d09a6 | 1566 | nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); |
bfac8e9f AM |
1567 | if (nvmeq->sq_cmds) { |
1568 | nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, | |
1569 | nvmeq->sq_cmds); | |
1570 | if (nvmeq->sq_dma_addr) { | |
1571 | set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); | |
1572 | return 0; | |
1573 | } | |
1574 | ||
8a1d09a6 | 1575 | pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); |
63223078 | 1576 | } |
0f238ff5 | 1577 | } |
8ffaadf7 | 1578 | |
8a1d09a6 | 1579 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), |
63223078 | 1580 | &nvmeq->sq_dma_addr, GFP_KERNEL); |
815c6704 KB |
1581 | if (!nvmeq->sq_cmds) |
1582 | return -ENOMEM; | |
8ffaadf7 JD |
1583 | return 0; |
1584 | } | |
1585 | ||
a6ff7262 | 1586 | static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) |
b60503ba | 1587 | { |
147b27e4 | 1588 | struct nvme_queue *nvmeq = &dev->queues[qid]; |
b60503ba | 1589 | |
62314e40 KB |
1590 | if (dev->ctrl.queue_count > qid) |
1591 | return 0; | |
b60503ba | 1592 | |
c1e0cc7e | 1593 | nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; |
8a1d09a6 BH |
1594 | nvmeq->q_depth = depth; |
1595 | nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), | |
750afb08 | 1596 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1597 | if (!nvmeq->cqes) |
1598 | goto free_nvmeq; | |
b60503ba | 1599 | |
8a1d09a6 | 1600 | if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) |
b60503ba MW |
1601 | goto free_cqdma; |
1602 | ||
091b6092 | 1603 | nvmeq->dev = dev; |
1ab0cd69 | 1604 | spin_lock_init(&nvmeq->sq_lock); |
3a7afd8e | 1605 | spin_lock_init(&nvmeq->cq_poll_lock); |
b60503ba | 1606 | nvmeq->cq_head = 0; |
82123460 | 1607 | nvmeq->cq_phase = 1; |
b80d5ccc | 1608 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
c30341dc | 1609 | nvmeq->qid = qid; |
d858e5f0 | 1610 | dev->ctrl.queue_count++; |
36a7e993 | 1611 | |
147b27e4 | 1612 | return 0; |
b60503ba MW |
1613 | |
1614 | free_cqdma: | |
8a1d09a6 BH |
1615 | dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, |
1616 | nvmeq->cq_dma_addr); | |
b60503ba | 1617 | free_nvmeq: |
147b27e4 | 1618 | return -ENOMEM; |
b60503ba MW |
1619 | } |
1620 | ||
dca51e78 | 1621 | static int queue_request_irq(struct nvme_queue *nvmeq) |
3001082c | 1622 | { |
0ff199cb CH |
1623 | struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); |
1624 | int nr = nvmeq->dev->ctrl.instance; | |
1625 | ||
1626 | if (use_threaded_interrupts) { | |
1627 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, | |
1628 | nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1629 | } else { | |
1630 | return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, | |
1631 | NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); | |
1632 | } | |
3001082c MW |
1633 | } |
1634 | ||
22404274 | 1635 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1636 | { |
22404274 | 1637 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1638 | |
22404274 | 1639 | nvmeq->sq_tail = 0; |
38210800 | 1640 | nvmeq->last_sq_tail = 0; |
22404274 KB |
1641 | nvmeq->cq_head = 0; |
1642 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1643 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
8a1d09a6 | 1644 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); |
f9f38e33 | 1645 | nvme_dbbuf_init(dev, nvmeq, qid); |
42f61420 | 1646 | dev->online_queues++; |
3a7afd8e | 1647 | wmb(); /* ensure the first interrupt sees the initialization */ |
22404274 KB |
1648 | } |
1649 | ||
e4b9852a CC |
1650 | /* |
1651 | * Try getting shutdown_lock while setting up IO queues. | |
1652 | */ | |
1653 | static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) | |
1654 | { | |
1655 | /* | |
1656 | * Give up if the lock is being held by nvme_dev_disable. | |
1657 | */ | |
1658 | if (!mutex_trylock(&dev->shutdown_lock)) | |
1659 | return -ENODEV; | |
1660 | ||
1661 | /* | |
1662 | * Controller is in wrong state, fail early. | |
1663 | */ | |
1664 | if (dev->ctrl.state != NVME_CTRL_CONNECTING) { | |
1665 | mutex_unlock(&dev->shutdown_lock); | |
1666 | return -ENODEV; | |
1667 | } | |
1668 | ||
1669 | return 0; | |
1670 | } | |
1671 | ||
4b04cc6a | 1672 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) |
22404274 KB |
1673 | { |
1674 | struct nvme_dev *dev = nvmeq->dev; | |
1675 | int result; | |
7c349dde | 1676 | u16 vector = 0; |
3f85d50b | 1677 | |
d1ed6aa1 CH |
1678 | clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); |
1679 | ||
22b55601 KB |
1680 | /* |
1681 | * A queue's vector matches the queue identifier unless the controller | |
1682 | * has only one vector available. | |
1683 | */ | |
4b04cc6a JA |
1684 | if (!polled) |
1685 | vector = dev->num_vecs == 1 ? 0 : qid; | |
1686 | else | |
7c349dde | 1687 | set_bit(NVMEQ_POLLED, &nvmeq->flags); |
4b04cc6a | 1688 | |
a8e3e0bb | 1689 | result = adapter_alloc_cq(dev, qid, nvmeq, vector); |
ded45505 KB |
1690 | if (result) |
1691 | return result; | |
b60503ba MW |
1692 | |
1693 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1694 | if (result < 0) | |
ded45505 | 1695 | return result; |
c80b36cd | 1696 | if (result) |
b60503ba MW |
1697 | goto release_cq; |
1698 | ||
a8e3e0bb | 1699 | nvmeq->cq_vector = vector; |
4b04cc6a | 1700 | |
e4b9852a CC |
1701 | result = nvme_setup_io_queues_trylock(dev); |
1702 | if (result) | |
1703 | return result; | |
1704 | nvme_init_queue(nvmeq, qid); | |
7c349dde | 1705 | if (!polled) { |
4b04cc6a JA |
1706 | result = queue_request_irq(nvmeq); |
1707 | if (result < 0) | |
1708 | goto release_sq; | |
1709 | } | |
b60503ba | 1710 | |
4e224106 | 1711 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
e4b9852a | 1712 | mutex_unlock(&dev->shutdown_lock); |
22404274 | 1713 | return result; |
b60503ba | 1714 | |
a8e3e0bb | 1715 | release_sq: |
f25a2dfc | 1716 | dev->online_queues--; |
e4b9852a | 1717 | mutex_unlock(&dev->shutdown_lock); |
b60503ba | 1718 | adapter_delete_sq(dev, qid); |
a8e3e0bb | 1719 | release_cq: |
b60503ba | 1720 | adapter_delete_cq(dev, qid); |
22404274 | 1721 | return result; |
b60503ba MW |
1722 | } |
1723 | ||
f363b089 | 1724 | static const struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1725 | .queue_rq = nvme_queue_rq, |
77f02a7a | 1726 | .complete = nvme_pci_complete_rq, |
a4aea562 | 1727 | .init_hctx = nvme_admin_init_hctx, |
e559398f | 1728 | .init_request = nvme_pci_init_request, |
a4aea562 MB |
1729 | .timeout = nvme_timeout, |
1730 | }; | |
1731 | ||
f363b089 | 1732 | static const struct blk_mq_ops nvme_mq_ops = { |
376f7ef8 | 1733 | .queue_rq = nvme_queue_rq, |
d62cbcf6 | 1734 | .queue_rqs = nvme_queue_rqs, |
376f7ef8 CH |
1735 | .complete = nvme_pci_complete_rq, |
1736 | .commit_rqs = nvme_commit_rqs, | |
1737 | .init_hctx = nvme_init_hctx, | |
e559398f | 1738 | .init_request = nvme_pci_init_request, |
376f7ef8 CH |
1739 | .map_queues = nvme_pci_map_queues, |
1740 | .timeout = nvme_timeout, | |
1741 | .poll = nvme_poll, | |
dabcefab JA |
1742 | }; |
1743 | ||
ea191d2f KB |
1744 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1745 | { | |
1c63dc66 | 1746 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { |
69d9a99c KB |
1747 | /* |
1748 | * If the controller was reset during removal, it's possible | |
1749 | * user requests may be waiting on a stopped queue. Start the | |
1750 | * queue to flush these to completion. | |
1751 | */ | |
6ca1d902 | 1752 | nvme_start_admin_queue(&dev->ctrl); |
6f8191fd | 1753 | blk_mq_destroy_queue(dev->ctrl.admin_q); |
ea191d2f KB |
1754 | blk_mq_free_tag_set(&dev->admin_tagset); |
1755 | } | |
1756 | } | |
1757 | ||
f91b727c | 1758 | static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) |
a4aea562 | 1759 | { |
f91b727c | 1760 | struct blk_mq_tag_set *set = &dev->admin_tagset; |
e3e9d50c | 1761 | |
f91b727c CH |
1762 | set->ops = &nvme_mq_admin_ops; |
1763 | set->nr_hw_queues = 1; | |
a4aea562 | 1764 | |
f91b727c CH |
1765 | set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; |
1766 | set->timeout = NVME_ADMIN_TIMEOUT; | |
1767 | set->numa_node = dev->ctrl.numa_node; | |
1768 | set->cmd_size = sizeof(struct nvme_iod); | |
1769 | set->flags = BLK_MQ_F_NO_SCHED; | |
1770 | set->driver_data = dev; | |
a4aea562 | 1771 | |
f91b727c CH |
1772 | if (blk_mq_alloc_tag_set(set)) |
1773 | return -ENOMEM; | |
1774 | dev->ctrl.admin_tagset = set; | |
a4aea562 | 1775 | |
f91b727c CH |
1776 | dev->ctrl.admin_q = blk_mq_init_queue(set); |
1777 | if (IS_ERR(dev->ctrl.admin_q)) { | |
1778 | blk_mq_free_tag_set(set); | |
1779 | dev->ctrl.admin_q = NULL; | |
1780 | return -ENOMEM; | |
1781 | } | |
1782 | if (!blk_get_queue(dev->ctrl.admin_q)) { | |
1783 | nvme_dev_remove_admin(dev); | |
1784 | dev->ctrl.admin_q = NULL; | |
1785 | return -ENODEV; | |
1786 | } | |
a4aea562 MB |
1787 | return 0; |
1788 | } | |
1789 | ||
97f6ef64 XY |
1790 | static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
1791 | { | |
1792 | return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); | |
1793 | } | |
1794 | ||
1795 | static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) | |
1796 | { | |
1797 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
1798 | ||
1799 | if (size <= dev->bar_mapped_size) | |
1800 | return 0; | |
1801 | if (size > pci_resource_len(pdev, 0)) | |
1802 | return -ENOMEM; | |
1803 | if (dev->bar) | |
1804 | iounmap(dev->bar); | |
1805 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
1806 | if (!dev->bar) { | |
1807 | dev->bar_mapped_size = 0; | |
1808 | return -ENOMEM; | |
1809 | } | |
1810 | dev->bar_mapped_size = size; | |
1811 | dev->dbs = dev->bar + NVME_REG_DBS; | |
1812 | ||
1813 | return 0; | |
1814 | } | |
1815 | ||
01ad0990 | 1816 | static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1817 | { |
ba47e386 | 1818 | int result; |
b60503ba MW |
1819 | u32 aqa; |
1820 | struct nvme_queue *nvmeq; | |
1821 | ||
97f6ef64 XY |
1822 | result = nvme_remap_bar(dev, db_bar_size(dev, 0)); |
1823 | if (result < 0) | |
1824 | return result; | |
1825 | ||
8ef2074d | 1826 | dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? |
20d0dfe6 | 1827 | NVME_CAP_NSSRC(dev->ctrl.cap) : 0; |
dfbac8c7 | 1828 | |
7a67cbea CH |
1829 | if (dev->subsystem && |
1830 | (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) | |
1831 | writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); | |
dfbac8c7 | 1832 | |
b5b05048 | 1833 | result = nvme_disable_ctrl(&dev->ctrl); |
ba47e386 MW |
1834 | if (result < 0) |
1835 | return result; | |
b60503ba | 1836 | |
a6ff7262 | 1837 | result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
147b27e4 SG |
1838 | if (result) |
1839 | return result; | |
b60503ba | 1840 | |
635333e4 MG |
1841 | dev->ctrl.numa_node = dev_to_node(dev->dev); |
1842 | ||
147b27e4 | 1843 | nvmeq = &dev->queues[0]; |
b60503ba MW |
1844 | aqa = nvmeq->q_depth - 1; |
1845 | aqa |= aqa << 16; | |
1846 | ||
7a67cbea CH |
1847 | writel(aqa, dev->bar + NVME_REG_AQA); |
1848 | lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); | |
1849 | lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); | |
b60503ba | 1850 | |
c0f2f45b | 1851 | result = nvme_enable_ctrl(&dev->ctrl); |
025c557a | 1852 | if (result) |
d4875622 | 1853 | return result; |
a4aea562 | 1854 | |
2b25d981 | 1855 | nvmeq->cq_vector = 0; |
161b8be2 | 1856 | nvme_init_queue(nvmeq, 0); |
dca51e78 | 1857 | result = queue_request_irq(nvmeq); |
758dd7fd | 1858 | if (result) { |
7c349dde | 1859 | dev->online_queues--; |
d4875622 | 1860 | return result; |
758dd7fd | 1861 | } |
025c557a | 1862 | |
4e224106 | 1863 | set_bit(NVMEQ_ENABLED, &nvmeq->flags); |
b60503ba MW |
1864 | return result; |
1865 | } | |
1866 | ||
749941f2 | 1867 | static int nvme_create_io_queues(struct nvme_dev *dev) |
42f61420 | 1868 | { |
4b04cc6a | 1869 | unsigned i, max, rw_queues; |
749941f2 | 1870 | int ret = 0; |
42f61420 | 1871 | |
d858e5f0 | 1872 | for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { |
a6ff7262 | 1873 | if (nvme_alloc_queue(dev, i, dev->q_depth)) { |
749941f2 | 1874 | ret = -ENOMEM; |
42f61420 | 1875 | break; |
749941f2 CH |
1876 | } |
1877 | } | |
42f61420 | 1878 | |
d858e5f0 | 1879 | max = min(dev->max_qid, dev->ctrl.queue_count - 1); |
e20ba6e1 CH |
1880 | if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { |
1881 | rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + | |
1882 | dev->io_queues[HCTX_TYPE_READ]; | |
4b04cc6a JA |
1883 | } else { |
1884 | rw_queues = max; | |
1885 | } | |
1886 | ||
949928c1 | 1887 | for (i = dev->online_queues; i <= max; i++) { |
4b04cc6a JA |
1888 | bool polled = i > rw_queues; |
1889 | ||
1890 | ret = nvme_create_queue(&dev->queues[i], i, polled); | |
d4875622 | 1891 | if (ret) |
42f61420 | 1892 | break; |
27e8166c | 1893 | } |
749941f2 CH |
1894 | |
1895 | /* | |
1896 | * Ignore failing Create SQ/CQ commands, we can continue with less | |
8adb8c14 MI |
1897 | * than the desired amount of queues, and even a controller without |
1898 | * I/O queues can still be used to issue admin commands. This might | |
749941f2 CH |
1899 | * be useful to upgrade a buggy firmware for example. |
1900 | */ | |
1901 | return ret >= 0 ? 0 : ret; | |
b60503ba MW |
1902 | } |
1903 | ||
88de4598 | 1904 | static u64 nvme_cmb_size_unit(struct nvme_dev *dev) |
8ffaadf7 | 1905 | { |
88de4598 CH |
1906 | u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; |
1907 | ||
1908 | return 1ULL << (12 + 4 * szu); | |
1909 | } | |
1910 | ||
1911 | static u32 nvme_cmb_size(struct nvme_dev *dev) | |
1912 | { | |
1913 | return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; | |
1914 | } | |
1915 | ||
f65efd6d | 1916 | static void nvme_map_cmb(struct nvme_dev *dev) |
8ffaadf7 | 1917 | { |
88de4598 | 1918 | u64 size, offset; |
8ffaadf7 JD |
1919 | resource_size_t bar_size; |
1920 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
8969f1f8 | 1921 | int bar; |
8ffaadf7 | 1922 | |
9fe5c59f KB |
1923 | if (dev->cmb_size) |
1924 | return; | |
1925 | ||
20d3bb92 KJ |
1926 | if (NVME_CAP_CMBS(dev->ctrl.cap)) |
1927 | writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); | |
1928 | ||
7a67cbea | 1929 | dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); |
f65efd6d CH |
1930 | if (!dev->cmbsz) |
1931 | return; | |
202021c1 | 1932 | dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); |
8ffaadf7 | 1933 | |
88de4598 CH |
1934 | size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); |
1935 | offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); | |
8969f1f8 CH |
1936 | bar = NVME_CMB_BIR(dev->cmbloc); |
1937 | bar_size = pci_resource_len(pdev, bar); | |
8ffaadf7 JD |
1938 | |
1939 | if (offset > bar_size) | |
f65efd6d | 1940 | return; |
8ffaadf7 | 1941 | |
20d3bb92 KJ |
1942 | /* |
1943 | * Tell the controller about the host side address mapping the CMB, | |
1944 | * and enable CMB decoding for the NVMe 1.4+ scheme: | |
1945 | */ | |
1946 | if (NVME_CAP_CMBS(dev->ctrl.cap)) { | |
1947 | hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | | |
1948 | (pci_bus_address(pdev, bar) + offset), | |
1949 | dev->bar + NVME_REG_CMBMSC); | |
1950 | } | |
1951 | ||
8ffaadf7 JD |
1952 | /* |
1953 | * Controllers may support a CMB size larger than their BAR, | |
1954 | * for example, due to being behind a bridge. Reduce the CMB to | |
1955 | * the reported size of the BAR | |
1956 | */ | |
1957 | if (size > bar_size - offset) | |
1958 | size = bar_size - offset; | |
1959 | ||
0f238ff5 LG |
1960 | if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { |
1961 | dev_warn(dev->ctrl.device, | |
1962 | "failed to register the CMB\n"); | |
f65efd6d | 1963 | return; |
0f238ff5 LG |
1964 | } |
1965 | ||
8ffaadf7 | 1966 | dev->cmb_size = size; |
0f238ff5 LG |
1967 | dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); |
1968 | ||
1969 | if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == | |
1970 | (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) | |
1971 | pci_p2pmem_publish(pdev, true); | |
8ffaadf7 JD |
1972 | } |
1973 | ||
87ad72a5 CH |
1974 | static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) |
1975 | { | |
6c3c05b0 | 1976 | u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; |
4033f35d | 1977 | u64 dma_addr = dev->host_mem_descs_dma; |
f66e2804 | 1978 | struct nvme_command c = { }; |
87ad72a5 CH |
1979 | int ret; |
1980 | ||
87ad72a5 CH |
1981 | c.features.opcode = nvme_admin_set_features; |
1982 | c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); | |
1983 | c.features.dword11 = cpu_to_le32(bits); | |
6c3c05b0 | 1984 | c.features.dword12 = cpu_to_le32(host_mem_size); |
87ad72a5 CH |
1985 | c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); |
1986 | c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); | |
1987 | c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); | |
1988 | ||
1989 | ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); | |
1990 | if (ret) { | |
1991 | dev_warn(dev->ctrl.device, | |
1992 | "failed to set host mem (err %d, flags %#x).\n", | |
1993 | ret, bits); | |
a5df5e79 KB |
1994 | } else |
1995 | dev->hmb = bits & NVME_HOST_MEM_ENABLE; | |
1996 | ||
87ad72a5 CH |
1997 | return ret; |
1998 | } | |
1999 | ||
2000 | static void nvme_free_host_mem(struct nvme_dev *dev) | |
2001 | { | |
2002 | int i; | |
2003 | ||
2004 | for (i = 0; i < dev->nr_host_mem_descs; i++) { | |
2005 | struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; | |
6c3c05b0 | 2006 | size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; |
87ad72a5 | 2007 | |
cc667f6d LD |
2008 | dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], |
2009 | le64_to_cpu(desc->addr), | |
2010 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
87ad72a5 CH |
2011 | } |
2012 | ||
2013 | kfree(dev->host_mem_desc_bufs); | |
2014 | dev->host_mem_desc_bufs = NULL; | |
4033f35d CH |
2015 | dma_free_coherent(dev->dev, |
2016 | dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), | |
2017 | dev->host_mem_descs, dev->host_mem_descs_dma); | |
87ad72a5 | 2018 | dev->host_mem_descs = NULL; |
7e5dd57e | 2019 | dev->nr_host_mem_descs = 0; |
87ad72a5 CH |
2020 | } |
2021 | ||
92dc6895 CH |
2022 | static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, |
2023 | u32 chunk_size) | |
9d713c2b | 2024 | { |
87ad72a5 | 2025 | struct nvme_host_mem_buf_desc *descs; |
92dc6895 | 2026 | u32 max_entries, len; |
4033f35d | 2027 | dma_addr_t descs_dma; |
2ee0e4ed | 2028 | int i = 0; |
87ad72a5 | 2029 | void **bufs; |
6fbcde66 | 2030 | u64 size, tmp; |
87ad72a5 | 2031 | |
87ad72a5 CH |
2032 | tmp = (preferred + chunk_size - 1); |
2033 | do_div(tmp, chunk_size); | |
2034 | max_entries = tmp; | |
044a9df1 CH |
2035 | |
2036 | if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) | |
2037 | max_entries = dev->ctrl.hmmaxd; | |
2038 | ||
750afb08 LC |
2039 | descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), |
2040 | &descs_dma, GFP_KERNEL); | |
87ad72a5 CH |
2041 | if (!descs) |
2042 | goto out; | |
2043 | ||
2044 | bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); | |
2045 | if (!bufs) | |
2046 | goto out_free_descs; | |
2047 | ||
244a8fe4 | 2048 | for (size = 0; size < preferred && i < max_entries; size += len) { |
87ad72a5 CH |
2049 | dma_addr_t dma_addr; |
2050 | ||
50cdb7c6 | 2051 | len = min_t(u64, chunk_size, preferred - size); |
87ad72a5 CH |
2052 | bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, |
2053 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
2054 | if (!bufs[i]) | |
2055 | break; | |
2056 | ||
2057 | descs[i].addr = cpu_to_le64(dma_addr); | |
6c3c05b0 | 2058 | descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); |
87ad72a5 CH |
2059 | i++; |
2060 | } | |
2061 | ||
92dc6895 | 2062 | if (!size) |
87ad72a5 | 2063 | goto out_free_bufs; |
87ad72a5 | 2064 | |
87ad72a5 CH |
2065 | dev->nr_host_mem_descs = i; |
2066 | dev->host_mem_size = size; | |
2067 | dev->host_mem_descs = descs; | |
4033f35d | 2068 | dev->host_mem_descs_dma = descs_dma; |
87ad72a5 CH |
2069 | dev->host_mem_desc_bufs = bufs; |
2070 | return 0; | |
2071 | ||
2072 | out_free_bufs: | |
2073 | while (--i >= 0) { | |
6c3c05b0 | 2074 | size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; |
87ad72a5 | 2075 | |
cc667f6d LD |
2076 | dma_free_attrs(dev->dev, size, bufs[i], |
2077 | le64_to_cpu(descs[i].addr), | |
2078 | DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); | |
87ad72a5 CH |
2079 | } |
2080 | ||
2081 | kfree(bufs); | |
2082 | out_free_descs: | |
4033f35d CH |
2083 | dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, |
2084 | descs_dma); | |
87ad72a5 | 2085 | out: |
87ad72a5 CH |
2086 | dev->host_mem_descs = NULL; |
2087 | return -ENOMEM; | |
2088 | } | |
2089 | ||
92dc6895 CH |
2090 | static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) |
2091 | { | |
9dc54a0d CK |
2092 | u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); |
2093 | u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); | |
2094 | u64 chunk_size; | |
92dc6895 CH |
2095 | |
2096 | /* start big and work our way down */ | |
9dc54a0d | 2097 | for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { |
92dc6895 CH |
2098 | if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { |
2099 | if (!min || dev->host_mem_size >= min) | |
2100 | return 0; | |
2101 | nvme_free_host_mem(dev); | |
2102 | } | |
2103 | } | |
2104 | ||
2105 | return -ENOMEM; | |
2106 | } | |
2107 | ||
9620cfba | 2108 | static int nvme_setup_host_mem(struct nvme_dev *dev) |
87ad72a5 CH |
2109 | { |
2110 | u64 max = (u64)max_host_mem_size_mb * SZ_1M; | |
2111 | u64 preferred = (u64)dev->ctrl.hmpre * 4096; | |
2112 | u64 min = (u64)dev->ctrl.hmmin * 4096; | |
2113 | u32 enable_bits = NVME_HOST_MEM_ENABLE; | |
6fbcde66 | 2114 | int ret; |
87ad72a5 CH |
2115 | |
2116 | preferred = min(preferred, max); | |
2117 | if (min > max) { | |
2118 | dev_warn(dev->ctrl.device, | |
2119 | "min host memory (%lld MiB) above limit (%d MiB).\n", | |
2120 | min >> ilog2(SZ_1M), max_host_mem_size_mb); | |
2121 | nvme_free_host_mem(dev); | |
9620cfba | 2122 | return 0; |
87ad72a5 CH |
2123 | } |
2124 | ||
2125 | /* | |
2126 | * If we already have a buffer allocated check if we can reuse it. | |
2127 | */ | |
2128 | if (dev->host_mem_descs) { | |
2129 | if (dev->host_mem_size >= min) | |
2130 | enable_bits |= NVME_HOST_MEM_RETURN; | |
2131 | else | |
2132 | nvme_free_host_mem(dev); | |
2133 | } | |
2134 | ||
2135 | if (!dev->host_mem_descs) { | |
92dc6895 CH |
2136 | if (nvme_alloc_host_mem(dev, min, preferred)) { |
2137 | dev_warn(dev->ctrl.device, | |
2138 | "failed to allocate host memory buffer.\n"); | |
9620cfba | 2139 | return 0; /* controller must work without HMB */ |
92dc6895 CH |
2140 | } |
2141 | ||
2142 | dev_info(dev->ctrl.device, | |
2143 | "allocated %lld MiB host memory buffer.\n", | |
2144 | dev->host_mem_size >> ilog2(SZ_1M)); | |
87ad72a5 CH |
2145 | } |
2146 | ||
9620cfba CH |
2147 | ret = nvme_set_host_mem(dev, enable_bits); |
2148 | if (ret) | |
87ad72a5 | 2149 | nvme_free_host_mem(dev); |
9620cfba | 2150 | return ret; |
9d713c2b KB |
2151 | } |
2152 | ||
0521905e KB |
2153 | static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, |
2154 | char *buf) | |
2155 | { | |
2156 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2157 | ||
2158 | return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", | |
2159 | ndev->cmbloc, ndev->cmbsz); | |
2160 | } | |
2161 | static DEVICE_ATTR_RO(cmb); | |
2162 | ||
1751e97a KB |
2163 | static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, |
2164 | char *buf) | |
2165 | { | |
2166 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2167 | ||
2168 | return sysfs_emit(buf, "%u\n", ndev->cmbloc); | |
2169 | } | |
2170 | static DEVICE_ATTR_RO(cmbloc); | |
2171 | ||
2172 | static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, | |
2173 | char *buf) | |
2174 | { | |
2175 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2176 | ||
2177 | return sysfs_emit(buf, "%u\n", ndev->cmbsz); | |
2178 | } | |
2179 | static DEVICE_ATTR_RO(cmbsz); | |
2180 | ||
a5df5e79 KB |
2181 | static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, |
2182 | char *buf) | |
2183 | { | |
2184 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2185 | ||
2186 | return sysfs_emit(buf, "%d\n", ndev->hmb); | |
2187 | } | |
2188 | ||
2189 | static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, | |
2190 | const char *buf, size_t count) | |
2191 | { | |
2192 | struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); | |
2193 | bool new; | |
2194 | int ret; | |
2195 | ||
2196 | if (strtobool(buf, &new) < 0) | |
2197 | return -EINVAL; | |
2198 | ||
2199 | if (new == ndev->hmb) | |
2200 | return count; | |
2201 | ||
2202 | if (new) { | |
2203 | ret = nvme_setup_host_mem(ndev); | |
2204 | } else { | |
2205 | ret = nvme_set_host_mem(ndev, 0); | |
2206 | if (!ret) | |
2207 | nvme_free_host_mem(ndev); | |
2208 | } | |
2209 | ||
2210 | if (ret < 0) | |
2211 | return ret; | |
2212 | ||
2213 | return count; | |
2214 | } | |
2215 | static DEVICE_ATTR_RW(hmb); | |
2216 | ||
0521905e KB |
2217 | static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, |
2218 | struct attribute *a, int n) | |
2219 | { | |
2220 | struct nvme_ctrl *ctrl = | |
2221 | dev_get_drvdata(container_of(kobj, struct device, kobj)); | |
2222 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
2223 | ||
1751e97a KB |
2224 | if (a == &dev_attr_cmb.attr || |
2225 | a == &dev_attr_cmbloc.attr || | |
2226 | a == &dev_attr_cmbsz.attr) { | |
2227 | if (!dev->cmbsz) | |
2228 | return 0; | |
2229 | } | |
a5df5e79 KB |
2230 | if (a == &dev_attr_hmb.attr && !ctrl->hmpre) |
2231 | return 0; | |
2232 | ||
0521905e KB |
2233 | return a->mode; |
2234 | } | |
2235 | ||
2236 | static struct attribute *nvme_pci_attrs[] = { | |
2237 | &dev_attr_cmb.attr, | |
1751e97a KB |
2238 | &dev_attr_cmbloc.attr, |
2239 | &dev_attr_cmbsz.attr, | |
a5df5e79 | 2240 | &dev_attr_hmb.attr, |
0521905e KB |
2241 | NULL, |
2242 | }; | |
2243 | ||
2244 | static const struct attribute_group nvme_pci_attr_group = { | |
2245 | .attrs = nvme_pci_attrs, | |
2246 | .is_visible = nvme_pci_attrs_are_visible, | |
2247 | }; | |
2248 | ||
612b7286 ML |
2249 | /* |
2250 | * nirqs is the number of interrupts available for write and read | |
2251 | * queues. The core already reserved an interrupt for the admin queue. | |
2252 | */ | |
2253 | static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) | |
3b6592f7 | 2254 | { |
612b7286 | 2255 | struct nvme_dev *dev = affd->priv; |
2a5bcfdd | 2256 | unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; |
3b6592f7 JA |
2257 | |
2258 | /* | |
ee0d96d3 | 2259 | * If there is no interrupt available for queues, ensure that |
612b7286 ML |
2260 | * the default queue is set to 1. The affinity set size is |
2261 | * also set to one, but the irq core ignores it for this case. | |
2262 | * | |
2263 | * If only one interrupt is available or 'write_queue' == 0, combine | |
2264 | * write and read queues. | |
2265 | * | |
2266 | * If 'write_queues' > 0, ensure it leaves room for at least one read | |
2267 | * queue. | |
3b6592f7 | 2268 | */ |
612b7286 ML |
2269 | if (!nrirqs) { |
2270 | nrirqs = 1; | |
2271 | nr_read_queues = 0; | |
2a5bcfdd | 2272 | } else if (nrirqs == 1 || !nr_write_queues) { |
612b7286 | 2273 | nr_read_queues = 0; |
2a5bcfdd | 2274 | } else if (nr_write_queues >= nrirqs) { |
612b7286 | 2275 | nr_read_queues = 1; |
3b6592f7 | 2276 | } else { |
2a5bcfdd | 2277 | nr_read_queues = nrirqs - nr_write_queues; |
3b6592f7 | 2278 | } |
612b7286 ML |
2279 | |
2280 | dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; | |
2281 | affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; | |
2282 | dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; | |
2283 | affd->set_size[HCTX_TYPE_READ] = nr_read_queues; | |
2284 | affd->nr_sets = nr_read_queues ? 2 : 1; | |
3b6592f7 JA |
2285 | } |
2286 | ||
6451fe73 | 2287 | static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) |
3b6592f7 JA |
2288 | { |
2289 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
3b6592f7 | 2290 | struct irq_affinity affd = { |
9cfef55b | 2291 | .pre_vectors = 1, |
612b7286 ML |
2292 | .calc_sets = nvme_calc_irq_sets, |
2293 | .priv = dev, | |
3b6592f7 | 2294 | }; |
21cc2f3f | 2295 | unsigned int irq_queues, poll_queues; |
6451fe73 JA |
2296 | |
2297 | /* | |
21cc2f3f JX |
2298 | * Poll queues don't need interrupts, but we need at least one I/O queue |
2299 | * left over for non-polled I/O. | |
6451fe73 | 2300 | */ |
21cc2f3f JX |
2301 | poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); |
2302 | dev->io_queues[HCTX_TYPE_POLL] = poll_queues; | |
3b6592f7 | 2303 | |
21cc2f3f JX |
2304 | /* |
2305 | * Initialize for the single interrupt case, will be updated in | |
2306 | * nvme_calc_irq_sets(). | |
2307 | */ | |
612b7286 ML |
2308 | dev->io_queues[HCTX_TYPE_DEFAULT] = 1; |
2309 | dev->io_queues[HCTX_TYPE_READ] = 0; | |
3b6592f7 | 2310 | |
66341331 | 2311 | /* |
21cc2f3f JX |
2312 | * We need interrupts for the admin queue and each non-polled I/O queue, |
2313 | * but some Apple controllers require all queues to use the first | |
2314 | * vector. | |
66341331 | 2315 | */ |
21cc2f3f JX |
2316 | irq_queues = 1; |
2317 | if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) | |
2318 | irq_queues += (nr_io_queues - poll_queues); | |
612b7286 ML |
2319 | return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, |
2320 | PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); | |
3b6592f7 JA |
2321 | } |
2322 | ||
8fae268b KB |
2323 | static void nvme_disable_io_queues(struct nvme_dev *dev) |
2324 | { | |
2325 | if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) | |
2326 | __nvme_disable_io_queues(dev, nvme_admin_delete_cq); | |
2327 | } | |
2328 | ||
2a5bcfdd WZ |
2329 | static unsigned int nvme_max_io_queues(struct nvme_dev *dev) |
2330 | { | |
e3aef095 NS |
2331 | /* |
2332 | * If tags are shared with admin queue (Apple bug), then | |
2333 | * make sure we only use one IO queue. | |
2334 | */ | |
2335 | if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) | |
2336 | return 1; | |
2a5bcfdd WZ |
2337 | return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; |
2338 | } | |
2339 | ||
8d85fce7 | 2340 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2341 | { |
147b27e4 | 2342 | struct nvme_queue *adminq = &dev->queues[0]; |
e75ec752 | 2343 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2a5bcfdd | 2344 | unsigned int nr_io_queues; |
97f6ef64 | 2345 | unsigned long size; |
2a5bcfdd | 2346 | int result; |
b60503ba | 2347 | |
2a5bcfdd WZ |
2348 | /* |
2349 | * Sample the module parameters once at reset time so that we have | |
2350 | * stable values to work with. | |
2351 | */ | |
2352 | dev->nr_write_queues = write_queues; | |
2353 | dev->nr_poll_queues = poll_queues; | |
d38e9f04 | 2354 | |
e3aef095 | 2355 | nr_io_queues = dev->nr_allocated_queues - 1; |
9a0be7ab CH |
2356 | result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); |
2357 | if (result < 0) | |
1b23484b | 2358 | return result; |
9a0be7ab | 2359 | |
f5fa90dc | 2360 | if (nr_io_queues == 0) |
a5229050 | 2361 | return 0; |
53dc180e | 2362 | |
e4b9852a CC |
2363 | /* |
2364 | * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions | |
2365 | * from set to unset. If there is a window to it is truely freed, | |
2366 | * pci_free_irq_vectors() jumping into this window will crash. | |
2367 | * And take lock to avoid racing with pci_free_irq_vectors() in | |
2368 | * nvme_dev_disable() path. | |
2369 | */ | |
2370 | result = nvme_setup_io_queues_trylock(dev); | |
2371 | if (result) | |
2372 | return result; | |
2373 | if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) | |
2374 | pci_free_irq(pdev, 0, adminq); | |
b60503ba | 2375 | |
0f238ff5 | 2376 | if (dev->cmb_use_sqes) { |
8ffaadf7 JD |
2377 | result = nvme_cmb_qdepth(dev, nr_io_queues, |
2378 | sizeof(struct nvme_command)); | |
2379 | if (result > 0) | |
2380 | dev->q_depth = result; | |
2381 | else | |
0f238ff5 | 2382 | dev->cmb_use_sqes = false; |
8ffaadf7 JD |
2383 | } |
2384 | ||
97f6ef64 XY |
2385 | do { |
2386 | size = db_bar_size(dev, nr_io_queues); | |
2387 | result = nvme_remap_bar(dev, size); | |
2388 | if (!result) | |
2389 | break; | |
e4b9852a CC |
2390 | if (!--nr_io_queues) { |
2391 | result = -ENOMEM; | |
2392 | goto out_unlock; | |
2393 | } | |
97f6ef64 XY |
2394 | } while (1); |
2395 | adminq->q_db = dev->dbs; | |
f1938f6e | 2396 | |
8fae268b | 2397 | retry: |
9d713c2b | 2398 | /* Deregister the admin queue's interrupt */ |
e4b9852a CC |
2399 | if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) |
2400 | pci_free_irq(pdev, 0, adminq); | |
9d713c2b | 2401 | |
e32efbfc JA |
2402 | /* |
2403 | * If we enable msix early due to not intx, disable it again before | |
2404 | * setting up the full range we need. | |
2405 | */ | |
dca51e78 | 2406 | pci_free_irq_vectors(pdev); |
3b6592f7 JA |
2407 | |
2408 | result = nvme_setup_irqs(dev, nr_io_queues); | |
e4b9852a CC |
2409 | if (result <= 0) { |
2410 | result = -EIO; | |
2411 | goto out_unlock; | |
2412 | } | |
3b6592f7 | 2413 | |
22b55601 | 2414 | dev->num_vecs = result; |
4b04cc6a | 2415 | result = max(result - 1, 1); |
e20ba6e1 | 2416 | dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; |
fa08a396 | 2417 | |
063a8096 MW |
2418 | /* |
2419 | * Should investigate if there's a performance win from allocating | |
2420 | * more queues than interrupt vectors; it might allow the submission | |
2421 | * path to scale better, even if the receive path is limited by the | |
2422 | * number of interrupts. | |
2423 | */ | |
dca51e78 | 2424 | result = queue_request_irq(adminq); |
7c349dde | 2425 | if (result) |
e4b9852a | 2426 | goto out_unlock; |
4e224106 | 2427 | set_bit(NVMEQ_ENABLED, &adminq->flags); |
e4b9852a | 2428 | mutex_unlock(&dev->shutdown_lock); |
8fae268b KB |
2429 | |
2430 | result = nvme_create_io_queues(dev); | |
2431 | if (result || dev->online_queues < 2) | |
2432 | return result; | |
2433 | ||
2434 | if (dev->online_queues - 1 < dev->max_qid) { | |
2435 | nr_io_queues = dev->online_queues - 1; | |
2436 | nvme_disable_io_queues(dev); | |
e4b9852a CC |
2437 | result = nvme_setup_io_queues_trylock(dev); |
2438 | if (result) | |
2439 | return result; | |
8fae268b KB |
2440 | nvme_suspend_io_queues(dev); |
2441 | goto retry; | |
2442 | } | |
2443 | dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", | |
2444 | dev->io_queues[HCTX_TYPE_DEFAULT], | |
2445 | dev->io_queues[HCTX_TYPE_READ], | |
2446 | dev->io_queues[HCTX_TYPE_POLL]); | |
2447 | return 0; | |
e4b9852a CC |
2448 | out_unlock: |
2449 | mutex_unlock(&dev->shutdown_lock); | |
2450 | return result; | |
b60503ba MW |
2451 | } |
2452 | ||
2a842aca | 2453 | static void nvme_del_queue_end(struct request *req, blk_status_t error) |
a5768aa8 | 2454 | { |
db3cbfff | 2455 | struct nvme_queue *nvmeq = req->end_io_data; |
b5875222 | 2456 | |
db3cbfff | 2457 | blk_mq_free_request(req); |
d1ed6aa1 | 2458 | complete(&nvmeq->delete_done); |
a5768aa8 KB |
2459 | } |
2460 | ||
2a842aca | 2461 | static void nvme_del_cq_end(struct request *req, blk_status_t error) |
a5768aa8 | 2462 | { |
db3cbfff | 2463 | struct nvme_queue *nvmeq = req->end_io_data; |
a5768aa8 | 2464 | |
d1ed6aa1 CH |
2465 | if (error) |
2466 | set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); | |
db3cbfff KB |
2467 | |
2468 | nvme_del_queue_end(req, error); | |
a5768aa8 KB |
2469 | } |
2470 | ||
db3cbfff | 2471 | static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) |
bda4e0fb | 2472 | { |
db3cbfff KB |
2473 | struct request_queue *q = nvmeq->dev->ctrl.admin_q; |
2474 | struct request *req; | |
f66e2804 | 2475 | struct nvme_command cmd = { }; |
bda4e0fb | 2476 | |
db3cbfff KB |
2477 | cmd.delete_queue.opcode = opcode; |
2478 | cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
bda4e0fb | 2479 | |
e559398f | 2480 | req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); |
db3cbfff KB |
2481 | if (IS_ERR(req)) |
2482 | return PTR_ERR(req); | |
e559398f | 2483 | nvme_init_request(req, &cmd); |
bda4e0fb | 2484 | |
e2e53086 CH |
2485 | if (opcode == nvme_admin_delete_cq) |
2486 | req->end_io = nvme_del_cq_end; | |
2487 | else | |
2488 | req->end_io = nvme_del_queue_end; | |
db3cbfff KB |
2489 | req->end_io_data = nvmeq; |
2490 | ||
d1ed6aa1 | 2491 | init_completion(&nvmeq->delete_done); |
128126a7 | 2492 | req->rq_flags |= RQF_QUIET; |
e2e53086 | 2493 | blk_execute_rq_nowait(req, false); |
db3cbfff | 2494 | return 0; |
bda4e0fb KB |
2495 | } |
2496 | ||
8fae268b | 2497 | static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) |
a5768aa8 | 2498 | { |
5271edd4 | 2499 | int nr_queues = dev->online_queues - 1, sent = 0; |
db3cbfff | 2500 | unsigned long timeout; |
a5768aa8 | 2501 | |
db3cbfff | 2502 | retry: |
dc96f938 | 2503 | timeout = NVME_ADMIN_TIMEOUT; |
5271edd4 CH |
2504 | while (nr_queues > 0) { |
2505 | if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) | |
2506 | break; | |
2507 | nr_queues--; | |
2508 | sent++; | |
db3cbfff | 2509 | } |
d1ed6aa1 CH |
2510 | while (sent) { |
2511 | struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; | |
2512 | ||
2513 | timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, | |
5271edd4 CH |
2514 | timeout); |
2515 | if (timeout == 0) | |
2516 | return false; | |
d1ed6aa1 | 2517 | |
d1ed6aa1 | 2518 | sent--; |
5271edd4 CH |
2519 | if (nr_queues) |
2520 | goto retry; | |
2521 | } | |
2522 | return true; | |
a5768aa8 KB |
2523 | } |
2524 | ||
2455a4b7 | 2525 | static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) |
b60503ba | 2526 | { |
2455a4b7 | 2527 | struct blk_mq_tag_set * set = &dev->tagset; |
2b1b7e78 JW |
2528 | int ret; |
2529 | ||
2455a4b7 CH |
2530 | set->ops = &nvme_mq_ops; |
2531 | set->nr_hw_queues = dev->online_queues - 1; | |
2532 | set->nr_maps = 2; /* default + read */ | |
2533 | if (dev->io_queues[HCTX_TYPE_POLL]) | |
2534 | set->nr_maps++; | |
2535 | set->timeout = NVME_IO_TIMEOUT; | |
2536 | set->numa_node = dev->ctrl.numa_node; | |
2537 | set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; | |
2538 | set->cmd_size = sizeof(struct nvme_iod); | |
2539 | set->flags = BLK_MQ_F_SHOULD_MERGE; | |
2540 | set->driver_data = dev; | |
d38e9f04 | 2541 | |
2455a4b7 CH |
2542 | /* |
2543 | * Some Apple controllers requires tags to be unique | |
2544 | * across admin and IO queue, so reserve the first 32 | |
2545 | * tags of the IO queue. | |
2546 | */ | |
2547 | if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) | |
2548 | set->reserved_tags = NVME_AQ_DEPTH; | |
949928c1 | 2549 | |
2455a4b7 CH |
2550 | ret = blk_mq_alloc_tag_set(set); |
2551 | if (ret) { | |
2552 | dev_warn(dev->ctrl.device, | |
2553 | "IO queues tagset allocation failed %d\n", ret); | |
2554 | return; | |
ffe7704d | 2555 | } |
2455a4b7 CH |
2556 | dev->ctrl.tagset = set; |
2557 | } | |
949928c1 | 2558 | |
2455a4b7 CH |
2559 | static void nvme_pci_update_nr_queues(struct nvme_dev *dev) |
2560 | { | |
2561 | blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); | |
2562 | /* free previously allocated queues that are no longer usable */ | |
2563 | nvme_free_queues(dev, dev->online_queues); | |
b60503ba MW |
2564 | } |
2565 | ||
b00a726a | 2566 | static int nvme_pci_enable(struct nvme_dev *dev) |
0877cb0d | 2567 | { |
b00a726a | 2568 | int result = -ENOMEM; |
e75ec752 | 2569 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
4bdf2603 | 2570 | int dma_address_bits = 64; |
0877cb0d KB |
2571 | |
2572 | if (pci_enable_device_mem(pdev)) | |
2573 | return result; | |
2574 | ||
0877cb0d | 2575 | pci_set_master(pdev); |
0877cb0d | 2576 | |
4bdf2603 FS |
2577 | if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) |
2578 | dma_address_bits = 48; | |
2579 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) | |
052d0efa | 2580 | goto disable; |
0877cb0d | 2581 | |
7a67cbea | 2582 | if (readl(dev->bar + NVME_REG_CSTS) == -1) { |
0e53d180 | 2583 | result = -ENODEV; |
b00a726a | 2584 | goto disable; |
0e53d180 | 2585 | } |
e32efbfc JA |
2586 | |
2587 | /* | |
a5229050 KB |
2588 | * Some devices and/or platforms don't advertise or work with INTx |
2589 | * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll | |
2590 | * adjust this later. | |
e32efbfc | 2591 | */ |
dca51e78 CH |
2592 | result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); |
2593 | if (result < 0) | |
2594 | return result; | |
e32efbfc | 2595 | |
20d0dfe6 | 2596 | dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); |
7a67cbea | 2597 | |
7442ddce | 2598 | dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, |
b27c1e68 | 2599 | io_queue_depth); |
aa22c8e6 | 2600 | dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ |
20d0dfe6 | 2601 | dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); |
7a67cbea | 2602 | dev->dbs = dev->bar + 4096; |
1f390c1f | 2603 | |
66341331 BH |
2604 | /* |
2605 | * Some Apple controllers require a non-standard SQE size. | |
2606 | * Interestingly they also seem to ignore the CC:IOSQES register | |
2607 | * so we don't bother updating it here. | |
2608 | */ | |
2609 | if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) | |
2610 | dev->io_sqes = 7; | |
2611 | else | |
2612 | dev->io_sqes = NVME_NVM_IOSQES; | |
1f390c1f SG |
2613 | |
2614 | /* | |
2615 | * Temporary fix for the Apple controller found in the MacBook8,1 and | |
2616 | * some MacBook7,1 to avoid controller resets and data loss. | |
2617 | */ | |
2618 | if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { | |
2619 | dev->q_depth = 2; | |
9bdcfb10 CH |
2620 | dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " |
2621 | "set queue depth=%u to work around controller resets\n", | |
1f390c1f | 2622 | dev->q_depth); |
d554b5e1 MP |
2623 | } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && |
2624 | (pdev->device == 0xa821 || pdev->device == 0xa822) && | |
20d0dfe6 | 2625 | NVME_CAP_MQES(dev->ctrl.cap) == 0) { |
d554b5e1 MP |
2626 | dev->q_depth = 64; |
2627 | dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " | |
2628 | "set queue depth=%u\n", dev->q_depth); | |
1f390c1f SG |
2629 | } |
2630 | ||
d38e9f04 BH |
2631 | /* |
2632 | * Controllers with the shared tags quirk need the IO queue to be | |
2633 | * big enough so that we get 32 tags for the admin queue | |
2634 | */ | |
2635 | if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && | |
2636 | (dev->q_depth < (NVME_AQ_DEPTH + 2))) { | |
2637 | dev->q_depth = NVME_AQ_DEPTH + 2; | |
2638 | dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", | |
2639 | dev->q_depth); | |
2640 | } | |
2641 | ||
2642 | ||
f65efd6d | 2643 | nvme_map_cmb(dev); |
202021c1 | 2644 | |
a0a3408e KB |
2645 | pci_enable_pcie_error_reporting(pdev); |
2646 | pci_save_state(pdev); | |
0877cb0d KB |
2647 | return 0; |
2648 | ||
2649 | disable: | |
0877cb0d KB |
2650 | pci_disable_device(pdev); |
2651 | return result; | |
2652 | } | |
2653 | ||
2654 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
b00a726a KB |
2655 | { |
2656 | if (dev->bar) | |
2657 | iounmap(dev->bar); | |
a1f447b3 | 2658 | pci_release_mem_regions(to_pci_dev(dev->dev)); |
b00a726a KB |
2659 | } |
2660 | ||
2661 | static void nvme_pci_disable(struct nvme_dev *dev) | |
0877cb0d | 2662 | { |
e75ec752 CH |
2663 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2664 | ||
dca51e78 | 2665 | pci_free_irq_vectors(pdev); |
0877cb0d | 2666 | |
a0a3408e KB |
2667 | if (pci_is_enabled(pdev)) { |
2668 | pci_disable_pcie_error_reporting(pdev); | |
e75ec752 | 2669 | pci_disable_device(pdev); |
4d115420 | 2670 | } |
4d115420 KB |
2671 | } |
2672 | ||
a5cdb68c | 2673 | static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) |
b60503ba | 2674 | { |
e43269e6 | 2675 | bool dead = true, freeze = false; |
302ad8cc | 2676 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
22404274 | 2677 | |
77bf25ea | 2678 | mutex_lock(&dev->shutdown_lock); |
081f5e75 KB |
2679 | if (pci_is_enabled(pdev)) { |
2680 | u32 csts; | |
2681 | ||
2682 | if (pci_device_is_present(pdev)) | |
2683 | csts = readl(dev->bar + NVME_REG_CSTS); | |
2684 | else | |
2685 | csts = ~0; | |
302ad8cc | 2686 | |
ebef7368 | 2687 | if (dev->ctrl.state == NVME_CTRL_LIVE || |
e43269e6 KB |
2688 | dev->ctrl.state == NVME_CTRL_RESETTING) { |
2689 | freeze = true; | |
302ad8cc | 2690 | nvme_start_freeze(&dev->ctrl); |
e43269e6 | 2691 | } |
302ad8cc KB |
2692 | dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || |
2693 | pdev->error_state != pci_channel_io_normal); | |
c9d3bf88 | 2694 | } |
c21377f8 | 2695 | |
302ad8cc KB |
2696 | /* |
2697 | * Give the controller a chance to complete all entered requests if | |
2698 | * doing a safe shutdown. | |
2699 | */ | |
e43269e6 KB |
2700 | if (!dead && shutdown && freeze) |
2701 | nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); | |
9a915a5b JW |
2702 | |
2703 | nvme_stop_queues(&dev->ctrl); | |
87ad72a5 | 2704 | |
64ee0ac0 | 2705 | if (!dead && dev->ctrl.queue_count > 0) { |
8fae268b | 2706 | nvme_disable_io_queues(dev); |
a5cdb68c | 2707 | nvme_disable_admin_queue(dev, shutdown); |
4d115420 | 2708 | } |
8fae268b KB |
2709 | nvme_suspend_io_queues(dev); |
2710 | nvme_suspend_queue(&dev->queues[0]); | |
b00a726a | 2711 | nvme_pci_disable(dev); |
fa46c6fb | 2712 | nvme_reap_pending_cqes(dev); |
07836e65 | 2713 | |
1fcfca78 GL |
2714 | nvme_cancel_tagset(&dev->ctrl); |
2715 | nvme_cancel_admin_tagset(&dev->ctrl); | |
302ad8cc KB |
2716 | |
2717 | /* | |
2718 | * The driver will not be starting up queues again if shutting down so | |
2719 | * must flush all entered requests to their failed completion to avoid | |
2720 | * deadlocking blk-mq hot-cpu notifier. | |
2721 | */ | |
c8e9e9b7 | 2722 | if (shutdown) { |
302ad8cc | 2723 | nvme_start_queues(&dev->ctrl); |
c8e9e9b7 | 2724 | if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) |
6ca1d902 | 2725 | nvme_start_admin_queue(&dev->ctrl); |
c8e9e9b7 | 2726 | } |
77bf25ea | 2727 | mutex_unlock(&dev->shutdown_lock); |
b60503ba MW |
2728 | } |
2729 | ||
c1ac9a4b KB |
2730 | static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) |
2731 | { | |
2732 | if (!nvme_wait_reset(&dev->ctrl)) | |
2733 | return -EBUSY; | |
2734 | nvme_dev_disable(dev, shutdown); | |
2735 | return 0; | |
2736 | } | |
2737 | ||
091b6092 MW |
2738 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2739 | { | |
e75ec752 | 2740 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
c61b82c7 CH |
2741 | NVME_CTRL_PAGE_SIZE, |
2742 | NVME_CTRL_PAGE_SIZE, 0); | |
091b6092 MW |
2743 | if (!dev->prp_page_pool) |
2744 | return -ENOMEM; | |
2745 | ||
99802a7a | 2746 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2747 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2748 | 256, 256, 0); |
2749 | if (!dev->prp_small_pool) { | |
2750 | dma_pool_destroy(dev->prp_page_pool); | |
2751 | return -ENOMEM; | |
2752 | } | |
091b6092 MW |
2753 | return 0; |
2754 | } | |
2755 | ||
2756 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2757 | { | |
2758 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2759 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2760 | } |
2761 | ||
770597ec KB |
2762 | static void nvme_free_tagset(struct nvme_dev *dev) |
2763 | { | |
2764 | if (dev->tagset.tags) | |
2765 | blk_mq_free_tag_set(&dev->tagset); | |
2766 | dev->ctrl.tagset = NULL; | |
2767 | } | |
2768 | ||
1673f1f0 | 2769 | static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) |
5e82e952 | 2770 | { |
1673f1f0 | 2771 | struct nvme_dev *dev = to_nvme_dev(ctrl); |
9ac27090 | 2772 | |
f9f38e33 | 2773 | nvme_dbbuf_dma_free(dev); |
770597ec | 2774 | nvme_free_tagset(dev); |
1c63dc66 CH |
2775 | if (dev->ctrl.admin_q) |
2776 | blk_put_queue(dev->ctrl.admin_q); | |
e286bcfc | 2777 | free_opal_dev(dev->ctrl.opal_dev); |
943e942e | 2778 | mempool_destroy(dev->iod_mempool); |
253fd4ac IR |
2779 | put_device(dev->dev); |
2780 | kfree(dev->queues); | |
5e82e952 KB |
2781 | kfree(dev); |
2782 | } | |
2783 | ||
7c1ce408 | 2784 | static void nvme_remove_dead_ctrl(struct nvme_dev *dev) |
f58944e2 | 2785 | { |
c1ac9a4b KB |
2786 | /* |
2787 | * Set state to deleting now to avoid blocking nvme_wait_reset(), which | |
2788 | * may be holding this pci_dev's device lock. | |
2789 | */ | |
2790 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); | |
d22524a4 | 2791 | nvme_get_ctrl(&dev->ctrl); |
69d9a99c | 2792 | nvme_dev_disable(dev, false); |
9f9cafc1 | 2793 | nvme_kill_queues(&dev->ctrl); |
03e0f3a6 | 2794 | if (!queue_work(nvme_wq, &dev->remove_work)) |
f58944e2 KB |
2795 | nvme_put_ctrl(&dev->ctrl); |
2796 | } | |
2797 | ||
fd634f41 | 2798 | static void nvme_reset_work(struct work_struct *work) |
5e82e952 | 2799 | { |
d86c4d8e CH |
2800 | struct nvme_dev *dev = |
2801 | container_of(work, struct nvme_dev, ctrl.reset_work); | |
a98e58e5 | 2802 | bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); |
e71afda4 | 2803 | int result; |
5e82e952 | 2804 | |
7764656b ZC |
2805 | if (dev->ctrl.state != NVME_CTRL_RESETTING) { |
2806 | dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", | |
2807 | dev->ctrl.state); | |
e71afda4 | 2808 | result = -ENODEV; |
fd634f41 | 2809 | goto out; |
e71afda4 | 2810 | } |
5e82e952 | 2811 | |
fd634f41 CH |
2812 | /* |
2813 | * If we're called to reset a live controller first shut it down before | |
2814 | * moving on. | |
2815 | */ | |
b00a726a | 2816 | if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) |
a5cdb68c | 2817 | nvme_dev_disable(dev, false); |
d6135c3a | 2818 | nvme_sync_queues(&dev->ctrl); |
5e82e952 | 2819 | |
5c959d73 | 2820 | mutex_lock(&dev->shutdown_lock); |
b00a726a | 2821 | result = nvme_pci_enable(dev); |
f0b50732 | 2822 | if (result) |
4726bcf3 | 2823 | goto out_unlock; |
f0b50732 | 2824 | |
01ad0990 | 2825 | result = nvme_pci_configure_admin_queue(dev); |
f0b50732 | 2826 | if (result) |
4726bcf3 | 2827 | goto out_unlock; |
f0b50732 | 2828 | |
f91b727c CH |
2829 | if (!dev->ctrl.admin_q) { |
2830 | result = nvme_pci_alloc_admin_tag_set(dev); | |
2831 | if (result) | |
2832 | goto out_unlock; | |
2833 | } else { | |
2834 | nvme_start_admin_queue(&dev->ctrl); | |
2835 | } | |
b9afca3e | 2836 | |
943e942e JA |
2837 | /* |
2838 | * Limit the max command size to prevent iod->sg allocations going | |
2839 | * over a single page. | |
2840 | */ | |
7637de31 CH |
2841 | dev->ctrl.max_hw_sectors = min_t(u32, |
2842 | NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); | |
943e942e | 2843 | dev->ctrl.max_segments = NVME_MAX_SEGS; |
a48bc520 CH |
2844 | |
2845 | /* | |
2846 | * Don't limit the IOMMU merged segment size. | |
2847 | */ | |
2848 | dma_set_max_seg_size(dev->dev, 0xffffffff); | |
3d2d861e | 2849 | dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); |
a48bc520 | 2850 | |
5c959d73 KB |
2851 | mutex_unlock(&dev->shutdown_lock); |
2852 | ||
2853 | /* | |
2854 | * Introduce CONNECTING state from nvme-fc/rdma transports to mark the | |
2855 | * initializing procedure here. | |
2856 | */ | |
2857 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { | |
2858 | dev_warn(dev->ctrl.device, | |
2859 | "failed to mark controller CONNECTING\n"); | |
cee6c269 | 2860 | result = -EBUSY; |
5c959d73 KB |
2861 | goto out; |
2862 | } | |
943e942e | 2863 | |
95093350 MG |
2864 | /* |
2865 | * We do not support an SGL for metadata (yet), so we are limited to a | |
2866 | * single integrity segment for the separate metadata pointer. | |
2867 | */ | |
2868 | dev->ctrl.max_integrity_segments = 1; | |
2869 | ||
f21c4769 | 2870 | result = nvme_init_ctrl_finish(&dev->ctrl); |
ce4541f4 | 2871 | if (result) |
f58944e2 | 2872 | goto out; |
ce4541f4 | 2873 | |
e286bcfc SB |
2874 | if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { |
2875 | if (!dev->ctrl.opal_dev) | |
2876 | dev->ctrl.opal_dev = | |
2877 | init_opal_dev(&dev->ctrl, &nvme_sec_submit); | |
2878 | else if (was_suspend) | |
2879 | opal_unlock_from_suspend(dev->ctrl.opal_dev); | |
2880 | } else { | |
2881 | free_opal_dev(dev->ctrl.opal_dev); | |
2882 | dev->ctrl.opal_dev = NULL; | |
4f1244c8 | 2883 | } |
a98e58e5 | 2884 | |
f9f38e33 HK |
2885 | if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { |
2886 | result = nvme_dbbuf_dma_alloc(dev); | |
2887 | if (result) | |
2888 | dev_warn(dev->dev, | |
2889 | "unable to allocate dma for dbbuf\n"); | |
2890 | } | |
2891 | ||
9620cfba CH |
2892 | if (dev->ctrl.hmpre) { |
2893 | result = nvme_setup_host_mem(dev); | |
2894 | if (result < 0) | |
2895 | goto out; | |
2896 | } | |
87ad72a5 | 2897 | |
f0b50732 | 2898 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2899 | if (result) |
f58944e2 | 2900 | goto out; |
f0b50732 | 2901 | |
2659e57b CH |
2902 | /* |
2903 | * Keep the controller around but remove all namespaces if we don't have | |
2904 | * any working I/O queue. | |
2905 | */ | |
3cf519b5 | 2906 | if (dev->online_queues < 2) { |
1b3c47c1 | 2907 | dev_warn(dev->ctrl.device, "IO queues not created\n"); |
3b24774e | 2908 | nvme_kill_queues(&dev->ctrl); |
5bae7f73 | 2909 | nvme_remove_namespaces(&dev->ctrl); |
770597ec | 2910 | nvme_free_tagset(dev); |
3cf519b5 | 2911 | } else { |
25646264 | 2912 | nvme_start_queues(&dev->ctrl); |
302ad8cc | 2913 | nvme_wait_freeze(&dev->ctrl); |
2455a4b7 CH |
2914 | if (!dev->ctrl.tagset) |
2915 | nvme_pci_alloc_tag_set(dev); | |
2916 | else | |
2917 | nvme_pci_update_nr_queues(dev); | |
2918 | nvme_dbbuf_set(dev); | |
302ad8cc | 2919 | nvme_unfreeze(&dev->ctrl); |
3cf519b5 CH |
2920 | } |
2921 | ||
2b1b7e78 JW |
2922 | /* |
2923 | * If only admin queue live, keep it to do further investigation or | |
2924 | * recovery. | |
2925 | */ | |
5d02a5c1 | 2926 | if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { |
2b1b7e78 | 2927 | dev_warn(dev->ctrl.device, |
5d02a5c1 | 2928 | "failed to mark controller live state\n"); |
e71afda4 | 2929 | result = -ENODEV; |
bb8d261e CH |
2930 | goto out; |
2931 | } | |
92911a55 | 2932 | |
0521905e KB |
2933 | if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, |
2934 | &nvme_pci_attr_group)) | |
2935 | dev->attrs_added = true; | |
2936 | ||
d09f2b45 | 2937 | nvme_start_ctrl(&dev->ctrl); |
3cf519b5 | 2938 | return; |
f0b50732 | 2939 | |
4726bcf3 KB |
2940 | out_unlock: |
2941 | mutex_unlock(&dev->shutdown_lock); | |
3cf519b5 | 2942 | out: |
7c1ce408 CK |
2943 | if (result) |
2944 | dev_warn(dev->ctrl.device, | |
2945 | "Removing after probe failure status: %d\n", result); | |
2946 | nvme_remove_dead_ctrl(dev); | |
f0b50732 KB |
2947 | } |
2948 | ||
5c8809e6 | 2949 | static void nvme_remove_dead_ctrl_work(struct work_struct *work) |
9a6b9458 | 2950 | { |
5c8809e6 | 2951 | struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); |
e75ec752 | 2952 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2953 | |
2954 | if (pci_get_drvdata(pdev)) | |
921920ab | 2955 | device_release_driver(&pdev->dev); |
1673f1f0 | 2956 | nvme_put_ctrl(&dev->ctrl); |
9a6b9458 KB |
2957 | } |
2958 | ||
1c63dc66 | 2959 | static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) |
9ca97374 | 2960 | { |
1c63dc66 | 2961 | *val = readl(to_nvme_dev(ctrl)->bar + off); |
90667892 | 2962 | return 0; |
9ca97374 TH |
2963 | } |
2964 | ||
5fd4ce1b | 2965 | static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) |
4cc06521 | 2966 | { |
5fd4ce1b CH |
2967 | writel(val, to_nvme_dev(ctrl)->bar + off); |
2968 | return 0; | |
2969 | } | |
4cc06521 | 2970 | |
7fd8930f CH |
2971 | static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) |
2972 | { | |
3a8ecc93 | 2973 | *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); |
7fd8930f | 2974 | return 0; |
4cc06521 KB |
2975 | } |
2976 | ||
97c12223 KB |
2977 | static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) |
2978 | { | |
2979 | struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); | |
2980 | ||
2db24e4a | 2981 | return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); |
97c12223 KB |
2982 | } |
2983 | ||
2f0dad17 KB |
2984 | static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) |
2985 | { | |
2986 | struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); | |
2987 | struct nvme_subsystem *subsys = ctrl->subsys; | |
2988 | ||
2989 | dev_err(ctrl->device, | |
2990 | "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", | |
2991 | pdev->vendor, pdev->device, | |
2992 | nvme_strlen(subsys->model, sizeof(subsys->model)), | |
2993 | subsys->model, nvme_strlen(subsys->firmware_rev, | |
2994 | sizeof(subsys->firmware_rev)), | |
2995 | subsys->firmware_rev); | |
2996 | } | |
2997 | ||
2f859441 LG |
2998 | static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) |
2999 | { | |
3000 | struct nvme_dev *dev = to_nvme_dev(ctrl); | |
3001 | ||
3002 | return dma_pci_p2pdma_supported(dev->dev); | |
3003 | } | |
3004 | ||
1c63dc66 | 3005 | static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { |
1a353d85 | 3006 | .name = "pcie", |
e439bb12 | 3007 | .module = THIS_MODULE, |
2f859441 | 3008 | .flags = NVME_F_METADATA_SUPPORTED, |
1c63dc66 | 3009 | .reg_read32 = nvme_pci_reg_read32, |
5fd4ce1b | 3010 | .reg_write32 = nvme_pci_reg_write32, |
7fd8930f | 3011 | .reg_read64 = nvme_pci_reg_read64, |
1673f1f0 | 3012 | .free_ctrl = nvme_pci_free_ctrl, |
f866fc42 | 3013 | .submit_async_event = nvme_pci_submit_async_event, |
97c12223 | 3014 | .get_address = nvme_pci_get_address, |
2f0dad17 | 3015 | .print_device_info = nvme_pci_print_device_info, |
2f859441 | 3016 | .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, |
1c63dc66 | 3017 | }; |
4cc06521 | 3018 | |
b00a726a KB |
3019 | static int nvme_dev_map(struct nvme_dev *dev) |
3020 | { | |
b00a726a KB |
3021 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
3022 | ||
a1f447b3 | 3023 | if (pci_request_mem_regions(pdev, "nvme")) |
b00a726a KB |
3024 | return -ENODEV; |
3025 | ||
97f6ef64 | 3026 | if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) |
b00a726a KB |
3027 | goto release; |
3028 | ||
9fa196e7 | 3029 | return 0; |
b00a726a | 3030 | release: |
9fa196e7 MG |
3031 | pci_release_mem_regions(pdev); |
3032 | return -ENODEV; | |
b00a726a KB |
3033 | } |
3034 | ||
8427bbc2 | 3035 | static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) |
ff5350a8 AL |
3036 | { |
3037 | if (pdev->vendor == 0x144d && pdev->device == 0xa802) { | |
3038 | /* | |
3039 | * Several Samsung devices seem to drop off the PCIe bus | |
3040 | * randomly when APST is on and uses the deepest sleep state. | |
3041 | * This has been observed on a Samsung "SM951 NVMe SAMSUNG | |
3042 | * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD | |
3043 | * 950 PRO 256GB", but it seems to be restricted to two Dell | |
3044 | * laptops. | |
3045 | */ | |
3046 | if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && | |
3047 | (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || | |
3048 | dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) | |
3049 | return NVME_QUIRK_NO_DEEPEST_PS; | |
8427bbc2 KHF |
3050 | } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { |
3051 | /* | |
3052 | * Samsung SSD 960 EVO drops off the PCIe bus after system | |
467c77d4 JJ |
3053 | * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as |
3054 | * within few minutes after bootup on a Coffee Lake board - | |
3055 | * ASUS PRIME Z370-A | |
8427bbc2 KHF |
3056 | */ |
3057 | if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && | |
467c77d4 JJ |
3058 | (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || |
3059 | dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) | |
8427bbc2 | 3060 | return NVME_QUIRK_NO_APST; |
1fae37ac S |
3061 | } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || |
3062 | pdev->device == 0xa808 || pdev->device == 0xa809)) || | |
3063 | (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { | |
3064 | /* | |
3065 | * Forcing to use host managed nvme power settings for | |
3066 | * lowest idle power with quick resume latency on | |
3067 | * Samsung and Toshiba SSDs based on suspend behavior | |
3068 | * on Coffee Lake board for LENOVO C640 | |
3069 | */ | |
3070 | if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && | |
3071 | dmi_match(DMI_BOARD_NAME, "LNVNB161216")) | |
3072 | return NVME_QUIRK_SIMPLE_SUSPEND; | |
ff5350a8 AL |
3073 | } |
3074 | ||
3075 | return 0; | |
3076 | } | |
3077 | ||
18119775 KB |
3078 | static void nvme_async_probe(void *data, async_cookie_t cookie) |
3079 | { | |
3080 | struct nvme_dev *dev = data; | |
80f513b5 | 3081 | |
bd46a906 | 3082 | flush_work(&dev->ctrl.reset_work); |
18119775 | 3083 | flush_work(&dev->ctrl.scan_work); |
80f513b5 | 3084 | nvme_put_ctrl(&dev->ctrl); |
18119775 KB |
3085 | } |
3086 | ||
8d85fce7 | 3087 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 3088 | { |
a4aea562 | 3089 | int node, result = -ENOMEM; |
b60503ba | 3090 | struct nvme_dev *dev; |
ff5350a8 | 3091 | unsigned long quirks = id->driver_data; |
943e942e | 3092 | size_t alloc_size; |
b60503ba | 3093 | |
a4aea562 MB |
3094 | node = dev_to_node(&pdev->dev); |
3095 | if (node == NUMA_NO_NODE) | |
2fa84351 | 3096 | set_dev_node(&pdev->dev, first_memory_node); |
a4aea562 MB |
3097 | |
3098 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
3099 | if (!dev) |
3100 | return -ENOMEM; | |
147b27e4 | 3101 | |
2a5bcfdd WZ |
3102 | dev->nr_write_queues = write_queues; |
3103 | dev->nr_poll_queues = poll_queues; | |
3104 | dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; | |
3105 | dev->queues = kcalloc_node(dev->nr_allocated_queues, | |
3106 | sizeof(struct nvme_queue), GFP_KERNEL, node); | |
b60503ba MW |
3107 | if (!dev->queues) |
3108 | goto free; | |
3109 | ||
e75ec752 | 3110 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 3111 | pci_set_drvdata(pdev, dev); |
1c63dc66 | 3112 | |
b00a726a KB |
3113 | result = nvme_dev_map(dev); |
3114 | if (result) | |
b00c9b7a | 3115 | goto put_pci; |
b00a726a | 3116 | |
d86c4d8e | 3117 | INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); |
5c8809e6 | 3118 | INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); |
77bf25ea | 3119 | mutex_init(&dev->shutdown_lock); |
b60503ba | 3120 | |
091b6092 MW |
3121 | result = nvme_setup_prp_pools(dev); |
3122 | if (result) | |
b00c9b7a | 3123 | goto unmap; |
4cc06521 | 3124 | |
8427bbc2 | 3125 | quirks |= check_vendor_combination_bug(pdev); |
ff5350a8 | 3126 | |
2744d7a0 | 3127 | if (!noacpi && acpi_storage_d3(&pdev->dev)) { |
df4f9bc4 DB |
3128 | /* |
3129 | * Some systems use a bios work around to ask for D3 on | |
3130 | * platforms that support kernel managed suspend. | |
3131 | */ | |
3132 | dev_info(&pdev->dev, | |
3133 | "platform quirk: setting simple suspend\n"); | |
3134 | quirks |= NVME_QUIRK_SIMPLE_SUSPEND; | |
3135 | } | |
3136 | ||
943e942e JA |
3137 | /* |
3138 | * Double check that our mempool alloc size will cover the biggest | |
3139 | * command we support. | |
3140 | */ | |
b13c6393 | 3141 | alloc_size = nvme_pci_iod_alloc_size(); |
943e942e JA |
3142 | WARN_ON_ONCE(alloc_size > PAGE_SIZE); |
3143 | ||
3144 | dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, | |
3145 | mempool_kfree, | |
3146 | (void *) alloc_size, | |
3147 | GFP_KERNEL, node); | |
3148 | if (!dev->iod_mempool) { | |
3149 | result = -ENOMEM; | |
3150 | goto release_pools; | |
3151 | } | |
3152 | ||
b6e44b4c KB |
3153 | result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, |
3154 | quirks); | |
3155 | if (result) | |
3156 | goto release_mempool; | |
3157 | ||
1b3c47c1 SG |
3158 | dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); |
3159 | ||
bd46a906 | 3160 | nvme_reset_ctrl(&dev->ctrl); |
18119775 | 3161 | async_schedule(nvme_async_probe, dev); |
4caff8fc | 3162 | |
b60503ba MW |
3163 | return 0; |
3164 | ||
b6e44b4c KB |
3165 | release_mempool: |
3166 | mempool_destroy(dev->iod_mempool); | |
0877cb0d | 3167 | release_pools: |
091b6092 | 3168 | nvme_release_prp_pools(dev); |
b00c9b7a CJ |
3169 | unmap: |
3170 | nvme_dev_unmap(dev); | |
a96d4f5c | 3171 | put_pci: |
e75ec752 | 3172 | put_device(dev->dev); |
b60503ba MW |
3173 | free: |
3174 | kfree(dev->queues); | |
b60503ba MW |
3175 | kfree(dev); |
3176 | return result; | |
3177 | } | |
3178 | ||
775755ed | 3179 | static void nvme_reset_prepare(struct pci_dev *pdev) |
f0d54a54 | 3180 | { |
a6739479 | 3181 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
c1ac9a4b KB |
3182 | |
3183 | /* | |
3184 | * We don't need to check the return value from waiting for the reset | |
3185 | * state as pci_dev device lock is held, making it impossible to race | |
3186 | * with ->remove(). | |
3187 | */ | |
3188 | nvme_disable_prepare_reset(dev, false); | |
3189 | nvme_sync_queues(&dev->ctrl); | |
775755ed | 3190 | } |
f0d54a54 | 3191 | |
775755ed CH |
3192 | static void nvme_reset_done(struct pci_dev *pdev) |
3193 | { | |
f263fbb8 | 3194 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
c1ac9a4b KB |
3195 | |
3196 | if (!nvme_try_sched_reset(&dev->ctrl)) | |
3197 | flush_work(&dev->ctrl.reset_work); | |
f0d54a54 KB |
3198 | } |
3199 | ||
09ece142 KB |
3200 | static void nvme_shutdown(struct pci_dev *pdev) |
3201 | { | |
3202 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
4e523547 | 3203 | |
c1ac9a4b | 3204 | nvme_disable_prepare_reset(dev, true); |
09ece142 KB |
3205 | } |
3206 | ||
0521905e KB |
3207 | static void nvme_remove_attrs(struct nvme_dev *dev) |
3208 | { | |
3209 | if (dev->attrs_added) | |
3210 | sysfs_remove_group(&dev->ctrl.device->kobj, | |
3211 | &nvme_pci_attr_group); | |
3212 | } | |
3213 | ||
f58944e2 KB |
3214 | /* |
3215 | * The driver's remove may be called on a device in a partially initialized | |
3216 | * state. This function must not have any dependencies on the device state in | |
3217 | * order to proceed. | |
3218 | */ | |
8d85fce7 | 3219 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3220 | { |
3221 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 | 3222 | |
bb8d261e | 3223 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); |
9a6b9458 | 3224 | pci_set_drvdata(pdev, NULL); |
0ff9d4e1 | 3225 | |
6db28eda | 3226 | if (!pci_device_is_present(pdev)) { |
0ff9d4e1 | 3227 | nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); |
1d39e692 | 3228 | nvme_dev_disable(dev, true); |
6db28eda | 3229 | } |
0ff9d4e1 | 3230 | |
d86c4d8e | 3231 | flush_work(&dev->ctrl.reset_work); |
d09f2b45 SG |
3232 | nvme_stop_ctrl(&dev->ctrl); |
3233 | nvme_remove_namespaces(&dev->ctrl); | |
a5cdb68c | 3234 | nvme_dev_disable(dev, true); |
0521905e | 3235 | nvme_remove_attrs(dev); |
87ad72a5 | 3236 | nvme_free_host_mem(dev); |
a4aea562 | 3237 | nvme_dev_remove_admin(dev); |
a1a5ef99 | 3238 | nvme_free_queues(dev, 0); |
9a6b9458 | 3239 | nvme_release_prp_pools(dev); |
b00a726a | 3240 | nvme_dev_unmap(dev); |
726612b6 | 3241 | nvme_uninit_ctrl(&dev->ctrl); |
b60503ba MW |
3242 | } |
3243 | ||
671a6018 | 3244 | #ifdef CONFIG_PM_SLEEP |
d916b1be KB |
3245 | static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) |
3246 | { | |
3247 | return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); | |
3248 | } | |
3249 | ||
3250 | static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) | |
3251 | { | |
3252 | return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); | |
3253 | } | |
3254 | ||
3255 | static int nvme_resume(struct device *dev) | |
3256 | { | |
3257 | struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); | |
3258 | struct nvme_ctrl *ctrl = &ndev->ctrl; | |
3259 | ||
4eaefe8c | 3260 | if (ndev->last_ps == U32_MAX || |
d916b1be | 3261 | nvme_set_power_state(ctrl, ndev->last_ps) != 0) |
e5ad96f3 KB |
3262 | goto reset; |
3263 | if (ctrl->hmpre && nvme_setup_host_mem(ndev)) | |
3264 | goto reset; | |
3265 | ||
d916b1be | 3266 | return 0; |
e5ad96f3 KB |
3267 | reset: |
3268 | return nvme_try_sched_reset(ctrl); | |
d916b1be KB |
3269 | } |
3270 | ||
cd638946 KB |
3271 | static int nvme_suspend(struct device *dev) |
3272 | { | |
3273 | struct pci_dev *pdev = to_pci_dev(dev); | |
3274 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
d916b1be KB |
3275 | struct nvme_ctrl *ctrl = &ndev->ctrl; |
3276 | int ret = -EBUSY; | |
3277 | ||
4eaefe8c RW |
3278 | ndev->last_ps = U32_MAX; |
3279 | ||
d916b1be KB |
3280 | /* |
3281 | * The platform does not remove power for a kernel managed suspend so | |
3282 | * use host managed nvme power settings for lowest idle power if | |
3283 | * possible. This should have quicker resume latency than a full device | |
3284 | * shutdown. But if the firmware is involved after the suspend or the | |
3285 | * device does not support any non-default power states, shut down the | |
3286 | * device fully. | |
4eaefe8c RW |
3287 | * |
3288 | * If ASPM is not enabled for the device, shut down the device and allow | |
3289 | * the PCI bus layer to put it into D3 in order to take the PCIe link | |
3290 | * down, so as to allow the platform to achieve its minimum low-power | |
3291 | * state (which may not be possible if the link is up). | |
d916b1be | 3292 | */ |
4eaefe8c | 3293 | if (pm_suspend_via_firmware() || !ctrl->npss || |
cb32de1b | 3294 | !pcie_aspm_enabled(pdev) || |
c1ac9a4b KB |
3295 | (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) |
3296 | return nvme_disable_prepare_reset(ndev, true); | |
d916b1be KB |
3297 | |
3298 | nvme_start_freeze(ctrl); | |
3299 | nvme_wait_freeze(ctrl); | |
3300 | nvme_sync_queues(ctrl); | |
3301 | ||
5d02a5c1 | 3302 | if (ctrl->state != NVME_CTRL_LIVE) |
d916b1be KB |
3303 | goto unfreeze; |
3304 | ||
e5ad96f3 KB |
3305 | /* |
3306 | * Host memory access may not be successful in a system suspend state, | |
3307 | * but the specification allows the controller to access memory in a | |
3308 | * non-operational power state. | |
3309 | */ | |
3310 | if (ndev->hmb) { | |
3311 | ret = nvme_set_host_mem(ndev, 0); | |
3312 | if (ret < 0) | |
3313 | goto unfreeze; | |
3314 | } | |
3315 | ||
d916b1be KB |
3316 | ret = nvme_get_power_state(ctrl, &ndev->last_ps); |
3317 | if (ret < 0) | |
3318 | goto unfreeze; | |
3319 | ||
7cbb5c6f ML |
3320 | /* |
3321 | * A saved state prevents pci pm from generically controlling the | |
3322 | * device's power. If we're using protocol specific settings, we don't | |
3323 | * want pci interfering. | |
3324 | */ | |
3325 | pci_save_state(pdev); | |
3326 | ||
d916b1be KB |
3327 | ret = nvme_set_power_state(ctrl, ctrl->npss); |
3328 | if (ret < 0) | |
3329 | goto unfreeze; | |
3330 | ||
3331 | if (ret) { | |
7cbb5c6f ML |
3332 | /* discard the saved state */ |
3333 | pci_load_saved_state(pdev, NULL); | |
3334 | ||
d916b1be KB |
3335 | /* |
3336 | * Clearing npss forces a controller reset on resume. The | |
05d3046f | 3337 | * correct value will be rediscovered then. |
d916b1be | 3338 | */ |
c1ac9a4b | 3339 | ret = nvme_disable_prepare_reset(ndev, true); |
d916b1be | 3340 | ctrl->npss = 0; |
d916b1be | 3341 | } |
d916b1be KB |
3342 | unfreeze: |
3343 | nvme_unfreeze(ctrl); | |
3344 | return ret; | |
3345 | } | |
3346 | ||
3347 | static int nvme_simple_suspend(struct device *dev) | |
3348 | { | |
3349 | struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); | |
4e523547 | 3350 | |
c1ac9a4b | 3351 | return nvme_disable_prepare_reset(ndev, true); |
cd638946 KB |
3352 | } |
3353 | ||
d916b1be | 3354 | static int nvme_simple_resume(struct device *dev) |
cd638946 KB |
3355 | { |
3356 | struct pci_dev *pdev = to_pci_dev(dev); | |
3357 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3358 | |
c1ac9a4b | 3359 | return nvme_try_sched_reset(&ndev->ctrl); |
cd638946 KB |
3360 | } |
3361 | ||
21774222 | 3362 | static const struct dev_pm_ops nvme_dev_pm_ops = { |
d916b1be KB |
3363 | .suspend = nvme_suspend, |
3364 | .resume = nvme_resume, | |
3365 | .freeze = nvme_simple_suspend, | |
3366 | .thaw = nvme_simple_resume, | |
3367 | .poweroff = nvme_simple_suspend, | |
3368 | .restore = nvme_simple_resume, | |
3369 | }; | |
3370 | #endif /* CONFIG_PM_SLEEP */ | |
b60503ba | 3371 | |
a0a3408e KB |
3372 | static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, |
3373 | pci_channel_state_t state) | |
3374 | { | |
3375 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3376 | ||
3377 | /* | |
3378 | * A frozen channel requires a reset. When detected, this method will | |
3379 | * shutdown the controller to quiesce. The controller will be restarted | |
3380 | * after the slot reset through driver's slot_reset callback. | |
3381 | */ | |
a0a3408e KB |
3382 | switch (state) { |
3383 | case pci_channel_io_normal: | |
3384 | return PCI_ERS_RESULT_CAN_RECOVER; | |
3385 | case pci_channel_io_frozen: | |
d011fb31 KB |
3386 | dev_warn(dev->ctrl.device, |
3387 | "frozen state error detected, reset controller\n"); | |
a5cdb68c | 3388 | nvme_dev_disable(dev, false); |
a0a3408e KB |
3389 | return PCI_ERS_RESULT_NEED_RESET; |
3390 | case pci_channel_io_perm_failure: | |
d011fb31 KB |
3391 | dev_warn(dev->ctrl.device, |
3392 | "failure state error detected, request disconnect\n"); | |
a0a3408e KB |
3393 | return PCI_ERS_RESULT_DISCONNECT; |
3394 | } | |
3395 | return PCI_ERS_RESULT_NEED_RESET; | |
3396 | } | |
3397 | ||
3398 | static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) | |
3399 | { | |
3400 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3401 | ||
1b3c47c1 | 3402 | dev_info(dev->ctrl.device, "restart after slot reset\n"); |
a0a3408e | 3403 | pci_restore_state(pdev); |
d86c4d8e | 3404 | nvme_reset_ctrl(&dev->ctrl); |
a0a3408e KB |
3405 | return PCI_ERS_RESULT_RECOVERED; |
3406 | } | |
3407 | ||
3408 | static void nvme_error_resume(struct pci_dev *pdev) | |
3409 | { | |
72cd4cc2 KB |
3410 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
3411 | ||
3412 | flush_work(&dev->ctrl.reset_work); | |
a0a3408e KB |
3413 | } |
3414 | ||
1d352035 | 3415 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba | 3416 | .error_detected = nvme_error_detected, |
b60503ba MW |
3417 | .slot_reset = nvme_slot_reset, |
3418 | .resume = nvme_error_resume, | |
775755ed CH |
3419 | .reset_prepare = nvme_reset_prepare, |
3420 | .reset_done = nvme_reset_done, | |
b60503ba MW |
3421 | }; |
3422 | ||
6eb0d698 | 3423 | static const struct pci_device_id nvme_id_table[] = { |
972b13e2 | 3424 | { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ |
08095e70 | 3425 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 3426 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
972b13e2 | 3427 | { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ |
99466e70 | 3428 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
e850fd16 | 3429 | NVME_QUIRK_DEALLOCATE_ZEROES, }, |
972b13e2 | 3430 | { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ |
99466e70 | 3431 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
25e58af4 WZ |
3432 | NVME_QUIRK_DEALLOCATE_ZEROES | |
3433 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
972b13e2 | 3434 | { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ |
f99cb7af DWF |
3435 | .driver_data = NVME_QUIRK_STRIPE_SIZE | |
3436 | NVME_QUIRK_DEALLOCATE_ZEROES, }, | |
50af47d0 | 3437 | { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ |
9abd68ef | 3438 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | |
6c6aa2f2 | 3439 | NVME_QUIRK_MEDIUM_PRIO_SQ | |
ce4cc313 DM |
3440 | NVME_QUIRK_NO_TEMP_THRESH_CHANGE | |
3441 | NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
6299358d JD |
3442 | { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ |
3443 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
540c801c | 3444 | { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ |
7b210e4e | 3445 | .driver_data = NVME_QUIRK_IDENTIFY_CNS | |
66dd346b CH |
3446 | NVME_QUIRK_DISABLE_WRITE_ZEROES | |
3447 | NVME_QUIRK_BOGUS_NID, }, | |
3448 | { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ | |
3449 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
5bedd3af | 3450 | { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ |
c98a8793 KB |
3451 | .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | |
3452 | NVME_QUIRK_BOGUS_NID, }, | |
0302ae60 | 3453 | { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ |
5e112d3f JE |
3454 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | |
3455 | NVME_QUIRK_NO_NS_DESC_LIST, }, | |
54adc010 GP |
3456 | { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ |
3457 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
8c97eecc JL |
3458 | { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ |
3459 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
015282c9 WW |
3460 | { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ |
3461 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
d554b5e1 MP |
3462 | { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ |
3463 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, | |
3464 | { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ | |
7ee5c78c | 3465 | .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | |
abbb5f59 | 3466 | NVME_QUIRK_DISABLE_WRITE_ZEROES| |
7ee5c78c | 3467 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, |
2cf7a77e KB |
3468 | { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ |
3469 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
c9e95c39 | 3470 | { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ |
73029c9b KB |
3471 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | |
3472 | NVME_QUIRK_BOGUS_NID, }, | |
6e6a6828 PT |
3473 | { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ |
3474 | .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | | |
3475 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
e1c70d79 LVS |
3476 | { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ |
3477 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
08b903b5 | 3478 | { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ |
1629de0e PG |
3479 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | |
3480 | NVME_QUIRK_BOGUS_NID, }, | |
f03e42c6 GC |
3481 | { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ |
3482 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS | | |
3483 | NVME_QUIRK_IGNORE_DEV_SUBNQN, }, | |
41f38043 LS |
3484 | { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ |
3485 | .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, | |
5611ec2b KHF |
3486 | { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ |
3487 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
c4f01a77 KB |
3488 | { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ |
3489 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
02ca079c KHF |
3490 | { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ |
3491 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
89919929 CK |
3492 | { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ |
3493 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
43047e08 | 3494 | { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ |
3495 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3496 | { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ | |
3497 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3498 | { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ | |
3499 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
3500 | { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ | |
3501 | .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, | |
dc22c1c0 ZB |
3502 | { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ |
3503 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
538e4a8c TL |
3504 | { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ |
3505 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
70ce3455 CH |
3506 | { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ |
3507 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
a98a945b CH |
3508 | { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ |
3509 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
3510 | { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ | |
3511 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
3765fad5 SR |
3512 | { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ |
3513 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
f37527a0 DK |
3514 | { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ |
3515 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
6b961bce NW |
3516 | { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ |
3517 | .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, | |
d6c52fa3 TG |
3518 | { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ |
3519 | .driver_data = NVME_QUIRK_BOGUS_NID, }, | |
4bdf2603 FS |
3520 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), |
3521 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3522 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), | |
3523 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3524 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), | |
3525 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3526 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), | |
3527 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3528 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), | |
3529 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
3530 | { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), | |
3531 | .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, | |
98f7b86a AS |
3532 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), |
3533 | .driver_data = NVME_QUIRK_SINGLE_VECTOR }, | |
124298bd | 3534 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, |
66341331 BH |
3535 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), |
3536 | .driver_data = NVME_QUIRK_SINGLE_VECTOR | | |
d38e9f04 | 3537 | NVME_QUIRK_128_BYTES_SQES | |
a2941f6a KB |
3538 | NVME_QUIRK_SHARED_TAGS | |
3539 | NVME_QUIRK_SKIP_CID_GEN }, | |
0b85f59d | 3540 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
b60503ba MW |
3541 | { 0, } |
3542 | }; | |
3543 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3544 | ||
3545 | static struct pci_driver nvme_driver = { | |
3546 | .name = "nvme", | |
3547 | .id_table = nvme_id_table, | |
3548 | .probe = nvme_probe, | |
8d85fce7 | 3549 | .remove = nvme_remove, |
09ece142 | 3550 | .shutdown = nvme_shutdown, |
d916b1be | 3551 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3552 | .driver = { |
3553 | .pm = &nvme_dev_pm_ops, | |
3554 | }, | |
d916b1be | 3555 | #endif |
74d986ab | 3556 | .sriov_configure = pci_sriov_configure_simple, |
b60503ba MW |
3557 | .err_handler = &nvme_err_handler, |
3558 | }; | |
3559 | ||
3560 | static int __init nvme_init(void) | |
3561 | { | |
81101540 CH |
3562 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); |
3563 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
3564 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
612b7286 | 3565 | BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); |
17c33167 | 3566 | |
9a6327d2 | 3567 | return pci_register_driver(&nvme_driver); |
b60503ba MW |
3568 | } |
3569 | ||
3570 | static void __exit nvme_exit(void) | |
3571 | { | |
3572 | pci_unregister_driver(&nvme_driver); | |
03e0f3a6 | 3573 | flush_workqueue(nvme_wq); |
b60503ba MW |
3574 | } |
3575 | ||
3576 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3577 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3578 | MODULE_VERSION("1.0"); |
b60503ba MW |
3579 | module_init(nvme_init); |
3580 | module_exit(nvme_exit); |