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nvme-pci: cleanup nvme_suspend_queue
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
99722c8a 18#include <linux/kstrtox.h>
dc90f084 19#include <linux/memremap.h>
b60503ba
MW		 20#include <linux/mm.h>
21#include <linux/module.h>
77bf25ea 22#include <linux/mutex.h>
d0877473 23#include <linux/once.h>
b60503ba 24#include <linux/pci.h>
d916b1be 25#include <linux/suspend.h>
e1e5e564 26#include <linux/t10-pi.h>
b60503ba 27#include <linux/types.h>
2f8e2c87 28#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 29#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 30#include <linux/sed-opal.h>
0f238ff5 31#include <linux/pci-p2pdma.h>
797a796a 32
604c01d5 33#include "trace.h"
f11bb3e2
CH		 34#include "nvme.h"
35
c1e0cc7e 36#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 37#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 38
a7a7cbe3 39#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 40
943e942e
JA		 41/*
42 * These can be higher, but we need to ensure that any command doesn't
43 * require an sg allocation that needs more than a page of data.
44 */
45#define NVME_MAX_KB_SZ 4096
46#define NVME_MAX_SEGS 127
47
58ffacb5 48static int use_threaded_interrupts;
2e21e445 49module_param(use_threaded_interrupts, int, 0444);
58ffacb5 50
8ffaadf7 51static bool use_cmb_sqes = true;
69f4eb9f 52module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 53MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
87ad72a5
CH		 55static unsigned int max_host_mem_size_mb = 128;
56module_param(max_host_mem_size_mb, uint, 0444);
57MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 59
a7a7cbe3
CK		 60static unsigned int sgl_threshold = SZ_32K;
61module_param(sgl_threshold, uint, 0644);
62MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
27453b45
SG		 66#define NVME_PCI_MIN_QUEUE_SIZE 2
67#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 68static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
61f3b896 71 .get = param_get_uint,
b27c1e68 72};
73
61f3b896 74static unsigned int io_queue_depth = 1024;
b27c1e68 75module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 76MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 77
9c9e76d5
WZ		 78static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79{
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87}
88
89static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92};
93
3f68baf7 94static unsigned int write_queues;
9c9e76d5 95module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 96MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
3f68baf7 100static unsigned int poll_queues;
9c9e76d5 101module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 102MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
df4f9bc4
DB		 104static bool noacpi;
105module_param(noacpi, bool, 0444);
106MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
1c63dc66
CH		 108struct nvme_dev;
109struct nvme_queue;
b3fffdef 110
a5cdb68c 111static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 112static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 113
1c63dc66
CH		 114/*
115 * Represents an NVM Express device. Each nvme_dev is a PCI function.
116 */
117struct nvme_dev {
147b27e4 118 struct nvme_queue *queues;
1c63dc66
CH		 119 struct blk_mq_tag_set tagset;
120 struct blk_mq_tag_set admin_tagset;
121 u32 __iomem *dbs;
122 struct device *dev;
123 struct dma_pool *prp_page_pool;
124 struct dma_pool *prp_small_pool;
1c63dc66
CH		 125 unsigned online_queues;
126 unsigned max_qid;
e20ba6e1 127 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 128 unsigned int num_vecs;
7442ddce 129 u32 q_depth;
c1e0cc7e 130 int io_sqes;
1c63dc66 131 u32 db_stride;
1c63dc66 132 void __iomem *bar;
97f6ef64 133 unsigned long bar_mapped_size;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
f9f38e33
HK		 147 u32 *dbbuf_dbs;
148 dma_addr_t dbbuf_dbs_dma_addr;
149 u32 *dbbuf_eis;
150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
4d115420 161};
1fa6aead 162
b27c1e68 163static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
164{
27453b45
SG		 165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 167}
168
f9f38e33
HK		 169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
1c63dc66
CH		 179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
b60503ba
MW		 184/*
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
187 */
188struct nvme_queue {
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
c1e0cc7e 191 void *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 194 struct nvme_completion *cqes;
b60503ba
MW		 195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
b60503ba 197 u32 __iomem *q_db;
7442ddce 198 u32 q_depth;
7c349dde 199 u16 cq_vector;
b60503ba 200 u16 sq_tail;
38210800 201 u16 last_sq_tail;
b60503ba 202 u16 cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
c1e0cc7e 205 u8 sqes;
4e224106
CH		 206 unsigned long flags;
207#define NVMEQ_ENABLED 0
63223078 208#define NVMEQ_SQ_CMB 1
d1ed6aa1 209#define NVMEQ_DELETE_ERROR 2
7c349dde 210#define NVMEQ_POLLED 3
f9f38e33
HK		 211 u32 *dbbuf_sq_db;
212 u32 *dbbuf_cq_db;
213 u32 *dbbuf_sq_ei;
214 u32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c 218/*
9b048119
CH		 219 * The nvme_iod describes the data in an I/O.
220 *
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
71bd150c
CH		 223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
af7fae85 226 struct nvme_command cmd;
a7a7cbe3 227 bool use_sgl;
52da4f3f 228 bool aborted;
c372cdd1
KB		 229 s8 nr_allocations; /* PRP list pool allocations. 0 means small
230 pool in use */
dff824b2 231 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 232 dma_addr_t first_dma;
783b94bd 233 dma_addr_t meta_dma;
91fb2b60 234 struct sg_table sgt;
b60503ba
MW		 235};
236
2a5bcfdd 237static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 238{
2a5bcfdd 239 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 240}
241
65a54646 242static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
f9f38e33 243{
2a5bcfdd 244 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 245
65a54646
CH		 246 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
247 return;
248
58847f12
KB		 249 if (dev->dbbuf_dbs) {
250 /*
251 * Clear the dbbuf memory so the driver doesn't observe stale
252 * values from the previous instantiation.
253 */
254 memset(dev->dbbuf_dbs, 0, mem_size);
255 memset(dev->dbbuf_eis, 0, mem_size);
65a54646 256 return;
58847f12 257 }
f9f38e33
HK		 258
259 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
260 &dev->dbbuf_dbs_dma_addr,
261 GFP_KERNEL);
262 if (!dev->dbbuf_dbs)
65a54646 263 goto fail;
f9f38e33
HK		 264 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
265 &dev->dbbuf_eis_dma_addr,
266 GFP_KERNEL);
65a54646
CH		 267 if (!dev->dbbuf_eis)
268 goto fail_free_dbbuf_dbs;
269 return;
f9f38e33 270
65a54646
CH		 271fail_free_dbbuf_dbs:
272 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
273 dev->dbbuf_dbs_dma_addr);
274 dev->dbbuf_dbs = NULL;
275fail:
276 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
f9f38e33
HK		 277}
278
279static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
280{
2a5bcfdd 281 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 282
283 if (dev->dbbuf_dbs) {
284 dma_free_coherent(dev->dev, mem_size,
285 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
286 dev->dbbuf_dbs = NULL;
287 }
288 if (dev->dbbuf_eis) {
289 dma_free_coherent(dev->dev, mem_size,
290 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
291 dev->dbbuf_eis = NULL;
292 }
293}
294
295static void nvme_dbbuf_init(struct nvme_dev *dev,
296 struct nvme_queue *nvmeq, int qid)
297{
298 if (!dev->dbbuf_dbs || !qid)
299 return;
300
301 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
302 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
303 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
304 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
305}
306
0f0d2c87
MI		 307static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
308{
309 if (!nvmeq->qid)
310 return;
311
312 nvmeq->dbbuf_sq_db = NULL;
313 nvmeq->dbbuf_cq_db = NULL;
314 nvmeq->dbbuf_sq_ei = NULL;
315 nvmeq->dbbuf_cq_ei = NULL;
316}
317
f9f38e33
HK		 318static void nvme_dbbuf_set(struct nvme_dev *dev)
319{
f66e2804 320 struct nvme_command c = { };
0f0d2c87 321 unsigned int i;
f9f38e33
HK		 322
323 if (!dev->dbbuf_dbs)
324 return;
325
f9f38e33
HK		 326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
329
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 334
335 for (i = 1; i <= dev->online_queues; i++)
336 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 337 }
338}
339
340static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
341{
342 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
343}
344
345/* Update dbbuf and return true if an MMIO is required */
346static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
347 volatile u32 *dbbuf_ei)
348{
349 if (dbbuf_db) {
350 u16 old_value;
351
352 /*
353 * Ensure that the queue is written before updating
354 * the doorbell in memory
355 */
356 wmb();
357
358 old_value = *dbbuf_db;
359 *dbbuf_db = value;
360
f1ed3df2
MW		 361 /*
362 * Ensure that the doorbell is updated before reading the event
363 * index from memory. The controller needs to provide similar
364 * ordering to ensure the envent index is updated before reading
365 * the doorbell.
366 */
367 mb();
368
f9f38e33
HK		 369 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
370 return false;
371 }
372
373 return true;
b60503ba
MW		 374}
375
ac3dd5bd
JA		 376/*
377 * Will slightly overestimate the number of pages needed. This is OK
378 * as it only leads to a small amount of wasted memory for the lifetime of
379 * the I/O.
380 */
b13c6393 381static int nvme_pci_npages_prp(void)
ac3dd5bd 382{
b13c6393 383 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 384 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 385 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
386}
387
a7a7cbe3
CK		 388/*
389 * Calculates the number of pages needed for the SGL segments. For example a 4k
390 * page can accommodate 256 SGL descriptors.
391 */
b13c6393 392static int nvme_pci_npages_sgl(void)
ac3dd5bd 393{
b13c6393
CK		 394 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
395 PAGE_SIZE);
f4800d6d 396}
ac3dd5bd 397
a4aea562
MB		 398static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
399 unsigned int hctx_idx)
e85248e5 400{
a4aea562 401 struct nvme_dev *dev = data;
147b27e4 402 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 403
42483228
KB		 404 WARN_ON(hctx_idx != 0);
405 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 406
a4aea562
MB		 407 hctx->driver_data = nvmeq;
408 return 0;
e85248e5
MW		 409}
410
a4aea562
MB		 411static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
412 unsigned int hctx_idx)
b60503ba 413{
a4aea562 414 struct nvme_dev *dev = data;
147b27e4 415 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 416
42483228 417 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 418 hctx->driver_data = nvmeq;
419 return 0;
b60503ba
MW		 420}
421
e559398f
CH		 422static int nvme_pci_init_request(struct blk_mq_tag_set *set,
423 struct request *req, unsigned int hctx_idx,
424 unsigned int numa_node)
b60503ba 425{
d6296d39 426 struct nvme_dev *dev = set->driver_data;
f4800d6d 427 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 428
429 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 430 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 431 return 0;
432}
433
3b6592f7
JA		 434static int queue_irq_offset(struct nvme_dev *dev)
435{
436 /* if we have more than 1 vec, admin queue offsets us by 1 */
437 if (dev->num_vecs > 1)
438 return 1;
439
440 return 0;
441}
442
a4e1d0b7 443static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78
CH		 444{
445 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 446 int i, qoff, offset;
447
448 offset = queue_irq_offset(dev);
449 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
450 struct blk_mq_queue_map *map = &set->map[i];
451
452 map->nr_queues = dev->io_queues[i];
453 if (!map->nr_queues) {
e20ba6e1 454 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 455 continue;
3b6592f7
JA		 456 }
457
4b04cc6a
JA		 458 /*
459 * The poll queue(s) doesn't have an IRQ (and hence IRQ
460 * affinity), so use the regular blk-mq cpu mapping
461 */
3b6592f7 462 map->queue_offset = qoff;
cb9e0e50 463 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 464 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
465 else
466 blk_mq_map_queues(map);
3b6592f7
JA		 467 qoff += map->nr_queues;
468 offset += map->nr_queues;
469 }
dca51e78
CH		 470}
471
38210800
KB		 472/*
473 * Write sq tail if we are asked to, or if the next command would wrap.
474 */
475static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 476{
38210800
KB		 477 if (!write_sq) {
478 u16 next_tail = nvmeq->sq_tail + 1;
479
480 if (next_tail == nvmeq->q_depth)
481 next_tail = 0;
482 if (next_tail != nvmeq->last_sq_tail)
483 return;
484 }
485
04f3eafd
JA		 486 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
487 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
488 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 489 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 490}
491
3233b94c
JA		 492static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
493 struct nvme_command *cmd)
b60503ba 494{
c1e0cc7e 495 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 496 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 497 if (++nvmeq->sq_tail == nvmeq->q_depth)
498 nvmeq->sq_tail = 0;
04f3eafd
JA		 499}
500
501static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
502{
503 struct nvme_queue *nvmeq = hctx->driver_data;
504
505 spin_lock(&nvmeq->sq_lock);
38210800
KB		 506 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
507 nvme_write_sq_db(nvmeq, true);
90ea5ca4 508 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 509}
510
a7a7cbe3 511static void **nvme_pci_iod_list(struct request *req)
b60503ba 512{
f4800d6d 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
91fb2b60 514 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
b60503ba
MW		 515}
516
955b1b5a
MI		 517static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
518{
a53232cb 519 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
20469a37 520 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 521 unsigned int avg_seg_size;
522
20469a37 523 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 524
253a0b76 525 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 526 return false;
a53232cb 527 if (!nvmeq->qid)
955b1b5a
MI		 528 return false;
529 if (!sgl_threshold || avg_seg_size < sgl_threshold)
530 return false;
531 return true;
532}
533
9275c206 534static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 535{
6c3c05b0 536 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 537 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
538 dma_addr_t dma_addr = iod->first_dma;
eca18b23 539 int i;
eca18b23 540
c372cdd1 541 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 542 __le64 *prp_list = nvme_pci_iod_list(req)[i];
543 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
544
545 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
546 dma_addr = next_dma_addr;
7fe07d14 547 }
9275c206 548}
dff824b2 549
9275c206
CH		 550static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
551{
552 const int last_sg = SGES_PER_PAGE - 1;
553 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
554 dma_addr_t dma_addr = iod->first_dma;
555 int i;
dff824b2 556
c372cdd1 557 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 558 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
559 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 560
9275c206
CH		 561 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
562 dma_addr = next_dma_addr;
563 }
9275c206 564}
a7a7cbe3 565
9275c206
CH		 566static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
567{
568 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 569
9275c206
CH		 570 if (iod->dma_len) {
571 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
572 rq_dma_dir(req));
573 return;
eca18b23 574 }
ac3dd5bd 575
91fb2b60
LG		 576 WARN_ON_ONCE(!iod->sgt.nents);
577
578 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 579
c372cdd1 580 if (iod->nr_allocations == 0)
9275c206
CH		 581 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
582 iod->first_dma);
583 else if (iod->use_sgl)
584 nvme_free_sgls(dev, req);
585 else
586 nvme_free_prps(dev, req);
91fb2b60 587 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 588}
589
d0877473
KB		 590static void nvme_print_sgl(struct scatterlist *sgl, int nents)
591{
592 int i;
593 struct scatterlist *sg;
594
595 for_each_sg(sgl, sg, nents, i) {
596 dma_addr_t phys = sg_phys(sg);
597 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
598 "dma_address:%pad dma_length:%d\n",
599 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
600 sg_dma_len(sg));
601 }
602}
603
a7a7cbe3
CK		 604static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
605 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 606{
f4800d6d 607 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 608 struct dma_pool *pool;
b131c61d 609 int length = blk_rq_payload_bytes(req);
91fb2b60 610 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 611 int dma_len = sg_dma_len(sg);
612 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 613 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 614 __le64 *prp_list;
a7a7cbe3 615 void **list = nvme_pci_iod_list(req);
e025344c 616 dma_addr_t prp_dma;
eca18b23 617 int nprps, i;
ff22b54f 618
6c3c05b0 619 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 620 if (length <= 0) {
621 iod->first_dma = 0;
a7a7cbe3 622 goto done;
5228b328 623 }
ff22b54f 624
6c3c05b0 625 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 626 if (dma_len) {
6c3c05b0 627 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 628 } else {
629 sg = sg_next(sg);
630 dma_addr = sg_dma_address(sg);
631 dma_len = sg_dma_len(sg);
632 }
633
6c3c05b0 634 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 635 iod->first_dma = dma_addr;
a7a7cbe3 636 goto done;
e025344c
SMM		 637 }
638
6c3c05b0 639 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 640 if (nprps <= (256 / 8)) {
641 pool = dev->prp_small_pool;
c372cdd1 642 iod->nr_allocations = 0;
99802a7a
MW		 643 } else {
644 pool = dev->prp_page_pool;
c372cdd1 645 iod->nr_allocations = 1;
99802a7a
MW		 646 }
647
69d2b571 648 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 649 if (!prp_list) {
c372cdd1 650 iod->nr_allocations = -1;
86eea289 651 return BLK_STS_RESOURCE;
b77954cb 652 }
eca18b23
MW		 653 list[0] = prp_list;
654 iod->first_dma = prp_dma;
e025344c
SMM		 655 i = 0;
656 for (;;) {
6c3c05b0 657 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 658 __le64 *old_prp_list = prp_list;
69d2b571 659 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 660 if (!prp_list)
fa073216 661 goto free_prps;
c372cdd1 662 list[iod->nr_allocations++] = prp_list;
7523d834
MW		 663 prp_list[0] = old_prp_list[i - 1];
664 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
665 i = 1;
e025344c
SMM		 666 }
667 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 668 dma_len -= NVME_CTRL_PAGE_SIZE;
669 dma_addr += NVME_CTRL_PAGE_SIZE;
670 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 671 if (length <= 0)
672 break;
673 if (dma_len > 0)
674 continue;
86eea289
KB		 675 if (unlikely(dma_len < 0))
676 goto bad_sgl;
e025344c
SMM		 677 sg = sg_next(sg);
678 dma_addr = sg_dma_address(sg);
679 dma_len = sg_dma_len(sg);
ff22b54f 680 }
a7a7cbe3 681done:
91fb2b60 682 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 683 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 684 return BLK_STS_OK;
fa073216
CH		 685free_prps:
686 nvme_free_prps(dev, req);
687 return BLK_STS_RESOURCE;
688bad_sgl:
91fb2b60 689 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 690 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 691 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 692 return BLK_STS_IOERR;
ff22b54f
MW		 693}
694
a7a7cbe3
CK		 695static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
696 struct scatterlist *sg)
697{
698 sge->addr = cpu_to_le64(sg_dma_address(sg));
699 sge->length = cpu_to_le32(sg_dma_len(sg));
700 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
701}
702
703static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
704 dma_addr_t dma_addr, int entries)
705{
706 sge->addr = cpu_to_le64(dma_addr);
707 if (entries < SGES_PER_PAGE) {
708 sge->length = cpu_to_le32(entries * sizeof(*sge));
709 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
710 } else {
711 sge->length = cpu_to_le32(PAGE_SIZE);
712 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
713 }
714}
715
716static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 717 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 718{
719 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 720 struct dma_pool *pool;
721 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 722 struct scatterlist *sg = iod->sgt.sgl;
723 unsigned int entries = iod->sgt.nents;
a7a7cbe3 724 dma_addr_t sgl_dma;
b0f2853b 725 int i = 0;
a7a7cbe3 726
a7a7cbe3
CK		 727 /* setting the transfer type as SGL */
728 cmd->flags = NVME_CMD_SGL_METABUF;
729
b0f2853b 730 if (entries == 1) {
a7a7cbe3
CK		 731 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
732 return BLK_STS_OK;
733 }
734
735 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
736 pool = dev->prp_small_pool;
c372cdd1 737 iod->nr_allocations = 0;
a7a7cbe3
CK		 738 } else {
739 pool = dev->prp_page_pool;
c372cdd1 740 iod->nr_allocations = 1;
a7a7cbe3
CK		 741 }
742
743 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
744 if (!sg_list) {
c372cdd1 745 iod->nr_allocations = -1;
a7a7cbe3
CK		 746 return BLK_STS_RESOURCE;
747 }
748
749 nvme_pci_iod_list(req)[0] = sg_list;
750 iod->first_dma = sgl_dma;
751
752 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
753
754 do {
755 if (i == SGES_PER_PAGE) {
756 struct nvme_sgl_desc *old_sg_desc = sg_list;
757 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
758
759 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
760 if (!sg_list)
fa073216 761 goto free_sgls;
a7a7cbe3
CK		 762
763 i = 0;
c372cdd1 764 nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list;
a7a7cbe3
CK		 765 sg_list[i++] = *link;
766 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
767 }
768
769 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 770 sg = sg_next(sg);
b0f2853b 771 } while (--entries > 0);
a7a7cbe3 772
a7a7cbe3 773 return BLK_STS_OK;
fa073216
CH		 774free_sgls:
775 nvme_free_sgls(dev, req);
776 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 777}
778
dff824b2
CH		 779static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
780 struct request *req, struct nvme_rw_command *cmnd,
781 struct bio_vec *bv)
782{
783 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 784 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
785 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 786
787 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
788 if (dma_mapping_error(dev->dev, iod->first_dma))
789 return BLK_STS_RESOURCE;
790 iod->dma_len = bv->bv_len;
791
792 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
793 if (bv->bv_len > first_prp_len)
794 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 795 return BLK_STS_OK;
dff824b2
CH		 796}
797
29791057
CH		 798static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
799 struct request *req, struct nvme_rw_command *cmnd,
800 struct bio_vec *bv)
801{
802 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
803
804 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
805 if (dma_mapping_error(dev->dev, iod->first_dma))
806 return BLK_STS_RESOURCE;
807 iod->dma_len = bv->bv_len;
808
049bf372 809 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 810 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
811 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
812 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 813 return BLK_STS_OK;
29791057
CH		 814}
815
fc17b653 816static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 817 struct nvme_command *cmnd)
d29ec824 818{
f4800d6d 819 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 820 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 821 int rc;
d29ec824 822
dff824b2 823 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 824 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 825 struct bio_vec bv = req_bvec(req);
826
827 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 828 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 829 return nvme_setup_prp_simple(dev, req,
830 &cmnd->rw, &bv);
29791057 831
a53232cb 832 if (nvmeq->qid && sgl_threshold &&
253a0b76 833 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 834 return nvme_setup_sgl_simple(dev, req,
835 &cmnd->rw, &bv);
dff824b2
CH		 836 }
837 }
838
839 iod->dma_len = 0;
91fb2b60
LG		 840 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
841 if (!iod->sgt.sgl)
d43f1ccf 842 return BLK_STS_RESOURCE;
91fb2b60
LG		 843 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
844 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
845 if (!iod->sgt.orig_nents)
fa073216 846 goto out_free_sg;
d29ec824 847
91fb2b60
LG		 848 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
849 DMA_ATTR_NO_WARN);
850 if (rc) {
851 if (rc == -EREMOTEIO)
852 ret = BLK_STS_TARGET;
fa073216 853 goto out_free_sg;
91fb2b60 854 }
d29ec824 855
70479b71 856 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 857 if (iod->use_sgl)
91fb2b60 858 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 859 else
860 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 861 if (ret != BLK_STS_OK)
fa073216
CH		 862 goto out_unmap_sg;
863 return BLK_STS_OK;
864
865out_unmap_sg:
91fb2b60 866 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 867out_free_sg:
91fb2b60 868 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 869 return ret;
870}
3045c0d0 871
4aedb705
CH		 872static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
873 struct nvme_command *cmnd)
874{
875 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 876
4aedb705
CH		 877 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
878 rq_dma_dir(req), 0);
879 if (dma_mapping_error(dev->dev, iod->meta_dma))
880 return BLK_STS_IOERR;
881 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 882 return BLK_STS_OK;
00df5cb4
MW		 883}
884
62451a2b 885static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 886{
9b048119 887 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 888 blk_status_t ret;
e1e5e564 889
52da4f3f 890 iod->aborted = false;
c372cdd1 891 iod->nr_allocations = -1;
91fb2b60 892 iod->sgt.nents = 0;
9b048119 893
62451a2b 894 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 895 if (ret)
f4800d6d 896 return ret;
a4aea562 897
fc17b653 898 if (blk_rq_nr_phys_segments(req)) {
62451a2b 899 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 900 if (ret)
9b048119 901 goto out_free_cmd;
fc17b653 902 }
a4aea562 903
4aedb705 904 if (blk_integrity_rq(req)) {
62451a2b 905 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 906 if (ret)
907 goto out_unmap_data;
908 }
909
6887fc64 910 nvme_start_request(req);
fc17b653 911 return BLK_STS_OK;
4aedb705
CH		 912out_unmap_data:
913 nvme_unmap_data(dev, req);
f9d03f96
CH		 914out_free_cmd:
915 nvme_cleanup_cmd(req);
ba1ca37e 916 return ret;
b60503ba 917}
e1e5e564 918
62451a2b
JA		 919/*
920 * NOTE: ns is NULL when called on the admin queue.
921 */
922static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
923 const struct blk_mq_queue_data *bd)
924{
925 struct nvme_queue *nvmeq = hctx->driver_data;
926 struct nvme_dev *dev = nvmeq->dev;
927 struct request *req = bd->rq;
928 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
929 blk_status_t ret;
930
931 /*
932 * We should not need to do this, but we're still using this to
933 * ensure we can drain requests on a dying queue.
934 */
935 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
936 return BLK_STS_IOERR;
937
938 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
939 return nvme_fail_nonready_command(&dev->ctrl, req);
940
941 ret = nvme_prep_rq(dev, req);
942 if (unlikely(ret))
943 return ret;
944 spin_lock(&nvmeq->sq_lock);
945 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
946 nvme_write_sq_db(nvmeq, bd->last);
947 spin_unlock(&nvmeq->sq_lock);
948 return BLK_STS_OK;
949}
950
d62cbcf6
JA		 951static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
952{
953 spin_lock(&nvmeq->sq_lock);
954 while (!rq_list_empty(*rqlist)) {
955 struct request *req = rq_list_pop(rqlist);
956 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
957
958 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
959 }
960 nvme_write_sq_db(nvmeq, true);
961 spin_unlock(&nvmeq->sq_lock);
962}
963
964static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
965{
966 /*
967 * We should not need to do this, but we're still using this to
968 * ensure we can drain requests on a dying queue.
969 */
970 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
971 return false;
972 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
973 return false;
974
975 req->mq_hctx->tags->rqs[req->tag] = req;
976 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
977}
978
979static void nvme_queue_rqs(struct request **rqlist)
980{
6bfec799 981 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 982 struct request *requeue_list = NULL;
983
6bfec799 984 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 985 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
986
987 if (!nvme_prep_rq_batch(nvmeq, req)) {
988 /* detach 'req' and add to remainder list */
6bfec799
KB		 989 rq_list_move(rqlist, &requeue_list, req, prev);
990
991 req = prev;
992 if (!req)
993 continue;
d62cbcf6
JA		 994 }
995
6bfec799 996 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 997 /* detach rest of list, and submit */
6bfec799 998 req->rq_next = NULL;
d62cbcf6 999 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 1000 *rqlist = next;
1001 prev = NULL;
1002 } else
1003 prev = req;
1004 }
d62cbcf6
JA		 1005
1006 *rqlist = requeue_list;
1007}
1008
c234a653 1009static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 1010{
a53232cb
KB		 1011 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1012 struct nvme_dev *dev = nvmeq->dev;
1013
1014 if (blk_integrity_rq(req)) {
1015 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 1016
4aedb705
CH		 1017 dma_unmap_page(dev->dev, iod->meta_dma,
1018 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 1019 }
1020
b15c592d 1021 if (blk_rq_nr_phys_segments(req))
4aedb705 1022 nvme_unmap_data(dev, req);
c234a653
JA		 1023}
1024
1025static void nvme_pci_complete_rq(struct request *req)
1026{
1027 nvme_pci_unmap_rq(req);
77f02a7a 1028 nvme_complete_rq(req);
b60503ba
MW		 1029}
1030
c234a653
JA		 1031static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1032{
1033 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1034}
1035
d783e0bd 1036/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1037static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1038{
74943d45
KB		 1039 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1040
1041 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1042}
1043
eb281c82 1044static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1045{
eb281c82 1046 u16 head = nvmeq->cq_head;
adf68f21 1047
397c699f
KB		 1048 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1049 nvmeq->dbbuf_cq_ei))
1050 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1051}
aae239e1 1052
cfa27356
CH		 1053static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1054{
1055 if (!nvmeq->qid)
1056 return nvmeq->dev->admin_tagset.tags[0];
1057 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1058}
1059
c234a653
JA		 1060static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1061 struct io_comp_batch *iob, u16 idx)
83a12fb7 1062{
74943d45 1063 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1064 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1065 struct request *req;
adf68f21 1066
83a12fb7
SG		 1067 /*
1068 * AEN requests are special as they don't time out and can
1069 * survive any kind of queue freeze and often don't respond to
1070 * aborts. We don't even bother to allocate a struct request
1071 * for them but rather special case them here.
1072 */
62df8016 1073 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1074 nvme_complete_async_event(&nvmeq->dev->ctrl,
1075 cqe->status, &cqe->result);
a0fa9647 1076 return;
83a12fb7 1077 }
b60503ba 1078
e7006de6 1079 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1080 if (unlikely(!req)) {
1081 dev_warn(nvmeq->dev->ctrl.device,
1082 "invalid id %d completed on queue %d\n",
62df8016 1083 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1084 return;
1085 }
1086
604c01d5 1087 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1088 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1089 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1090 nvme_pci_complete_batch))
ff029451 1091 nvme_pci_complete_rq(req);
83a12fb7 1092}
b60503ba 1093
5cb525c8
JA		 1094static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1095{
a0aac973 1096 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1097
1098 if (tmp == nvmeq->q_depth) {
5cb525c8 1099 nvmeq->cq_head = 0;
e2a366a4 1100 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1101 } else {
1102 nvmeq->cq_head = tmp;
b60503ba 1103 }
a0fa9647
JA		 1104}
1105
c234a653
JA		 1106static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1107 struct io_comp_batch *iob)
a0fa9647 1108{
1052b8ac 1109 int found = 0;
b60503ba 1110
1052b8ac 1111 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1112 found++;
b69e2ef2
KB		 1113 /*
1114 * load-load control dependency between phase and the rest of
1115 * the cqe requires a full read memory barrier
1116 */
1117 dma_rmb();
c234a653 1118 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1119 nvme_update_cq_head(nvmeq);
920d13a8 1120 }
eb281c82 1121
324b494c 1122 if (found)
920d13a8 1123 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1124 return found;
b60503ba
MW		 1125}
1126
1127static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1128{
58ffacb5 1129 struct nvme_queue *nvmeq = data;
4f502245 1130 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1131
4f502245
JA		 1132 if (nvme_poll_cq(nvmeq, &iob)) {
1133 if (!rq_list_empty(iob.req_list))
1134 nvme_pci_complete_batch(&iob);
05fae499 1135 return IRQ_HANDLED;
4f502245 1136 }
05fae499 1137 return IRQ_NONE;
58ffacb5
MW		 1138}
1139
1140static irqreturn_t nvme_irq_check(int irq, void *data)
1141{
1142 struct nvme_queue *nvmeq = data;
4e523547 1143
750dde44 1144 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1145 return IRQ_WAKE_THREAD;
1146 return IRQ_NONE;
58ffacb5
MW		 1147}
1148
0b2a8a9f 1149/*
fa059b85 1150 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1151 * Can be called from any context.
1152 */
fa059b85 1153static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1154{
3a7afd8e 1155 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1156
fa059b85 1157 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1158
fa059b85 1159 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1160 nvme_poll_cq(nvmeq, NULL);
fa059b85 1161 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1162}
1163
5a72e899 1164static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1165{
1166 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1167 bool found;
1168
1169 if (!nvme_cqe_pending(nvmeq))
1170 return 0;
1171
3a7afd8e 1172 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1173 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1174 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1175
dabcefab
JA		 1176 return found;
1177}
1178
ad22c355 1179static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1180{
f866fc42 1181 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1182 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1183 struct nvme_command c = { };
b60503ba 1184
a4aea562 1185 c.common.opcode = nvme_admin_async_event;
ad22c355 1186 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1187
1188 spin_lock(&nvmeq->sq_lock);
1189 nvme_sq_copy_cmd(nvmeq, &c);
1190 nvme_write_sq_db(nvmeq, true);
1191 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1192}
1193
b60503ba 1194static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1195{
f66e2804 1196 struct nvme_command c = { };
b60503ba 1197
b60503ba
MW		 1198 c.delete_queue.opcode = opcode;
1199 c.delete_queue.qid = cpu_to_le16(id);
1200
1c63dc66 1201 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1202}
1203
b60503ba 1204static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1205 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1206{
f66e2804 1207 struct nvme_command c = { };
4b04cc6a
JA		 1208 int flags = NVME_QUEUE_PHYS_CONTIG;
1209
7c349dde 1210 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1211 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1212
d29ec824 1213 /*
16772ae6 1214 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1215 * is attached to the request.
1216 */
b60503ba
MW		 1217 c.create_cq.opcode = nvme_admin_create_cq;
1218 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1219 c.create_cq.cqid = cpu_to_le16(qid);
1220 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1221 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1222 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1223
1c63dc66 1224 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1225}
1226
1227static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1228 struct nvme_queue *nvmeq)
1229{
9abd68ef 1230 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1231 struct nvme_command c = { };
81c1cd98 1232 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1233
9abd68ef
JA		 1234 /*
1235 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1236 * set. Since URGENT priority is zeroes, it makes all queues
1237 * URGENT.
1238 */
1239 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1240 flags |= NVME_SQ_PRIO_MEDIUM;
1241
d29ec824 1242 /*
16772ae6 1243 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1244 * is attached to the request.
1245 */
b60503ba
MW		 1246 c.create_sq.opcode = nvme_admin_create_sq;
1247 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1248 c.create_sq.sqid = cpu_to_le16(qid);
1249 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1250 c.create_sq.sq_flags = cpu_to_le16(flags);
1251 c.create_sq.cqid = cpu_to_le16(qid);
1252
1c63dc66 1253 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1254}
1255
1256static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1257{
1258 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1259}
1260
1261static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1262{
1263 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1264}
1265
de671d61 1266static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1267{
a53232cb 1268 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1269
27fa9bc5
CH		 1270 dev_warn(nvmeq->dev->ctrl.device,
1271 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1272 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1273 blk_mq_free_request(req);
de671d61 1274 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1275}
1276
b2a0eb1a
KB		 1277static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1278{
b2a0eb1a
KB		 1279 /* If true, indicates loss of adapter communication, possibly by a
1280 * NVMe Subsystem reset.
1281 */
1282 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1283
ad70062c
JW		 1284 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1285 switch (dev->ctrl.state) {
1286 case NVME_CTRL_RESETTING:
ad6a0a52 1287 case NVME_CTRL_CONNECTING:
b2a0eb1a 1288 return false;
ad70062c
JW		 1289 default:
1290 break;
1291 }
b2a0eb1a
KB		 1292
1293 /* We shouldn't reset unless the controller is on fatal error state
1294 * _or_ if we lost the communication with it.
1295 */
1296 if (!(csts & NVME_CSTS_CFS) && !nssro)
1297 return false;
1298
b2a0eb1a
KB		 1299 return true;
1300}
1301
1302static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1303{
1304 /* Read a config register to help see what died. */
1305 u16 pci_status;
1306 int result;
1307
1308 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1309 &pci_status);
1310 if (result == PCIBIOS_SUCCESSFUL)
1311 dev_warn(dev->ctrl.device,
1312 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1313 csts, pci_status);
1314 else
1315 dev_warn(dev->ctrl.device,
1316 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1317 csts, result);
4641a8e6
KB		 1318
1319 if (csts != ~0)
1320 return;
1321
1322 dev_warn(dev->ctrl.device,
1323 "Does your device have a faulty power saving mode enabled?\n");
1324 dev_warn(dev->ctrl.device,
1325 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1326}
1327
9bdb4833 1328static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1329{
f4800d6d 1330 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1331 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1332 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1333 struct request *abort_req;
f66e2804 1334 struct nvme_command cmd = { };
b2a0eb1a
KB		 1335 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1336
651438bb
WX		 1337 /* If PCI error recovery process is happening, we cannot reset or
1338 * the recovery mechanism will surely fail.
1339 */
1340 mb();
1341 if (pci_channel_offline(to_pci_dev(dev->dev)))
1342 return BLK_EH_RESET_TIMER;
1343
b2a0eb1a
KB		 1344 /*
1345 * Reset immediately if the controller is failed
1346 */
1347 if (nvme_should_reset(dev, csts)) {
1348 nvme_warn_reset(dev, csts);
1349 nvme_dev_disable(dev, false);
d86c4d8e 1350 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1351 return BLK_EH_DONE;
b2a0eb1a 1352 }
c30341dc 1353
7776db1c
KB		 1354 /*
1355 * Did we miss an interrupt?
1356 */
fa059b85 1357 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1358 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1359 else
1360 nvme_poll_irqdisable(nvmeq);
1361
bf392a5d 1362 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1363 dev_warn(dev->ctrl.device,
1364 "I/O %d QID %d timeout, completion polled\n",
1365 req->tag, nvmeq->qid);
db8c48e4 1366 return BLK_EH_DONE;
7776db1c
KB		 1367 }
1368
31c7c7d2 1369 /*
fd634f41
CH		 1370 * Shutdown immediately if controller times out while starting. The
1371 * reset work will see the pci device disabled when it gets the forced
1372 * cancellation error. All outstanding requests are completed on
db8c48e4 1373 * shutdown, so we return BLK_EH_DONE.
fd634f41 1374 */
4244140d
KB		 1375 switch (dev->ctrl.state) {
1376 case NVME_CTRL_CONNECTING:
2036f726 1377 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1378 fallthrough;
2036f726 1379 case NVME_CTRL_DELETING:
b9cac43c 1380 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1381 "I/O %d QID %d timeout, disable controller\n",
1382 req->tag, nvmeq->qid);
27fa9bc5 1383 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1384 nvme_dev_disable(dev, true);
db8c48e4 1385 return BLK_EH_DONE;
39a9dd81
KB		 1386 case NVME_CTRL_RESETTING:
1387 return BLK_EH_RESET_TIMER;
4244140d
KB		 1388 default:
1389 break;
c30341dc
KB		 1390 }
1391
fd634f41 1392 /*
ee0d96d3
BW		 1393 * Shutdown the controller immediately and schedule a reset if the
1394 * command was already aborted once before and still hasn't been
1395 * returned to the driver, or if this is the admin queue.
31c7c7d2 1396 */
f4800d6d 1397 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1398 dev_warn(dev->ctrl.device,
e1569a16
KB		 1399 "I/O %d QID %d timeout, reset controller\n",
1400 req->tag, nvmeq->qid);
7ad92f65 1401 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1402 nvme_dev_disable(dev, false);
d86c4d8e 1403 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1404
db8c48e4 1405 return BLK_EH_DONE;
c30341dc 1406 }
c30341dc 1407
e7a2a87d 1408 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1409 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1410 return BLK_EH_RESET_TIMER;
6bf25d16 1411 }
52da4f3f 1412 iod->aborted = true;
a4aea562 1413
c30341dc 1414 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1415 cmd.abort.cid = nvme_cid(req);
c30341dc 1416 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1417
1b3c47c1 1418 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1419 "I/O %d (%s) QID %d timeout, aborting\n",
1420 req->tag,
1421 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1422 nvmeq->qid);
e7a2a87d 1423
e559398f
CH		 1424 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1425 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1426 if (IS_ERR(abort_req)) {
1427 atomic_inc(&dev->ctrl.abort_limit);
1428 return BLK_EH_RESET_TIMER;
1429 }
e559398f 1430 nvme_init_request(abort_req, &cmd);
e7a2a87d 1431
e2e53086 1432 abort_req->end_io = abort_endio;
e7a2a87d 1433 abort_req->end_io_data = NULL;
128126a7 1434 abort_req->rq_flags |= RQF_QUIET;
e2e53086 1435 blk_execute_rq_nowait(abort_req, false);
c30341dc 1436
31c7c7d2
CH		 1437 /*
1438 * The aborted req will be completed on receiving the abort req.
1439 * We enable the timer again. If hit twice, it'll cause a device reset,
1440 * as the device then is in a faulty state.
1441 */
1442 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1443}
1444
a4aea562
MB		 1445static void nvme_free_queue(struct nvme_queue *nvmeq)
1446{
8a1d09a6 1447 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1448 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1449 if (!nvmeq->sq_cmds)
1450 return;
0f238ff5 1451
63223078 1452 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1453 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1454 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1455 } else {
8a1d09a6 1456 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1457 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1458 }
9e866774
MW		 1459}
1460
a1a5ef99 1461static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1462{
1463 int i;
1464
d858e5f0 1465 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1466 dev->ctrl.queue_count--;
147b27e4 1467 nvme_free_queue(&dev->queues[i]);
121c7ad4 1468 }
22404274
KB		 1469}
1470
10981f23 1471static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
b60503ba 1472{
10981f23
CH		 1473 struct nvme_queue *nvmeq = &dev->queues[qid];
1474
4e224106 1475 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
10981f23 1476 return;
a09115b2 1477
4e224106 1478 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1479 mb();
a09115b2 1480
4e224106 1481 nvmeq->dev->online_queues--;
1c63dc66 1482 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
9f27bd70 1483 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
7c349dde 1484 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
10981f23 1485 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
4d115420 1486}
b60503ba 1487
8fae268b
KB		 1488static void nvme_suspend_io_queues(struct nvme_dev *dev)
1489{
1490 int i;
1491
1492 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
10981f23 1493 nvme_suspend_queue(dev, i);
8fae268b
KB		 1494}
1495
fa46c6fb
KB		 1496/*
1497 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1498 * that can check this device's completion queues have synced, except
1499 * nvme_poll(). This is the last chance for the driver to see a natural
1500 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1501 */
1502static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1503{
fa46c6fb
KB		 1504 int i;
1505
9210c075
DZ		 1506 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1507 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1508 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1509 spin_unlock(&dev->queues[i].cq_poll_lock);
1510 }
fa46c6fb
KB		 1511}
1512
8ffaadf7
JD		 1513static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1514 int entry_size)
1515{
1516 int q_depth = dev->q_depth;
5fd4ce1b 1517 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1518 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1519
1520 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1521 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1522
6c3c05b0 1523 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1524 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1525
1526 /*
1527 * Ensure the reduced q_depth is above some threshold where it
1528 * would be better to map queues in system memory with the
1529 * original depth
1530 */
1531 if (q_depth < 64)
1532 return -ENOMEM;
1533 }
1534
1535 return q_depth;
1536}
1537
1538static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1539 int qid)
8ffaadf7 1540{
0f238ff5
LG		 1541 struct pci_dev *pdev = to_pci_dev(dev->dev);
1542
1543 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1544 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1545 if (nvmeq->sq_cmds) {
1546 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1547 nvmeq->sq_cmds);
1548 if (nvmeq->sq_dma_addr) {
1549 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1550 return 0;
1551 }
1552
8a1d09a6 1553 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1554 }
0f238ff5 1555 }
8ffaadf7 1556
8a1d09a6 1557 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1558 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1559 if (!nvmeq->sq_cmds)
1560 return -ENOMEM;
8ffaadf7
JD		 1561 return 0;
1562}
1563
a6ff7262 1564static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1565{
147b27e4 1566 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1567
62314e40
KB		 1568 if (dev->ctrl.queue_count > qid)
1569 return 0;
b60503ba 1570
c1e0cc7e 1571 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1572 nvmeq->q_depth = depth;
1573 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1574 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1575 if (!nvmeq->cqes)
1576 goto free_nvmeq;
b60503ba 1577
8a1d09a6 1578 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1579 goto free_cqdma;
1580
091b6092 1581 nvmeq->dev = dev;
1ab0cd69 1582 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1583 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1584 nvmeq->cq_head = 0;
82123460 1585 nvmeq->cq_phase = 1;
b80d5ccc 1586 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1587 nvmeq->qid = qid;
d858e5f0 1588 dev->ctrl.queue_count++;
36a7e993 1589
147b27e4 1590 return 0;
b60503ba
MW		 1591
1592 free_cqdma:
8a1d09a6
BH		 1593 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1594 nvmeq->cq_dma_addr);
b60503ba 1595 free_nvmeq:
147b27e4 1596 return -ENOMEM;
b60503ba
MW		 1597}
1598
dca51e78 1599static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1600{
0ff199cb
CH		 1601 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1602 int nr = nvmeq->dev->ctrl.instance;
1603
1604 if (use_threaded_interrupts) {
1605 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1606 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1607 } else {
1608 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1609 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1610 }
3001082c
MW		 1611}
1612
22404274 1613static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1614{
22404274 1615 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1616
22404274 1617 nvmeq->sq_tail = 0;
38210800 1618 nvmeq->last_sq_tail = 0;
22404274
KB		 1619 nvmeq->cq_head = 0;
1620 nvmeq->cq_phase = 1;
b80d5ccc 1621 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1622 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1623 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1624 dev->online_queues++;
3a7afd8e 1625 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1626}
1627
e4b9852a
CC		 1628/*
1629 * Try getting shutdown_lock while setting up IO queues.
1630 */
1631static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1632{
1633 /*
1634 * Give up if the lock is being held by nvme_dev_disable.
1635 */
1636 if (!mutex_trylock(&dev->shutdown_lock))
1637 return -ENODEV;
1638
1639 /*
1640 * Controller is in wrong state, fail early.
1641 */
1642 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1643 mutex_unlock(&dev->shutdown_lock);
1644 return -ENODEV;
1645 }
1646
1647 return 0;
1648}
1649
4b04cc6a 1650static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1651{
1652 struct nvme_dev *dev = nvmeq->dev;
1653 int result;
7c349dde 1654 u16 vector = 0;
3f85d50b 1655
d1ed6aa1
CH		 1656 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1657
22b55601
KB		 1658 /*
1659 * A queue's vector matches the queue identifier unless the controller
1660 * has only one vector available.
1661 */
4b04cc6a
JA		 1662 if (!polled)
1663 vector = dev->num_vecs == 1 ? 0 : qid;
1664 else
7c349dde 1665 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1666
a8e3e0bb 1667 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1668 if (result)
1669 return result;
b60503ba
MW		 1670
1671 result = adapter_alloc_sq(dev, qid, nvmeq);
1672 if (result < 0)
ded45505 1673 return result;
c80b36cd 1674 if (result)
b60503ba
MW		 1675 goto release_cq;
1676
a8e3e0bb 1677 nvmeq->cq_vector = vector;
4b04cc6a 1678
e4b9852a
CC		 1679 result = nvme_setup_io_queues_trylock(dev);
1680 if (result)
1681 return result;
1682 nvme_init_queue(nvmeq, qid);
7c349dde 1683 if (!polled) {
4b04cc6a
JA		 1684 result = queue_request_irq(nvmeq);
1685 if (result < 0)
1686 goto release_sq;
1687 }
b60503ba 1688
4e224106 1689 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1690 mutex_unlock(&dev->shutdown_lock);
22404274 1691 return result;
b60503ba 1692
a8e3e0bb 1693release_sq:
f25a2dfc 1694 dev->online_queues--;
e4b9852a 1695 mutex_unlock(&dev->shutdown_lock);
b60503ba 1696 adapter_delete_sq(dev, qid);
a8e3e0bb 1697release_cq:
b60503ba 1698 adapter_delete_cq(dev, qid);
22404274 1699 return result;
b60503ba
MW		 1700}
1701
f363b089 1702static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1703 .queue_rq = nvme_queue_rq,
77f02a7a 1704 .complete = nvme_pci_complete_rq,
a4aea562 1705 .init_hctx = nvme_admin_init_hctx,
e559398f 1706 .init_request = nvme_pci_init_request,
a4aea562
MB		 1707 .timeout = nvme_timeout,
1708};
1709
f363b089 1710static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1711 .queue_rq = nvme_queue_rq,
d62cbcf6 1712 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1713 .complete = nvme_pci_complete_rq,
1714 .commit_rqs = nvme_commit_rqs,
1715 .init_hctx = nvme_init_hctx,
e559398f 1716 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1717 .map_queues = nvme_pci_map_queues,
1718 .timeout = nvme_timeout,
1719 .poll = nvme_poll,
dabcefab
JA		 1720};
1721
ea191d2f
KB		 1722static void nvme_dev_remove_admin(struct nvme_dev *dev)
1723{
1c63dc66 1724 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1725 /*
1726 * If the controller was reset during removal, it's possible
1727 * user requests may be waiting on a stopped queue. Start the
1728 * queue to flush these to completion.
1729 */
9f27bd70 1730 nvme_unquiesce_admin_queue(&dev->ctrl);
6f8191fd 1731 blk_mq_destroy_queue(dev->ctrl.admin_q);
96ef1be5 1732 blk_put_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1733 blk_mq_free_tag_set(&dev->admin_tagset);
1734 }
1735}
1736
f91b727c 1737static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev)
a4aea562 1738{
f91b727c 1739 struct blk_mq_tag_set *set = &dev->admin_tagset;
e3e9d50c 1740
f91b727c
CH		 1741 set->ops = &nvme_mq_admin_ops;
1742 set->nr_hw_queues = 1;
a4aea562 1743
f91b727c
CH		 1744 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1745 set->timeout = NVME_ADMIN_TIMEOUT;
1746 set->numa_node = dev->ctrl.numa_node;
1747 set->cmd_size = sizeof(struct nvme_iod);
1748 set->flags = BLK_MQ_F_NO_SCHED;
1749 set->driver_data = dev;
a4aea562 1750
f91b727c
CH		 1751 if (blk_mq_alloc_tag_set(set))
1752 return -ENOMEM;
1753 dev->ctrl.admin_tagset = set;
a4aea562 1754
f91b727c
CH		 1755 dev->ctrl.admin_q = blk_mq_init_queue(set);
1756 if (IS_ERR(dev->ctrl.admin_q)) {
1757 blk_mq_free_tag_set(set);
1758 dev->ctrl.admin_q = NULL;
1759 return -ENOMEM;
1760 }
a4aea562
MB		 1761 return 0;
1762}
1763
97f6ef64
XY		 1764static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1765{
1766 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1767}
1768
1769static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1770{
1771 struct pci_dev *pdev = to_pci_dev(dev->dev);
1772
1773 if (size <= dev->bar_mapped_size)
1774 return 0;
1775 if (size > pci_resource_len(pdev, 0))
1776 return -ENOMEM;
1777 if (dev->bar)
1778 iounmap(dev->bar);
1779 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1780 if (!dev->bar) {
1781 dev->bar_mapped_size = 0;
1782 return -ENOMEM;
1783 }
1784 dev->bar_mapped_size = size;
1785 dev->dbs = dev->bar + NVME_REG_DBS;
1786
1787 return 0;
1788}
1789
01ad0990 1790static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1791{
ba47e386 1792 int result;
b60503ba
MW		 1793 u32 aqa;
1794 struct nvme_queue *nvmeq;
1795
97f6ef64
XY		 1796 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1797 if (result < 0)
1798 return result;
1799
8ef2074d 1800 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1801 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1802
7a67cbea
CH		 1803 if (dev->subsystem &&
1804 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1805 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1806
285b6e9b
CH		 1807 /*
1808 * If the device has been passed off to us in an enabled state, just
1809 * clear the enabled bit. The spec says we should set the 'shutdown
1810 * notification bits', but doing so may cause the device to complete
1811 * commands to the admin queue ... and we don't know what memory that
1812 * might be pointing at!
1813 */
1814 result = nvme_disable_ctrl(&dev->ctrl, false);
ba47e386
MW		 1815 if (result < 0)
1816 return result;
b60503ba 1817
a6ff7262 1818 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1819 if (result)
1820 return result;
b60503ba 1821
635333e4
MG		 1822 dev->ctrl.numa_node = dev_to_node(dev->dev);
1823
147b27e4 1824 nvmeq = &dev->queues[0];
b60503ba
MW		 1825 aqa = nvmeq->q_depth - 1;
1826 aqa |= aqa << 16;
1827
7a67cbea
CH		 1828 writel(aqa, dev->bar + NVME_REG_AQA);
1829 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1830 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1831
c0f2f45b 1832 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1833 if (result)
d4875622 1834 return result;
a4aea562 1835
2b25d981 1836 nvmeq->cq_vector = 0;
161b8be2 1837 nvme_init_queue(nvmeq, 0);
dca51e78 1838 result = queue_request_irq(nvmeq);
758dd7fd 1839 if (result) {
7c349dde 1840 dev->online_queues--;
d4875622 1841 return result;
758dd7fd 1842 }
025c557a 1843
4e224106 1844 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1845 return result;
1846}
1847
749941f2 1848static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1849{
4b04cc6a 1850 unsigned i, max, rw_queues;
749941f2 1851 int ret = 0;
42f61420 1852
d858e5f0 1853 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1854 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1855 ret = -ENOMEM;
42f61420 1856 break;
749941f2
CH		 1857 }
1858 }
42f61420 1859
d858e5f0 1860 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1861 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1862 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1863 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1864 } else {
1865 rw_queues = max;
1866 }
1867
949928c1 1868 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1869 bool polled = i > rw_queues;
1870
1871 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1872 if (ret)
42f61420 1873 break;
27e8166c 1874 }
749941f2
CH		 1875
1876 /*
1877 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1878 * than the desired amount of queues, and even a controller without
1879 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1880 * be useful to upgrade a buggy firmware for example.
1881 */
1882 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1883}
1884
88de4598 1885static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1886{
88de4598
CH		 1887 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1888
1889 return 1ULL << (12 + 4 * szu);
1890}
1891
1892static u32 nvme_cmb_size(struct nvme_dev *dev)
1893{
1894 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1895}
1896
f65efd6d 1897static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1898{
88de4598 1899 u64 size, offset;
8ffaadf7
JD		 1900 resource_size_t bar_size;
1901 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1902 int bar;
8ffaadf7 1903
9fe5c59f
KB		 1904 if (dev->cmb_size)
1905 return;
1906
20d3bb92
KJ		 1907 if (NVME_CAP_CMBS(dev->ctrl.cap))
1908 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1909
7a67cbea 1910 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1911 if (!dev->cmbsz)
1912 return;
202021c1 1913 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1914
88de4598
CH		 1915 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1916 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1917 bar = NVME_CMB_BIR(dev->cmbloc);
1918 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1919
1920 if (offset > bar_size)
f65efd6d 1921 return;
8ffaadf7 1922
20d3bb92
KJ		 1923 /*
1924 * Tell the controller about the host side address mapping the CMB,
1925 * and enable CMB decoding for the NVMe 1.4+ scheme:
1926 */
1927 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1928 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1929 (pci_bus_address(pdev, bar) + offset),
1930 dev->bar + NVME_REG_CMBMSC);
1931 }
1932
8ffaadf7
JD		 1933 /*
1934 * Controllers may support a CMB size larger than their BAR,
1935 * for example, due to being behind a bridge. Reduce the CMB to
1936 * the reported size of the BAR
1937 */
1938 if (size > bar_size - offset)
1939 size = bar_size - offset;
1940
0f238ff5
LG		 1941 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1942 dev_warn(dev->ctrl.device,
1943 "failed to register the CMB\n");
f65efd6d 1944 return;
0f238ff5
LG		 1945 }
1946
8ffaadf7 1947 dev->cmb_size = size;
0f238ff5
LG		 1948 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1949
1950 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1951 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1952 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1953}
1954
87ad72a5
CH		 1955static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1956{
6c3c05b0 1957 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1958 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1959 struct nvme_command c = { };
87ad72a5
CH		 1960 int ret;
1961
87ad72a5
CH		 1962 c.features.opcode = nvme_admin_set_features;
1963 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1964 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1965 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1966 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1967 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1968 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1969
1970 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1971 if (ret) {
1972 dev_warn(dev->ctrl.device,
1973 "failed to set host mem (err %d, flags %#x).\n",
1974 ret, bits);
a5df5e79
KB		 1975 } else
1976 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1977
87ad72a5
CH		 1978 return ret;
1979}
1980
1981static void nvme_free_host_mem(struct nvme_dev *dev)
1982{
1983 int i;
1984
1985 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1986 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1987 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1988
cc667f6d
LD		 1989 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1990 le64_to_cpu(desc->addr),
1991 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1992 }
1993
1994 kfree(dev->host_mem_desc_bufs);
1995 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1996 dma_free_coherent(dev->dev,
1997 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1998 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1999 dev->host_mem_descs = NULL;
7e5dd57e 2000 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 2001}
2002
92dc6895
CH		 2003static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2004 u32 chunk_size)
9d713c2b 2005{
87ad72a5 2006 struct nvme_host_mem_buf_desc *descs;
92dc6895 2007 u32 max_entries, len;
4033f35d 2008 dma_addr_t descs_dma;
2ee0e4ed 2009 int i = 0;
87ad72a5 2010 void **bufs;
6fbcde66 2011 u64 size, tmp;
87ad72a5 2012
87ad72a5
CH		 2013 tmp = (preferred + chunk_size - 1);
2014 do_div(tmp, chunk_size);
2015 max_entries = tmp;
044a9df1
CH		 2016
2017 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2018 max_entries = dev->ctrl.hmmaxd;
2019
750afb08
LC		 2020 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2021 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 2022 if (!descs)
2023 goto out;
2024
2025 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2026 if (!bufs)
2027 goto out_free_descs;
2028
244a8fe4 2029 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 2030 dma_addr_t dma_addr;
2031
50cdb7c6 2032 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 2033 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2034 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2035 if (!bufs[i])
2036 break;
2037
2038 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 2039 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 2040 i++;
2041 }
2042
92dc6895 2043 if (!size)
87ad72a5 2044 goto out_free_bufs;
87ad72a5 2045
87ad72a5
CH		 2046 dev->nr_host_mem_descs = i;
2047 dev->host_mem_size = size;
2048 dev->host_mem_descs = descs;
4033f35d 2049 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 2050 dev->host_mem_desc_bufs = bufs;
2051 return 0;
2052
2053out_free_bufs:
2054 while (--i >= 0) {
6c3c05b0 2055 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 2056
cc667f6d
LD		 2057 dma_free_attrs(dev->dev, size, bufs[i],
2058 le64_to_cpu(descs[i].addr),
2059 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 2060 }
2061
2062 kfree(bufs);
2063out_free_descs:
4033f35d
CH		 2064 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2065 descs_dma);
87ad72a5 2066out:
87ad72a5
CH		 2067 dev->host_mem_descs = NULL;
2068 return -ENOMEM;
2069}
2070
92dc6895
CH		 2071static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2072{
9dc54a0d
CK		 2073 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2074 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2075 u64 chunk_size;
92dc6895
CH		 2076
2077 /* start big and work our way down */
9dc54a0d 2078 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2079 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2080 if (!min || dev->host_mem_size >= min)
2081 return 0;
2082 nvme_free_host_mem(dev);
2083 }
2084 }
2085
2086 return -ENOMEM;
2087}
2088
9620cfba 2089static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2090{
2091 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2092 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2093 u64 min = (u64)dev->ctrl.hmmin * 4096;
2094 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2095 int ret;
87ad72a5 2096
acb71e53
CH		 2097 if (!dev->ctrl.hmpre)
2098 return 0;
2099
87ad72a5
CH		 2100 preferred = min(preferred, max);
2101 if (min > max) {
2102 dev_warn(dev->ctrl.device,
2103 "min host memory (%lld MiB) above limit (%d MiB).\n",
2104 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2105 nvme_free_host_mem(dev);
9620cfba 2106 return 0;
87ad72a5
CH		 2107 }
2108
2109 /*
2110 * If we already have a buffer allocated check if we can reuse it.
2111 */
2112 if (dev->host_mem_descs) {
2113 if (dev->host_mem_size >= min)
2114 enable_bits |= NVME_HOST_MEM_RETURN;
2115 else
2116 nvme_free_host_mem(dev);
2117 }
2118
2119 if (!dev->host_mem_descs) {
92dc6895
CH		 2120 if (nvme_alloc_host_mem(dev, min, preferred)) {
2121 dev_warn(dev->ctrl.device,
2122 "failed to allocate host memory buffer.\n");
9620cfba 2123 return 0; /* controller must work without HMB */
92dc6895
CH		 2124 }
2125
2126 dev_info(dev->ctrl.device,
2127 "allocated %lld MiB host memory buffer.\n",
2128 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2129 }
2130
9620cfba
CH		 2131 ret = nvme_set_host_mem(dev, enable_bits);
2132 if (ret)
87ad72a5 2133 nvme_free_host_mem(dev);
9620cfba 2134 return ret;
9d713c2b
KB		 2135}
2136
0521905e
KB		 2137static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2138 char *buf)
2139{
2140 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2141
2142 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2143 ndev->cmbloc, ndev->cmbsz);
2144}
2145static DEVICE_ATTR_RO(cmb);
2146
1751e97a
KB		 2147static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2148 char *buf)
2149{
2150 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2151
2152 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2153}
2154static DEVICE_ATTR_RO(cmbloc);
2155
2156static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2157 char *buf)
2158{
2159 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2160
2161 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2162}
2163static DEVICE_ATTR_RO(cmbsz);
2164
a5df5e79
KB		 2165static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2166 char *buf)
2167{
2168 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2169
2170 return sysfs_emit(buf, "%d\n", ndev->hmb);
2171}
2172
2173static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2174 const char *buf, size_t count)
2175{
2176 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2177 bool new;
2178 int ret;
2179
99722c8a 2180 if (kstrtobool(buf, &new) < 0)
a5df5e79
KB		 2181 return -EINVAL;
2182
2183 if (new == ndev->hmb)
2184 return count;
2185
2186 if (new) {
2187 ret = nvme_setup_host_mem(ndev);
2188 } else {
2189 ret = nvme_set_host_mem(ndev, 0);
2190 if (!ret)
2191 nvme_free_host_mem(ndev);
2192 }
2193
2194 if (ret < 0)
2195 return ret;
2196
2197 return count;
2198}
2199static DEVICE_ATTR_RW(hmb);
2200
0521905e
KB		 2201static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2202 struct attribute *a, int n)
2203{
2204 struct nvme_ctrl *ctrl =
2205 dev_get_drvdata(container_of(kobj, struct device, kobj));
2206 struct nvme_dev *dev = to_nvme_dev(ctrl);
2207
1751e97a
KB		 2208 if (a == &dev_attr_cmb.attr ||
2209 a == &dev_attr_cmbloc.attr ||
2210 a == &dev_attr_cmbsz.attr) {
2211 if (!dev->cmbsz)
2212 return 0;
2213 }
a5df5e79
KB		 2214 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2215 return 0;
2216
0521905e
KB		 2217 return a->mode;
2218}
2219
2220static struct attribute *nvme_pci_attrs[] = {
2221 &dev_attr_cmb.attr,
1751e97a
KB		 2222 &dev_attr_cmbloc.attr,
2223 &dev_attr_cmbsz.attr,
a5df5e79 2224 &dev_attr_hmb.attr,
0521905e
KB		 2225 NULL,
2226};
2227
86adbf0c 2228static const struct attribute_group nvme_pci_dev_attrs_group = {
0521905e
KB		 2229 .attrs = nvme_pci_attrs,
2230 .is_visible = nvme_pci_attrs_are_visible,
2231};
2232
86adbf0c
CH		 2233static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2234 &nvme_dev_attrs_group,
2235 &nvme_pci_dev_attrs_group,
2236 NULL,
2237};
2238
612b7286
ML		 2239/*
2240 * nirqs is the number of interrupts available for write and read
2241 * queues. The core already reserved an interrupt for the admin queue.
2242 */
2243static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2244{
612b7286 2245 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2246 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2247
2248 /*
ee0d96d3 2249 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2250 * the default queue is set to 1. The affinity set size is
2251 * also set to one, but the irq core ignores it for this case.
2252 *
2253 * If only one interrupt is available or 'write_queue' == 0, combine
2254 * write and read queues.
2255 *
2256 * If 'write_queues' > 0, ensure it leaves room for at least one read
2257 * queue.
3b6592f7 2258 */
612b7286
ML		 2259 if (!nrirqs) {
2260 nrirqs = 1;
2261 nr_read_queues = 0;
2a5bcfdd 2262 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2263 nr_read_queues = 0;
2a5bcfdd 2264 } else if (nr_write_queues >= nrirqs) {
612b7286 2265 nr_read_queues = 1;
3b6592f7 2266 } else {
2a5bcfdd 2267 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2268 }
612b7286
ML		 2269
2270 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2271 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2272 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2273 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2274 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2275}
2276
6451fe73 2277static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2278{
2279 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2280 struct irq_affinity affd = {
9cfef55b 2281 .pre_vectors = 1,
612b7286
ML		 2282 .calc_sets = nvme_calc_irq_sets,
2283 .priv = dev,
3b6592f7 2284 };
21cc2f3f 2285 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2286
2287 /*
21cc2f3f
JX		 2288 * Poll queues don't need interrupts, but we need at least one I/O queue
2289 * left over for non-polled I/O.
6451fe73 2290 */
21cc2f3f
JX		 2291 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2292 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2293
21cc2f3f
JX		 2294 /*
2295 * Initialize for the single interrupt case, will be updated in
2296 * nvme_calc_irq_sets().
2297 */
612b7286
ML		 2298 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2299 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2300
66341331 2301 /*
21cc2f3f
JX		 2302 * We need interrupts for the admin queue and each non-polled I/O queue,
2303 * but some Apple controllers require all queues to use the first
2304 * vector.
66341331 2305 */
21cc2f3f
JX		 2306 irq_queues = 1;
2307 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2308 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2309 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2310 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2311}
2312
8fae268b
KB		 2313static void nvme_disable_io_queues(struct nvme_dev *dev)
2314{
2315 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2316 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2317}
2318
2a5bcfdd
WZ		 2319static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2320{
e3aef095
NS		 2321 /*
2322 * If tags are shared with admin queue (Apple bug), then
2323 * make sure we only use one IO queue.
2324 */
2325 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2326 return 1;
2a5bcfdd
WZ		 2327 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2328}
2329
8d85fce7 2330static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2331{
147b27e4 2332 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2333 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2334 unsigned int nr_io_queues;
97f6ef64 2335 unsigned long size;
2a5bcfdd 2336 int result;
b60503ba 2337
2a5bcfdd
WZ		 2338 /*
2339 * Sample the module parameters once at reset time so that we have
2340 * stable values to work with.
2341 */
2342 dev->nr_write_queues = write_queues;
2343 dev->nr_poll_queues = poll_queues;
d38e9f04 2344
e3aef095 2345 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2346 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2347 if (result < 0)
1b23484b 2348 return result;
9a0be7ab 2349
f5fa90dc 2350 if (nr_io_queues == 0)
a5229050 2351 return 0;
53dc180e 2352
e4b9852a
CC		 2353 /*
2354 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2355 * from set to unset. If there is a window to it is truely freed,
2356 * pci_free_irq_vectors() jumping into this window will crash.
2357 * And take lock to avoid racing with pci_free_irq_vectors() in
2358 * nvme_dev_disable() path.
2359 */
2360 result = nvme_setup_io_queues_trylock(dev);
2361 if (result)
2362 return result;
2363 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2364 pci_free_irq(pdev, 0, adminq);
b60503ba 2365
0f238ff5 2366 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2367 result = nvme_cmb_qdepth(dev, nr_io_queues,
2368 sizeof(struct nvme_command));
2369 if (result > 0)
2370 dev->q_depth = result;
2371 else
0f238ff5 2372 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2373 }
2374
97f6ef64
XY		 2375 do {
2376 size = db_bar_size(dev, nr_io_queues);
2377 result = nvme_remap_bar(dev, size);
2378 if (!result)
2379 break;
e4b9852a
CC		 2380 if (!--nr_io_queues) {
2381 result = -ENOMEM;
2382 goto out_unlock;
2383 }
97f6ef64
XY		 2384 } while (1);
2385 adminq->q_db = dev->dbs;
f1938f6e 2386
8fae268b 2387 retry:
9d713c2b 2388 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2389 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2390 pci_free_irq(pdev, 0, adminq);
9d713c2b 2391
e32efbfc
JA		 2392 /*
2393 * If we enable msix early due to not intx, disable it again before
2394 * setting up the full range we need.
2395 */
dca51e78 2396 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2397
2398 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2399 if (result <= 0) {
2400 result = -EIO;
2401 goto out_unlock;
2402 }
3b6592f7 2403
22b55601 2404 dev->num_vecs = result;
4b04cc6a 2405 result = max(result - 1, 1);
e20ba6e1 2406 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2407
063a8096
MW		 2408 /*
2409 * Should investigate if there's a performance win from allocating
2410 * more queues than interrupt vectors; it might allow the submission
2411 * path to scale better, even if the receive path is limited by the
2412 * number of interrupts.
2413 */
dca51e78 2414 result = queue_request_irq(adminq);
7c349dde 2415 if (result)
e4b9852a 2416 goto out_unlock;
4e224106 2417 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2418 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2419
2420 result = nvme_create_io_queues(dev);
2421 if (result || dev->online_queues < 2)
2422 return result;
2423
2424 if (dev->online_queues - 1 < dev->max_qid) {
2425 nr_io_queues = dev->online_queues - 1;
2426 nvme_disable_io_queues(dev);
e4b9852a
CC		 2427 result = nvme_setup_io_queues_trylock(dev);
2428 if (result)
2429 return result;
8fae268b
KB		 2430 nvme_suspend_io_queues(dev);
2431 goto retry;
2432 }
2433 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2434 dev->io_queues[HCTX_TYPE_DEFAULT],
2435 dev->io_queues[HCTX_TYPE_READ],
2436 dev->io_queues[HCTX_TYPE_POLL]);
2437 return 0;
e4b9852a
CC		 2438out_unlock:
2439 mutex_unlock(&dev->shutdown_lock);
2440 return result;
b60503ba
MW		 2441}
2442
de671d61
JA		 2443static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2444 blk_status_t error)
a5768aa8 2445{
db3cbfff 2446 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2447
db3cbfff 2448 blk_mq_free_request(req);
d1ed6aa1 2449 complete(&nvmeq->delete_done);
de671d61 2450 return RQ_END_IO_NONE;
a5768aa8
KB		 2451}
2452
de671d61
JA		 2453static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2454 blk_status_t error)
a5768aa8 2455{
db3cbfff 2456 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2457
d1ed6aa1
CH		 2458 if (error)
2459 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2460
de671d61 2461 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2462}
2463
db3cbfff 2464static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2465{
db3cbfff
KB		 2466 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2467 struct request *req;
f66e2804 2468 struct nvme_command cmd = { };
bda4e0fb 2469
db3cbfff
KB		 2470 cmd.delete_queue.opcode = opcode;
2471 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2472
e559398f 2473 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2474 if (IS_ERR(req))
2475 return PTR_ERR(req);
e559398f 2476 nvme_init_request(req, &cmd);
bda4e0fb 2477
e2e53086
CH		 2478 if (opcode == nvme_admin_delete_cq)
2479 req->end_io = nvme_del_cq_end;
2480 else
2481 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2482 req->end_io_data = nvmeq;
2483
d1ed6aa1 2484 init_completion(&nvmeq->delete_done);
128126a7 2485 req->rq_flags |= RQF_QUIET;
e2e53086 2486 blk_execute_rq_nowait(req, false);
db3cbfff 2487 return 0;
bda4e0fb
KB		 2488}
2489
8fae268b 2490static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2491{
5271edd4 2492 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2493 unsigned long timeout;
a5768aa8 2494
db3cbfff 2495 retry:
dc96f938 2496 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2497 while (nr_queues > 0) {
2498 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2499 break;
2500 nr_queues--;
2501 sent++;
db3cbfff 2502 }
d1ed6aa1
CH		 2503 while (sent) {
2504 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2505
2506 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2507 timeout);
2508 if (timeout == 0)
2509 return false;
d1ed6aa1 2510
d1ed6aa1 2511 sent--;
5271edd4
CH		 2512 if (nr_queues)
2513 goto retry;
2514 }
2515 return true;
a5768aa8
KB		 2516}
2517
2455a4b7 2518static void nvme_pci_alloc_tag_set(struct nvme_dev *dev)
b60503ba 2519{
2455a4b7 2520 struct blk_mq_tag_set * set = &dev->tagset;
2b1b7e78
JW		 2521 int ret;
2522
2455a4b7
CH		 2523 set->ops = &nvme_mq_ops;
2524 set->nr_hw_queues = dev->online_queues - 1;
6ee742fa
KB		 2525 set->nr_maps = 1;
2526 if (dev->io_queues[HCTX_TYPE_READ])
2527 set->nr_maps = 2;
2455a4b7 2528 if (dev->io_queues[HCTX_TYPE_POLL])
6ee742fa 2529 set->nr_maps = 3;
2455a4b7
CH		 2530 set->timeout = NVME_IO_TIMEOUT;
2531 set->numa_node = dev->ctrl.numa_node;
2532 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2533 set->cmd_size = sizeof(struct nvme_iod);
2534 set->flags = BLK_MQ_F_SHOULD_MERGE;
2535 set->driver_data = dev;
d38e9f04 2536
2455a4b7
CH		 2537 /*
2538 * Some Apple controllers requires tags to be unique
2539 * across admin and IO queue, so reserve the first 32
2540 * tags of the IO queue.
2541 */
2542 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2543 set->reserved_tags = NVME_AQ_DEPTH;
949928c1 2544
2455a4b7
CH		 2545 ret = blk_mq_alloc_tag_set(set);
2546 if (ret) {
2547 dev_warn(dev->ctrl.device,
2548 "IO queues tagset allocation failed %d\n", ret);
2549 return;
ffe7704d 2550 }
2455a4b7
CH		 2551 dev->ctrl.tagset = set;
2552}
949928c1 2553
2455a4b7
CH		 2554static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2555{
2556 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2557 /* free previously allocated queues that are no longer usable */
2558 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2559}
2560
b00a726a 2561static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2562{
b00a726a 2563 int result = -ENOMEM;
e75ec752 2564 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2565 int dma_address_bits = 64;
0877cb0d
KB		 2566
2567 if (pci_enable_device_mem(pdev))
2568 return result;
2569
0877cb0d 2570 pci_set_master(pdev);
0877cb0d 2571
4bdf2603
FS		 2572 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2573 dma_address_bits = 48;
2574 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2575 goto disable;
0877cb0d 2576
7a67cbea 2577 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2578 result = -ENODEV;
b00a726a 2579 goto disable;
0e53d180 2580 }
e32efbfc
JA		 2581
2582 /*
a5229050
KB		 2583 * Some devices and/or platforms don't advertise or work with INTx
2584 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2585 * adjust this later.
e32efbfc 2586 */
dca51e78
CH		 2587 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2588 if (result < 0)
2589 return result;
e32efbfc 2590
20d0dfe6 2591 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2592
7442ddce 2593 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2594 io_queue_depth);
aa22c8e6 2595 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2596 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2597 dev->dbs = dev->bar + 4096;
1f390c1f 2598
66341331
BH		 2599 /*
2600 * Some Apple controllers require a non-standard SQE size.
2601 * Interestingly they also seem to ignore the CC:IOSQES register
2602 * so we don't bother updating it here.
2603 */
2604 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2605 dev->io_sqes = 7;
2606 else
2607 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2608
2609 /*
2610 * Temporary fix for the Apple controller found in the MacBook8,1 and
2611 * some MacBook7,1 to avoid controller resets and data loss.
2612 */
2613 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2614 dev->q_depth = 2;
9bdcfb10
CH		 2615 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2616 "set queue depth=%u to work around controller resets\n",
1f390c1f 2617 dev->q_depth);
d554b5e1
MP		 2618 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2619 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2620 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2621 dev->q_depth = 64;
2622 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2623 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2624 }
2625
d38e9f04
BH		 2626 /*
2627 * Controllers with the shared tags quirk need the IO queue to be
2628 * big enough so that we get 32 tags for the admin queue
2629 */
2630 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2631 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2632 dev->q_depth = NVME_AQ_DEPTH + 2;
2633 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2634 dev->q_depth);
2635 }
2636
2637
f65efd6d 2638 nvme_map_cmb(dev);
202021c1 2639
a0a3408e
KB		 2640 pci_enable_pcie_error_reporting(pdev);
2641 pci_save_state(pdev);
a6ee7f19
CH		 2642
2643 return nvme_pci_configure_admin_queue(dev);
0877cb0d
KB		 2644
2645 disable:
0877cb0d
KB		 2646 pci_disable_device(pdev);
2647 return result;
2648}
2649
2650static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2651{
2652 if (dev->bar)
2653 iounmap(dev->bar);
a1f447b3 2654 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2655}
2656
a5cdb68c 2657static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2658{
e43269e6 2659 bool dead = true, freeze = false;
302ad8cc 2660 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2661
77bf25ea 2662 mutex_lock(&dev->shutdown_lock);
081f5e75
KB		 2663 if (pci_is_enabled(pdev)) {
2664 u32 csts;
2665
2666 if (pci_device_is_present(pdev))
2667 csts = readl(dev->bar + NVME_REG_CSTS);
2668 else
2669 csts = ~0;
302ad8cc 2670
ebef7368 2671 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2672 dev->ctrl.state == NVME_CTRL_RESETTING) {
2673 freeze = true;
302ad8cc 2674 nvme_start_freeze(&dev->ctrl);
e43269e6 2675 }
302ad8cc
KB		 2676 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2677 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2678 }
c21377f8 2679
302ad8cc
KB		 2680 /*
2681 * Give the controller a chance to complete all entered requests if
2682 * doing a safe shutdown.
2683 */
e43269e6
KB		 2684 if (!dead && shutdown && freeze)
2685 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b 2686
9f27bd70 2687 nvme_quiesce_io_queues(&dev->ctrl);
87ad72a5 2688
64ee0ac0 2689 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2690 nvme_disable_io_queues(dev);
47d42d22
CH		 2691 nvme_disable_ctrl(&dev->ctrl, shutdown);
2692 nvme_poll_irqdisable(&dev->queues[0]);
4d115420 2693 }
8fae268b 2694 nvme_suspend_io_queues(dev);
10981f23 2695 nvme_suspend_queue(dev, 0);
c80767f7
CH		 2696 pci_free_irq_vectors(pdev);
2697 if (pci_is_enabled(pdev)) {
2698 pci_disable_pcie_error_reporting(pdev);
2699 pci_disable_device(pdev);
2700 }
fa46c6fb 2701 nvme_reap_pending_cqes(dev);
07836e65 2702
1fcfca78
GL		 2703 nvme_cancel_tagset(&dev->ctrl);
2704 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2705
2706 /*
2707 * The driver will not be starting up queues again if shutting down so
2708 * must flush all entered requests to their failed completion to avoid
2709 * deadlocking blk-mq hot-cpu notifier.
2710 */
c8e9e9b7 2711 if (shutdown) {
9f27bd70 2712 nvme_unquiesce_io_queues(&dev->ctrl);
c8e9e9b7 2713 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
9f27bd70 2714 nvme_unquiesce_admin_queue(&dev->ctrl);
c8e9e9b7 2715 }
77bf25ea 2716 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2717}
2718
c1ac9a4b
KB		 2719static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2720{
2721 if (!nvme_wait_reset(&dev->ctrl))
2722 return -EBUSY;
2723 nvme_dev_disable(dev, shutdown);
2724 return 0;
2725}
2726
091b6092
MW		 2727static int nvme_setup_prp_pools(struct nvme_dev *dev)
2728{
e75ec752 2729 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2730 NVME_CTRL_PAGE_SIZE,
2731 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2732 if (!dev->prp_page_pool)
2733 return -ENOMEM;
2734
99802a7a 2735 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2736 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2737 256, 256, 0);
2738 if (!dev->prp_small_pool) {
2739 dma_pool_destroy(dev->prp_page_pool);
2740 return -ENOMEM;
2741 }
091b6092
MW		 2742 return 0;
2743}
2744
2745static void nvme_release_prp_pools(struct nvme_dev *dev)
2746{
2747 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2748 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2749}
2750
081a7d95
CH		 2751static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2752{
2753 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
2754 size_t alloc_size = sizeof(__le64 *) * npages +
2755 sizeof(struct scatterlist) * NVME_MAX_SEGS;
2756
2757 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2758 dev->iod_mempool = mempool_create_node(1,
2759 mempool_kmalloc, mempool_kfree,
2760 (void *)alloc_size, GFP_KERNEL,
2761 dev_to_node(dev->dev));
2762 if (!dev->iod_mempool)
2763 return -ENOMEM;
2764 return 0;
2765}
2766
770597ec
KB		 2767static void nvme_free_tagset(struct nvme_dev *dev)
2768{
2769 if (dev->tagset.tags)
2770 blk_mq_free_tag_set(&dev->tagset);
2771 dev->ctrl.tagset = NULL;
2772}
2773
2e87570b 2774/* pairs with nvme_pci_alloc_dev */
1673f1f0 2775static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2776{
1673f1f0 2777 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2778
770597ec 2779 nvme_free_tagset(dev);
253fd4ac
IR		 2780 put_device(dev->dev);
2781 kfree(dev->queues);
5e82e952
KB		 2782 kfree(dev);
2783}
2784
fd634f41 2785static void nvme_reset_work(struct work_struct *work)
5e82e952 2786{
d86c4d8e
CH		 2787 struct nvme_dev *dev =
2788 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2789 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2790 int result;
5e82e952 2791
7764656b
ZC		 2792 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2793 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2794 dev->ctrl.state);
e71afda4 2795 result = -ENODEV;
fd634f41 2796 goto out;
e71afda4 2797 }
5e82e952 2798
fd634f41
CH		 2799 /*
2800 * If we're called to reset a live controller first shut it down before
2801 * moving on.
2802 */
b00a726a 2803 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2804 nvme_dev_disable(dev, false);
d6135c3a 2805 nvme_sync_queues(&dev->ctrl);
5e82e952 2806
5c959d73 2807 mutex_lock(&dev->shutdown_lock);
b00a726a 2808 result = nvme_pci_enable(dev);
f0b50732 2809 if (result)
4726bcf3 2810 goto out_unlock;
9f27bd70 2811 nvme_unquiesce_admin_queue(&dev->ctrl);
5c959d73
KB		 2812 mutex_unlock(&dev->shutdown_lock);
2813
2814 /*
2815 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2816 * initializing procedure here.
2817 */
2818 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2819 dev_warn(dev->ctrl.device,
2820 "failed to mark controller CONNECTING\n");
cee6c269 2821 result = -EBUSY;
5c959d73
KB		 2822 goto out;
2823 }
943e942e 2824
94cc781f 2825 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
ce4541f4 2826 if (result)
f58944e2 2827 goto out;
ce4541f4 2828
65a54646 2829 nvme_dbbuf_dma_alloc(dev);
f9f38e33 2830
acb71e53
CH		 2831 result = nvme_setup_host_mem(dev);
2832 if (result < 0)
2833 goto out;
87ad72a5 2834
f0b50732 2835 result = nvme_setup_io_queues(dev);
badc34d4 2836 if (result)
f58944e2 2837 goto out;
f0b50732 2838
eac3ef26
CH		 2839 /*
2840 * Freeze and update the number of I/O queues as thos might have
2841 * changed. If there are no I/O queues left after this reset, keep the
2842 * controller around but remove all namespaces.
2843 */
2844 if (dev->online_queues > 1) {
9f27bd70 2845 nvme_unquiesce_io_queues(&dev->ctrl);
eac3ef26
CH		 2846 nvme_wait_freeze(&dev->ctrl);
2847 nvme_pci_update_nr_queues(dev);
2848 nvme_dbbuf_set(dev);
2849 nvme_unfreeze(&dev->ctrl);
3cf519b5 2850 } else {
eac3ef26
CH		 2851 dev_warn(dev->ctrl.device, "IO queues lost\n");
2852 nvme_mark_namespaces_dead(&dev->ctrl);
9f27bd70 2853 nvme_unquiesce_io_queues(&dev->ctrl);
eac3ef26
CH		 2854 nvme_remove_namespaces(&dev->ctrl);
2855 nvme_free_tagset(dev);
3cf519b5
CH		 2856 }
2857
2b1b7e78
JW		 2858 /*
2859 * If only admin queue live, keep it to do further investigation or
2860 * recovery.
2861 */
5d02a5c1 2862 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2863 dev_warn(dev->ctrl.device,
5d02a5c1 2864 "failed to mark controller live state\n");
e71afda4 2865 result = -ENODEV;
bb8d261e
CH		 2866 goto out;
2867 }
92911a55 2868
d09f2b45 2869 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2870 return;
f0b50732 2871
4726bcf3
KB		 2872 out_unlock:
2873 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2874 out:
c7c16c5b
CH		 2875 /*
2876 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2877 * may be holding this pci_dev's device lock.
2878 */
2879 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2880 result);
2881 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2882 nvme_dev_disable(dev, true);
2883 nvme_mark_namespaces_dead(&dev->ctrl);
2884 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
9a6b9458
KB		 2885}
2886
1c63dc66 2887static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2888{
1c63dc66 2889 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2890 return 0;
9ca97374
TH		 2891}
2892
5fd4ce1b 2893static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2894{
5fd4ce1b
CH		 2895 writel(val, to_nvme_dev(ctrl)->bar + off);
2896 return 0;
2897}
4cc06521 2898
7fd8930f
CH		 2899static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2900{
3a8ecc93 2901 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2902 return 0;
4cc06521
KB		 2903}
2904
97c12223
KB		 2905static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2906{
2907 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2908
2db24e4a 2909 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2910}
2911
2f0dad17
KB		 2912static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2913{
2914 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2915 struct nvme_subsystem *subsys = ctrl->subsys;
2916
2917 dev_err(ctrl->device,
2918 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2919 pdev->vendor, pdev->device,
2920 nvme_strlen(subsys->model, sizeof(subsys->model)),
2921 subsys->model, nvme_strlen(subsys->firmware_rev,
2922 sizeof(subsys->firmware_rev)),
2923 subsys->firmware_rev);
2924}
2925
2f859441
LG		 2926static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2927{
2928 struct nvme_dev *dev = to_nvme_dev(ctrl);
2929
2930 return dma_pci_p2pdma_supported(dev->dev);
2931}
2932
1c63dc66 2933static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2934 .name = "pcie",
e439bb12 2935 .module = THIS_MODULE,
2f859441 2936 .flags = NVME_F_METADATA_SUPPORTED,
86adbf0c 2937 .dev_attr_groups = nvme_pci_dev_attr_groups,
1c63dc66 2938 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2939 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2940 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2941 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2942 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2943 .get_address = nvme_pci_get_address,
2f0dad17 2944 .print_device_info = nvme_pci_print_device_info,
2f859441 2945 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 2946};
4cc06521 2947
b00a726a
KB		 2948static int nvme_dev_map(struct nvme_dev *dev)
2949{
b00a726a
KB		 2950 struct pci_dev *pdev = to_pci_dev(dev->dev);
2951
a1f447b3 2952 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2953 return -ENODEV;
2954
97f6ef64 2955 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2956 goto release;
2957
9fa196e7 2958 return 0;
b00a726a 2959 release:
9fa196e7
MG		 2960 pci_release_mem_regions(pdev);
2961 return -ENODEV;
b00a726a
KB		 2962}
2963
8427bbc2 2964static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2965{
2966 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2967 /*
2968 * Several Samsung devices seem to drop off the PCIe bus
2969 * randomly when APST is on and uses the deepest sleep state.
2970 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2971 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2972 * 950 PRO 256GB", but it seems to be restricted to two Dell
2973 * laptops.
2974 */
2975 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2976 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2977 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2978 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2979 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2980 /*
2981 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2982 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2983 * within few minutes after bootup on a Coffee Lake board -
2984 * ASUS PRIME Z370-A
8427bbc2
KHF		 2985 */
2986 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2987 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2988 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2989 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2990 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2991 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2992 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2993 /*
2994 * Forcing to use host managed nvme power settings for
2995 * lowest idle power with quick resume latency on
2996 * Samsung and Toshiba SSDs based on suspend behavior
2997 * on Coffee Lake board for LENOVO C640
2998 */
2999 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3000 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3001 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 3002 }
3003
3004 return 0;
3005}
3006
2e87570b
CH		 3007static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
3008 const struct pci_device_id *id)
b60503ba 3009{
ff5350a8 3010 unsigned long quirks = id->driver_data;
2e87570b
CH		 3011 int node = dev_to_node(&pdev->dev);
3012 struct nvme_dev *dev;
3013 int ret = -ENOMEM;
b60503ba 3014
a4aea562 3015 if (node == NUMA_NO_NODE)
2fa84351 3016 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 3017
3018 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba 3019 if (!dev)
2e87570b
CH		 3020 return NULL;
3021 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2e87570b 3022 mutex_init(&dev->shutdown_lock);
147b27e4 3023
2a5bcfdd
WZ		 3024 dev->nr_write_queues = write_queues;
3025 dev->nr_poll_queues = poll_queues;
3026 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3027 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3028 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba 3029 if (!dev->queues)
2e87570b 3030 goto out_free_dev;
b60503ba 3031
e75ec752 3032 dev->dev = get_device(&pdev->dev);
4cc06521 3033
8427bbc2 3034 quirks |= check_vendor_combination_bug(pdev);
2744d7a0 3035 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 3036 /*
3037 * Some systems use a bios work around to ask for D3 on
3038 * platforms that support kernel managed suspend.
3039 */
3040 dev_info(&pdev->dev,
3041 "platform quirk: setting simple suspend\n");
3042 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3043 }
2e87570b
CH		 3044 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3045 quirks);
3046 if (ret)
3047 goto out_put_device;
3f30a79c
CH		 3048
3049 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
3050 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
3051
3052 /*
3053 * Limit the max command size to prevent iod->sg allocations going
3054 * over a single page.
3055 */
3056 dev->ctrl.max_hw_sectors = min_t(u32,
3057 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9);
3058 dev->ctrl.max_segments = NVME_MAX_SEGS;
3059
3060 /*
3061 * There is no support for SGLs for metadata (yet), so we are limited to
3062 * a single integrity segment for the separate metadata pointer.
3063 */
3064 dev->ctrl.max_integrity_segments = 1;
2e87570b 3065 return dev;
df4f9bc4 3066
2e87570b
CH		 3067out_put_device:
3068 put_device(dev->dev);
3069 kfree(dev->queues);
3070out_free_dev:
3071 kfree(dev);
3072 return ERR_PTR(ret);
3073}
3074
3075static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3076{
3077 struct nvme_dev *dev;
3078 int result = -ENOMEM;
3079
3080 dev = nvme_pci_alloc_dev(pdev, id);
3081 if (!dev)
3082 return -ENOMEM;
3083
3084 result = nvme_dev_map(dev);
3085 if (result)
3086 goto out_uninit_ctrl;
3087
3088 result = nvme_setup_prp_pools(dev);
081a7d95 3089 if (result)
2e87570b 3090 goto out_dev_unmap;
943e942e 3091
2e87570b 3092 result = nvme_pci_alloc_iod_mempool(dev);
b6e44b4c 3093 if (result)
2e87570b 3094 goto out_release_prp_pools;
b6e44b4c 3095
1b3c47c1 3096 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
eac3ef26
CH		 3097
3098 result = nvme_pci_enable(dev);
3099 if (result)
3100 goto out_release_iod_mempool;
3101
3102 result = nvme_pci_alloc_admin_tag_set(dev);
3103 if (result)
3104 goto out_disable;
3105
3106 /*
3107 * Mark the controller as connecting before sending admin commands to
3108 * allow the timeout handler to do the right thing.
3109 */
3110 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3111 dev_warn(dev->ctrl.device,
3112 "failed to mark controller CONNECTING\n");
3113 result = -EBUSY;
3114 goto out_disable;
3115 }
3116
3117 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3118 if (result)
3119 goto out_disable;
3120
3121 nvme_dbbuf_dma_alloc(dev);
3122
3123 result = nvme_setup_host_mem(dev);
3124 if (result < 0)
3125 goto out_disable;
3126
3127 result = nvme_setup_io_queues(dev);
3128 if (result)
3129 goto out_disable;
3130
3131 if (dev->online_queues > 1) {
3132 nvme_pci_alloc_tag_set(dev);
3133 nvme_dbbuf_set(dev);
3134 } else {
3135 dev_warn(dev->ctrl.device, "IO queues not created\n");
3136 }
3137
3138 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3139 dev_warn(dev->ctrl.device,
3140 "failed to mark controller live state\n");
3141 result = -ENODEV;
3142 goto out_disable;
3143 }
3144
2e87570b 3145 pci_set_drvdata(pdev, dev);
1b3c47c1 3146
eac3ef26
CH		 3147 nvme_start_ctrl(&dev->ctrl);
3148 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 3149 return 0;
3150
eac3ef26
CH		 3151out_disable:
3152 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3153 nvme_dev_disable(dev, true);
3154 nvme_free_host_mem(dev);
3155 nvme_dev_remove_admin(dev);
3156 nvme_dbbuf_dma_free(dev);
3157 nvme_free_queues(dev, 0);
3158out_release_iod_mempool:
3159 mempool_destroy(dev->iod_mempool);
2e87570b 3160out_release_prp_pools:
091b6092 3161 nvme_release_prp_pools(dev);
2e87570b 3162out_dev_unmap:
b00c9b7a 3163 nvme_dev_unmap(dev);
2e87570b
CH		 3164out_uninit_ctrl:
3165 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3166 return result;
3167}
3168
775755ed 3169static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3170{
a6739479 3171 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3172
3173 /*
3174 * We don't need to check the return value from waiting for the reset
3175 * state as pci_dev device lock is held, making it impossible to race
3176 * with ->remove().
3177 */
3178 nvme_disable_prepare_reset(dev, false);
3179 nvme_sync_queues(&dev->ctrl);
775755ed 3180}
f0d54a54 3181
775755ed
CH		 3182static void nvme_reset_done(struct pci_dev *pdev)
3183{
f263fbb8 3184 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3185
3186 if (!nvme_try_sched_reset(&dev->ctrl))
3187 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3188}
3189
09ece142
KB		 3190static void nvme_shutdown(struct pci_dev *pdev)
3191{
3192 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3193
c1ac9a4b 3194 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3195}
3196
f58944e2
KB		 3197/*
3198 * The driver's remove may be called on a device in a partially initialized
3199 * state. This function must not have any dependencies on the device state in
3200 * order to proceed.
3201 */
8d85fce7 3202static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3203{
3204 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3205
bb8d261e 3206 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3207 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3208
6db28eda 3209 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3210 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3211 nvme_dev_disable(dev, true);
6db28eda 3212 }
0ff9d4e1 3213
d86c4d8e 3214 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3215 nvme_stop_ctrl(&dev->ctrl);
3216 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3217 nvme_dev_disable(dev, true);
87ad72a5 3218 nvme_free_host_mem(dev);
a4aea562 3219 nvme_dev_remove_admin(dev);
c11b7716 3220 nvme_dbbuf_dma_free(dev);
a1a5ef99 3221 nvme_free_queues(dev, 0);
c11b7716 3222 mempool_destroy(dev->iod_mempool);
9a6b9458 3223 nvme_release_prp_pools(dev);
b00a726a 3224 nvme_dev_unmap(dev);
726612b6 3225 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3226}
3227
671a6018 3228#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3229static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3230{
3231 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3232}
3233
3234static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3235{
3236 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3237}
3238
3239static int nvme_resume(struct device *dev)
3240{
3241 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3242 struct nvme_ctrl *ctrl = &ndev->ctrl;
3243
4eaefe8c 3244 if (ndev->last_ps == U32_MAX ||
d916b1be 3245 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3246 goto reset;
3247 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3248 goto reset;
3249
d916b1be 3250 return 0;
e5ad96f3
KB		 3251reset:
3252 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3253}
3254
cd638946
KB		 3255static int nvme_suspend(struct device *dev)
3256{
3257 struct pci_dev *pdev = to_pci_dev(dev);
3258 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3259 struct nvme_ctrl *ctrl = &ndev->ctrl;
3260 int ret = -EBUSY;
3261
4eaefe8c
RW		 3262 ndev->last_ps = U32_MAX;
3263
d916b1be
KB		 3264 /*
3265 * The platform does not remove power for a kernel managed suspend so
3266 * use host managed nvme power settings for lowest idle power if
3267 * possible. This should have quicker resume latency than a full device
3268 * shutdown. But if the firmware is involved after the suspend or the
3269 * device does not support any non-default power states, shut down the
3270 * device fully.
4eaefe8c
RW		 3271 *
3272 * If ASPM is not enabled for the device, shut down the device and allow
3273 * the PCI bus layer to put it into D3 in order to take the PCIe link
3274 * down, so as to allow the platform to achieve its minimum low-power
3275 * state (which may not be possible if the link is up).
d916b1be 3276 */
4eaefe8c 3277 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3278 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3279 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3280 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3281
3282 nvme_start_freeze(ctrl);
3283 nvme_wait_freeze(ctrl);
3284 nvme_sync_queues(ctrl);
3285
5d02a5c1 3286 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3287 goto unfreeze;
3288
e5ad96f3
KB		 3289 /*
3290 * Host memory access may not be successful in a system suspend state,
3291 * but the specification allows the controller to access memory in a
3292 * non-operational power state.
3293 */
3294 if (ndev->hmb) {
3295 ret = nvme_set_host_mem(ndev, 0);
3296 if (ret < 0)
3297 goto unfreeze;
3298 }
3299
d916b1be
KB		 3300 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3301 if (ret < 0)
3302 goto unfreeze;
3303
7cbb5c6f
ML		 3304 /*
3305 * A saved state prevents pci pm from generically controlling the
3306 * device's power. If we're using protocol specific settings, we don't
3307 * want pci interfering.
3308 */
3309 pci_save_state(pdev);
3310
d916b1be
KB		 3311 ret = nvme_set_power_state(ctrl, ctrl->npss);
3312 if (ret < 0)
3313 goto unfreeze;
3314
3315 if (ret) {
7cbb5c6f
ML		 3316 /* discard the saved state */
3317 pci_load_saved_state(pdev, NULL);
3318
d916b1be
KB		 3319 /*
3320 * Clearing npss forces a controller reset on resume. The
05d3046f 3321 * correct value will be rediscovered then.
d916b1be 3322 */
c1ac9a4b 3323 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3324 ctrl->npss = 0;
d916b1be 3325 }
d916b1be
KB		 3326unfreeze:
3327 nvme_unfreeze(ctrl);
3328 return ret;
3329}
3330
3331static int nvme_simple_suspend(struct device *dev)
3332{
3333 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3334
c1ac9a4b 3335 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3336}
3337
d916b1be 3338static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3339{
3340 struct pci_dev *pdev = to_pci_dev(dev);
3341 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3342
c1ac9a4b 3343 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3344}
3345
21774222 3346static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3347 .suspend = nvme_suspend,
3348 .resume = nvme_resume,
3349 .freeze = nvme_simple_suspend,
3350 .thaw = nvme_simple_resume,
3351 .poweroff = nvme_simple_suspend,
3352 .restore = nvme_simple_resume,
3353};
3354#endif /* CONFIG_PM_SLEEP */
b60503ba 3355
a0a3408e
KB		 3356static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3357 pci_channel_state_t state)
3358{
3359 struct nvme_dev *dev = pci_get_drvdata(pdev);
3360
3361 /*
3362 * A frozen channel requires a reset. When detected, this method will
3363 * shutdown the controller to quiesce. The controller will be restarted
3364 * after the slot reset through driver's slot_reset callback.
3365 */
a0a3408e
KB		 3366 switch (state) {
3367 case pci_channel_io_normal:
3368 return PCI_ERS_RESULT_CAN_RECOVER;
3369 case pci_channel_io_frozen:
d011fb31
KB		 3370 dev_warn(dev->ctrl.device,
3371 "frozen state error detected, reset controller\n");
a5cdb68c 3372 nvme_dev_disable(dev, false);
a0a3408e
KB		 3373 return PCI_ERS_RESULT_NEED_RESET;
3374 case pci_channel_io_perm_failure:
d011fb31
KB		 3375 dev_warn(dev->ctrl.device,
3376 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3377 return PCI_ERS_RESULT_DISCONNECT;
3378 }
3379 return PCI_ERS_RESULT_NEED_RESET;
3380}
3381
3382static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3383{
3384 struct nvme_dev *dev = pci_get_drvdata(pdev);
3385
1b3c47c1 3386 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3387 pci_restore_state(pdev);
d86c4d8e 3388 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3389 return PCI_ERS_RESULT_RECOVERED;
3390}
3391
3392static void nvme_error_resume(struct pci_dev *pdev)
3393{
72cd4cc2
KB		 3394 struct nvme_dev *dev = pci_get_drvdata(pdev);
3395
3396 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3397}
3398
1d352035 3399static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3400 .error_detected = nvme_error_detected,
b60503ba
MW		 3401 .slot_reset = nvme_slot_reset,
3402 .resume = nvme_error_resume,
775755ed
CH		 3403 .reset_prepare = nvme_reset_prepare,
3404 .reset_done = nvme_reset_done,
b60503ba
MW		 3405};
3406
6eb0d698 3407static const struct pci_device_id nvme_id_table[] = {
972b13e2 3408 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3409 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3410 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3411 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3412 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3413 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3414 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3415 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3416 NVME_QUIRK_DEALLOCATE_ZEROES |
3417 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3418 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3419 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3420 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3421 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3422 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3423 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3424 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3425 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3426 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3427 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3428 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3429 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3430 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3431 NVME_QUIRK_BOGUS_NID, },
3432 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3433 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3434 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3435 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3436 NVME_QUIRK_BOGUS_NID, },
0302ae60 3437 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3438 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3439 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3440 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3441 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3442 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3443 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3444 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3445 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3446 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3447 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3448 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3449 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3450 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3451 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3452 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3453 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3454 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3455 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3456 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3457 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3458 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3459 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3460 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3461 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3462 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3463 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3464 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3465 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3466 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3467 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3468 NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3469 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3470 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3471 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3472 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3473 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
5611ec2b
KHF		 3474 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3475 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3476 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3477 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3478 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3479 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3480 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3481 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3482 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3483 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3484 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3485 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3486 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3487 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3488 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3489 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3490 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3491 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3492 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3493 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
ac9b57d4
XL		 3494 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3495 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3496 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3497 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3498 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3499 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3500 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3501 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3502 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3503 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
70ce3455
CH		 3504 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3505 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3506 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3507 .driver_data = NVME_QUIRK_BOGUS_NID, },
3508 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3509 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3510 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3511 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3512 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3513 .driver_data = NVME_QUIRK_BOGUS_NID, },
d5d3c100
XR		 3514 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3515 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
6b961bce
NW		 3516 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3517 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3518 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3519 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3520 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3521 .driver_data = NVME_QUIRK_BOGUS_NID, },
80b26240
A		 3522 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3523 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3524 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3525 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3526 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3527 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3528 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3529 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3530 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3531 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3532 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3533 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3534 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3535 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3536 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3537 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3538 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3539 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3540 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3541 NVME_QUIRK_128_BYTES_SQES |
a2941f6a
KB		 3542 NVME_QUIRK_SHARED_TAGS |
3543 NVME_QUIRK_SKIP_CID_GEN },
0b85f59d 3544 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3545 { 0, }
3546};
3547MODULE_DEVICE_TABLE(pci, nvme_id_table);
3548
3549static struct pci_driver nvme_driver = {
3550 .name = "nvme",
3551 .id_table = nvme_id_table,
3552 .probe = nvme_probe,
8d85fce7 3553 .remove = nvme_remove,
09ece142 3554 .shutdown = nvme_shutdown,
cd638946 3555 .driver = {
eac3ef26
CH		 3556 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3557#ifdef CONFIG_PM_SLEEP
3558 .pm = &nvme_dev_pm_ops,
d916b1be 3559#endif
eac3ef26 3560 },
74d986ab 3561 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3562 .err_handler = &nvme_err_handler,
3563};
3564
3565static int __init nvme_init(void)
3566{
81101540
CH		 3567 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3568 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3569 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3570 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
c372cdd1
KB		 3571 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3572 S8_MAX);
17c33167 3573
9a6327d2 3574 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3575}
3576
3577static void __exit nvme_exit(void)
3578{
3579 pci_unregister_driver(&nvme_driver);
03e0f3a6 3580 flush_workqueue(nvme_wq);
b60503ba
MW		 3581}
3582
3583MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3584MODULE_LICENSE("GPL");
c78b4713 3585MODULE_VERSION("1.0");
b60503ba
MW		 3586module_init(nvme_init);
3587module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)