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nvme: centralize setting the timeout in nvme_alloc_request
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 26#include <linux/sed-opal.h>
0f238ff5 27#include <linux/pci-p2pdma.h>
797a796a 28
604c01d5 29#include "trace.h"
f11bb3e2
CH		 30#include "nvme.h"
31
c1e0cc7e 32#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 33#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 34
a7a7cbe3 35#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 36
943e942e
JA		 37/*
38 * These can be higher, but we need to ensure that any command doesn't
39 * require an sg allocation that needs more than a page of data.
40 */
41#define NVME_MAX_KB_SZ 4096
42#define NVME_MAX_SEGS 127
43
58ffacb5
MW		 44static int use_threaded_interrupts;
45module_param(use_threaded_interrupts, int, 0);
46
8ffaadf7 47static bool use_cmb_sqes = true;
69f4eb9f 48module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 49MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
50
87ad72a5
CH		 51static unsigned int max_host_mem_size_mb = 128;
52module_param(max_host_mem_size_mb, uint, 0444);
53MODULE_PARM_DESC(max_host_mem_size_mb,
54 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 55
a7a7cbe3
CK		 56static unsigned int sgl_threshold = SZ_32K;
57module_param(sgl_threshold, uint, 0644);
58MODULE_PARM_DESC(sgl_threshold,
59 "Use SGLs when average request segment size is larger or equal to "
60 "this size. Use 0 to disable SGLs.");
61
b27c1e68 62static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
63static const struct kernel_param_ops io_queue_depth_ops = {
64 .set = io_queue_depth_set,
61f3b896 65 .get = param_get_uint,
b27c1e68 66};
67
61f3b896 68static unsigned int io_queue_depth = 1024;
b27c1e68 69module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
70MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
71
9c9e76d5
WZ		 72static int io_queue_count_set(const char *val, const struct kernel_param *kp)
73{
74 unsigned int n;
75 int ret;
76
77 ret = kstrtouint(val, 10, &n);
78 if (ret != 0 || n > num_possible_cpus())
79 return -EINVAL;
80 return param_set_uint(val, kp);
81}
82
83static const struct kernel_param_ops io_queue_count_ops = {
84 .set = io_queue_count_set,
85 .get = param_get_uint,
86};
87
3f68baf7 88static unsigned int write_queues;
9c9e76d5 89module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 90MODULE_PARM_DESC(write_queues,
91 "Number of queues to use for writes. If not set, reads and writes "
92 "will share a queue set.");
93
3f68baf7 94static unsigned int poll_queues;
9c9e76d5 95module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 96MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
97
df4f9bc4
DB		 98static bool noacpi;
99module_param(noacpi, bool, 0444);
100MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
101
1c63dc66
CH		 102struct nvme_dev;
103struct nvme_queue;
b3fffdef 104
a5cdb68c 105static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 106static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 107
1c63dc66
CH		 108/*
109 * Represents an NVM Express device. Each nvme_dev is a PCI function.
110 */
111struct nvme_dev {
147b27e4 112 struct nvme_queue *queues;
1c63dc66
CH		 113 struct blk_mq_tag_set tagset;
114 struct blk_mq_tag_set admin_tagset;
115 u32 __iomem *dbs;
116 struct device *dev;
117 struct dma_pool *prp_page_pool;
118 struct dma_pool *prp_small_pool;
1c63dc66
CH		 119 unsigned online_queues;
120 unsigned max_qid;
e20ba6e1 121 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 122 unsigned int num_vecs;
7442ddce 123 u32 q_depth;
c1e0cc7e 124 int io_sqes;
1c63dc66 125 u32 db_stride;
1c63dc66 126 void __iomem *bar;
97f6ef64 127 unsigned long bar_mapped_size;
5c8809e6 128 struct work_struct remove_work;
77bf25ea 129 struct mutex shutdown_lock;
1c63dc66 130 bool subsystem;
1c63dc66 131 u64 cmb_size;
0f238ff5 132 bool cmb_use_sqes;
1c63dc66 133 u32 cmbsz;
202021c1 134 u32 cmbloc;
1c63dc66 135 struct nvme_ctrl ctrl;
d916b1be 136 u32 last_ps;
87ad72a5 137
943e942e
JA		 138 mempool_t *iod_mempool;
139
87ad72a5 140 /* shadow doorbell buffer support: */
f9f38e33
HK		 141 u32 *dbbuf_dbs;
142 dma_addr_t dbbuf_dbs_dma_addr;
143 u32 *dbbuf_eis;
144 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 145
146 /* host memory buffer support: */
147 u64 host_mem_size;
148 u32 nr_host_mem_descs;
4033f35d 149 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 150 struct nvme_host_mem_buf_desc *host_mem_descs;
151 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 152 unsigned int nr_allocated_queues;
153 unsigned int nr_write_queues;
154 unsigned int nr_poll_queues;
4d115420 155};
1fa6aead 156
b27c1e68 157static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
158{
61f3b896 159 int ret;
7442ddce 160 u32 n;
b27c1e68 161
7442ddce 162 ret = kstrtou32(val, 10, &n);
b27c1e68 163 if (ret != 0 || n < 2)
164 return -EINVAL;
165
7442ddce 166 return param_set_uint(val, kp);
b27c1e68 167}
168
f9f38e33
HK		 169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
1c63dc66
CH		 179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
b60503ba
MW		 184/*
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
187 */
188struct nvme_queue {
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
c1e0cc7e 191 void *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 194 struct nvme_completion *cqes;
b60503ba
MW		 195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
b60503ba 197 u32 __iomem *q_db;
7442ddce 198 u32 q_depth;
7c349dde 199 u16 cq_vector;
b60503ba 200 u16 sq_tail;
38210800 201 u16 last_sq_tail;
b60503ba 202 u16 cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
c1e0cc7e 205 u8 sqes;
4e224106
CH		 206 unsigned long flags;
207#define NVMEQ_ENABLED 0
63223078 208#define NVMEQ_SQ_CMB 1
d1ed6aa1 209#define NVMEQ_DELETE_ERROR 2
7c349dde 210#define NVMEQ_POLLED 3
f9f38e33
HK		 211 u32 *dbbuf_sq_db;
212 u32 *dbbuf_cq_db;
213 u32 *dbbuf_sq_ei;
214 u32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c 218/*
9b048119
CH		 219 * The nvme_iod describes the data in an I/O.
220 *
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
71bd150c
CH		 223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
f4800d6d 226 struct nvme_queue *nvmeq;
a7a7cbe3 227 bool use_sgl;
f4800d6d 228 int aborted;
71bd150c 229 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 230 int nents; /* Used in scatterlist */
71bd150c 231 dma_addr_t first_dma;
dff824b2 232 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 233 dma_addr_t meta_dma;
f4800d6d 234 struct scatterlist *sg;
b60503ba
MW		 235};
236
2a5bcfdd 237static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 238{
2a5bcfdd 239 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 240}
241
242static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
243{
2a5bcfdd 244 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 245
246 if (dev->dbbuf_dbs)
247 return 0;
248
249 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
250 &dev->dbbuf_dbs_dma_addr,
251 GFP_KERNEL);
252 if (!dev->dbbuf_dbs)
253 return -ENOMEM;
254 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
255 &dev->dbbuf_eis_dma_addr,
256 GFP_KERNEL);
257 if (!dev->dbbuf_eis) {
258 dma_free_coherent(dev->dev, mem_size,
259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
260 dev->dbbuf_dbs = NULL;
261 return -ENOMEM;
262 }
263
264 return 0;
265}
266
267static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
268{
2a5bcfdd 269 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 270
271 if (dev->dbbuf_dbs) {
272 dma_free_coherent(dev->dev, mem_size,
273 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
274 dev->dbbuf_dbs = NULL;
275 }
276 if (dev->dbbuf_eis) {
277 dma_free_coherent(dev->dev, mem_size,
278 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
279 dev->dbbuf_eis = NULL;
280 }
281}
282
283static void nvme_dbbuf_init(struct nvme_dev *dev,
284 struct nvme_queue *nvmeq, int qid)
285{
286 if (!dev->dbbuf_dbs || !qid)
287 return;
288
289 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
290 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
291 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
293}
294
295static void nvme_dbbuf_set(struct nvme_dev *dev)
296{
297 struct nvme_command c;
298
299 if (!dev->dbbuf_dbs)
300 return;
301
302 memset(&c, 0, sizeof(c));
303 c.dbbuf.opcode = nvme_admin_dbbuf;
304 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
305 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
306
307 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 308 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 309 /* Free memory and continue on */
310 nvme_dbbuf_dma_free(dev);
311 }
312}
313
314static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
315{
316 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
317}
318
319/* Update dbbuf and return true if an MMIO is required */
320static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
321 volatile u32 *dbbuf_ei)
322{
323 if (dbbuf_db) {
324 u16 old_value;
325
326 /*
327 * Ensure that the queue is written before updating
328 * the doorbell in memory
329 */
330 wmb();
331
332 old_value = *dbbuf_db;
333 *dbbuf_db = value;
334
f1ed3df2
MW		 335 /*
336 * Ensure that the doorbell is updated before reading the event
337 * index from memory. The controller needs to provide similar
338 * ordering to ensure the envent index is updated before reading
339 * the doorbell.
340 */
341 mb();
342
f9f38e33
HK		 343 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
344 return false;
345 }
346
347 return true;
b60503ba
MW		 348}
349
ac3dd5bd
JA		 350/*
351 * Will slightly overestimate the number of pages needed. This is OK
352 * as it only leads to a small amount of wasted memory for the lifetime of
353 * the I/O.
354 */
b13c6393 355static int nvme_pci_npages_prp(void)
ac3dd5bd 356{
b13c6393 357 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 358 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 359 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
360}
361
a7a7cbe3
CK		 362/*
363 * Calculates the number of pages needed for the SGL segments. For example a 4k
364 * page can accommodate 256 SGL descriptors.
365 */
b13c6393 366static int nvme_pci_npages_sgl(void)
ac3dd5bd 367{
b13c6393
CK		 368 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
369 PAGE_SIZE);
f4800d6d 370}
ac3dd5bd 371
b13c6393 372static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 373{
b13c6393 374 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 375
b13c6393
CK		 376 return sizeof(__le64 *) * npages +
377 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 378}
ac3dd5bd 379
a4aea562
MB		 380static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
381 unsigned int hctx_idx)
e85248e5 382{
a4aea562 383 struct nvme_dev *dev = data;
147b27e4 384 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 385
42483228
KB		 386 WARN_ON(hctx_idx != 0);
387 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 388
a4aea562
MB		 389 hctx->driver_data = nvmeq;
390 return 0;
e85248e5
MW		 391}
392
a4aea562
MB		 393static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
394 unsigned int hctx_idx)
b60503ba 395{
a4aea562 396 struct nvme_dev *dev = data;
147b27e4 397 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 398
42483228 399 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 400 hctx->driver_data = nvmeq;
401 return 0;
b60503ba
MW		 402}
403
d6296d39
CH		 404static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
405 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 406{
d6296d39 407 struct nvme_dev *dev = set->driver_data;
f4800d6d 408 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 409 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 410 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 411
412 BUG_ON(!nvmeq);
f4800d6d 413 iod->nvmeq = nvmeq;
59e29ce6
SG		 414
415 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 416 return 0;
417}
418
3b6592f7
JA		 419static int queue_irq_offset(struct nvme_dev *dev)
420{
421 /* if we have more than 1 vec, admin queue offsets us by 1 */
422 if (dev->num_vecs > 1)
423 return 1;
424
425 return 0;
426}
427
dca51e78
CH		 428static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
429{
430 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 431 int i, qoff, offset;
432
433 offset = queue_irq_offset(dev);
434 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
435 struct blk_mq_queue_map *map = &set->map[i];
436
437 map->nr_queues = dev->io_queues[i];
438 if (!map->nr_queues) {
e20ba6e1 439 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 440 continue;
3b6592f7
JA		 441 }
442
4b04cc6a
JA		 443 /*
444 * The poll queue(s) doesn't have an IRQ (and hence IRQ
445 * affinity), so use the regular blk-mq cpu mapping
446 */
3b6592f7 447 map->queue_offset = qoff;
cb9e0e50 448 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 449 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
450 else
451 blk_mq_map_queues(map);
3b6592f7
JA		 452 qoff += map->nr_queues;
453 offset += map->nr_queues;
454 }
455
456 return 0;
dca51e78
CH		 457}
458
38210800
KB		 459/*
460 * Write sq tail if we are asked to, or if the next command would wrap.
461 */
462static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 463{
38210800
KB		 464 if (!write_sq) {
465 u16 next_tail = nvmeq->sq_tail + 1;
466
467 if (next_tail == nvmeq->q_depth)
468 next_tail = 0;
469 if (next_tail != nvmeq->last_sq_tail)
470 return;
471 }
472
04f3eafd
JA		 473 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
474 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
475 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 476 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 477}
478
b60503ba 479/**
90ea5ca4 480 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 481 * @nvmeq: The queue to use
482 * @cmd: The command to send
04f3eafd 483 * @write_sq: whether to write to the SQ doorbell
b60503ba 484 */
04f3eafd
JA		 485static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
486 bool write_sq)
b60503ba 487{
90ea5ca4 488 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 489 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
490 cmd, sizeof(*cmd));
90ea5ca4
CH		 491 if (++nvmeq->sq_tail == nvmeq->q_depth)
492 nvmeq->sq_tail = 0;
38210800 493 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 494 spin_unlock(&nvmeq->sq_lock);
495}
496
497static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498{
499 struct nvme_queue *nvmeq = hctx->driver_data;
500
501 spin_lock(&nvmeq->sq_lock);
38210800
KB		 502 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503 nvme_write_sq_db(nvmeq, true);
90ea5ca4 504 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 505}
506
a7a7cbe3 507static void **nvme_pci_iod_list(struct request *req)
b60503ba 508{
f4800d6d 509 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 510 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 511}
512
955b1b5a
MI		 513static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
514{
515 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 516 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 517 unsigned int avg_seg_size;
518
20469a37 519 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 520
521 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
522 return false;
523 if (!iod->nvmeq->qid)
524 return false;
525 if (!sgl_threshold || avg_seg_size < sgl_threshold)
526 return false;
527 return true;
528}
529
7fe07d14 530static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 531{
f4800d6d 532 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0 533 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
a7a7cbe3 534 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
eca18b23 535 int i;
eca18b23 536
dff824b2 537 if (iod->dma_len) {
f2fa006f
IR		 538 dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
539 rq_dma_dir(req));
dff824b2 540 return;
7fe07d14
CH		 541 }
542
dff824b2
CH		 543 WARN_ON_ONCE(!iod->nents);
544
7f73eac3
LG		 545 if (is_pci_p2pdma_page(sg_page(iod->sg)))
546 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
547 rq_dma_dir(req));
548 else
dff824b2
CH		 549 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
550
551
eca18b23 552 if (iod->npages == 0)
a7a7cbe3
CK		 553 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
554 dma_addr);
555
eca18b23 556 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 557 void *addr = nvme_pci_iod_list(req)[i];
558
559 if (iod->use_sgl) {
560 struct nvme_sgl_desc *sg_list = addr;
561
562 next_dma_addr =
563 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
564 } else {
565 __le64 *prp_list = addr;
566
567 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
568 }
569
570 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
571 dma_addr = next_dma_addr;
eca18b23 572 }
ac3dd5bd 573
d43f1ccf 574 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 575}
576
d0877473
KB		 577static void nvme_print_sgl(struct scatterlist *sgl, int nents)
578{
579 int i;
580 struct scatterlist *sg;
581
582 for_each_sg(sgl, sg, nents, i) {
583 dma_addr_t phys = sg_phys(sg);
584 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
585 "dma_address:%pad dma_length:%d\n",
586 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
587 sg_dma_len(sg));
588 }
589}
590
a7a7cbe3
CK		 591static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
592 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 593{
f4800d6d 594 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 595 struct dma_pool *pool;
b131c61d 596 int length = blk_rq_payload_bytes(req);
eca18b23 597 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 598 int dma_len = sg_dma_len(sg);
599 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 600 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 601 __le64 *prp_list;
a7a7cbe3 602 void **list = nvme_pci_iod_list(req);
e025344c 603 dma_addr_t prp_dma;
eca18b23 604 int nprps, i;
ff22b54f 605
6c3c05b0 606 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 607 if (length <= 0) {
608 iod->first_dma = 0;
a7a7cbe3 609 goto done;
5228b328 610 }
ff22b54f 611
6c3c05b0 612 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 613 if (dma_len) {
6c3c05b0 614 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 615 } else {
616 sg = sg_next(sg);
617 dma_addr = sg_dma_address(sg);
618 dma_len = sg_dma_len(sg);
619 }
620
6c3c05b0 621 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 622 iod->first_dma = dma_addr;
a7a7cbe3 623 goto done;
e025344c
SMM		 624 }
625
6c3c05b0 626 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 627 if (nprps <= (256 / 8)) {
628 pool = dev->prp_small_pool;
eca18b23 629 iod->npages = 0;
99802a7a
MW		 630 } else {
631 pool = dev->prp_page_pool;
eca18b23 632 iod->npages = 1;
99802a7a
MW		 633 }
634
69d2b571 635 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 636 if (!prp_list) {
edd10d33 637 iod->first_dma = dma_addr;
eca18b23 638 iod->npages = -1;
86eea289 639 return BLK_STS_RESOURCE;
b77954cb 640 }
eca18b23
MW		 641 list[0] = prp_list;
642 iod->first_dma = prp_dma;
e025344c
SMM		 643 i = 0;
644 for (;;) {
6c3c05b0 645 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 646 __le64 *old_prp_list = prp_list;
69d2b571 647 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 648 if (!prp_list)
86eea289 649 return BLK_STS_RESOURCE;
eca18b23 650 list[iod->npages++] = prp_list;
7523d834
MW		 651 prp_list[0] = old_prp_list[i - 1];
652 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
653 i = 1;
e025344c
SMM		 654 }
655 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 656 dma_len -= NVME_CTRL_PAGE_SIZE;
657 dma_addr += NVME_CTRL_PAGE_SIZE;
658 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 659 if (length <= 0)
660 break;
661 if (dma_len > 0)
662 continue;
86eea289
KB		 663 if (unlikely(dma_len < 0))
664 goto bad_sgl;
e025344c
SMM		 665 sg = sg_next(sg);
666 dma_addr = sg_dma_address(sg);
667 dma_len = sg_dma_len(sg);
ff22b54f
MW		 668 }
669
a7a7cbe3
CK		 670done:
671 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
672 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
673
86eea289
KB		 674 return BLK_STS_OK;
675
676 bad_sgl:
d0877473
KB		 677 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
678 "Invalid SGL for payload:%d nents:%d\n",
679 blk_rq_payload_bytes(req), iod->nents);
86eea289 680 return BLK_STS_IOERR;
ff22b54f
MW		 681}
682
a7a7cbe3
CK		 683static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
684 struct scatterlist *sg)
685{
686 sge->addr = cpu_to_le64(sg_dma_address(sg));
687 sge->length = cpu_to_le32(sg_dma_len(sg));
688 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
689}
690
691static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
692 dma_addr_t dma_addr, int entries)
693{
694 sge->addr = cpu_to_le64(dma_addr);
695 if (entries < SGES_PER_PAGE) {
696 sge->length = cpu_to_le32(entries * sizeof(*sge));
697 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
698 } else {
699 sge->length = cpu_to_le32(PAGE_SIZE);
700 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
701 }
702}
703
704static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 705 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 706{
707 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 708 struct dma_pool *pool;
709 struct nvme_sgl_desc *sg_list;
710 struct scatterlist *sg = iod->sg;
a7a7cbe3 711 dma_addr_t sgl_dma;
b0f2853b 712 int i = 0;
a7a7cbe3 713
a7a7cbe3
CK		 714 /* setting the transfer type as SGL */
715 cmd->flags = NVME_CMD_SGL_METABUF;
716
b0f2853b 717 if (entries == 1) {
a7a7cbe3
CK		 718 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
719 return BLK_STS_OK;
720 }
721
722 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
723 pool = dev->prp_small_pool;
724 iod->npages = 0;
725 } else {
726 pool = dev->prp_page_pool;
727 iod->npages = 1;
728 }
729
730 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
731 if (!sg_list) {
732 iod->npages = -1;
733 return BLK_STS_RESOURCE;
734 }
735
736 nvme_pci_iod_list(req)[0] = sg_list;
737 iod->first_dma = sgl_dma;
738
739 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
740
741 do {
742 if (i == SGES_PER_PAGE) {
743 struct nvme_sgl_desc *old_sg_desc = sg_list;
744 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
745
746 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
747 if (!sg_list)
748 return BLK_STS_RESOURCE;
749
750 i = 0;
751 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
752 sg_list[i++] = *link;
753 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
754 }
755
756 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 757 sg = sg_next(sg);
b0f2853b 758 } while (--entries > 0);
a7a7cbe3 759
a7a7cbe3
CK		 760 return BLK_STS_OK;
761}
762
dff824b2
CH		 763static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
764 struct request *req, struct nvme_rw_command *cmnd,
765 struct bio_vec *bv)
766{
767 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 768 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
769 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 770
771 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
772 if (dma_mapping_error(dev->dev, iod->first_dma))
773 return BLK_STS_RESOURCE;
774 iod->dma_len = bv->bv_len;
775
776 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
777 if (bv->bv_len > first_prp_len)
778 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 779 return BLK_STS_OK;
dff824b2
CH		 780}
781
29791057
CH		 782static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
783 struct request *req, struct nvme_rw_command *cmnd,
784 struct bio_vec *bv)
785{
786 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
787
788 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
789 if (dma_mapping_error(dev->dev, iod->first_dma))
790 return BLK_STS_RESOURCE;
791 iod->dma_len = bv->bv_len;
792
049bf372 793 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 794 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
795 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
796 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 797 return BLK_STS_OK;
29791057
CH		 798}
799
fc17b653 800static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 801 struct nvme_command *cmnd)
d29ec824 802{
f4800d6d 803 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 804 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 805 int nr_mapped;
d29ec824 806
dff824b2
CH		 807 if (blk_rq_nr_phys_segments(req) == 1) {
808 struct bio_vec bv = req_bvec(req);
809
810 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 811 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 812 return nvme_setup_prp_simple(dev, req,
813 &cmnd->rw, &bv);
29791057
CH		 814
815 if (iod->nvmeq->qid &&
816 dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
817 return nvme_setup_sgl_simple(dev, req,
818 &cmnd->rw, &bv);
dff824b2
CH		 819 }
820 }
821
822 iod->dma_len = 0;
d43f1ccf
CH		 823 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
824 if (!iod->sg)
825 return BLK_STS_RESOURCE;
f9d03f96 826 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 827 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e
CH		 828 if (!iod->nents)
829 goto out;
d29ec824 830
e0596ab2 831 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 832 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
833 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 834 else
835 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 836 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 837 if (!nr_mapped)
ba1ca37e 838 goto out;
d29ec824 839
70479b71 840 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 841 if (iod->use_sgl)
b0f2853b 842 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 843 else
844 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
4aedb705 845out:
86eea289 846 if (ret != BLK_STS_OK)
4aedb705
CH		 847 nvme_unmap_data(dev, req);
848 return ret;
849}
3045c0d0 850
4aedb705
CH		 851static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
852 struct nvme_command *cmnd)
853{
854 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 855
4aedb705
CH		 856 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
857 rq_dma_dir(req), 0);
858 if (dma_mapping_error(dev->dev, iod->meta_dma))
859 return BLK_STS_IOERR;
860 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 861 return BLK_STS_OK;
00df5cb4
MW		 862}
863
d29ec824
CH		 864/*
865 * NOTE: ns is NULL when called on the admin queue.
866 */
fc17b653 867static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 868 const struct blk_mq_queue_data *bd)
edd10d33 869{
a4aea562
MB		 870 struct nvme_ns *ns = hctx->queue->queuedata;
871 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 872 struct nvme_dev *dev = nvmeq->dev;
a4aea562 873 struct request *req = bd->rq;
9b048119 874 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e 875 struct nvme_command cmnd;
ebe6d874 876 blk_status_t ret;
e1e5e564 877
9b048119
CH		 878 iod->aborted = 0;
879 iod->npages = -1;
880 iod->nents = 0;
881
d1f06f4a
JA		 882 /*
883 * We should not need to do this, but we're still using this to
884 * ensure we can drain requests on a dying queue.
885 */
4e224106 886 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 887 return BLK_STS_IOERR;
888
f9d03f96 889 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 890 if (ret)
f4800d6d 891 return ret;
a4aea562 892
fc17b653 893 if (blk_rq_nr_phys_segments(req)) {
b131c61d 894 ret = nvme_map_data(dev, req, &cmnd);
fc17b653 895 if (ret)
9b048119 896 goto out_free_cmd;
fc17b653 897 }
a4aea562 898
4aedb705
CH		 899 if (blk_integrity_rq(req)) {
900 ret = nvme_map_metadata(dev, req, &cmnd);
901 if (ret)
902 goto out_unmap_data;
903 }
904
aae239e1 905 blk_mq_start_request(req);
04f3eafd 906 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 907 return BLK_STS_OK;
4aedb705
CH		 908out_unmap_data:
909 nvme_unmap_data(dev, req);
f9d03f96
CH		 910out_free_cmd:
911 nvme_cleanup_cmd(req);
ba1ca37e 912 return ret;
b60503ba 913}
e1e5e564 914
77f02a7a 915static void nvme_pci_complete_rq(struct request *req)
eee417b0 916{
f4800d6d 917 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 918 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 919
4aedb705
CH		 920 if (blk_integrity_rq(req))
921 dma_unmap_page(dev->dev, iod->meta_dma,
922 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 923 if (blk_rq_nr_phys_segments(req))
4aedb705 924 nvme_unmap_data(dev, req);
77f02a7a 925 nvme_complete_rq(req);
b60503ba
MW		 926}
927
d783e0bd 928/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 929static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 930{
74943d45
KB		 931 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
932
933 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 934}
935
eb281c82 936static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 937{
eb281c82 938 u16 head = nvmeq->cq_head;
adf68f21 939
397c699f
KB		 940 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
941 nvmeq->dbbuf_cq_ei))
942 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 943}
aae239e1 944
cfa27356
CH		 945static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
946{
947 if (!nvmeq->qid)
948 return nvmeq->dev->admin_tagset.tags[0];
949 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
950}
951
5cb525c8 952static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 953{
74943d45 954 struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 955 struct request *req;
adf68f21 956
83a12fb7
SG		 957 /*
958 * AEN requests are special as they don't time out and can
959 * survive any kind of queue freeze and often don't respond to
960 * aborts. We don't even bother to allocate a struct request
961 * for them but rather special case them here.
962 */
58a8df67 963 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
83a12fb7
SG		 964 nvme_complete_async_event(&nvmeq->dev->ctrl,
965 cqe->status, &cqe->result);
a0fa9647 966 return;
83a12fb7 967 }
b60503ba 968
cfa27356 969 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
50b7c243
XT		 970 if (unlikely(!req)) {
971 dev_warn(nvmeq->dev->ctrl.device,
972 "invalid id %d completed on queue %d\n",
973 cqe->command_id, le16_to_cpu(cqe->sq_id));
974 return;
975 }
976
604c01d5 977 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 978 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 979 nvme_pci_complete_rq(req);
83a12fb7 980}
b60503ba 981
5cb525c8
JA		 982static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
983{
a8de6639
AD		 984 u16 tmp = nvmeq->cq_head + 1;
985
986 if (tmp == nvmeq->q_depth) {
5cb525c8 987 nvmeq->cq_head = 0;
e2a366a4 988 nvmeq->cq_phase ^= 1;
a8de6639
AD		 989 } else {
990 nvmeq->cq_head = tmp;
b60503ba 991 }
a0fa9647
JA		 992}
993
324b494c 994static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 995{
1052b8ac 996 int found = 0;
b60503ba 997
1052b8ac 998 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 999 found++;
b69e2ef2
KB		 1000 /*
1001 * load-load control dependency between phase and the rest of
1002 * the cqe requires a full read memory barrier
1003 */
1004 dma_rmb();
324b494c 1005 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1006 nvme_update_cq_head(nvmeq);
920d13a8 1007 }
eb281c82 1008
324b494c 1009 if (found)
920d13a8 1010 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1011 return found;
b60503ba
MW		 1012}
1013
1014static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1015{
58ffacb5 1016 struct nvme_queue *nvmeq = data;
68fa9dbe 1017 irqreturn_t ret = IRQ_NONE;
5cb525c8 1018
3a7afd8e
CH		 1019 /*
1020 * The rmb/wmb pair ensures we see all updates from a previous run of
1021 * the irq handler, even if that was on another CPU.
1022 */
1023 rmb();
324b494c
KB		 1024 if (nvme_process_cq(nvmeq))
1025 ret = IRQ_HANDLED;
3a7afd8e 1026 wmb();
5cb525c8 1027
68fa9dbe 1028 return ret;
58ffacb5
MW		 1029}
1030
1031static irqreturn_t nvme_irq_check(int irq, void *data)
1032{
1033 struct nvme_queue *nvmeq = data;
4e523547 1034
750dde44 1035 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1036 return IRQ_WAKE_THREAD;
1037 return IRQ_NONE;
58ffacb5
MW		 1038}
1039
0b2a8a9f 1040/*
fa059b85 1041 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1042 * Can be called from any context.
1043 */
fa059b85 1044static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1045{
3a7afd8e 1046 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1047
fa059b85 1048 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1049
fa059b85
KB		 1050 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1051 nvme_process_cq(nvmeq);
1052 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1053}
1054
9743139c 1055static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1056{
1057 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1058 bool found;
1059
1060 if (!nvme_cqe_pending(nvmeq))
1061 return 0;
1062
3a7afd8e 1063 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1064 found = nvme_process_cq(nvmeq);
3a7afd8e 1065 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1066
dabcefab
JA		 1067 return found;
1068}
1069
ad22c355 1070static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1071{
f866fc42 1072 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1073 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1074 struct nvme_command c;
b60503ba 1075
a4aea562
MB		 1076 memset(&c, 0, sizeof(c));
1077 c.common.opcode = nvme_admin_async_event;
ad22c355 1078 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1079 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1080}
1081
b60503ba 1082static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1083{
b60503ba
MW		 1084 struct nvme_command c;
1085
1086 memset(&c, 0, sizeof(c));
1087 c.delete_queue.opcode = opcode;
1088 c.delete_queue.qid = cpu_to_le16(id);
1089
1c63dc66 1090 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1091}
1092
b60503ba 1093static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1094 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1095{
b60503ba 1096 struct nvme_command c;
4b04cc6a
JA		 1097 int flags = NVME_QUEUE_PHYS_CONTIG;
1098
7c349dde 1099 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1100 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1101
d29ec824 1102 /*
16772ae6 1103 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1104 * is attached to the request.
1105 */
b60503ba
MW		 1106 memset(&c, 0, sizeof(c));
1107 c.create_cq.opcode = nvme_admin_create_cq;
1108 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1109 c.create_cq.cqid = cpu_to_le16(qid);
1110 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1111 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1112 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1113
1c63dc66 1114 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1115}
1116
1117static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1118 struct nvme_queue *nvmeq)
1119{
9abd68ef 1120 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1121 struct nvme_command c;
81c1cd98 1122 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1123
9abd68ef
JA		 1124 /*
1125 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1126 * set. Since URGENT priority is zeroes, it makes all queues
1127 * URGENT.
1128 */
1129 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1130 flags |= NVME_SQ_PRIO_MEDIUM;
1131
d29ec824 1132 /*
16772ae6 1133 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1134 * is attached to the request.
1135 */
b60503ba
MW		 1136 memset(&c, 0, sizeof(c));
1137 c.create_sq.opcode = nvme_admin_create_sq;
1138 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1139 c.create_sq.sqid = cpu_to_le16(qid);
1140 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1141 c.create_sq.sq_flags = cpu_to_le16(flags);
1142 c.create_sq.cqid = cpu_to_le16(qid);
1143
1c63dc66 1144 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1145}
1146
1147static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1148{
1149 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1150}
1151
1152static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1153{
1154 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1155}
1156
2a842aca 1157static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1158{
f4800d6d
CH		 1159 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1160 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1161
27fa9bc5
CH		 1162 dev_warn(nvmeq->dev->ctrl.device,
1163 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1164 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1165 blk_mq_free_request(req);
bc5fc7e4
MW		 1166}
1167
b2a0eb1a
KB		 1168static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1169{
b2a0eb1a
KB		 1170 /* If true, indicates loss of adapter communication, possibly by a
1171 * NVMe Subsystem reset.
1172 */
1173 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1174
ad70062c
JW		 1175 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1176 switch (dev->ctrl.state) {
1177 case NVME_CTRL_RESETTING:
ad6a0a52 1178 case NVME_CTRL_CONNECTING:
b2a0eb1a 1179 return false;
ad70062c
JW		 1180 default:
1181 break;
1182 }
b2a0eb1a
KB		 1183
1184 /* We shouldn't reset unless the controller is on fatal error state
1185 * _or_ if we lost the communication with it.
1186 */
1187 if (!(csts & NVME_CSTS_CFS) && !nssro)
1188 return false;
1189
b2a0eb1a
KB		 1190 return true;
1191}
1192
1193static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1194{
1195 /* Read a config register to help see what died. */
1196 u16 pci_status;
1197 int result;
1198
1199 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1200 &pci_status);
1201 if (result == PCIBIOS_SUCCESSFUL)
1202 dev_warn(dev->ctrl.device,
1203 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1204 csts, pci_status);
1205 else
1206 dev_warn(dev->ctrl.device,
1207 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1208 csts, result);
1209}
1210
31c7c7d2 1211static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1212{
f4800d6d
CH		 1213 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1214 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1215 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1216 struct request *abort_req;
a4aea562 1217 struct nvme_command cmd;
b2a0eb1a
KB		 1218 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1219
651438bb
WX		 1220 /* If PCI error recovery process is happening, we cannot reset or
1221 * the recovery mechanism will surely fail.
1222 */
1223 mb();
1224 if (pci_channel_offline(to_pci_dev(dev->dev)))
1225 return BLK_EH_RESET_TIMER;
1226
b2a0eb1a
KB		 1227 /*
1228 * Reset immediately if the controller is failed
1229 */
1230 if (nvme_should_reset(dev, csts)) {
1231 nvme_warn_reset(dev, csts);
1232 nvme_dev_disable(dev, false);
d86c4d8e 1233 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1234 return BLK_EH_DONE;
b2a0eb1a 1235 }
c30341dc 1236
7776db1c
KB		 1237 /*
1238 * Did we miss an interrupt?
1239 */
fa059b85
KB		 1240 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1241 nvme_poll(req->mq_hctx);
1242 else
1243 nvme_poll_irqdisable(nvmeq);
1244
bf392a5d 1245 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1246 dev_warn(dev->ctrl.device,
1247 "I/O %d QID %d timeout, completion polled\n",
1248 req->tag, nvmeq->qid);
db8c48e4 1249 return BLK_EH_DONE;
7776db1c
KB		 1250 }
1251
31c7c7d2 1252 /*
fd634f41
CH		 1253 * Shutdown immediately if controller times out while starting. The
1254 * reset work will see the pci device disabled when it gets the forced
1255 * cancellation error. All outstanding requests are completed on
db8c48e4 1256 * shutdown, so we return BLK_EH_DONE.
fd634f41 1257 */
4244140d
KB		 1258 switch (dev->ctrl.state) {
1259 case NVME_CTRL_CONNECTING:
2036f726 1260 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1261 fallthrough;
2036f726 1262 case NVME_CTRL_DELETING:
b9cac43c 1263 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1264 "I/O %d QID %d timeout, disable controller\n",
1265 req->tag, nvmeq->qid);
27fa9bc5 1266 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1267 nvme_dev_disable(dev, true);
db8c48e4 1268 return BLK_EH_DONE;
39a9dd81
KB		 1269 case NVME_CTRL_RESETTING:
1270 return BLK_EH_RESET_TIMER;
4244140d
KB		 1271 default:
1272 break;
c30341dc
KB		 1273 }
1274
fd634f41 1275 /*
ee0d96d3
BW		 1276 * Shutdown the controller immediately and schedule a reset if the
1277 * command was already aborted once before and still hasn't been
1278 * returned to the driver, or if this is the admin queue.
31c7c7d2 1279 */
f4800d6d 1280 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1281 dev_warn(dev->ctrl.device,
e1569a16
KB		 1282 "I/O %d QID %d timeout, reset controller\n",
1283 req->tag, nvmeq->qid);
7ad92f65 1284 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1285 nvme_dev_disable(dev, false);
d86c4d8e 1286 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1287
db8c48e4 1288 return BLK_EH_DONE;
c30341dc 1289 }
c30341dc 1290
e7a2a87d 1291 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1292 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1293 return BLK_EH_RESET_TIMER;
6bf25d16 1294 }
7bf7d778 1295 iod->aborted = 1;
a4aea562 1296
c30341dc
KB		 1297 memset(&cmd, 0, sizeof(cmd));
1298 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1299 cmd.abort.cid = req->tag;
c30341dc 1300 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1301
1b3c47c1
SG		 1302 dev_warn(nvmeq->dev->ctrl.device,
1303 "I/O %d QID %d timeout, aborting\n",
1304 req->tag, nvmeq->qid);
e7a2a87d
CH		 1305
1306 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1307 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1308 if (IS_ERR(abort_req)) {
1309 atomic_inc(&dev->ctrl.abort_limit);
1310 return BLK_EH_RESET_TIMER;
1311 }
1312
e7a2a87d
CH		 1313 abort_req->end_io_data = NULL;
1314 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1315
31c7c7d2
CH		 1316 /*
1317 * The aborted req will be completed on receiving the abort req.
1318 * We enable the timer again. If hit twice, it'll cause a device reset,
1319 * as the device then is in a faulty state.
1320 */
1321 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1322}
1323
a4aea562
MB		 1324static void nvme_free_queue(struct nvme_queue *nvmeq)
1325{
8a1d09a6 1326 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1327 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1328 if (!nvmeq->sq_cmds)
1329 return;
0f238ff5 1330
63223078 1331 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1332 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1333 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1334 } else {
8a1d09a6 1335 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1336 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1337 }
9e866774
MW		 1338}
1339
a1a5ef99 1340static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1341{
1342 int i;
1343
d858e5f0 1344 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1345 dev->ctrl.queue_count--;
147b27e4 1346 nvme_free_queue(&dev->queues[i]);
121c7ad4 1347 }
22404274
KB		 1348}
1349
4d115420
KB		 1350/**
1351 * nvme_suspend_queue - put queue into suspended state
40581d1a 1352 * @nvmeq: queue to suspend
4d115420
KB		 1353 */
1354static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1355{
4e224106 1356 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1357 return 1;
a09115b2 1358
4e224106 1359 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1360 mb();
a09115b2 1361
4e224106 1362 nvmeq->dev->online_queues--;
1c63dc66 1363 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1364 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1365 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1366 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1367 return 0;
1368}
b60503ba 1369
8fae268b
KB		 1370static void nvme_suspend_io_queues(struct nvme_dev *dev)
1371{
1372 int i;
1373
1374 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1375 nvme_suspend_queue(&dev->queues[i]);
1376}
1377
a5cdb68c 1378static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1379{
147b27e4 1380 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1381
a5cdb68c
KB		 1382 if (shutdown)
1383 nvme_shutdown_ctrl(&dev->ctrl);
1384 else
b5b05048 1385 nvme_disable_ctrl(&dev->ctrl);
07836e65 1386
bf392a5d 1387 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1388}
1389
fa46c6fb
KB		 1390/*
1391 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1392 * that can check this device's completion queues have synced, except
1393 * nvme_poll(). This is the last chance for the driver to see a natural
1394 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1395 */
1396static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1397{
fa46c6fb
KB		 1398 int i;
1399
9210c075
DZ		 1400 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1401 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1402 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1403 spin_unlock(&dev->queues[i].cq_poll_lock);
1404 }
fa46c6fb
KB		 1405}
1406
8ffaadf7
JD		 1407static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1408 int entry_size)
1409{
1410 int q_depth = dev->q_depth;
5fd4ce1b 1411 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1412 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1413
1414 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1415 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1416
6c3c05b0 1417 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1418 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1419
1420 /*
1421 * Ensure the reduced q_depth is above some threshold where it
1422 * would be better to map queues in system memory with the
1423 * original depth
1424 */
1425 if (q_depth < 64)
1426 return -ENOMEM;
1427 }
1428
1429 return q_depth;
1430}
1431
1432static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1433 int qid)
8ffaadf7 1434{
0f238ff5
LG		 1435 struct pci_dev *pdev = to_pci_dev(dev->dev);
1436
1437 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1438 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1439 if (nvmeq->sq_cmds) {
1440 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1441 nvmeq->sq_cmds);
1442 if (nvmeq->sq_dma_addr) {
1443 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1444 return 0;
1445 }
1446
8a1d09a6 1447 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1448 }
0f238ff5 1449 }
8ffaadf7 1450
8a1d09a6 1451 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1452 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1453 if (!nvmeq->sq_cmds)
1454 return -ENOMEM;
8ffaadf7
JD		 1455 return 0;
1456}
1457
a6ff7262 1458static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1459{
147b27e4 1460 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1461
62314e40
KB		 1462 if (dev->ctrl.queue_count > qid)
1463 return 0;
b60503ba 1464
c1e0cc7e 1465 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1466 nvmeq->q_depth = depth;
1467 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1468 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1469 if (!nvmeq->cqes)
1470 goto free_nvmeq;
b60503ba 1471
8a1d09a6 1472 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1473 goto free_cqdma;
1474
091b6092 1475 nvmeq->dev = dev;
1ab0cd69 1476 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1477 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1478 nvmeq->cq_head = 0;
82123460 1479 nvmeq->cq_phase = 1;
b80d5ccc 1480 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1481 nvmeq->qid = qid;
d858e5f0 1482 dev->ctrl.queue_count++;
36a7e993 1483
147b27e4 1484 return 0;
b60503ba
MW		 1485
1486 free_cqdma:
8a1d09a6
BH		 1487 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1488 nvmeq->cq_dma_addr);
b60503ba 1489 free_nvmeq:
147b27e4 1490 return -ENOMEM;
b60503ba
MW		 1491}
1492
dca51e78 1493static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1494{
0ff199cb
CH		 1495 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1496 int nr = nvmeq->dev->ctrl.instance;
1497
1498 if (use_threaded_interrupts) {
1499 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1500 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1501 } else {
1502 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1503 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1504 }
3001082c
MW		 1505}
1506
22404274 1507static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1508{
22404274 1509 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1510
22404274 1511 nvmeq->sq_tail = 0;
38210800 1512 nvmeq->last_sq_tail = 0;
22404274
KB		 1513 nvmeq->cq_head = 0;
1514 nvmeq->cq_phase = 1;
b80d5ccc 1515 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1516 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1517 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1518 dev->online_queues++;
3a7afd8e 1519 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1520}
1521
4b04cc6a 1522static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1523{
1524 struct nvme_dev *dev = nvmeq->dev;
1525 int result;
7c349dde 1526 u16 vector = 0;
3f85d50b 1527
d1ed6aa1
CH		 1528 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1529
22b55601
KB		 1530 /*
1531 * A queue's vector matches the queue identifier unless the controller
1532 * has only one vector available.
1533 */
4b04cc6a
JA		 1534 if (!polled)
1535 vector = dev->num_vecs == 1 ? 0 : qid;
1536 else
7c349dde 1537 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1538
a8e3e0bb 1539 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1540 if (result)
1541 return result;
b60503ba
MW		 1542
1543 result = adapter_alloc_sq(dev, qid, nvmeq);
1544 if (result < 0)
ded45505 1545 return result;
c80b36cd 1546 if (result)
b60503ba
MW		 1547 goto release_cq;
1548
a8e3e0bb 1549 nvmeq->cq_vector = vector;
161b8be2 1550 nvme_init_queue(nvmeq, qid);
4b04cc6a 1551
7c349dde 1552 if (!polled) {
4b04cc6a
JA		 1553 result = queue_request_irq(nvmeq);
1554 if (result < 0)
1555 goto release_sq;
1556 }
b60503ba 1557
4e224106 1558 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1559 return result;
b60503ba 1560
a8e3e0bb 1561release_sq:
f25a2dfc 1562 dev->online_queues--;
b60503ba 1563 adapter_delete_sq(dev, qid);
a8e3e0bb 1564release_cq:
b60503ba 1565 adapter_delete_cq(dev, qid);
22404274 1566 return result;
b60503ba
MW		 1567}
1568
f363b089 1569static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1570 .queue_rq = nvme_queue_rq,
77f02a7a 1571 .complete = nvme_pci_complete_rq,
a4aea562 1572 .init_hctx = nvme_admin_init_hctx,
0350815a 1573 .init_request = nvme_init_request,
a4aea562
MB		 1574 .timeout = nvme_timeout,
1575};
1576
f363b089 1577static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1578 .queue_rq = nvme_queue_rq,
1579 .complete = nvme_pci_complete_rq,
1580 .commit_rqs = nvme_commit_rqs,
1581 .init_hctx = nvme_init_hctx,
1582 .init_request = nvme_init_request,
1583 .map_queues = nvme_pci_map_queues,
1584 .timeout = nvme_timeout,
1585 .poll = nvme_poll,
dabcefab
JA		 1586};
1587
ea191d2f
KB		 1588static void nvme_dev_remove_admin(struct nvme_dev *dev)
1589{
1c63dc66 1590 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1591 /*
1592 * If the controller was reset during removal, it's possible
1593 * user requests may be waiting on a stopped queue. Start the
1594 * queue to flush these to completion.
1595 */
c81545f9 1596 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1597 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1598 blk_mq_free_tag_set(&dev->admin_tagset);
1599 }
1600}
1601
a4aea562
MB		 1602static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1603{
1c63dc66 1604 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1605 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1606 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1607
38dabe21 1608 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1609 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
d4ec47f1 1610 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1611 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1612 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1613 dev->admin_tagset.driver_data = dev;
1614
1615 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1616 return -ENOMEM;
34b6c231 1617 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1618
1c63dc66
CH		 1619 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1620 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1621 blk_mq_free_tag_set(&dev->admin_tagset);
1622 return -ENOMEM;
1623 }
1c63dc66 1624 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1625 nvme_dev_remove_admin(dev);
1c63dc66 1626 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1627 return -ENODEV;
1628 }
0fb59cbc 1629 } else
c81545f9 1630 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1631
1632 return 0;
1633}
1634
97f6ef64
XY		 1635static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1636{
1637 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1638}
1639
1640static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1641{
1642 struct pci_dev *pdev = to_pci_dev(dev->dev);
1643
1644 if (size <= dev->bar_mapped_size)
1645 return 0;
1646 if (size > pci_resource_len(pdev, 0))
1647 return -ENOMEM;
1648 if (dev->bar)
1649 iounmap(dev->bar);
1650 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1651 if (!dev->bar) {
1652 dev->bar_mapped_size = 0;
1653 return -ENOMEM;
1654 }
1655 dev->bar_mapped_size = size;
1656 dev->dbs = dev->bar + NVME_REG_DBS;
1657
1658 return 0;
1659}
1660
01ad0990 1661static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1662{
ba47e386 1663 int result;
b60503ba
MW		 1664 u32 aqa;
1665 struct nvme_queue *nvmeq;
1666
97f6ef64
XY		 1667 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1668 if (result < 0)
1669 return result;
1670
8ef2074d 1671 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1672 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1673
7a67cbea
CH		 1674 if (dev->subsystem &&
1675 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1676 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1677
b5b05048 1678 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1679 if (result < 0)
1680 return result;
b60503ba 1681
a6ff7262 1682 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1683 if (result)
1684 return result;
b60503ba 1685
635333e4
MG		 1686 dev->ctrl.numa_node = dev_to_node(dev->dev);
1687
147b27e4 1688 nvmeq = &dev->queues[0];
b60503ba
MW		 1689 aqa = nvmeq->q_depth - 1;
1690 aqa |= aqa << 16;
1691
7a67cbea
CH		 1692 writel(aqa, dev->bar + NVME_REG_AQA);
1693 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1694 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1695
c0f2f45b 1696 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1697 if (result)
d4875622 1698 return result;
a4aea562 1699
2b25d981 1700 nvmeq->cq_vector = 0;
161b8be2 1701 nvme_init_queue(nvmeq, 0);
dca51e78 1702 result = queue_request_irq(nvmeq);
758dd7fd 1703 if (result) {
7c349dde 1704 dev->online_queues--;
d4875622 1705 return result;
758dd7fd 1706 }
025c557a 1707
4e224106 1708 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1709 return result;
1710}
1711
749941f2 1712static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1713{
4b04cc6a 1714 unsigned i, max, rw_queues;
749941f2 1715 int ret = 0;
42f61420 1716
d858e5f0 1717 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1718 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1719 ret = -ENOMEM;
42f61420 1720 break;
749941f2
CH		 1721 }
1722 }
42f61420 1723
d858e5f0 1724 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1725 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1726 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1727 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1728 } else {
1729 rw_queues = max;
1730 }
1731
949928c1 1732 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1733 bool polled = i > rw_queues;
1734
1735 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1736 if (ret)
42f61420 1737 break;
27e8166c 1738 }
749941f2
CH		 1739
1740 /*
1741 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1742 * than the desired amount of queues, and even a controller without
1743 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1744 * be useful to upgrade a buggy firmware for example.
1745 */
1746 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1747}
1748
202021c1
SB		 1749static ssize_t nvme_cmb_show(struct device *dev,
1750 struct device_attribute *attr,
1751 char *buf)
1752{
1753 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1754
c965809c 1755 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1756 ndev->cmbloc, ndev->cmbsz);
1757}
1758static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1759
88de4598 1760static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1761{
88de4598
CH		 1762 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1763
1764 return 1ULL << (12 + 4 * szu);
1765}
1766
1767static u32 nvme_cmb_size(struct nvme_dev *dev)
1768{
1769 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1770}
1771
f65efd6d 1772static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1773{
88de4598 1774 u64 size, offset;
8ffaadf7
JD		 1775 resource_size_t bar_size;
1776 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1777 int bar;
8ffaadf7 1778
9fe5c59f
KB		 1779 if (dev->cmb_size)
1780 return;
1781
7a67cbea 1782 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1783 if (!dev->cmbsz)
1784 return;
202021c1 1785 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1786
88de4598
CH		 1787 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1788 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1789 bar = NVME_CMB_BIR(dev->cmbloc);
1790 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1791
1792 if (offset > bar_size)
f65efd6d 1793 return;
8ffaadf7
JD		 1794
1795 /*
1796 * Controllers may support a CMB size larger than their BAR,
1797 * for example, due to being behind a bridge. Reduce the CMB to
1798 * the reported size of the BAR
1799 */
1800 if (size > bar_size - offset)
1801 size = bar_size - offset;
1802
0f238ff5
LG		 1803 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1804 dev_warn(dev->ctrl.device,
1805 "failed to register the CMB\n");
f65efd6d 1806 return;
0f238ff5
LG		 1807 }
1808
8ffaadf7 1809 dev->cmb_size = size;
0f238ff5
LG		 1810 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1811
1812 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1813 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1814 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1815
1816 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1817 &dev_attr_cmb.attr, NULL))
1818 dev_warn(dev->ctrl.device,
1819 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1820}
1821
1822static inline void nvme_release_cmb(struct nvme_dev *dev)
1823{
0f238ff5 1824 if (dev->cmb_size) {
1c78f773
MG		 1825 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1826 &dev_attr_cmb.attr, NULL);
0f238ff5 1827 dev->cmb_size = 0;
8ffaadf7
JD		 1828 }
1829}
1830
87ad72a5
CH		 1831static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1832{
6c3c05b0 1833 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1834 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1835 struct nvme_command c;
87ad72a5
CH		 1836 int ret;
1837
87ad72a5
CH		 1838 memset(&c, 0, sizeof(c));
1839 c.features.opcode = nvme_admin_set_features;
1840 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1841 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1842 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1843 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1844 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1845 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1846
1847 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1848 if (ret) {
1849 dev_warn(dev->ctrl.device,
1850 "failed to set host mem (err %d, flags %#x).\n",
1851 ret, bits);
1852 }
87ad72a5
CH		 1853 return ret;
1854}
1855
1856static void nvme_free_host_mem(struct nvme_dev *dev)
1857{
1858 int i;
1859
1860 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1861 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1862 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1863
cc667f6d
LD		 1864 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1865 le64_to_cpu(desc->addr),
1866 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1867 }
1868
1869 kfree(dev->host_mem_desc_bufs);
1870 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1871 dma_free_coherent(dev->dev,
1872 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1873 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1874 dev->host_mem_descs = NULL;
7e5dd57e 1875 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1876}
1877
92dc6895
CH		 1878static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1879 u32 chunk_size)
9d713c2b 1880{
87ad72a5 1881 struct nvme_host_mem_buf_desc *descs;
92dc6895 1882 u32 max_entries, len;
4033f35d 1883 dma_addr_t descs_dma;
2ee0e4ed 1884 int i = 0;
87ad72a5 1885 void **bufs;
6fbcde66 1886 u64 size, tmp;
87ad72a5 1887
87ad72a5
CH		 1888 tmp = (preferred + chunk_size - 1);
1889 do_div(tmp, chunk_size);
1890 max_entries = tmp;
044a9df1
CH		 1891
1892 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1893 max_entries = dev->ctrl.hmmaxd;
1894
750afb08
LC		 1895 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1896 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1897 if (!descs)
1898 goto out;
1899
1900 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1901 if (!bufs)
1902 goto out_free_descs;
1903
244a8fe4 1904 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1905 dma_addr_t dma_addr;
1906
50cdb7c6 1907 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1908 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1909 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1910 if (!bufs[i])
1911 break;
1912
1913 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1914 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1915 i++;
1916 }
1917
92dc6895 1918 if (!size)
87ad72a5 1919 goto out_free_bufs;
87ad72a5 1920
87ad72a5
CH		 1921 dev->nr_host_mem_descs = i;
1922 dev->host_mem_size = size;
1923 dev->host_mem_descs = descs;
4033f35d 1924 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1925 dev->host_mem_desc_bufs = bufs;
1926 return 0;
1927
1928out_free_bufs:
1929 while (--i >= 0) {
6c3c05b0 1930 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1931
cc667f6d
LD		 1932 dma_free_attrs(dev->dev, size, bufs[i],
1933 le64_to_cpu(descs[i].addr),
1934 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1935 }
1936
1937 kfree(bufs);
1938out_free_descs:
4033f35d
CH		 1939 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1940 descs_dma);
87ad72a5 1941out:
87ad72a5
CH		 1942 dev->host_mem_descs = NULL;
1943 return -ENOMEM;
1944}
1945
92dc6895
CH		 1946static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1947{
9dc54a0d
CK		 1948 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1949 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1950 u64 chunk_size;
92dc6895
CH		 1951
1952 /* start big and work our way down */
9dc54a0d 1953 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 1954 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1955 if (!min || dev->host_mem_size >= min)
1956 return 0;
1957 nvme_free_host_mem(dev);
1958 }
1959 }
1960
1961 return -ENOMEM;
1962}
1963
9620cfba 1964static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1965{
1966 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1967 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1968 u64 min = (u64)dev->ctrl.hmmin * 4096;
1969 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1970 int ret;
87ad72a5
CH		 1971
1972 preferred = min(preferred, max);
1973 if (min > max) {
1974 dev_warn(dev->ctrl.device,
1975 "min host memory (%lld MiB) above limit (%d MiB).\n",
1976 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1977 nvme_free_host_mem(dev);
9620cfba 1978 return 0;
87ad72a5
CH		 1979 }
1980
1981 /*
1982 * If we already have a buffer allocated check if we can reuse it.
1983 */
1984 if (dev->host_mem_descs) {
1985 if (dev->host_mem_size >= min)
1986 enable_bits |= NVME_HOST_MEM_RETURN;
1987 else
1988 nvme_free_host_mem(dev);
1989 }
1990
1991 if (!dev->host_mem_descs) {
92dc6895
CH		 1992 if (nvme_alloc_host_mem(dev, min, preferred)) {
1993 dev_warn(dev->ctrl.device,
1994 "failed to allocate host memory buffer.\n");
9620cfba 1995 return 0; /* controller must work without HMB */
92dc6895
CH		 1996 }
1997
1998 dev_info(dev->ctrl.device,
1999 "allocated %lld MiB host memory buffer.\n",
2000 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2001 }
2002
9620cfba
CH		 2003 ret = nvme_set_host_mem(dev, enable_bits);
2004 if (ret)
87ad72a5 2005 nvme_free_host_mem(dev);
9620cfba 2006 return ret;
9d713c2b
KB		 2007}
2008
612b7286
ML		 2009/*
2010 * nirqs is the number of interrupts available for write and read
2011 * queues. The core already reserved an interrupt for the admin queue.
2012 */
2013static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2014{
612b7286 2015 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2016 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2017
2018 /*
ee0d96d3 2019 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2020 * the default queue is set to 1. The affinity set size is
2021 * also set to one, but the irq core ignores it for this case.
2022 *
2023 * If only one interrupt is available or 'write_queue' == 0, combine
2024 * write and read queues.
2025 *
2026 * If 'write_queues' > 0, ensure it leaves room for at least one read
2027 * queue.
3b6592f7 2028 */
612b7286
ML		 2029 if (!nrirqs) {
2030 nrirqs = 1;
2031 nr_read_queues = 0;
2a5bcfdd 2032 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2033 nr_read_queues = 0;
2a5bcfdd 2034 } else if (nr_write_queues >= nrirqs) {
612b7286 2035 nr_read_queues = 1;
3b6592f7 2036 } else {
2a5bcfdd 2037 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2038 }
612b7286
ML		 2039
2040 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2041 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2042 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2043 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2044 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2045}
2046
6451fe73 2047static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2048{
2049 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2050 struct irq_affinity affd = {
9cfef55b 2051 .pre_vectors = 1,
612b7286
ML		 2052 .calc_sets = nvme_calc_irq_sets,
2053 .priv = dev,
3b6592f7 2054 };
21cc2f3f 2055 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2056
2057 /*
21cc2f3f
JX		 2058 * Poll queues don't need interrupts, but we need at least one I/O queue
2059 * left over for non-polled I/O.
6451fe73 2060 */
21cc2f3f
JX		 2061 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2062 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2063
21cc2f3f
JX		 2064 /*
2065 * Initialize for the single interrupt case, will be updated in
2066 * nvme_calc_irq_sets().
2067 */
612b7286
ML		 2068 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2069 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2070
66341331 2071 /*
21cc2f3f
JX		 2072 * We need interrupts for the admin queue and each non-polled I/O queue,
2073 * but some Apple controllers require all queues to use the first
2074 * vector.
66341331 2075 */
21cc2f3f
JX		 2076 irq_queues = 1;
2077 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2078 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2079 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2080 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2081}
2082
8fae268b
KB		 2083static void nvme_disable_io_queues(struct nvme_dev *dev)
2084{
2085 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2086 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2087}
2088
2a5bcfdd
WZ		 2089static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2090{
2091 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2092}
2093
8d85fce7 2094static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2095{
147b27e4 2096 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2097 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2098 unsigned int nr_io_queues;
97f6ef64 2099 unsigned long size;
2a5bcfdd 2100 int result;
b60503ba 2101
2a5bcfdd
WZ		 2102 /*
2103 * Sample the module parameters once at reset time so that we have
2104 * stable values to work with.
2105 */
2106 dev->nr_write_queues = write_queues;
2107 dev->nr_poll_queues = poll_queues;
d38e9f04
BH		 2108
2109 /*
2110 * If tags are shared with admin queue (Apple bug), then
2111 * make sure we only use one IO queue.
2112 */
2113 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2114 nr_io_queues = 1;
2a5bcfdd
WZ		 2115 else
2116 nr_io_queues = min(nvme_max_io_queues(dev),
2117 dev->nr_allocated_queues - 1);
d38e9f04 2118
9a0be7ab
CH		 2119 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2120 if (result < 0)
1b23484b 2121 return result;
9a0be7ab 2122
f5fa90dc 2123 if (nr_io_queues == 0)
a5229050 2124 return 0;
4e224106
CH		 2125
2126 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2127
0f238ff5 2128 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2129 result = nvme_cmb_qdepth(dev, nr_io_queues,
2130 sizeof(struct nvme_command));
2131 if (result > 0)
2132 dev->q_depth = result;
2133 else
0f238ff5 2134 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2135 }
2136
97f6ef64
XY		 2137 do {
2138 size = db_bar_size(dev, nr_io_queues);
2139 result = nvme_remap_bar(dev, size);
2140 if (!result)
2141 break;
2142 if (!--nr_io_queues)
2143 return -ENOMEM;
2144 } while (1);
2145 adminq->q_db = dev->dbs;
f1938f6e 2146
8fae268b 2147 retry:
9d713c2b 2148 /* Deregister the admin queue's interrupt */
0ff199cb 2149 pci_free_irq(pdev, 0, adminq);
9d713c2b 2150
e32efbfc
JA		 2151 /*
2152 * If we enable msix early due to not intx, disable it again before
2153 * setting up the full range we need.
2154 */
dca51e78 2155 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2156
2157 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2158 if (result <= 0)
dca51e78 2159 return -EIO;
3b6592f7 2160
22b55601 2161 dev->num_vecs = result;
4b04cc6a 2162 result = max(result - 1, 1);
e20ba6e1 2163 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2164
063a8096
MW		 2165 /*
2166 * Should investigate if there's a performance win from allocating
2167 * more queues than interrupt vectors; it might allow the submission
2168 * path to scale better, even if the receive path is limited by the
2169 * number of interrupts.
2170 */
dca51e78 2171 result = queue_request_irq(adminq);
7c349dde 2172 if (result)
d4875622 2173 return result;
4e224106 2174 set_bit(NVMEQ_ENABLED, &adminq->flags);
8fae268b
KB		 2175
2176 result = nvme_create_io_queues(dev);
2177 if (result || dev->online_queues < 2)
2178 return result;
2179
2180 if (dev->online_queues - 1 < dev->max_qid) {
2181 nr_io_queues = dev->online_queues - 1;
2182 nvme_disable_io_queues(dev);
2183 nvme_suspend_io_queues(dev);
2184 goto retry;
2185 }
2186 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2187 dev->io_queues[HCTX_TYPE_DEFAULT],
2188 dev->io_queues[HCTX_TYPE_READ],
2189 dev->io_queues[HCTX_TYPE_POLL]);
2190 return 0;
b60503ba
MW		 2191}
2192
2a842aca 2193static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2194{
db3cbfff 2195 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2196
db3cbfff 2197 blk_mq_free_request(req);
d1ed6aa1 2198 complete(&nvmeq->delete_done);
a5768aa8
KB		 2199}
2200
2a842aca 2201static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2202{
db3cbfff 2203 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2204
d1ed6aa1
CH		 2205 if (error)
2206 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2207
2208 nvme_del_queue_end(req, error);
a5768aa8
KB		 2209}
2210
db3cbfff 2211static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2212{
db3cbfff
KB		 2213 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2214 struct request *req;
2215 struct nvme_command cmd;
bda4e0fb 2216
db3cbfff
KB		 2217 memset(&cmd, 0, sizeof(cmd));
2218 cmd.delete_queue.opcode = opcode;
2219 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2220
eb71f435 2221 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2222 if (IS_ERR(req))
2223 return PTR_ERR(req);
bda4e0fb 2224
db3cbfff
KB		 2225 req->end_io_data = nvmeq;
2226
d1ed6aa1 2227 init_completion(&nvmeq->delete_done);
db3cbfff
KB		 2228 blk_execute_rq_nowait(q, NULL, req, false,
2229 opcode == nvme_admin_delete_cq ?
2230 nvme_del_cq_end : nvme_del_queue_end);
2231 return 0;
bda4e0fb
KB		 2232}
2233
8fae268b 2234static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2235{
5271edd4 2236 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2237 unsigned long timeout;
a5768aa8 2238
db3cbfff 2239 retry:
5271edd4
CH		 2240 timeout = ADMIN_TIMEOUT;
2241 while (nr_queues > 0) {
2242 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2243 break;
2244 nr_queues--;
2245 sent++;
db3cbfff 2246 }
d1ed6aa1
CH		 2247 while (sent) {
2248 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2249
2250 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2251 timeout);
2252 if (timeout == 0)
2253 return false;
d1ed6aa1 2254
d1ed6aa1 2255 sent--;
5271edd4
CH		 2256 if (nr_queues)
2257 goto retry;
2258 }
2259 return true;
a5768aa8
KB		 2260}
2261
5d02a5c1 2262static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2263{
2b1b7e78
JW		 2264 int ret;
2265
5bae7f73 2266 if (!dev->ctrl.tagset) {
376f7ef8 2267 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2268 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2269 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2270 if (dev->io_queues[HCTX_TYPE_POLL])
2271 dev->tagset.nr_maps++;
ffe7704d 2272 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2273 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2274 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2275 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2276 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2277 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2278 dev->tagset.driver_data = dev;
b60503ba 2279
d38e9f04
BH		 2280 /*
2281 * Some Apple controllers requires tags to be unique
2282 * across admin and IO queue, so reserve the first 32
2283 * tags of the IO queue.
2284 */
2285 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2286 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2287
2b1b7e78
JW		 2288 ret = blk_mq_alloc_tag_set(&dev->tagset);
2289 if (ret) {
2290 dev_warn(dev->ctrl.device,
2291 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2292 return;
2b1b7e78 2293 }
5bae7f73 2294 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2295 } else {
2296 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2297
2298 /* Free previously allocated queues that are no longer usable */
2299 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2300 }
949928c1 2301
e8fd41bb 2302 nvme_dbbuf_set(dev);
b60503ba
MW		 2303}
2304
b00a726a 2305static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2306{
b00a726a 2307 int result = -ENOMEM;
e75ec752 2308 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2309
2310 if (pci_enable_device_mem(pdev))
2311 return result;
2312
0877cb0d 2313 pci_set_master(pdev);
0877cb0d 2314
4fe06923 2315 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
052d0efa 2316 goto disable;
0877cb0d 2317
7a67cbea 2318 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2319 result = -ENODEV;
b00a726a 2320 goto disable;
0e53d180 2321 }
e32efbfc
JA		 2322
2323 /*
a5229050
KB		 2324 * Some devices and/or platforms don't advertise or work with INTx
2325 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2326 * adjust this later.
e32efbfc 2327 */
dca51e78
CH		 2328 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2329 if (result < 0)
2330 return result;
e32efbfc 2331
20d0dfe6 2332 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2333
7442ddce 2334 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2335 io_queue_depth);
aa22c8e6 2336 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2337 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2338 dev->dbs = dev->bar + 4096;
1f390c1f 2339
66341331
BH		 2340 /*
2341 * Some Apple controllers require a non-standard SQE size.
2342 * Interestingly they also seem to ignore the CC:IOSQES register
2343 * so we don't bother updating it here.
2344 */
2345 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2346 dev->io_sqes = 7;
2347 else
2348 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2349
2350 /*
2351 * Temporary fix for the Apple controller found in the MacBook8,1 and
2352 * some MacBook7,1 to avoid controller resets and data loss.
2353 */
2354 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2355 dev->q_depth = 2;
9bdcfb10
CH		 2356 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2357 "set queue depth=%u to work around controller resets\n",
1f390c1f 2358 dev->q_depth);
d554b5e1
MP		 2359 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2360 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2361 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2362 dev->q_depth = 64;
2363 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2364 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2365 }
2366
d38e9f04
BH		 2367 /*
2368 * Controllers with the shared tags quirk need the IO queue to be
2369 * big enough so that we get 32 tags for the admin queue
2370 */
2371 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2372 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2373 dev->q_depth = NVME_AQ_DEPTH + 2;
2374 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2375 dev->q_depth);
2376 }
2377
2378
f65efd6d 2379 nvme_map_cmb(dev);
202021c1 2380
a0a3408e
KB		 2381 pci_enable_pcie_error_reporting(pdev);
2382 pci_save_state(pdev);
0877cb0d
KB		 2383 return 0;
2384
2385 disable:
0877cb0d
KB		 2386 pci_disable_device(pdev);
2387 return result;
2388}
2389
2390static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2391{
2392 if (dev->bar)
2393 iounmap(dev->bar);
a1f447b3 2394 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2395}
2396
2397static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2398{
e75ec752
CH		 2399 struct pci_dev *pdev = to_pci_dev(dev->dev);
2400
dca51e78 2401 pci_free_irq_vectors(pdev);
0877cb0d 2402
a0a3408e
KB		 2403 if (pci_is_enabled(pdev)) {
2404 pci_disable_pcie_error_reporting(pdev);
e75ec752 2405 pci_disable_device(pdev);
4d115420 2406 }
4d115420
KB		 2407}
2408
a5cdb68c 2409static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2410{
e43269e6 2411 bool dead = true, freeze = false;
302ad8cc 2412 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2413
77bf25ea 2414 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2415 if (pci_is_enabled(pdev)) {
2416 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2417
ebef7368 2418 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2419 dev->ctrl.state == NVME_CTRL_RESETTING) {
2420 freeze = true;
302ad8cc 2421 nvme_start_freeze(&dev->ctrl);
e43269e6 2422 }
302ad8cc
KB		 2423 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2424 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2425 }
c21377f8 2426
302ad8cc
KB		 2427 /*
2428 * Give the controller a chance to complete all entered requests if
2429 * doing a safe shutdown.
2430 */
e43269e6
KB		 2431 if (!dead && shutdown && freeze)
2432 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2433
2434 nvme_stop_queues(&dev->ctrl);
87ad72a5 2435
64ee0ac0 2436 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2437 nvme_disable_io_queues(dev);
a5cdb68c 2438 nvme_disable_admin_queue(dev, shutdown);
4d115420 2439 }
8fae268b
KB		 2440 nvme_suspend_io_queues(dev);
2441 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2442 nvme_pci_disable(dev);
fa46c6fb 2443 nvme_reap_pending_cqes(dev);
07836e65 2444
e1958e65
ML		 2445 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2446 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2447 blk_mq_tagset_wait_completed_request(&dev->tagset);
2448 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2449
2450 /*
2451 * The driver will not be starting up queues again if shutting down so
2452 * must flush all entered requests to their failed completion to avoid
2453 * deadlocking blk-mq hot-cpu notifier.
2454 */
c8e9e9b7 2455 if (shutdown) {
302ad8cc 2456 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2457 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2458 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2459 }
77bf25ea 2460 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2461}
2462
c1ac9a4b
KB		 2463static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2464{
2465 if (!nvme_wait_reset(&dev->ctrl))
2466 return -EBUSY;
2467 nvme_dev_disable(dev, shutdown);
2468 return 0;
2469}
2470
091b6092
MW		 2471static int nvme_setup_prp_pools(struct nvme_dev *dev)
2472{
e75ec752 2473 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2474 NVME_CTRL_PAGE_SIZE,
2475 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2476 if (!dev->prp_page_pool)
2477 return -ENOMEM;
2478
99802a7a 2479 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2480 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2481 256, 256, 0);
2482 if (!dev->prp_small_pool) {
2483 dma_pool_destroy(dev->prp_page_pool);
2484 return -ENOMEM;
2485 }
091b6092
MW		 2486 return 0;
2487}
2488
2489static void nvme_release_prp_pools(struct nvme_dev *dev)
2490{
2491 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2492 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2493}
2494
770597ec
KB		 2495static void nvme_free_tagset(struct nvme_dev *dev)
2496{
2497 if (dev->tagset.tags)
2498 blk_mq_free_tag_set(&dev->tagset);
2499 dev->ctrl.tagset = NULL;
2500}
2501
1673f1f0 2502static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2503{
1673f1f0 2504 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2505
f9f38e33 2506 nvme_dbbuf_dma_free(dev);
770597ec 2507 nvme_free_tagset(dev);
1c63dc66
CH		 2508 if (dev->ctrl.admin_q)
2509 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2510 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2511 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2512 put_device(dev->dev);
2513 kfree(dev->queues);
5e82e952
KB		 2514 kfree(dev);
2515}
2516
7c1ce408 2517static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2518{
c1ac9a4b
KB		 2519 /*
2520 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2521 * may be holding this pci_dev's device lock.
2522 */
2523 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2524 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2525 nvme_dev_disable(dev, false);
9f9cafc1 2526 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2527 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2528 nvme_put_ctrl(&dev->ctrl);
2529}
2530
fd634f41 2531static void nvme_reset_work(struct work_struct *work)
5e82e952 2532{
d86c4d8e
CH		 2533 struct nvme_dev *dev =
2534 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2535 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2536 int result;
5e82e952 2537
e71afda4
CK		 2538 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2539 result = -ENODEV;
fd634f41 2540 goto out;
e71afda4 2541 }
5e82e952 2542
fd634f41
CH		 2543 /*
2544 * If we're called to reset a live controller first shut it down before
2545 * moving on.
2546 */
b00a726a 2547 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2548 nvme_dev_disable(dev, false);
d6135c3a 2549 nvme_sync_queues(&dev->ctrl);
5e82e952 2550
5c959d73 2551 mutex_lock(&dev->shutdown_lock);
b00a726a 2552 result = nvme_pci_enable(dev);
f0b50732 2553 if (result)
4726bcf3 2554 goto out_unlock;
f0b50732 2555
01ad0990 2556 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2557 if (result)
4726bcf3 2558 goto out_unlock;
f0b50732 2559
0fb59cbc
KB		 2560 result = nvme_alloc_admin_tags(dev);
2561 if (result)
4726bcf3 2562 goto out_unlock;
b9afca3e 2563
943e942e
JA		 2564 /*
2565 * Limit the max command size to prevent iod->sg allocations going
2566 * over a single page.
2567 */
7637de31
CH		 2568 dev->ctrl.max_hw_sectors = min_t(u32,
2569 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2570 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2571
2572 /*
2573 * Don't limit the IOMMU merged segment size.
2574 */
2575 dma_set_max_seg_size(dev->dev, 0xffffffff);
2576
5c959d73
KB		 2577 mutex_unlock(&dev->shutdown_lock);
2578
2579 /*
2580 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2581 * initializing procedure here.
2582 */
2583 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2584 dev_warn(dev->ctrl.device,
2585 "failed to mark controller CONNECTING\n");
cee6c269 2586 result = -EBUSY;
5c959d73
KB		 2587 goto out;
2588 }
943e942e 2589
95093350
MG		 2590 /*
2591 * We do not support an SGL for metadata (yet), so we are limited to a
2592 * single integrity segment for the separate metadata pointer.
2593 */
2594 dev->ctrl.max_integrity_segments = 1;
2595
ce4541f4
CH		 2596 result = nvme_init_identify(&dev->ctrl);
2597 if (result)
f58944e2 2598 goto out;
ce4541f4 2599
e286bcfc
SB		 2600 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2601 if (!dev->ctrl.opal_dev)
2602 dev->ctrl.opal_dev =
2603 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2604 else if (was_suspend)
2605 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2606 } else {
2607 free_opal_dev(dev->ctrl.opal_dev);
2608 dev->ctrl.opal_dev = NULL;
4f1244c8 2609 }
a98e58e5 2610
f9f38e33
HK		 2611 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2612 result = nvme_dbbuf_dma_alloc(dev);
2613 if (result)
2614 dev_warn(dev->dev,
2615 "unable to allocate dma for dbbuf\n");
2616 }
2617
9620cfba
CH		 2618 if (dev->ctrl.hmpre) {
2619 result = nvme_setup_host_mem(dev);
2620 if (result < 0)
2621 goto out;
2622 }
87ad72a5 2623
f0b50732 2624 result = nvme_setup_io_queues(dev);
badc34d4 2625 if (result)
f58944e2 2626 goto out;
f0b50732 2627
2659e57b
CH		 2628 /*
2629 * Keep the controller around but remove all namespaces if we don't have
2630 * any working I/O queue.
2631 */
3cf519b5 2632 if (dev->online_queues < 2) {
1b3c47c1 2633 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2634 nvme_kill_queues(&dev->ctrl);
5bae7f73 2635 nvme_remove_namespaces(&dev->ctrl);
770597ec 2636 nvme_free_tagset(dev);
3cf519b5 2637 } else {
25646264 2638 nvme_start_queues(&dev->ctrl);
302ad8cc 2639 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2640 nvme_dev_add(dev);
302ad8cc 2641 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2642 }
2643
2b1b7e78
JW		 2644 /*
2645 * If only admin queue live, keep it to do further investigation or
2646 * recovery.
2647 */
5d02a5c1 2648 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2649 dev_warn(dev->ctrl.device,
5d02a5c1 2650 "failed to mark controller live state\n");
e71afda4 2651 result = -ENODEV;
bb8d261e
CH		 2652 goto out;
2653 }
92911a55 2654
d09f2b45 2655 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2656 return;
f0b50732 2657
4726bcf3
KB		 2658 out_unlock:
2659 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2660 out:
7c1ce408
CK		 2661 if (result)
2662 dev_warn(dev->ctrl.device,
2663 "Removing after probe failure status: %d\n", result);
2664 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2665}
2666
5c8809e6 2667static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2668{
5c8809e6 2669 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2670 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2671
2672 if (pci_get_drvdata(pdev))
921920ab 2673 device_release_driver(&pdev->dev);
1673f1f0 2674 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2675}
2676
1c63dc66 2677static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2678{
1c63dc66 2679 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2680 return 0;
9ca97374
TH		 2681}
2682
5fd4ce1b 2683static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2684{
5fd4ce1b
CH		 2685 writel(val, to_nvme_dev(ctrl)->bar + off);
2686 return 0;
2687}
4cc06521 2688
7fd8930f
CH		 2689static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2690{
3a8ecc93 2691 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2692 return 0;
4cc06521
KB		 2693}
2694
97c12223
KB		 2695static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2696{
2697 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2698
2db24e4a 2699 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2700}
2701
1c63dc66 2702static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2703 .name = "pcie",
e439bb12 2704 .module = THIS_MODULE,
e0596ab2
LG		 2705 .flags = NVME_F_METADATA_SUPPORTED |
2706 NVME_F_PCI_P2PDMA,
1c63dc66 2707 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2708 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2709 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2710 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2711 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2712 .get_address = nvme_pci_get_address,
1c63dc66 2713};
4cc06521 2714
b00a726a
KB		 2715static int nvme_dev_map(struct nvme_dev *dev)
2716{
b00a726a
KB		 2717 struct pci_dev *pdev = to_pci_dev(dev->dev);
2718
a1f447b3 2719 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2720 return -ENODEV;
2721
97f6ef64 2722 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2723 goto release;
2724
9fa196e7 2725 return 0;
b00a726a 2726 release:
9fa196e7
MG		 2727 pci_release_mem_regions(pdev);
2728 return -ENODEV;
b00a726a
KB		 2729}
2730
8427bbc2 2731static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2732{
2733 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2734 /*
2735 * Several Samsung devices seem to drop off the PCIe bus
2736 * randomly when APST is on and uses the deepest sleep state.
2737 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2738 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2739 * 950 PRO 256GB", but it seems to be restricted to two Dell
2740 * laptops.
2741 */
2742 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2743 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2744 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2745 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2746 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2747 /*
2748 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2749 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2750 * within few minutes after bootup on a Coffee Lake board -
2751 * ASUS PRIME Z370-A
8427bbc2
KHF		 2752 */
2753 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2754 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2755 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2756 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2757 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2758 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2759 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2760 /*
2761 * Forcing to use host managed nvme power settings for
2762 * lowest idle power with quick resume latency on
2763 * Samsung and Toshiba SSDs based on suspend behavior
2764 * on Coffee Lake board for LENOVO C640
2765 */
2766 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2767 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2768 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2769 }
2770
2771 return 0;
2772}
2773
df4f9bc4
DB		 2774#ifdef CONFIG_ACPI
2775static bool nvme_acpi_storage_d3(struct pci_dev *dev)
2776{
2777 struct acpi_device *adev;
2778 struct pci_dev *root;
2779 acpi_handle handle;
2780 acpi_status status;
2781 u8 val;
2782
2783 /*
2784 * Look for _DSD property specifying that the storage device on the port
2785 * must use D3 to support deep platform power savings during
2786 * suspend-to-idle.
2787 */
2788 root = pcie_find_root_port(dev);
2789 if (!root)
2790 return false;
2791
2792 adev = ACPI_COMPANION(&root->dev);
2793 if (!adev)
2794 return false;
2795
2796 /*
2797 * The property is defined in the PXSX device for South complex ports
2798 * and in the PEGP device for North complex ports.
2799 */
2800 status = acpi_get_handle(adev->handle, "PXSX", &handle);
2801 if (ACPI_FAILURE(status)) {
2802 status = acpi_get_handle(adev->handle, "PEGP", &handle);
2803 if (ACPI_FAILURE(status))
2804 return false;
2805 }
2806
2807 if (acpi_bus_get_device(handle, &adev))
2808 return false;
2809
2810 if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable",
2811 &val))
2812 return false;
2813 return val == 1;
2814}
2815#else
2816static inline bool nvme_acpi_storage_d3(struct pci_dev *dev)
2817{
2818 return false;
2819}
2820#endif /* CONFIG_ACPI */
2821
18119775
KB		 2822static void nvme_async_probe(void *data, async_cookie_t cookie)
2823{
2824 struct nvme_dev *dev = data;
80f513b5 2825
bd46a906 2826 flush_work(&dev->ctrl.reset_work);
18119775 2827 flush_work(&dev->ctrl.scan_work);
80f513b5 2828 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2829}
2830
8d85fce7 2831static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2832{
a4aea562 2833 int node, result = -ENOMEM;
b60503ba 2834 struct nvme_dev *dev;
ff5350a8 2835 unsigned long quirks = id->driver_data;
943e942e 2836 size_t alloc_size;
b60503ba 2837
a4aea562
MB		 2838 node = dev_to_node(&pdev->dev);
2839 if (node == NUMA_NO_NODE)
2fa84351 2840 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2841
2842 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2843 if (!dev)
2844 return -ENOMEM;
147b27e4 2845
2a5bcfdd
WZ		 2846 dev->nr_write_queues = write_queues;
2847 dev->nr_poll_queues = poll_queues;
2848 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2849 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2850 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2851 if (!dev->queues)
2852 goto free;
2853
e75ec752 2854 dev->dev = get_device(&pdev->dev);
9a6b9458 2855 pci_set_drvdata(pdev, dev);
1c63dc66 2856
b00a726a
KB		 2857 result = nvme_dev_map(dev);
2858 if (result)
b00c9b7a 2859 goto put_pci;
b00a726a 2860
d86c4d8e 2861 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2862 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2863 mutex_init(&dev->shutdown_lock);
b60503ba 2864
091b6092
MW		 2865 result = nvme_setup_prp_pools(dev);
2866 if (result)
b00c9b7a 2867 goto unmap;
4cc06521 2868
8427bbc2 2869 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2870
df4f9bc4
DB		 2871 if (!noacpi && nvme_acpi_storage_d3(pdev)) {
2872 /*
2873 * Some systems use a bios work around to ask for D3 on
2874 * platforms that support kernel managed suspend.
2875 */
2876 dev_info(&pdev->dev,
2877 "platform quirk: setting simple suspend\n");
2878 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2879 }
2880
943e942e
JA		 2881 /*
2882 * Double check that our mempool alloc size will cover the biggest
2883 * command we support.
2884 */
b13c6393 2885 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 2886 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2887
2888 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2889 mempool_kfree,
2890 (void *) alloc_size,
2891 GFP_KERNEL, node);
2892 if (!dev->iod_mempool) {
2893 result = -ENOMEM;
2894 goto release_pools;
2895 }
2896
b6e44b4c
KB		 2897 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2898 quirks);
2899 if (result)
2900 goto release_mempool;
2901
1b3c47c1
SG		 2902 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2903
bd46a906 2904 nvme_reset_ctrl(&dev->ctrl);
18119775 2905 async_schedule(nvme_async_probe, dev);
4caff8fc 2906
b60503ba
MW		 2907 return 0;
2908
b6e44b4c
KB		 2909 release_mempool:
2910 mempool_destroy(dev->iod_mempool);
0877cb0d 2911 release_pools:
091b6092 2912 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2913 unmap:
2914 nvme_dev_unmap(dev);
a96d4f5c 2915 put_pci:
e75ec752 2916 put_device(dev->dev);
b60503ba
MW		 2917 free:
2918 kfree(dev->queues);
b60503ba
MW		 2919 kfree(dev);
2920 return result;
2921}
2922
775755ed 2923static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2924{
a6739479 2925 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2926
2927 /*
2928 * We don't need to check the return value from waiting for the reset
2929 * state as pci_dev device lock is held, making it impossible to race
2930 * with ->remove().
2931 */
2932 nvme_disable_prepare_reset(dev, false);
2933 nvme_sync_queues(&dev->ctrl);
775755ed 2934}
f0d54a54 2935
775755ed
CH		 2936static void nvme_reset_done(struct pci_dev *pdev)
2937{
f263fbb8 2938 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2939
2940 if (!nvme_try_sched_reset(&dev->ctrl))
2941 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 2942}
2943
09ece142
KB		 2944static void nvme_shutdown(struct pci_dev *pdev)
2945{
2946 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 2947
c1ac9a4b 2948 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 2949}
2950
f58944e2
KB		 2951/*
2952 * The driver's remove may be called on a device in a partially initialized
2953 * state. This function must not have any dependencies on the device state in
2954 * order to proceed.
2955 */
8d85fce7 2956static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2957{
2958 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2959
bb8d261e 2960 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2961 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2962
6db28eda 2963 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2964 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2965 nvme_dev_disable(dev, true);
cb4bfda6 2966 nvme_dev_remove_admin(dev);
6db28eda 2967 }
0ff9d4e1 2968
d86c4d8e 2969 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2970 nvme_stop_ctrl(&dev->ctrl);
2971 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2972 nvme_dev_disable(dev, true);
9fe5c59f 2973 nvme_release_cmb(dev);
87ad72a5 2974 nvme_free_host_mem(dev);
a4aea562 2975 nvme_dev_remove_admin(dev);
a1a5ef99 2976 nvme_free_queues(dev, 0);
9a6b9458 2977 nvme_release_prp_pools(dev);
b00a726a 2978 nvme_dev_unmap(dev);
726612b6 2979 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 2980}
2981
671a6018 2982#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 2983static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2984{
2985 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2986}
2987
2988static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2989{
2990 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2991}
2992
2993static int nvme_resume(struct device *dev)
2994{
2995 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2996 struct nvme_ctrl *ctrl = &ndev->ctrl;
2997
4eaefe8c 2998 if (ndev->last_ps == U32_MAX ||
d916b1be 2999 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 3000 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 3001 return 0;
3002}
3003
cd638946
KB		 3004static int nvme_suspend(struct device *dev)
3005{
3006 struct pci_dev *pdev = to_pci_dev(dev);
3007 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3008 struct nvme_ctrl *ctrl = &ndev->ctrl;
3009 int ret = -EBUSY;
3010
4eaefe8c
RW		 3011 ndev->last_ps = U32_MAX;
3012
d916b1be
KB		 3013 /*
3014 * The platform does not remove power for a kernel managed suspend so
3015 * use host managed nvme power settings for lowest idle power if
3016 * possible. This should have quicker resume latency than a full device
3017 * shutdown. But if the firmware is involved after the suspend or the
3018 * device does not support any non-default power states, shut down the
3019 * device fully.
4eaefe8c
RW		 3020 *
3021 * If ASPM is not enabled for the device, shut down the device and allow
3022 * the PCI bus layer to put it into D3 in order to take the PCIe link
3023 * down, so as to allow the platform to achieve its minimum low-power
3024 * state (which may not be possible if the link is up).
b97120b1
CH		 3025 *
3026 * If a host memory buffer is enabled, shut down the device as the NVMe
3027 * specification allows the device to access the host memory buffer in
3028 * host DRAM from all power states, but hosts will fail access to DRAM
3029 * during S3.
d916b1be 3030 */
4eaefe8c 3031 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3032 !pcie_aspm_enabled(pdev) ||
b97120b1 3033 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 3034 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3035 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3036
3037 nvme_start_freeze(ctrl);
3038 nvme_wait_freeze(ctrl);
3039 nvme_sync_queues(ctrl);
3040
5d02a5c1 3041 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3042 goto unfreeze;
3043
d916b1be
KB		 3044 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3045 if (ret < 0)
3046 goto unfreeze;
3047
7cbb5c6f
ML		 3048 /*
3049 * A saved state prevents pci pm from generically controlling the
3050 * device's power. If we're using protocol specific settings, we don't
3051 * want pci interfering.
3052 */
3053 pci_save_state(pdev);
3054
d916b1be
KB		 3055 ret = nvme_set_power_state(ctrl, ctrl->npss);
3056 if (ret < 0)
3057 goto unfreeze;
3058
3059 if (ret) {
7cbb5c6f
ML		 3060 /* discard the saved state */
3061 pci_load_saved_state(pdev, NULL);
3062
d916b1be
KB		 3063 /*
3064 * Clearing npss forces a controller reset on resume. The
05d3046f 3065 * correct value will be rediscovered then.
d916b1be 3066 */
c1ac9a4b 3067 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3068 ctrl->npss = 0;
d916b1be 3069 }
d916b1be
KB		 3070unfreeze:
3071 nvme_unfreeze(ctrl);
3072 return ret;
3073}
3074
3075static int nvme_simple_suspend(struct device *dev)
3076{
3077 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3078
c1ac9a4b 3079 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3080}
3081
d916b1be 3082static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3083{
3084 struct pci_dev *pdev = to_pci_dev(dev);
3085 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3086
c1ac9a4b 3087 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3088}
3089
21774222 3090static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3091 .suspend = nvme_suspend,
3092 .resume = nvme_resume,
3093 .freeze = nvme_simple_suspend,
3094 .thaw = nvme_simple_resume,
3095 .poweroff = nvme_simple_suspend,
3096 .restore = nvme_simple_resume,
3097};
3098#endif /* CONFIG_PM_SLEEP */
b60503ba 3099
a0a3408e
KB		 3100static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3101 pci_channel_state_t state)
3102{
3103 struct nvme_dev *dev = pci_get_drvdata(pdev);
3104
3105 /*
3106 * A frozen channel requires a reset. When detected, this method will
3107 * shutdown the controller to quiesce. The controller will be restarted
3108 * after the slot reset through driver's slot_reset callback.
3109 */
a0a3408e
KB		 3110 switch (state) {
3111 case pci_channel_io_normal:
3112 return PCI_ERS_RESULT_CAN_RECOVER;
3113 case pci_channel_io_frozen:
d011fb31
KB		 3114 dev_warn(dev->ctrl.device,
3115 "frozen state error detected, reset controller\n");
a5cdb68c 3116 nvme_dev_disable(dev, false);
a0a3408e
KB		 3117 return PCI_ERS_RESULT_NEED_RESET;
3118 case pci_channel_io_perm_failure:
d011fb31
KB		 3119 dev_warn(dev->ctrl.device,
3120 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3121 return PCI_ERS_RESULT_DISCONNECT;
3122 }
3123 return PCI_ERS_RESULT_NEED_RESET;
3124}
3125
3126static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3127{
3128 struct nvme_dev *dev = pci_get_drvdata(pdev);
3129
1b3c47c1 3130 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3131 pci_restore_state(pdev);
d86c4d8e 3132 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3133 return PCI_ERS_RESULT_RECOVERED;
3134}
3135
3136static void nvme_error_resume(struct pci_dev *pdev)
3137{
72cd4cc2
KB		 3138 struct nvme_dev *dev = pci_get_drvdata(pdev);
3139
3140 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3141}
3142
1d352035 3143static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3144 .error_detected = nvme_error_detected,
b60503ba
MW		 3145 .slot_reset = nvme_slot_reset,
3146 .resume = nvme_error_resume,
775755ed
CH		 3147 .reset_prepare = nvme_reset_prepare,
3148 .reset_done = nvme_reset_done,
b60503ba
MW		 3149};
3150
6eb0d698 3151static const struct pci_device_id nvme_id_table[] = {
972b13e2 3152 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3153 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3154 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3155 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3156 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3157 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3158 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3159 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3160 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3161 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3162 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3163 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3164 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3165 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3166 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3167 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3168 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3169 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3170 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3171 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3172 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3173 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3174 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3175 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60
MP		 3176 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3177 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 3178 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3179 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3180 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3181 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3182 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3183 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3184 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3185 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3186 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3187 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 3188 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
3189 .driver_data = NVME_QUIRK_LIGHTNVM, },
3190 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
3191 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 3192 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
3193 .driver_data = NVME_QUIRK_LIGHTNVM, },
08b903b5
MN		 3194 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3195 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3196 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3197 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3198 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3199 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3200 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3201 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3202 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
98f7b86a
AS		 3203 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3204 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3205 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3206 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3207 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3208 NVME_QUIRK_128_BYTES_SQES |
3209 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3210
3211 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3212 { 0, }
3213};
3214MODULE_DEVICE_TABLE(pci, nvme_id_table);
3215
3216static struct pci_driver nvme_driver = {
3217 .name = "nvme",
3218 .id_table = nvme_id_table,
3219 .probe = nvme_probe,
8d85fce7 3220 .remove = nvme_remove,
09ece142 3221 .shutdown = nvme_shutdown,
d916b1be 3222#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3223 .driver = {
3224 .pm = &nvme_dev_pm_ops,
3225 },
d916b1be 3226#endif
74d986ab 3227 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3228 .err_handler = &nvme_err_handler,
3229};
3230
3231static int __init nvme_init(void)
3232{
81101540
CH		 3233 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3234 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3235 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3236 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3237
9a6327d2 3238 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3239}
3240
3241static void __exit nvme_exit(void)
3242{
3243 pci_unregister_driver(&nvme_driver);
03e0f3a6 3244 flush_workqueue(nvme_wq);
b60503ba
MW		 3245}
3246
3247MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3248MODULE_LICENSE("GPL");
c78b4713 3249MODULE_VERSION("1.0");
b60503ba
MW		 3250module_init(nvme_init);
3251module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)