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nvme-pci: consolidate code for polling non-dedicated queues
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
a0a3408e 15#include <linux/aer.h>
18119775 16#include <linux/async.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
dca51e78 19#include <linux/blk-mq-pci.h>
ff5350a8 20#include <linux/dmi.h>
b60503ba
MW		 21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
b60503ba
MW		 24#include <linux/mm.h>
25#include <linux/module.h>
77bf25ea 26#include <linux/mutex.h>
d0877473 27#include <linux/once.h>
b60503ba 28#include <linux/pci.h>
e1e5e564 29#include <linux/t10-pi.h>
b60503ba 30#include <linux/types.h>
2f8e2c87 31#include <linux/io-64-nonatomic-lo-hi.h>
a98e58e5 32#include <linux/sed-opal.h>
0f238ff5 33#include <linux/pci-p2pdma.h>
797a796a 34
f11bb3e2
CH		 35#include "nvme.h"
36
b60503ba
MW		 37#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
38#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
c965809c 39
a7a7cbe3 40#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 41
943e942e
JA		 42/*
43 * These can be higher, but we need to ensure that any command doesn't
44 * require an sg allocation that needs more than a page of data.
45 */
46#define NVME_MAX_KB_SZ 4096
47#define NVME_MAX_SEGS 127
48
58ffacb5
MW		 49static int use_threaded_interrupts;
50module_param(use_threaded_interrupts, int, 0);
51
8ffaadf7 52static bool use_cmb_sqes = true;
69f4eb9f 53module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 54MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
55
87ad72a5
CH		 56static unsigned int max_host_mem_size_mb = 128;
57module_param(max_host_mem_size_mb, uint, 0444);
58MODULE_PARM_DESC(max_host_mem_size_mb,
59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 60
a7a7cbe3
CK		 61static unsigned int sgl_threshold = SZ_32K;
62module_param(sgl_threshold, uint, 0644);
63MODULE_PARM_DESC(sgl_threshold,
64 "Use SGLs when average request segment size is larger or equal to "
65 "this size. Use 0 to disable SGLs.");
66
b27c1e68 67static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68static const struct kernel_param_ops io_queue_depth_ops = {
69 .set = io_queue_depth_set,
70 .get = param_get_int,
71};
72
73static int io_queue_depth = 1024;
74module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
76
3b6592f7
JA		 77static int queue_count_set(const char *val, const struct kernel_param *kp);
78static const struct kernel_param_ops queue_count_ops = {
79 .set = queue_count_set,
80 .get = param_get_int,
81};
82
83static int write_queues;
84module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644);
85MODULE_PARM_DESC(write_queues,
86 "Number of queues to use for writes. If not set, reads and writes "
87 "will share a queue set.");
88
a4668d9b 89static int poll_queues = 0;
4b04cc6a
JA		 90module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644);
91MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
92
1c63dc66
CH		 93struct nvme_dev;
94struct nvme_queue;
b3fffdef 95
a5cdb68c 96static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
d4b4ff8e 97
1c63dc66
CH		 98/*
99 * Represents an NVM Express device. Each nvme_dev is a PCI function.
100 */
101struct nvme_dev {
147b27e4 102 struct nvme_queue *queues;
1c63dc66
CH		 103 struct blk_mq_tag_set tagset;
104 struct blk_mq_tag_set admin_tagset;
105 u32 __iomem *dbs;
106 struct device *dev;
107 struct dma_pool *prp_page_pool;
108 struct dma_pool *prp_small_pool;
1c63dc66
CH		 109 unsigned online_queues;
110 unsigned max_qid;
e20ba6e1 111 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 112 unsigned int num_vecs;
1c63dc66
CH		 113 int q_depth;
114 u32 db_stride;
1c63dc66 115 void __iomem *bar;
97f6ef64 116 unsigned long bar_mapped_size;
5c8809e6 117 struct work_struct remove_work;
77bf25ea 118 struct mutex shutdown_lock;
1c63dc66 119 bool subsystem;
1c63dc66 120 u64 cmb_size;
0f238ff5 121 bool cmb_use_sqes;
1c63dc66 122 u32 cmbsz;
202021c1 123 u32 cmbloc;
1c63dc66 124 struct nvme_ctrl ctrl;
db3cbfff 125 struct completion ioq_wait;
87ad72a5 126
943e942e
JA		 127 mempool_t *iod_mempool;
128
87ad72a5 129 /* shadow doorbell buffer support: */
f9f38e33
HK		 130 u32 *dbbuf_dbs;
131 dma_addr_t dbbuf_dbs_dma_addr;
132 u32 *dbbuf_eis;
133 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 134
135 /* host memory buffer support: */
136 u64 host_mem_size;
137 u32 nr_host_mem_descs;
4033f35d 138 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 139 struct nvme_host_mem_buf_desc *host_mem_descs;
140 void **host_mem_desc_bufs;
4d115420 141};
1fa6aead 142
b27c1e68 143static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
144{
145 int n = 0, ret;
146
147 ret = kstrtoint(val, 10, &n);
148 if (ret != 0 || n < 2)
149 return -EINVAL;
150
151 return param_set_int(val, kp);
152}
153
3b6592f7
JA		 154static int queue_count_set(const char *val, const struct kernel_param *kp)
155{
156 int n = 0, ret;
157
158 ret = kstrtoint(val, 10, &n);
159 if (n > num_possible_cpus())
160 n = num_possible_cpus();
161
162 return param_set_int(val, kp);
163}
164
f9f38e33
HK		 165static inline unsigned int sq_idx(unsigned int qid, u32 stride)
166{
167 return qid * 2 * stride;
168}
169
170static inline unsigned int cq_idx(unsigned int qid, u32 stride)
171{
172 return (qid * 2 + 1) * stride;
173}
174
1c63dc66
CH		 175static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
176{
177 return container_of(ctrl, struct nvme_dev, ctrl);
178}
179
b60503ba
MW		 180/*
181 * An NVM Express queue. Each device has at least two (one for admin
182 * commands and one for I/O commands).
183 */
184struct nvme_queue {
185 struct device *q_dmadev;
091b6092 186 struct nvme_dev *dev;
1ab0cd69 187 spinlock_t sq_lock;
b60503ba 188 struct nvme_command *sq_cmds;
1ab0cd69 189 spinlock_t cq_lock ____cacheline_aligned_in_smp;
b60503ba 190 volatile struct nvme_completion *cqes;
42483228 191 struct blk_mq_tags **tags;
b60503ba
MW		 192 dma_addr_t sq_dma_addr;
193 dma_addr_t cq_dma_addr;
b60503ba
MW		 194 u32 __iomem *q_db;
195 u16 q_depth;
6222d172 196 s16 cq_vector;
b60503ba 197 u16 sq_tail;
04f3eafd 198 u16 last_sq_tail;
b60503ba 199 u16 cq_head;
68fa9dbe 200 u16 last_cq_head;
c30341dc 201 u16 qid;
e9539f47 202 u8 cq_phase;
4e224106
CH		 203 unsigned long flags;
204#define NVMEQ_ENABLED 0
63223078 205#define NVMEQ_SQ_CMB 1
f9f38e33
HK		 206 u32 *dbbuf_sq_db;
207 u32 *dbbuf_cq_db;
208 u32 *dbbuf_sq_ei;
209 u32 *dbbuf_cq_ei;
b60503ba
MW		 210};
211
71bd150c
CH		 212/*
213 * The nvme_iod describes the data in an I/O, including the list of PRP
214 * entries. You can't see it in this data structure because C doesn't let
f4800d6d 215 * me express that. Use nvme_init_iod to ensure there's enough space
71bd150c
CH		 216 * allocated to store the PRP list.
217 */
218struct nvme_iod {
d49187e9 219 struct nvme_request req;
f4800d6d 220 struct nvme_queue *nvmeq;
a7a7cbe3 221 bool use_sgl;
f4800d6d 222 int aborted;
71bd150c 223 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c
CH		 224 int nents; /* Used in scatterlist */
225 int length; /* Of data, in bytes */
226 dma_addr_t first_dma;
bf684057 227 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
f4800d6d
CH		 228 struct scatterlist *sg;
229 struct scatterlist inline_sg[0];
b60503ba
MW		 230};
231
232/*
233 * Check we didin't inadvertently grow the command struct
234 */
235static inline void _nvme_check_size(void)
236{
237 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
238 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
239 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
240 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
241 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 242 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 243 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba 244 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
0add5e8e
JT		 245 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
246 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
b60503ba 247 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 248 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
f9f38e33
HK		 249 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
250}
251
3b6592f7
JA		 252static unsigned int max_io_queues(void)
253{
4b04cc6a 254 return num_possible_cpus() + write_queues + poll_queues;
3b6592f7
JA		 255}
256
257static unsigned int max_queue_count(void)
258{
259 /* IO queues + admin queue */
260 return 1 + max_io_queues();
261}
262
f9f38e33
HK		 263static inline unsigned int nvme_dbbuf_size(u32 stride)
264{
3b6592f7 265 return (max_queue_count() * 8 * stride);
f9f38e33
HK		 266}
267
268static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
269{
270 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
271
272 if (dev->dbbuf_dbs)
273 return 0;
274
275 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
276 &dev->dbbuf_dbs_dma_addr,
277 GFP_KERNEL);
278 if (!dev->dbbuf_dbs)
279 return -ENOMEM;
280 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
281 &dev->dbbuf_eis_dma_addr,
282 GFP_KERNEL);
283 if (!dev->dbbuf_eis) {
284 dma_free_coherent(dev->dev, mem_size,
285 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
286 dev->dbbuf_dbs = NULL;
287 return -ENOMEM;
288 }
289
290 return 0;
291}
292
293static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
294{
295 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
296
297 if (dev->dbbuf_dbs) {
298 dma_free_coherent(dev->dev, mem_size,
299 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
300 dev->dbbuf_dbs = NULL;
301 }
302 if (dev->dbbuf_eis) {
303 dma_free_coherent(dev->dev, mem_size,
304 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
305 dev->dbbuf_eis = NULL;
306 }
307}
308
309static void nvme_dbbuf_init(struct nvme_dev *dev,
310 struct nvme_queue *nvmeq, int qid)
311{
312 if (!dev->dbbuf_dbs || !qid)
313 return;
314
315 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
316 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
317 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
318 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
319}
320
321static void nvme_dbbuf_set(struct nvme_dev *dev)
322{
323 struct nvme_command c;
324
325 if (!dev->dbbuf_dbs)
326 return;
327
328 memset(&c, 0, sizeof(c));
329 c.dbbuf.opcode = nvme_admin_dbbuf;
330 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
331 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
332
333 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 334 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 335 /* Free memory and continue on */
336 nvme_dbbuf_dma_free(dev);
337 }
338}
339
340static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
341{
342 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
343}
344
345/* Update dbbuf and return true if an MMIO is required */
346static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
347 volatile u32 *dbbuf_ei)
348{
349 if (dbbuf_db) {
350 u16 old_value;
351
352 /*
353 * Ensure that the queue is written before updating
354 * the doorbell in memory
355 */
356 wmb();
357
358 old_value = *dbbuf_db;
359 *dbbuf_db = value;
360
f1ed3df2
MW		 361 /*
362 * Ensure that the doorbell is updated before reading the event
363 * index from memory. The controller needs to provide similar
364 * ordering to ensure the envent index is updated before reading
365 * the doorbell.
366 */
367 mb();
368
f9f38e33
HK		 369 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
370 return false;
371 }
372
373 return true;
b60503ba
MW		 374}
375
ac3dd5bd
JA		 376/*
377 * Max size of iod being embedded in the request payload
378 */
379#define NVME_INT_PAGES 2
5fd4ce1b 380#define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
ac3dd5bd
JA		 381
382/*
383 * Will slightly overestimate the number of pages needed. This is OK
384 * as it only leads to a small amount of wasted memory for the lifetime of
385 * the I/O.
386 */
387static int nvme_npages(unsigned size, struct nvme_dev *dev)
388{
5fd4ce1b
CH		 389 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
390 dev->ctrl.page_size);
ac3dd5bd
JA		 391 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
392}
393
a7a7cbe3
CK		 394/*
395 * Calculates the number of pages needed for the SGL segments. For example a 4k
396 * page can accommodate 256 SGL descriptors.
397 */
398static int nvme_pci_npages_sgl(unsigned int num_seg)
ac3dd5bd 399{
a7a7cbe3 400 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
f4800d6d 401}
ac3dd5bd 402
a7a7cbe3
CK		 403static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
404 unsigned int size, unsigned int nseg, bool use_sgl)
f4800d6d 405{
a7a7cbe3
CK		 406 size_t alloc_size;
407
408 if (use_sgl)
409 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
410 else
411 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
412
413 return alloc_size + sizeof(struct scatterlist) * nseg;
f4800d6d 414}
ac3dd5bd 415
a7a7cbe3 416static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
f4800d6d 417{
a7a7cbe3
CK		 418 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
419 NVME_INT_BYTES(dev), NVME_INT_PAGES,
420 use_sgl);
421
422 return sizeof(struct nvme_iod) + alloc_size;
ac3dd5bd
JA		 423}
424
a4aea562
MB		 425static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
426 unsigned int hctx_idx)
e85248e5 427{
a4aea562 428 struct nvme_dev *dev = data;
147b27e4 429 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 430
42483228
KB		 431 WARN_ON(hctx_idx != 0);
432 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
433 WARN_ON(nvmeq->tags);
434
a4aea562 435 hctx->driver_data = nvmeq;
42483228 436 nvmeq->tags = &dev->admin_tagset.tags[0];
a4aea562 437 return 0;
e85248e5
MW		 438}
439
4af0e21c
KB		 440static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
441{
442 struct nvme_queue *nvmeq = hctx->driver_data;
443
444 nvmeq->tags = NULL;
445}
446
a4aea562
MB		 447static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
448 unsigned int hctx_idx)
b60503ba 449{
a4aea562 450 struct nvme_dev *dev = data;
147b27e4 451 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 452
42483228
KB		 453 if (!nvmeq->tags)
454 nvmeq->tags = &dev->tagset.tags[hctx_idx];
b60503ba 455
42483228 456 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 457 hctx->driver_data = nvmeq;
458 return 0;
b60503ba
MW		 459}
460
d6296d39
CH		 461static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
462 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 463{
d6296d39 464 struct nvme_dev *dev = set->driver_data;
f4800d6d 465 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 466 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 467 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 468
469 BUG_ON(!nvmeq);
f4800d6d 470 iod->nvmeq = nvmeq;
59e29ce6
SG		 471
472 nvme_req(req)->ctrl = &dev->ctrl;
a4aea562
MB		 473 return 0;
474}
475
3b6592f7
JA		 476static int queue_irq_offset(struct nvme_dev *dev)
477{
478 /* if we have more than 1 vec, admin queue offsets us by 1 */
479 if (dev->num_vecs > 1)
480 return 1;
481
482 return 0;
483}
484
dca51e78
CH		 485static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
486{
487 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 488 int i, qoff, offset;
489
490 offset = queue_irq_offset(dev);
491 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
492 struct blk_mq_queue_map *map = &set->map[i];
493
494 map->nr_queues = dev->io_queues[i];
495 if (!map->nr_queues) {
e20ba6e1 496 BUG_ON(i == HCTX_TYPE_DEFAULT);
dca51e78 497
3b6592f7 498 /* shared set, resuse read set parameters */
e20ba6e1 499 map->nr_queues = dev->io_queues[HCTX_TYPE_DEFAULT];
3b6592f7
JA		 500 qoff = 0;
501 offset = queue_irq_offset(dev);
502 }
503
4b04cc6a
JA		 504 /*
505 * The poll queue(s) doesn't have an IRQ (and hence IRQ
506 * affinity), so use the regular blk-mq cpu mapping
507 */
3b6592f7 508 map->queue_offset = qoff;
e20ba6e1 509 if (i != HCTX_TYPE_POLL)
4b04cc6a
JA		 510 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
511 else
512 blk_mq_map_queues(map);
3b6592f7
JA		 513 qoff += map->nr_queues;
514 offset += map->nr_queues;
515 }
516
517 return 0;
dca51e78
CH		 518}
519
04f3eafd
JA		 520/*
521 * Write sq tail if we are asked to, or if the next command would wrap.
522 */
523static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
524{
525 if (!write_sq) {
526 u16 next_tail = nvmeq->sq_tail + 1;
527
528 if (next_tail == nvmeq->q_depth)
529 next_tail = 0;
530 if (next_tail != nvmeq->last_sq_tail)
531 return;
532 }
533
534 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
535 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
536 writel(nvmeq->sq_tail, nvmeq->q_db);
537 nvmeq->last_sq_tail = nvmeq->sq_tail;
538}
539
b60503ba 540/**
90ea5ca4 541 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 542 * @nvmeq: The queue to use
543 * @cmd: The command to send
04f3eafd 544 * @write_sq: whether to write to the SQ doorbell
b60503ba 545 */
04f3eafd
JA		 546static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
547 bool write_sq)
b60503ba 548{
90ea5ca4 549 spin_lock(&nvmeq->sq_lock);
0f238ff5 550 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
90ea5ca4
CH		 551 if (++nvmeq->sq_tail == nvmeq->q_depth)
552 nvmeq->sq_tail = 0;
04f3eafd
JA		 553 nvme_write_sq_db(nvmeq, write_sq);
554 spin_unlock(&nvmeq->sq_lock);
555}
556
557static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
558{
559 struct nvme_queue *nvmeq = hctx->driver_data;
560
561 spin_lock(&nvmeq->sq_lock);
562 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
563 nvme_write_sq_db(nvmeq, true);
90ea5ca4 564 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 565}
566
a7a7cbe3 567static void **nvme_pci_iod_list(struct request *req)
b60503ba 568{
f4800d6d 569 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 570 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 571}
572
955b1b5a
MI		 573static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
574{
575 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 576 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 577 unsigned int avg_seg_size;
578
20469a37
KB		 579 if (nseg == 0)
580 return false;
581
582 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a
MI		 583
584 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
585 return false;
586 if (!iod->nvmeq->qid)
587 return false;
588 if (!sgl_threshold || avg_seg_size < sgl_threshold)
589 return false;
590 return true;
591}
592
fc17b653 593static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
ac3dd5bd 594{
f4800d6d 595 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
f9d03f96 596 int nseg = blk_rq_nr_phys_segments(rq);
b131c61d 597 unsigned int size = blk_rq_payload_bytes(rq);
ac3dd5bd 598
955b1b5a
MI		 599 iod->use_sgl = nvme_pci_use_sgls(dev, rq);
600
f4800d6d 601 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
943e942e 602 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
f4800d6d 603 if (!iod->sg)
fc17b653 604 return BLK_STS_RESOURCE;
f4800d6d
CH		 605 } else {
606 iod->sg = iod->inline_sg;
ac3dd5bd
JA		 607 }
608
f4800d6d
CH		 609 iod->aborted = 0;
610 iod->npages = -1;
611 iod->nents = 0;
612 iod->length = size;
f80ec966 613
fc17b653 614 return BLK_STS_OK;
ac3dd5bd
JA		 615}
616
f4800d6d 617static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
b60503ba 618{
f4800d6d 619 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 620 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
621 dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
622
eca18b23 623 int i;
eca18b23
MW		 624
625 if (iod->npages == 0)
a7a7cbe3
CK		 626 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
627 dma_addr);
628
eca18b23 629 for (i = 0; i < iod->npages; i++) {
a7a7cbe3
CK		 630 void *addr = nvme_pci_iod_list(req)[i];
631
632 if (iod->use_sgl) {
633 struct nvme_sgl_desc *sg_list = addr;
634
635 next_dma_addr =
636 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
637 } else {
638 __le64 *prp_list = addr;
639
640 next_dma_addr = le64_to_cpu(prp_list[last_prp]);
641 }
642
643 dma_pool_free(dev->prp_page_pool, addr, dma_addr);
644 dma_addr = next_dma_addr;
eca18b23 645 }
ac3dd5bd 646
f4800d6d 647 if (iod->sg != iod->inline_sg)
943e942e 648 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 649}
650
d0877473
KB		 651static void nvme_print_sgl(struct scatterlist *sgl, int nents)
652{
653 int i;
654 struct scatterlist *sg;
655
656 for_each_sg(sgl, sg, nents, i) {
657 dma_addr_t phys = sg_phys(sg);
658 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
659 "dma_address:%pad dma_length:%d\n",
660 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
661 sg_dma_len(sg));
662 }
663}
664
a7a7cbe3
CK		 665static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
666 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 667{
f4800d6d 668 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 669 struct dma_pool *pool;
b131c61d 670 int length = blk_rq_payload_bytes(req);
eca18b23 671 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 672 int dma_len = sg_dma_len(sg);
673 u64 dma_addr = sg_dma_address(sg);
5fd4ce1b 674 u32 page_size = dev->ctrl.page_size;
f137e0f1 675 int offset = dma_addr & (page_size - 1);
e025344c 676 __le64 *prp_list;
a7a7cbe3 677 void **list = nvme_pci_iod_list(req);
e025344c 678 dma_addr_t prp_dma;
eca18b23 679 int nprps, i;
ff22b54f 680
1d090624 681 length -= (page_size - offset);
5228b328
JS		 682 if (length <= 0) {
683 iod->first_dma = 0;
a7a7cbe3 684 goto done;
5228b328 685 }
ff22b54f 686
1d090624 687 dma_len -= (page_size - offset);
ff22b54f 688 if (dma_len) {
1d090624 689 dma_addr += (page_size - offset);
ff22b54f
MW		 690 } else {
691 sg = sg_next(sg);
692 dma_addr = sg_dma_address(sg);
693 dma_len = sg_dma_len(sg);
694 }
695
1d090624 696 if (length <= page_size) {
edd10d33 697 iod->first_dma = dma_addr;
a7a7cbe3 698 goto done;
e025344c
SMM		 699 }
700
1d090624 701 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 702 if (nprps <= (256 / 8)) {
703 pool = dev->prp_small_pool;
eca18b23 704 iod->npages = 0;
99802a7a
MW		 705 } else {
706 pool = dev->prp_page_pool;
eca18b23 707 iod->npages = 1;
99802a7a
MW		 708 }
709
69d2b571 710 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 711 if (!prp_list) {
edd10d33 712 iod->first_dma = dma_addr;
eca18b23 713 iod->npages = -1;
86eea289 714 return BLK_STS_RESOURCE;
b77954cb 715 }
eca18b23
MW		 716 list[0] = prp_list;
717 iod->first_dma = prp_dma;
e025344c
SMM		 718 i = 0;
719 for (;;) {
1d090624 720 if (i == page_size >> 3) {
e025344c 721 __le64 *old_prp_list = prp_list;
69d2b571 722 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 723 if (!prp_list)
86eea289 724 return BLK_STS_RESOURCE;
eca18b23 725 list[iod->npages++] = prp_list;
7523d834
MW		 726 prp_list[0] = old_prp_list[i - 1];
727 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
728 i = 1;
e025344c
SMM		 729 }
730 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 731 dma_len -= page_size;
732 dma_addr += page_size;
733 length -= page_size;
e025344c
SMM		 734 if (length <= 0)
735 break;
736 if (dma_len > 0)
737 continue;
86eea289
KB		 738 if (unlikely(dma_len < 0))
739 goto bad_sgl;
e025344c
SMM		 740 sg = sg_next(sg);
741 dma_addr = sg_dma_address(sg);
742 dma_len = sg_dma_len(sg);
ff22b54f
MW		 743 }
744
a7a7cbe3
CK		 745done:
746 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
747 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
748
86eea289
KB		 749 return BLK_STS_OK;
750
751 bad_sgl:
d0877473
KB		 752 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
753 "Invalid SGL for payload:%d nents:%d\n",
754 blk_rq_payload_bytes(req), iod->nents);
86eea289 755 return BLK_STS_IOERR;
ff22b54f
MW		 756}
757
a7a7cbe3
CK		 758static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
759 struct scatterlist *sg)
760{
761 sge->addr = cpu_to_le64(sg_dma_address(sg));
762 sge->length = cpu_to_le32(sg_dma_len(sg));
763 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
764}
765
766static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
767 dma_addr_t dma_addr, int entries)
768{
769 sge->addr = cpu_to_le64(dma_addr);
770 if (entries < SGES_PER_PAGE) {
771 sge->length = cpu_to_le32(entries * sizeof(*sge));
772 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
773 } else {
774 sge->length = cpu_to_le32(PAGE_SIZE);
775 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
776 }
777}
778
779static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 780 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 781{
782 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 783 struct dma_pool *pool;
784 struct nvme_sgl_desc *sg_list;
785 struct scatterlist *sg = iod->sg;
a7a7cbe3 786 dma_addr_t sgl_dma;
b0f2853b 787 int i = 0;
a7a7cbe3 788
a7a7cbe3
CK		 789 /* setting the transfer type as SGL */
790 cmd->flags = NVME_CMD_SGL_METABUF;
791
b0f2853b 792 if (entries == 1) {
a7a7cbe3
CK		 793 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
794 return BLK_STS_OK;
795 }
796
797 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
798 pool = dev->prp_small_pool;
799 iod->npages = 0;
800 } else {
801 pool = dev->prp_page_pool;
802 iod->npages = 1;
803 }
804
805 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
806 if (!sg_list) {
807 iod->npages = -1;
808 return BLK_STS_RESOURCE;
809 }
810
811 nvme_pci_iod_list(req)[0] = sg_list;
812 iod->first_dma = sgl_dma;
813
814 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
815
816 do {
817 if (i == SGES_PER_PAGE) {
818 struct nvme_sgl_desc *old_sg_desc = sg_list;
819 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
820
821 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
822 if (!sg_list)
823 return BLK_STS_RESOURCE;
824
825 i = 0;
826 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
827 sg_list[i++] = *link;
828 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
829 }
830
831 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 832 sg = sg_next(sg);
b0f2853b 833 } while (--entries > 0);
a7a7cbe3 834
a7a7cbe3
CK		 835 return BLK_STS_OK;
836}
837
fc17b653 838static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 839 struct nvme_command *cmnd)
d29ec824 840{
f4800d6d 841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ba1ca37e
CH		 842 struct request_queue *q = req->q;
843 enum dma_data_direction dma_dir = rq_data_dir(req) ?
844 DMA_TO_DEVICE : DMA_FROM_DEVICE;
fc17b653 845 blk_status_t ret = BLK_STS_IOERR;
b0f2853b 846 int nr_mapped;
d29ec824 847
f9d03f96 848 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
ba1ca37e
CH		 849 iod->nents = blk_rq_map_sg(q, req, iod->sg);
850 if (!iod->nents)
851 goto out;
d29ec824 852
fc17b653 853 ret = BLK_STS_RESOURCE;
e0596ab2
LG		 854
855 if (is_pci_p2pdma_page(sg_page(iod->sg)))
856 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents,
857 dma_dir);
858 else
859 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
860 dma_dir, DMA_ATTR_NO_WARN);
b0f2853b 861 if (!nr_mapped)
ba1ca37e 862 goto out;
d29ec824 863
955b1b5a 864 if (iod->use_sgl)
b0f2853b 865 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 866 else
867 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
868
86eea289 869 if (ret != BLK_STS_OK)
ba1ca37e 870 goto out_unmap;
0e5e4f0e 871
fc17b653 872 ret = BLK_STS_IOERR;
ba1ca37e
CH		 873 if (blk_integrity_rq(req)) {
874 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
875 goto out_unmap;
0e5e4f0e 876
bf684057
CH		 877 sg_init_table(&iod->meta_sg, 1);
878 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
ba1ca37e 879 goto out_unmap;
0e5e4f0e 880
bf684057 881 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
ba1ca37e 882 goto out_unmap;
00df5cb4 883
bf684057 884 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
3045c0d0
CK		 885 }
886
fc17b653 887 return BLK_STS_OK;
00df5cb4 888
ba1ca37e
CH		 889out_unmap:
890 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
891out:
892 return ret;
00df5cb4
MW		 893}
894
f4800d6d 895static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
b60503ba 896{
f4800d6d 897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
d4f6c3ab
CH		 898 enum dma_data_direction dma_dir = rq_data_dir(req) ?
899 DMA_TO_DEVICE : DMA_FROM_DEVICE;
900
901 if (iod->nents) {
e0596ab2
LG		 902 /* P2PDMA requests do not need to be unmapped */
903 if (!is_pci_p2pdma_page(sg_page(iod->sg)))
904 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
905
f7f1fc36 906 if (blk_integrity_rq(req))
bf684057 907 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
e19b127f 908 }
e1e5e564 909
f9d03f96 910 nvme_cleanup_cmd(req);
f4800d6d 911 nvme_free_iod(dev, req);
d4f6c3ab 912}
b60503ba 913
d29ec824
CH		 914/*
915 * NOTE: ns is NULL when called on the admin queue.
916 */
fc17b653 917static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 918 const struct blk_mq_queue_data *bd)
edd10d33 919{
a4aea562
MB		 920 struct nvme_ns *ns = hctx->queue->queuedata;
921 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 922 struct nvme_dev *dev = nvmeq->dev;
a4aea562 923 struct request *req = bd->rq;
ba1ca37e 924 struct nvme_command cmnd;
ebe6d874 925 blk_status_t ret;
e1e5e564 926
d1f06f4a
JA		 927 /*
928 * We should not need to do this, but we're still using this to
929 * ensure we can drain requests on a dying queue.
930 */
4e224106 931 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 932 return BLK_STS_IOERR;
933
f9d03f96 934 ret = nvme_setup_cmd(ns, req, &cmnd);
fc17b653 935 if (ret)
f4800d6d 936 return ret;
a4aea562 937
b131c61d 938 ret = nvme_init_iod(req, dev);
fc17b653 939 if (ret)
f9d03f96 940 goto out_free_cmd;
a4aea562 941
fc17b653 942 if (blk_rq_nr_phys_segments(req)) {
b131c61d 943 ret = nvme_map_data(dev, req, &cmnd);
fc17b653
CH		 944 if (ret)
945 goto out_cleanup_iod;
946 }
a4aea562 947
aae239e1 948 blk_mq_start_request(req);
04f3eafd 949 nvme_submit_cmd(nvmeq, &cmnd, bd->last);
fc17b653 950 return BLK_STS_OK;
f9d03f96 951out_cleanup_iod:
f4800d6d 952 nvme_free_iod(dev, req);
f9d03f96
CH		 953out_free_cmd:
954 nvme_cleanup_cmd(req);
ba1ca37e 955 return ret;
b60503ba 956}
e1e5e564 957
77f02a7a 958static void nvme_pci_complete_rq(struct request *req)
eee417b0 959{
f4800d6d 960 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 961
77f02a7a
CH		 962 nvme_unmap_data(iod->nvmeq->dev, req);
963 nvme_complete_rq(req);
b60503ba
MW		 964}
965
d783e0bd 966/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 967static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 968{
750dde44
CH		 969 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
970 nvmeq->cq_phase;
d783e0bd
MR		 971}
972
eb281c82 973static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 974{
eb281c82 975 u16 head = nvmeq->cq_head;
adf68f21 976
397c699f
KB		 977 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
978 nvmeq->dbbuf_cq_ei))
979 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 980}
aae239e1 981
5cb525c8 982static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 983{
5cb525c8 984 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
83a12fb7 985 struct request *req;
adf68f21 986
83a12fb7
SG		 987 if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
988 dev_warn(nvmeq->dev->ctrl.device,
989 "invalid id %d completed on queue %d\n",
990 cqe->command_id, le16_to_cpu(cqe->sq_id));
991 return;
b60503ba
MW		 992 }
993
83a12fb7
SG		 994 /*
995 * AEN requests are special as they don't time out and can
996 * survive any kind of queue freeze and often don't respond to
997 * aborts. We don't even bother to allocate a struct request
998 * for them but rather special case them here.
999 */
1000 if (unlikely(nvmeq->qid == 0 &&
38dabe21 1001 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
83a12fb7
SG		 1002 nvme_complete_async_event(&nvmeq->dev->ctrl,
1003 cqe->status, &cqe->result);
a0fa9647 1004 return;
83a12fb7 1005 }
b60503ba 1006
83a12fb7
SG		 1007 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
1008 nvme_end_request(req, cqe->status, cqe->result);
1009}
b60503ba 1010
5cb525c8 1011static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
b60503ba 1012{
5cb525c8
JA		 1013 while (start != end) {
1014 nvme_handle_cqe(nvmeq, start);
1015 if (++start == nvmeq->q_depth)
1016 start = 0;
1017 }
1018}
adf68f21 1019
5cb525c8
JA		 1020static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1021{
1022 if (++nvmeq->cq_head == nvmeq->q_depth) {
1023 nvmeq->cq_head = 0;
1024 nvmeq->cq_phase = !nvmeq->cq_phase;
b60503ba 1025 }
a0fa9647
JA		 1026}
1027
1052b8ac
JA		 1028static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
1029 u16 *end, unsigned int tag)
a0fa9647 1030{
1052b8ac 1031 int found = 0;
b60503ba 1032
5cb525c8 1033 *start = nvmeq->cq_head;
1052b8ac
JA		 1034 while (nvme_cqe_pending(nvmeq)) {
1035 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag)
1036 found++;
5cb525c8 1037 nvme_update_cq_head(nvmeq);
920d13a8 1038 }
5cb525c8 1039 *end = nvmeq->cq_head;
eb281c82 1040
5cb525c8 1041 if (*start != *end)
920d13a8 1042 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1043 return found;
b60503ba
MW		 1044}
1045
1046static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1047{
58ffacb5 1048 struct nvme_queue *nvmeq = data;
68fa9dbe 1049 irqreturn_t ret = IRQ_NONE;
5cb525c8
JA		 1050 u16 start, end;
1051
1ab0cd69 1052 spin_lock(&nvmeq->cq_lock);
68fa9dbe
JA		 1053 if (nvmeq->cq_head != nvmeq->last_cq_head)
1054 ret = IRQ_HANDLED;
5cb525c8 1055 nvme_process_cq(nvmeq, &start, &end, -1);
68fa9dbe 1056 nvmeq->last_cq_head = nvmeq->cq_head;
1ab0cd69 1057 spin_unlock(&nvmeq->cq_lock);
5cb525c8 1058
68fa9dbe
JA		 1059 if (start != end) {
1060 nvme_complete_cqes(nvmeq, start, end);
1061 return IRQ_HANDLED;
1062 }
1063
1064 return ret;
58ffacb5
MW		 1065}
1066
1067static irqreturn_t nvme_irq_check(int irq, void *data)
1068{
1069 struct nvme_queue *nvmeq = data;
750dde44 1070 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1071 return IRQ_WAKE_THREAD;
1072 return IRQ_NONE;
58ffacb5
MW		 1073}
1074
0b2a8a9f
CH		 1075/*
1076 * Poll for completions any queue, including those not dedicated to polling.
1077 * Can be called from any context.
1078 */
1079static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag)
a0fa9647 1080{
0b2a8a9f 1081 unsigned long flags;
5cb525c8 1082 u16 start, end;
1052b8ac 1083 int found;
a0fa9647 1084
0b2a8a9f 1085 spin_lock_irqsave(&nvmeq->cq_lock, flags);
5cb525c8 1086 found = nvme_process_cq(nvmeq, &start, &end, tag);
0b2a8a9f 1087 spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
442e19b7 1088
5cb525c8 1089 nvme_complete_cqes(nvmeq, start, end);
442e19b7 1090 return found;
a0fa9647
JA		 1091}
1092
9743139c 1093static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1094{
1095 struct nvme_queue *nvmeq = hctx->driver_data;
1096 u16 start, end;
1097 bool found;
1098
1099 if (!nvme_cqe_pending(nvmeq))
1100 return 0;
1101
1102 spin_lock(&nvmeq->cq_lock);
9743139c 1103 found = nvme_process_cq(nvmeq, &start, &end, -1);
dabcefab
JA		 1104 spin_unlock(&nvmeq->cq_lock);
1105
1106 nvme_complete_cqes(nvmeq, start, end);
1107 return found;
1108}
1109
ad22c355 1110static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1111{
f866fc42 1112 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1113 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 1114 struct nvme_command c;
b60503ba 1115
a4aea562
MB		 1116 memset(&c, 0, sizeof(c));
1117 c.common.opcode = nvme_admin_async_event;
ad22c355 1118 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1119 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1120}
1121
b60503ba 1122static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1123{
b60503ba
MW		 1124 struct nvme_command c;
1125
1126 memset(&c, 0, sizeof(c));
1127 c.delete_queue.opcode = opcode;
1128 c.delete_queue.qid = cpu_to_le16(id);
1129
1c63dc66 1130 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1131}
1132
b60503ba 1133static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1134 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1135{
b60503ba 1136 struct nvme_command c;
4b04cc6a
JA		 1137 int flags = NVME_QUEUE_PHYS_CONTIG;
1138
1139 if (vector != -1)
1140 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1141
d29ec824 1142 /*
16772ae6 1143 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1144 * is attached to the request.
1145 */
b60503ba
MW		 1146 memset(&c, 0, sizeof(c));
1147 c.create_cq.opcode = nvme_admin_create_cq;
1148 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1149 c.create_cq.cqid = cpu_to_le16(qid);
1150 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1151 c.create_cq.cq_flags = cpu_to_le16(flags);
4b04cc6a
JA		 1152 if (vector != -1)
1153 c.create_cq.irq_vector = cpu_to_le16(vector);
1154 else
1155 c.create_cq.irq_vector = 0;
b60503ba 1156
1c63dc66 1157 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1158}
1159
1160static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1161 struct nvme_queue *nvmeq)
1162{
9abd68ef 1163 struct nvme_ctrl *ctrl = &dev->ctrl;
b60503ba 1164 struct nvme_command c;
81c1cd98 1165 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1166
9abd68ef
JA		 1167 /*
1168 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1169 * set. Since URGENT priority is zeroes, it makes all queues
1170 * URGENT.
1171 */
1172 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1173 flags |= NVME_SQ_PRIO_MEDIUM;
1174
d29ec824 1175 /*
16772ae6 1176 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1177 * is attached to the request.
1178 */
b60503ba
MW		 1179 memset(&c, 0, sizeof(c));
1180 c.create_sq.opcode = nvme_admin_create_sq;
1181 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1182 c.create_sq.sqid = cpu_to_le16(qid);
1183 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1184 c.create_sq.sq_flags = cpu_to_le16(flags);
1185 c.create_sq.cqid = cpu_to_le16(qid);
1186
1c63dc66 1187 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1188}
1189
1190static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1191{
1192 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1193}
1194
1195static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1196{
1197 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1198}
1199
2a842aca 1200static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1201{
f4800d6d
CH		 1202 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1203 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1204
27fa9bc5
CH		 1205 dev_warn(nvmeq->dev->ctrl.device,
1206 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1207 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1208 blk_mq_free_request(req);
bc5fc7e4
MW		 1209}
1210
b2a0eb1a
KB		 1211static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1212{
1213
1214 /* If true, indicates loss of adapter communication, possibly by a
1215 * NVMe Subsystem reset.
1216 */
1217 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1218
ad70062c
JW		 1219 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1220 switch (dev->ctrl.state) {
1221 case NVME_CTRL_RESETTING:
ad6a0a52 1222 case NVME_CTRL_CONNECTING:
b2a0eb1a 1223 return false;
ad70062c
JW		 1224 default:
1225 break;
1226 }
b2a0eb1a
KB		 1227
1228 /* We shouldn't reset unless the controller is on fatal error state
1229 * _or_ if we lost the communication with it.
1230 */
1231 if (!(csts & NVME_CSTS_CFS) && !nssro)
1232 return false;
1233
b2a0eb1a
KB		 1234 return true;
1235}
1236
1237static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1238{
1239 /* Read a config register to help see what died. */
1240 u16 pci_status;
1241 int result;
1242
1243 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1244 &pci_status);
1245 if (result == PCIBIOS_SUCCESSFUL)
1246 dev_warn(dev->ctrl.device,
1247 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1248 csts, pci_status);
1249 else
1250 dev_warn(dev->ctrl.device,
1251 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1252 csts, result);
1253}
1254
31c7c7d2 1255static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1256{
f4800d6d
CH		 1257 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1258 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1259 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1260 struct request *abort_req;
a4aea562 1261 struct nvme_command cmd;
b2a0eb1a
KB		 1262 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1263
651438bb
WX		 1264 /* If PCI error recovery process is happening, we cannot reset or
1265 * the recovery mechanism will surely fail.
1266 */
1267 mb();
1268 if (pci_channel_offline(to_pci_dev(dev->dev)))
1269 return BLK_EH_RESET_TIMER;
1270
b2a0eb1a
KB		 1271 /*
1272 * Reset immediately if the controller is failed
1273 */
1274 if (nvme_should_reset(dev, csts)) {
1275 nvme_warn_reset(dev, csts);
1276 nvme_dev_disable(dev, false);
d86c4d8e 1277 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1278 return BLK_EH_DONE;
b2a0eb1a 1279 }
c30341dc 1280
7776db1c
KB		 1281 /*
1282 * Did we miss an interrupt?
1283 */
0b2a8a9f 1284 if (nvme_poll_irqdisable(nvmeq, req->tag)) {
7776db1c
KB		 1285 dev_warn(dev->ctrl.device,
1286 "I/O %d QID %d timeout, completion polled\n",
1287 req->tag, nvmeq->qid);
db8c48e4 1288 return BLK_EH_DONE;
7776db1c
KB		 1289 }
1290
31c7c7d2 1291 /*
fd634f41
CH		 1292 * Shutdown immediately if controller times out while starting. The
1293 * reset work will see the pci device disabled when it gets the forced
1294 * cancellation error. All outstanding requests are completed on
db8c48e4 1295 * shutdown, so we return BLK_EH_DONE.
fd634f41 1296 */
4244140d
KB		 1297 switch (dev->ctrl.state) {
1298 case NVME_CTRL_CONNECTING:
1299 case NVME_CTRL_RESETTING:
b9cac43c 1300 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1301 "I/O %d QID %d timeout, disable controller\n",
1302 req->tag, nvmeq->qid);
a5cdb68c 1303 nvme_dev_disable(dev, false);
27fa9bc5 1304 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1305 return BLK_EH_DONE;
4244140d
KB		 1306 default:
1307 break;
c30341dc
KB		 1308 }
1309
fd634f41
CH		 1310 /*
1311 * Shutdown the controller immediately and schedule a reset if the
1312 * command was already aborted once before and still hasn't been
1313 * returned to the driver, or if this is the admin queue.
31c7c7d2 1314 */
f4800d6d 1315 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1316 dev_warn(dev->ctrl.device,
e1569a16
KB		 1317 "I/O %d QID %d timeout, reset controller\n",
1318 req->tag, nvmeq->qid);
a5cdb68c 1319 nvme_dev_disable(dev, false);
d86c4d8e 1320 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1321
27fa9bc5 1322 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
db8c48e4 1323 return BLK_EH_DONE;
c30341dc 1324 }
c30341dc 1325
e7a2a87d 1326 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1327 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1328 return BLK_EH_RESET_TIMER;
6bf25d16 1329 }
7bf7d778 1330 iod->aborted = 1;
a4aea562 1331
c30341dc
KB		 1332 memset(&cmd, 0, sizeof(cmd));
1333 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1334 cmd.abort.cid = req->tag;
c30341dc 1335 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1336
1b3c47c1
SG		 1337 dev_warn(nvmeq->dev->ctrl.device,
1338 "I/O %d QID %d timeout, aborting\n",
1339 req->tag, nvmeq->qid);
e7a2a87d
CH		 1340
1341 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
eb71f435 1342 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
e7a2a87d
CH		 1343 if (IS_ERR(abort_req)) {
1344 atomic_inc(&dev->ctrl.abort_limit);
1345 return BLK_EH_RESET_TIMER;
1346 }
1347
1348 abort_req->timeout = ADMIN_TIMEOUT;
1349 abort_req->end_io_data = NULL;
1350 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
c30341dc 1351
31c7c7d2
CH		 1352 /*
1353 * The aborted req will be completed on receiving the abort req.
1354 * We enable the timer again. If hit twice, it'll cause a device reset,
1355 * as the device then is in a faulty state.
1356 */
1357 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1358}
1359
a4aea562
MB		 1360static void nvme_free_queue(struct nvme_queue *nvmeq)
1361{
9e866774
MW		 1362 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1363 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1364 if (!nvmeq->sq_cmds)
1365 return;
0f238ff5 1366
63223078
CH		 1367 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1368 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev),
1369 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
1370 } else {
1371 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1372 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1373 }
9e866774
MW		 1374}
1375
a1a5ef99 1376static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1377{
1378 int i;
1379
d858e5f0 1380 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1381 dev->ctrl.queue_count--;
147b27e4 1382 nvme_free_queue(&dev->queues[i]);
121c7ad4 1383 }
22404274
KB		 1384}
1385
4d115420
KB		 1386/**
1387 * nvme_suspend_queue - put queue into suspended state
40581d1a 1388 * @nvmeq: queue to suspend
4d115420
KB		 1389 */
1390static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1391{
4e224106 1392 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1393 return 1;
a09115b2 1394
4e224106 1395 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1396 mb();
a09115b2 1397
4e224106 1398 nvmeq->dev->online_queues--;
1c63dc66 1399 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1400 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
4e224106
CH		 1401 if (nvmeq->cq_vector == -1)
1402 return 0;
1403 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1404 nvmeq->cq_vector = -1;
4d115420
KB		 1405 return 0;
1406}
b60503ba 1407
a5cdb68c 1408static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1409{
147b27e4 1410 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1411
a5cdb68c
KB		 1412 if (shutdown)
1413 nvme_shutdown_ctrl(&dev->ctrl);
1414 else
20d0dfe6 1415 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
07836e65 1416
0b2a8a9f 1417 nvme_poll_irqdisable(nvmeq, -1);
b60503ba
MW		 1418}
1419
8ffaadf7
JD		 1420static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1421 int entry_size)
1422{
1423 int q_depth = dev->q_depth;
5fd4ce1b
CH		 1424 unsigned q_size_aligned = roundup(q_depth * entry_size,
1425 dev->ctrl.page_size);
8ffaadf7
JD		 1426
1427 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1428 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
5fd4ce1b 1429 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
c45f5c99 1430 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1431
1432 /*
1433 * Ensure the reduced q_depth is above some threshold where it
1434 * would be better to map queues in system memory with the
1435 * original depth
1436 */
1437 if (q_depth < 64)
1438 return -ENOMEM;
1439 }
1440
1441 return q_depth;
1442}
1443
1444static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1445 int qid, int depth)
1446{
0f238ff5
LG		 1447 struct pci_dev *pdev = to_pci_dev(dev->dev);
1448
1449 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1450 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
1451 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1452 nvmeq->sq_cmds);
63223078
CH		 1453 if (nvmeq->sq_dma_addr) {
1454 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1455 return 0;
1456 }
0f238ff5 1457 }
8ffaadf7 1458
63223078
CH		 1459 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1460 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1461 if (!nvmeq->sq_cmds)
1462 return -ENOMEM;
8ffaadf7
JD		 1463 return 0;
1464}
1465
a6ff7262 1466static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1467{
147b27e4 1468 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1469
62314e40
KB		 1470 if (dev->ctrl.queue_count > qid)
1471 return 0;
b60503ba 1472
e75ec752 1473 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
4d51abf9 1474 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1475 if (!nvmeq->cqes)
1476 goto free_nvmeq;
b60503ba 1477
8ffaadf7 1478 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
b60503ba
MW		 1479 goto free_cqdma;
1480
e75ec752 1481 nvmeq->q_dmadev = dev->dev;
091b6092 1482 nvmeq->dev = dev;
1ab0cd69
JA		 1483 spin_lock_init(&nvmeq->sq_lock);
1484 spin_lock_init(&nvmeq->cq_lock);
b60503ba 1485 nvmeq->cq_head = 0;
82123460 1486 nvmeq->cq_phase = 1;
b80d5ccc 1487 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1488 nvmeq->q_depth = depth;
c30341dc 1489 nvmeq->qid = qid;
758dd7fd 1490 nvmeq->cq_vector = -1;
d858e5f0 1491 dev->ctrl.queue_count++;
36a7e993 1492
147b27e4 1493 return 0;
b60503ba
MW		 1494
1495 free_cqdma:
e75ec752 1496 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1497 nvmeq->cq_dma_addr);
1498 free_nvmeq:
147b27e4 1499 return -ENOMEM;
b60503ba
MW		 1500}
1501
dca51e78 1502static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1503{
0ff199cb
CH		 1504 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1505 int nr = nvmeq->dev->ctrl.instance;
1506
1507 if (use_threaded_interrupts) {
1508 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1509 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1510 } else {
1511 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1512 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1513 }
3001082c
MW		 1514}
1515
22404274 1516static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1517{
22404274 1518 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1519
1ab0cd69 1520 spin_lock_irq(&nvmeq->cq_lock);
22404274 1521 nvmeq->sq_tail = 0;
04f3eafd 1522 nvmeq->last_sq_tail = 0;
22404274
KB		 1523 nvmeq->cq_head = 0;
1524 nvmeq->cq_phase = 1;
b80d5ccc 1525 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1526 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
f9f38e33 1527 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1528 dev->online_queues++;
1ab0cd69 1529 spin_unlock_irq(&nvmeq->cq_lock);
22404274
KB		 1530}
1531
4b04cc6a 1532static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1533{
1534 struct nvme_dev *dev = nvmeq->dev;
1535 int result;
a8e3e0bb 1536 s16 vector;
3f85d50b 1537
22b55601
KB		 1538 /*
1539 * A queue's vector matches the queue identifier unless the controller
1540 * has only one vector available.
1541 */
4b04cc6a
JA		 1542 if (!polled)
1543 vector = dev->num_vecs == 1 ? 0 : qid;
1544 else
1545 vector = -1;
1546
a8e3e0bb 1547 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1548 if (result)
1549 return result;
b60503ba
MW		 1550
1551 result = adapter_alloc_sq(dev, qid, nvmeq);
1552 if (result < 0)
ded45505
KB		 1553 return result;
1554 else if (result)
b60503ba
MW		 1555 goto release_cq;
1556
a8e3e0bb 1557 nvmeq->cq_vector = vector;
161b8be2 1558 nvme_init_queue(nvmeq, qid);
4b04cc6a
JA		 1559
1560 if (vector != -1) {
1561 result = queue_request_irq(nvmeq);
1562 if (result < 0)
1563 goto release_sq;
1564 }
b60503ba 1565
4e224106 1566 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
22404274 1567 return result;
b60503ba 1568
a8e3e0bb
JW		 1569release_sq:
1570 nvmeq->cq_vector = -1;
f25a2dfc 1571 dev->online_queues--;
b60503ba 1572 adapter_delete_sq(dev, qid);
a8e3e0bb 1573release_cq:
b60503ba 1574 adapter_delete_cq(dev, qid);
22404274 1575 return result;
b60503ba
MW		 1576}
1577
f363b089 1578static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1579 .queue_rq = nvme_queue_rq,
77f02a7a 1580 .complete = nvme_pci_complete_rq,
a4aea562 1581 .init_hctx = nvme_admin_init_hctx,
4af0e21c 1582 .exit_hctx = nvme_admin_exit_hctx,
0350815a 1583 .init_request = nvme_init_request,
a4aea562
MB		 1584 .timeout = nvme_timeout,
1585};
1586
dabcefab
JA		 1587#define NVME_SHARED_MQ_OPS \
1588 .queue_rq = nvme_queue_rq, \
04f3eafd 1589 .commit_rqs = nvme_commit_rqs, \
dabcefab
JA		 1590 .complete = nvme_pci_complete_rq, \
1591 .init_hctx = nvme_init_hctx, \
1592 .init_request = nvme_init_request, \
1593 .map_queues = nvme_pci_map_queues, \
1594 .timeout = nvme_timeout \
1595
f363b089 1596static const struct blk_mq_ops nvme_mq_ops = {
dabcefab 1597 NVME_SHARED_MQ_OPS,
a4aea562
MB		 1598};
1599
c6d962ae 1600static const struct blk_mq_ops nvme_mq_poll_ops = {
dabcefab 1601 NVME_SHARED_MQ_OPS,
c6d962ae 1602 .poll = nvme_poll,
dabcefab
JA		 1603};
1604
ea191d2f
KB		 1605static void nvme_dev_remove_admin(struct nvme_dev *dev)
1606{
1c63dc66 1607 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1608 /*
1609 * If the controller was reset during removal, it's possible
1610 * user requests may be waiting on a stopped queue. Start the
1611 * queue to flush these to completion.
1612 */
c81545f9 1613 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1614 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1615 blk_mq_free_tag_set(&dev->admin_tagset);
1616 }
1617}
1618
a4aea562
MB		 1619static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1620{
1c63dc66 1621 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1622 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1623 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1624
38dabe21 1625 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
a4aea562 1626 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
e75ec752 1627 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
a7a7cbe3 1628 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
d3484991 1629 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1630 dev->admin_tagset.driver_data = dev;
1631
1632 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1633 return -ENOMEM;
34b6c231 1634 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1635
1c63dc66
CH		 1636 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1637 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1638 blk_mq_free_tag_set(&dev->admin_tagset);
1639 return -ENOMEM;
1640 }
1c63dc66 1641 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1642 nvme_dev_remove_admin(dev);
1c63dc66 1643 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1644 return -ENODEV;
1645 }
0fb59cbc 1646 } else
c81545f9 1647 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1648
1649 return 0;
1650}
1651
97f6ef64
XY		 1652static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1653{
1654 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1655}
1656
1657static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1658{
1659 struct pci_dev *pdev = to_pci_dev(dev->dev);
1660
1661 if (size <= dev->bar_mapped_size)
1662 return 0;
1663 if (size > pci_resource_len(pdev, 0))
1664 return -ENOMEM;
1665 if (dev->bar)
1666 iounmap(dev->bar);
1667 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1668 if (!dev->bar) {
1669 dev->bar_mapped_size = 0;
1670 return -ENOMEM;
1671 }
1672 dev->bar_mapped_size = size;
1673 dev->dbs = dev->bar + NVME_REG_DBS;
1674
1675 return 0;
1676}
1677
01ad0990 1678static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1679{
ba47e386 1680 int result;
b60503ba
MW		 1681 u32 aqa;
1682 struct nvme_queue *nvmeq;
1683
97f6ef64
XY		 1684 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1685 if (result < 0)
1686 return result;
1687
8ef2074d 1688 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1689 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1690
7a67cbea
CH		 1691 if (dev->subsystem &&
1692 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1693 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1694
20d0dfe6 1695 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
ba47e386
MW		 1696 if (result < 0)
1697 return result;
b60503ba 1698
a6ff7262 1699 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1700 if (result)
1701 return result;
b60503ba 1702
147b27e4 1703 nvmeq = &dev->queues[0];
b60503ba
MW		 1704 aqa = nvmeq->q_depth - 1;
1705 aqa |= aqa << 16;
1706
7a67cbea
CH		 1707 writel(aqa, dev->bar + NVME_REG_AQA);
1708 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1709 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1710
20d0dfe6 1711 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
025c557a 1712 if (result)
d4875622 1713 return result;
a4aea562 1714
2b25d981 1715 nvmeq->cq_vector = 0;
161b8be2 1716 nvme_init_queue(nvmeq, 0);
dca51e78 1717 result = queue_request_irq(nvmeq);
758dd7fd
JD		 1718 if (result) {
1719 nvmeq->cq_vector = -1;
d4875622 1720 return result;
758dd7fd 1721 }
025c557a 1722
4e224106 1723 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1724 return result;
1725}
1726
749941f2 1727static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1728{
4b04cc6a 1729 unsigned i, max, rw_queues;
749941f2 1730 int ret = 0;
42f61420 1731
d858e5f0 1732 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1733 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1734 ret = -ENOMEM;
42f61420 1735 break;
749941f2
CH		 1736 }
1737 }
42f61420 1738
d858e5f0 1739 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1740 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1741 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1742 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1743 } else {
1744 rw_queues = max;
1745 }
1746
949928c1 1747 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1748 bool polled = i > rw_queues;
1749
1750 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1751 if (ret)
42f61420 1752 break;
27e8166c 1753 }
749941f2
CH		 1754
1755 /*
1756 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1757 * than the desired amount of queues, and even a controller without
1758 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1759 * be useful to upgrade a buggy firmware for example.
1760 */
1761 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1762}
1763
202021c1
SB		 1764static ssize_t nvme_cmb_show(struct device *dev,
1765 struct device_attribute *attr,
1766 char *buf)
1767{
1768 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1769
c965809c 1770 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n",
202021c1
SB		 1771 ndev->cmbloc, ndev->cmbsz);
1772}
1773static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1774
88de4598 1775static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1776{
88de4598
CH		 1777 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1778
1779 return 1ULL << (12 + 4 * szu);
1780}
1781
1782static u32 nvme_cmb_size(struct nvme_dev *dev)
1783{
1784 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1785}
1786
f65efd6d 1787static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1788{
88de4598 1789 u64 size, offset;
8ffaadf7
JD		 1790 resource_size_t bar_size;
1791 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1792 int bar;
8ffaadf7 1793
9fe5c59f
KB		 1794 if (dev->cmb_size)
1795 return;
1796
7a67cbea 1797 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1798 if (!dev->cmbsz)
1799 return;
202021c1 1800 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1801
88de4598
CH		 1802 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1803 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1804 bar = NVME_CMB_BIR(dev->cmbloc);
1805 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1806
1807 if (offset > bar_size)
f65efd6d 1808 return;
8ffaadf7
JD		 1809
1810 /*
1811 * Controllers may support a CMB size larger than their BAR,
1812 * for example, due to being behind a bridge. Reduce the CMB to
1813 * the reported size of the BAR
1814 */
1815 if (size > bar_size - offset)
1816 size = bar_size - offset;
1817
0f238ff5
LG		 1818 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1819 dev_warn(dev->ctrl.device,
1820 "failed to register the CMB\n");
f65efd6d 1821 return;
0f238ff5
LG		 1822 }
1823
8ffaadf7 1824 dev->cmb_size = size;
0f238ff5
LG		 1825 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1826
1827 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1828 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1829 pci_p2pmem_publish(pdev, true);
f65efd6d
CH		 1830
1831 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1832 &dev_attr_cmb.attr, NULL))
1833 dev_warn(dev->ctrl.device,
1834 "failed to add sysfs attribute for CMB\n");
8ffaadf7
JD		 1835}
1836
1837static inline void nvme_release_cmb(struct nvme_dev *dev)
1838{
0f238ff5 1839 if (dev->cmb_size) {
1c78f773
MG		 1840 sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1841 &dev_attr_cmb.attr, NULL);
0f238ff5 1842 dev->cmb_size = 0;
8ffaadf7
JD		 1843 }
1844}
1845
87ad72a5
CH		 1846static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1847{
4033f35d 1848 u64 dma_addr = dev->host_mem_descs_dma;
87ad72a5 1849 struct nvme_command c;
87ad72a5
CH		 1850 int ret;
1851
87ad72a5
CH		 1852 memset(&c, 0, sizeof(c));
1853 c.features.opcode = nvme_admin_set_features;
1854 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1855 c.features.dword11 = cpu_to_le32(bits);
1856 c.features.dword12 = cpu_to_le32(dev->host_mem_size >>
1857 ilog2(dev->ctrl.page_size));
1858 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1859 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1860 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1861
1862 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1863 if (ret) {
1864 dev_warn(dev->ctrl.device,
1865 "failed to set host mem (err %d, flags %#x).\n",
1866 ret, bits);
1867 }
87ad72a5
CH		 1868 return ret;
1869}
1870
1871static void nvme_free_host_mem(struct nvme_dev *dev)
1872{
1873 int i;
1874
1875 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1876 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1877 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1878
1879 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1880 le64_to_cpu(desc->addr));
1881 }
1882
1883 kfree(dev->host_mem_desc_bufs);
1884 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1885 dma_free_coherent(dev->dev,
1886 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1887 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1888 dev->host_mem_descs = NULL;
7e5dd57e 1889 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1890}
1891
92dc6895
CH		 1892static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1893 u32 chunk_size)
9d713c2b 1894{
87ad72a5 1895 struct nvme_host_mem_buf_desc *descs;
92dc6895 1896 u32 max_entries, len;
4033f35d 1897 dma_addr_t descs_dma;
2ee0e4ed 1898 int i = 0;
87ad72a5 1899 void **bufs;
6fbcde66 1900 u64 size, tmp;
87ad72a5 1901
87ad72a5
CH		 1902 tmp = (preferred + chunk_size - 1);
1903 do_div(tmp, chunk_size);
1904 max_entries = tmp;
044a9df1
CH		 1905
1906 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1907 max_entries = dev->ctrl.hmmaxd;
1908
4033f35d
CH		 1909 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
1910 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1911 if (!descs)
1912 goto out;
1913
1914 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1915 if (!bufs)
1916 goto out_free_descs;
1917
244a8fe4 1918 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1919 dma_addr_t dma_addr;
1920
50cdb7c6 1921 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1922 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1923 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1924 if (!bufs[i])
1925 break;
1926
1927 descs[i].addr = cpu_to_le64(dma_addr);
1928 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1929 i++;
1930 }
1931
92dc6895 1932 if (!size)
87ad72a5 1933 goto out_free_bufs;
87ad72a5 1934
87ad72a5
CH		 1935 dev->nr_host_mem_descs = i;
1936 dev->host_mem_size = size;
1937 dev->host_mem_descs = descs;
4033f35d 1938 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1939 dev->host_mem_desc_bufs = bufs;
1940 return 0;
1941
1942out_free_bufs:
1943 while (--i >= 0) {
1944 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1945
1946 dma_free_coherent(dev->dev, size, bufs[i],
1947 le64_to_cpu(descs[i].addr));
1948 }
1949
1950 kfree(bufs);
1951out_free_descs:
4033f35d
CH		 1952 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1953 descs_dma);
87ad72a5 1954out:
87ad72a5
CH		 1955 dev->host_mem_descs = NULL;
1956 return -ENOMEM;
1957}
1958
92dc6895
CH		 1959static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1960{
1961 u32 chunk_size;
1962
1963 /* start big and work our way down */
30f92d62 1964 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
044a9df1 1965 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
92dc6895
CH		 1966 chunk_size /= 2) {
1967 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1968 if (!min || dev->host_mem_size >= min)
1969 return 0;
1970 nvme_free_host_mem(dev);
1971 }
1972 }
1973
1974 return -ENOMEM;
1975}
1976
9620cfba 1977static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 1978{
1979 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1980 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1981 u64 min = (u64)dev->ctrl.hmmin * 4096;
1982 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 1983 int ret;
87ad72a5
CH		 1984
1985 preferred = min(preferred, max);
1986 if (min > max) {
1987 dev_warn(dev->ctrl.device,
1988 "min host memory (%lld MiB) above limit (%d MiB).\n",
1989 min >> ilog2(SZ_1M), max_host_mem_size_mb);
1990 nvme_free_host_mem(dev);
9620cfba 1991 return 0;
87ad72a5
CH		 1992 }
1993
1994 /*
1995 * If we already have a buffer allocated check if we can reuse it.
1996 */
1997 if (dev->host_mem_descs) {
1998 if (dev->host_mem_size >= min)
1999 enable_bits |= NVME_HOST_MEM_RETURN;
2000 else
2001 nvme_free_host_mem(dev);
2002 }
2003
2004 if (!dev->host_mem_descs) {
92dc6895
CH		 2005 if (nvme_alloc_host_mem(dev, min, preferred)) {
2006 dev_warn(dev->ctrl.device,
2007 "failed to allocate host memory buffer.\n");
9620cfba 2008 return 0; /* controller must work without HMB */
92dc6895
CH		 2009 }
2010
2011 dev_info(dev->ctrl.device,
2012 "allocated %lld MiB host memory buffer.\n",
2013 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2014 }
2015
9620cfba
CH		 2016 ret = nvme_set_host_mem(dev, enable_bits);
2017 if (ret)
87ad72a5 2018 nvme_free_host_mem(dev);
9620cfba 2019 return ret;
9d713c2b
KB		 2020}
2021
3b6592f7
JA		 2022static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int nr_io_queues)
2023{
2024 unsigned int this_w_queues = write_queues;
4b04cc6a 2025 unsigned int this_p_queues = poll_queues;
3b6592f7
JA		 2026
2027 /*
2028 * Setup read/write queue split
2029 */
2030 if (nr_io_queues == 1) {
e20ba6e1
CH		 2031 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2032 dev->io_queues[HCTX_TYPE_READ] = 0;
2033 dev->io_queues[HCTX_TYPE_POLL] = 0;
3b6592f7
JA		 2034 return;
2035 }
2036
4b04cc6a
JA		 2037 /*
2038 * Configure number of poll queues, if set
2039 */
2040 if (this_p_queues) {
2041 /*
2042 * We need at least one queue left. With just one queue, we'll
2043 * have a single shared read/write set.
2044 */
2045 if (this_p_queues >= nr_io_queues) {
2046 this_w_queues = 0;
2047 this_p_queues = nr_io_queues - 1;
2048 }
2049
e20ba6e1 2050 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
4b04cc6a
JA		 2051 nr_io_queues -= this_p_queues;
2052 } else
e20ba6e1 2053 dev->io_queues[HCTX_TYPE_POLL] = 0;
4b04cc6a 2054
3b6592f7
JA		 2055 /*
2056 * If 'write_queues' is set, ensure it leaves room for at least
2057 * one read queue
2058 */
2059 if (this_w_queues >= nr_io_queues)
2060 this_w_queues = nr_io_queues - 1;
2061
2062 /*
2063 * If 'write_queues' is set to zero, reads and writes will share
2064 * a queue set.
2065 */
2066 if (!this_w_queues) {
e20ba6e1
CH		 2067 dev->io_queues[HCTX_TYPE_DEFAULT] = nr_io_queues;
2068 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2069 } else {
e20ba6e1
CH		 2070 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues;
2071 dev->io_queues[HCTX_TYPE_READ] = nr_io_queues - this_w_queues;
3b6592f7
JA		 2072 }
2073}
2074
2075static int nvme_setup_irqs(struct nvme_dev *dev, int nr_io_queues)
2076{
2077 struct pci_dev *pdev = to_pci_dev(dev->dev);
2078 int irq_sets[2];
2079 struct irq_affinity affd = {
2080 .pre_vectors = 1,
2081 .nr_sets = ARRAY_SIZE(irq_sets),
2082 .sets = irq_sets,
2083 };
30e06628 2084 int result = 0;
3b6592f7
JA		 2085
2086 /*
2087 * For irq sets, we have to ask for minvec == maxvec. This passes
2088 * any reduction back to us, so we can adjust our queue counts and
2089 * IRQ vector needs.
2090 */
2091 do {
2092 nvme_calc_io_queues(dev, nr_io_queues);
e20ba6e1
CH		 2093 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT];
2094 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ];
3b6592f7
JA		 2095 if (!irq_sets[1])
2096 affd.nr_sets = 1;
2097
2098 /*
db29eb05
JA		 2099 * If we got a failure and we're down to asking for just
2100 * 1 + 1 queues, just ask for a single vector. We'll share
2101 * that between the single IO queue and the admin queue.
3b6592f7 2102 */
db29eb05 2103 if (!(result < 0 && nr_io_queues == 1))
30e06628 2104 nr_io_queues = irq_sets[0] + irq_sets[1] + 1;
3b6592f7
JA		 2105
2106 result = pci_alloc_irq_vectors_affinity(pdev, nr_io_queues,
2107 nr_io_queues,
2108 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2109
2110 /*
db29eb05
JA		 2111 * Need to reduce our vec counts. If we get ENOSPC, the
2112 * platform should support mulitple vecs, we just need
2113 * to decrease our ask. If we get EINVAL, the platform
2114 * likely does not. Back down to ask for just one vector.
3b6592f7
JA		 2115 */
2116 if (result == -ENOSPC) {
2117 nr_io_queues--;
2118 if (!nr_io_queues)
2119 return result;
2120 continue;
db29eb05
JA		 2121 } else if (result == -EINVAL) {
2122 nr_io_queues = 1;
2123 continue;
3b6592f7
JA		 2124 } else if (result <= 0)
2125 return -EIO;
2126 break;
2127 } while (1);
2128
2129 return result;
2130}
2131
8d85fce7 2132static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2133{
147b27e4 2134 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2135 struct pci_dev *pdev = to_pci_dev(dev->dev);
97f6ef64
XY		 2136 int result, nr_io_queues;
2137 unsigned long size;
b60503ba 2138
3b6592f7 2139 nr_io_queues = max_io_queues();
9a0be7ab
CH		 2140 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2141 if (result < 0)
1b23484b 2142 return result;
9a0be7ab 2143
f5fa90dc 2144 if (nr_io_queues == 0)
a5229050 2145 return 0;
4e224106
CH		 2146
2147 clear_bit(NVMEQ_ENABLED, &adminq->flags);
b60503ba 2148
0f238ff5 2149 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2150 result = nvme_cmb_qdepth(dev, nr_io_queues,
2151 sizeof(struct nvme_command));
2152 if (result > 0)
2153 dev->q_depth = result;
2154 else
0f238ff5 2155 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2156 }
2157
97f6ef64
XY		 2158 do {
2159 size = db_bar_size(dev, nr_io_queues);
2160 result = nvme_remap_bar(dev, size);
2161 if (!result)
2162 break;
2163 if (!--nr_io_queues)
2164 return -ENOMEM;
2165 } while (1);
2166 adminq->q_db = dev->dbs;
f1938f6e 2167
9d713c2b 2168 /* Deregister the admin queue's interrupt */
0ff199cb 2169 pci_free_irq(pdev, 0, adminq);
9d713c2b 2170
e32efbfc
JA		 2171 /*
2172 * If we enable msix early due to not intx, disable it again before
2173 * setting up the full range we need.
2174 */
dca51e78 2175 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2176
2177 result = nvme_setup_irqs(dev, nr_io_queues);
22b55601 2178 if (result <= 0)
dca51e78 2179 return -EIO;
3b6592f7 2180
22b55601 2181 dev->num_vecs = result;
4b04cc6a 2182 result = max(result - 1, 1);
e20ba6e1 2183 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2184
e20ba6e1
CH		 2185 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2186 dev->io_queues[HCTX_TYPE_DEFAULT],
2187 dev->io_queues[HCTX_TYPE_READ],
2188 dev->io_queues[HCTX_TYPE_POLL]);
3b6592f7 2189
063a8096
MW		 2190 /*
2191 * Should investigate if there's a performance win from allocating
2192 * more queues than interrupt vectors; it might allow the submission
2193 * path to scale better, even if the receive path is limited by the
2194 * number of interrupts.
2195 */
063a8096 2196
dca51e78 2197 result = queue_request_irq(adminq);
758dd7fd
JD		 2198 if (result) {
2199 adminq->cq_vector = -1;
d4875622 2200 return result;
758dd7fd 2201 }
4e224106 2202 set_bit(NVMEQ_ENABLED, &adminq->flags);
749941f2 2203 return nvme_create_io_queues(dev);
b60503ba
MW		 2204}
2205
2a842aca 2206static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2207{
db3cbfff 2208 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2209
db3cbfff
KB		 2210 blk_mq_free_request(req);
2211 complete(&nvmeq->dev->ioq_wait);
a5768aa8
KB		 2212}
2213
2a842aca 2214static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2215{
db3cbfff 2216 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2217
0b2a8a9f
CH		 2218 if (!error)
2219 nvme_poll_irqdisable(nvmeq, -1);
db3cbfff
KB		 2220
2221 nvme_del_queue_end(req, error);
a5768aa8
KB		 2222}
2223
db3cbfff 2224static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2225{
db3cbfff
KB		 2226 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2227 struct request *req;
2228 struct nvme_command cmd;
bda4e0fb 2229
db3cbfff
KB		 2230 memset(&cmd, 0, sizeof(cmd));
2231 cmd.delete_queue.opcode = opcode;
2232 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2233
eb71f435 2234 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
db3cbfff
KB		 2235 if (IS_ERR(req))
2236 return PTR_ERR(req);
bda4e0fb 2237
db3cbfff
KB		 2238 req->timeout = ADMIN_TIMEOUT;
2239 req->end_io_data = nvmeq;
2240
2241 blk_execute_rq_nowait(q, NULL, req, false,
2242 opcode == nvme_admin_delete_cq ?
2243 nvme_del_cq_end : nvme_del_queue_end);
2244 return 0;
bda4e0fb
KB		 2245}
2246
ee9aebb2 2247static void nvme_disable_io_queues(struct nvme_dev *dev)
a5768aa8 2248{
ee9aebb2 2249 int pass, queues = dev->online_queues - 1;
db3cbfff
KB		 2250 unsigned long timeout;
2251 u8 opcode = nvme_admin_delete_sq;
a5768aa8 2252
db3cbfff 2253 for (pass = 0; pass < 2; pass++) {
014a0d60 2254 int sent = 0, i = queues;
db3cbfff
KB		 2255
2256 reinit_completion(&dev->ioq_wait);
2257 retry:
2258 timeout = ADMIN_TIMEOUT;
c21377f8 2259 for (; i > 0; i--, sent++)
147b27e4 2260 if (nvme_delete_queue(&dev->queues[i], opcode))
db3cbfff 2261 break;
c21377f8 2262
db3cbfff
KB		 2263 while (sent--) {
2264 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2265 if (timeout == 0)
2266 return;
2267 if (i)
2268 goto retry;
2269 }
2270 opcode = nvme_admin_delete_cq;
2271 }
a5768aa8
KB		 2272}
2273
422ef0c7 2274/*
2b1b7e78 2275 * return error value only when tagset allocation failed
422ef0c7 2276 */
8d85fce7 2277static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2278{
2b1b7e78
JW		 2279 int ret;
2280
5bae7f73 2281 if (!dev->ctrl.tagset) {
c6d962ae
CH		 2282 if (dev->io_queues[HCTX_TYPE_POLL])
2283 dev->tagset.ops = &nvme_mq_poll_ops;
dabcefab 2284 else
c6d962ae 2285 dev->tagset.ops = &nvme_mq_ops;
dabcefab 2286
ffe7704d 2287 dev->tagset.nr_hw_queues = dev->online_queues - 1;
e20ba6e1 2288 dev->tagset.nr_maps = HCTX_MAX_TYPES;
ffe7704d
KB		 2289 dev->tagset.timeout = NVME_IO_TIMEOUT;
2290 dev->tagset.numa_node = dev_to_node(dev->dev);
2291 dev->tagset.queue_depth =
a4aea562 2292 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
a7a7cbe3
CK		 2293 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2294 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2295 dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2296 nvme_pci_cmd_size(dev, true));
2297 }
ffe7704d
KB		 2298 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2299 dev->tagset.driver_data = dev;
b60503ba 2300
2b1b7e78
JW		 2301 ret = blk_mq_alloc_tag_set(&dev->tagset);
2302 if (ret) {
2303 dev_warn(dev->ctrl.device,
2304 "IO queues tagset allocation failed %d\n", ret);
2305 return ret;
2306 }
5bae7f73 2307 dev->ctrl.tagset = &dev->tagset;
f9f38e33
HK		 2308
2309 nvme_dbbuf_set(dev);
949928c1
KB		 2310 } else {
2311 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2312
2313 /* Free previously allocated queues that are no longer usable */
2314 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2315 }
949928c1 2316
e1e5e564 2317 return 0;
b60503ba
MW		 2318}
2319
b00a726a 2320static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2321{
b00a726a 2322 int result = -ENOMEM;
e75ec752 2323 struct pci_dev *pdev = to_pci_dev(dev->dev);
0877cb0d
KB		 2324
2325 if (pci_enable_device_mem(pdev))
2326 return result;
2327
0877cb0d 2328 pci_set_master(pdev);
0877cb0d 2329
e75ec752
CH		 2330 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2331 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
052d0efa 2332 goto disable;
0877cb0d 2333
7a67cbea 2334 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2335 result = -ENODEV;
b00a726a 2336 goto disable;
0e53d180 2337 }
e32efbfc
JA		 2338
2339 /*
a5229050
KB		 2340 * Some devices and/or platforms don't advertise or work with INTx
2341 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2342 * adjust this later.
e32efbfc 2343 */
dca51e78
CH		 2344 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2345 if (result < 0)
2346 return result;
e32efbfc 2347
20d0dfe6 2348 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2349
20d0dfe6 2350 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2351 io_queue_depth);
20d0dfe6 2352 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2353 dev->dbs = dev->bar + 4096;
1f390c1f
SG		 2354
2355 /*
2356 * Temporary fix for the Apple controller found in the MacBook8,1 and
2357 * some MacBook7,1 to avoid controller resets and data loss.
2358 */
2359 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2360 dev->q_depth = 2;
9bdcfb10
CH		 2361 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2362 "set queue depth=%u to work around controller resets\n",
1f390c1f 2363 dev->q_depth);
d554b5e1
MP		 2364 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2365 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2366 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2367 dev->q_depth = 64;
2368 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2369 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2370 }
2371
f65efd6d 2372 nvme_map_cmb(dev);
202021c1 2373
a0a3408e
KB		 2374 pci_enable_pcie_error_reporting(pdev);
2375 pci_save_state(pdev);
0877cb0d
KB		 2376 return 0;
2377
2378 disable:
0877cb0d
KB		 2379 pci_disable_device(pdev);
2380 return result;
2381}
2382
2383static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2384{
2385 if (dev->bar)
2386 iounmap(dev->bar);
a1f447b3 2387 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2388}
2389
2390static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2391{
e75ec752
CH		 2392 struct pci_dev *pdev = to_pci_dev(dev->dev);
2393
dca51e78 2394 pci_free_irq_vectors(pdev);
0877cb0d 2395
a0a3408e
KB		 2396 if (pci_is_enabled(pdev)) {
2397 pci_disable_pcie_error_reporting(pdev);
e75ec752 2398 pci_disable_device(pdev);
4d115420 2399 }
4d115420
KB		 2400}
2401
a5cdb68c 2402static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2403{
ee9aebb2 2404 int i;
302ad8cc
KB		 2405 bool dead = true;
2406 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2407
77bf25ea 2408 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2409 if (pci_is_enabled(pdev)) {
2410 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2411
ebef7368
KB		 2412 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2413 dev->ctrl.state == NVME_CTRL_RESETTING)
302ad8cc
KB		 2414 nvme_start_freeze(&dev->ctrl);
2415 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2416 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2417 }
c21377f8 2418
302ad8cc
KB		 2419 /*
2420 * Give the controller a chance to complete all entered requests if
2421 * doing a safe shutdown.
2422 */
87ad72a5
CH		 2423 if (!dead) {
2424 if (shutdown)
2425 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2426 }
2427
2428 nvme_stop_queues(&dev->ctrl);
87ad72a5 2429
64ee0ac0 2430 if (!dead && dev->ctrl.queue_count > 0) {
ee9aebb2 2431 nvme_disable_io_queues(dev);
a5cdb68c 2432 nvme_disable_admin_queue(dev, shutdown);
4d115420 2433 }
ee9aebb2
KB		 2434 for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2435 nvme_suspend_queue(&dev->queues[i]);
2436
b00a726a 2437 nvme_pci_disable(dev);
07836e65 2438
e1958e65
ML		 2439 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2440 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
302ad8cc
KB		 2441
2442 /*
2443 * The driver will not be starting up queues again if shutting down so
2444 * must flush all entered requests to their failed completion to avoid
2445 * deadlocking blk-mq hot-cpu notifier.
2446 */
2447 if (shutdown)
2448 nvme_start_queues(&dev->ctrl);
77bf25ea 2449 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2450}
2451
091b6092
MW		 2452static int nvme_setup_prp_pools(struct nvme_dev *dev)
2453{
e75ec752 2454 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
091b6092
MW		 2455 PAGE_SIZE, PAGE_SIZE, 0);
2456 if (!dev->prp_page_pool)
2457 return -ENOMEM;
2458
99802a7a 2459 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2460 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2461 256, 256, 0);
2462 if (!dev->prp_small_pool) {
2463 dma_pool_destroy(dev->prp_page_pool);
2464 return -ENOMEM;
2465 }
091b6092
MW		 2466 return 0;
2467}
2468
2469static void nvme_release_prp_pools(struct nvme_dev *dev)
2470{
2471 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2472 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2473}
2474
1673f1f0 2475static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2476{
1673f1f0 2477 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2478
f9f38e33 2479 nvme_dbbuf_dma_free(dev);
e75ec752 2480 put_device(dev->dev);
4af0e21c
KB		 2481 if (dev->tagset.tags)
2482 blk_mq_free_tag_set(&dev->tagset);
1c63dc66
CH		 2483 if (dev->ctrl.admin_q)
2484 blk_put_queue(dev->ctrl.admin_q);
5e82e952 2485 kfree(dev->queues);
e286bcfc 2486 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2487 mempool_destroy(dev->iod_mempool);
5e82e952
KB		 2488 kfree(dev);
2489}
2490
f58944e2
KB		 2491static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2492{
237045fc 2493 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
f58944e2 2494
d22524a4 2495 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2496 nvme_dev_disable(dev, false);
9f9cafc1 2497 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2498 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2499 nvme_put_ctrl(&dev->ctrl);
2500}
2501
fd634f41 2502static void nvme_reset_work(struct work_struct *work)
5e82e952 2503{
d86c4d8e
CH		 2504 struct nvme_dev *dev =
2505 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2506 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
f58944e2 2507 int result = -ENODEV;
2b1b7e78 2508 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
5e82e952 2509
82b057ca 2510 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
fd634f41 2511 goto out;
5e82e952 2512
fd634f41
CH		 2513 /*
2514 * If we're called to reset a live controller first shut it down before
2515 * moving on.
2516 */
b00a726a 2517 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2518 nvme_dev_disable(dev, false);
5e82e952 2519
ad70062c 2520 /*
ad6a0a52 2521 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
ad70062c
JW		 2522 * initializing procedure here.
2523 */
ad6a0a52 2524 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
ad70062c 2525 dev_warn(dev->ctrl.device,
ad6a0a52 2526 "failed to mark controller CONNECTING\n");
ad70062c
JW		 2527 goto out;
2528 }
2529
b00a726a 2530 result = nvme_pci_enable(dev);
f0b50732 2531 if (result)
3cf519b5 2532 goto out;
f0b50732 2533
01ad0990 2534 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2535 if (result)
f58944e2 2536 goto out;
f0b50732 2537
0fb59cbc
KB		 2538 result = nvme_alloc_admin_tags(dev);
2539 if (result)
f58944e2 2540 goto out;
b9afca3e 2541
943e942e
JA		 2542 /*
2543 * Limit the max command size to prevent iod->sg allocations going
2544 * over a single page.
2545 */
2546 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2547 dev->ctrl.max_segments = NVME_MAX_SEGS;
2548
ce4541f4
CH		 2549 result = nvme_init_identify(&dev->ctrl);
2550 if (result)
f58944e2 2551 goto out;
ce4541f4 2552
e286bcfc
SB		 2553 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2554 if (!dev->ctrl.opal_dev)
2555 dev->ctrl.opal_dev =
2556 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2557 else if (was_suspend)
2558 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2559 } else {
2560 free_opal_dev(dev->ctrl.opal_dev);
2561 dev->ctrl.opal_dev = NULL;
4f1244c8 2562 }
a98e58e5 2563
f9f38e33
HK		 2564 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2565 result = nvme_dbbuf_dma_alloc(dev);
2566 if (result)
2567 dev_warn(dev->dev,
2568 "unable to allocate dma for dbbuf\n");
2569 }
2570
9620cfba
CH		 2571 if (dev->ctrl.hmpre) {
2572 result = nvme_setup_host_mem(dev);
2573 if (result < 0)
2574 goto out;
2575 }
87ad72a5 2576
f0b50732 2577 result = nvme_setup_io_queues(dev);
badc34d4 2578 if (result)
f58944e2 2579 goto out;
f0b50732 2580
2659e57b
CH		 2581 /*
2582 * Keep the controller around but remove all namespaces if we don't have
2583 * any working I/O queue.
2584 */
3cf519b5 2585 if (dev->online_queues < 2) {
1b3c47c1 2586 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2587 nvme_kill_queues(&dev->ctrl);
5bae7f73 2588 nvme_remove_namespaces(&dev->ctrl);
2b1b7e78 2589 new_state = NVME_CTRL_ADMIN_ONLY;
3cf519b5 2590 } else {
25646264 2591 nvme_start_queues(&dev->ctrl);
302ad8cc 2592 nvme_wait_freeze(&dev->ctrl);
2b1b7e78
JW		 2593 /* hit this only when allocate tagset fails */
2594 if (nvme_dev_add(dev))
2595 new_state = NVME_CTRL_ADMIN_ONLY;
302ad8cc 2596 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2597 }
2598
2b1b7e78
JW		 2599 /*
2600 * If only admin queue live, keep it to do further investigation or
2601 * recovery.
2602 */
2603 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
2604 dev_warn(dev->ctrl.device,
2605 "failed to mark controller state %d\n", new_state);
bb8d261e
CH		 2606 goto out;
2607 }
92911a55 2608
d09f2b45 2609 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2610 return;
f0b50732 2611
3cf519b5 2612 out:
f58944e2 2613 nvme_remove_dead_ctrl(dev, result);
f0b50732
KB		 2614}
2615
5c8809e6 2616static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2617{
5c8809e6 2618 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2619 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2620
2621 if (pci_get_drvdata(pdev))
921920ab 2622 device_release_driver(&pdev->dev);
1673f1f0 2623 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2624}
2625
1c63dc66 2626static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2627{
1c63dc66 2628 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2629 return 0;
9ca97374
TH		 2630}
2631
5fd4ce1b 2632static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2633{
5fd4ce1b
CH		 2634 writel(val, to_nvme_dev(ctrl)->bar + off);
2635 return 0;
2636}
4cc06521 2637
7fd8930f
CH		 2638static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2639{
2640 *val = readq(to_nvme_dev(ctrl)->bar + off);
2641 return 0;
4cc06521
KB		 2642}
2643
97c12223
KB		 2644static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2645{
2646 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2647
2648 return snprintf(buf, size, "%s", dev_name(&pdev->dev));
2649}
2650
1c63dc66 2651static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2652 .name = "pcie",
e439bb12 2653 .module = THIS_MODULE,
e0596ab2
LG		 2654 .flags = NVME_F_METADATA_SUPPORTED |
2655 NVME_F_PCI_P2PDMA,
1c63dc66 2656 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2657 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2658 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2659 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2660 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2661 .get_address = nvme_pci_get_address,
1c63dc66 2662};
4cc06521 2663
b00a726a
KB		 2664static int nvme_dev_map(struct nvme_dev *dev)
2665{
b00a726a
KB		 2666 struct pci_dev *pdev = to_pci_dev(dev->dev);
2667
a1f447b3 2668 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2669 return -ENODEV;
2670
97f6ef64 2671 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2672 goto release;
2673
9fa196e7 2674 return 0;
b00a726a 2675 release:
9fa196e7
MG		 2676 pci_release_mem_regions(pdev);
2677 return -ENODEV;
b00a726a
KB		 2678}
2679
8427bbc2 2680static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2681{
2682 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2683 /*
2684 * Several Samsung devices seem to drop off the PCIe bus
2685 * randomly when APST is on and uses the deepest sleep state.
2686 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2687 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2688 * 950 PRO 256GB", but it seems to be restricted to two Dell
2689 * laptops.
2690 */
2691 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2692 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2693 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2694 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2695 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2696 /*
2697 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2698 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2699 * within few minutes after bootup on a Coffee Lake board -
2700 * ASUS PRIME Z370-A
8427bbc2
KHF		 2701 */
2702 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2703 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2704 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2705 return NVME_QUIRK_NO_APST;
ff5350a8
AL		 2706 }
2707
2708 return 0;
2709}
2710
18119775
KB		 2711static void nvme_async_probe(void *data, async_cookie_t cookie)
2712{
2713 struct nvme_dev *dev = data;
80f513b5 2714
18119775
KB		 2715 nvme_reset_ctrl_sync(&dev->ctrl);
2716 flush_work(&dev->ctrl.scan_work);
80f513b5 2717 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2718}
2719
8d85fce7 2720static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2721{
a4aea562 2722 int node, result = -ENOMEM;
b60503ba 2723 struct nvme_dev *dev;
ff5350a8 2724 unsigned long quirks = id->driver_data;
943e942e 2725 size_t alloc_size;
b60503ba 2726
a4aea562
MB		 2727 node = dev_to_node(&pdev->dev);
2728 if (node == NUMA_NO_NODE)
2fa84351 2729 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2730
2731 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2732 if (!dev)
2733 return -ENOMEM;
147b27e4 2734
3b6592f7
JA		 2735 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2736 GFP_KERNEL, node);
b60503ba
MW		 2737 if (!dev->queues)
2738 goto free;
2739
e75ec752 2740 dev->dev = get_device(&pdev->dev);
9a6b9458 2741 pci_set_drvdata(pdev, dev);
1c63dc66 2742
b00a726a
KB		 2743 result = nvme_dev_map(dev);
2744 if (result)
b00c9b7a 2745 goto put_pci;
b00a726a 2746
d86c4d8e 2747 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2748 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2749 mutex_init(&dev->shutdown_lock);
db3cbfff 2750 init_completion(&dev->ioq_wait);
b60503ba 2751
091b6092
MW		 2752 result = nvme_setup_prp_pools(dev);
2753 if (result)
b00c9b7a 2754 goto unmap;
4cc06521 2755
8427bbc2 2756 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2757
943e942e
JA		 2758 /*
2759 * Double check that our mempool alloc size will cover the biggest
2760 * command we support.
2761 */
2762 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2763 NVME_MAX_SEGS, true);
2764 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2765
2766 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2767 mempool_kfree,
2768 (void *) alloc_size,
2769 GFP_KERNEL, node);
2770 if (!dev->iod_mempool) {
2771 result = -ENOMEM;
2772 goto release_pools;
2773 }
2774
b6e44b4c
KB		 2775 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2776 quirks);
2777 if (result)
2778 goto release_mempool;
2779
1b3c47c1
SG		 2780 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2781
80f513b5 2782 nvme_get_ctrl(&dev->ctrl);
18119775 2783 async_schedule(nvme_async_probe, dev);
4caff8fc 2784
b60503ba
MW		 2785 return 0;
2786
b6e44b4c
KB		 2787 release_mempool:
2788 mempool_destroy(dev->iod_mempool);
0877cb0d 2789 release_pools:
091b6092 2790 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2791 unmap:
2792 nvme_dev_unmap(dev);
a96d4f5c 2793 put_pci:
e75ec752 2794 put_device(dev->dev);
b60503ba
MW		 2795 free:
2796 kfree(dev->queues);
b60503ba
MW		 2797 kfree(dev);
2798 return result;
2799}
2800
775755ed 2801static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2802{
a6739479 2803 struct nvme_dev *dev = pci_get_drvdata(pdev);
f263fbb8 2804 nvme_dev_disable(dev, false);
775755ed 2805}
f0d54a54 2806
775755ed
CH		 2807static void nvme_reset_done(struct pci_dev *pdev)
2808{
f263fbb8 2809 struct nvme_dev *dev = pci_get_drvdata(pdev);
79c48ccf 2810 nvme_reset_ctrl_sync(&dev->ctrl);
f0d54a54
KB		 2811}
2812
09ece142
KB		 2813static void nvme_shutdown(struct pci_dev *pdev)
2814{
2815 struct nvme_dev *dev = pci_get_drvdata(pdev);
a5cdb68c 2816 nvme_dev_disable(dev, true);
09ece142
KB		 2817}
2818
f58944e2
KB		 2819/*
2820 * The driver's remove may be called on a device in a partially initialized
2821 * state. This function must not have any dependencies on the device state in
2822 * order to proceed.
2823 */
8d85fce7 2824static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2825{
2826 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 2827
bb8d261e 2828 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 2829 pci_set_drvdata(pdev, NULL);
0ff9d4e1 2830
6db28eda 2831 if (!pci_device_is_present(pdev)) {
0ff9d4e1 2832 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 2833 nvme_dev_disable(dev, true);
cb4bfda6 2834 nvme_dev_remove_admin(dev);
6db28eda 2835 }
0ff9d4e1 2836
d86c4d8e 2837 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 2838 nvme_stop_ctrl(&dev->ctrl);
2839 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 2840 nvme_dev_disable(dev, true);
9fe5c59f 2841 nvme_release_cmb(dev);
87ad72a5 2842 nvme_free_host_mem(dev);
a4aea562 2843 nvme_dev_remove_admin(dev);
a1a5ef99 2844 nvme_free_queues(dev, 0);
d09f2b45 2845 nvme_uninit_ctrl(&dev->ctrl);
9a6b9458 2846 nvme_release_prp_pools(dev);
b00a726a 2847 nvme_dev_unmap(dev);
1673f1f0 2848 nvme_put_ctrl(&dev->ctrl);
b60503ba
MW		 2849}
2850
671a6018 2851#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2852static int nvme_suspend(struct device *dev)
2853{
2854 struct pci_dev *pdev = to_pci_dev(dev);
2855 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2856
a5cdb68c 2857 nvme_dev_disable(ndev, true);
cd638946
KB		 2858 return 0;
2859}
2860
2861static int nvme_resume(struct device *dev)
2862{
2863 struct pci_dev *pdev = to_pci_dev(dev);
2864 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2865
d86c4d8e 2866 nvme_reset_ctrl(&ndev->ctrl);
9a6b9458 2867 return 0;
cd638946 2868}
671a6018 2869#endif
cd638946
KB		 2870
2871static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2872
a0a3408e
KB		 2873static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2874 pci_channel_state_t state)
2875{
2876 struct nvme_dev *dev = pci_get_drvdata(pdev);
2877
2878 /*
2879 * A frozen channel requires a reset. When detected, this method will
2880 * shutdown the controller to quiesce. The controller will be restarted
2881 * after the slot reset through driver's slot_reset callback.
2882 */
a0a3408e
KB		 2883 switch (state) {
2884 case pci_channel_io_normal:
2885 return PCI_ERS_RESULT_CAN_RECOVER;
2886 case pci_channel_io_frozen:
d011fb31
KB		 2887 dev_warn(dev->ctrl.device,
2888 "frozen state error detected, reset controller\n");
a5cdb68c 2889 nvme_dev_disable(dev, false);
a0a3408e
KB		 2890 return PCI_ERS_RESULT_NEED_RESET;
2891 case pci_channel_io_perm_failure:
d011fb31
KB		 2892 dev_warn(dev->ctrl.device,
2893 "failure state error detected, request disconnect\n");
a0a3408e
KB		 2894 return PCI_ERS_RESULT_DISCONNECT;
2895 }
2896 return PCI_ERS_RESULT_NEED_RESET;
2897}
2898
2899static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2900{
2901 struct nvme_dev *dev = pci_get_drvdata(pdev);
2902
1b3c47c1 2903 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 2904 pci_restore_state(pdev);
d86c4d8e 2905 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 2906 return PCI_ERS_RESULT_RECOVERED;
2907}
2908
2909static void nvme_error_resume(struct pci_dev *pdev)
2910{
72cd4cc2
KB		 2911 struct nvme_dev *dev = pci_get_drvdata(pdev);
2912
2913 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 2914}
2915
1d352035 2916static const struct pci_error_handlers nvme_err_handler = {
b60503ba 2917 .error_detected = nvme_error_detected,
b60503ba
MW		 2918 .slot_reset = nvme_slot_reset,
2919 .resume = nvme_error_resume,
775755ed
CH		 2920 .reset_prepare = nvme_reset_prepare,
2921 .reset_done = nvme_reset_done,
b60503ba
MW		 2922};
2923
6eb0d698 2924static const struct pci_device_id nvme_id_table[] = {
106198ed 2925 { PCI_VDEVICE(INTEL, 0x0953),
08095e70 2926 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2927 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2928 { PCI_VDEVICE(INTEL, 0x0a53),
2929 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2930 NVME_QUIRK_DEALLOCATE_ZEROES, },
99466e70
KB		 2931 { PCI_VDEVICE(INTEL, 0x0a54),
2932 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 2933 NVME_QUIRK_DEALLOCATE_ZEROES, },
f99cb7af
DWF		 2934 { PCI_VDEVICE(INTEL, 0x0a55),
2935 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2936 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 2937 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef
JA		 2938 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
2939 NVME_QUIRK_MEDIUM_PRIO_SQ },
540c801c
KB		 2940 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
2941 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
0302ae60
MP		 2942 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
2943 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
54adc010
GP		 2944 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2945 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 2946 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
2947 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 2948 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2949 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 2950 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2951 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2952 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2953 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
608cc4b1
CH		 2954 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2955 .driver_data = NVME_QUIRK_LIGHTNVM, },
2956 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2957 .driver_data = NVME_QUIRK_LIGHTNVM, },
ea48e877
WX		 2958 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */
2959 .driver_data = NVME_QUIRK_LIGHTNVM, },
b60503ba 2960 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
c74dc780 2961 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
124298bd 2962 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
b60503ba
MW		 2963 { 0, }
2964};
2965MODULE_DEVICE_TABLE(pci, nvme_id_table);
2966
2967static struct pci_driver nvme_driver = {
2968 .name = "nvme",
2969 .id_table = nvme_id_table,
2970 .probe = nvme_probe,
8d85fce7 2971 .remove = nvme_remove,
09ece142 2972 .shutdown = nvme_shutdown,
cd638946
KB		 2973 .driver = {
2974 .pm = &nvme_dev_pm_ops,
2975 },
74d986ab 2976 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 2977 .err_handler = &nvme_err_handler,
2978};
2979
2980static int __init nvme_init(void)
2981{
9a6327d2 2982 return pci_register_driver(&nvme_driver);
b60503ba
MW		 2983}
2984
2985static void __exit nvme_exit(void)
2986{
2987 pci_unregister_driver(&nvme_driver);
03e0f3a6 2988 flush_workqueue(nvme_wq);
21bd78bc 2989 _nvme_check_size();
b60503ba
MW		 2990}
2991
2992MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2993MODULE_LICENSE("GPL");
c78b4713 2994MODULE_VERSION("1.0");
b60503ba
MW		 2995module_init(nvme_init);
2996module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)