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nvme-pci: use attribute group for cmb sysfs
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
ff5350a8 13#include <linux/dmi.h>
b60503ba
MW		 14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
b60503ba
MW		 17#include <linux/mm.h>
18#include <linux/module.h>
77bf25ea 19#include <linux/mutex.h>
d0877473 20#include <linux/once.h>
b60503ba 21#include <linux/pci.h>
d916b1be 22#include <linux/suspend.h>
e1e5e564 23#include <linux/t10-pi.h>
b60503ba 24#include <linux/types.h>
2f8e2c87 25#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 26#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 27#include <linux/sed-opal.h>
0f238ff5 28#include <linux/pci-p2pdma.h>
797a796a 29
604c01d5 30#include "trace.h"
f11bb3e2
CH		 31#include "nvme.h"
32
c1e0cc7e 33#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 34#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 35
a7a7cbe3 36#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 37
943e942e
JA		 38/*
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
41 */
42#define NVME_MAX_KB_SZ 4096
43#define NVME_MAX_SEGS 127
44
58ffacb5
MW		 45static int use_threaded_interrupts;
46module_param(use_threaded_interrupts, int, 0);
47
8ffaadf7 48static bool use_cmb_sqes = true;
69f4eb9f 49module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
51
87ad72a5
CH		 52static unsigned int max_host_mem_size_mb = 128;
53module_param(max_host_mem_size_mb, uint, 0444);
54MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 56
a7a7cbe3
CK		 57static unsigned int sgl_threshold = SZ_32K;
58module_param(sgl_threshold, uint, 0644);
59MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
62
27453b45
SG		 63#define NVME_PCI_MIN_QUEUE_SIZE 2
64#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 65static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
66static const struct kernel_param_ops io_queue_depth_ops = {
67 .set = io_queue_depth_set,
61f3b896 68 .get = param_get_uint,
b27c1e68 69};
70
61f3b896 71static unsigned int io_queue_depth = 1024;
b27c1e68 72module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 73MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 74
9c9e76d5
WZ		 75static int io_queue_count_set(const char *val, const struct kernel_param *kp)
76{
77 unsigned int n;
78 int ret;
79
80 ret = kstrtouint(val, 10, &n);
81 if (ret != 0 || n > num_possible_cpus())
82 return -EINVAL;
83 return param_set_uint(val, kp);
84}
85
86static const struct kernel_param_ops io_queue_count_ops = {
87 .set = io_queue_count_set,
88 .get = param_get_uint,
89};
90
3f68baf7 91static unsigned int write_queues;
9c9e76d5 92module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 93MODULE_PARM_DESC(write_queues,
94 "Number of queues to use for writes. If not set, reads and writes "
95 "will share a queue set.");
96
3f68baf7 97static unsigned int poll_queues;
9c9e76d5 98module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 99MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
100
df4f9bc4
DB		 101static bool noacpi;
102module_param(noacpi, bool, 0444);
103MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
104
1c63dc66
CH		 105struct nvme_dev;
106struct nvme_queue;
b3fffdef 107
a5cdb68c 108static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8fae268b 109static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
d4b4ff8e 110
1c63dc66
CH		 111/*
112 * Represents an NVM Express device. Each nvme_dev is a PCI function.
113 */
114struct nvme_dev {
147b27e4 115 struct nvme_queue *queues;
1c63dc66
CH		 116 struct blk_mq_tag_set tagset;
117 struct blk_mq_tag_set admin_tagset;
118 u32 __iomem *dbs;
119 struct device *dev;
120 struct dma_pool *prp_page_pool;
121 struct dma_pool *prp_small_pool;
1c63dc66
CH		 122 unsigned online_queues;
123 unsigned max_qid;
e20ba6e1 124 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 125 unsigned int num_vecs;
7442ddce 126 u32 q_depth;
c1e0cc7e 127 int io_sqes;
1c63dc66 128 u32 db_stride;
1c63dc66 129 void __iomem *bar;
97f6ef64 130 unsigned long bar_mapped_size;
5c8809e6 131 struct work_struct remove_work;
77bf25ea 132 struct mutex shutdown_lock;
1c63dc66 133 bool subsystem;
1c63dc66 134 u64 cmb_size;
0f238ff5 135 bool cmb_use_sqes;
1c63dc66 136 u32 cmbsz;
202021c1 137 u32 cmbloc;
1c63dc66 138 struct nvme_ctrl ctrl;
d916b1be 139 u32 last_ps;
87ad72a5 140
943e942e
JA		 141 mempool_t *iod_mempool;
142
87ad72a5 143 /* shadow doorbell buffer support: */
f9f38e33
HK		 144 u32 *dbbuf_dbs;
145 dma_addr_t dbbuf_dbs_dma_addr;
146 u32 *dbbuf_eis;
147 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 148
149 /* host memory buffer support: */
150 u64 host_mem_size;
151 u32 nr_host_mem_descs;
4033f35d 152 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 153 struct nvme_host_mem_buf_desc *host_mem_descs;
154 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 155 unsigned int nr_allocated_queues;
156 unsigned int nr_write_queues;
157 unsigned int nr_poll_queues;
0521905e
KB		 158
159 bool attrs_added;
4d115420 160};
1fa6aead 161
b27c1e68 162static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
163{
27453b45
SG		 164 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
165 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 166}
167
f9f38e33
HK		 168static inline unsigned int sq_idx(unsigned int qid, u32 stride)
169{
170 return qid * 2 * stride;
171}
172
173static inline unsigned int cq_idx(unsigned int qid, u32 stride)
174{
175 return (qid * 2 + 1) * stride;
176}
177
1c63dc66
CH		 178static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
179{
180 return container_of(ctrl, struct nvme_dev, ctrl);
181}
182
b60503ba
MW		 183/*
184 * An NVM Express queue. Each device has at least two (one for admin
185 * commands and one for I/O commands).
186 */
187struct nvme_queue {
091b6092 188 struct nvme_dev *dev;
1ab0cd69 189 spinlock_t sq_lock;
c1e0cc7e 190 void *sq_cmds;
3a7afd8e
CH		 191 /* only used for poll queues: */
192 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 193 struct nvme_completion *cqes;
b60503ba
MW		 194 dma_addr_t sq_dma_addr;
195 dma_addr_t cq_dma_addr;
b60503ba 196 u32 __iomem *q_db;
7442ddce 197 u32 q_depth;
7c349dde 198 u16 cq_vector;
b60503ba 199 u16 sq_tail;
38210800 200 u16 last_sq_tail;
b60503ba 201 u16 cq_head;
c30341dc 202 u16 qid;
e9539f47 203 u8 cq_phase;
c1e0cc7e 204 u8 sqes;
4e224106
CH		 205 unsigned long flags;
206#define NVMEQ_ENABLED 0
63223078 207#define NVMEQ_SQ_CMB 1
d1ed6aa1 208#define NVMEQ_DELETE_ERROR 2
7c349dde 209#define NVMEQ_POLLED 3
f9f38e33
HK		 210 u32 *dbbuf_sq_db;
211 u32 *dbbuf_cq_db;
212 u32 *dbbuf_sq_ei;
213 u32 *dbbuf_cq_ei;
d1ed6aa1 214 struct completion delete_done;
b60503ba
MW		 215};
216
71bd150c 217/*
9b048119
CH		 218 * The nvme_iod describes the data in an I/O.
219 *
220 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
221 * to the actual struct scatterlist.
71bd150c
CH		 222 */
223struct nvme_iod {
d49187e9 224 struct nvme_request req;
af7fae85 225 struct nvme_command cmd;
f4800d6d 226 struct nvme_queue *nvmeq;
a7a7cbe3 227 bool use_sgl;
f4800d6d 228 int aborted;
71bd150c 229 int npages; /* In the PRP list. 0 means small pool in use */
71bd150c 230 int nents; /* Used in scatterlist */
71bd150c 231 dma_addr_t first_dma;
dff824b2 232 unsigned int dma_len; /* length of single DMA segment mapping */
783b94bd 233 dma_addr_t meta_dma;
f4800d6d 234 struct scatterlist *sg;
b60503ba
MW		 235};
236
2a5bcfdd 237static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 238{
2a5bcfdd 239 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 240}
241
242static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
243{
2a5bcfdd 244 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 245
246 if (dev->dbbuf_dbs)
247 return 0;
248
249 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
250 &dev->dbbuf_dbs_dma_addr,
251 GFP_KERNEL);
252 if (!dev->dbbuf_dbs)
253 return -ENOMEM;
254 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
255 &dev->dbbuf_eis_dma_addr,
256 GFP_KERNEL);
257 if (!dev->dbbuf_eis) {
258 dma_free_coherent(dev->dev, mem_size,
259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
260 dev->dbbuf_dbs = NULL;
261 return -ENOMEM;
262 }
263
264 return 0;
265}
266
267static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
268{
2a5bcfdd 269 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 270
271 if (dev->dbbuf_dbs) {
272 dma_free_coherent(dev->dev, mem_size,
273 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
274 dev->dbbuf_dbs = NULL;
275 }
276 if (dev->dbbuf_eis) {
277 dma_free_coherent(dev->dev, mem_size,
278 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
279 dev->dbbuf_eis = NULL;
280 }
281}
282
283static void nvme_dbbuf_init(struct nvme_dev *dev,
284 struct nvme_queue *nvmeq, int qid)
285{
286 if (!dev->dbbuf_dbs || !qid)
287 return;
288
289 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
290 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
291 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
293}
294
0f0d2c87
MI		 295static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
296{
297 if (!nvmeq->qid)
298 return;
299
300 nvmeq->dbbuf_sq_db = NULL;
301 nvmeq->dbbuf_cq_db = NULL;
302 nvmeq->dbbuf_sq_ei = NULL;
303 nvmeq->dbbuf_cq_ei = NULL;
304}
305
f9f38e33
HK		 306static void nvme_dbbuf_set(struct nvme_dev *dev)
307{
f66e2804 308 struct nvme_command c = { };
0f0d2c87 309 unsigned int i;
f9f38e33
HK		 310
311 if (!dev->dbbuf_dbs)
312 return;
313
f9f38e33
HK		 314 c.dbbuf.opcode = nvme_admin_dbbuf;
315 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
316 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
317
318 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 319 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 320 /* Free memory and continue on */
321 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 322
323 for (i = 1; i <= dev->online_queues; i++)
324 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 325 }
326}
327
328static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
329{
330 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
331}
332
333/* Update dbbuf and return true if an MMIO is required */
334static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
335 volatile u32 *dbbuf_ei)
336{
337 if (dbbuf_db) {
338 u16 old_value;
339
340 /*
341 * Ensure that the queue is written before updating
342 * the doorbell in memory
343 */
344 wmb();
345
346 old_value = *dbbuf_db;
347 *dbbuf_db = value;
348
f1ed3df2
MW		 349 /*
350 * Ensure that the doorbell is updated before reading the event
351 * index from memory. The controller needs to provide similar
352 * ordering to ensure the envent index is updated before reading
353 * the doorbell.
354 */
355 mb();
356
f9f38e33
HK		 357 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
358 return false;
359 }
360
361 return true;
b60503ba
MW		 362}
363
ac3dd5bd
JA		 364/*
365 * Will slightly overestimate the number of pages needed. This is OK
366 * as it only leads to a small amount of wasted memory for the lifetime of
367 * the I/O.
368 */
b13c6393 369static int nvme_pci_npages_prp(void)
ac3dd5bd 370{
b13c6393 371 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
6c3c05b0 372 NVME_CTRL_PAGE_SIZE);
ac3dd5bd
JA		 373 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
374}
375
a7a7cbe3
CK		 376/*
377 * Calculates the number of pages needed for the SGL segments. For example a 4k
378 * page can accommodate 256 SGL descriptors.
379 */
b13c6393 380static int nvme_pci_npages_sgl(void)
ac3dd5bd 381{
b13c6393
CK		 382 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
383 PAGE_SIZE);
f4800d6d 384}
ac3dd5bd 385
b13c6393 386static size_t nvme_pci_iod_alloc_size(void)
f4800d6d 387{
b13c6393 388 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
a7a7cbe3 389
b13c6393
CK		 390 return sizeof(__le64 *) * npages +
391 sizeof(struct scatterlist) * NVME_MAX_SEGS;
f4800d6d 392}
ac3dd5bd 393
a4aea562
MB		 394static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
395 unsigned int hctx_idx)
e85248e5 396{
a4aea562 397 struct nvme_dev *dev = data;
147b27e4 398 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 399
42483228
KB		 400 WARN_ON(hctx_idx != 0);
401 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 402
a4aea562
MB		 403 hctx->driver_data = nvmeq;
404 return 0;
e85248e5
MW		 405}
406
a4aea562
MB		 407static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
408 unsigned int hctx_idx)
b60503ba 409{
a4aea562 410 struct nvme_dev *dev = data;
147b27e4 411 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 412
42483228 413 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 414 hctx->driver_data = nvmeq;
415 return 0;
b60503ba
MW		 416}
417
d6296d39
CH		 418static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
419 unsigned int hctx_idx, unsigned int numa_node)
b60503ba 420{
d6296d39 421 struct nvme_dev *dev = set->driver_data;
f4800d6d 422 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
0350815a 423 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
147b27e4 424 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
a4aea562
MB		 425
426 BUG_ON(!nvmeq);
f4800d6d 427 iod->nvmeq = nvmeq;
59e29ce6
SG		 428
429 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 430 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 431 return 0;
432}
433
3b6592f7
JA		 434static int queue_irq_offset(struct nvme_dev *dev)
435{
436 /* if we have more than 1 vec, admin queue offsets us by 1 */
437 if (dev->num_vecs > 1)
438 return 1;
439
440 return 0;
441}
442
dca51e78
CH		 443static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
444{
445 struct nvme_dev *dev = set->driver_data;
3b6592f7
JA		 446 int i, qoff, offset;
447
448 offset = queue_irq_offset(dev);
449 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
450 struct blk_mq_queue_map *map = &set->map[i];
451
452 map->nr_queues = dev->io_queues[i];
453 if (!map->nr_queues) {
e20ba6e1 454 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 455 continue;
3b6592f7
JA		 456 }
457
4b04cc6a
JA		 458 /*
459 * The poll queue(s) doesn't have an IRQ (and hence IRQ
460 * affinity), so use the regular blk-mq cpu mapping
461 */
3b6592f7 462 map->queue_offset = qoff;
cb9e0e50 463 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 464 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
465 else
466 blk_mq_map_queues(map);
3b6592f7
JA		 467 qoff += map->nr_queues;
468 offset += map->nr_queues;
469 }
470
471 return 0;
dca51e78
CH		 472}
473
38210800
KB		 474/*
475 * Write sq tail if we are asked to, or if the next command would wrap.
476 */
477static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 478{
38210800
KB		 479 if (!write_sq) {
480 u16 next_tail = nvmeq->sq_tail + 1;
481
482 if (next_tail == nvmeq->q_depth)
483 next_tail = 0;
484 if (next_tail != nvmeq->last_sq_tail)
485 return;
486 }
487
04f3eafd
JA		 488 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
489 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
490 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 491 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 492}
493
b60503ba 494/**
90ea5ca4 495 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 496 * @nvmeq: The queue to use
497 * @cmd: The command to send
04f3eafd 498 * @write_sq: whether to write to the SQ doorbell
b60503ba 499 */
04f3eafd
JA		 500static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
501 bool write_sq)
b60503ba 502{
90ea5ca4 503 spin_lock(&nvmeq->sq_lock);
c1e0cc7e
BH		 504 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
505 cmd, sizeof(*cmd));
90ea5ca4
CH		 506 if (++nvmeq->sq_tail == nvmeq->q_depth)
507 nvmeq->sq_tail = 0;
38210800 508 nvme_write_sq_db(nvmeq, write_sq);
04f3eafd
JA		 509 spin_unlock(&nvmeq->sq_lock);
510}
511
512static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
513{
514 struct nvme_queue *nvmeq = hctx->driver_data;
515
516 spin_lock(&nvmeq->sq_lock);
38210800
KB		 517 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
518 nvme_write_sq_db(nvmeq, true);
90ea5ca4 519 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 520}
521
a7a7cbe3 522static void **nvme_pci_iod_list(struct request *req)
b60503ba 523{
f4800d6d 524 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 525 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
b60503ba
MW		 526}
527
955b1b5a
MI		 528static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
529{
530 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
20469a37 531 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 532 unsigned int avg_seg_size;
533
20469a37 534 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 535
253a0b76 536 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a
MI		 537 return false;
538 if (!iod->nvmeq->qid)
539 return false;
540 if (!sgl_threshold || avg_seg_size < sgl_threshold)
541 return false;
542 return true;
543}
544
9275c206 545static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 546{
6c3c05b0 547 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 548 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
549 dma_addr_t dma_addr = iod->first_dma;
eca18b23 550 int i;
eca18b23 551
9275c206
CH		 552 for (i = 0; i < iod->npages; i++) {
553 __le64 *prp_list = nvme_pci_iod_list(req)[i];
554 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
555
556 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
557 dma_addr = next_dma_addr;
7fe07d14 558 }
9275c206 559}
dff824b2 560
9275c206
CH		 561static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
562{
563 const int last_sg = SGES_PER_PAGE - 1;
564 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
565 dma_addr_t dma_addr = iod->first_dma;
566 int i;
dff824b2 567
9275c206
CH		 568 for (i = 0; i < iod->npages; i++) {
569 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
570 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
dff824b2 571
9275c206
CH		 572 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
573 dma_addr = next_dma_addr;
574 }
9275c206 575}
a7a7cbe3 576
9275c206
CH		 577static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
578{
579 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 580
9275c206
CH		 581 if (is_pci_p2pdma_page(sg_page(iod->sg)))
582 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
583 rq_dma_dir(req));
584 else
585 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
586}
a7a7cbe3 587
9275c206
CH		 588static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
589{
590 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 591
9275c206
CH		 592 if (iod->dma_len) {
593 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
594 rq_dma_dir(req));
595 return;
eca18b23 596 }
ac3dd5bd 597
9275c206
CH		 598 WARN_ON_ONCE(!iod->nents);
599
600 nvme_unmap_sg(dev, req);
601 if (iod->npages == 0)
602 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
603 iod->first_dma);
604 else if (iod->use_sgl)
605 nvme_free_sgls(dev, req);
606 else
607 nvme_free_prps(dev, req);
d43f1ccf 608 mempool_free(iod->sg, dev->iod_mempool);
b4ff9c8d
KB		 609}
610
d0877473
KB		 611static void nvme_print_sgl(struct scatterlist *sgl, int nents)
612{
613 int i;
614 struct scatterlist *sg;
615
616 for_each_sg(sgl, sg, nents, i) {
617 dma_addr_t phys = sg_phys(sg);
618 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
619 "dma_address:%pad dma_length:%d\n",
620 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
621 sg_dma_len(sg));
622 }
623}
624
a7a7cbe3
CK		 625static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
626 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 627{
f4800d6d 628 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 629 struct dma_pool *pool;
b131c61d 630 int length = blk_rq_payload_bytes(req);
eca18b23 631 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 632 int dma_len = sg_dma_len(sg);
633 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 634 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 635 __le64 *prp_list;
a7a7cbe3 636 void **list = nvme_pci_iod_list(req);
e025344c 637 dma_addr_t prp_dma;
eca18b23 638 int nprps, i;
ff22b54f 639
6c3c05b0 640 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 641 if (length <= 0) {
642 iod->first_dma = 0;
a7a7cbe3 643 goto done;
5228b328 644 }
ff22b54f 645
6c3c05b0 646 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 647 if (dma_len) {
6c3c05b0 648 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 649 } else {
650 sg = sg_next(sg);
651 dma_addr = sg_dma_address(sg);
652 dma_len = sg_dma_len(sg);
653 }
654
6c3c05b0 655 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 656 iod->first_dma = dma_addr;
a7a7cbe3 657 goto done;
e025344c
SMM		 658 }
659
6c3c05b0 660 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 661 if (nprps <= (256 / 8)) {
662 pool = dev->prp_small_pool;
eca18b23 663 iod->npages = 0;
99802a7a
MW		 664 } else {
665 pool = dev->prp_page_pool;
eca18b23 666 iod->npages = 1;
99802a7a
MW		 667 }
668
69d2b571 669 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 670 if (!prp_list) {
edd10d33 671 iod->first_dma = dma_addr;
eca18b23 672 iod->npages = -1;
86eea289 673 return BLK_STS_RESOURCE;
b77954cb 674 }
eca18b23
MW		 675 list[0] = prp_list;
676 iod->first_dma = prp_dma;
e025344c
SMM		 677 i = 0;
678 for (;;) {
6c3c05b0 679 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 680 __le64 *old_prp_list = prp_list;
69d2b571 681 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 682 if (!prp_list)
fa073216 683 goto free_prps;
eca18b23 684 list[iod->npages++] = prp_list;
7523d834
MW		 685 prp_list[0] = old_prp_list[i - 1];
686 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
687 i = 1;
e025344c
SMM		 688 }
689 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 690 dma_len -= NVME_CTRL_PAGE_SIZE;
691 dma_addr += NVME_CTRL_PAGE_SIZE;
692 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 693 if (length <= 0)
694 break;
695 if (dma_len > 0)
696 continue;
86eea289
KB		 697 if (unlikely(dma_len < 0))
698 goto bad_sgl;
e025344c
SMM		 699 sg = sg_next(sg);
700 dma_addr = sg_dma_address(sg);
701 dma_len = sg_dma_len(sg);
ff22b54f 702 }
a7a7cbe3
CK		 703done:
704 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
705 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 706 return BLK_STS_OK;
fa073216
CH		 707free_prps:
708 nvme_free_prps(dev, req);
709 return BLK_STS_RESOURCE;
710bad_sgl:
d0877473
KB		 711 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
712 "Invalid SGL for payload:%d nents:%d\n",
713 blk_rq_payload_bytes(req), iod->nents);
86eea289 714 return BLK_STS_IOERR;
ff22b54f
MW		 715}
716
a7a7cbe3
CK		 717static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
718 struct scatterlist *sg)
719{
720 sge->addr = cpu_to_le64(sg_dma_address(sg));
721 sge->length = cpu_to_le32(sg_dma_len(sg));
722 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
723}
724
725static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
726 dma_addr_t dma_addr, int entries)
727{
728 sge->addr = cpu_to_le64(dma_addr);
729 if (entries < SGES_PER_PAGE) {
730 sge->length = cpu_to_le32(entries * sizeof(*sge));
731 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
732 } else {
733 sge->length = cpu_to_le32(PAGE_SIZE);
734 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
735 }
736}
737
738static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
b0f2853b 739 struct request *req, struct nvme_rw_command *cmd, int entries)
a7a7cbe3
CK		 740{
741 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 742 struct dma_pool *pool;
743 struct nvme_sgl_desc *sg_list;
744 struct scatterlist *sg = iod->sg;
a7a7cbe3 745 dma_addr_t sgl_dma;
b0f2853b 746 int i = 0;
a7a7cbe3 747
a7a7cbe3
CK		 748 /* setting the transfer type as SGL */
749 cmd->flags = NVME_CMD_SGL_METABUF;
750
b0f2853b 751 if (entries == 1) {
a7a7cbe3
CK		 752 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
753 return BLK_STS_OK;
754 }
755
756 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
757 pool = dev->prp_small_pool;
758 iod->npages = 0;
759 } else {
760 pool = dev->prp_page_pool;
761 iod->npages = 1;
762 }
763
764 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
765 if (!sg_list) {
766 iod->npages = -1;
767 return BLK_STS_RESOURCE;
768 }
769
770 nvme_pci_iod_list(req)[0] = sg_list;
771 iod->first_dma = sgl_dma;
772
773 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
774
775 do {
776 if (i == SGES_PER_PAGE) {
777 struct nvme_sgl_desc *old_sg_desc = sg_list;
778 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
779
780 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
781 if (!sg_list)
fa073216 782 goto free_sgls;
a7a7cbe3
CK		 783
784 i = 0;
785 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
786 sg_list[i++] = *link;
787 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
788 }
789
790 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 791 sg = sg_next(sg);
b0f2853b 792 } while (--entries > 0);
a7a7cbe3 793
a7a7cbe3 794 return BLK_STS_OK;
fa073216
CH		 795free_sgls:
796 nvme_free_sgls(dev, req);
797 return BLK_STS_RESOURCE;
a7a7cbe3
CK		 798}
799
dff824b2
CH		 800static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
801 struct request *req, struct nvme_rw_command *cmnd,
802 struct bio_vec *bv)
803{
804 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 805 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
806 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 807
808 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
809 if (dma_mapping_error(dev->dev, iod->first_dma))
810 return BLK_STS_RESOURCE;
811 iod->dma_len = bv->bv_len;
812
813 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
814 if (bv->bv_len > first_prp_len)
815 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
359c1f88 816 return BLK_STS_OK;
dff824b2
CH		 817}
818
29791057
CH		 819static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
820 struct request *req, struct nvme_rw_command *cmnd,
821 struct bio_vec *bv)
822{
823 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
824
825 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
826 if (dma_mapping_error(dev->dev, iod->first_dma))
827 return BLK_STS_RESOURCE;
828 iod->dma_len = bv->bv_len;
829
049bf372 830 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 831 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
832 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
833 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 834 return BLK_STS_OK;
29791057
CH		 835}
836
fc17b653 837static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 838 struct nvme_command *cmnd)
d29ec824 839{
f4800d6d 840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 841 blk_status_t ret = BLK_STS_RESOURCE;
b0f2853b 842 int nr_mapped;
d29ec824 843
dff824b2
CH		 844 if (blk_rq_nr_phys_segments(req) == 1) {
845 struct bio_vec bv = req_bvec(req);
846
847 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 848 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 849 return nvme_setup_prp_simple(dev, req,
850 &cmnd->rw, &bv);
29791057 851
e51183be 852 if (iod->nvmeq->qid && sgl_threshold &&
253a0b76 853 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 854 return nvme_setup_sgl_simple(dev, req,
855 &cmnd->rw, &bv);
dff824b2
CH		 856 }
857 }
858
859 iod->dma_len = 0;
d43f1ccf
CH		 860 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
861 if (!iod->sg)
862 return BLK_STS_RESOURCE;
f9d03f96 863 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
70479b71 864 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
ba1ca37e 865 if (!iod->nents)
fa073216 866 goto out_free_sg;
d29ec824 867
e0596ab2 868 if (is_pci_p2pdma_page(sg_page(iod->sg)))
2b9f4bb2
LG		 869 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
870 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
e0596ab2
LG		 871 else
872 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
70479b71 873 rq_dma_dir(req), DMA_ATTR_NO_WARN);
b0f2853b 874 if (!nr_mapped)
fa073216 875 goto out_free_sg;
d29ec824 876
70479b71 877 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 878 if (iod->use_sgl)
b0f2853b 879 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
a7a7cbe3
CK		 880 else
881 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 882 if (ret != BLK_STS_OK)
fa073216
CH		 883 goto out_unmap_sg;
884 return BLK_STS_OK;
885
886out_unmap_sg:
887 nvme_unmap_sg(dev, req);
888out_free_sg:
889 mempool_free(iod->sg, dev->iod_mempool);
4aedb705
CH		 890 return ret;
891}
3045c0d0 892
4aedb705
CH		 893static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
894 struct nvme_command *cmnd)
895{
896 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 897
4aedb705
CH		 898 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
899 rq_dma_dir(req), 0);
900 if (dma_mapping_error(dev->dev, iod->meta_dma))
901 return BLK_STS_IOERR;
902 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 903 return BLK_STS_OK;
00df5cb4
MW		 904}
905
d29ec824
CH		 906/*
907 * NOTE: ns is NULL when called on the admin queue.
908 */
fc17b653 909static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
a4aea562 910 const struct blk_mq_queue_data *bd)
edd10d33 911{
a4aea562
MB		 912 struct nvme_ns *ns = hctx->queue->queuedata;
913 struct nvme_queue *nvmeq = hctx->driver_data;
d29ec824 914 struct nvme_dev *dev = nvmeq->dev;
a4aea562 915 struct request *req = bd->rq;
9b048119 916 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
af7fae85 917 struct nvme_command *cmnd = &iod->cmd;
ebe6d874 918 blk_status_t ret;
e1e5e564 919
9b048119
CH		 920 iod->aborted = 0;
921 iod->npages = -1;
922 iod->nents = 0;
923
d1f06f4a
JA		 924 /*
925 * We should not need to do this, but we're still using this to
926 * ensure we can drain requests on a dying queue.
927 */
4e224106 928 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
d1f06f4a
JA		 929 return BLK_STS_IOERR;
930
d4060d2b
TC		 931 if (!nvme_check_ready(&dev->ctrl, req, true))
932 return nvme_fail_nonready_command(&dev->ctrl, req);
933
f4b9e6c9 934 ret = nvme_setup_cmd(ns, req);
fc17b653 935 if (ret)
f4800d6d 936 return ret;
a4aea562 937
fc17b653 938 if (blk_rq_nr_phys_segments(req)) {
af7fae85 939 ret = nvme_map_data(dev, req, cmnd);
fc17b653 940 if (ret)
9b048119 941 goto out_free_cmd;
fc17b653 942 }
a4aea562 943
4aedb705 944 if (blk_integrity_rq(req)) {
af7fae85 945 ret = nvme_map_metadata(dev, req, cmnd);
4aedb705
CH		 946 if (ret)
947 goto out_unmap_data;
948 }
949
aae239e1 950 blk_mq_start_request(req);
af7fae85 951 nvme_submit_cmd(nvmeq, cmnd, bd->last);
fc17b653 952 return BLK_STS_OK;
4aedb705
CH		 953out_unmap_data:
954 nvme_unmap_data(dev, req);
f9d03f96
CH		 955out_free_cmd:
956 nvme_cleanup_cmd(req);
ba1ca37e 957 return ret;
b60503ba 958}
e1e5e564 959
77f02a7a 960static void nvme_pci_complete_rq(struct request *req)
eee417b0 961{
f4800d6d 962 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4aedb705 963 struct nvme_dev *dev = iod->nvmeq->dev;
a4aea562 964
4aedb705
CH		 965 if (blk_integrity_rq(req))
966 dma_unmap_page(dev->dev, iod->meta_dma,
967 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
b15c592d 968 if (blk_rq_nr_phys_segments(req))
4aedb705 969 nvme_unmap_data(dev, req);
77f02a7a 970 nvme_complete_rq(req);
b60503ba
MW		 971}
972
d783e0bd 973/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 974static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 975{
74943d45
KB		 976 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
977
978 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 979}
980
eb281c82 981static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 982{
eb281c82 983 u16 head = nvmeq->cq_head;
adf68f21 984
397c699f
KB		 985 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
986 nvmeq->dbbuf_cq_ei))
987 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 988}
aae239e1 989
cfa27356
CH		 990static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
991{
992 if (!nvmeq->qid)
993 return nvmeq->dev->admin_tagset.tags[0];
994 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
995}
996
5cb525c8 997static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
83a12fb7 998{
74943d45 999 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1000 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1001 struct request *req;
adf68f21 1002
83a12fb7
SG		 1003 /*
1004 * AEN requests are special as they don't time out and can
1005 * survive any kind of queue freeze and often don't respond to
1006 * aborts. We don't even bother to allocate a struct request
1007 * for them but rather special case them here.
1008 */
62df8016 1009 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1010 nvme_complete_async_event(&nvmeq->dev->ctrl,
1011 cqe->status, &cqe->result);
a0fa9647 1012 return;
83a12fb7 1013 }
b60503ba 1014
e7006de6 1015 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1016 if (unlikely(!req)) {
1017 dev_warn(nvmeq->dev->ctrl.device,
1018 "invalid id %d completed on queue %d\n",
62df8016 1019 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1020 return;
1021 }
1022
604c01d5 1023 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
2eb81a33 1024 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
ff029451 1025 nvme_pci_complete_rq(req);
83a12fb7 1026}
b60503ba 1027
5cb525c8
JA		 1028static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1029{
a0aac973 1030 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1031
1032 if (tmp == nvmeq->q_depth) {
5cb525c8 1033 nvmeq->cq_head = 0;
e2a366a4 1034 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1035 } else {
1036 nvmeq->cq_head = tmp;
b60503ba 1037 }
a0fa9647
JA		 1038}
1039
324b494c 1040static inline int nvme_process_cq(struct nvme_queue *nvmeq)
a0fa9647 1041{
1052b8ac 1042 int found = 0;
b60503ba 1043
1052b8ac 1044 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1045 found++;
b69e2ef2
KB		 1046 /*
1047 * load-load control dependency between phase and the rest of
1048 * the cqe requires a full read memory barrier
1049 */
1050 dma_rmb();
324b494c 1051 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
5cb525c8 1052 nvme_update_cq_head(nvmeq);
920d13a8 1053 }
eb281c82 1054
324b494c 1055 if (found)
920d13a8 1056 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1057 return found;
b60503ba
MW		 1058}
1059
1060static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1061{
58ffacb5 1062 struct nvme_queue *nvmeq = data;
5cb525c8 1063
324b494c 1064 if (nvme_process_cq(nvmeq))
05fae499
CK		 1065 return IRQ_HANDLED;
1066 return IRQ_NONE;
58ffacb5
MW		 1067}
1068
1069static irqreturn_t nvme_irq_check(int irq, void *data)
1070{
1071 struct nvme_queue *nvmeq = data;
4e523547 1072
750dde44 1073 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1074 return IRQ_WAKE_THREAD;
1075 return IRQ_NONE;
58ffacb5
MW		 1076}
1077
0b2a8a9f 1078/*
fa059b85 1079 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1080 * Can be called from any context.
1081 */
fa059b85 1082static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1083{
3a7afd8e 1084 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1085
fa059b85 1086 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1087
fa059b85
KB		 1088 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1089 nvme_process_cq(nvmeq);
1090 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1091}
1092
9743139c 1093static int nvme_poll(struct blk_mq_hw_ctx *hctx)
dabcefab
JA		 1094{
1095 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1096 bool found;
1097
1098 if (!nvme_cqe_pending(nvmeq))
1099 return 0;
1100
3a7afd8e 1101 spin_lock(&nvmeq->cq_poll_lock);
324b494c 1102 found = nvme_process_cq(nvmeq);
3a7afd8e 1103 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1104
dabcefab
JA		 1105 return found;
1106}
1107
ad22c355 1108static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1109{
f866fc42 1110 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1111 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1112 struct nvme_command c = { };
b60503ba 1113
a4aea562 1114 c.common.opcode = nvme_admin_async_event;
ad22c355 1115 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
04f3eafd 1116 nvme_submit_cmd(nvmeq, &c, true);
f705f837
CH		 1117}
1118
b60503ba 1119static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1120{
f66e2804 1121 struct nvme_command c = { };
b60503ba 1122
b60503ba
MW		 1123 c.delete_queue.opcode = opcode;
1124 c.delete_queue.qid = cpu_to_le16(id);
1125
1c63dc66 1126 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1127}
1128
b60503ba 1129static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1130 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1131{
f66e2804 1132 struct nvme_command c = { };
4b04cc6a
JA		 1133 int flags = NVME_QUEUE_PHYS_CONTIG;
1134
7c349dde 1135 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1136 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1137
d29ec824 1138 /*
16772ae6 1139 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1140 * is attached to the request.
1141 */
b60503ba
MW		 1142 c.create_cq.opcode = nvme_admin_create_cq;
1143 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1144 c.create_cq.cqid = cpu_to_le16(qid);
1145 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1146 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1147 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1148
1c63dc66 1149 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1150}
1151
1152static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1153 struct nvme_queue *nvmeq)
1154{
9abd68ef 1155 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1156 struct nvme_command c = { };
81c1cd98 1157 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1158
9abd68ef
JA		 1159 /*
1160 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1161 * set. Since URGENT priority is zeroes, it makes all queues
1162 * URGENT.
1163 */
1164 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1165 flags |= NVME_SQ_PRIO_MEDIUM;
1166
d29ec824 1167 /*
16772ae6 1168 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1169 * is attached to the request.
1170 */
b60503ba
MW		 1171 c.create_sq.opcode = nvme_admin_create_sq;
1172 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1173 c.create_sq.sqid = cpu_to_le16(qid);
1174 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1175 c.create_sq.sq_flags = cpu_to_le16(flags);
1176 c.create_sq.cqid = cpu_to_le16(qid);
1177
1c63dc66 1178 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1179}
1180
1181static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1182{
1183 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1184}
1185
1186static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1187{
1188 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1189}
1190
2a842aca 1191static void abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1192{
f4800d6d
CH		 1193 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1194 struct nvme_queue *nvmeq = iod->nvmeq;
e44ac588 1195
27fa9bc5
CH		 1196 dev_warn(nvmeq->dev->ctrl.device,
1197 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1198 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1199 blk_mq_free_request(req);
bc5fc7e4
MW		 1200}
1201
b2a0eb1a
KB		 1202static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1203{
b2a0eb1a
KB		 1204 /* If true, indicates loss of adapter communication, possibly by a
1205 * NVMe Subsystem reset.
1206 */
1207 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1208
ad70062c
JW		 1209 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1210 switch (dev->ctrl.state) {
1211 case NVME_CTRL_RESETTING:
ad6a0a52 1212 case NVME_CTRL_CONNECTING:
b2a0eb1a 1213 return false;
ad70062c
JW		 1214 default:
1215 break;
1216 }
b2a0eb1a
KB		 1217
1218 /* We shouldn't reset unless the controller is on fatal error state
1219 * _or_ if we lost the communication with it.
1220 */
1221 if (!(csts & NVME_CSTS_CFS) && !nssro)
1222 return false;
1223
b2a0eb1a
KB		 1224 return true;
1225}
1226
1227static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1228{
1229 /* Read a config register to help see what died. */
1230 u16 pci_status;
1231 int result;
1232
1233 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1234 &pci_status);
1235 if (result == PCIBIOS_SUCCESSFUL)
1236 dev_warn(dev->ctrl.device,
1237 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1238 csts, pci_status);
1239 else
1240 dev_warn(dev->ctrl.device,
1241 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1242 csts, result);
1243}
1244
31c7c7d2 1245static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
c30341dc 1246{
f4800d6d
CH		 1247 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1248 struct nvme_queue *nvmeq = iod->nvmeq;
c30341dc 1249 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1250 struct request *abort_req;
f66e2804 1251 struct nvme_command cmd = { };
b2a0eb1a
KB		 1252 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1253
651438bb
WX		 1254 /* If PCI error recovery process is happening, we cannot reset or
1255 * the recovery mechanism will surely fail.
1256 */
1257 mb();
1258 if (pci_channel_offline(to_pci_dev(dev->dev)))
1259 return BLK_EH_RESET_TIMER;
1260
b2a0eb1a
KB		 1261 /*
1262 * Reset immediately if the controller is failed
1263 */
1264 if (nvme_should_reset(dev, csts)) {
1265 nvme_warn_reset(dev, csts);
1266 nvme_dev_disable(dev, false);
d86c4d8e 1267 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1268 return BLK_EH_DONE;
b2a0eb1a 1269 }
c30341dc 1270
7776db1c
KB		 1271 /*
1272 * Did we miss an interrupt?
1273 */
fa059b85
KB		 1274 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1275 nvme_poll(req->mq_hctx);
1276 else
1277 nvme_poll_irqdisable(nvmeq);
1278
bf392a5d 1279 if (blk_mq_request_completed(req)) {
7776db1c
KB		 1280 dev_warn(dev->ctrl.device,
1281 "I/O %d QID %d timeout, completion polled\n",
1282 req->tag, nvmeq->qid);
db8c48e4 1283 return BLK_EH_DONE;
7776db1c
KB		 1284 }
1285
31c7c7d2 1286 /*
fd634f41
CH		 1287 * Shutdown immediately if controller times out while starting. The
1288 * reset work will see the pci device disabled when it gets the forced
1289 * cancellation error. All outstanding requests are completed on
db8c48e4 1290 * shutdown, so we return BLK_EH_DONE.
fd634f41 1291 */
4244140d
KB		 1292 switch (dev->ctrl.state) {
1293 case NVME_CTRL_CONNECTING:
2036f726 1294 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1295 fallthrough;
2036f726 1296 case NVME_CTRL_DELETING:
b9cac43c 1297 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1298 "I/O %d QID %d timeout, disable controller\n",
1299 req->tag, nvmeq->qid);
27fa9bc5 1300 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1301 nvme_dev_disable(dev, true);
db8c48e4 1302 return BLK_EH_DONE;
39a9dd81
KB		 1303 case NVME_CTRL_RESETTING:
1304 return BLK_EH_RESET_TIMER;
4244140d
KB		 1305 default:
1306 break;
c30341dc
KB		 1307 }
1308
fd634f41 1309 /*
ee0d96d3
BW		 1310 * Shutdown the controller immediately and schedule a reset if the
1311 * command was already aborted once before and still hasn't been
1312 * returned to the driver, or if this is the admin queue.
31c7c7d2 1313 */
f4800d6d 1314 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1315 dev_warn(dev->ctrl.device,
e1569a16
KB		 1316 "I/O %d QID %d timeout, reset controller\n",
1317 req->tag, nvmeq->qid);
7ad92f65 1318 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1319 nvme_dev_disable(dev, false);
d86c4d8e 1320 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1321
db8c48e4 1322 return BLK_EH_DONE;
c30341dc 1323 }
c30341dc 1324
e7a2a87d 1325 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1326 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1327 return BLK_EH_RESET_TIMER;
6bf25d16 1328 }
7bf7d778 1329 iod->aborted = 1;
a4aea562 1330
c30341dc 1331 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1332 cmd.abort.cid = req->tag;
c30341dc 1333 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1334
1b3c47c1
SG		 1335 dev_warn(nvmeq->dev->ctrl.device,
1336 "I/O %d QID %d timeout, aborting\n",
1337 req->tag, nvmeq->qid);
e7a2a87d
CH		 1338
1339 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
39dfe844 1340 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1341 if (IS_ERR(abort_req)) {
1342 atomic_inc(&dev->ctrl.abort_limit);
1343 return BLK_EH_RESET_TIMER;
1344 }
1345
e7a2a87d 1346 abort_req->end_io_data = NULL;
8eeed0b5 1347 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
c30341dc 1348
31c7c7d2
CH		 1349 /*
1350 * The aborted req will be completed on receiving the abort req.
1351 * We enable the timer again. If hit twice, it'll cause a device reset,
1352 * as the device then is in a faulty state.
1353 */
1354 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1355}
1356
a4aea562
MB		 1357static void nvme_free_queue(struct nvme_queue *nvmeq)
1358{
8a1d09a6 1359 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1360 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1361 if (!nvmeq->sq_cmds)
1362 return;
0f238ff5 1363
63223078 1364 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1365 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1366 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1367 } else {
8a1d09a6 1368 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1369 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1370 }
9e866774
MW		 1371}
1372
a1a5ef99 1373static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1374{
1375 int i;
1376
d858e5f0 1377 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1378 dev->ctrl.queue_count--;
147b27e4 1379 nvme_free_queue(&dev->queues[i]);
121c7ad4 1380 }
22404274
KB		 1381}
1382
4d115420
KB		 1383/**
1384 * nvme_suspend_queue - put queue into suspended state
40581d1a 1385 * @nvmeq: queue to suspend
4d115420
KB		 1386 */
1387static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1388{
4e224106 1389 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2b25d981 1390 return 1;
a09115b2 1391
4e224106 1392 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1393 mb();
a09115b2 1394
4e224106 1395 nvmeq->dev->online_queues--;
1c63dc66 1396 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
c81545f9 1397 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
7c349dde
KB		 1398 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1399 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
4d115420
KB		 1400 return 0;
1401}
b60503ba 1402
8fae268b
KB		 1403static void nvme_suspend_io_queues(struct nvme_dev *dev)
1404{
1405 int i;
1406
1407 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1408 nvme_suspend_queue(&dev->queues[i]);
1409}
1410
a5cdb68c 1411static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
4d115420 1412{
147b27e4 1413 struct nvme_queue *nvmeq = &dev->queues[0];
4d115420 1414
a5cdb68c
KB		 1415 if (shutdown)
1416 nvme_shutdown_ctrl(&dev->ctrl);
1417 else
b5b05048 1418 nvme_disable_ctrl(&dev->ctrl);
07836e65 1419
bf392a5d 1420 nvme_poll_irqdisable(nvmeq);
b60503ba
MW		 1421}
1422
fa46c6fb
KB		 1423/*
1424 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1425 * that can check this device's completion queues have synced, except
1426 * nvme_poll(). This is the last chance for the driver to see a natural
1427 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1428 */
1429static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1430{
fa46c6fb
KB		 1431 int i;
1432
9210c075
DZ		 1433 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1434 spin_lock(&dev->queues[i].cq_poll_lock);
324b494c 1435 nvme_process_cq(&dev->queues[i]);
9210c075
DZ		 1436 spin_unlock(&dev->queues[i].cq_poll_lock);
1437 }
fa46c6fb
KB		 1438}
1439
8ffaadf7
JD		 1440static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1441 int entry_size)
1442{
1443 int q_depth = dev->q_depth;
5fd4ce1b 1444 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1445 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1446
1447 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1448 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1449
6c3c05b0 1450 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1451 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1452
1453 /*
1454 * Ensure the reduced q_depth is above some threshold where it
1455 * would be better to map queues in system memory with the
1456 * original depth
1457 */
1458 if (q_depth < 64)
1459 return -ENOMEM;
1460 }
1461
1462 return q_depth;
1463}
1464
1465static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1466 int qid)
8ffaadf7 1467{
0f238ff5
LG		 1468 struct pci_dev *pdev = to_pci_dev(dev->dev);
1469
1470 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1471 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1472 if (nvmeq->sq_cmds) {
1473 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1474 nvmeq->sq_cmds);
1475 if (nvmeq->sq_dma_addr) {
1476 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1477 return 0;
1478 }
1479
8a1d09a6 1480 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1481 }
0f238ff5 1482 }
8ffaadf7 1483
8a1d09a6 1484 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1485 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1486 if (!nvmeq->sq_cmds)
1487 return -ENOMEM;
8ffaadf7
JD		 1488 return 0;
1489}
1490
a6ff7262 1491static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1492{
147b27e4 1493 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1494
62314e40
KB		 1495 if (dev->ctrl.queue_count > qid)
1496 return 0;
b60503ba 1497
c1e0cc7e 1498 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1499 nvmeq->q_depth = depth;
1500 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1501 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1502 if (!nvmeq->cqes)
1503 goto free_nvmeq;
b60503ba 1504
8a1d09a6 1505 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1506 goto free_cqdma;
1507
091b6092 1508 nvmeq->dev = dev;
1ab0cd69 1509 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1510 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1511 nvmeq->cq_head = 0;
82123460 1512 nvmeq->cq_phase = 1;
b80d5ccc 1513 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1514 nvmeq->qid = qid;
d858e5f0 1515 dev->ctrl.queue_count++;
36a7e993 1516
147b27e4 1517 return 0;
b60503ba
MW		 1518
1519 free_cqdma:
8a1d09a6
BH		 1520 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1521 nvmeq->cq_dma_addr);
b60503ba 1522 free_nvmeq:
147b27e4 1523 return -ENOMEM;
b60503ba
MW		 1524}
1525
dca51e78 1526static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1527{
0ff199cb
CH		 1528 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1529 int nr = nvmeq->dev->ctrl.instance;
1530
1531 if (use_threaded_interrupts) {
1532 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1533 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1534 } else {
1535 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1536 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1537 }
3001082c
MW		 1538}
1539
22404274 1540static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1541{
22404274 1542 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1543
22404274 1544 nvmeq->sq_tail = 0;
38210800 1545 nvmeq->last_sq_tail = 0;
22404274
KB		 1546 nvmeq->cq_head = 0;
1547 nvmeq->cq_phase = 1;
b80d5ccc 1548 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1549 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1550 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1551 dev->online_queues++;
3a7afd8e 1552 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1553}
1554
e4b9852a
CC		 1555/*
1556 * Try getting shutdown_lock while setting up IO queues.
1557 */
1558static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1559{
1560 /*
1561 * Give up if the lock is being held by nvme_dev_disable.
1562 */
1563 if (!mutex_trylock(&dev->shutdown_lock))
1564 return -ENODEV;
1565
1566 /*
1567 * Controller is in wrong state, fail early.
1568 */
1569 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1570 mutex_unlock(&dev->shutdown_lock);
1571 return -ENODEV;
1572 }
1573
1574 return 0;
1575}
1576
4b04cc6a 1577static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1578{
1579 struct nvme_dev *dev = nvmeq->dev;
1580 int result;
7c349dde 1581 u16 vector = 0;
3f85d50b 1582
d1ed6aa1
CH		 1583 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1584
22b55601
KB		 1585 /*
1586 * A queue's vector matches the queue identifier unless the controller
1587 * has only one vector available.
1588 */
4b04cc6a
JA		 1589 if (!polled)
1590 vector = dev->num_vecs == 1 ? 0 : qid;
1591 else
7c349dde 1592 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1593
a8e3e0bb 1594 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1595 if (result)
1596 return result;
b60503ba
MW		 1597
1598 result = adapter_alloc_sq(dev, qid, nvmeq);
1599 if (result < 0)
ded45505 1600 return result;
c80b36cd 1601 if (result)
b60503ba
MW		 1602 goto release_cq;
1603
a8e3e0bb 1604 nvmeq->cq_vector = vector;
4b04cc6a 1605
e4b9852a
CC		 1606 result = nvme_setup_io_queues_trylock(dev);
1607 if (result)
1608 return result;
1609 nvme_init_queue(nvmeq, qid);
7c349dde 1610 if (!polled) {
4b04cc6a
JA		 1611 result = queue_request_irq(nvmeq);
1612 if (result < 0)
1613 goto release_sq;
1614 }
b60503ba 1615
4e224106 1616 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1617 mutex_unlock(&dev->shutdown_lock);
22404274 1618 return result;
b60503ba 1619
a8e3e0bb 1620release_sq:
f25a2dfc 1621 dev->online_queues--;
e4b9852a 1622 mutex_unlock(&dev->shutdown_lock);
b60503ba 1623 adapter_delete_sq(dev, qid);
a8e3e0bb 1624release_cq:
b60503ba 1625 adapter_delete_cq(dev, qid);
22404274 1626 return result;
b60503ba
MW		 1627}
1628
f363b089 1629static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1630 .queue_rq = nvme_queue_rq,
77f02a7a 1631 .complete = nvme_pci_complete_rq,
a4aea562 1632 .init_hctx = nvme_admin_init_hctx,
0350815a 1633 .init_request = nvme_init_request,
a4aea562
MB		 1634 .timeout = nvme_timeout,
1635};
1636
f363b089 1637static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8
CH		 1638 .queue_rq = nvme_queue_rq,
1639 .complete = nvme_pci_complete_rq,
1640 .commit_rqs = nvme_commit_rqs,
1641 .init_hctx = nvme_init_hctx,
1642 .init_request = nvme_init_request,
1643 .map_queues = nvme_pci_map_queues,
1644 .timeout = nvme_timeout,
1645 .poll = nvme_poll,
dabcefab
JA		 1646};
1647
ea191d2f
KB		 1648static void nvme_dev_remove_admin(struct nvme_dev *dev)
1649{
1c63dc66 1650 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1651 /*
1652 * If the controller was reset during removal, it's possible
1653 * user requests may be waiting on a stopped queue. Start the
1654 * queue to flush these to completion.
1655 */
c81545f9 1656 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1c63dc66 1657 blk_cleanup_queue(dev->ctrl.admin_q);
ea191d2f
KB		 1658 blk_mq_free_tag_set(&dev->admin_tagset);
1659 }
1660}
1661
a4aea562
MB		 1662static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1663{
1c63dc66 1664 if (!dev->ctrl.admin_q) {
a4aea562
MB		 1665 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1666 dev->admin_tagset.nr_hw_queues = 1;
e3e9d50c 1667
38dabe21 1668 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
dc96f938 1669 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
d4ec47f1 1670 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
d43f1ccf 1671 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
d3484991 1672 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
a4aea562
MB		 1673 dev->admin_tagset.driver_data = dev;
1674
1675 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1676 return -ENOMEM;
34b6c231 1677 dev->ctrl.admin_tagset = &dev->admin_tagset;
a4aea562 1678
1c63dc66
CH		 1679 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1680 if (IS_ERR(dev->ctrl.admin_q)) {
a4aea562
MB		 1681 blk_mq_free_tag_set(&dev->admin_tagset);
1682 return -ENOMEM;
1683 }
1c63dc66 1684 if (!blk_get_queue(dev->ctrl.admin_q)) {
ea191d2f 1685 nvme_dev_remove_admin(dev);
1c63dc66 1686 dev->ctrl.admin_q = NULL;
ea191d2f
KB		 1687 return -ENODEV;
1688 }
0fb59cbc 1689 } else
c81545f9 1690 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
a4aea562
MB		 1691
1692 return 0;
1693}
1694
97f6ef64
XY		 1695static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1696{
1697 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1698}
1699
1700static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1701{
1702 struct pci_dev *pdev = to_pci_dev(dev->dev);
1703
1704 if (size <= dev->bar_mapped_size)
1705 return 0;
1706 if (size > pci_resource_len(pdev, 0))
1707 return -ENOMEM;
1708 if (dev->bar)
1709 iounmap(dev->bar);
1710 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1711 if (!dev->bar) {
1712 dev->bar_mapped_size = 0;
1713 return -ENOMEM;
1714 }
1715 dev->bar_mapped_size = size;
1716 dev->dbs = dev->bar + NVME_REG_DBS;
1717
1718 return 0;
1719}
1720
01ad0990 1721static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1722{
ba47e386 1723 int result;
b60503ba
MW		 1724 u32 aqa;
1725 struct nvme_queue *nvmeq;
1726
97f6ef64
XY		 1727 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1728 if (result < 0)
1729 return result;
1730
8ef2074d 1731 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1732 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1733
7a67cbea
CH		 1734 if (dev->subsystem &&
1735 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1736 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1737
b5b05048 1738 result = nvme_disable_ctrl(&dev->ctrl);
ba47e386
MW		 1739 if (result < 0)
1740 return result;
b60503ba 1741
a6ff7262 1742 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1743 if (result)
1744 return result;
b60503ba 1745
635333e4
MG		 1746 dev->ctrl.numa_node = dev_to_node(dev->dev);
1747
147b27e4 1748 nvmeq = &dev->queues[0];
b60503ba
MW		 1749 aqa = nvmeq->q_depth - 1;
1750 aqa |= aqa << 16;
1751
7a67cbea
CH		 1752 writel(aqa, dev->bar + NVME_REG_AQA);
1753 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1754 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1755
c0f2f45b 1756 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1757 if (result)
d4875622 1758 return result;
a4aea562 1759
2b25d981 1760 nvmeq->cq_vector = 0;
161b8be2 1761 nvme_init_queue(nvmeq, 0);
dca51e78 1762 result = queue_request_irq(nvmeq);
758dd7fd 1763 if (result) {
7c349dde 1764 dev->online_queues--;
d4875622 1765 return result;
758dd7fd 1766 }
025c557a 1767
4e224106 1768 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1769 return result;
1770}
1771
749941f2 1772static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1773{
4b04cc6a 1774 unsigned i, max, rw_queues;
749941f2 1775 int ret = 0;
42f61420 1776
d858e5f0 1777 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1778 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1779 ret = -ENOMEM;
42f61420 1780 break;
749941f2
CH		 1781 }
1782 }
42f61420 1783
d858e5f0 1784 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1785 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1786 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1787 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1788 } else {
1789 rw_queues = max;
1790 }
1791
949928c1 1792 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1793 bool polled = i > rw_queues;
1794
1795 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1796 if (ret)
42f61420 1797 break;
27e8166c 1798 }
749941f2
CH		 1799
1800 /*
1801 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1802 * than the desired amount of queues, and even a controller without
1803 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1804 * be useful to upgrade a buggy firmware for example.
1805 */
1806 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1807}
1808
88de4598 1809static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1810{
88de4598
CH		 1811 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1812
1813 return 1ULL << (12 + 4 * szu);
1814}
1815
1816static u32 nvme_cmb_size(struct nvme_dev *dev)
1817{
1818 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1819}
1820
f65efd6d 1821static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1822{
88de4598 1823 u64 size, offset;
8ffaadf7
JD		 1824 resource_size_t bar_size;
1825 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1826 int bar;
8ffaadf7 1827
9fe5c59f
KB		 1828 if (dev->cmb_size)
1829 return;
1830
20d3bb92
KJ		 1831 if (NVME_CAP_CMBS(dev->ctrl.cap))
1832 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1833
7a67cbea 1834 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1835 if (!dev->cmbsz)
1836 return;
202021c1 1837 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1838
88de4598
CH		 1839 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1840 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1841 bar = NVME_CMB_BIR(dev->cmbloc);
1842 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1843
1844 if (offset > bar_size)
f65efd6d 1845 return;
8ffaadf7 1846
20d3bb92
KJ		 1847 /*
1848 * Tell the controller about the host side address mapping the CMB,
1849 * and enable CMB decoding for the NVMe 1.4+ scheme:
1850 */
1851 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1852 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1853 (pci_bus_address(pdev, bar) + offset),
1854 dev->bar + NVME_REG_CMBMSC);
1855 }
1856
8ffaadf7
JD		 1857 /*
1858 * Controllers may support a CMB size larger than their BAR,
1859 * for example, due to being behind a bridge. Reduce the CMB to
1860 * the reported size of the BAR
1861 */
1862 if (size > bar_size - offset)
1863 size = bar_size - offset;
1864
0f238ff5
LG		 1865 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1866 dev_warn(dev->ctrl.device,
1867 "failed to register the CMB\n");
f65efd6d 1868 return;
0f238ff5
LG		 1869 }
1870
8ffaadf7 1871 dev->cmb_size = size;
0f238ff5
LG		 1872 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1873
1874 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1875 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1876 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1877}
1878
87ad72a5
CH		 1879static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1880{
6c3c05b0 1881 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1882 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1883 struct nvme_command c = { };
87ad72a5
CH		 1884 int ret;
1885
87ad72a5
CH		 1886 c.features.opcode = nvme_admin_set_features;
1887 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1888 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1889 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1890 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1891 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1892 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1893
1894 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1895 if (ret) {
1896 dev_warn(dev->ctrl.device,
1897 "failed to set host mem (err %d, flags %#x).\n",
1898 ret, bits);
1899 }
87ad72a5
CH		 1900 return ret;
1901}
1902
1903static void nvme_free_host_mem(struct nvme_dev *dev)
1904{
1905 int i;
1906
1907 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1908 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1909 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1910
cc667f6d
LD		 1911 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1912 le64_to_cpu(desc->addr),
1913 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1914 }
1915
1916 kfree(dev->host_mem_desc_bufs);
1917 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1918 dma_free_coherent(dev->dev,
1919 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1920 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1921 dev->host_mem_descs = NULL;
7e5dd57e 1922 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1923}
1924
92dc6895
CH		 1925static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1926 u32 chunk_size)
9d713c2b 1927{
87ad72a5 1928 struct nvme_host_mem_buf_desc *descs;
92dc6895 1929 u32 max_entries, len;
4033f35d 1930 dma_addr_t descs_dma;
2ee0e4ed 1931 int i = 0;
87ad72a5 1932 void **bufs;
6fbcde66 1933 u64 size, tmp;
87ad72a5 1934
87ad72a5
CH		 1935 tmp = (preferred + chunk_size - 1);
1936 do_div(tmp, chunk_size);
1937 max_entries = tmp;
044a9df1
CH		 1938
1939 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1940 max_entries = dev->ctrl.hmmaxd;
1941
750afb08
LC		 1942 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1943 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1944 if (!descs)
1945 goto out;
1946
1947 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1948 if (!bufs)
1949 goto out_free_descs;
1950
244a8fe4 1951 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1952 dma_addr_t dma_addr;
1953
50cdb7c6 1954 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1955 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1956 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1957 if (!bufs[i])
1958 break;
1959
1960 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1961 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1962 i++;
1963 }
1964
92dc6895 1965 if (!size)
87ad72a5 1966 goto out_free_bufs;
87ad72a5 1967
87ad72a5
CH		 1968 dev->nr_host_mem_descs = i;
1969 dev->host_mem_size = size;
1970 dev->host_mem_descs = descs;
4033f35d 1971 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1972 dev->host_mem_desc_bufs = bufs;
1973 return 0;
1974
1975out_free_bufs:
1976 while (--i >= 0) {
6c3c05b0 1977 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1978
cc667f6d
LD		 1979 dma_free_attrs(dev->dev, size, bufs[i],
1980 le64_to_cpu(descs[i].addr),
1981 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1982 }
1983
1984 kfree(bufs);
1985out_free_descs:
4033f35d
CH		 1986 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1987 descs_dma);
87ad72a5 1988out:
87ad72a5
CH		 1989 dev->host_mem_descs = NULL;
1990 return -ENOMEM;
1991}
1992
92dc6895
CH		 1993static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1994{
9dc54a0d
CK		 1995 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1996 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1997 u64 chunk_size;
92dc6895
CH		 1998
1999 /* start big and work our way down */
9dc54a0d 2000 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2001 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2002 if (!min || dev->host_mem_size >= min)
2003 return 0;
2004 nvme_free_host_mem(dev);
2005 }
2006 }
2007
2008 return -ENOMEM;
2009}
2010
9620cfba 2011static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2012{
2013 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2014 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2015 u64 min = (u64)dev->ctrl.hmmin * 4096;
2016 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2017 int ret;
87ad72a5
CH		 2018
2019 preferred = min(preferred, max);
2020 if (min > max) {
2021 dev_warn(dev->ctrl.device,
2022 "min host memory (%lld MiB) above limit (%d MiB).\n",
2023 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2024 nvme_free_host_mem(dev);
9620cfba 2025 return 0;
87ad72a5
CH		 2026 }
2027
2028 /*
2029 * If we already have a buffer allocated check if we can reuse it.
2030 */
2031 if (dev->host_mem_descs) {
2032 if (dev->host_mem_size >= min)
2033 enable_bits |= NVME_HOST_MEM_RETURN;
2034 else
2035 nvme_free_host_mem(dev);
2036 }
2037
2038 if (!dev->host_mem_descs) {
92dc6895
CH		 2039 if (nvme_alloc_host_mem(dev, min, preferred)) {
2040 dev_warn(dev->ctrl.device,
2041 "failed to allocate host memory buffer.\n");
9620cfba 2042 return 0; /* controller must work without HMB */
92dc6895
CH		 2043 }
2044
2045 dev_info(dev->ctrl.device,
2046 "allocated %lld MiB host memory buffer.\n",
2047 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2048 }
2049
9620cfba
CH		 2050 ret = nvme_set_host_mem(dev, enable_bits);
2051 if (ret)
87ad72a5 2052 nvme_free_host_mem(dev);
9620cfba 2053 return ret;
9d713c2b
KB		 2054}
2055
0521905e
KB		 2056static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2057 char *buf)
2058{
2059 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2060
2061 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2062 ndev->cmbloc, ndev->cmbsz);
2063}
2064static DEVICE_ATTR_RO(cmb);
2065
2066static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2067 struct attribute *a, int n)
2068{
2069 struct nvme_ctrl *ctrl =
2070 dev_get_drvdata(container_of(kobj, struct device, kobj));
2071 struct nvme_dev *dev = to_nvme_dev(ctrl);
2072
2073 if (a == &dev_attr_cmb.attr && !dev->cmbsz)
2074 return 0;
2075 return a->mode;
2076}
2077
2078static struct attribute *nvme_pci_attrs[] = {
2079 &dev_attr_cmb.attr,
2080 NULL,
2081};
2082
2083static const struct attribute_group nvme_pci_attr_group = {
2084 .attrs = nvme_pci_attrs,
2085 .is_visible = nvme_pci_attrs_are_visible,
2086};
2087
612b7286
ML		 2088/*
2089 * nirqs is the number of interrupts available for write and read
2090 * queues. The core already reserved an interrupt for the admin queue.
2091 */
2092static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2093{
612b7286 2094 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2095 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2096
2097 /*
ee0d96d3 2098 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2099 * the default queue is set to 1. The affinity set size is
2100 * also set to one, but the irq core ignores it for this case.
2101 *
2102 * If only one interrupt is available or 'write_queue' == 0, combine
2103 * write and read queues.
2104 *
2105 * If 'write_queues' > 0, ensure it leaves room for at least one read
2106 * queue.
3b6592f7 2107 */
612b7286
ML		 2108 if (!nrirqs) {
2109 nrirqs = 1;
2110 nr_read_queues = 0;
2a5bcfdd 2111 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2112 nr_read_queues = 0;
2a5bcfdd 2113 } else if (nr_write_queues >= nrirqs) {
612b7286 2114 nr_read_queues = 1;
3b6592f7 2115 } else {
2a5bcfdd 2116 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2117 }
612b7286
ML		 2118
2119 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2120 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2121 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2122 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2123 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2124}
2125
6451fe73 2126static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2127{
2128 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2129 struct irq_affinity affd = {
9cfef55b 2130 .pre_vectors = 1,
612b7286
ML		 2131 .calc_sets = nvme_calc_irq_sets,
2132 .priv = dev,
3b6592f7 2133 };
21cc2f3f 2134 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2135
2136 /*
21cc2f3f
JX		 2137 * Poll queues don't need interrupts, but we need at least one I/O queue
2138 * left over for non-polled I/O.
6451fe73 2139 */
21cc2f3f
JX		 2140 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2141 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2142
21cc2f3f
JX		 2143 /*
2144 * Initialize for the single interrupt case, will be updated in
2145 * nvme_calc_irq_sets().
2146 */
612b7286
ML		 2147 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2148 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2149
66341331 2150 /*
21cc2f3f
JX		 2151 * We need interrupts for the admin queue and each non-polled I/O queue,
2152 * but some Apple controllers require all queues to use the first
2153 * vector.
66341331 2154 */
21cc2f3f
JX		 2155 irq_queues = 1;
2156 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2157 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2158 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2159 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2160}
2161
8fae268b
KB		 2162static void nvme_disable_io_queues(struct nvme_dev *dev)
2163{
2164 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2165 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2166}
2167
2a5bcfdd
WZ		 2168static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2169{
e3aef095
NS		 2170 /*
2171 * If tags are shared with admin queue (Apple bug), then
2172 * make sure we only use one IO queue.
2173 */
2174 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2175 return 1;
2a5bcfdd
WZ		 2176 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2177}
2178
8d85fce7 2179static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2180{
147b27e4 2181 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2182 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2183 unsigned int nr_io_queues;
97f6ef64 2184 unsigned long size;
2a5bcfdd 2185 int result;
b60503ba 2186
2a5bcfdd
WZ		 2187 /*
2188 * Sample the module parameters once at reset time so that we have
2189 * stable values to work with.
2190 */
2191 dev->nr_write_queues = write_queues;
2192 dev->nr_poll_queues = poll_queues;
d38e9f04 2193
e3aef095 2194 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2195 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2196 if (result < 0)
1b23484b 2197 return result;
9a0be7ab 2198
f5fa90dc 2199 if (nr_io_queues == 0)
a5229050 2200 return 0;
53dc180e 2201
e4b9852a
CC		 2202 /*
2203 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2204 * from set to unset. If there is a window to it is truely freed,
2205 * pci_free_irq_vectors() jumping into this window will crash.
2206 * And take lock to avoid racing with pci_free_irq_vectors() in
2207 * nvme_dev_disable() path.
2208 */
2209 result = nvme_setup_io_queues_trylock(dev);
2210 if (result)
2211 return result;
2212 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2213 pci_free_irq(pdev, 0, adminq);
b60503ba 2214
0f238ff5 2215 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2216 result = nvme_cmb_qdepth(dev, nr_io_queues,
2217 sizeof(struct nvme_command));
2218 if (result > 0)
2219 dev->q_depth = result;
2220 else
0f238ff5 2221 dev->cmb_use_sqes = false;
8ffaadf7
JD		 2222 }
2223
97f6ef64
XY		 2224 do {
2225 size = db_bar_size(dev, nr_io_queues);
2226 result = nvme_remap_bar(dev, size);
2227 if (!result)
2228 break;
e4b9852a
CC		 2229 if (!--nr_io_queues) {
2230 result = -ENOMEM;
2231 goto out_unlock;
2232 }
97f6ef64
XY		 2233 } while (1);
2234 adminq->q_db = dev->dbs;
f1938f6e 2235
8fae268b 2236 retry:
9d713c2b 2237 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2238 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2239 pci_free_irq(pdev, 0, adminq);
9d713c2b 2240
e32efbfc
JA		 2241 /*
2242 * If we enable msix early due to not intx, disable it again before
2243 * setting up the full range we need.
2244 */
dca51e78 2245 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2246
2247 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2248 if (result <= 0) {
2249 result = -EIO;
2250 goto out_unlock;
2251 }
3b6592f7 2252
22b55601 2253 dev->num_vecs = result;
4b04cc6a 2254 result = max(result - 1, 1);
e20ba6e1 2255 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2256
063a8096
MW		 2257 /*
2258 * Should investigate if there's a performance win from allocating
2259 * more queues than interrupt vectors; it might allow the submission
2260 * path to scale better, even if the receive path is limited by the
2261 * number of interrupts.
2262 */
dca51e78 2263 result = queue_request_irq(adminq);
7c349dde 2264 if (result)
e4b9852a 2265 goto out_unlock;
4e224106 2266 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2267 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2268
2269 result = nvme_create_io_queues(dev);
2270 if (result || dev->online_queues < 2)
2271 return result;
2272
2273 if (dev->online_queues - 1 < dev->max_qid) {
2274 nr_io_queues = dev->online_queues - 1;
2275 nvme_disable_io_queues(dev);
e4b9852a
CC		 2276 result = nvme_setup_io_queues_trylock(dev);
2277 if (result)
2278 return result;
8fae268b
KB		 2279 nvme_suspend_io_queues(dev);
2280 goto retry;
2281 }
2282 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2283 dev->io_queues[HCTX_TYPE_DEFAULT],
2284 dev->io_queues[HCTX_TYPE_READ],
2285 dev->io_queues[HCTX_TYPE_POLL]);
2286 return 0;
e4b9852a
CC		 2287out_unlock:
2288 mutex_unlock(&dev->shutdown_lock);
2289 return result;
b60503ba
MW		 2290}
2291
2a842aca 2292static void nvme_del_queue_end(struct request *req, blk_status_t error)
a5768aa8 2293{
db3cbfff 2294 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2295
db3cbfff 2296 blk_mq_free_request(req);
d1ed6aa1 2297 complete(&nvmeq->delete_done);
a5768aa8
KB		 2298}
2299
2a842aca 2300static void nvme_del_cq_end(struct request *req, blk_status_t error)
a5768aa8 2301{
db3cbfff 2302 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2303
d1ed6aa1
CH		 2304 if (error)
2305 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff
KB		 2306
2307 nvme_del_queue_end(req, error);
a5768aa8
KB		 2308}
2309
db3cbfff 2310static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2311{
db3cbfff
KB		 2312 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2313 struct request *req;
f66e2804 2314 struct nvme_command cmd = { };
bda4e0fb 2315
db3cbfff
KB		 2316 cmd.delete_queue.opcode = opcode;
2317 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2318
39dfe844 2319 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2320 if (IS_ERR(req))
2321 return PTR_ERR(req);
bda4e0fb 2322
db3cbfff
KB		 2323 req->end_io_data = nvmeq;
2324
d1ed6aa1 2325 init_completion(&nvmeq->delete_done);
8eeed0b5 2326 blk_execute_rq_nowait(NULL, req, false,
db3cbfff
KB		 2327 opcode == nvme_admin_delete_cq ?
2328 nvme_del_cq_end : nvme_del_queue_end);
2329 return 0;
bda4e0fb
KB		 2330}
2331
8fae268b 2332static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2333{
5271edd4 2334 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2335 unsigned long timeout;
a5768aa8 2336
db3cbfff 2337 retry:
dc96f938 2338 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2339 while (nr_queues > 0) {
2340 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2341 break;
2342 nr_queues--;
2343 sent++;
db3cbfff 2344 }
d1ed6aa1
CH		 2345 while (sent) {
2346 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2347
2348 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2349 timeout);
2350 if (timeout == 0)
2351 return false;
d1ed6aa1 2352
d1ed6aa1 2353 sent--;
5271edd4
CH		 2354 if (nr_queues)
2355 goto retry;
2356 }
2357 return true;
a5768aa8
KB		 2358}
2359
5d02a5c1 2360static void nvme_dev_add(struct nvme_dev *dev)
b60503ba 2361{
2b1b7e78
JW		 2362 int ret;
2363
5bae7f73 2364 if (!dev->ctrl.tagset) {
376f7ef8 2365 dev->tagset.ops = &nvme_mq_ops;
ffe7704d 2366 dev->tagset.nr_hw_queues = dev->online_queues - 1;
8fe34be1 2367 dev->tagset.nr_maps = 2; /* default + read */
ed92ad37
CH		 2368 if (dev->io_queues[HCTX_TYPE_POLL])
2369 dev->tagset.nr_maps++;
ffe7704d 2370 dev->tagset.timeout = NVME_IO_TIMEOUT;
d4ec47f1 2371 dev->tagset.numa_node = dev->ctrl.numa_node;
61f3b896
CK		 2372 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2373 BLK_MQ_MAX_DEPTH) - 1;
d43f1ccf 2374 dev->tagset.cmd_size = sizeof(struct nvme_iod);
ffe7704d
KB		 2375 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2376 dev->tagset.driver_data = dev;
b60503ba 2377
d38e9f04
BH		 2378 /*
2379 * Some Apple controllers requires tags to be unique
2380 * across admin and IO queue, so reserve the first 32
2381 * tags of the IO queue.
2382 */
2383 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2384 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2385
2b1b7e78
JW		 2386 ret = blk_mq_alloc_tag_set(&dev->tagset);
2387 if (ret) {
2388 dev_warn(dev->ctrl.device,
2389 "IO queues tagset allocation failed %d\n", ret);
5d02a5c1 2390 return;
2b1b7e78 2391 }
5bae7f73 2392 dev->ctrl.tagset = &dev->tagset;
949928c1
KB		 2393 } else {
2394 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2395
2396 /* Free previously allocated queues that are no longer usable */
2397 nvme_free_queues(dev, dev->online_queues);
ffe7704d 2398 }
949928c1 2399
e8fd41bb 2400 nvme_dbbuf_set(dev);
b60503ba
MW		 2401}
2402
b00a726a 2403static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2404{
b00a726a 2405 int result = -ENOMEM;
e75ec752 2406 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2407 int dma_address_bits = 64;
0877cb0d
KB		 2408
2409 if (pci_enable_device_mem(pdev))
2410 return result;
2411
0877cb0d 2412 pci_set_master(pdev);
0877cb0d 2413
4bdf2603
FS		 2414 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2415 dma_address_bits = 48;
2416 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2417 goto disable;
0877cb0d 2418
7a67cbea 2419 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2420 result = -ENODEV;
b00a726a 2421 goto disable;
0e53d180 2422 }
e32efbfc
JA		 2423
2424 /*
a5229050
KB		 2425 * Some devices and/or platforms don't advertise or work with INTx
2426 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2427 * adjust this later.
e32efbfc 2428 */
dca51e78
CH		 2429 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2430 if (result < 0)
2431 return result;
e32efbfc 2432
20d0dfe6 2433 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2434
7442ddce 2435 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2436 io_queue_depth);
aa22c8e6 2437 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
20d0dfe6 2438 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2439 dev->dbs = dev->bar + 4096;
1f390c1f 2440
66341331
BH		 2441 /*
2442 * Some Apple controllers require a non-standard SQE size.
2443 * Interestingly they also seem to ignore the CC:IOSQES register
2444 * so we don't bother updating it here.
2445 */
2446 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2447 dev->io_sqes = 7;
2448 else
2449 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2450
2451 /*
2452 * Temporary fix for the Apple controller found in the MacBook8,1 and
2453 * some MacBook7,1 to avoid controller resets and data loss.
2454 */
2455 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2456 dev->q_depth = 2;
9bdcfb10
CH		 2457 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2458 "set queue depth=%u to work around controller resets\n",
1f390c1f 2459 dev->q_depth);
d554b5e1
MP		 2460 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2461 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2462 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2463 dev->q_depth = 64;
2464 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2465 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2466 }
2467
d38e9f04
BH		 2468 /*
2469 * Controllers with the shared tags quirk need the IO queue to be
2470 * big enough so that we get 32 tags for the admin queue
2471 */
2472 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2473 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2474 dev->q_depth = NVME_AQ_DEPTH + 2;
2475 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2476 dev->q_depth);
2477 }
2478
2479
f65efd6d 2480 nvme_map_cmb(dev);
202021c1 2481
a0a3408e
KB		 2482 pci_enable_pcie_error_reporting(pdev);
2483 pci_save_state(pdev);
0877cb0d
KB		 2484 return 0;
2485
2486 disable:
0877cb0d
KB		 2487 pci_disable_device(pdev);
2488 return result;
2489}
2490
2491static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2492{
2493 if (dev->bar)
2494 iounmap(dev->bar);
a1f447b3 2495 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2496}
2497
2498static void nvme_pci_disable(struct nvme_dev *dev)
0877cb0d 2499{
e75ec752
CH		 2500 struct pci_dev *pdev = to_pci_dev(dev->dev);
2501
dca51e78 2502 pci_free_irq_vectors(pdev);
0877cb0d 2503
a0a3408e
KB		 2504 if (pci_is_enabled(pdev)) {
2505 pci_disable_pcie_error_reporting(pdev);
e75ec752 2506 pci_disable_device(pdev);
4d115420 2507 }
4d115420
KB		 2508}
2509
a5cdb68c 2510static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2511{
e43269e6 2512 bool dead = true, freeze = false;
302ad8cc 2513 struct pci_dev *pdev = to_pci_dev(dev->dev);
22404274 2514
77bf25ea 2515 mutex_lock(&dev->shutdown_lock);
302ad8cc
KB		 2516 if (pci_is_enabled(pdev)) {
2517 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2518
ebef7368 2519 if (dev->ctrl.state == NVME_CTRL_LIVE ||
e43269e6
KB		 2520 dev->ctrl.state == NVME_CTRL_RESETTING) {
2521 freeze = true;
302ad8cc 2522 nvme_start_freeze(&dev->ctrl);
e43269e6 2523 }
302ad8cc
KB		 2524 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2525 pdev->error_state != pci_channel_io_normal);
c9d3bf88 2526 }
c21377f8 2527
302ad8cc
KB		 2528 /*
2529 * Give the controller a chance to complete all entered requests if
2530 * doing a safe shutdown.
2531 */
e43269e6
KB		 2532 if (!dead && shutdown && freeze)
2533 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
9a915a5b
JW		 2534
2535 nvme_stop_queues(&dev->ctrl);
87ad72a5 2536
64ee0ac0 2537 if (!dead && dev->ctrl.queue_count > 0) {
8fae268b 2538 nvme_disable_io_queues(dev);
a5cdb68c 2539 nvme_disable_admin_queue(dev, shutdown);
4d115420 2540 }
8fae268b
KB		 2541 nvme_suspend_io_queues(dev);
2542 nvme_suspend_queue(&dev->queues[0]);
b00a726a 2543 nvme_pci_disable(dev);
fa46c6fb 2544 nvme_reap_pending_cqes(dev);
07836e65 2545
e1958e65
ML		 2546 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2547 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
622b8b68
ML		 2548 blk_mq_tagset_wait_completed_request(&dev->tagset);
2549 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
302ad8cc
KB		 2550
2551 /*
2552 * The driver will not be starting up queues again if shutting down so
2553 * must flush all entered requests to their failed completion to avoid
2554 * deadlocking blk-mq hot-cpu notifier.
2555 */
c8e9e9b7 2556 if (shutdown) {
302ad8cc 2557 nvme_start_queues(&dev->ctrl);
c8e9e9b7
KB		 2558 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2559 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2560 }
77bf25ea 2561 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2562}
2563
c1ac9a4b
KB		 2564static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2565{
2566 if (!nvme_wait_reset(&dev->ctrl))
2567 return -EBUSY;
2568 nvme_dev_disable(dev, shutdown);
2569 return 0;
2570}
2571
091b6092
MW		 2572static int nvme_setup_prp_pools(struct nvme_dev *dev)
2573{
e75ec752 2574 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2575 NVME_CTRL_PAGE_SIZE,
2576 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2577 if (!dev->prp_page_pool)
2578 return -ENOMEM;
2579
99802a7a 2580 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2581 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2582 256, 256, 0);
2583 if (!dev->prp_small_pool) {
2584 dma_pool_destroy(dev->prp_page_pool);
2585 return -ENOMEM;
2586 }
091b6092
MW		 2587 return 0;
2588}
2589
2590static void nvme_release_prp_pools(struct nvme_dev *dev)
2591{
2592 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2593 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2594}
2595
770597ec
KB		 2596static void nvme_free_tagset(struct nvme_dev *dev)
2597{
2598 if (dev->tagset.tags)
2599 blk_mq_free_tag_set(&dev->tagset);
2600 dev->ctrl.tagset = NULL;
2601}
2602
1673f1f0 2603static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2604{
1673f1f0 2605 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2606
f9f38e33 2607 nvme_dbbuf_dma_free(dev);
770597ec 2608 nvme_free_tagset(dev);
1c63dc66
CH		 2609 if (dev->ctrl.admin_q)
2610 blk_put_queue(dev->ctrl.admin_q);
e286bcfc 2611 free_opal_dev(dev->ctrl.opal_dev);
943e942e 2612 mempool_destroy(dev->iod_mempool);
253fd4ac
IR		 2613 put_device(dev->dev);
2614 kfree(dev->queues);
5e82e952
KB		 2615 kfree(dev);
2616}
2617
7c1ce408 2618static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
f58944e2 2619{
c1ac9a4b
KB		 2620 /*
2621 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2622 * may be holding this pci_dev's device lock.
2623 */
2624 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
d22524a4 2625 nvme_get_ctrl(&dev->ctrl);
69d9a99c 2626 nvme_dev_disable(dev, false);
9f9cafc1 2627 nvme_kill_queues(&dev->ctrl);
03e0f3a6 2628 if (!queue_work(nvme_wq, &dev->remove_work))
f58944e2
KB		 2629 nvme_put_ctrl(&dev->ctrl);
2630}
2631
fd634f41 2632static void nvme_reset_work(struct work_struct *work)
5e82e952 2633{
d86c4d8e
CH		 2634 struct nvme_dev *dev =
2635 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2636 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2637 int result;
5e82e952 2638
7764656b
ZC		 2639 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2640 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2641 dev->ctrl.state);
e71afda4 2642 result = -ENODEV;
fd634f41 2643 goto out;
e71afda4 2644 }
5e82e952 2645
fd634f41
CH		 2646 /*
2647 * If we're called to reset a live controller first shut it down before
2648 * moving on.
2649 */
b00a726a 2650 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2651 nvme_dev_disable(dev, false);
d6135c3a 2652 nvme_sync_queues(&dev->ctrl);
5e82e952 2653
5c959d73 2654 mutex_lock(&dev->shutdown_lock);
b00a726a 2655 result = nvme_pci_enable(dev);
f0b50732 2656 if (result)
4726bcf3 2657 goto out_unlock;
f0b50732 2658
01ad0990 2659 result = nvme_pci_configure_admin_queue(dev);
f0b50732 2660 if (result)
4726bcf3 2661 goto out_unlock;
f0b50732 2662
0fb59cbc
KB		 2663 result = nvme_alloc_admin_tags(dev);
2664 if (result)
4726bcf3 2665 goto out_unlock;
b9afca3e 2666
943e942e
JA		 2667 /*
2668 * Limit the max command size to prevent iod->sg allocations going
2669 * over a single page.
2670 */
7637de31
CH		 2671 dev->ctrl.max_hw_sectors = min_t(u32,
2672 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
943e942e 2673 dev->ctrl.max_segments = NVME_MAX_SEGS;
a48bc520
CH		 2674
2675 /*
2676 * Don't limit the IOMMU merged segment size.
2677 */
2678 dma_set_max_seg_size(dev->dev, 0xffffffff);
3d2d861e 2679 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
a48bc520 2680
5c959d73
KB		 2681 mutex_unlock(&dev->shutdown_lock);
2682
2683 /*
2684 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2685 * initializing procedure here.
2686 */
2687 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2688 dev_warn(dev->ctrl.device,
2689 "failed to mark controller CONNECTING\n");
cee6c269 2690 result = -EBUSY;
5c959d73
KB		 2691 goto out;
2692 }
943e942e 2693
95093350
MG		 2694 /*
2695 * We do not support an SGL for metadata (yet), so we are limited to a
2696 * single integrity segment for the separate metadata pointer.
2697 */
2698 dev->ctrl.max_integrity_segments = 1;
2699
f21c4769 2700 result = nvme_init_ctrl_finish(&dev->ctrl);
ce4541f4 2701 if (result)
f58944e2 2702 goto out;
ce4541f4 2703
e286bcfc
SB		 2704 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2705 if (!dev->ctrl.opal_dev)
2706 dev->ctrl.opal_dev =
2707 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2708 else if (was_suspend)
2709 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2710 } else {
2711 free_opal_dev(dev->ctrl.opal_dev);
2712 dev->ctrl.opal_dev = NULL;
4f1244c8 2713 }
a98e58e5 2714
f9f38e33
HK		 2715 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2716 result = nvme_dbbuf_dma_alloc(dev);
2717 if (result)
2718 dev_warn(dev->dev,
2719 "unable to allocate dma for dbbuf\n");
2720 }
2721
9620cfba
CH		 2722 if (dev->ctrl.hmpre) {
2723 result = nvme_setup_host_mem(dev);
2724 if (result < 0)
2725 goto out;
2726 }
87ad72a5 2727
f0b50732 2728 result = nvme_setup_io_queues(dev);
badc34d4 2729 if (result)
f58944e2 2730 goto out;
f0b50732 2731
2659e57b
CH		 2732 /*
2733 * Keep the controller around but remove all namespaces if we don't have
2734 * any working I/O queue.
2735 */
3cf519b5 2736 if (dev->online_queues < 2) {
1b3c47c1 2737 dev_warn(dev->ctrl.device, "IO queues not created\n");
3b24774e 2738 nvme_kill_queues(&dev->ctrl);
5bae7f73 2739 nvme_remove_namespaces(&dev->ctrl);
770597ec 2740 nvme_free_tagset(dev);
3cf519b5 2741 } else {
25646264 2742 nvme_start_queues(&dev->ctrl);
302ad8cc 2743 nvme_wait_freeze(&dev->ctrl);
5d02a5c1 2744 nvme_dev_add(dev);
302ad8cc 2745 nvme_unfreeze(&dev->ctrl);
3cf519b5
CH		 2746 }
2747
2b1b7e78
JW		 2748 /*
2749 * If only admin queue live, keep it to do further investigation or
2750 * recovery.
2751 */
5d02a5c1 2752 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2753 dev_warn(dev->ctrl.device,
5d02a5c1 2754 "failed to mark controller live state\n");
e71afda4 2755 result = -ENODEV;
bb8d261e
CH		 2756 goto out;
2757 }
92911a55 2758
0521905e
KB		 2759 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2760 &nvme_pci_attr_group))
2761 dev->attrs_added = true;
2762
d09f2b45 2763 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2764 return;
f0b50732 2765
4726bcf3
KB		 2766 out_unlock:
2767 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2768 out:
7c1ce408
CK		 2769 if (result)
2770 dev_warn(dev->ctrl.device,
2771 "Removing after probe failure status: %d\n", result);
2772 nvme_remove_dead_ctrl(dev);
f0b50732
KB		 2773}
2774
5c8809e6 2775static void nvme_remove_dead_ctrl_work(struct work_struct *work)
9a6b9458 2776{
5c8809e6 2777 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
e75ec752 2778 struct pci_dev *pdev = to_pci_dev(dev->dev);
9a6b9458
KB		 2779
2780 if (pci_get_drvdata(pdev))
921920ab 2781 device_release_driver(&pdev->dev);
1673f1f0 2782 nvme_put_ctrl(&dev->ctrl);
9a6b9458
KB		 2783}
2784
1c63dc66 2785static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2786{
1c63dc66 2787 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2788 return 0;
9ca97374
TH		 2789}
2790
5fd4ce1b 2791static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2792{
5fd4ce1b
CH		 2793 writel(val, to_nvme_dev(ctrl)->bar + off);
2794 return 0;
2795}
4cc06521 2796
7fd8930f
CH		 2797static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2798{
3a8ecc93 2799 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2800 return 0;
4cc06521
KB		 2801}
2802
97c12223
KB		 2803static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2804{
2805 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2806
2db24e4a 2807 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2808}
2809
1c63dc66 2810static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2811 .name = "pcie",
e439bb12 2812 .module = THIS_MODULE,
e0596ab2
LG		 2813 .flags = NVME_F_METADATA_SUPPORTED |
2814 NVME_F_PCI_P2PDMA,
1c63dc66 2815 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2816 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2817 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2818 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2819 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2820 .get_address = nvme_pci_get_address,
1c63dc66 2821};
4cc06521 2822
b00a726a
KB		 2823static int nvme_dev_map(struct nvme_dev *dev)
2824{
b00a726a
KB		 2825 struct pci_dev *pdev = to_pci_dev(dev->dev);
2826
a1f447b3 2827 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2828 return -ENODEV;
2829
97f6ef64 2830 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2831 goto release;
2832
9fa196e7 2833 return 0;
b00a726a 2834 release:
9fa196e7
MG		 2835 pci_release_mem_regions(pdev);
2836 return -ENODEV;
b00a726a
KB		 2837}
2838
8427bbc2 2839static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2840{
2841 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2842 /*
2843 * Several Samsung devices seem to drop off the PCIe bus
2844 * randomly when APST is on and uses the deepest sleep state.
2845 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2846 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2847 * 950 PRO 256GB", but it seems to be restricted to two Dell
2848 * laptops.
2849 */
2850 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2851 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2852 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2853 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2854 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2855 /*
2856 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2857 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2858 * within few minutes after bootup on a Coffee Lake board -
2859 * ASUS PRIME Z370-A
8427bbc2
KHF		 2860 */
2861 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2862 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2863 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2864 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2865 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2866 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2867 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2868 /*
2869 * Forcing to use host managed nvme power settings for
2870 * lowest idle power with quick resume latency on
2871 * Samsung and Toshiba SSDs based on suspend behavior
2872 * on Coffee Lake board for LENOVO C640
2873 */
2874 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2875 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2876 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2877 }
2878
2879 return 0;
2880}
2881
18119775
KB		 2882static void nvme_async_probe(void *data, async_cookie_t cookie)
2883{
2884 struct nvme_dev *dev = data;
80f513b5 2885
bd46a906 2886 flush_work(&dev->ctrl.reset_work);
18119775 2887 flush_work(&dev->ctrl.scan_work);
80f513b5 2888 nvme_put_ctrl(&dev->ctrl);
18119775
KB		 2889}
2890
8d85fce7 2891static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2892{
a4aea562 2893 int node, result = -ENOMEM;
b60503ba 2894 struct nvme_dev *dev;
ff5350a8 2895 unsigned long quirks = id->driver_data;
943e942e 2896 size_t alloc_size;
b60503ba 2897
a4aea562
MB		 2898 node = dev_to_node(&pdev->dev);
2899 if (node == NUMA_NO_NODE)
2fa84351 2900 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2901
2902 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2903 if (!dev)
2904 return -ENOMEM;
147b27e4 2905
2a5bcfdd
WZ		 2906 dev->nr_write_queues = write_queues;
2907 dev->nr_poll_queues = poll_queues;
2908 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2909 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2910 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba
MW		 2911 if (!dev->queues)
2912 goto free;
2913
e75ec752 2914 dev->dev = get_device(&pdev->dev);
9a6b9458 2915 pci_set_drvdata(pdev, dev);
1c63dc66 2916
b00a726a
KB		 2917 result = nvme_dev_map(dev);
2918 if (result)
b00c9b7a 2919 goto put_pci;
b00a726a 2920
d86c4d8e 2921 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
5c8809e6 2922 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
77bf25ea 2923 mutex_init(&dev->shutdown_lock);
b60503ba 2924
091b6092
MW		 2925 result = nvme_setup_prp_pools(dev);
2926 if (result)
b00c9b7a 2927 goto unmap;
4cc06521 2928
8427bbc2 2929 quirks |= check_vendor_combination_bug(pdev);
ff5350a8 2930
2744d7a0 2931 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2932 /*
2933 * Some systems use a bios work around to ask for D3 on
2934 * platforms that support kernel managed suspend.
2935 */
2936 dev_info(&pdev->dev,
2937 "platform quirk: setting simple suspend\n");
2938 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2939 }
2940
943e942e
JA		 2941 /*
2942 * Double check that our mempool alloc size will cover the biggest
2943 * command we support.
2944 */
b13c6393 2945 alloc_size = nvme_pci_iod_alloc_size();
943e942e
JA		 2946 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2947
2948 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2949 mempool_kfree,
2950 (void *) alloc_size,
2951 GFP_KERNEL, node);
2952 if (!dev->iod_mempool) {
2953 result = -ENOMEM;
2954 goto release_pools;
2955 }
2956
b6e44b4c
KB		 2957 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2958 quirks);
2959 if (result)
2960 goto release_mempool;
2961
1b3c47c1
SG		 2962 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2963
bd46a906 2964 nvme_reset_ctrl(&dev->ctrl);
18119775 2965 async_schedule(nvme_async_probe, dev);
4caff8fc 2966
b60503ba
MW		 2967 return 0;
2968
b6e44b4c
KB		 2969 release_mempool:
2970 mempool_destroy(dev->iod_mempool);
0877cb0d 2971 release_pools:
091b6092 2972 nvme_release_prp_pools(dev);
b00c9b7a
CJ		 2973 unmap:
2974 nvme_dev_unmap(dev);
a96d4f5c 2975 put_pci:
e75ec752 2976 put_device(dev->dev);
b60503ba
MW		 2977 free:
2978 kfree(dev->queues);
b60503ba
MW		 2979 kfree(dev);
2980 return result;
2981}
2982
775755ed 2983static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 2984{
a6739479 2985 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2986
2987 /*
2988 * We don't need to check the return value from waiting for the reset
2989 * state as pci_dev device lock is held, making it impossible to race
2990 * with ->remove().
2991 */
2992 nvme_disable_prepare_reset(dev, false);
2993 nvme_sync_queues(&dev->ctrl);
775755ed 2994}
f0d54a54 2995
775755ed
CH		 2996static void nvme_reset_done(struct pci_dev *pdev)
2997{
f263fbb8 2998 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 2999
3000 if (!nvme_try_sched_reset(&dev->ctrl))
3001 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3002}
3003
09ece142
KB		 3004static void nvme_shutdown(struct pci_dev *pdev)
3005{
3006 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3007
c1ac9a4b 3008 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3009}
3010
0521905e
KB		 3011static void nvme_remove_attrs(struct nvme_dev *dev)
3012{
3013 if (dev->attrs_added)
3014 sysfs_remove_group(&dev->ctrl.device->kobj,
3015 &nvme_pci_attr_group);
3016}
3017
f58944e2
KB		 3018/*
3019 * The driver's remove may be called on a device in a partially initialized
3020 * state. This function must not have any dependencies on the device state in
3021 * order to proceed.
3022 */
8d85fce7 3023static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3024{
3025 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3026
bb8d261e 3027 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3028 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3029
6db28eda 3030 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3031 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3032 nvme_dev_disable(dev, true);
6db28eda 3033 }
0ff9d4e1 3034
d86c4d8e 3035 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3036 nvme_stop_ctrl(&dev->ctrl);
3037 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3038 nvme_dev_disable(dev, true);
0521905e 3039 nvme_remove_attrs(dev);
87ad72a5 3040 nvme_free_host_mem(dev);
a4aea562 3041 nvme_dev_remove_admin(dev);
a1a5ef99 3042 nvme_free_queues(dev, 0);
9a6b9458 3043 nvme_release_prp_pools(dev);
b00a726a 3044 nvme_dev_unmap(dev);
726612b6 3045 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3046}
3047
671a6018 3048#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3049static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3050{
3051 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3052}
3053
3054static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3055{
3056 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3057}
3058
3059static int nvme_resume(struct device *dev)
3060{
3061 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3062 struct nvme_ctrl *ctrl = &ndev->ctrl;
3063
4eaefe8c 3064 if (ndev->last_ps == U32_MAX ||
d916b1be 3065 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
c1ac9a4b 3066 return nvme_try_sched_reset(&ndev->ctrl);
d916b1be
KB		 3067 return 0;
3068}
3069
cd638946
KB		 3070static int nvme_suspend(struct device *dev)
3071{
3072 struct pci_dev *pdev = to_pci_dev(dev);
3073 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3074 struct nvme_ctrl *ctrl = &ndev->ctrl;
3075 int ret = -EBUSY;
3076
4eaefe8c
RW		 3077 ndev->last_ps = U32_MAX;
3078
d916b1be
KB		 3079 /*
3080 * The platform does not remove power for a kernel managed suspend so
3081 * use host managed nvme power settings for lowest idle power if
3082 * possible. This should have quicker resume latency than a full device
3083 * shutdown. But if the firmware is involved after the suspend or the
3084 * device does not support any non-default power states, shut down the
3085 * device fully.
4eaefe8c
RW		 3086 *
3087 * If ASPM is not enabled for the device, shut down the device and allow
3088 * the PCI bus layer to put it into D3 in order to take the PCIe link
3089 * down, so as to allow the platform to achieve its minimum low-power
3090 * state (which may not be possible if the link is up).
b97120b1
CH		 3091 *
3092 * If a host memory buffer is enabled, shut down the device as the NVMe
3093 * specification allows the device to access the host memory buffer in
3094 * host DRAM from all power states, but hosts will fail access to DRAM
3095 * during S3.
d916b1be 3096 */
4eaefe8c 3097 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3098 !pcie_aspm_enabled(pdev) ||
b97120b1 3099 ndev->nr_host_mem_descs ||
c1ac9a4b
KB		 3100 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3101 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3102
3103 nvme_start_freeze(ctrl);
3104 nvme_wait_freeze(ctrl);
3105 nvme_sync_queues(ctrl);
3106
5d02a5c1 3107 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3108 goto unfreeze;
3109
d916b1be
KB		 3110 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3111 if (ret < 0)
3112 goto unfreeze;
3113
7cbb5c6f
ML		 3114 /*
3115 * A saved state prevents pci pm from generically controlling the
3116 * device's power. If we're using protocol specific settings, we don't
3117 * want pci interfering.
3118 */
3119 pci_save_state(pdev);
3120
d916b1be
KB		 3121 ret = nvme_set_power_state(ctrl, ctrl->npss);
3122 if (ret < 0)
3123 goto unfreeze;
3124
3125 if (ret) {
7cbb5c6f
ML		 3126 /* discard the saved state */
3127 pci_load_saved_state(pdev, NULL);
3128
d916b1be
KB		 3129 /*
3130 * Clearing npss forces a controller reset on resume. The
05d3046f 3131 * correct value will be rediscovered then.
d916b1be 3132 */
c1ac9a4b 3133 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3134 ctrl->npss = 0;
d916b1be 3135 }
d916b1be
KB		 3136unfreeze:
3137 nvme_unfreeze(ctrl);
3138 return ret;
3139}
3140
3141static int nvme_simple_suspend(struct device *dev)
3142{
3143 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3144
c1ac9a4b 3145 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3146}
3147
d916b1be 3148static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3149{
3150 struct pci_dev *pdev = to_pci_dev(dev);
3151 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3152
c1ac9a4b 3153 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3154}
3155
21774222 3156static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3157 .suspend = nvme_suspend,
3158 .resume = nvme_resume,
3159 .freeze = nvme_simple_suspend,
3160 .thaw = nvme_simple_resume,
3161 .poweroff = nvme_simple_suspend,
3162 .restore = nvme_simple_resume,
3163};
3164#endif /* CONFIG_PM_SLEEP */
b60503ba 3165
a0a3408e
KB		 3166static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3167 pci_channel_state_t state)
3168{
3169 struct nvme_dev *dev = pci_get_drvdata(pdev);
3170
3171 /*
3172 * A frozen channel requires a reset. When detected, this method will
3173 * shutdown the controller to quiesce. The controller will be restarted
3174 * after the slot reset through driver's slot_reset callback.
3175 */
a0a3408e
KB		 3176 switch (state) {
3177 case pci_channel_io_normal:
3178 return PCI_ERS_RESULT_CAN_RECOVER;
3179 case pci_channel_io_frozen:
d011fb31
KB		 3180 dev_warn(dev->ctrl.device,
3181 "frozen state error detected, reset controller\n");
a5cdb68c 3182 nvme_dev_disable(dev, false);
a0a3408e
KB		 3183 return PCI_ERS_RESULT_NEED_RESET;
3184 case pci_channel_io_perm_failure:
d011fb31
KB		 3185 dev_warn(dev->ctrl.device,
3186 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3187 return PCI_ERS_RESULT_DISCONNECT;
3188 }
3189 return PCI_ERS_RESULT_NEED_RESET;
3190}
3191
3192static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3193{
3194 struct nvme_dev *dev = pci_get_drvdata(pdev);
3195
1b3c47c1 3196 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3197 pci_restore_state(pdev);
d86c4d8e 3198 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3199 return PCI_ERS_RESULT_RECOVERED;
3200}
3201
3202static void nvme_error_resume(struct pci_dev *pdev)
3203{
72cd4cc2
KB		 3204 struct nvme_dev *dev = pci_get_drvdata(pdev);
3205
3206 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3207}
3208
1d352035 3209static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3210 .error_detected = nvme_error_detected,
b60503ba
MW		 3211 .slot_reset = nvme_slot_reset,
3212 .resume = nvme_error_resume,
775755ed
CH		 3213 .reset_prepare = nvme_reset_prepare,
3214 .reset_done = nvme_reset_done,
b60503ba
MW		 3215};
3216
6eb0d698 3217static const struct pci_device_id nvme_id_table[] = {
972b13e2 3218 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3219 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3220 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3221 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3222 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3223 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3224 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3225 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3226 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3227 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3228 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3229 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3230 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3231 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3232 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3233 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3234 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3235 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3236 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3237 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e
CH		 3238 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3239 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
5bedd3af
CH		 3240 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3241 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
0302ae60 3242 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3243 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3244 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3245 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3246 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3247 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3248 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3249 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3250 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3251 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3252 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3253 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3254 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3255 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3256 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
c9e95c39
CS		 3257 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3258 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
6e6a6828
PT		 3259 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3260 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3261 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
08b903b5
MN		 3262 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3263 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
f03e42c6
GC		 3264 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3265 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3266 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
5611ec2b
KHF		 3267 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3268 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
02ca079c
KHF		 3269 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3270 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3271 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3272 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3273 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3274 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3275 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3276 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4bdf2603
FS		 3277 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3278 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3279 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3280 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3281 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3282 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3283 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3284 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3285 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3286 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3287 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3288 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3289 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3290 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3291 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3292 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3293 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04
BH		 3294 NVME_QUIRK_128_BYTES_SQES |
3295 NVME_QUIRK_SHARED_TAGS },
0b85f59d
AS		 3296
3297 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3298 { 0, }
3299};
3300MODULE_DEVICE_TABLE(pci, nvme_id_table);
3301
3302static struct pci_driver nvme_driver = {
3303 .name = "nvme",
3304 .id_table = nvme_id_table,
3305 .probe = nvme_probe,
8d85fce7 3306 .remove = nvme_remove,
09ece142 3307 .shutdown = nvme_shutdown,
d916b1be 3308#ifdef CONFIG_PM_SLEEP
cd638946
KB		 3309 .driver = {
3310 .pm = &nvme_dev_pm_ops,
3311 },
d916b1be 3312#endif
74d986ab 3313 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3314 .err_handler = &nvme_err_handler,
3315};
3316
3317static int __init nvme_init(void)
3318{
81101540
CH		 3319 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3320 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3321 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3322 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
17c33167 3323
9a6327d2 3324 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3325}
3326
3327static void __exit nvme_exit(void)
3328{
3329 pci_unregister_driver(&nvme_driver);
03e0f3a6 3330 flush_workqueue(nvme_wq);
b60503ba
MW		 3331}
3332
3333MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3334MODULE_LICENSE("GPL");
c78b4713 3335MODULE_VERSION("1.0");
b60503ba
MW		 3336module_init(nvme_init);
3337module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)