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nvme-pci: remove SGL segment descriptors
[linux-2.6-block.git] / drivers / nvme / host / pci.c
CommitLineData
5f37396d 1// SPDX-License-Identifier: GPL-2.0
b60503ba
MW		 2/*
3 * NVM Express device driver
6eb0d698 4 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 5 */
6
df4f9bc4 7#include <linux/acpi.h>
a0a3408e 8#include <linux/aer.h>
18119775 9#include <linux/async.h>
b60503ba 10#include <linux/blkdev.h>
a4aea562 11#include <linux/blk-mq.h>
dca51e78 12#include <linux/blk-mq-pci.h>
fe45e630 13#include <linux/blk-integrity.h>
ff5350a8 14#include <linux/dmi.h>
b60503ba
MW		 15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
99722c8a 18#include <linux/kstrtox.h>
dc90f084 19#include <linux/memremap.h>
b60503ba
MW		 20#include <linux/mm.h>
21#include <linux/module.h>
77bf25ea 22#include <linux/mutex.h>
d0877473 23#include <linux/once.h>
b60503ba 24#include <linux/pci.h>
d916b1be 25#include <linux/suspend.h>
e1e5e564 26#include <linux/t10-pi.h>
b60503ba 27#include <linux/types.h>
2f8e2c87 28#include <linux/io-64-nonatomic-lo-hi.h>
20d3bb92 29#include <linux/io-64-nonatomic-hi-lo.h>
a98e58e5 30#include <linux/sed-opal.h>
0f238ff5 31#include <linux/pci-p2pdma.h>
797a796a 32
604c01d5 33#include "trace.h"
f11bb3e2
CH		 34#include "nvme.h"
35
c1e0cc7e 36#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
8a1d09a6 37#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
c965809c 38
84173423 39#define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
9d43cf64 40
943e942e
JA		 41/*
42 * These can be higher, but we need to ensure that any command doesn't
43 * require an sg allocation that needs more than a page of data.
44 */
45#define NVME_MAX_KB_SZ 4096
46#define NVME_MAX_SEGS 127
47
58ffacb5 48static int use_threaded_interrupts;
2e21e445 49module_param(use_threaded_interrupts, int, 0444);
58ffacb5 50
8ffaadf7 51static bool use_cmb_sqes = true;
69f4eb9f 52module_param(use_cmb_sqes, bool, 0444);
8ffaadf7
JD		 53MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
87ad72a5
CH		 55static unsigned int max_host_mem_size_mb = 128;
56module_param(max_host_mem_size_mb, uint, 0444);
57MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
1fa6aead 59
a7a7cbe3
CK		 60static unsigned int sgl_threshold = SZ_32K;
61module_param(sgl_threshold, uint, 0644);
62MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
27453b45
SG		 66#define NVME_PCI_MIN_QUEUE_SIZE 2
67#define NVME_PCI_MAX_QUEUE_SIZE 4095
b27c1e68 68static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
61f3b896 71 .get = param_get_uint,
b27c1e68 72};
73
61f3b896 74static unsigned int io_queue_depth = 1024;
b27c1e68 75module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
27453b45 76MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
b27c1e68 77
9c9e76d5
WZ		 78static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79{
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87}
88
89static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92};
93
3f68baf7 94static unsigned int write_queues;
9c9e76d5 95module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
3b6592f7
JA		 96MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
3f68baf7 100static unsigned int poll_queues;
9c9e76d5 101module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
4b04cc6a
JA		 102MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
df4f9bc4
DB		 104static bool noacpi;
105module_param(noacpi, bool, 0444);
106MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
1c63dc66
CH		 108struct nvme_dev;
109struct nvme_queue;
b3fffdef 110
a5cdb68c 111static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
7d879c90 112static void nvme_delete_io_queues(struct nvme_dev *dev);
d4b4ff8e 113
1c63dc66
CH		 114/*
115 * Represents an NVM Express device. Each nvme_dev is a PCI function.
116 */
117struct nvme_dev {
147b27e4 118 struct nvme_queue *queues;
1c63dc66
CH		 119 struct blk_mq_tag_set tagset;
120 struct blk_mq_tag_set admin_tagset;
121 u32 __iomem *dbs;
122 struct device *dev;
123 struct dma_pool *prp_page_pool;
124 struct dma_pool *prp_small_pool;
1c63dc66
CH		 125 unsigned online_queues;
126 unsigned max_qid;
e20ba6e1 127 unsigned io_queues[HCTX_MAX_TYPES];
22b55601 128 unsigned int num_vecs;
7442ddce 129 u32 q_depth;
c1e0cc7e 130 int io_sqes;
1c63dc66 131 u32 db_stride;
1c63dc66 132 void __iomem *bar;
97f6ef64 133 unsigned long bar_mapped_size;
77bf25ea 134 struct mutex shutdown_lock;
1c63dc66 135 bool subsystem;
1c63dc66 136 u64 cmb_size;
0f238ff5 137 bool cmb_use_sqes;
1c63dc66 138 u32 cmbsz;
202021c1 139 u32 cmbloc;
1c63dc66 140 struct nvme_ctrl ctrl;
d916b1be 141 u32 last_ps;
a5df5e79 142 bool hmb;
87ad72a5 143
943e942e
JA		 144 mempool_t *iod_mempool;
145
87ad72a5 146 /* shadow doorbell buffer support: */
b5f96cb7 147 __le32 *dbbuf_dbs;
f9f38e33 148 dma_addr_t dbbuf_dbs_dma_addr;
b5f96cb7 149 __le32 *dbbuf_eis;
f9f38e33 150 dma_addr_t dbbuf_eis_dma_addr;
87ad72a5
CH		 151
152 /* host memory buffer support: */
153 u64 host_mem_size;
154 u32 nr_host_mem_descs;
4033f35d 155 dma_addr_t host_mem_descs_dma;
87ad72a5
CH		 156 struct nvme_host_mem_buf_desc *host_mem_descs;
157 void **host_mem_desc_bufs;
2a5bcfdd
WZ		 158 unsigned int nr_allocated_queues;
159 unsigned int nr_write_queues;
160 unsigned int nr_poll_queues;
4d115420 161};
1fa6aead 162
b27c1e68 163static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
164{
27453b45
SG		 165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
b27c1e68 167}
168
f9f38e33
HK		 169static inline unsigned int sq_idx(unsigned int qid, u32 stride)
170{
171 return qid * 2 * stride;
172}
173
174static inline unsigned int cq_idx(unsigned int qid, u32 stride)
175{
176 return (qid * 2 + 1) * stride;
177}
178
1c63dc66
CH		 179static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
180{
181 return container_of(ctrl, struct nvme_dev, ctrl);
182}
183
b60503ba
MW		 184/*
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
187 */
188struct nvme_queue {
091b6092 189 struct nvme_dev *dev;
1ab0cd69 190 spinlock_t sq_lock;
c1e0cc7e 191 void *sq_cmds;
3a7afd8e
CH		 192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
74943d45 194 struct nvme_completion *cqes;
b60503ba
MW		 195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
b60503ba 197 u32 __iomem *q_db;
7442ddce 198 u32 q_depth;
7c349dde 199 u16 cq_vector;
b60503ba 200 u16 sq_tail;
38210800 201 u16 last_sq_tail;
b60503ba 202 u16 cq_head;
c30341dc 203 u16 qid;
e9539f47 204 u8 cq_phase;
c1e0cc7e 205 u8 sqes;
4e224106
CH		 206 unsigned long flags;
207#define NVMEQ_ENABLED 0
63223078 208#define NVMEQ_SQ_CMB 1
d1ed6aa1 209#define NVMEQ_DELETE_ERROR 2
7c349dde 210#define NVMEQ_POLLED 3
b5f96cb7
KJ		 211 __le32 *dbbuf_sq_db;
212 __le32 *dbbuf_cq_db;
213 __le32 *dbbuf_sq_ei;
214 __le32 *dbbuf_cq_ei;
d1ed6aa1 215 struct completion delete_done;
b60503ba
MW		 216};
217
71bd150c 218/*
9b048119
CH		 219 * The nvme_iod describes the data in an I/O.
220 *
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
71bd150c
CH		 223 */
224struct nvme_iod {
d49187e9 225 struct nvme_request req;
af7fae85 226 struct nvme_command cmd;
a7a7cbe3 227 bool use_sgl;
52da4f3f 228 bool aborted;
c372cdd1
KB		 229 s8 nr_allocations; /* PRP list pool allocations. 0 means small
230 pool in use */
dff824b2 231 unsigned int dma_len; /* length of single DMA segment mapping */
c4c22c52 232 dma_addr_t first_dma;
783b94bd 233 dma_addr_t meta_dma;
91fb2b60 234 struct sg_table sgt;
b60503ba
MW		 235};
236
2a5bcfdd 237static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
3b6592f7 238{
2a5bcfdd 239 return dev->nr_allocated_queues * 8 * dev->db_stride;
f9f38e33
HK		 240}
241
65a54646 242static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
f9f38e33 243{
2a5bcfdd 244 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33 245
65a54646
CH		 246 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
247 return;
248
58847f12
KB		 249 if (dev->dbbuf_dbs) {
250 /*
251 * Clear the dbbuf memory so the driver doesn't observe stale
252 * values from the previous instantiation.
253 */
254 memset(dev->dbbuf_dbs, 0, mem_size);
255 memset(dev->dbbuf_eis, 0, mem_size);
65a54646 256 return;
58847f12 257 }
f9f38e33
HK		 258
259 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
260 &dev->dbbuf_dbs_dma_addr,
261 GFP_KERNEL);
262 if (!dev->dbbuf_dbs)
65a54646 263 goto fail;
f9f38e33
HK		 264 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
265 &dev->dbbuf_eis_dma_addr,
266 GFP_KERNEL);
65a54646
CH		 267 if (!dev->dbbuf_eis)
268 goto fail_free_dbbuf_dbs;
269 return;
f9f38e33 270
65a54646
CH		 271fail_free_dbbuf_dbs:
272 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
273 dev->dbbuf_dbs_dma_addr);
274 dev->dbbuf_dbs = NULL;
275fail:
276 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
f9f38e33
HK		 277}
278
279static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
280{
2a5bcfdd 281 unsigned int mem_size = nvme_dbbuf_size(dev);
f9f38e33
HK		 282
283 if (dev->dbbuf_dbs) {
284 dma_free_coherent(dev->dev, mem_size,
285 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
286 dev->dbbuf_dbs = NULL;
287 }
288 if (dev->dbbuf_eis) {
289 dma_free_coherent(dev->dev, mem_size,
290 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
291 dev->dbbuf_eis = NULL;
292 }
293}
294
295static void nvme_dbbuf_init(struct nvme_dev *dev,
296 struct nvme_queue *nvmeq, int qid)
297{
298 if (!dev->dbbuf_dbs || !qid)
299 return;
300
301 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
302 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
303 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
304 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
305}
306
0f0d2c87
MI		 307static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
308{
309 if (!nvmeq->qid)
310 return;
311
312 nvmeq->dbbuf_sq_db = NULL;
313 nvmeq->dbbuf_cq_db = NULL;
314 nvmeq->dbbuf_sq_ei = NULL;
315 nvmeq->dbbuf_cq_ei = NULL;
316}
317
f9f38e33
HK		 318static void nvme_dbbuf_set(struct nvme_dev *dev)
319{
f66e2804 320 struct nvme_command c = { };
0f0d2c87 321 unsigned int i;
f9f38e33
HK		 322
323 if (!dev->dbbuf_dbs)
324 return;
325
f9f38e33
HK		 326 c.dbbuf.opcode = nvme_admin_dbbuf;
327 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
328 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
329
330 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
9bdcfb10 331 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
f9f38e33
HK		 332 /* Free memory and continue on */
333 nvme_dbbuf_dma_free(dev);
0f0d2c87
MI		 334
335 for (i = 1; i <= dev->online_queues; i++)
336 nvme_dbbuf_free(&dev->queues[i]);
f9f38e33
HK		 337 }
338}
339
340static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
341{
342 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
343}
344
345/* Update dbbuf and return true if an MMIO is required */
b5f96cb7
KJ		 346static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
347 volatile __le32 *dbbuf_ei)
f9f38e33
HK		 348{
349 if (dbbuf_db) {
b5f96cb7 350 u16 old_value, event_idx;
f9f38e33
HK		 351
352 /*
353 * Ensure that the queue is written before updating
354 * the doorbell in memory
355 */
356 wmb();
357
b5f96cb7
KJ		 358 old_value = le32_to_cpu(*dbbuf_db);
359 *dbbuf_db = cpu_to_le32(value);
f9f38e33 360
f1ed3df2
MW		 361 /*
362 * Ensure that the doorbell is updated before reading the event
363 * index from memory. The controller needs to provide similar
364 * ordering to ensure the envent index is updated before reading
365 * the doorbell.
366 */
367 mb();
368
b5f96cb7
KJ		 369 event_idx = le32_to_cpu(*dbbuf_ei);
370 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
f9f38e33
HK		 371 return false;
372 }
373
374 return true;
b60503ba
MW		 375}
376
ac3dd5bd
JA		 377/*
378 * Will slightly overestimate the number of pages needed. This is OK
379 * as it only leads to a small amount of wasted memory for the lifetime of
380 * the I/O.
381 */
b13c6393 382static int nvme_pci_npages_prp(void)
ac3dd5bd 383{
c89a529e
KB		 384 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
385 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
84173423 386 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
ac3dd5bd
JA		 387}
388
a7a7cbe3
CK		 389/*
390 * Calculates the number of pages needed for the SGL segments. For example a 4k
391 * page can accommodate 256 SGL descriptors.
392 */
b13c6393 393static int nvme_pci_npages_sgl(void)
ac3dd5bd 394{
b13c6393 395 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
84173423 396 NVME_CTRL_PAGE_SIZE);
f4800d6d 397}
ac3dd5bd 398
a4aea562
MB		 399static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
400 unsigned int hctx_idx)
e85248e5 401{
0da7feaa 402 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 403 struct nvme_queue *nvmeq = &dev->queues[0];
a4aea562 404
42483228
KB		 405 WARN_ON(hctx_idx != 0);
406 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
42483228 407
a4aea562
MB		 408 hctx->driver_data = nvmeq;
409 return 0;
e85248e5
MW		 410}
411
a4aea562
MB		 412static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
413 unsigned int hctx_idx)
b60503ba 414{
0da7feaa 415 struct nvme_dev *dev = to_nvme_dev(data);
147b27e4 416 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
a4aea562 417
42483228 418 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
a4aea562
MB		 419 hctx->driver_data = nvmeq;
420 return 0;
b60503ba
MW		 421}
422
e559398f
CH		 423static int nvme_pci_init_request(struct blk_mq_tag_set *set,
424 struct request *req, unsigned int hctx_idx,
425 unsigned int numa_node)
b60503ba 426{
0da7feaa 427 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
f4800d6d 428 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
59e29ce6
SG		 429
430 nvme_req(req)->ctrl = &dev->ctrl;
f4b9e6c9 431 nvme_req(req)->cmd = &iod->cmd;
a4aea562
MB		 432 return 0;
433}
434
3b6592f7
JA		 435static int queue_irq_offset(struct nvme_dev *dev)
436{
437 /* if we have more than 1 vec, admin queue offsets us by 1 */
438 if (dev->num_vecs > 1)
439 return 1;
440
441 return 0;
442}
443
a4e1d0b7 444static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
dca51e78 445{
0da7feaa 446 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
3b6592f7
JA		 447 int i, qoff, offset;
448
449 offset = queue_irq_offset(dev);
450 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 struct blk_mq_queue_map *map = &set->map[i];
452
453 map->nr_queues = dev->io_queues[i];
454 if (!map->nr_queues) {
e20ba6e1 455 BUG_ON(i == HCTX_TYPE_DEFAULT);
7e849dd9 456 continue;
3b6592f7
JA		 457 }
458
4b04cc6a
JA		 459 /*
460 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 * affinity), so use the regular blk-mq cpu mapping
462 */
3b6592f7 463 map->queue_offset = qoff;
cb9e0e50 464 if (i != HCTX_TYPE_POLL && offset)
4b04cc6a
JA		 465 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
466 else
467 blk_mq_map_queues(map);
3b6592f7
JA		 468 qoff += map->nr_queues;
469 offset += map->nr_queues;
470 }
dca51e78
CH		 471}
472
38210800
KB		 473/*
474 * Write sq tail if we are asked to, or if the next command would wrap.
475 */
476static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
04f3eafd 477{
38210800
KB		 478 if (!write_sq) {
479 u16 next_tail = nvmeq->sq_tail + 1;
480
481 if (next_tail == nvmeq->q_depth)
482 next_tail = 0;
483 if (next_tail != nvmeq->last_sq_tail)
484 return;
485 }
486
04f3eafd
JA		 487 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
488 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
489 writel(nvmeq->sq_tail, nvmeq->q_db);
38210800 490 nvmeq->last_sq_tail = nvmeq->sq_tail;
04f3eafd
JA		 491}
492
3233b94c
JA		 493static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
494 struct nvme_command *cmd)
b60503ba 495{
c1e0cc7e 496 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
3233b94c 497 absolute_pointer(cmd), sizeof(*cmd));
90ea5ca4
CH		 498 if (++nvmeq->sq_tail == nvmeq->q_depth)
499 nvmeq->sq_tail = 0;
04f3eafd
JA		 500}
501
502static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
503{
504 struct nvme_queue *nvmeq = hctx->driver_data;
505
506 spin_lock(&nvmeq->sq_lock);
38210800
KB		 507 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
508 nvme_write_sq_db(nvmeq, true);
90ea5ca4 509 spin_unlock(&nvmeq->sq_lock);
b60503ba
MW		 510}
511
a7a7cbe3 512static void **nvme_pci_iod_list(struct request *req)
b60503ba 513{
f4800d6d 514 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
91fb2b60 515 return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req));
b60503ba
MW		 516}
517
955b1b5a
MI		 518static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
519{
a53232cb 520 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
20469a37 521 int nseg = blk_rq_nr_phys_segments(req);
955b1b5a
MI		 522 unsigned int avg_seg_size;
523
20469a37 524 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
955b1b5a 525
253a0b76 526 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
955b1b5a 527 return false;
a53232cb 528 if (!nvmeq->qid)
955b1b5a
MI		 529 return false;
530 if (!sgl_threshold || avg_seg_size < sgl_threshold)
531 return false;
532 return true;
533}
534
9275c206 535static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
b60503ba 536{
6c3c05b0 537 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
9275c206
CH		 538 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
539 dma_addr_t dma_addr = iod->first_dma;
eca18b23 540 int i;
eca18b23 541
c372cdd1 542 for (i = 0; i < iod->nr_allocations; i++) {
9275c206
CH		 543 __le64 *prp_list = nvme_pci_iod_list(req)[i];
544 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
545
546 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
547 dma_addr = next_dma_addr;
7fe07d14 548 }
9275c206 549}
dff824b2 550
9275c206
CH		 551static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
552{
553 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3 554
9275c206
CH		 555 if (iod->dma_len) {
556 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
557 rq_dma_dir(req));
558 return;
eca18b23 559 }
ac3dd5bd 560
91fb2b60
LG		 561 WARN_ON_ONCE(!iod->sgt.nents);
562
563 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
9275c206 564
c372cdd1 565 if (iod->nr_allocations == 0)
9275c206
CH		 566 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
567 iod->first_dma);
568 else if (iod->use_sgl)
01df742d
KB		 569 dma_pool_free(dev->prp_page_pool, nvme_pci_iod_list(req)[0],
570 iod->first_dma);
9275c206
CH		 571 else
572 nvme_free_prps(dev, req);
91fb2b60 573 mempool_free(iod->sgt.sgl, dev->iod_mempool);
b4ff9c8d
KB		 574}
575
d0877473
KB		 576static void nvme_print_sgl(struct scatterlist *sgl, int nents)
577{
578 int i;
579 struct scatterlist *sg;
580
581 for_each_sg(sgl, sg, nents, i) {
582 dma_addr_t phys = sg_phys(sg);
583 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
584 "dma_address:%pad dma_length:%d\n",
585 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
586 sg_dma_len(sg));
587 }
588}
589
a7a7cbe3
CK		 590static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
591 struct request *req, struct nvme_rw_command *cmnd)
ff22b54f 592{
f4800d6d 593 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
99802a7a 594 struct dma_pool *pool;
b131c61d 595 int length = blk_rq_payload_bytes(req);
91fb2b60 596 struct scatterlist *sg = iod->sgt.sgl;
ff22b54f
MW		 597 int dma_len = sg_dma_len(sg);
598 u64 dma_addr = sg_dma_address(sg);
6c3c05b0 599 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
e025344c 600 __le64 *prp_list;
a7a7cbe3 601 void **list = nvme_pci_iod_list(req);
e025344c 602 dma_addr_t prp_dma;
eca18b23 603 int nprps, i;
ff22b54f 604
6c3c05b0 605 length -= (NVME_CTRL_PAGE_SIZE - offset);
5228b328
JS		 606 if (length <= 0) {
607 iod->first_dma = 0;
a7a7cbe3 608 goto done;
5228b328 609 }
ff22b54f 610
6c3c05b0 611 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f 612 if (dma_len) {
6c3c05b0 613 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
ff22b54f
MW		 614 } else {
615 sg = sg_next(sg);
616 dma_addr = sg_dma_address(sg);
617 dma_len = sg_dma_len(sg);
618 }
619
6c3c05b0 620 if (length <= NVME_CTRL_PAGE_SIZE) {
edd10d33 621 iod->first_dma = dma_addr;
a7a7cbe3 622 goto done;
e025344c
SMM		 623 }
624
6c3c05b0 625 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
99802a7a
MW		 626 if (nprps <= (256 / 8)) {
627 pool = dev->prp_small_pool;
c372cdd1 628 iod->nr_allocations = 0;
99802a7a
MW		 629 } else {
630 pool = dev->prp_page_pool;
c372cdd1 631 iod->nr_allocations = 1;
99802a7a
MW		 632 }
633
69d2b571 634 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
b77954cb 635 if (!prp_list) {
c372cdd1 636 iod->nr_allocations = -1;
86eea289 637 return BLK_STS_RESOURCE;
b77954cb 638 }
eca18b23
MW		 639 list[0] = prp_list;
640 iod->first_dma = prp_dma;
e025344c
SMM		 641 i = 0;
642 for (;;) {
6c3c05b0 643 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
e025344c 644 __le64 *old_prp_list = prp_list;
69d2b571 645 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
eca18b23 646 if (!prp_list)
fa073216 647 goto free_prps;
c372cdd1 648 list[iod->nr_allocations++] = prp_list;
7523d834
MW		 649 prp_list[0] = old_prp_list[i - 1];
650 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
651 i = 1;
e025344c
SMM		 652 }
653 prp_list[i++] = cpu_to_le64(dma_addr);
6c3c05b0
CK		 654 dma_len -= NVME_CTRL_PAGE_SIZE;
655 dma_addr += NVME_CTRL_PAGE_SIZE;
656 length -= NVME_CTRL_PAGE_SIZE;
e025344c
SMM		 657 if (length <= 0)
658 break;
659 if (dma_len > 0)
660 continue;
86eea289
KB		 661 if (unlikely(dma_len < 0))
662 goto bad_sgl;
e025344c
SMM		 663 sg = sg_next(sg);
664 dma_addr = sg_dma_address(sg);
665 dma_len = sg_dma_len(sg);
ff22b54f 666 }
a7a7cbe3 667done:
91fb2b60 668 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
a7a7cbe3 669 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
86eea289 670 return BLK_STS_OK;
fa073216
CH		 671free_prps:
672 nvme_free_prps(dev, req);
673 return BLK_STS_RESOURCE;
674bad_sgl:
91fb2b60 675 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
d0877473 676 "Invalid SGL for payload:%d nents:%d\n",
91fb2b60 677 blk_rq_payload_bytes(req), iod->sgt.nents);
86eea289 678 return BLK_STS_IOERR;
ff22b54f
MW		 679}
680
a7a7cbe3
CK		 681static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
682 struct scatterlist *sg)
683{
684 sge->addr = cpu_to_le64(sg_dma_address(sg));
685 sge->length = cpu_to_le32(sg_dma_len(sg));
686 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
687}
688
689static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
690 dma_addr_t dma_addr, int entries)
691{
692 sge->addr = cpu_to_le64(dma_addr);
01df742d
KB		 693 sge->length = cpu_to_le32(entries * sizeof(*sge));
694 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
a7a7cbe3
CK		 695}
696
697static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
91fb2b60 698 struct request *req, struct nvme_rw_command *cmd)
a7a7cbe3
CK		 699{
700 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a7a7cbe3
CK		 701 struct dma_pool *pool;
702 struct nvme_sgl_desc *sg_list;
91fb2b60
LG		 703 struct scatterlist *sg = iod->sgt.sgl;
704 unsigned int entries = iod->sgt.nents;
a7a7cbe3 705 dma_addr_t sgl_dma;
b0f2853b 706 int i = 0;
a7a7cbe3 707
a7a7cbe3
CK		 708 /* setting the transfer type as SGL */
709 cmd->flags = NVME_CMD_SGL_METABUF;
710
b0f2853b 711 if (entries == 1) {
a7a7cbe3
CK		 712 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
713 return BLK_STS_OK;
714 }
715
716 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
717 pool = dev->prp_small_pool;
c372cdd1 718 iod->nr_allocations = 0;
a7a7cbe3
CK		 719 } else {
720 pool = dev->prp_page_pool;
c372cdd1 721 iod->nr_allocations = 1;
a7a7cbe3
CK		 722 }
723
724 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
725 if (!sg_list) {
c372cdd1 726 iod->nr_allocations = -1;
a7a7cbe3
CK		 727 return BLK_STS_RESOURCE;
728 }
729
730 nvme_pci_iod_list(req)[0] = sg_list;
731 iod->first_dma = sgl_dma;
732
733 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
a7a7cbe3 734 do {
a7a7cbe3 735 nvme_pci_sgl_set_data(&sg_list[i++], sg);
a7a7cbe3 736 sg = sg_next(sg);
b0f2853b 737 } while (--entries > 0);
a7a7cbe3 738
a7a7cbe3
CK		 739 return BLK_STS_OK;
740}
741
dff824b2
CH		 742static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
743 struct request *req, struct nvme_rw_command *cmnd,
744 struct bio_vec *bv)
745{
746 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
6c3c05b0
CK		 747 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
748 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
dff824b2
CH		 749
750 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
751 if (dma_mapping_error(dev->dev, iod->first_dma))
752 return BLK_STS_RESOURCE;
753 iod->dma_len = bv->bv_len;
754
755 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
756 if (bv->bv_len > first_prp_len)
757 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
a56ea614
LR		 758 else
759 cmnd->dptr.prp2 = 0;
359c1f88 760 return BLK_STS_OK;
dff824b2
CH		 761}
762
29791057
CH		 763static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
764 struct request *req, struct nvme_rw_command *cmnd,
765 struct bio_vec *bv)
766{
767 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
768
769 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
770 if (dma_mapping_error(dev->dev, iod->first_dma))
771 return BLK_STS_RESOURCE;
772 iod->dma_len = bv->bv_len;
773
049bf372 774 cmnd->flags = NVME_CMD_SGL_METABUF;
29791057
CH		 775 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
776 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
777 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
359c1f88 778 return BLK_STS_OK;
29791057
CH		 779}
780
fc17b653 781static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
b131c61d 782 struct nvme_command *cmnd)
d29ec824 783{
f4800d6d 784 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
70479b71 785 blk_status_t ret = BLK_STS_RESOURCE;
91fb2b60 786 int rc;
d29ec824 787
dff824b2 788 if (blk_rq_nr_phys_segments(req) == 1) {
a53232cb 789 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
dff824b2
CH		 790 struct bio_vec bv = req_bvec(req);
791
792 if (!is_pci_p2pdma_page(bv.bv_page)) {
6c3c05b0 793 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
dff824b2
CH		 794 return nvme_setup_prp_simple(dev, req,
795 &cmnd->rw, &bv);
29791057 796
a53232cb 797 if (nvmeq->qid && sgl_threshold &&
253a0b76 798 nvme_ctrl_sgl_supported(&dev->ctrl))
29791057
CH		 799 return nvme_setup_sgl_simple(dev, req,
800 &cmnd->rw, &bv);
dff824b2
CH		 801 }
802 }
803
804 iod->dma_len = 0;
91fb2b60
LG		 805 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
806 if (!iod->sgt.sgl)
d43f1ccf 807 return BLK_STS_RESOURCE;
91fb2b60
LG		 808 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
809 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
810 if (!iod->sgt.orig_nents)
fa073216 811 goto out_free_sg;
d29ec824 812
91fb2b60
LG		 813 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
814 DMA_ATTR_NO_WARN);
815 if (rc) {
816 if (rc == -EREMOTEIO)
817 ret = BLK_STS_TARGET;
fa073216 818 goto out_free_sg;
91fb2b60 819 }
d29ec824 820
70479b71 821 iod->use_sgl = nvme_pci_use_sgls(dev, req);
955b1b5a 822 if (iod->use_sgl)
91fb2b60 823 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
a7a7cbe3
CK		 824 else
825 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
86eea289 826 if (ret != BLK_STS_OK)
fa073216
CH		 827 goto out_unmap_sg;
828 return BLK_STS_OK;
829
830out_unmap_sg:
91fb2b60 831 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
fa073216 832out_free_sg:
91fb2b60 833 mempool_free(iod->sgt.sgl, dev->iod_mempool);
4aedb705
CH		 834 return ret;
835}
3045c0d0 836
4aedb705
CH		 837static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
838 struct nvme_command *cmnd)
839{
840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
00df5cb4 841
4aedb705
CH		 842 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
843 rq_dma_dir(req), 0);
844 if (dma_mapping_error(dev->dev, iod->meta_dma))
845 return BLK_STS_IOERR;
846 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
359c1f88 847 return BLK_STS_OK;
00df5cb4
MW		 848}
849
62451a2b 850static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
edd10d33 851{
9b048119 852 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
ebe6d874 853 blk_status_t ret;
e1e5e564 854
52da4f3f 855 iod->aborted = false;
c372cdd1 856 iod->nr_allocations = -1;
91fb2b60 857 iod->sgt.nents = 0;
9b048119 858
62451a2b 859 ret = nvme_setup_cmd(req->q->queuedata, req);
fc17b653 860 if (ret)
f4800d6d 861 return ret;
a4aea562 862
fc17b653 863 if (blk_rq_nr_phys_segments(req)) {
62451a2b 864 ret = nvme_map_data(dev, req, &iod->cmd);
fc17b653 865 if (ret)
9b048119 866 goto out_free_cmd;
fc17b653 867 }
a4aea562 868
4aedb705 869 if (blk_integrity_rq(req)) {
62451a2b 870 ret = nvme_map_metadata(dev, req, &iod->cmd);
4aedb705
CH		 871 if (ret)
872 goto out_unmap_data;
873 }
874
6887fc64 875 nvme_start_request(req);
fc17b653 876 return BLK_STS_OK;
4aedb705
CH		 877out_unmap_data:
878 nvme_unmap_data(dev, req);
f9d03f96
CH		 879out_free_cmd:
880 nvme_cleanup_cmd(req);
ba1ca37e 881 return ret;
b60503ba 882}
e1e5e564 883
62451a2b
JA		 884/*
885 * NOTE: ns is NULL when called on the admin queue.
886 */
887static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
888 const struct blk_mq_queue_data *bd)
889{
890 struct nvme_queue *nvmeq = hctx->driver_data;
891 struct nvme_dev *dev = nvmeq->dev;
892 struct request *req = bd->rq;
893 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
894 blk_status_t ret;
895
896 /*
897 * We should not need to do this, but we're still using this to
898 * ensure we can drain requests on a dying queue.
899 */
900 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
901 return BLK_STS_IOERR;
902
903 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
904 return nvme_fail_nonready_command(&dev->ctrl, req);
905
906 ret = nvme_prep_rq(dev, req);
907 if (unlikely(ret))
908 return ret;
909 spin_lock(&nvmeq->sq_lock);
910 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
911 nvme_write_sq_db(nvmeq, bd->last);
912 spin_unlock(&nvmeq->sq_lock);
913 return BLK_STS_OK;
914}
915
d62cbcf6
JA		 916static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
917{
918 spin_lock(&nvmeq->sq_lock);
919 while (!rq_list_empty(*rqlist)) {
920 struct request *req = rq_list_pop(rqlist);
921 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
922
923 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
924 }
925 nvme_write_sq_db(nvmeq, true);
926 spin_unlock(&nvmeq->sq_lock);
927}
928
929static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
930{
931 /*
932 * We should not need to do this, but we're still using this to
933 * ensure we can drain requests on a dying queue.
934 */
935 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
936 return false;
937 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
938 return false;
939
940 req->mq_hctx->tags->rqs[req->tag] = req;
941 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
942}
943
944static void nvme_queue_rqs(struct request **rqlist)
945{
6bfec799 946 struct request *req, *next, *prev = NULL;
d62cbcf6
JA		 947 struct request *requeue_list = NULL;
948
6bfec799 949 rq_list_for_each_safe(rqlist, req, next) {
d62cbcf6
JA		 950 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
951
952 if (!nvme_prep_rq_batch(nvmeq, req)) {
953 /* detach 'req' and add to remainder list */
6bfec799
KB		 954 rq_list_move(rqlist, &requeue_list, req, prev);
955
956 req = prev;
957 if (!req)
958 continue;
d62cbcf6
JA		 959 }
960
6bfec799 961 if (!next || req->mq_hctx != next->mq_hctx) {
d62cbcf6 962 /* detach rest of list, and submit */
6bfec799 963 req->rq_next = NULL;
d62cbcf6 964 nvme_submit_cmds(nvmeq, rqlist);
6bfec799
KB		 965 *rqlist = next;
966 prev = NULL;
967 } else
968 prev = req;
969 }
d62cbcf6
JA		 970
971 *rqlist = requeue_list;
972}
973
c234a653 974static __always_inline void nvme_pci_unmap_rq(struct request *req)
eee417b0 975{
a53232cb
KB		 976 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
977 struct nvme_dev *dev = nvmeq->dev;
978
979 if (blk_integrity_rq(req)) {
980 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a4aea562 981
4aedb705
CH		 982 dma_unmap_page(dev->dev, iod->meta_dma,
983 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
a53232cb
KB		 984 }
985
b15c592d 986 if (blk_rq_nr_phys_segments(req))
4aedb705 987 nvme_unmap_data(dev, req);
c234a653
JA		 988}
989
990static void nvme_pci_complete_rq(struct request *req)
991{
992 nvme_pci_unmap_rq(req);
77f02a7a 993 nvme_complete_rq(req);
b60503ba
MW		 994}
995
c234a653
JA		 996static void nvme_pci_complete_batch(struct io_comp_batch *iob)
997{
998 nvme_complete_batch(iob, nvme_pci_unmap_rq);
999}
1000
d783e0bd 1001/* We read the CQE phase first to check if the rest of the entry is valid */
750dde44 1002static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
d783e0bd 1003{
74943d45
KB		 1004 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1005
1006 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
d783e0bd
MR		 1007}
1008
eb281c82 1009static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
b60503ba 1010{
eb281c82 1011 u16 head = nvmeq->cq_head;
adf68f21 1012
397c699f
KB		 1013 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1014 nvmeq->dbbuf_cq_ei))
1015 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
eb281c82 1016}
aae239e1 1017
cfa27356
CH		 1018static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1019{
1020 if (!nvmeq->qid)
1021 return nvmeq->dev->admin_tagset.tags[0];
1022 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1023}
1024
c234a653
JA		 1025static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1026 struct io_comp_batch *iob, u16 idx)
83a12fb7 1027{
74943d45 1028 struct nvme_completion *cqe = &nvmeq->cqes[idx];
62df8016 1029 __u16 command_id = READ_ONCE(cqe->command_id);
83a12fb7 1030 struct request *req;
adf68f21 1031
83a12fb7
SG		 1032 /*
1033 * AEN requests are special as they don't time out and can
1034 * survive any kind of queue freeze and often don't respond to
1035 * aborts. We don't even bother to allocate a struct request
1036 * for them but rather special case them here.
1037 */
62df8016 1038 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
83a12fb7
SG		 1039 nvme_complete_async_event(&nvmeq->dev->ctrl,
1040 cqe->status, &cqe->result);
a0fa9647 1041 return;
83a12fb7 1042 }
b60503ba 1043
e7006de6 1044 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
50b7c243
XT		 1045 if (unlikely(!req)) {
1046 dev_warn(nvmeq->dev->ctrl.device,
1047 "invalid id %d completed on queue %d\n",
62df8016 1048 command_id, le16_to_cpu(cqe->sq_id));
50b7c243
XT		 1049 return;
1050 }
1051
604c01d5 1052 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
c234a653
JA		 1053 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1054 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1055 nvme_pci_complete_batch))
ff029451 1056 nvme_pci_complete_rq(req);
83a12fb7 1057}
b60503ba 1058
5cb525c8
JA		 1059static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1060{
a0aac973 1061 u32 tmp = nvmeq->cq_head + 1;
a8de6639
AD		 1062
1063 if (tmp == nvmeq->q_depth) {
5cb525c8 1064 nvmeq->cq_head = 0;
e2a366a4 1065 nvmeq->cq_phase ^= 1;
a8de6639
AD		 1066 } else {
1067 nvmeq->cq_head = tmp;
b60503ba 1068 }
a0fa9647
JA		 1069}
1070
c234a653
JA		 1071static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1072 struct io_comp_batch *iob)
a0fa9647 1073{
1052b8ac 1074 int found = 0;
b60503ba 1075
1052b8ac 1076 while (nvme_cqe_pending(nvmeq)) {
bf392a5d 1077 found++;
b69e2ef2
KB		 1078 /*
1079 * load-load control dependency between phase and the rest of
1080 * the cqe requires a full read memory barrier
1081 */
1082 dma_rmb();
c234a653 1083 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
5cb525c8 1084 nvme_update_cq_head(nvmeq);
920d13a8 1085 }
eb281c82 1086
324b494c 1087 if (found)
920d13a8 1088 nvme_ring_cq_doorbell(nvmeq);
5cb525c8 1089 return found;
b60503ba
MW		 1090}
1091
1092static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5 1093{
58ffacb5 1094 struct nvme_queue *nvmeq = data;
4f502245 1095 DEFINE_IO_COMP_BATCH(iob);
5cb525c8 1096
4f502245
JA		 1097 if (nvme_poll_cq(nvmeq, &iob)) {
1098 if (!rq_list_empty(iob.req_list))
1099 nvme_pci_complete_batch(&iob);
05fae499 1100 return IRQ_HANDLED;
4f502245 1101 }
05fae499 1102 return IRQ_NONE;
58ffacb5
MW		 1103}
1104
1105static irqreturn_t nvme_irq_check(int irq, void *data)
1106{
1107 struct nvme_queue *nvmeq = data;
4e523547 1108
750dde44 1109 if (nvme_cqe_pending(nvmeq))
d783e0bd
MR		 1110 return IRQ_WAKE_THREAD;
1111 return IRQ_NONE;
58ffacb5
MW		 1112}
1113
0b2a8a9f 1114/*
fa059b85 1115 * Poll for completions for any interrupt driven queue
0b2a8a9f
CH		 1116 * Can be called from any context.
1117 */
fa059b85 1118static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
a0fa9647 1119{
3a7afd8e 1120 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
a0fa9647 1121
fa059b85 1122 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
442e19b7 1123
fa059b85 1124 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
c234a653 1125 nvme_poll_cq(nvmeq, NULL);
fa059b85 1126 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
a0fa9647
JA		 1127}
1128
5a72e899 1129static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
dabcefab
JA		 1130{
1131 struct nvme_queue *nvmeq = hctx->driver_data;
dabcefab
JA		 1132 bool found;
1133
1134 if (!nvme_cqe_pending(nvmeq))
1135 return 0;
1136
3a7afd8e 1137 spin_lock(&nvmeq->cq_poll_lock);
c234a653 1138 found = nvme_poll_cq(nvmeq, iob);
3a7afd8e 1139 spin_unlock(&nvmeq->cq_poll_lock);
dabcefab 1140
dabcefab
JA		 1141 return found;
1142}
1143
ad22c355 1144static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
b60503ba 1145{
f866fc42 1146 struct nvme_dev *dev = to_nvme_dev(ctrl);
147b27e4 1147 struct nvme_queue *nvmeq = &dev->queues[0];
f66e2804 1148 struct nvme_command c = { };
b60503ba 1149
a4aea562 1150 c.common.opcode = nvme_admin_async_event;
ad22c355 1151 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
3233b94c
JA		 1152
1153 spin_lock(&nvmeq->sq_lock);
1154 nvme_sq_copy_cmd(nvmeq, &c);
1155 nvme_write_sq_db(nvmeq, true);
1156 spin_unlock(&nvmeq->sq_lock);
f705f837
CH		 1157}
1158
b60503ba 1159static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
f705f837 1160{
f66e2804 1161 struct nvme_command c = { };
b60503ba 1162
b60503ba
MW		 1163 c.delete_queue.opcode = opcode;
1164 c.delete_queue.qid = cpu_to_le16(id);
1165
1c63dc66 1166 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1167}
1168
b60503ba 1169static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
a8e3e0bb 1170 struct nvme_queue *nvmeq, s16 vector)
b60503ba 1171{
f66e2804 1172 struct nvme_command c = { };
4b04cc6a
JA		 1173 int flags = NVME_QUEUE_PHYS_CONTIG;
1174
7c349dde 1175 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
4b04cc6a 1176 flags |= NVME_CQ_IRQ_ENABLED;
b60503ba 1177
d29ec824 1178 /*
16772ae6 1179 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1180 * is attached to the request.
1181 */
b60503ba
MW		 1182 c.create_cq.opcode = nvme_admin_create_cq;
1183 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1184 c.create_cq.cqid = cpu_to_le16(qid);
1185 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1186 c.create_cq.cq_flags = cpu_to_le16(flags);
7c349dde 1187 c.create_cq.irq_vector = cpu_to_le16(vector);
b60503ba 1188
1c63dc66 1189 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1190}
1191
1192static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1193 struct nvme_queue *nvmeq)
1194{
9abd68ef 1195 struct nvme_ctrl *ctrl = &dev->ctrl;
f66e2804 1196 struct nvme_command c = { };
81c1cd98 1197 int flags = NVME_QUEUE_PHYS_CONTIG;
b60503ba 1198
9abd68ef
JA		 1199 /*
1200 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1201 * set. Since URGENT priority is zeroes, it makes all queues
1202 * URGENT.
1203 */
1204 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1205 flags |= NVME_SQ_PRIO_MEDIUM;
1206
d29ec824 1207 /*
16772ae6 1208 * Note: we (ab)use the fact that the prp fields survive if no data
d29ec824
CH		 1209 * is attached to the request.
1210 */
b60503ba
MW		 1211 c.create_sq.opcode = nvme_admin_create_sq;
1212 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1213 c.create_sq.sqid = cpu_to_le16(qid);
1214 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1215 c.create_sq.sq_flags = cpu_to_le16(flags);
1216 c.create_sq.cqid = cpu_to_le16(qid);
1217
1c63dc66 1218 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
b60503ba
MW		 1219}
1220
1221static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1222{
1223 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1224}
1225
1226static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1227{
1228 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1229}
1230
de671d61 1231static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
bc5fc7e4 1232{
a53232cb 1233 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
e44ac588 1234
27fa9bc5
CH		 1235 dev_warn(nvmeq->dev->ctrl.device,
1236 "Abort status: 0x%x", nvme_req(req)->status);
e7a2a87d 1237 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
e7a2a87d 1238 blk_mq_free_request(req);
de671d61 1239 return RQ_END_IO_NONE;
bc5fc7e4
MW		 1240}
1241
b2a0eb1a
KB		 1242static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1243{
b2a0eb1a
KB		 1244 /* If true, indicates loss of adapter communication, possibly by a
1245 * NVMe Subsystem reset.
1246 */
1247 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1248
ad70062c
JW		 1249 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1250 switch (dev->ctrl.state) {
1251 case NVME_CTRL_RESETTING:
ad6a0a52 1252 case NVME_CTRL_CONNECTING:
b2a0eb1a 1253 return false;
ad70062c
JW		 1254 default:
1255 break;
1256 }
b2a0eb1a
KB		 1257
1258 /* We shouldn't reset unless the controller is on fatal error state
1259 * _or_ if we lost the communication with it.
1260 */
1261 if (!(csts & NVME_CSTS_CFS) && !nssro)
1262 return false;
1263
b2a0eb1a
KB		 1264 return true;
1265}
1266
1267static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1268{
1269 /* Read a config register to help see what died. */
1270 u16 pci_status;
1271 int result;
1272
1273 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1274 &pci_status);
1275 if (result == PCIBIOS_SUCCESSFUL)
1276 dev_warn(dev->ctrl.device,
1277 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1278 csts, pci_status);
1279 else
1280 dev_warn(dev->ctrl.device,
1281 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1282 csts, result);
4641a8e6
KB		 1283
1284 if (csts != ~0)
1285 return;
1286
1287 dev_warn(dev->ctrl.device,
1288 "Does your device have a faulty power saving mode enabled?\n");
1289 dev_warn(dev->ctrl.device,
1290 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
b2a0eb1a
KB		 1291}
1292
9bdb4833 1293static enum blk_eh_timer_return nvme_timeout(struct request *req)
c30341dc 1294{
f4800d6d 1295 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
a53232cb 1296 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
c30341dc 1297 struct nvme_dev *dev = nvmeq->dev;
a4aea562 1298 struct request *abort_req;
f66e2804 1299 struct nvme_command cmd = { };
b2a0eb1a
KB		 1300 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1301
651438bb
WX		 1302 /* If PCI error recovery process is happening, we cannot reset or
1303 * the recovery mechanism will surely fail.
1304 */
1305 mb();
1306 if (pci_channel_offline(to_pci_dev(dev->dev)))
1307 return BLK_EH_RESET_TIMER;
1308
b2a0eb1a
KB		 1309 /*
1310 * Reset immediately if the controller is failed
1311 */
1312 if (nvme_should_reset(dev, csts)) {
1313 nvme_warn_reset(dev, csts);
1314 nvme_dev_disable(dev, false);
d86c4d8e 1315 nvme_reset_ctrl(&dev->ctrl);
db8c48e4 1316 return BLK_EH_DONE;
b2a0eb1a 1317 }
c30341dc 1318
7776db1c
KB		 1319 /*
1320 * Did we miss an interrupt?
1321 */
fa059b85 1322 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
5a72e899 1323 nvme_poll(req->mq_hctx, NULL);
fa059b85
KB		 1324 else
1325 nvme_poll_irqdisable(nvmeq);
1326
1c584208 1327 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
7776db1c
KB		 1328 dev_warn(dev->ctrl.device,
1329 "I/O %d QID %d timeout, completion polled\n",
1330 req->tag, nvmeq->qid);
db8c48e4 1331 return BLK_EH_DONE;
7776db1c
KB		 1332 }
1333
31c7c7d2 1334 /*
fd634f41
CH		 1335 * Shutdown immediately if controller times out while starting. The
1336 * reset work will see the pci device disabled when it gets the forced
1337 * cancellation error. All outstanding requests are completed on
db8c48e4 1338 * shutdown, so we return BLK_EH_DONE.
fd634f41 1339 */
4244140d
KB		 1340 switch (dev->ctrl.state) {
1341 case NVME_CTRL_CONNECTING:
2036f726 1342 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
df561f66 1343 fallthrough;
2036f726 1344 case NVME_CTRL_DELETING:
b9cac43c 1345 dev_warn_ratelimited(dev->ctrl.device,
fd634f41
CH		 1346 "I/O %d QID %d timeout, disable controller\n",
1347 req->tag, nvmeq->qid);
27fa9bc5 1348 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
7ad92f65 1349 nvme_dev_disable(dev, true);
db8c48e4 1350 return BLK_EH_DONE;
39a9dd81
KB		 1351 case NVME_CTRL_RESETTING:
1352 return BLK_EH_RESET_TIMER;
4244140d
KB		 1353 default:
1354 break;
c30341dc
KB		 1355 }
1356
fd634f41 1357 /*
ee0d96d3
BW		 1358 * Shutdown the controller immediately and schedule a reset if the
1359 * command was already aborted once before and still hasn't been
1360 * returned to the driver, or if this is the admin queue.
31c7c7d2 1361 */
f4800d6d 1362 if (!nvmeq->qid || iod->aborted) {
1b3c47c1 1363 dev_warn(dev->ctrl.device,
e1569a16
KB		 1364 "I/O %d QID %d timeout, reset controller\n",
1365 req->tag, nvmeq->qid);
7ad92f65 1366 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
a5cdb68c 1367 nvme_dev_disable(dev, false);
d86c4d8e 1368 nvme_reset_ctrl(&dev->ctrl);
c30341dc 1369
db8c48e4 1370 return BLK_EH_DONE;
c30341dc 1371 }
c30341dc 1372
e7a2a87d 1373 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
6bf25d16 1374 atomic_inc(&dev->ctrl.abort_limit);
31c7c7d2 1375 return BLK_EH_RESET_TIMER;
6bf25d16 1376 }
52da4f3f 1377 iod->aborted = true;
a4aea562 1378
c30341dc 1379 cmd.abort.opcode = nvme_admin_abort_cmd;
85f74acf 1380 cmd.abort.cid = nvme_cid(req);
c30341dc 1381 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
c30341dc 1382
1b3c47c1 1383 dev_warn(nvmeq->dev->ctrl.device,
86141440
CH		 1384 "I/O %d (%s) QID %d timeout, aborting\n",
1385 req->tag,
1386 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1387 nvmeq->qid);
e7a2a87d 1388
e559398f
CH		 1389 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1390 BLK_MQ_REQ_NOWAIT);
e7a2a87d
CH		 1391 if (IS_ERR(abort_req)) {
1392 atomic_inc(&dev->ctrl.abort_limit);
1393 return BLK_EH_RESET_TIMER;
1394 }
e559398f 1395 nvme_init_request(abort_req, &cmd);
e7a2a87d 1396
e2e53086 1397 abort_req->end_io = abort_endio;
e7a2a87d 1398 abort_req->end_io_data = NULL;
e2e53086 1399 blk_execute_rq_nowait(abort_req, false);
c30341dc 1400
31c7c7d2
CH		 1401 /*
1402 * The aborted req will be completed on receiving the abort req.
1403 * We enable the timer again. If hit twice, it'll cause a device reset,
1404 * as the device then is in a faulty state.
1405 */
1406 return BLK_EH_RESET_TIMER;
c30341dc
KB		 1407}
1408
a4aea562
MB		 1409static void nvme_free_queue(struct nvme_queue *nvmeq)
1410{
8a1d09a6 1411 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
9e866774 1412 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
63223078
CH		 1413 if (!nvmeq->sq_cmds)
1414 return;
0f238ff5 1415
63223078 1416 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
88a041f4 1417 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
8a1d09a6 1418 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1419 } else {
8a1d09a6 1420 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
63223078 1421 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
0f238ff5 1422 }
9e866774
MW		 1423}
1424
a1a5ef99 1425static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1426{
1427 int i;
1428
d858e5f0 1429 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
d858e5f0 1430 dev->ctrl.queue_count--;
147b27e4 1431 nvme_free_queue(&dev->queues[i]);
121c7ad4 1432 }
22404274
KB		 1433}
1434
10981f23 1435static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
b60503ba 1436{
10981f23
CH		 1437 struct nvme_queue *nvmeq = &dev->queues[qid];
1438
4e224106 1439 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
10981f23 1440 return;
a09115b2 1441
4e224106 1442 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
d1f06f4a 1443 mb();
a09115b2 1444
4e224106 1445 nvmeq->dev->online_queues--;
1c63dc66 1446 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
9f27bd70 1447 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
7c349dde 1448 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
10981f23 1449 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
4d115420 1450}
b60503ba 1451
8fae268b
KB		 1452static void nvme_suspend_io_queues(struct nvme_dev *dev)
1453{
1454 int i;
1455
1456 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
10981f23 1457 nvme_suspend_queue(dev, i);
b60503ba
MW		 1458}
1459
fa46c6fb
KB		 1460/*
1461 * Called only on a device that has been disabled and after all other threads
9210c075
DZ		 1462 * that can check this device's completion queues have synced, except
1463 * nvme_poll(). This is the last chance for the driver to see a natural
1464 * completion before nvme_cancel_request() terminates all incomplete requests.
fa46c6fb
KB		 1465 */
1466static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1467{
fa46c6fb
KB		 1468 int i;
1469
9210c075
DZ		 1470 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1471 spin_lock(&dev->queues[i].cq_poll_lock);
c234a653 1472 nvme_poll_cq(&dev->queues[i], NULL);
9210c075
DZ		 1473 spin_unlock(&dev->queues[i].cq_poll_lock);
1474 }
fa46c6fb
KB		 1475}
1476
8ffaadf7
JD		 1477static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1478 int entry_size)
1479{
1480 int q_depth = dev->q_depth;
5fd4ce1b 1481 unsigned q_size_aligned = roundup(q_depth * entry_size,
6c3c05b0 1482 NVME_CTRL_PAGE_SIZE);
8ffaadf7
JD		 1483
1484 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
c45f5c99 1485 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
4e523547 1486
6c3c05b0 1487 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
c45f5c99 1488 q_depth = div_u64(mem_per_q, entry_size);
8ffaadf7
JD		 1489
1490 /*
1491 * Ensure the reduced q_depth is above some threshold where it
1492 * would be better to map queues in system memory with the
1493 * original depth
1494 */
1495 if (q_depth < 64)
1496 return -ENOMEM;
1497 }
1498
1499 return q_depth;
1500}
1501
1502static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
8a1d09a6 1503 int qid)
8ffaadf7 1504{
0f238ff5
LG		 1505 struct pci_dev *pdev = to_pci_dev(dev->dev);
1506
1507 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
8a1d09a6 1508 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
bfac8e9f
AM		 1509 if (nvmeq->sq_cmds) {
1510 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1511 nvmeq->sq_cmds);
1512 if (nvmeq->sq_dma_addr) {
1513 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1514 return 0;
1515 }
1516
8a1d09a6 1517 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
63223078 1518 }
0f238ff5 1519 }
8ffaadf7 1520
8a1d09a6 1521 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
63223078 1522 &nvmeq->sq_dma_addr, GFP_KERNEL);
815c6704
KB		 1523 if (!nvmeq->sq_cmds)
1524 return -ENOMEM;
8ffaadf7
JD		 1525 return 0;
1526}
1527
a6ff7262 1528static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
b60503ba 1529{
147b27e4 1530 struct nvme_queue *nvmeq = &dev->queues[qid];
b60503ba 1531
62314e40
KB		 1532 if (dev->ctrl.queue_count > qid)
1533 return 0;
b60503ba 1534
c1e0cc7e 1535 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
8a1d09a6
BH		 1536 nvmeq->q_depth = depth;
1537 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
750afb08 1538 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1539 if (!nvmeq->cqes)
1540 goto free_nvmeq;
b60503ba 1541
8a1d09a6 1542 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
b60503ba
MW		 1543 goto free_cqdma;
1544
091b6092 1545 nvmeq->dev = dev;
1ab0cd69 1546 spin_lock_init(&nvmeq->sq_lock);
3a7afd8e 1547 spin_lock_init(&nvmeq->cq_poll_lock);
b60503ba 1548 nvmeq->cq_head = 0;
82123460 1549 nvmeq->cq_phase = 1;
b80d5ccc 1550 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
c30341dc 1551 nvmeq->qid = qid;
d858e5f0 1552 dev->ctrl.queue_count++;
36a7e993 1553
147b27e4 1554 return 0;
b60503ba
MW		 1555
1556 free_cqdma:
8a1d09a6
BH		 1557 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1558 nvmeq->cq_dma_addr);
b60503ba 1559 free_nvmeq:
147b27e4 1560 return -ENOMEM;
b60503ba
MW		 1561}
1562
dca51e78 1563static int queue_request_irq(struct nvme_queue *nvmeq)
3001082c 1564{
0ff199cb
CH		 1565 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1566 int nr = nvmeq->dev->ctrl.instance;
1567
1568 if (use_threaded_interrupts) {
1569 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1570 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1571 } else {
1572 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1573 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1574 }
3001082c
MW		 1575}
1576
22404274 1577static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1578{
22404274 1579 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1580
22404274 1581 nvmeq->sq_tail = 0;
38210800 1582 nvmeq->last_sq_tail = 0;
22404274
KB		 1583 nvmeq->cq_head = 0;
1584 nvmeq->cq_phase = 1;
b80d5ccc 1585 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
8a1d09a6 1586 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
f9f38e33 1587 nvme_dbbuf_init(dev, nvmeq, qid);
42f61420 1588 dev->online_queues++;
3a7afd8e 1589 wmb(); /* ensure the first interrupt sees the initialization */
22404274
KB		 1590}
1591
e4b9852a
CC		 1592/*
1593 * Try getting shutdown_lock while setting up IO queues.
1594 */
1595static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1596{
1597 /*
1598 * Give up if the lock is being held by nvme_dev_disable.
1599 */
1600 if (!mutex_trylock(&dev->shutdown_lock))
1601 return -ENODEV;
1602
1603 /*
1604 * Controller is in wrong state, fail early.
1605 */
1606 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1607 mutex_unlock(&dev->shutdown_lock);
1608 return -ENODEV;
1609 }
1610
1611 return 0;
1612}
1613
4b04cc6a 1614static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
22404274
KB		 1615{
1616 struct nvme_dev *dev = nvmeq->dev;
1617 int result;
7c349dde 1618 u16 vector = 0;
3f85d50b 1619
d1ed6aa1
CH		 1620 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1621
22b55601
KB		 1622 /*
1623 * A queue's vector matches the queue identifier unless the controller
1624 * has only one vector available.
1625 */
4b04cc6a
JA		 1626 if (!polled)
1627 vector = dev->num_vecs == 1 ? 0 : qid;
1628 else
7c349dde 1629 set_bit(NVMEQ_POLLED, &nvmeq->flags);
4b04cc6a 1630
a8e3e0bb 1631 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
ded45505
KB		 1632 if (result)
1633 return result;
b60503ba
MW		 1634
1635 result = adapter_alloc_sq(dev, qid, nvmeq);
1636 if (result < 0)
ded45505 1637 return result;
c80b36cd 1638 if (result)
b60503ba
MW		 1639 goto release_cq;
1640
a8e3e0bb 1641 nvmeq->cq_vector = vector;
4b04cc6a 1642
e4b9852a
CC		 1643 result = nvme_setup_io_queues_trylock(dev);
1644 if (result)
1645 return result;
1646 nvme_init_queue(nvmeq, qid);
7c349dde 1647 if (!polled) {
4b04cc6a
JA		 1648 result = queue_request_irq(nvmeq);
1649 if (result < 0)
1650 goto release_sq;
1651 }
b60503ba 1652
4e224106 1653 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
e4b9852a 1654 mutex_unlock(&dev->shutdown_lock);
22404274 1655 return result;
b60503ba 1656
a8e3e0bb 1657release_sq:
f25a2dfc 1658 dev->online_queues--;
e4b9852a 1659 mutex_unlock(&dev->shutdown_lock);
b60503ba 1660 adapter_delete_sq(dev, qid);
a8e3e0bb 1661release_cq:
b60503ba 1662 adapter_delete_cq(dev, qid);
22404274 1663 return result;
b60503ba
MW		 1664}
1665
f363b089 1666static const struct blk_mq_ops nvme_mq_admin_ops = {
d29ec824 1667 .queue_rq = nvme_queue_rq,
77f02a7a 1668 .complete = nvme_pci_complete_rq,
a4aea562 1669 .init_hctx = nvme_admin_init_hctx,
e559398f 1670 .init_request = nvme_pci_init_request,
a4aea562
MB		 1671 .timeout = nvme_timeout,
1672};
1673
f363b089 1674static const struct blk_mq_ops nvme_mq_ops = {
376f7ef8 1675 .queue_rq = nvme_queue_rq,
d62cbcf6 1676 .queue_rqs = nvme_queue_rqs,
376f7ef8
CH		 1677 .complete = nvme_pci_complete_rq,
1678 .commit_rqs = nvme_commit_rqs,
1679 .init_hctx = nvme_init_hctx,
e559398f 1680 .init_request = nvme_pci_init_request,
376f7ef8
CH		 1681 .map_queues = nvme_pci_map_queues,
1682 .timeout = nvme_timeout,
1683 .poll = nvme_poll,
dabcefab
JA		 1684};
1685
ea191d2f
KB		 1686static void nvme_dev_remove_admin(struct nvme_dev *dev)
1687{
1c63dc66 1688 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
69d9a99c
KB		 1689 /*
1690 * If the controller was reset during removal, it's possible
1691 * user requests may be waiting on a stopped queue. Start the
1692 * queue to flush these to completion.
1693 */
9f27bd70 1694 nvme_unquiesce_admin_queue(&dev->ctrl);
0da7feaa 1695 nvme_remove_admin_tag_set(&dev->ctrl);
ea191d2f
KB		 1696 }
1697}
1698
97f6ef64
XY		 1699static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1700{
1701 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1702}
1703
1704static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1705{
1706 struct pci_dev *pdev = to_pci_dev(dev->dev);
1707
1708 if (size <= dev->bar_mapped_size)
1709 return 0;
1710 if (size > pci_resource_len(pdev, 0))
1711 return -ENOMEM;
1712 if (dev->bar)
1713 iounmap(dev->bar);
1714 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1715 if (!dev->bar) {
1716 dev->bar_mapped_size = 0;
1717 return -ENOMEM;
1718 }
1719 dev->bar_mapped_size = size;
1720 dev->dbs = dev->bar + NVME_REG_DBS;
1721
1722 return 0;
1723}
1724
01ad0990 1725static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1726{
ba47e386 1727 int result;
b60503ba
MW		 1728 u32 aqa;
1729 struct nvme_queue *nvmeq;
1730
97f6ef64
XY		 1731 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1732 if (result < 0)
1733 return result;
1734
8ef2074d 1735 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
20d0dfe6 1736 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
dfbac8c7 1737
7a67cbea
CH		 1738 if (dev->subsystem &&
1739 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1740 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
dfbac8c7 1741
285b6e9b
CH		 1742 /*
1743 * If the device has been passed off to us in an enabled state, just
1744 * clear the enabled bit. The spec says we should set the 'shutdown
1745 * notification bits', but doing so may cause the device to complete
1746 * commands to the admin queue ... and we don't know what memory that
1747 * might be pointing at!
1748 */
1749 result = nvme_disable_ctrl(&dev->ctrl, false);
ba47e386
MW		 1750 if (result < 0)
1751 return result;
b60503ba 1752
a6ff7262 1753 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
147b27e4
SG		 1754 if (result)
1755 return result;
b60503ba 1756
635333e4
MG		 1757 dev->ctrl.numa_node = dev_to_node(dev->dev);
1758
147b27e4 1759 nvmeq = &dev->queues[0];
b60503ba
MW		 1760 aqa = nvmeq->q_depth - 1;
1761 aqa |= aqa << 16;
1762
7a67cbea
CH		 1763 writel(aqa, dev->bar + NVME_REG_AQA);
1764 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1765 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
b60503ba 1766
c0f2f45b 1767 result = nvme_enable_ctrl(&dev->ctrl);
025c557a 1768 if (result)
d4875622 1769 return result;
a4aea562 1770
2b25d981 1771 nvmeq->cq_vector = 0;
161b8be2 1772 nvme_init_queue(nvmeq, 0);
dca51e78 1773 result = queue_request_irq(nvmeq);
758dd7fd 1774 if (result) {
7c349dde 1775 dev->online_queues--;
d4875622 1776 return result;
758dd7fd 1777 }
025c557a 1778
4e224106 1779 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
b60503ba
MW		 1780 return result;
1781}
1782
749941f2 1783static int nvme_create_io_queues(struct nvme_dev *dev)
42f61420 1784{
4b04cc6a 1785 unsigned i, max, rw_queues;
749941f2 1786 int ret = 0;
42f61420 1787
d858e5f0 1788 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
a6ff7262 1789 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
749941f2 1790 ret = -ENOMEM;
42f61420 1791 break;
749941f2
CH		 1792 }
1793 }
42f61420 1794
d858e5f0 1795 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
e20ba6e1
CH		 1796 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1797 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1798 dev->io_queues[HCTX_TYPE_READ];
4b04cc6a
JA		 1799 } else {
1800 rw_queues = max;
1801 }
1802
949928c1 1803 for (i = dev->online_queues; i <= max; i++) {
4b04cc6a
JA		 1804 bool polled = i > rw_queues;
1805
1806 ret = nvme_create_queue(&dev->queues[i], i, polled);
d4875622 1807 if (ret)
42f61420 1808 break;
27e8166c 1809 }
749941f2
CH		 1810
1811 /*
1812 * Ignore failing Create SQ/CQ commands, we can continue with less
8adb8c14
MI		 1813 * than the desired amount of queues, and even a controller without
1814 * I/O queues can still be used to issue admin commands. This might
749941f2
CH		 1815 * be useful to upgrade a buggy firmware for example.
1816 */
1817 return ret >= 0 ? 0 : ret;
b60503ba
MW		 1818}
1819
88de4598 1820static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
8ffaadf7 1821{
88de4598
CH		 1822 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1823
1824 return 1ULL << (12 + 4 * szu);
1825}
1826
1827static u32 nvme_cmb_size(struct nvme_dev *dev)
1828{
1829 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1830}
1831
f65efd6d 1832static void nvme_map_cmb(struct nvme_dev *dev)
8ffaadf7 1833{
88de4598 1834 u64 size, offset;
8ffaadf7
JD		 1835 resource_size_t bar_size;
1836 struct pci_dev *pdev = to_pci_dev(dev->dev);
8969f1f8 1837 int bar;
8ffaadf7 1838
9fe5c59f
KB		 1839 if (dev->cmb_size)
1840 return;
1841
20d3bb92
KJ		 1842 if (NVME_CAP_CMBS(dev->ctrl.cap))
1843 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1844
7a67cbea 1845 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
f65efd6d
CH		 1846 if (!dev->cmbsz)
1847 return;
202021c1 1848 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
8ffaadf7 1849
88de4598
CH		 1850 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1851 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
8969f1f8
CH		 1852 bar = NVME_CMB_BIR(dev->cmbloc);
1853 bar_size = pci_resource_len(pdev, bar);
8ffaadf7
JD		 1854
1855 if (offset > bar_size)
f65efd6d 1856 return;
8ffaadf7 1857
20d3bb92
KJ		 1858 /*
1859 * Tell the controller about the host side address mapping the CMB,
1860 * and enable CMB decoding for the NVMe 1.4+ scheme:
1861 */
1862 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1863 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1864 (pci_bus_address(pdev, bar) + offset),
1865 dev->bar + NVME_REG_CMBMSC);
1866 }
1867
8ffaadf7
JD		 1868 /*
1869 * Controllers may support a CMB size larger than their BAR,
1870 * for example, due to being behind a bridge. Reduce the CMB to
1871 * the reported size of the BAR
1872 */
1873 if (size > bar_size - offset)
1874 size = bar_size - offset;
1875
0f238ff5
LG		 1876 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1877 dev_warn(dev->ctrl.device,
1878 "failed to register the CMB\n");
f65efd6d 1879 return;
0f238ff5
LG		 1880 }
1881
8ffaadf7 1882 dev->cmb_size = size;
0f238ff5
LG		 1883 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1884
1885 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1886 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1887 pci_p2pmem_publish(pdev, true);
8ffaadf7
JD		 1888}
1889
87ad72a5
CH		 1890static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1891{
6c3c05b0 1892 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
4033f35d 1893 u64 dma_addr = dev->host_mem_descs_dma;
f66e2804 1894 struct nvme_command c = { };
87ad72a5
CH		 1895 int ret;
1896
87ad72a5
CH		 1897 c.features.opcode = nvme_admin_set_features;
1898 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1899 c.features.dword11 = cpu_to_le32(bits);
6c3c05b0 1900 c.features.dword12 = cpu_to_le32(host_mem_size);
87ad72a5
CH		 1901 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1902 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1903 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1904
1905 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1906 if (ret) {
1907 dev_warn(dev->ctrl.device,
1908 "failed to set host mem (err %d, flags %#x).\n",
1909 ret, bits);
a5df5e79
KB		 1910 } else
1911 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1912
87ad72a5
CH		 1913 return ret;
1914}
1915
1916static void nvme_free_host_mem(struct nvme_dev *dev)
1917{
1918 int i;
1919
1920 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1921 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
6c3c05b0 1922 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1923
cc667f6d
LD		 1924 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1925 le64_to_cpu(desc->addr),
1926 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1927 }
1928
1929 kfree(dev->host_mem_desc_bufs);
1930 dev->host_mem_desc_bufs = NULL;
4033f35d
CH		 1931 dma_free_coherent(dev->dev,
1932 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1933 dev->host_mem_descs, dev->host_mem_descs_dma);
87ad72a5 1934 dev->host_mem_descs = NULL;
7e5dd57e 1935 dev->nr_host_mem_descs = 0;
87ad72a5
CH		 1936}
1937
92dc6895
CH		 1938static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1939 u32 chunk_size)
9d713c2b 1940{
87ad72a5 1941 struct nvme_host_mem_buf_desc *descs;
92dc6895 1942 u32 max_entries, len;
4033f35d 1943 dma_addr_t descs_dma;
2ee0e4ed 1944 int i = 0;
87ad72a5 1945 void **bufs;
6fbcde66 1946 u64 size, tmp;
87ad72a5 1947
87ad72a5
CH		 1948 tmp = (preferred + chunk_size - 1);
1949 do_div(tmp, chunk_size);
1950 max_entries = tmp;
044a9df1
CH		 1951
1952 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1953 max_entries = dev->ctrl.hmmaxd;
1954
750afb08
LC		 1955 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1956 &descs_dma, GFP_KERNEL);
87ad72a5
CH		 1957 if (!descs)
1958 goto out;
1959
1960 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1961 if (!bufs)
1962 goto out_free_descs;
1963
244a8fe4 1964 for (size = 0; size < preferred && i < max_entries; size += len) {
87ad72a5
CH		 1965 dma_addr_t dma_addr;
1966
50cdb7c6 1967 len = min_t(u64, chunk_size, preferred - size);
87ad72a5
CH		 1968 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1969 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1970 if (!bufs[i])
1971 break;
1972
1973 descs[i].addr = cpu_to_le64(dma_addr);
6c3c05b0 1974 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
87ad72a5
CH		 1975 i++;
1976 }
1977
92dc6895 1978 if (!size)
87ad72a5 1979 goto out_free_bufs;
87ad72a5 1980
87ad72a5
CH		 1981 dev->nr_host_mem_descs = i;
1982 dev->host_mem_size = size;
1983 dev->host_mem_descs = descs;
4033f35d 1984 dev->host_mem_descs_dma = descs_dma;
87ad72a5
CH		 1985 dev->host_mem_desc_bufs = bufs;
1986 return 0;
1987
1988out_free_bufs:
1989 while (--i >= 0) {
6c3c05b0 1990 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
87ad72a5 1991
cc667f6d
LD		 1992 dma_free_attrs(dev->dev, size, bufs[i],
1993 le64_to_cpu(descs[i].addr),
1994 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
87ad72a5
CH		 1995 }
1996
1997 kfree(bufs);
1998out_free_descs:
4033f35d
CH		 1999 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2000 descs_dma);
87ad72a5 2001out:
87ad72a5
CH		 2002 dev->host_mem_descs = NULL;
2003 return -ENOMEM;
2004}
2005
92dc6895
CH		 2006static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2007{
9dc54a0d
CK		 2008 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2009 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2010 u64 chunk_size;
92dc6895
CH		 2011
2012 /* start big and work our way down */
9dc54a0d 2013 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
92dc6895
CH		 2014 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2015 if (!min || dev->host_mem_size >= min)
2016 return 0;
2017 nvme_free_host_mem(dev);
2018 }
2019 }
2020
2021 return -ENOMEM;
2022}
2023
9620cfba 2024static int nvme_setup_host_mem(struct nvme_dev *dev)
87ad72a5
CH		 2025{
2026 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2027 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2028 u64 min = (u64)dev->ctrl.hmmin * 4096;
2029 u32 enable_bits = NVME_HOST_MEM_ENABLE;
6fbcde66 2030 int ret;
87ad72a5 2031
acb71e53
CH		 2032 if (!dev->ctrl.hmpre)
2033 return 0;
2034
87ad72a5
CH		 2035 preferred = min(preferred, max);
2036 if (min > max) {
2037 dev_warn(dev->ctrl.device,
2038 "min host memory (%lld MiB) above limit (%d MiB).\n",
2039 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2040 nvme_free_host_mem(dev);
9620cfba 2041 return 0;
87ad72a5
CH		 2042 }
2043
2044 /*
2045 * If we already have a buffer allocated check if we can reuse it.
2046 */
2047 if (dev->host_mem_descs) {
2048 if (dev->host_mem_size >= min)
2049 enable_bits |= NVME_HOST_MEM_RETURN;
2050 else
2051 nvme_free_host_mem(dev);
2052 }
2053
2054 if (!dev->host_mem_descs) {
92dc6895
CH		 2055 if (nvme_alloc_host_mem(dev, min, preferred)) {
2056 dev_warn(dev->ctrl.device,
2057 "failed to allocate host memory buffer.\n");
9620cfba 2058 return 0; /* controller must work without HMB */
92dc6895
CH		 2059 }
2060
2061 dev_info(dev->ctrl.device,
2062 "allocated %lld MiB host memory buffer.\n",
2063 dev->host_mem_size >> ilog2(SZ_1M));
87ad72a5
CH		 2064 }
2065
9620cfba
CH		 2066 ret = nvme_set_host_mem(dev, enable_bits);
2067 if (ret)
87ad72a5 2068 nvme_free_host_mem(dev);
9620cfba 2069 return ret;
9d713c2b
KB		 2070}
2071
0521905e
KB		 2072static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2073 char *buf)
2074{
2075 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2076
2077 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2078 ndev->cmbloc, ndev->cmbsz);
2079}
2080static DEVICE_ATTR_RO(cmb);
2081
1751e97a
KB		 2082static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2083 char *buf)
2084{
2085 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2086
2087 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2088}
2089static DEVICE_ATTR_RO(cmbloc);
2090
2091static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2092 char *buf)
2093{
2094 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2095
2096 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2097}
2098static DEVICE_ATTR_RO(cmbsz);
2099
a5df5e79
KB		 2100static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2101 char *buf)
2102{
2103 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2104
2105 return sysfs_emit(buf, "%d\n", ndev->hmb);
2106}
2107
2108static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2109 const char *buf, size_t count)
2110{
2111 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2112 bool new;
2113 int ret;
2114
99722c8a 2115 if (kstrtobool(buf, &new) < 0)
a5df5e79
KB		 2116 return -EINVAL;
2117
2118 if (new == ndev->hmb)
2119 return count;
2120
2121 if (new) {
2122 ret = nvme_setup_host_mem(ndev);
2123 } else {
2124 ret = nvme_set_host_mem(ndev, 0);
2125 if (!ret)
2126 nvme_free_host_mem(ndev);
2127 }
2128
2129 if (ret < 0)
2130 return ret;
2131
2132 return count;
2133}
2134static DEVICE_ATTR_RW(hmb);
2135
0521905e
KB		 2136static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2137 struct attribute *a, int n)
2138{
2139 struct nvme_ctrl *ctrl =
2140 dev_get_drvdata(container_of(kobj, struct device, kobj));
2141 struct nvme_dev *dev = to_nvme_dev(ctrl);
2142
1751e97a
KB		 2143 if (a == &dev_attr_cmb.attr ||
2144 a == &dev_attr_cmbloc.attr ||
2145 a == &dev_attr_cmbsz.attr) {
2146 if (!dev->cmbsz)
2147 return 0;
2148 }
a5df5e79
KB		 2149 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2150 return 0;
2151
0521905e
KB		 2152 return a->mode;
2153}
2154
2155static struct attribute *nvme_pci_attrs[] = {
2156 &dev_attr_cmb.attr,
1751e97a
KB		 2157 &dev_attr_cmbloc.attr,
2158 &dev_attr_cmbsz.attr,
a5df5e79 2159 &dev_attr_hmb.attr,
0521905e
KB		 2160 NULL,
2161};
2162
86adbf0c 2163static const struct attribute_group nvme_pci_dev_attrs_group = {
0521905e
KB		 2164 .attrs = nvme_pci_attrs,
2165 .is_visible = nvme_pci_attrs_are_visible,
2166};
2167
86adbf0c
CH		 2168static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2169 &nvme_dev_attrs_group,
2170 &nvme_pci_dev_attrs_group,
2171 NULL,
2172};
2173
612b7286
ML		 2174/*
2175 * nirqs is the number of interrupts available for write and read
2176 * queues. The core already reserved an interrupt for the admin queue.
2177 */
2178static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
3b6592f7 2179{
612b7286 2180 struct nvme_dev *dev = affd->priv;
2a5bcfdd 2181 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
3b6592f7
JA		 2182
2183 /*
ee0d96d3 2184 * If there is no interrupt available for queues, ensure that
612b7286
ML		 2185 * the default queue is set to 1. The affinity set size is
2186 * also set to one, but the irq core ignores it for this case.
2187 *
2188 * If only one interrupt is available or 'write_queue' == 0, combine
2189 * write and read queues.
2190 *
2191 * If 'write_queues' > 0, ensure it leaves room for at least one read
2192 * queue.
3b6592f7 2193 */
612b7286
ML		 2194 if (!nrirqs) {
2195 nrirqs = 1;
2196 nr_read_queues = 0;
2a5bcfdd 2197 } else if (nrirqs == 1 || !nr_write_queues) {
612b7286 2198 nr_read_queues = 0;
2a5bcfdd 2199 } else if (nr_write_queues >= nrirqs) {
612b7286 2200 nr_read_queues = 1;
3b6592f7 2201 } else {
2a5bcfdd 2202 nr_read_queues = nrirqs - nr_write_queues;
3b6592f7 2203 }
612b7286
ML		 2204
2205 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2206 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2207 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2208 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2209 affd->nr_sets = nr_read_queues ? 2 : 1;
3b6592f7
JA		 2210}
2211
6451fe73 2212static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
3b6592f7
JA		 2213{
2214 struct pci_dev *pdev = to_pci_dev(dev->dev);
3b6592f7 2215 struct irq_affinity affd = {
9cfef55b 2216 .pre_vectors = 1,
612b7286
ML		 2217 .calc_sets = nvme_calc_irq_sets,
2218 .priv = dev,
3b6592f7 2219 };
21cc2f3f 2220 unsigned int irq_queues, poll_queues;
6451fe73
JA		 2221
2222 /*
21cc2f3f
JX		 2223 * Poll queues don't need interrupts, but we need at least one I/O queue
2224 * left over for non-polled I/O.
6451fe73 2225 */
21cc2f3f
JX		 2226 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2227 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
3b6592f7 2228
21cc2f3f
JX		 2229 /*
2230 * Initialize for the single interrupt case, will be updated in
2231 * nvme_calc_irq_sets().
2232 */
612b7286
ML		 2233 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2234 dev->io_queues[HCTX_TYPE_READ] = 0;
3b6592f7 2235
66341331 2236 /*
21cc2f3f
JX		 2237 * We need interrupts for the admin queue and each non-polled I/O queue,
2238 * but some Apple controllers require all queues to use the first
2239 * vector.
66341331 2240 */
21cc2f3f
JX		 2241 irq_queues = 1;
2242 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2243 irq_queues += (nr_io_queues - poll_queues);
612b7286
ML		 2244 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2245 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
3b6592f7
JA		 2246}
2247
2a5bcfdd
WZ		 2248static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2249{
e3aef095
NS		 2250 /*
2251 * If tags are shared with admin queue (Apple bug), then
2252 * make sure we only use one IO queue.
2253 */
2254 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2255 return 1;
2a5bcfdd
WZ		 2256 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2257}
2258
8d85fce7 2259static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2260{
147b27e4 2261 struct nvme_queue *adminq = &dev->queues[0];
e75ec752 2262 struct pci_dev *pdev = to_pci_dev(dev->dev);
2a5bcfdd 2263 unsigned int nr_io_queues;
97f6ef64 2264 unsigned long size;
2a5bcfdd 2265 int result;
b60503ba 2266
2a5bcfdd
WZ		 2267 /*
2268 * Sample the module parameters once at reset time so that we have
2269 * stable values to work with.
2270 */
2271 dev->nr_write_queues = write_queues;
2272 dev->nr_poll_queues = poll_queues;
d38e9f04 2273
e3aef095 2274 nr_io_queues = dev->nr_allocated_queues - 1;
9a0be7ab
CH		 2275 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2276 if (result < 0)
1b23484b 2277 return result;
9a0be7ab 2278
f5fa90dc 2279 if (nr_io_queues == 0)
a5229050 2280 return 0;
53dc180e 2281
e4b9852a
CC		 2282 /*
2283 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2284 * from set to unset. If there is a window to it is truely freed,
2285 * pci_free_irq_vectors() jumping into this window will crash.
2286 * And take lock to avoid racing with pci_free_irq_vectors() in
2287 * nvme_dev_disable() path.
2288 */
2289 result = nvme_setup_io_queues_trylock(dev);
2290 if (result)
2291 return result;
2292 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2293 pci_free_irq(pdev, 0, adminq);
b60503ba 2294
0f238ff5 2295 if (dev->cmb_use_sqes) {
8ffaadf7
JD		 2296 result = nvme_cmb_qdepth(dev, nr_io_queues,
2297 sizeof(struct nvme_command));
88d356ca 2298 if (result > 0) {
8ffaadf7 2299 dev->q_depth = result;
88d356ca
CH		 2300 dev->ctrl.sqsize = result - 1;
2301 } else {
0f238ff5 2302 dev->cmb_use_sqes = false;
88d356ca 2303 }
8ffaadf7
JD		 2304 }
2305
97f6ef64
XY		 2306 do {
2307 size = db_bar_size(dev, nr_io_queues);
2308 result = nvme_remap_bar(dev, size);
2309 if (!result)
2310 break;
e4b9852a
CC		 2311 if (!--nr_io_queues) {
2312 result = -ENOMEM;
2313 goto out_unlock;
2314 }
97f6ef64
XY		 2315 } while (1);
2316 adminq->q_db = dev->dbs;
f1938f6e 2317
8fae268b 2318 retry:
9d713c2b 2319 /* Deregister the admin queue's interrupt */
e4b9852a
CC		 2320 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2321 pci_free_irq(pdev, 0, adminq);
9d713c2b 2322
e32efbfc
JA		 2323 /*
2324 * If we enable msix early due to not intx, disable it again before
2325 * setting up the full range we need.
2326 */
dca51e78 2327 pci_free_irq_vectors(pdev);
3b6592f7
JA		 2328
2329 result = nvme_setup_irqs(dev, nr_io_queues);
e4b9852a
CC		 2330 if (result <= 0) {
2331 result = -EIO;
2332 goto out_unlock;
2333 }
3b6592f7 2334
22b55601 2335 dev->num_vecs = result;
4b04cc6a 2336 result = max(result - 1, 1);
e20ba6e1 2337 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
fa08a396 2338
063a8096
MW		 2339 /*
2340 * Should investigate if there's a performance win from allocating
2341 * more queues than interrupt vectors; it might allow the submission
2342 * path to scale better, even if the receive path is limited by the
2343 * number of interrupts.
2344 */
dca51e78 2345 result = queue_request_irq(adminq);
7c349dde 2346 if (result)
e4b9852a 2347 goto out_unlock;
4e224106 2348 set_bit(NVMEQ_ENABLED, &adminq->flags);
e4b9852a 2349 mutex_unlock(&dev->shutdown_lock);
8fae268b
KB		 2350
2351 result = nvme_create_io_queues(dev);
2352 if (result || dev->online_queues < 2)
2353 return result;
2354
2355 if (dev->online_queues - 1 < dev->max_qid) {
2356 nr_io_queues = dev->online_queues - 1;
7d879c90 2357 nvme_delete_io_queues(dev);
e4b9852a
CC		 2358 result = nvme_setup_io_queues_trylock(dev);
2359 if (result)
2360 return result;
8fae268b
KB		 2361 nvme_suspend_io_queues(dev);
2362 goto retry;
2363 }
2364 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2365 dev->io_queues[HCTX_TYPE_DEFAULT],
2366 dev->io_queues[HCTX_TYPE_READ],
2367 dev->io_queues[HCTX_TYPE_POLL]);
2368 return 0;
e4b9852a
CC		 2369out_unlock:
2370 mutex_unlock(&dev->shutdown_lock);
2371 return result;
b60503ba
MW		 2372}
2373
de671d61
JA		 2374static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2375 blk_status_t error)
a5768aa8 2376{
db3cbfff 2377 struct nvme_queue *nvmeq = req->end_io_data;
b5875222 2378
db3cbfff 2379 blk_mq_free_request(req);
d1ed6aa1 2380 complete(&nvmeq->delete_done);
de671d61 2381 return RQ_END_IO_NONE;
a5768aa8
KB		 2382}
2383
de671d61
JA		 2384static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2385 blk_status_t error)
a5768aa8 2386{
db3cbfff 2387 struct nvme_queue *nvmeq = req->end_io_data;
a5768aa8 2388
d1ed6aa1
CH		 2389 if (error)
2390 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
db3cbfff 2391
de671d61 2392 return nvme_del_queue_end(req, error);
a5768aa8
KB		 2393}
2394
db3cbfff 2395static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
bda4e0fb 2396{
db3cbfff
KB		 2397 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2398 struct request *req;
f66e2804 2399 struct nvme_command cmd = { };
bda4e0fb 2400
db3cbfff
KB		 2401 cmd.delete_queue.opcode = opcode;
2402 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
bda4e0fb 2403
e559398f 2404 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
db3cbfff
KB		 2405 if (IS_ERR(req))
2406 return PTR_ERR(req);
e559398f 2407 nvme_init_request(req, &cmd);
bda4e0fb 2408
e2e53086
CH		 2409 if (opcode == nvme_admin_delete_cq)
2410 req->end_io = nvme_del_cq_end;
2411 else
2412 req->end_io = nvme_del_queue_end;
db3cbfff
KB		 2413 req->end_io_data = nvmeq;
2414
d1ed6aa1 2415 init_completion(&nvmeq->delete_done);
e2e53086 2416 blk_execute_rq_nowait(req, false);
db3cbfff 2417 return 0;
bda4e0fb
KB		 2418}
2419
7d879c90 2420static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
a5768aa8 2421{
5271edd4 2422 int nr_queues = dev->online_queues - 1, sent = 0;
db3cbfff 2423 unsigned long timeout;
a5768aa8 2424
db3cbfff 2425 retry:
dc96f938 2426 timeout = NVME_ADMIN_TIMEOUT;
5271edd4
CH		 2427 while (nr_queues > 0) {
2428 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2429 break;
2430 nr_queues--;
2431 sent++;
db3cbfff 2432 }
d1ed6aa1
CH		 2433 while (sent) {
2434 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2435
2436 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
5271edd4
CH		 2437 timeout);
2438 if (timeout == 0)
2439 return false;
d1ed6aa1 2440
d1ed6aa1 2441 sent--;
5271edd4
CH		 2442 if (nr_queues)
2443 goto retry;
2444 }
2445 return true;
a5768aa8
KB		 2446}
2447
7d879c90 2448static void nvme_delete_io_queues(struct nvme_dev *dev)
b60503ba 2449{
7d879c90
CH		 2450 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2451 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2452}
2b1b7e78 2453
0da7feaa 2454static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
b60503ba 2455{
2455a4b7 2456 if (dev->io_queues[HCTX_TYPE_POLL])
0da7feaa
CH		 2457 return 3;
2458 if (dev->io_queues[HCTX_TYPE_READ])
2459 return 2;
2460 return 1;
2455a4b7 2461}
949928c1 2462
2455a4b7
CH		 2463static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2464{
2465 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2466 /* free previously allocated queues that are no longer usable */
2467 nvme_free_queues(dev, dev->online_queues);
b60503ba
MW		 2468}
2469
b00a726a 2470static int nvme_pci_enable(struct nvme_dev *dev)
0877cb0d 2471{
b00a726a 2472 int result = -ENOMEM;
e75ec752 2473 struct pci_dev *pdev = to_pci_dev(dev->dev);
4bdf2603 2474 int dma_address_bits = 64;
0877cb0d
KB		 2475
2476 if (pci_enable_device_mem(pdev))
2477 return result;
2478
0877cb0d 2479 pci_set_master(pdev);
0877cb0d 2480
4bdf2603
FS		 2481 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2482 dma_address_bits = 48;
2483 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
052d0efa 2484 goto disable;
0877cb0d 2485
7a67cbea 2486 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
0e53d180 2487 result = -ENODEV;
b00a726a 2488 goto disable;
0e53d180 2489 }
e32efbfc
JA		 2490
2491 /*
a5229050
KB		 2492 * Some devices and/or platforms don't advertise or work with INTx
2493 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2494 * adjust this later.
e32efbfc 2495 */
dca51e78
CH		 2496 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2497 if (result < 0)
09113abf 2498 goto disable;
e32efbfc 2499
20d0dfe6 2500 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
7a67cbea 2501
7442ddce 2502 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
b27c1e68 2503 io_queue_depth);
20d0dfe6 2504 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
7a67cbea 2505 dev->dbs = dev->bar + 4096;
1f390c1f 2506
66341331
BH		 2507 /*
2508 * Some Apple controllers require a non-standard SQE size.
2509 * Interestingly they also seem to ignore the CC:IOSQES register
2510 * so we don't bother updating it here.
2511 */
2512 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2513 dev->io_sqes = 7;
2514 else
2515 dev->io_sqes = NVME_NVM_IOSQES;
1f390c1f
SG		 2516
2517 /*
2518 * Temporary fix for the Apple controller found in the MacBook8,1 and
2519 * some MacBook7,1 to avoid controller resets and data loss.
2520 */
2521 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2522 dev->q_depth = 2;
9bdcfb10
CH		 2523 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2524 "set queue depth=%u to work around controller resets\n",
1f390c1f 2525 dev->q_depth);
d554b5e1
MP		 2526 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2527 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
20d0dfe6 2528 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
d554b5e1
MP		 2529 dev->q_depth = 64;
2530 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2531 "set queue depth=%u\n", dev->q_depth);
1f390c1f
SG		 2532 }
2533
d38e9f04
BH		 2534 /*
2535 * Controllers with the shared tags quirk need the IO queue to be
2536 * big enough so that we get 32 tags for the admin queue
2537 */
2538 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2539 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2540 dev->q_depth = NVME_AQ_DEPTH + 2;
2541 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2542 dev->q_depth);
2543 }
88d356ca 2544 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
d38e9f04 2545
f65efd6d 2546 nvme_map_cmb(dev);
202021c1 2547
a0a3408e
KB		 2548 pci_enable_pcie_error_reporting(pdev);
2549 pci_save_state(pdev);
a6ee7f19 2550
09113abf
TZ		 2551 result = nvme_pci_configure_admin_queue(dev);
2552 if (result)
2553 goto free_irq;
2554 return result;
0877cb0d 2555
09113abf
TZ		 2556 free_irq:
2557 pci_free_irq_vectors(pdev);
0877cb0d 2558 disable:
0877cb0d
KB		 2559 pci_disable_device(pdev);
2560 return result;
2561}
2562
2563static void nvme_dev_unmap(struct nvme_dev *dev)
b00a726a
KB		 2564{
2565 if (dev->bar)
2566 iounmap(dev->bar);
a1f447b3 2567 pci_release_mem_regions(to_pci_dev(dev->dev));
b00a726a
KB		 2568}
2569
68e81eba 2570static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
0877cb0d 2571{
e75ec752 2572 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2573 u32 csts;
e75ec752 2574
68e81eba
CH		 2575 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2576 return true;
2577 if (pdev->error_state != pci_channel_io_normal)
2578 return true;
0877cb0d 2579
68e81eba
CH		 2580 csts = readl(dev->bar + NVME_REG_CSTS);
2581 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
4d115420
KB		 2582}
2583
a5cdb68c 2584static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
b60503ba 2585{
302ad8cc 2586 struct pci_dev *pdev = to_pci_dev(dev->dev);
68e81eba 2587 bool dead;
22404274 2588
77bf25ea 2589 mutex_lock(&dev->shutdown_lock);
68e81eba
CH		 2590 dead = nvme_pci_ctrl_is_dead(dev);
2591 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2592 dev->ctrl.state == NVME_CTRL_RESETTING) {
2593 if (pci_is_enabled(pdev))
302ad8cc 2594 nvme_start_freeze(&dev->ctrl);
68e81eba
CH		 2595 /*
2596 * Give the controller a chance to complete all entered requests
2597 * if doing a safe shutdown.
2598 */
2599 if (!dead && shutdown)
2600 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
c9d3bf88 2601 }
c21377f8 2602
9f27bd70 2603 nvme_quiesce_io_queues(&dev->ctrl);
87ad72a5 2604
64ee0ac0 2605 if (!dead && dev->ctrl.queue_count > 0) {
7d879c90 2606 nvme_delete_io_queues(dev);
47d42d22
CH		 2607 nvme_disable_ctrl(&dev->ctrl, shutdown);
2608 nvme_poll_irqdisable(&dev->queues[0]);
4d115420 2609 }
8fae268b 2610 nvme_suspend_io_queues(dev);
10981f23 2611 nvme_suspend_queue(dev, 0);
c80767f7
CH		 2612 pci_free_irq_vectors(pdev);
2613 if (pci_is_enabled(pdev)) {
2614 pci_disable_pcie_error_reporting(pdev);
2615 pci_disable_device(pdev);
2616 }
fa46c6fb 2617 nvme_reap_pending_cqes(dev);
07836e65 2618
1fcfca78
GL		 2619 nvme_cancel_tagset(&dev->ctrl);
2620 nvme_cancel_admin_tagset(&dev->ctrl);
302ad8cc
KB		 2621
2622 /*
2623 * The driver will not be starting up queues again if shutting down so
2624 * must flush all entered requests to their failed completion to avoid
2625 * deadlocking blk-mq hot-cpu notifier.
2626 */
c8e9e9b7 2627 if (shutdown) {
9f27bd70 2628 nvme_unquiesce_io_queues(&dev->ctrl);
c8e9e9b7 2629 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
9f27bd70 2630 nvme_unquiesce_admin_queue(&dev->ctrl);
c8e9e9b7 2631 }
77bf25ea 2632 mutex_unlock(&dev->shutdown_lock);
b60503ba
MW		 2633}
2634
c1ac9a4b
KB		 2635static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2636{
2637 if (!nvme_wait_reset(&dev->ctrl))
2638 return -EBUSY;
2639 nvme_dev_disable(dev, shutdown);
2640 return 0;
2641}
2642
091b6092
MW		 2643static int nvme_setup_prp_pools(struct nvme_dev *dev)
2644{
e75ec752 2645 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
c61b82c7
CH		 2646 NVME_CTRL_PAGE_SIZE,
2647 NVME_CTRL_PAGE_SIZE, 0);
091b6092
MW		 2648 if (!dev->prp_page_pool)
2649 return -ENOMEM;
2650
99802a7a 2651 /* Optimisation for I/Os between 4k and 128k */
e75ec752 2652 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
99802a7a
MW		 2653 256, 256, 0);
2654 if (!dev->prp_small_pool) {
2655 dma_pool_destroy(dev->prp_page_pool);
2656 return -ENOMEM;
2657 }
091b6092
MW		 2658 return 0;
2659}
2660
2661static void nvme_release_prp_pools(struct nvme_dev *dev)
2662{
2663 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2664 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2665}
2666
081a7d95
CH		 2667static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2668{
2669 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
2670 size_t alloc_size = sizeof(__le64 *) * npages +
2671 sizeof(struct scatterlist) * NVME_MAX_SEGS;
2672
2673 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2674 dev->iod_mempool = mempool_create_node(1,
2675 mempool_kmalloc, mempool_kfree,
2676 (void *)alloc_size, GFP_KERNEL,
2677 dev_to_node(dev->dev));
2678 if (!dev->iod_mempool)
2679 return -ENOMEM;
2680 return 0;
2681}
2682
770597ec
KB		 2683static void nvme_free_tagset(struct nvme_dev *dev)
2684{
2685 if (dev->tagset.tags)
0da7feaa 2686 nvme_remove_io_tag_set(&dev->ctrl);
770597ec
KB		 2687 dev->ctrl.tagset = NULL;
2688}
2689
2e87570b 2690/* pairs with nvme_pci_alloc_dev */
1673f1f0 2691static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
5e82e952 2692{
1673f1f0 2693 struct nvme_dev *dev = to_nvme_dev(ctrl);
9ac27090 2694
770597ec 2695 nvme_free_tagset(dev);
253fd4ac
IR		 2696 put_device(dev->dev);
2697 kfree(dev->queues);
5e82e952
KB		 2698 kfree(dev);
2699}
2700
fd634f41 2701static void nvme_reset_work(struct work_struct *work)
5e82e952 2702{
d86c4d8e
CH		 2703 struct nvme_dev *dev =
2704 container_of(work, struct nvme_dev, ctrl.reset_work);
a98e58e5 2705 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
e71afda4 2706 int result;
5e82e952 2707
7764656b
ZC		 2708 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2709 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2710 dev->ctrl.state);
8cb9f10b 2711 return;
e71afda4 2712 }
5e82e952 2713
fd634f41
CH		 2714 /*
2715 * If we're called to reset a live controller first shut it down before
2716 * moving on.
2717 */
b00a726a 2718 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
a5cdb68c 2719 nvme_dev_disable(dev, false);
d6135c3a 2720 nvme_sync_queues(&dev->ctrl);
5e82e952 2721
5c959d73 2722 mutex_lock(&dev->shutdown_lock);
b00a726a 2723 result = nvme_pci_enable(dev);
f0b50732 2724 if (result)
4726bcf3 2725 goto out_unlock;
9f27bd70 2726 nvme_unquiesce_admin_queue(&dev->ctrl);
5c959d73
KB		 2727 mutex_unlock(&dev->shutdown_lock);
2728
2729 /*
2730 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2731 * initializing procedure here.
2732 */
2733 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2734 dev_warn(dev->ctrl.device,
2735 "failed to mark controller CONNECTING\n");
cee6c269 2736 result = -EBUSY;
5c959d73
KB		 2737 goto out;
2738 }
943e942e 2739
94cc781f 2740 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
ce4541f4 2741 if (result)
f58944e2 2742 goto out;
ce4541f4 2743
65a54646 2744 nvme_dbbuf_dma_alloc(dev);
f9f38e33 2745
acb71e53
CH		 2746 result = nvme_setup_host_mem(dev);
2747 if (result < 0)
2748 goto out;
87ad72a5 2749
f0b50732 2750 result = nvme_setup_io_queues(dev);
badc34d4 2751 if (result)
f58944e2 2752 goto out;
f0b50732 2753
2659e57b 2754 /*
eac3ef26
CH		 2755 * Freeze and update the number of I/O queues as thos might have
2756 * changed. If there are no I/O queues left after this reset, keep the
2757 * controller around but remove all namespaces.
2659e57b 2758 */
eac3ef26 2759 if (dev->online_queues > 1) {
9f27bd70 2760 nvme_unquiesce_io_queues(&dev->ctrl);
302ad8cc 2761 nvme_wait_freeze(&dev->ctrl);
eac3ef26 2762 nvme_pci_update_nr_queues(dev);
2455a4b7 2763 nvme_dbbuf_set(dev);
302ad8cc 2764 nvme_unfreeze(&dev->ctrl);
3cf519b5 2765 } else {
eac3ef26
CH		 2766 dev_warn(dev->ctrl.device, "IO queues lost\n");
2767 nvme_mark_namespaces_dead(&dev->ctrl);
9f27bd70 2768 nvme_unquiesce_io_queues(&dev->ctrl);
eac3ef26
CH		 2769 nvme_remove_namespaces(&dev->ctrl);
2770 nvme_free_tagset(dev);
3cf519b5
CH		 2771 }
2772
2b1b7e78
JW		 2773 /*
2774 * If only admin queue live, keep it to do further investigation or
2775 * recovery.
2776 */
5d02a5c1 2777 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2b1b7e78 2778 dev_warn(dev->ctrl.device,
5d02a5c1 2779 "failed to mark controller live state\n");
e71afda4 2780 result = -ENODEV;
bb8d261e
CH		 2781 goto out;
2782 }
92911a55 2783
d09f2b45 2784 nvme_start_ctrl(&dev->ctrl);
3cf519b5 2785 return;
f0b50732 2786
4726bcf3
KB		 2787 out_unlock:
2788 mutex_unlock(&dev->shutdown_lock);
3cf519b5 2789 out:
c7c16c5b
CH		 2790 /*
2791 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2792 * may be holding this pci_dev's device lock.
2793 */
2794 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2795 result);
2796 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2797 nvme_dev_disable(dev, true);
2798 nvme_mark_namespaces_dead(&dev->ctrl);
2799 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
9a6b9458
KB		 2800}
2801
1c63dc66 2802static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
9ca97374 2803{
1c63dc66 2804 *val = readl(to_nvme_dev(ctrl)->bar + off);
90667892 2805 return 0;
9ca97374
TH		 2806}
2807
5fd4ce1b 2808static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
4cc06521 2809{
5fd4ce1b
CH		 2810 writel(val, to_nvme_dev(ctrl)->bar + off);
2811 return 0;
2812}
4cc06521 2813
7fd8930f
CH		 2814static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2815{
3a8ecc93 2816 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
7fd8930f 2817 return 0;
4cc06521
KB		 2818}
2819
97c12223
KB		 2820static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2821{
2822 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2823
2db24e4a 2824 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
97c12223
KB		 2825}
2826
2f0dad17
KB		 2827static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2828{
2829 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2830 struct nvme_subsystem *subsys = ctrl->subsys;
2831
2832 dev_err(ctrl->device,
2833 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2834 pdev->vendor, pdev->device,
2835 nvme_strlen(subsys->model, sizeof(subsys->model)),
2836 subsys->model, nvme_strlen(subsys->firmware_rev,
2837 sizeof(subsys->firmware_rev)),
2838 subsys->firmware_rev);
2839}
2840
2f859441
LG		 2841static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2842{
2843 struct nvme_dev *dev = to_nvme_dev(ctrl);
2844
2845 return dma_pci_p2pdma_supported(dev->dev);
2846}
2847
1c63dc66 2848static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1a353d85 2849 .name = "pcie",
e439bb12 2850 .module = THIS_MODULE,
2f859441 2851 .flags = NVME_F_METADATA_SUPPORTED,
86adbf0c 2852 .dev_attr_groups = nvme_pci_dev_attr_groups,
1c63dc66 2853 .reg_read32 = nvme_pci_reg_read32,
5fd4ce1b 2854 .reg_write32 = nvme_pci_reg_write32,
7fd8930f 2855 .reg_read64 = nvme_pci_reg_read64,
1673f1f0 2856 .free_ctrl = nvme_pci_free_ctrl,
f866fc42 2857 .submit_async_event = nvme_pci_submit_async_event,
97c12223 2858 .get_address = nvme_pci_get_address,
2f0dad17 2859 .print_device_info = nvme_pci_print_device_info,
2f859441 2860 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
1c63dc66 2861};
4cc06521 2862
b00a726a
KB		 2863static int nvme_dev_map(struct nvme_dev *dev)
2864{
b00a726a
KB		 2865 struct pci_dev *pdev = to_pci_dev(dev->dev);
2866
a1f447b3 2867 if (pci_request_mem_regions(pdev, "nvme"))
b00a726a
KB		 2868 return -ENODEV;
2869
97f6ef64 2870 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
b00a726a
KB		 2871 goto release;
2872
9fa196e7 2873 return 0;
b00a726a 2874 release:
9fa196e7
MG		 2875 pci_release_mem_regions(pdev);
2876 return -ENODEV;
b00a726a
KB		 2877}
2878
8427bbc2 2879static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
ff5350a8
AL		 2880{
2881 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2882 /*
2883 * Several Samsung devices seem to drop off the PCIe bus
2884 * randomly when APST is on and uses the deepest sleep state.
2885 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2886 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2887 * 950 PRO 256GB", but it seems to be restricted to two Dell
2888 * laptops.
2889 */
2890 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2891 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2892 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2893 return NVME_QUIRK_NO_DEEPEST_PS;
8427bbc2
KHF		 2894 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2895 /*
2896 * Samsung SSD 960 EVO drops off the PCIe bus after system
467c77d4
JJ		 2897 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2898 * within few minutes after bootup on a Coffee Lake board -
2899 * ASUS PRIME Z370-A
8427bbc2
KHF		 2900 */
2901 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
467c77d4
JJ		 2902 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2903 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
8427bbc2 2904 return NVME_QUIRK_NO_APST;
1fae37ac
S		 2905 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2906 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2907 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2908 /*
2909 * Forcing to use host managed nvme power settings for
2910 * lowest idle power with quick resume latency on
2911 * Samsung and Toshiba SSDs based on suspend behavior
2912 * on Coffee Lake board for LENOVO C640
2913 */
2914 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2915 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2916 return NVME_QUIRK_SIMPLE_SUSPEND;
ff5350a8
AL		 2917 }
2918
2919 return 0;
2920}
2921
2e87570b
CH		 2922static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2923 const struct pci_device_id *id)
18119775 2924{
ff5350a8 2925 unsigned long quirks = id->driver_data;
2e87570b
CH		 2926 int node = dev_to_node(&pdev->dev);
2927 struct nvme_dev *dev;
2928 int ret = -ENOMEM;
b60503ba 2929
a4aea562 2930 if (node == NUMA_NO_NODE)
2fa84351 2931 set_dev_node(&pdev->dev, first_memory_node);
a4aea562
MB		 2932
2933 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba 2934 if (!dev)
2e87570b
CH		 2935 return NULL;
2936 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2e87570b 2937 mutex_init(&dev->shutdown_lock);
147b27e4 2938
2a5bcfdd
WZ		 2939 dev->nr_write_queues = write_queues;
2940 dev->nr_poll_queues = poll_queues;
2941 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2942 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2943 sizeof(struct nvme_queue), GFP_KERNEL, node);
b60503ba 2944 if (!dev->queues)
2e87570b 2945 goto out_free_dev;
b60503ba 2946
e75ec752 2947 dev->dev = get_device(&pdev->dev);
4cc06521 2948
8427bbc2 2949 quirks |= check_vendor_combination_bug(pdev);
2744d7a0 2950 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
df4f9bc4
DB		 2951 /*
2952 * Some systems use a bios work around to ask for D3 on
2953 * platforms that support kernel managed suspend.
2954 */
2955 dev_info(&pdev->dev,
2956 "platform quirk: setting simple suspend\n");
2957 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2958 }
2e87570b
CH		 2959 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2960 quirks);
2961 if (ret)
2962 goto out_put_device;
3f30a79c
CH		 2963
2964 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2965 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
df4f9bc4 2966
943e942e 2967 /*
3f30a79c
CH		 2968 * Limit the max command size to prevent iod->sg allocations going
2969 * over a single page.
943e942e 2970 */
3f30a79c
CH		 2971 dev->ctrl.max_hw_sectors = min_t(u32,
2972 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9);
2973 dev->ctrl.max_segments = NVME_MAX_SEGS;
943e942e 2974
3f30a79c
CH		 2975 /*
2976 * There is no support for SGLs for metadata (yet), so we are limited to
2977 * a single integrity segment for the separate metadata pointer.
2978 */
2979 dev->ctrl.max_integrity_segments = 1;
2e87570b 2980 return dev;
df4f9bc4 2981
2e87570b
CH		 2982out_put_device:
2983 put_device(dev->dev);
2984 kfree(dev->queues);
2985out_free_dev:
2986 kfree(dev);
2987 return ERR_PTR(ret);
2988}
943e942e 2989
2e87570b
CH		 2990static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2991{
2992 struct nvme_dev *dev;
2993 int result = -ENOMEM;
2994
2995 dev = nvme_pci_alloc_dev(pdev, id);
2996 if (!dev)
2997 return -ENOMEM;
2998
2999 result = nvme_dev_map(dev);
b6e44b4c 3000 if (result)
2e87570b
CH		 3001 goto out_uninit_ctrl;
3002
3003 result = nvme_setup_prp_pools(dev);
081a7d95 3004 if (result)
2e87570b 3005 goto out_dev_unmap;
943e942e 3006
2e87570b 3007 result = nvme_pci_alloc_iod_mempool(dev);
b6e44b4c 3008 if (result)
2e87570b 3009 goto out_release_prp_pools;
b6e44b4c 3010
1b3c47c1
SG		 3011 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3012
eac3ef26
CH		 3013 result = nvme_pci_enable(dev);
3014 if (result)
3015 goto out_release_iod_mempool;
3016
0da7feaa
CH		 3017 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3018 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
eac3ef26
CH		 3019 if (result)
3020 goto out_disable;
3021
3022 /*
3023 * Mark the controller as connecting before sending admin commands to
3024 * allow the timeout handler to do the right thing.
3025 */
3026 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3027 dev_warn(dev->ctrl.device,
3028 "failed to mark controller CONNECTING\n");
3029 result = -EBUSY;
3030 goto out_disable;
3031 }
3032
3033 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3034 if (result)
3035 goto out_disable;
3036
3037 nvme_dbbuf_dma_alloc(dev);
3038
3039 result = nvme_setup_host_mem(dev);
3040 if (result < 0)
3041 goto out_disable;
3042
3043 result = nvme_setup_io_queues(dev);
3044 if (result)
3045 goto out_disable;
4caff8fc 3046
eac3ef26 3047 if (dev->online_queues > 1) {
0da7feaa
CH		 3048 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3049 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
eac3ef26 3050 nvme_dbbuf_set(dev);
eac3ef26
CH		 3051 }
3052
0da7feaa
CH		 3053 if (!dev->ctrl.tagset)
3054 dev_warn(dev->ctrl.device, "IO queues not created\n");
3055
eac3ef26
CH		 3056 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3057 dev_warn(dev->ctrl.device,
3058 "failed to mark controller live state\n");
3059 result = -ENODEV;
3060 goto out_disable;
3061 }
3062
2e87570b 3063 pci_set_drvdata(pdev, dev);
1b3c47c1 3064
eac3ef26
CH		 3065 nvme_start_ctrl(&dev->ctrl);
3066 nvme_put_ctrl(&dev->ctrl);
5a5754a4 3067 flush_work(&dev->ctrl.scan_work);
b60503ba
MW		 3068 return 0;
3069
eac3ef26
CH		 3070out_disable:
3071 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3072 nvme_dev_disable(dev, true);
3073 nvme_free_host_mem(dev);
3074 nvme_dev_remove_admin(dev);
3075 nvme_dbbuf_dma_free(dev);
3076 nvme_free_queues(dev, 0);
3077out_release_iod_mempool:
b6e44b4c 3078 mempool_destroy(dev->iod_mempool);
2e87570b 3079out_release_prp_pools:
091b6092 3080 nvme_release_prp_pools(dev);
2e87570b 3081out_dev_unmap:
b00c9b7a 3082 nvme_dev_unmap(dev);
2e87570b
CH		 3083out_uninit_ctrl:
3084 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3085 return result;
3086}
3087
775755ed 3088static void nvme_reset_prepare(struct pci_dev *pdev)
f0d54a54 3089{
a6739479 3090 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3091
3092 /*
3093 * We don't need to check the return value from waiting for the reset
3094 * state as pci_dev device lock is held, making it impossible to race
3095 * with ->remove().
3096 */
3097 nvme_disable_prepare_reset(dev, false);
3098 nvme_sync_queues(&dev->ctrl);
775755ed 3099}
f0d54a54 3100
775755ed
CH		 3101static void nvme_reset_done(struct pci_dev *pdev)
3102{
f263fbb8 3103 struct nvme_dev *dev = pci_get_drvdata(pdev);
c1ac9a4b
KB		 3104
3105 if (!nvme_try_sched_reset(&dev->ctrl))
3106 flush_work(&dev->ctrl.reset_work);
f0d54a54
KB		 3107}
3108
09ece142
KB		 3109static void nvme_shutdown(struct pci_dev *pdev)
3110{
3111 struct nvme_dev *dev = pci_get_drvdata(pdev);
4e523547 3112
c1ac9a4b 3113 nvme_disable_prepare_reset(dev, true);
09ece142
KB		 3114}
3115
f58944e2
KB		 3116/*
3117 * The driver's remove may be called on a device in a partially initialized
3118 * state. This function must not have any dependencies on the device state in
3119 * order to proceed.
3120 */
8d85fce7 3121static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 3122{
3123 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458 3124
bb8d261e 3125 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
9a6b9458 3126 pci_set_drvdata(pdev, NULL);
0ff9d4e1 3127
6db28eda 3128 if (!pci_device_is_present(pdev)) {
0ff9d4e1 3129 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1d39e692 3130 nvme_dev_disable(dev, true);
6db28eda 3131 }
0ff9d4e1 3132
d86c4d8e 3133 flush_work(&dev->ctrl.reset_work);
d09f2b45
SG		 3134 nvme_stop_ctrl(&dev->ctrl);
3135 nvme_remove_namespaces(&dev->ctrl);
a5cdb68c 3136 nvme_dev_disable(dev, true);
87ad72a5 3137 nvme_free_host_mem(dev);
a4aea562 3138 nvme_dev_remove_admin(dev);
c11b7716 3139 nvme_dbbuf_dma_free(dev);
a1a5ef99 3140 nvme_free_queues(dev, 0);
c11b7716 3141 mempool_destroy(dev->iod_mempool);
9a6b9458 3142 nvme_release_prp_pools(dev);
b00a726a 3143 nvme_dev_unmap(dev);
726612b6 3144 nvme_uninit_ctrl(&dev->ctrl);
b60503ba
MW		 3145}
3146
671a6018 3147#ifdef CONFIG_PM_SLEEP
d916b1be
KB		 3148static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3149{
3150 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3151}
3152
3153static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3154{
3155 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3156}
3157
3158static int nvme_resume(struct device *dev)
3159{
3160 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3161 struct nvme_ctrl *ctrl = &ndev->ctrl;
3162
4eaefe8c 3163 if (ndev->last_ps == U32_MAX ||
d916b1be 3164 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
e5ad96f3
KB		 3165 goto reset;
3166 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3167 goto reset;
3168
d916b1be 3169 return 0;
e5ad96f3
KB		 3170reset:
3171 return nvme_try_sched_reset(ctrl);
d916b1be
KB		 3172}
3173
cd638946
KB		 3174static int nvme_suspend(struct device *dev)
3175{
3176 struct pci_dev *pdev = to_pci_dev(dev);
3177 struct nvme_dev *ndev = pci_get_drvdata(pdev);
d916b1be
KB		 3178 struct nvme_ctrl *ctrl = &ndev->ctrl;
3179 int ret = -EBUSY;
3180
4eaefe8c
RW		 3181 ndev->last_ps = U32_MAX;
3182
d916b1be
KB		 3183 /*
3184 * The platform does not remove power for a kernel managed suspend so
3185 * use host managed nvme power settings for lowest idle power if
3186 * possible. This should have quicker resume latency than a full device
3187 * shutdown. But if the firmware is involved after the suspend or the
3188 * device does not support any non-default power states, shut down the
3189 * device fully.
4eaefe8c
RW		 3190 *
3191 * If ASPM is not enabled for the device, shut down the device and allow
3192 * the PCI bus layer to put it into D3 in order to take the PCIe link
3193 * down, so as to allow the platform to achieve its minimum low-power
3194 * state (which may not be possible if the link is up).
d916b1be 3195 */
4eaefe8c 3196 if (pm_suspend_via_firmware() || !ctrl->npss ||
cb32de1b 3197 !pcie_aspm_enabled(pdev) ||
c1ac9a4b
KB		 3198 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3199 return nvme_disable_prepare_reset(ndev, true);
d916b1be
KB		 3200
3201 nvme_start_freeze(ctrl);
3202 nvme_wait_freeze(ctrl);
3203 nvme_sync_queues(ctrl);
3204
5d02a5c1 3205 if (ctrl->state != NVME_CTRL_LIVE)
d916b1be
KB		 3206 goto unfreeze;
3207
e5ad96f3
KB		 3208 /*
3209 * Host memory access may not be successful in a system suspend state,
3210 * but the specification allows the controller to access memory in a
3211 * non-operational power state.
3212 */
3213 if (ndev->hmb) {
3214 ret = nvme_set_host_mem(ndev, 0);
3215 if (ret < 0)
3216 goto unfreeze;
3217 }
3218
d916b1be
KB		 3219 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3220 if (ret < 0)
3221 goto unfreeze;
3222
7cbb5c6f
ML		 3223 /*
3224 * A saved state prevents pci pm from generically controlling the
3225 * device's power. If we're using protocol specific settings, we don't
3226 * want pci interfering.
3227 */
3228 pci_save_state(pdev);
3229
d916b1be
KB		 3230 ret = nvme_set_power_state(ctrl, ctrl->npss);
3231 if (ret < 0)
3232 goto unfreeze;
3233
3234 if (ret) {
7cbb5c6f
ML		 3235 /* discard the saved state */
3236 pci_load_saved_state(pdev, NULL);
3237
d916b1be
KB		 3238 /*
3239 * Clearing npss forces a controller reset on resume. The
05d3046f 3240 * correct value will be rediscovered then.
d916b1be 3241 */
c1ac9a4b 3242 ret = nvme_disable_prepare_reset(ndev, true);
d916b1be 3243 ctrl->npss = 0;
d916b1be 3244 }
d916b1be
KB		 3245unfreeze:
3246 nvme_unfreeze(ctrl);
3247 return ret;
3248}
3249
3250static int nvme_simple_suspend(struct device *dev)
3251{
3252 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
4e523547 3253
c1ac9a4b 3254 return nvme_disable_prepare_reset(ndev, true);
cd638946
KB		 3255}
3256
d916b1be 3257static int nvme_simple_resume(struct device *dev)
cd638946
KB		 3258{
3259 struct pci_dev *pdev = to_pci_dev(dev);
3260 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 3261
c1ac9a4b 3262 return nvme_try_sched_reset(&ndev->ctrl);
cd638946
KB		 3263}
3264
21774222 3265static const struct dev_pm_ops nvme_dev_pm_ops = {
d916b1be
KB		 3266 .suspend = nvme_suspend,
3267 .resume = nvme_resume,
3268 .freeze = nvme_simple_suspend,
3269 .thaw = nvme_simple_resume,
3270 .poweroff = nvme_simple_suspend,
3271 .restore = nvme_simple_resume,
3272};
3273#endif /* CONFIG_PM_SLEEP */
b60503ba 3274
a0a3408e
KB		 3275static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3276 pci_channel_state_t state)
3277{
3278 struct nvme_dev *dev = pci_get_drvdata(pdev);
3279
3280 /*
3281 * A frozen channel requires a reset. When detected, this method will
3282 * shutdown the controller to quiesce. The controller will be restarted
3283 * after the slot reset through driver's slot_reset callback.
3284 */
a0a3408e
KB		 3285 switch (state) {
3286 case pci_channel_io_normal:
3287 return PCI_ERS_RESULT_CAN_RECOVER;
3288 case pci_channel_io_frozen:
d011fb31
KB		 3289 dev_warn(dev->ctrl.device,
3290 "frozen state error detected, reset controller\n");
a5cdb68c 3291 nvme_dev_disable(dev, false);
a0a3408e
KB		 3292 return PCI_ERS_RESULT_NEED_RESET;
3293 case pci_channel_io_perm_failure:
d011fb31
KB		 3294 dev_warn(dev->ctrl.device,
3295 "failure state error detected, request disconnect\n");
a0a3408e
KB		 3296 return PCI_ERS_RESULT_DISCONNECT;
3297 }
3298 return PCI_ERS_RESULT_NEED_RESET;
3299}
3300
3301static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3302{
3303 struct nvme_dev *dev = pci_get_drvdata(pdev);
3304
1b3c47c1 3305 dev_info(dev->ctrl.device, "restart after slot reset\n");
a0a3408e 3306 pci_restore_state(pdev);
d86c4d8e 3307 nvme_reset_ctrl(&dev->ctrl);
a0a3408e
KB		 3308 return PCI_ERS_RESULT_RECOVERED;
3309}
3310
3311static void nvme_error_resume(struct pci_dev *pdev)
3312{
72cd4cc2
KB		 3313 struct nvme_dev *dev = pci_get_drvdata(pdev);
3314
3315 flush_work(&dev->ctrl.reset_work);
a0a3408e
KB		 3316}
3317
1d352035 3318static const struct pci_error_handlers nvme_err_handler = {
b60503ba 3319 .error_detected = nvme_error_detected,
b60503ba
MW		 3320 .slot_reset = nvme_slot_reset,
3321 .resume = nvme_error_resume,
775755ed
CH		 3322 .reset_prepare = nvme_reset_prepare,
3323 .reset_done = nvme_reset_done,
b60503ba
MW		 3324};
3325
6eb0d698 3326static const struct pci_device_id nvme_id_table[] = {
972b13e2 3327 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
08095e70 3328 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3329 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3330 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
99466e70 3331 .driver_data = NVME_QUIRK_STRIPE_SIZE |
e850fd16 3332 NVME_QUIRK_DEALLOCATE_ZEROES, },
972b13e2 3333 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
99466e70 3334 .driver_data = NVME_QUIRK_STRIPE_SIZE |
25e58af4
WZ		 3335 NVME_QUIRK_DEALLOCATE_ZEROES |
3336 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
972b13e2 3337 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
f99cb7af
DWF		 3338 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3339 NVME_QUIRK_DEALLOCATE_ZEROES, },
50af47d0 3340 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
9abd68ef 3341 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
6c6aa2f2 3342 NVME_QUIRK_MEDIUM_PRIO_SQ |
ce4cc313
DM		 3343 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3344 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6299358d
JD		 3345 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3346 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
540c801c 3347 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
7b210e4e 3348 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
66dd346b
CH		 3349 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3350 NVME_QUIRK_BOGUS_NID, },
3351 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3352 .driver_data = NVME_QUIRK_BOGUS_NID, },
5bedd3af 3353 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
c98a8793
KB		 3354 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3355 NVME_QUIRK_BOGUS_NID, },
0302ae60 3356 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
5e112d3f
JE		 3357 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3358 NVME_QUIRK_NO_NS_DESC_LIST, },
54adc010
GP		 3359 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3360 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
8c97eecc
JL		 3361 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3362 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
015282c9
WW		 3363 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3364 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
d554b5e1
MP		 3365 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3366 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3367 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
7ee5c78c 3368 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
abbb5f59 3369 NVME_QUIRK_DISABLE_WRITE_ZEROES|
7ee5c78c 3370 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
2cf7a77e
KB		 3371 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3372 .driver_data = NVME_QUIRK_BOGUS_NID, },
c9e95c39 3373 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
73029c9b
KB		 3374 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3375 NVME_QUIRK_BOGUS_NID, },
d14c2731
TH		 3376 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3377 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3378 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3379 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
6e6a6828
PT		 3380 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3381 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3382 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
e1c70d79
LVS		 3383 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3384 .driver_data = NVME_QUIRK_BOGUS_NID, },
08b903b5 3385 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
1629de0e
PG		 3386 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3387 NVME_QUIRK_BOGUS_NID, },
f03e42c6
GC		 3388 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3389 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3390 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
41f38043
LS		 3391 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3392 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
d5ceb4d1
BH		 3393 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3394 .driver_data = NVME_QUIRK_BOGUS_NID, },
5611ec2b
KHF		 3395 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3396 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
c4f01a77
KB		 3397 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3398 .driver_data = NVME_QUIRK_BOGUS_NID, },
02ca079c
KHF		 3399 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3400 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
89919929
CK		 3401 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3402 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
43047e08 3403 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3404 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3405 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3406 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3407 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3408 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3409 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3410 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
dc22c1c0
ZB		 3411 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3412 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
538e4a8c
TL		 3413 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3414 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
ac9b57d4
XL		 3415 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3416 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3417 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3418 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3419 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3420 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3421 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3422 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3423 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3424 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
8d6e38f6
TDF		 3425 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3426 .driver_data = NVME_QUIRK_BOGUS_NID, },
70ce3455
CH		 3427 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3428 .driver_data = NVME_QUIRK_BOGUS_NID, },
a98a945b
CH		 3429 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3430 .driver_data = NVME_QUIRK_BOGUS_NID, },
3431 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3432 .driver_data = NVME_QUIRK_BOGUS_NID, },
3765fad5
SR		 3433 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3434 .driver_data = NVME_QUIRK_BOGUS_NID, },
f37527a0
DK		 3435 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3436 .driver_data = NVME_QUIRK_BOGUS_NID, },
d5d3c100
XR		 3437 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3438 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
6b961bce
NW		 3439 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3440 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
d6c52fa3
TG		 3441 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3442 .driver_data = NVME_QUIRK_BOGUS_NID, },
200dccd0
SA		 3443 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3444 .driver_data = NVME_QUIRK_BOGUS_NID, },
80b26240
A		 3445 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3446 .driver_data = NVME_QUIRK_BOGUS_NID, },
4bdf2603
FS		 3447 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3448 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3449 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3450 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3451 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3452 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3453 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3454 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3455 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3456 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3457 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3458 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
98f7b86a
AS		 3459 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3460 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
124298bd 3461 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
66341331
BH		 3462 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3463 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
d38e9f04 3464 NVME_QUIRK_128_BYTES_SQES |
a2941f6a 3465 NVME_QUIRK_SHARED_TAGS |
453116a4
HM		 3466 NVME_QUIRK_SKIP_CID_GEN |
3467 NVME_QUIRK_IDENTIFY_CNS },
0b85f59d 3468 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
b60503ba
MW		 3469 { 0, }
3470};
3471MODULE_DEVICE_TABLE(pci, nvme_id_table);
3472
3473static struct pci_driver nvme_driver = {
3474 .name = "nvme",
3475 .id_table = nvme_id_table,
3476 .probe = nvme_probe,
8d85fce7 3477 .remove = nvme_remove,
09ece142 3478 .shutdown = nvme_shutdown,
cd638946 3479 .driver = {
eac3ef26
CH		 3480 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3481#ifdef CONFIG_PM_SLEEP
3482 .pm = &nvme_dev_pm_ops,
d916b1be 3483#endif
eac3ef26 3484 },
74d986ab 3485 .sriov_configure = pci_sriov_configure_simple,
b60503ba
MW		 3486 .err_handler = &nvme_err_handler,
3487};
3488
3489static int __init nvme_init(void)
3490{
81101540
CH		 3491 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3492 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3493 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
612b7286 3494 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
c372cdd1
KB		 3495 BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) >
3496 S8_MAX);
01df742d 3497 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
17c33167 3498
9a6327d2 3499 return pci_register_driver(&nvme_driver);
b60503ba
MW		 3500}
3501
3502static void __exit nvme_exit(void)
3503{
3504 pci_unregister_driver(&nvme_driver);
03e0f3a6 3505 flush_workqueue(nvme_wq);
b60503ba
MW		 3506}
3507
3508MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3509MODULE_LICENSE("GPL");
c78b4713 3510MODULE_VERSION("1.0");
b60503ba
MW		 3511module_init(nvme_init);
3512module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)