[linux-2.6-block.git] / drivers / nvme / host / nvme.h

/*
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _NVME_H
#define _NVME_H

#include <linux/nvme.h>
#include <linux/pci.h>
#include <linux/kref.h>
#include <linux/blk-mq.h>

struct nvme_passthru_cmd;

extern unsigned char nvme_io_timeout;
#define NVME_IO_TIMEOUT	(nvme_io_timeout * HZ)

extern unsigned char admin_timeout;
#define ADMIN_TIMEOUT	(admin_timeout * HZ)

extern unsigned char shutdown_timeout;
#define SHUTDOWN_TIMEOUT	(shutdown_timeout * HZ)

enum {
	NVME_NS_LBA		= 0,
	NVME_NS_LIGHTNVM	= 1,
};

/*
 * List of workarounds for devices that required behavior not specified in
 * the standard.
 */
enum nvme_quirks {
	/*
	 * Prefers I/O aligned to a stripe size specified in a vendor
	 * specific Identify field.
	 */
	NVME_QUIRK_STRIPE_SIZE			= (1 << 0),
};

struct nvme_ctrl {
	const struct nvme_ctrl_ops *ops;
	struct request_queue *admin_q;
	struct device *dev;
	struct kref kref;
	int instance;

	char name[12];
	char serial[20];
	char model[40];
	char firmware_rev[8];

	u32 ctrl_config;

	u32 page_size;
	u16 oncs;
	u16 abort_limit;
	u8 event_limit;
	u8 vwc;
	unsigned long quirks;
};

/*
 * An NVM Express namespace is equivalent to a SCSI LUN
 */
struct nvme_ns {
	struct list_head list;

	struct nvme_ctrl *ctrl;
	struct request_queue *queue;
	struct gendisk *disk;
	struct kref kref;

	unsigned ns_id;
	int lba_shift;
	u16 ms;
	bool ext;
	u8 pi_type;
	int type;
	u64 mode_select_num_blocks;
	u32 mode_select_block_len;
};

struct nvme_ctrl_ops {
	int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
	int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
	void (*free_ctrl)(struct nvme_ctrl *ctrl);
};

static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
{
	u32 val = 0;

	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
		return false;
	return val & NVME_CSTS_RDY;
}

static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
{
	return (sector >> (ns->lba_shift - 9));
}

static inline void nvme_setup_flush(struct nvme_ns *ns,
		struct nvme_command *cmnd)
{
	memset(cmnd, 0, sizeof(*cmnd));
	cmnd->common.opcode = nvme_cmd_flush;
	cmnd->common.nsid = cpu_to_le32(ns->ns_id);
}

static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
		struct nvme_command *cmnd)
{
	u16 control = 0;
	u32 dsmgmt = 0;

	if (req->cmd_flags & REQ_FUA)
		control |= NVME_RW_FUA;
	if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
		control |= NVME_RW_LR;

	if (req->cmd_flags & REQ_RAHEAD)
		dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;

	memset(cmnd, 0, sizeof(*cmnd));
	cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
	cmnd->rw.command_id = req->tag;
	cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
	cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
	cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);

	if (ns->ms) {
		switch (ns->pi_type) {
		case NVME_NS_DPS_PI_TYPE3:
			control |= NVME_RW_PRINFO_PRCHK_GUARD;
			break;
		case NVME_NS_DPS_PI_TYPE1:
		case NVME_NS_DPS_PI_TYPE2:
			control |= NVME_RW_PRINFO_PRCHK_GUARD |
					NVME_RW_PRINFO_PRCHK_REF;
			cmnd->rw.reftag = cpu_to_le32(
					nvme_block_nr(ns, blk_rq_pos(req)));
			break;
		}
		if (!blk_integrity_rq(req))
			control |= NVME_RW_PRINFO_PRACT;
	}

	cmnd->rw.control = cpu_to_le16(control);
	cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
}


static inline int nvme_error_status(u16 status)
{
	switch (status & 0x7ff) {
	case NVME_SC_SUCCESS:
		return 0;
	case NVME_SC_CAP_EXCEEDED:
		return -ENOSPC;
	default:
		return -EIO;
	}
}

int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
void nvme_put_ns(struct nvme_ns *ns);

struct request *nvme_alloc_request(struct request_queue *q,
		struct nvme_command *cmd, unsigned int flags);
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buf, unsigned bufflen);
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
		void *buffer, unsigned bufflen,  u32 *result, unsigned timeout);
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen, u32 *result,
		unsigned timeout);
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
		void __user *ubuffer, unsigned bufflen,
		void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
		u32 *result, unsigned timeout);
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
		struct nvme_id_ns **id);
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
			dma_addr_t dma_addr, u32 *result);
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
			dma_addr_t dma_addr, u32 *result);

extern const struct block_device_operations nvme_fops;
extern spinlock_t dev_list_lock;

int nvme_revalidate_disk(struct gendisk *disk);
int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
			struct nvme_passthru_cmd __user *ucmd);

struct sg_io_hdr;

int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
int nvme_sg_get_version_num(int __user *ip);

int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
int nvme_nvm_register(struct request_queue *q, char *disk_name);
void nvme_nvm_unregister(struct request_queue *q, char *disk_name);

#endif /* _NVME_H */
Commit	Line	Data
f11bb3e2 CH	1	/*
	2	* Copyright (c) 2011-2014, Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*/
	13
	14	#ifndef _NVME_H
	15	#define _NVME_H
	16
	17	#include <linux/nvme.h>
	18	#include <linux/pci.h>
	19	#include <linux/kref.h>
	20	#include <linux/blk-mq.h>
	21
1673f1f0 CH	22	struct nvme_passthru_cmd;
1673f1f0 CH	23
f11bb3e2 CH	24	extern unsigned char nvme_io_timeout;
	25	#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
	26
21d34711 CH	27	extern unsigned char admin_timeout;
	28	#define ADMIN_TIMEOUT (admin_timeout * HZ)
	29
5fd4ce1b CH	30	extern unsigned char shutdown_timeout;
	31	#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
	32
ca064085 MB	33	enum {
	34	NVME_NS_LBA = 0,
	35	NVME_NS_LIGHTNVM = 1,
	36	};
	37
106198ed CH	38	/*
	39	* List of workarounds for devices that required behavior not specified in
	40	* the standard.
	41	*/
	42	enum nvme_quirks {
	43	/*
	44	* Prefers I/O aligned to a stripe size specified in a vendor
	45	* specific Identify field.
	46	*/
	47	NVME_QUIRK_STRIPE_SIZE = (1 << 0),
	48	};
	49
1c63dc66 CH	50	struct nvme_ctrl {
1c63dc66 CH	51	const struct nvme_ctrl_ops *ops;
f11bb3e2	52	struct request_queue *admin_q;
f11bb3e2	53	struct device *dev;
1673f1f0	54	struct kref kref;
f11bb3e2	55	int instance;
1c63dc66	56
f11bb3e2 CH	57	char name[12];
	58	char serial[20];
	59	char model[40];
	60	char firmware_rev[8];
5fd4ce1b CH	61
	62	u32 ctrl_config;
	63
	64	u32 page_size;
f11bb3e2 CH	65	u16 oncs;
	66	u16 abort_limit;
	67	u8 event_limit;
	68	u8 vwc;
106198ed	69	unsigned long quirks;
f11bb3e2 CH	70	};
	71
	72	/*
	73	* An NVM Express namespace is equivalent to a SCSI LUN
	74	*/
	75	struct nvme_ns {
	76	struct list_head list;
	77
1c63dc66	78	struct nvme_ctrl *ctrl;
f11bb3e2 CH	79	struct request_queue *queue;
	80	struct gendisk *disk;
	81	struct kref kref;
	82
	83	unsigned ns_id;
	84	int lba_shift;
	85	u16 ms;
	86	bool ext;
	87	u8 pi_type;
ca064085	88	int type;
f11bb3e2 CH	89	u64 mode_select_num_blocks;
	90	u32 mode_select_block_len;
	91	};
	92
1c63dc66 CH	93	struct nvme_ctrl_ops {
1c63dc66 CH	94	int (reg_read32)(struct nvme_ctrl ctrl, u32 off, u32 *val);
5fd4ce1b	95	int (reg_write32)(struct nvme_ctrl ctrl, u32 off, u32 val);
1673f1f0	96	void (free_ctrl)(struct nvme_ctrl ctrl);
1c63dc66 CH	97	};
	98
	99	static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
	100	{
	101	u32 val = 0;
	102
	103	if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
	104	return false;
	105	return val & NVME_CSTS_RDY;
	106	}
	107
f11bb3e2 CH	108	static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
	109	{
	110	return (sector >> (ns->lba_shift - 9));
	111	}
	112
22944e99 CH	113	static inline void nvme_setup_flush(struct nvme_ns *ns,
	114	struct nvme_command *cmnd)
	115	{
	116	memset(cmnd, 0, sizeof(*cmnd));
	117	cmnd->common.opcode = nvme_cmd_flush;
	118	cmnd->common.nsid = cpu_to_le32(ns->ns_id);
	119	}
	120
	121	static inline void nvme_setup_rw(struct nvme_ns ns, struct request req,
	122	struct nvme_command *cmnd)
	123	{
	124	u16 control = 0;
	125	u32 dsmgmt = 0;
	126
	127	if (req->cmd_flags & REQ_FUA)
	128	control \|= NVME_RW_FUA;
	129	if (req->cmd_flags & (REQ_FAILFAST_DEV \| REQ_RAHEAD))
	130	control \|= NVME_RW_LR;
	131
	132	if (req->cmd_flags & REQ_RAHEAD)
	133	dsmgmt \|= NVME_RW_DSM_FREQ_PREFETCH;
	134
	135	memset(cmnd, 0, sizeof(*cmnd));
	136	cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
	137	cmnd->rw.command_id = req->tag;
	138	cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
	139	cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
	140	cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
	141
	142	if (ns->ms) {
	143	switch (ns->pi_type) {
	144	case NVME_NS_DPS_PI_TYPE3:
	145	control \|= NVME_RW_PRINFO_PRCHK_GUARD;
	146	break;
	147	case NVME_NS_DPS_PI_TYPE1:
	148	case NVME_NS_DPS_PI_TYPE2:
	149	control \|= NVME_RW_PRINFO_PRCHK_GUARD \|
	150	NVME_RW_PRINFO_PRCHK_REF;
	151	cmnd->rw.reftag = cpu_to_le32(
	152	nvme_block_nr(ns, blk_rq_pos(req)));
	153	break;
	154	}
	155	if (!blk_integrity_rq(req))
	156	control \|= NVME_RW_PRINFO_PRACT;
	157	}
	158
	159	cmnd->rw.control = cpu_to_le16(control);
	160	cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
	161	}
	162
	163
15a190f7 CH	164	static inline int nvme_error_status(u16 status)
	165	{
	166	switch (status & 0x7ff) {
	167	case NVME_SC_SUCCESS:
	168	return 0;
	169	case NVME_SC_CAP_EXCEEDED:
	170	return -ENOSPC;
	171	default:
	172	return -EIO;
	173	}
	174	}
	175
5fd4ce1b CH	176	int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	177	int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
	178	int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
1673f1f0 CH	179	void nvme_put_ctrl(struct nvme_ctrl *ctrl);
	180	void nvme_put_ns(struct nvme_ns *ns);
	181
4160982e CH	182	struct request nvme_alloc_request(struct request_queue q,
4160982e CH	183	struct nvme_command *cmd, unsigned int flags);
f11bb3e2 CH	184	int nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
	185	void *buf, unsigned bufflen);
	186	int __nvme_submit_sync_cmd(struct request_queue q, struct nvme_command cmd,
4160982e CH	187	void buffer, unsigned bufflen, u32 result, unsigned timeout);
	188	int nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	189	void __user ubuffer, unsigned bufflen, u32 result,
	190	unsigned timeout);
0b7f1f26 KB	191	int __nvme_submit_user_cmd(struct request_queue q, struct nvme_command cmd,
	192	void __user *ubuffer, unsigned bufflen,
	193	void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
	194	u32 *result, unsigned timeout);
1c63dc66 CH	195	int nvme_identify_ctrl(struct nvme_ctrl dev, struct nvme_id_ctrl *id);
1c63dc66 CH	196	int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
f11bb3e2	197	struct nvme_id_ns **id);
1c63dc66 CH	198	int nvme_get_log_page(struct nvme_ctrl dev, struct nvme_smart_log *log);
1c63dc66 CH	199	int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
f11bb3e2	200	dma_addr_t dma_addr, u32 *result);
1c63dc66	201	int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
f11bb3e2 CH	202	dma_addr_t dma_addr, u32 *result);
f11bb3e2 CH	203
1673f1f0 CH	204	extern const struct block_device_operations nvme_fops;
	205	extern spinlock_t dev_list_lock;
	206
	207	int nvme_revalidate_disk(struct gendisk *disk);
	208	int nvme_user_cmd(struct nvme_ctrl ctrl, struct nvme_ns ns,
	209	struct nvme_passthru_cmd __user *ucmd);
	210
f11bb3e2 CH	211	struct sg_io_hdr;
	212
	213	int nvme_sg_io(struct nvme_ns ns, struct sg_io_hdr __user u_hdr);
	214	int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
	215	int nvme_sg_get_version_num(int __user *ip);
	216
ca064085 MB	217	int nvme_nvm_ns_supported(struct nvme_ns ns, struct nvme_id_ns id);
	218	int nvme_nvm_register(struct request_queue q, char disk_name);
	219	void nvme_nvm_unregister(struct request_queue q, char disk_name);
	220
f11bb3e2	221	#endif /* _NVME_H */