Commit | Line | Data |
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bc50ad75 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
f11bb3e2 CH |
2 | /* |
3 | * Copyright (c) 2011-2014, Intel Corporation. | |
f11bb3e2 CH |
4 | */ |
5 | ||
6 | #ifndef _NVME_H | |
7 | #define _NVME_H | |
8 | ||
9 | #include <linux/nvme.h> | |
a6a5149b | 10 | #include <linux/cdev.h> |
f11bb3e2 CH |
11 | #include <linux/pci.h> |
12 | #include <linux/kref.h> | |
13 | #include <linux/blk-mq.h> | |
a98e58e5 | 14 | #include <linux/sed-opal.h> |
b9e03857 | 15 | #include <linux/fault-inject.h> |
978628ec | 16 | #include <linux/rcupdate.h> |
c1ac9a4b | 17 | #include <linux/wait.h> |
4d2ce688 | 18 | #include <linux/t10-pi.h> |
a1a825ab | 19 | #include <linux/ratelimit_types.h> |
f11bb3e2 | 20 | |
35fe0d12 HR |
21 | #include <trace/events/block.h> |
22 | ||
b668f2f5 MC |
23 | extern const struct pr_ops nvme_pr_ops; |
24 | ||
8ae4e447 | 25 | extern unsigned int nvme_io_timeout; |
f11bb3e2 CH |
26 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) |
27 | ||
8ae4e447 | 28 | extern unsigned int admin_timeout; |
dc96f938 | 29 | #define NVME_ADMIN_TIMEOUT (admin_timeout * HZ) |
21d34711 | 30 | |
038bd4cb | 31 | #define NVME_DEFAULT_KATO 5 |
038bd4cb | 32 | |
38e18002 IR |
33 | #ifdef CONFIG_ARCH_NO_SG_CHAIN |
34 | #define NVME_INLINE_SG_CNT 0 | |
ba7ca2ae | 35 | #define NVME_INLINE_METADATA_SG_CNT 0 |
38e18002 IR |
36 | #else |
37 | #define NVME_INLINE_SG_CNT 2 | |
ba7ca2ae | 38 | #define NVME_INLINE_METADATA_SG_CNT 1 |
38e18002 IR |
39 | #endif |
40 | ||
6c3c05b0 CK |
41 | /* |
42 | * Default to a 4K page size, with the intention to update this | |
43 | * path in the future to accommodate architectures with differing | |
44 | * kernel and IO page sizes. | |
45 | */ | |
46 | #define NVME_CTRL_PAGE_SHIFT 12 | |
47 | #define NVME_CTRL_PAGE_SIZE (1 << NVME_CTRL_PAGE_SHIFT) | |
48 | ||
9a6327d2 | 49 | extern struct workqueue_struct *nvme_wq; |
b227c59b RS |
50 | extern struct workqueue_struct *nvme_reset_wq; |
51 | extern struct workqueue_struct *nvme_delete_wq; | |
9a6327d2 | 52 | |
f11bb3e2 | 53 | /* |
106198ed CH |
54 | * List of workarounds for devices that required behavior not specified in |
55 | * the standard. | |
f11bb3e2 | 56 | */ |
106198ed CH |
57 | enum nvme_quirks { |
58 | /* | |
59 | * Prefers I/O aligned to a stripe size specified in a vendor | |
60 | * specific Identify field. | |
61 | */ | |
62 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), | |
540c801c KB |
63 | |
64 | /* | |
65 | * The controller doesn't handle Identify value others than 0 or 1 | |
66 | * correctly. | |
67 | */ | |
68 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), | |
08095e70 KB |
69 | |
70 | /* | |
e850fd16 CH |
71 | * The controller deterministically returns O's on reads to |
72 | * logical blocks that deallocate was called on. | |
08095e70 | 73 | */ |
e850fd16 | 74 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
54adc010 GP |
75 | |
76 | /* | |
77 | * The controller needs a delay before starts checking the device | |
78 | * readiness, which is done by reading the NVME_CSTS_RDY bit. | |
79 | */ | |
80 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), | |
c5552fde AL |
81 | |
82 | /* | |
83 | * APST should not be used. | |
84 | */ | |
85 | NVME_QUIRK_NO_APST = (1 << 4), | |
ff5350a8 AL |
86 | |
87 | /* | |
88 | * The deepest sleep state should not be used. | |
89 | */ | |
90 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), | |
608cc4b1 | 91 | |
9abd68ef JA |
92 | /* |
93 | * Set MEDIUM priority on SQ creation | |
94 | */ | |
95 | NVME_QUIRK_MEDIUM_PRIO_SQ = (1 << 7), | |
6299358d JD |
96 | |
97 | /* | |
98 | * Ignore device provided subnqn. | |
99 | */ | |
100 | NVME_QUIRK_IGNORE_DEV_SUBNQN = (1 << 8), | |
7b210e4e CH |
101 | |
102 | /* | |
103 | * Broken Write Zeroes. | |
104 | */ | |
105 | NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9), | |
cb32de1b ML |
106 | |
107 | /* | |
108 | * Force simple suspend/resume path. | |
109 | */ | |
110 | NVME_QUIRK_SIMPLE_SUSPEND = (1 << 10), | |
7ad67ca5 | 111 | |
66341331 BH |
112 | /* |
113 | * Use only one interrupt vector for all queues | |
114 | */ | |
7ad67ca5 | 115 | NVME_QUIRK_SINGLE_VECTOR = (1 << 11), |
66341331 BH |
116 | |
117 | /* | |
118 | * Use non-standard 128 bytes SQEs. | |
119 | */ | |
7ad67ca5 | 120 | NVME_QUIRK_128_BYTES_SQES = (1 << 12), |
d38e9f04 BH |
121 | |
122 | /* | |
123 | * Prevent tag overlap between queues | |
124 | */ | |
7ad67ca5 | 125 | NVME_QUIRK_SHARED_TAGS = (1 << 13), |
6c6aa2f2 AM |
126 | |
127 | /* | |
128 | * Don't change the value of the temperature threshold feature | |
129 | */ | |
130 | NVME_QUIRK_NO_TEMP_THRESH_CHANGE = (1 << 14), | |
5bedd3af CH |
131 | |
132 | /* | |
133 | * The controller doesn't handle the Identify Namespace | |
134 | * Identification Descriptor list subcommand despite claiming | |
135 | * NVMe 1.3 compliance. | |
136 | */ | |
137 | NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15), | |
4bdf2603 FS |
138 | |
139 | /* | |
140 | * The controller does not properly handle DMA addresses over | |
141 | * 48 bits. | |
142 | */ | |
143 | NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16), | |
a2941f6a KB |
144 | |
145 | /* | |
b7df575f | 146 | * The controller requires the command_id value be limited, so skip |
a2941f6a KB |
147 | * encoding the generation sequence number. |
148 | */ | |
149 | NVME_QUIRK_SKIP_CID_GEN = (1 << 17), | |
00ff400e CH |
150 | |
151 | /* | |
152 | * Reports garbage in the namespace identifiers (eui64, nguid, uuid). | |
153 | */ | |
154 | NVME_QUIRK_BOGUS_NID = (1 << 18), | |
bd375fee HV |
155 | |
156 | /* | |
157 | * No temperature thresholds for channels other than 0 (Composite). | |
158 | */ | |
159 | NVME_QUIRK_NO_SECONDARY_TEMP_THRESH = (1 << 19), | |
107b4e06 GG |
160 | |
161 | /* | |
162 | * Disables simple suspend/resume path. | |
163 | */ | |
164 | NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND = (1 << 20), | |
106198ed CH |
165 | }; |
166 | ||
d49187e9 CH |
167 | /* |
168 | * Common request structure for NVMe passthrough. All drivers must have | |
169 | * this structure as the first member of their request-private data. | |
170 | */ | |
171 | struct nvme_request { | |
172 | struct nvme_command *cmd; | |
173 | union nvme_result result; | |
e7006de6 | 174 | u8 genctr; |
44e44b29 | 175 | u8 retries; |
27fa9bc5 CH |
176 | u8 flags; |
177 | u16 status; | |
d4d957b5 SG |
178 | #ifdef CONFIG_NVME_MULTIPATH |
179 | unsigned long start_time; | |
180 | #endif | |
59e29ce6 | 181 | struct nvme_ctrl *ctrl; |
27fa9bc5 CH |
182 | }; |
183 | ||
32acab31 CH |
184 | /* |
185 | * Mark a bio as coming in through the mpath node. | |
186 | */ | |
187 | #define REQ_NVME_MPATH REQ_DRV | |
188 | ||
27fa9bc5 CH |
189 | enum { |
190 | NVME_REQ_CANCELLED = (1 << 0), | |
bb06ec31 | 191 | NVME_REQ_USERCMD = (1 << 1), |
d4d957b5 | 192 | NVME_MPATH_IO_STATS = (1 << 2), |
d49187e9 CH |
193 | }; |
194 | ||
195 | static inline struct nvme_request *nvme_req(struct request *req) | |
196 | { | |
197 | return blk_mq_rq_to_pdu(req); | |
198 | } | |
199 | ||
5d87eb94 KB |
200 | static inline u16 nvme_req_qid(struct request *req) |
201 | { | |
643c476d | 202 | if (!req->q->queuedata) |
5d87eb94 | 203 | return 0; |
84115d6d BW |
204 | |
205 | return req->mq_hctx->queue_num + 1; | |
5d87eb94 KB |
206 | } |
207 | ||
54adc010 GP |
208 | /* The below value is the specific amount of delay needed before checking |
209 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the | |
210 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was | |
211 | * found empirically. | |
212 | */ | |
8c97eecc | 213 | #define NVME_QUIRK_DELAY_AMOUNT 2300 |
54adc010 | 214 | |
4212f4e9 SG |
215 | /* |
216 | * enum nvme_ctrl_state: Controller state | |
217 | * | |
218 | * @NVME_CTRL_NEW: New controller just allocated, initial state | |
219 | * @NVME_CTRL_LIVE: Controller is connected and I/O capable | |
220 | * @NVME_CTRL_RESETTING: Controller is resetting (or scheduled reset) | |
221 | * @NVME_CTRL_CONNECTING: Controller is disconnected, now connecting the | |
222 | * transport | |
223 | * @NVME_CTRL_DELETING: Controller is deleting (or scheduled deletion) | |
ecca390e SG |
224 | * @NVME_CTRL_DELETING_NOIO: Controller is deleting and I/O is not |
225 | * disabled/failed immediately. This state comes | |
226 | * after all async event processing took place and | |
227 | * before ns removal and the controller deletion | |
228 | * progress | |
4212f4e9 SG |
229 | * @NVME_CTRL_DEAD: Controller is non-present/unresponsive during |
230 | * shutdown or removal. In this case we forcibly | |
231 | * kill all inflight I/O as they have no chance to | |
232 | * complete | |
233 | */ | |
bb8d261e CH |
234 | enum nvme_ctrl_state { |
235 | NVME_CTRL_NEW, | |
236 | NVME_CTRL_LIVE, | |
237 | NVME_CTRL_RESETTING, | |
ad6a0a52 | 238 | NVME_CTRL_CONNECTING, |
bb8d261e | 239 | NVME_CTRL_DELETING, |
ecca390e | 240 | NVME_CTRL_DELETING_NOIO, |
0ff9d4e1 | 241 | NVME_CTRL_DEAD, |
bb8d261e CH |
242 | }; |
243 | ||
a3646451 AM |
244 | struct nvme_fault_inject { |
245 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS | |
246 | struct fault_attr attr; | |
247 | struct dentry *parent; | |
248 | bool dont_retry; /* DNR, do not retry */ | |
249 | u16 status; /* status code */ | |
250 | #endif | |
251 | }; | |
252 | ||
bf093d97 SG |
253 | enum nvme_ctrl_flags { |
254 | NVME_CTRL_FAILFAST_EXPIRED = 0, | |
255 | NVME_CTRL_ADMIN_Q_STOPPED = 1, | |
f46ef9e8 | 256 | NVME_CTRL_STARTED_ONCE = 2, |
98d81f0d | 257 | NVME_CTRL_STOPPED = 3, |
c917dd96 | 258 | NVME_CTRL_SKIP_ID_CNS_CS = 4, |
d0dd594b | 259 | NVME_CTRL_DIRTY_CAPABILITY = 5, |
839a40d1 | 260 | NVME_CTRL_FROZEN = 6, |
bf093d97 SG |
261 | }; |
262 | ||
1c63dc66 | 263 | struct nvme_ctrl { |
6e3ca03e | 264 | bool comp_seen; |
bd4da3ab | 265 | bool identified; |
9f079dda | 266 | bool passthru_err_log_enabled; |
9d217fb0 | 267 | enum nvme_ctrl_state state; |
bb8d261e | 268 | spinlock_t lock; |
e7ad43c3 | 269 | struct mutex scan_lock; |
1c63dc66 | 270 | const struct nvme_ctrl_ops *ops; |
f11bb3e2 | 271 | struct request_queue *admin_q; |
07bfcd09 | 272 | struct request_queue *connect_q; |
e7832cb4 | 273 | struct request_queue *fabrics_q; |
f11bb3e2 | 274 | struct device *dev; |
f11bb3e2 | 275 | int instance; |
103e515e | 276 | int numa_node; |
5bae7f73 | 277 | struct blk_mq_tag_set *tagset; |
34b6c231 | 278 | struct blk_mq_tag_set *admin_tagset; |
f11bb3e2 | 279 | struct list_head namespaces; |
765cc031 | 280 | struct rw_semaphore namespaces_rwsem; |
d22524a4 | 281 | struct device ctrl_device; |
5bae7f73 | 282 | struct device *device; /* char device */ |
ed7770f6 HR |
283 | #ifdef CONFIG_NVME_HWMON |
284 | struct device *hwmon_device; | |
285 | #endif | |
a6a5149b | 286 | struct cdev cdev; |
d86c4d8e | 287 | struct work_struct reset_work; |
c5017e85 | 288 | struct work_struct delete_work; |
c1ac9a4b | 289 | wait_queue_head_t state_wq; |
1c63dc66 | 290 | |
ab9e00cc CH |
291 | struct nvme_subsystem *subsys; |
292 | struct list_head subsys_entry; | |
293 | ||
4f1244c8 | 294 | struct opal_dev *opal_dev; |
a98e58e5 | 295 | |
f11bb3e2 | 296 | char name[12]; |
76e3914a | 297 | u16 cntlid; |
5fd4ce1b | 298 | |
b6dccf7f | 299 | u16 mtfa; |
9d217fb0 | 300 | u32 ctrl_config; |
d858e5f0 | 301 | u32 queue_count; |
5fd4ce1b | 302 | |
20d0dfe6 | 303 | u64 cap; |
f11bb3e2 | 304 | u32 max_hw_sectors; |
943e942e | 305 | u32 max_segments; |
95093350 | 306 | u32 max_integrity_segments; |
5befc7c2 | 307 | u32 max_zeroes_sectors; |
240e6ee2 KB |
308 | #ifdef CONFIG_BLK_DEV_ZONED |
309 | u32 max_zone_append; | |
310 | #endif | |
49cd84b6 | 311 | u16 crdt[3]; |
f11bb3e2 | 312 | u16 oncs; |
3b946fe1 | 313 | u8 dmrl; |
1a86924e | 314 | u32 dmrsl; |
8a9ae523 | 315 | u16 oacs; |
f968688f | 316 | u16 sqsize; |
0d0b660f | 317 | u32 max_namespaces; |
6bf25d16 | 318 | atomic_t abort_limit; |
f11bb3e2 | 319 | u8 vwc; |
f3ca80fc | 320 | u32 vs; |
07bfcd09 | 321 | u32 sgls; |
038bd4cb | 322 | u16 kas; |
c5552fde AL |
323 | u8 npss; |
324 | u8 apsta; | |
400b6a7b GR |
325 | u16 wctemp; |
326 | u16 cctemp; | |
c0561f82 | 327 | u32 oaes; |
e3d7874d | 328 | u32 aen_result; |
3e53ba38 | 329 | u32 ctratt; |
07fbd32a | 330 | unsigned int shutdown_timeout; |
038bd4cb | 331 | unsigned int kato; |
f3ca80fc | 332 | bool subsystem; |
106198ed | 333 | unsigned long quirks; |
c5552fde | 334 | struct nvme_id_power_state psd[32]; |
84fef62d | 335 | struct nvme_effects_log *effects; |
1cf7a12e | 336 | struct xarray cels; |
5955be21 | 337 | struct work_struct scan_work; |
f866fc42 | 338 | struct work_struct async_event_work; |
038bd4cb | 339 | struct delayed_work ka_work; |
8c4dfea9 | 340 | struct delayed_work failfast_work; |
0a34e466 | 341 | struct nvme_command ka_cmd; |
774a9636 | 342 | unsigned long ka_last_check_time; |
b6dccf7f | 343 | struct work_struct fw_act_work; |
30d90964 | 344 | unsigned long events; |
07bfcd09 | 345 | |
0d0b660f CH |
346 | #ifdef CONFIG_NVME_MULTIPATH |
347 | /* asymmetric namespace access: */ | |
348 | u8 anacap; | |
349 | u8 anatt; | |
350 | u32 anagrpmax; | |
351 | u32 nanagrpid; | |
352 | struct mutex ana_lock; | |
353 | struct nvme_ana_rsp_hdr *ana_log_buf; | |
354 | size_t ana_log_size; | |
355 | struct timer_list anatt_timer; | |
356 | struct work_struct ana_work; | |
357 | #endif | |
358 | ||
d6800634 | 359 | #ifdef CONFIG_NVME_HOST_AUTH |
f50fff73 | 360 | struct work_struct dhchap_auth_work; |
f50fff73 | 361 | struct mutex dhchap_auth_mutex; |
aa36d711 | 362 | struct nvme_dhchap_queue_context *dhchap_ctxs; |
f50fff73 HR |
363 | struct nvme_dhchap_key *host_key; |
364 | struct nvme_dhchap_key *ctrl_key; | |
365 | u16 transaction; | |
366 | #endif | |
be8e82ca | 367 | struct key *tls_key; |
f50fff73 | 368 | |
c5552fde AL |
369 | /* Power saving configuration */ |
370 | u64 ps_max_latency_us; | |
76a5af84 | 371 | bool apst_enabled; |
c5552fde | 372 | |
044a9df1 | 373 | /* PCIe only: */ |
9d217fb0 | 374 | u16 hmmaxd; |
fe6d53c9 CH |
375 | u32 hmpre; |
376 | u32 hmmin; | |
044a9df1 | 377 | u32 hmminds; |
fe6d53c9 | 378 | |
07bfcd09 | 379 | /* Fabrics only */ |
07bfcd09 CH |
380 | u32 ioccsz; |
381 | u32 iorcsz; | |
382 | u16 icdoff; | |
383 | u16 maxcmd; | |
fdf9dfa8 | 384 | int nr_reconnects; |
8c4dfea9 | 385 | unsigned long flags; |
07bfcd09 | 386 | struct nvmf_ctrl_options *opts; |
cb5b7262 JA |
387 | |
388 | struct page *discard_page; | |
389 | unsigned long discard_page_busy; | |
f79d5fda AM |
390 | |
391 | struct nvme_fault_inject fault_inject; | |
86c2457a MB |
392 | |
393 | enum nvme_ctrl_type cntrltype; | |
394 | enum nvme_dctype dctype; | |
f11bb3e2 CH |
395 | }; |
396 | ||
5c687c28 KB |
397 | static inline enum nvme_ctrl_state nvme_ctrl_state(struct nvme_ctrl *ctrl) |
398 | { | |
399 | return READ_ONCE(ctrl->state); | |
400 | } | |
401 | ||
75c10e73 HR |
402 | enum nvme_iopolicy { |
403 | NVME_IOPOLICY_NUMA, | |
404 | NVME_IOPOLICY_RR, | |
405 | }; | |
406 | ||
ab9e00cc CH |
407 | struct nvme_subsystem { |
408 | int instance; | |
409 | struct device dev; | |
410 | /* | |
411 | * Because we unregister the device on the last put we need | |
412 | * a separate refcount. | |
413 | */ | |
414 | struct kref ref; | |
415 | struct list_head entry; | |
416 | struct mutex lock; | |
417 | struct list_head ctrls; | |
ed754e5d | 418 | struct list_head nsheads; |
ab9e00cc CH |
419 | char subnqn[NVMF_NQN_SIZE]; |
420 | char serial[20]; | |
421 | char model[40]; | |
422 | char firmware_rev[8]; | |
423 | u8 cmic; | |
954ae166 | 424 | enum nvme_subsys_type subtype; |
ab9e00cc | 425 | u16 vendor_id; |
81adb863 | 426 | u16 awupf; /* 0's based awupf value. */ |
ed754e5d | 427 | struct ida ns_ida; |
75c10e73 HR |
428 | #ifdef CONFIG_NVME_MULTIPATH |
429 | enum nvme_iopolicy iopolicy; | |
430 | #endif | |
ab9e00cc CH |
431 | }; |
432 | ||
002fab04 CH |
433 | /* |
434 | * Container structure for uniqueue namespace identifiers. | |
435 | */ | |
436 | struct nvme_ns_ids { | |
437 | u8 eui64[8]; | |
438 | u8 nguid[16]; | |
439 | uuid_t uuid; | |
71010c30 | 440 | u8 csi; |
002fab04 CH |
441 | }; |
442 | ||
ed754e5d CH |
443 | /* |
444 | * Anchor structure for namespaces. There is one for each namespace in a | |
445 | * NVMe subsystem that any of our controllers can see, and the namespace | |
446 | * structure for each controller is chained of it. For private namespaces | |
447 | * there is a 1:1 relation to our namespace structures, that is ->list | |
448 | * only ever has a single entry for private namespaces. | |
449 | */ | |
450 | struct nvme_ns_head { | |
451 | struct list_head list; | |
452 | struct srcu_struct srcu; | |
453 | struct nvme_subsystem *subsys; | |
ed754e5d CH |
454 | struct nvme_ns_ids ids; |
455 | struct list_head entry; | |
456 | struct kref ref; | |
0c284db7 | 457 | bool shared; |
1f4137e8 | 458 | bool passthru_err_log_enabled; |
ed754e5d | 459 | int instance; |
be93e87e | 460 | struct nvme_effects_log *effects; |
96392961 DW |
461 | u64 nuse; |
462 | unsigned ns_id; | |
9419e71b DW |
463 | int lba_shift; |
464 | u16 ms; | |
465 | u16 pi_size; | |
9419e71b | 466 | u8 pi_type; |
921e81db | 467 | u8 pi_offset; |
9419e71b | 468 | u8 guard_type; |
96392961 DW |
469 | u16 sgs; |
470 | u32 sws; | |
9419e71b DW |
471 | #ifdef CONFIG_BLK_DEV_ZONED |
472 | u64 zsze; | |
473 | #endif | |
474 | unsigned long features; | |
2637baed | 475 | |
a1a825ab | 476 | struct ratelimit_state rs_nuse; |
2637baed MI |
477 | |
478 | struct cdev cdev; | |
479 | struct device cdev_device; | |
480 | ||
f3334447 | 481 | struct gendisk *disk; |
30897388 | 482 | #ifdef CONFIG_NVME_MULTIPATH |
f3334447 CH |
483 | struct bio_list requeue_list; |
484 | spinlock_t requeue_lock; | |
485 | struct work_struct requeue_work; | |
486 | struct mutex lock; | |
d8a22f85 AE |
487 | unsigned long flags; |
488 | #define NVME_NSHEAD_DISK_LIVE 0 | |
f3334447 CH |
489 | struct nvme_ns __rcu *current_path[]; |
490 | #endif | |
ed754e5d CH |
491 | }; |
492 | ||
30897388 MI |
493 | static inline bool nvme_ns_head_multipath(struct nvme_ns_head *head) |
494 | { | |
495 | return IS_ENABLED(CONFIG_NVME_MULTIPATH) && head->disk; | |
496 | } | |
497 | ||
ffc89b1d MG |
498 | enum nvme_ns_features { |
499 | NVME_NS_EXT_LBAS = 1 << 0, /* support extended LBA format */ | |
b29f8485 | 500 | NVME_NS_METADATA_SUPPORTED = 1 << 1, /* support getting generated md */ |
1b96f862 | 501 | NVME_NS_DEAC, /* DEAC bit in Write Zeores supported */ |
ffc89b1d MG |
502 | }; |
503 | ||
f11bb3e2 CH |
504 | struct nvme_ns { |
505 | struct list_head list; | |
506 | ||
1c63dc66 | 507 | struct nvme_ctrl *ctrl; |
f11bb3e2 CH |
508 | struct request_queue *queue; |
509 | struct gendisk *disk; | |
0d0b660f CH |
510 | #ifdef CONFIG_NVME_MULTIPATH |
511 | enum nvme_ana_state ana_state; | |
512 | u32 ana_grpid; | |
513 | #endif | |
ed754e5d | 514 | struct list_head siblings; |
f11bb3e2 | 515 | struct kref kref; |
ed754e5d | 516 | struct nvme_ns_head *head; |
f11bb3e2 | 517 | |
646017a6 | 518 | unsigned long flags; |
0d0b660f | 519 | #define NVME_NS_REMOVING 0 |
0d0b660f | 520 | #define NVME_NS_ANA_PENDING 2 |
2f4c9ba2 | 521 | #define NVME_NS_FORCE_RO 3 |
e7d65803 | 522 | #define NVME_NS_READY 4 |
b9e03857 | 523 | |
2637baed MI |
524 | struct cdev cdev; |
525 | struct device cdev_device; | |
526 | ||
b9e03857 | 527 | struct nvme_fault_inject fault_inject; |
f11bb3e2 CH |
528 | }; |
529 | ||
4d2ce688 | 530 | /* NVMe ns supports metadata actions by the controller (generate/strip) */ |
0372dd4e | 531 | static inline bool nvme_ns_has_pi(struct nvme_ns_head *head) |
4d2ce688 | 532 | { |
0372dd4e | 533 | return head->pi_type && head->ms == head->pi_size; |
4d2ce688 JS |
534 | } |
535 | ||
1c63dc66 | 536 | struct nvme_ctrl_ops { |
1a353d85 | 537 | const char *name; |
e439bb12 | 538 | struct module *module; |
d3d5b87d CH |
539 | unsigned int flags; |
540 | #define NVME_F_FABRICS (1 << 0) | |
c81bfba9 | 541 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
db45e1a5 CH |
542 | #define NVME_F_BLOCKING (1 << 2) |
543 | ||
86adbf0c | 544 | const struct attribute_group **dev_attr_groups; |
1c63dc66 | 545 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
5fd4ce1b | 546 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
7fd8930f | 547 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
1673f1f0 | 548 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
ad22c355 | 549 | void (*submit_async_event)(struct nvme_ctrl *ctrl); |
c5017e85 | 550 | void (*delete_ctrl)(struct nvme_ctrl *ctrl); |
f7f70f4a | 551 | void (*stop_ctrl)(struct nvme_ctrl *ctrl); |
1a353d85 | 552 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
2f0dad17 | 553 | void (*print_device_info)(struct nvme_ctrl *ctrl); |
2f859441 | 554 | bool (*supports_pci_p2pdma)(struct nvme_ctrl *ctrl); |
f11bb3e2 CH |
555 | }; |
556 | ||
e7006de6 SG |
557 | /* |
558 | * nvme command_id is constructed as such: | |
559 | * | xxxx | xxxxxxxxxxxx | | |
560 | * gen request tag | |
561 | */ | |
562 | #define nvme_genctr_mask(gen) (gen & 0xf) | |
563 | #define nvme_cid_install_genctr(gen) (nvme_genctr_mask(gen) << 12) | |
564 | #define nvme_genctr_from_cid(cid) ((cid & 0xf000) >> 12) | |
565 | #define nvme_tag_from_cid(cid) (cid & 0xfff) | |
566 | ||
567 | static inline u16 nvme_cid(struct request *rq) | |
568 | { | |
569 | return nvme_cid_install_genctr(nvme_req(rq)->genctr) | rq->tag; | |
570 | } | |
571 | ||
572 | static inline struct request *nvme_find_rq(struct blk_mq_tags *tags, | |
573 | u16 command_id) | |
574 | { | |
575 | u8 genctr = nvme_genctr_from_cid(command_id); | |
576 | u16 tag = nvme_tag_from_cid(command_id); | |
577 | struct request *rq; | |
578 | ||
579 | rq = blk_mq_tag_to_rq(tags, tag); | |
580 | if (unlikely(!rq)) { | |
581 | pr_err("could not locate request for tag %#x\n", | |
582 | tag); | |
583 | return NULL; | |
584 | } | |
585 | if (unlikely(nvme_genctr_mask(nvme_req(rq)->genctr) != genctr)) { | |
586 | dev_err(nvme_req(rq)->ctrl->device, | |
587 | "request %#x genctr mismatch (got %#x expected %#x)\n", | |
588 | tag, genctr, nvme_genctr_mask(nvme_req(rq)->genctr)); | |
589 | return NULL; | |
590 | } | |
591 | return rq; | |
592 | } | |
593 | ||
594 | static inline struct request *nvme_cid_to_rq(struct blk_mq_tags *tags, | |
595 | u16 command_id) | |
596 | { | |
597 | return blk_mq_tag_to_rq(tags, nvme_tag_from_cid(command_id)); | |
598 | } | |
599 | ||
2f0dad17 KB |
600 | /* |
601 | * Return the length of the string without the space padding | |
602 | */ | |
603 | static inline int nvme_strlen(char *s, int len) | |
604 | { | |
605 | while (s[len - 1] == ' ') | |
606 | len--; | |
607 | return len; | |
608 | } | |
609 | ||
610 | static inline void nvme_print_device_info(struct nvme_ctrl *ctrl) | |
611 | { | |
612 | struct nvme_subsystem *subsys = ctrl->subsys; | |
613 | ||
614 | if (ctrl->ops->print_device_info) { | |
615 | ctrl->ops->print_device_info(ctrl); | |
616 | return; | |
617 | } | |
618 | ||
619 | dev_err(ctrl->device, | |
620 | "VID:%04x model:%.*s firmware:%.*s\n", subsys->vendor_id, | |
621 | nvme_strlen(subsys->model, sizeof(subsys->model)), | |
622 | subsys->model, nvme_strlen(subsys->firmware_rev, | |
623 | sizeof(subsys->firmware_rev)), | |
624 | subsys->firmware_rev); | |
625 | } | |
626 | ||
b9e03857 | 627 | #ifdef CONFIG_FAULT_INJECTION_DEBUG_FS |
a3646451 AM |
628 | void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, |
629 | const char *dev_name); | |
630 | void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inject); | |
b9e03857 TT |
631 | void nvme_should_fail(struct request *req); |
632 | #else | |
a3646451 AM |
633 | static inline void nvme_fault_inject_init(struct nvme_fault_inject *fault_inj, |
634 | const char *dev_name) | |
635 | { | |
636 | } | |
637 | static inline void nvme_fault_inject_fini(struct nvme_fault_inject *fault_inj) | |
638 | { | |
639 | } | |
b9e03857 TT |
640 | static inline void nvme_should_fail(struct request *req) {} |
641 | #endif | |
642 | ||
1e866afd KB |
643 | bool nvme_wait_reset(struct nvme_ctrl *ctrl); |
644 | int nvme_try_sched_reset(struct nvme_ctrl *ctrl); | |
645 | ||
f3ca80fc CH |
646 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
647 | { | |
1e866afd KB |
648 | int ret; |
649 | ||
f3ca80fc CH |
650 | if (!ctrl->subsystem) |
651 | return -ENOTTY; | |
1e866afd KB |
652 | if (!nvme_wait_reset(ctrl)) |
653 | return -EBUSY; | |
654 | ||
655 | ret = ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); | |
656 | if (ret) | |
657 | return ret; | |
658 | ||
659 | return nvme_try_sched_reset(ctrl); | |
f3ca80fc CH |
660 | } |
661 | ||
314d48dd DLM |
662 | /* |
663 | * Convert a 512B sector number to a device logical block number. | |
664 | */ | |
0372dd4e | 665 | static inline u64 nvme_sect_to_lba(struct nvme_ns_head *head, sector_t sector) |
f11bb3e2 | 666 | { |
0372dd4e | 667 | return sector >> (head->lba_shift - SECTOR_SHIFT); |
f11bb3e2 CH |
668 | } |
669 | ||
e08f2ae8 DLM |
670 | /* |
671 | * Convert a device logical block number to a 512B sector number. | |
672 | */ | |
0372dd4e | 673 | static inline sector_t nvme_lba_to_sect(struct nvme_ns_head *head, u64 lba) |
f11bb3e2 | 674 | { |
0372dd4e | 675 | return lba << (head->lba_shift - SECTOR_SHIFT); |
f11bb3e2 CH |
676 | } |
677 | ||
71fb90eb KB |
678 | /* |
679 | * Convert byte length to nvme's 0-based num dwords | |
680 | */ | |
681 | static inline u32 nvme_bytes_to_numd(size_t len) | |
682 | { | |
683 | return (len >> 2) - 1; | |
684 | } | |
685 | ||
5ddaabe8 CH |
686 | static inline bool nvme_is_ana_error(u16 status) |
687 | { | |
688 | switch (status & 0x7ff) { | |
689 | case NVME_SC_ANA_TRANSITION: | |
690 | case NVME_SC_ANA_INACCESSIBLE: | |
691 | case NVME_SC_ANA_PERSISTENT_LOSS: | |
692 | return true; | |
693 | default: | |
694 | return false; | |
695 | } | |
696 | } | |
697 | ||
698 | static inline bool nvme_is_path_error(u16 status) | |
699 | { | |
1e41f3bd CH |
700 | /* check for a status code type of 'path related status' */ |
701 | return (status & 0x700) == 0x300; | |
5ddaabe8 CH |
702 | } |
703 | ||
2eb81a33 CH |
704 | /* |
705 | * Fill in the status and result information from the CQE, and then figure out | |
706 | * if blk-mq will need to use IPI magic to complete the request, and if yes do | |
707 | * so. If not let the caller complete the request without an indirect function | |
708 | * call. | |
709 | */ | |
710 | static inline bool nvme_try_complete_req(struct request *req, __le16 status, | |
27fa9bc5 | 711 | union nvme_result result) |
15a190f7 | 712 | { |
27fa9bc5 | 713 | struct nvme_request *rq = nvme_req(req); |
e4fdb2b1 KB |
714 | struct nvme_ctrl *ctrl = rq->ctrl; |
715 | ||
716 | if (!(ctrl->quirks & NVME_QUIRK_SKIP_CID_GEN)) | |
717 | rq->genctr++; | |
15a190f7 | 718 | |
27fa9bc5 CH |
719 | rq->status = le16_to_cpu(status) >> 1; |
720 | rq->result = result; | |
b9e03857 TT |
721 | /* inject error when permitted by fault injection framework */ |
722 | nvme_should_fail(req); | |
ff029451 CH |
723 | if (unlikely(blk_should_fake_timeout(req->q))) |
724 | return true; | |
725 | return blk_mq_complete_request_remote(req); | |
7688faa6 CH |
726 | } |
727 | ||
d22524a4 CH |
728 | static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) |
729 | { | |
730 | get_device(ctrl->device); | |
731 | } | |
732 | ||
733 | static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) | |
734 | { | |
735 | put_device(ctrl->device); | |
736 | } | |
737 | ||
58a8df67 IR |
738 | static inline bool nvme_is_aen_req(u16 qid, __u16 command_id) |
739 | { | |
e7006de6 SG |
740 | return !qid && |
741 | nvme_tag_from_cid(command_id) >= NVME_AQ_BLK_MQ_DEPTH; | |
58a8df67 IR |
742 | } |
743 | ||
77f02a7a | 744 | void nvme_complete_rq(struct request *req); |
c234a653 JA |
745 | void nvme_complete_batch_req(struct request *req); |
746 | ||
747 | static __always_inline void nvme_complete_batch(struct io_comp_batch *iob, | |
748 | void (*fn)(struct request *rq)) | |
749 | { | |
750 | struct request *req; | |
751 | ||
752 | rq_list_for_each(&iob->req_list, req) { | |
753 | fn(req); | |
754 | nvme_complete_batch_req(req); | |
755 | } | |
756 | blk_mq_end_request_batch(iob); | |
757 | } | |
758 | ||
dda3248e | 759 | blk_status_t nvme_host_path_error(struct request *req); |
2dd6532e | 760 | bool nvme_cancel_request(struct request *req, void *data); |
25479069 CL |
761 | void nvme_cancel_tagset(struct nvme_ctrl *ctrl); |
762 | void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl); | |
bb8d261e CH |
763 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
764 | enum nvme_ctrl_state new_state); | |
285b6e9b | 765 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown); |
c0f2f45b | 766 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl); |
f3ca80fc CH |
767 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
768 | const struct nvme_ctrl_ops *ops, unsigned long quirks); | |
53029b04 | 769 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
d09f2b45 SG |
770 | void nvme_start_ctrl(struct nvme_ctrl *ctrl); |
771 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl); | |
94cc781f | 772 | int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended); |
fe60e8c5 | 773 | int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, |
db45e1a5 | 774 | const struct blk_mq_ops *ops, unsigned int cmd_size); |
fe60e8c5 CH |
775 | void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl); |
776 | int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, | |
db45e1a5 CH |
777 | const struct blk_mq_ops *ops, unsigned int nr_maps, |
778 | unsigned int cmd_size); | |
fe60e8c5 | 779 | void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl); |
5bae7f73 | 780 | |
5bae7f73 | 781 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
1673f1f0 | 782 | |
7bf58533 | 783 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
287a63eb | 784 | volatile union nvme_result *res); |
f866fc42 | 785 | |
9f27bd70 CH |
786 | void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl); |
787 | void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl); | |
788 | void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl); | |
789 | void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl); | |
cd50f9b2 | 790 | void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl); |
d6135c3a | 791 | void nvme_sync_queues(struct nvme_ctrl *ctrl); |
04800fbf | 792 | void nvme_sync_io_queues(struct nvme_ctrl *ctrl); |
302ad8cc KB |
793 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
794 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); | |
7cf0d7c0 | 795 | int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); |
302ad8cc | 796 | void nvme_start_freeze(struct nvme_ctrl *ctrl); |
363c9aac | 797 | |
f9ed86dc | 798 | static inline enum req_op nvme_req_op(struct nvme_command *cmd) |
e559398f CH |
799 | { |
800 | return nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN; | |
801 | } | |
802 | ||
eb71f435 | 803 | #define NVME_QID_ANY -1 |
e559398f | 804 | void nvme_init_request(struct request *req, struct nvme_command *cmd); |
f7f1fc36 | 805 | void nvme_cleanup_cmd(struct request *req); |
f4b9e6c9 | 806 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req); |
a9715744 TC |
807 | blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, |
808 | struct request *req); | |
809 | bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, | |
6d3c7fb1 | 810 | bool queue_live, enum nvme_ctrl_state state); |
a9715744 TC |
811 | |
812 | static inline bool nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, | |
813 | bool queue_live) | |
814 | { | |
6d3c7fb1 KB |
815 | enum nvme_ctrl_state state = nvme_ctrl_state(ctrl); |
816 | ||
817 | if (likely(state == NVME_CTRL_LIVE)) | |
a9715744 | 818 | return true; |
6d3c7fb1 | 819 | if (ctrl->ops->flags & NVME_F_FABRICS && state == NVME_CTRL_DELETING) |
8b77fa6f | 820 | return queue_live; |
6d3c7fb1 | 821 | return __nvme_check_ready(ctrl, rq, queue_live, state); |
a9715744 | 822 | } |
5974ea7c SM |
823 | |
824 | /* | |
825 | * NSID shall be unique for all shared namespaces, or if at least one of the | |
826 | * following conditions is met: | |
827 | * 1. Namespace Management is supported by the controller | |
828 | * 2. ANA is supported by the controller | |
829 | * 3. NVM Set are supported by the controller | |
830 | * | |
831 | * In other case, private namespace are not required to report a unique NSID. | |
832 | */ | |
833 | static inline bool nvme_is_unique_nsid(struct nvme_ctrl *ctrl, | |
834 | struct nvme_ns_head *head) | |
835 | { | |
836 | return head->shared || | |
837 | (ctrl->oacs & NVME_CTRL_OACS_NS_MNGT_SUPP) || | |
838 | (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) || | |
839 | (ctrl->ctratt & NVME_CTRL_CTRATT_NVM_SETS); | |
840 | } | |
841 | ||
bd2687f2 HR |
842 | /* |
843 | * Flags for __nvme_submit_sync_cmd() | |
844 | */ | |
845 | typedef __u32 __bitwise nvme_submit_flags_t; | |
846 | ||
847 | enum { | |
848 | /* Insert request at the head of the queue */ | |
849 | NVME_SUBMIT_AT_HEAD = (__force nvme_submit_flags_t)(1 << 0), | |
850 | /* Set BLK_MQ_REQ_NOWAIT when allocating request */ | |
851 | NVME_SUBMIT_NOWAIT = (__force nvme_submit_flags_t)(1 << 1), | |
852 | /* Set BLK_MQ_REQ_RESERVED when allocating request */ | |
853 | NVME_SUBMIT_RESERVED = (__force nvme_submit_flags_t)(1 << 2), | |
48dae466 HR |
854 | /* Retry command when NVME_SC_DNR is not set in the result */ |
855 | NVME_SUBMIT_RETRY = (__force nvme_submit_flags_t)(1 << 3), | |
bd2687f2 HR |
856 | }; |
857 | ||
f11bb3e2 CH |
858 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
859 | void *buf, unsigned bufflen); | |
860 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 861 | union nvme_result *result, void *buffer, unsigned bufflen, |
bd2687f2 | 862 | int qid, nvme_submit_flags_t flags); |
1a87ee65 KB |
863 | int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, |
864 | unsigned int dword11, void *buffer, size_t buflen, | |
865 | u32 *result); | |
866 | int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, | |
867 | unsigned int dword11, void *buffer, size_t buflen, | |
868 | u32 *result); | |
9a0be7ab | 869 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
038bd4cb | 870 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); |
d86c4d8e | 871 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
2405252a | 872 | int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl); |
c5017e85 | 873 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl); |
2405252a | 874 | void nvme_queue_scan(struct nvme_ctrl *ctrl); |
be93e87e | 875 | int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, |
0e98719b | 876 | void *log, size_t size, u64 offset); |
1496bd49 CH |
877 | bool nvme_tryget_ns_head(struct nvme_ns_head *head); |
878 | void nvme_put_ns_head(struct nvme_ns_head *head); | |
2637baed MI |
879 | int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, |
880 | const struct file_operations *fops, struct module *owner); | |
881 | void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device); | |
05bdb996 | 882 | int nvme_ioctl(struct block_device *bdev, blk_mode_t mode, |
2405252a | 883 | unsigned int cmd, unsigned long arg); |
2637baed | 884 | long nvme_ns_chr_ioctl(struct file *file, unsigned int cmd, unsigned long arg); |
05bdb996 | 885 | int nvme_ns_head_ioctl(struct block_device *bdev, blk_mode_t mode, |
2405252a | 886 | unsigned int cmd, unsigned long arg); |
2637baed MI |
887 | long nvme_ns_head_chr_ioctl(struct file *file, unsigned int cmd, |
888 | unsigned long arg); | |
2405252a CH |
889 | long nvme_dev_ioctl(struct file *file, unsigned int cmd, |
890 | unsigned long arg); | |
de97fcb3 JA |
891 | int nvme_ns_chr_uring_cmd_iopoll(struct io_uring_cmd *ioucmd, |
892 | struct io_comp_batch *iob, unsigned int poll_flags); | |
456cba38 KJ |
893 | int nvme_ns_chr_uring_cmd(struct io_uring_cmd *ioucmd, |
894 | unsigned int issue_flags); | |
895 | int nvme_ns_head_chr_uring_cmd(struct io_uring_cmd *ioucmd, | |
896 | unsigned int issue_flags); | |
a1a825ab DW |
897 | int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid, |
898 | struct nvme_id_ns **id); | |
1496bd49 | 899 | int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo); |
58e5bdeb | 900 | int nvme_dev_uring_cmd(struct io_uring_cmd *ioucmd, unsigned int issue_flags); |
d558fb51 | 901 | |
83ac678e | 902 | extern const struct attribute_group *nvme_ns_attr_groups[]; |
1496bd49 | 903 | extern const struct pr_ops nvme_pr_ops; |
32acab31 | 904 | extern const struct block_device_operations nvme_ns_head_ops; |
86adbf0c | 905 | extern const struct attribute_group nvme_dev_attrs_group; |
942e21c0 MG |
906 | extern const struct attribute_group *nvme_subsys_attrs_groups[]; |
907 | extern const struct attribute_group *nvme_dev_attr_groups[]; | |
908 | extern const struct block_device_operations nvme_bdev_ops; | |
32acab31 | 909 | |
942e21c0 | 910 | void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); |
f1cf35e1 | 911 | struct nvme_ns *nvme_find_path(struct nvme_ns_head *head); |
32acab31 | 912 | #ifdef CONFIG_NVME_MULTIPATH |
66b20ac0 MR |
913 | static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) |
914 | { | |
915 | return ctrl->ana_log_buf != NULL; | |
916 | } | |
917 | ||
b9156dae SG |
918 | void nvme_mpath_unfreeze(struct nvme_subsystem *subsys); |
919 | void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys); | |
920 | void nvme_mpath_start_freeze(struct nvme_subsystem *subsys); | |
e3d34794 | 921 | void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys); |
5ddaabe8 | 922 | void nvme_failover_req(struct request *req); |
32acab31 CH |
923 | void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl); |
924 | int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl,struct nvme_ns_head *head); | |
c13cf14f | 925 | void nvme_mpath_add_disk(struct nvme_ns *ns, __le32 anagrpid); |
32acab31 | 926 | void nvme_mpath_remove_disk(struct nvme_ns_head *head); |
5e1f6899 CH |
927 | int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id); |
928 | void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl); | |
a4a6f3c8 | 929 | void nvme_mpath_update(struct nvme_ctrl *ctrl); |
0d0b660f CH |
930 | void nvme_mpath_uninit(struct nvme_ctrl *ctrl); |
931 | void nvme_mpath_stop(struct nvme_ctrl *ctrl); | |
0157ec8d | 932 | bool nvme_mpath_clear_current_path(struct nvme_ns *ns); |
e7d65803 | 933 | void nvme_mpath_revalidate_paths(struct nvme_ns *ns); |
0157ec8d | 934 | void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl); |
5396fdac | 935 | void nvme_mpath_shutdown_disk(struct nvme_ns_head *head); |
d4d957b5 SG |
936 | void nvme_mpath_start_request(struct request *rq); |
937 | void nvme_mpath_end_request(struct request *rq); | |
479a322f | 938 | |
2b59787a | 939 | static inline void nvme_trace_bio_complete(struct request *req) |
35fe0d12 HR |
940 | { |
941 | struct nvme_ns *ns = req->q->queuedata; | |
942 | ||
3659fb5a | 943 | if ((req->cmd_flags & REQ_NVME_MPATH) && req->bio) |
d24de76a | 944 | trace_block_bio_complete(ns->head->disk->queue, req->bio); |
35fe0d12 HR |
945 | } |
946 | ||
b739e137 | 947 | extern bool multipath; |
0d0b660f CH |
948 | extern struct device_attribute dev_attr_ana_grpid; |
949 | extern struct device_attribute dev_attr_ana_state; | |
75c10e73 | 950 | extern struct device_attribute subsys_attr_iopolicy; |
0d0b660f | 951 | |
bafd5909 GL |
952 | static inline bool nvme_disk_is_ns_head(struct gendisk *disk) |
953 | { | |
954 | return disk->fops == &nvme_ns_head_ops; | |
955 | } | |
32acab31 | 956 | #else |
b739e137 | 957 | #define multipath false |
0d0b660f CH |
958 | static inline bool nvme_ctrl_use_ana(struct nvme_ctrl *ctrl) |
959 | { | |
960 | return false; | |
961 | } | |
5ddaabe8 | 962 | static inline void nvme_failover_req(struct request *req) |
32acab31 CH |
963 | { |
964 | } | |
32acab31 CH |
965 | static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl) |
966 | { | |
967 | } | |
968 | static inline int nvme_mpath_alloc_disk(struct nvme_ctrl *ctrl, | |
969 | struct nvme_ns_head *head) | |
970 | { | |
971 | return 0; | |
972 | } | |
c13cf14f | 973 | static inline void nvme_mpath_add_disk(struct nvme_ns *ns, __le32 anagrpid) |
32acab31 CH |
974 | { |
975 | } | |
976 | static inline void nvme_mpath_remove_disk(struct nvme_ns_head *head) | |
977 | { | |
978 | } | |
0157ec8d SG |
979 | static inline bool nvme_mpath_clear_current_path(struct nvme_ns *ns) |
980 | { | |
981 | return false; | |
982 | } | |
e7d65803 HR |
983 | static inline void nvme_mpath_revalidate_paths(struct nvme_ns *ns) |
984 | { | |
985 | } | |
0157ec8d | 986 | static inline void nvme_mpath_clear_ctrl_paths(struct nvme_ctrl *ctrl) |
479a322f SG |
987 | { |
988 | } | |
5396fdac | 989 | static inline void nvme_mpath_shutdown_disk(struct nvme_ns_head *head) |
32acab31 CH |
990 | { |
991 | } | |
2b59787a | 992 | static inline void nvme_trace_bio_complete(struct request *req) |
35fe0d12 HR |
993 | { |
994 | } | |
5e1f6899 CH |
995 | static inline void nvme_mpath_init_ctrl(struct nvme_ctrl *ctrl) |
996 | { | |
997 | } | |
998 | static inline int nvme_mpath_init_identify(struct nvme_ctrl *ctrl, | |
0d0b660f CH |
999 | struct nvme_id_ctrl *id) |
1000 | { | |
2bd64307 | 1001 | if (ctrl->subsys->cmic & NVME_CTRL_CMIC_ANA) |
14a1336e CH |
1002 | dev_warn(ctrl->device, |
1003 | "Please enable CONFIG_NVME_MULTIPATH for full support of multi-port devices.\n"); | |
0d0b660f CH |
1004 | return 0; |
1005 | } | |
a4a6f3c8 AE |
1006 | static inline void nvme_mpath_update(struct nvme_ctrl *ctrl) |
1007 | { | |
1008 | } | |
0d0b660f CH |
1009 | static inline void nvme_mpath_uninit(struct nvme_ctrl *ctrl) |
1010 | { | |
1011 | } | |
1012 | static inline void nvme_mpath_stop(struct nvme_ctrl *ctrl) | |
1013 | { | |
1014 | } | |
b9156dae SG |
1015 | static inline void nvme_mpath_unfreeze(struct nvme_subsystem *subsys) |
1016 | { | |
1017 | } | |
1018 | static inline void nvme_mpath_wait_freeze(struct nvme_subsystem *subsys) | |
1019 | { | |
1020 | } | |
1021 | static inline void nvme_mpath_start_freeze(struct nvme_subsystem *subsys) | |
1022 | { | |
1023 | } | |
e3d34794 HR |
1024 | static inline void nvme_mpath_default_iopolicy(struct nvme_subsystem *subsys) |
1025 | { | |
1026 | } | |
d4d957b5 SG |
1027 | static inline void nvme_mpath_start_request(struct request *rq) |
1028 | { | |
1029 | } | |
1030 | static inline void nvme_mpath_end_request(struct request *rq) | |
1031 | { | |
1032 | } | |
bafd5909 GL |
1033 | static inline bool nvme_disk_is_ns_head(struct gendisk *disk) |
1034 | { | |
1035 | return false; | |
1036 | } | |
32acab31 CH |
1037 | #endif /* CONFIG_NVME_MULTIPATH */ |
1038 | ||
8b4fb0f9 CH |
1039 | int nvme_ns_report_zones(struct nvme_ns *ns, sector_t sector, |
1040 | unsigned int nr_zones, report_zones_cb cb, void *data); | |
e6c9b130 CH |
1041 | int nvme_update_zone_info(struct nvme_ns *ns, unsigned lbaf, |
1042 | struct queue_limits *lim); | |
240e6ee2 | 1043 | #ifdef CONFIG_BLK_DEV_ZONED |
240e6ee2 KB |
1044 | blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, struct request *req, |
1045 | struct nvme_command *cmnd, | |
1046 | enum nvme_zone_mgmt_action action); | |
1047 | #else | |
240e6ee2 KB |
1048 | static inline blk_status_t nvme_setup_zone_mgmt_send(struct nvme_ns *ns, |
1049 | struct request *req, struct nvme_command *cmnd, | |
1050 | enum nvme_zone_mgmt_action action) | |
1051 | { | |
1052 | return BLK_STS_NOTSUPP; | |
1053 | } | |
240e6ee2 KB |
1054 | #endif |
1055 | ||
40267efd SL |
1056 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
1057 | { | |
bafd5909 GL |
1058 | struct gendisk *disk = dev_to_disk(dev); |
1059 | ||
1060 | WARN_ON(nvme_disk_is_ns_head(disk)); | |
1061 | return disk->private_data; | |
40267efd | 1062 | } |
ca064085 | 1063 | |
400b6a7b | 1064 | #ifdef CONFIG_NVME_HWMON |
59e330f8 | 1065 | int nvme_hwmon_init(struct nvme_ctrl *ctrl); |
ed7770f6 | 1066 | void nvme_hwmon_exit(struct nvme_ctrl *ctrl); |
400b6a7b | 1067 | #else |
59e330f8 KB |
1068 | static inline int nvme_hwmon_init(struct nvme_ctrl *ctrl) |
1069 | { | |
1070 | return 0; | |
1071 | } | |
ed7770f6 HR |
1072 | |
1073 | static inline void nvme_hwmon_exit(struct nvme_ctrl *ctrl) | |
1074 | { | |
1075 | } | |
400b6a7b GR |
1076 | #endif |
1077 | ||
6887fc64 SG |
1078 | static inline void nvme_start_request(struct request *rq) |
1079 | { | |
d4d957b5 SG |
1080 | if (rq->cmd_flags & REQ_NVME_MPATH) |
1081 | nvme_mpath_start_request(rq); | |
6887fc64 SG |
1082 | blk_mq_start_request(rq); |
1083 | } | |
1084 | ||
73eefc27 CK |
1085 | static inline bool nvme_ctrl_sgl_supported(struct nvme_ctrl *ctrl) |
1086 | { | |
1087 | return ctrl->sgls & ((1 << 0) | (1 << 1)); | |
1088 | } | |
1089 | ||
d6800634 | 1090 | #ifdef CONFIG_NVME_HOST_AUTH |
e481fc0a SG |
1091 | int __init nvme_init_auth(void); |
1092 | void __exit nvme_exit_auth(void); | |
193a8c7e | 1093 | int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl); |
f50fff73 HR |
1094 | void nvme_auth_stop(struct nvme_ctrl *ctrl); |
1095 | int nvme_auth_negotiate(struct nvme_ctrl *ctrl, int qid); | |
1096 | int nvme_auth_wait(struct nvme_ctrl *ctrl, int qid); | |
f50fff73 HR |
1097 | void nvme_auth_free(struct nvme_ctrl *ctrl); |
1098 | #else | |
193a8c7e SG |
1099 | static inline int nvme_auth_init_ctrl(struct nvme_ctrl *ctrl) |
1100 | { | |
1101 | return 0; | |
1102 | } | |
e481fc0a SG |
1103 | static inline int __init nvme_init_auth(void) |
1104 | { | |
1105 | return 0; | |
1106 | } | |
1107 | static inline void __exit nvme_exit_auth(void) | |
1108 | { | |
1109 | } | |
f50fff73 HR |
1110 | static inline void nvme_auth_stop(struct nvme_ctrl *ctrl) {}; |
1111 | static inline int nvme_auth_negotiate(struct nvme_ctrl *ctrl, int qid) | |
1112 | { | |
1113 | return -EPROTONOSUPPORT; | |
1114 | } | |
1115 | static inline int nvme_auth_wait(struct nvme_ctrl *ctrl, int qid) | |
1116 | { | |
1117 | return NVME_SC_AUTH_REQUIRED; | |
1118 | } | |
1119 | static inline void nvme_auth_free(struct nvme_ctrl *ctrl) {}; | |
1120 | #endif | |
1121 | ||
df21b6b1 LG |
1122 | u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, |
1123 | u8 opcode); | |
62281b9e CH |
1124 | u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode); |
1125 | int nvme_execute_rq(struct request *rq, bool at_head); | |
31a59782 | 1126 | void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects, |
bc8fb906 | 1127 | struct nvme_command *cmd, int status); |
b2702aaa | 1128 | struct nvme_ctrl *nvme_ctrl_from_file(struct file *file); |
24493b8b LG |
1129 | struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid); |
1130 | void nvme_put_ns(struct nvme_ns *ns); | |
df21b6b1 | 1131 | |
43dc9878 AM |
1132 | static inline bool nvme_multi_css(struct nvme_ctrl *ctrl) |
1133 | { | |
1134 | return (ctrl->ctrl_config & NVME_CC_CSS_MASK) == NVME_CC_CSS_CSI; | |
1135 | } | |
1136 | ||
bd83fe6f | 1137 | #ifdef CONFIG_NVME_VERBOSE_ERRORS |
4b682194 CS |
1138 | const char *nvme_get_error_status_str(u16 status); |
1139 | const char *nvme_get_opcode_str(u8 opcode); | |
1140 | const char *nvme_get_admin_opcode_str(u8 opcode); | |
1141 | const char *nvme_get_fabrics_opcode_str(u8 opcode); | |
bd83fe6f | 1142 | #else /* CONFIG_NVME_VERBOSE_ERRORS */ |
4b682194 | 1143 | static inline const char *nvme_get_error_status_str(u16 status) |
bd83fe6f AA |
1144 | { |
1145 | return "I/O Error"; | |
1146 | } | |
4b682194 | 1147 | static inline const char *nvme_get_opcode_str(u8 opcode) |
bd83fe6f AA |
1148 | { |
1149 | return "I/O Cmd"; | |
1150 | } | |
4b682194 | 1151 | static inline const char *nvme_get_admin_opcode_str(u8 opcode) |
bd83fe6f AA |
1152 | { |
1153 | return "Admin Cmd"; | |
1154 | } | |
567da14d | 1155 | |
4b682194 | 1156 | static inline const char *nvme_get_fabrics_opcode_str(u8 opcode) |
567da14d AE |
1157 | { |
1158 | return "Fabrics Cmd"; | |
1159 | } | |
bd83fe6f AA |
1160 | #endif /* CONFIG_NVME_VERBOSE_ERRORS */ |
1161 | ||
7d23e836 | 1162 | static inline const char *nvme_opcode_str(int qid, u8 opcode) |
567da14d | 1163 | { |
567da14d AE |
1164 | return qid ? nvme_get_opcode_str(opcode) : |
1165 | nvme_get_admin_opcode_str(opcode); | |
1166 | } | |
7d23e836 CS |
1167 | |
1168 | static inline const char *nvme_fabrics_opcode_str( | |
1169 | int qid, const struct nvme_command *cmd) | |
1170 | { | |
1171 | if (nvme_is_fabrics(cmd)) | |
1172 | return nvme_get_fabrics_opcode_str(cmd->fabrics.fctype); | |
1173 | ||
1174 | return nvme_opcode_str(qid, cmd->common.opcode); | |
1175 | } | |
f11bb3e2 | 1176 | #endif /* _NVME_H */ |