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Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[linux-2.6-block.git] / drivers / nvme / host / core.c
CommitLineData
bc50ad75 1// SPDX-License-Identifier: GPL-2.0
21d34711
CH		 2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
21d34711
CH		 5 */
6
7#include <linux/blkdev.h>
8#include <linux/blk-mq.h>
fe45e630 9#include <linux/blk-integrity.h>
c95b708d 10#include <linux/compat.h>
5fd4ce1b 11#include <linux/delay.h>
21d34711 12#include <linux/errno.h>
1673f1f0 13#include <linux/hdreg.h>
21d34711 14#include <linux/kernel.h>
5bae7f73 15#include <linux/module.h>
958f2a0f 16#include <linux/backing-dev.h>
21d34711
CH		 17#include <linux/slab.h>
18#include <linux/types.h>
1673f1f0
CH		 19#include <linux/pr.h>
20#include <linux/ptrace.h>
21#include <linux/nvme_ioctl.h>
c5552fde 22#include <linux/pm_qos.h>
a1a825ab 23#include <linux/ratelimit.h>
1673f1f0 24#include <asm/unaligned.h>
21d34711
CH		 25
26#include "nvme.h"
038bd4cb 27#include "fabrics.h"
f50fff73 28#include <linux/nvme-auth.h>
21d34711 29
35fe0d12
HR		 30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
f3ca80fc
CH		 33#define NVME_MINORS (1U << MINORBITS)
34
1a893c2b
CH		 35struct nvme_ns_info {
36 struct nvme_ns_ids ids;
37 u32 nsid;
38 __le32 anagrpid;
39 bool is_shared;
1e4ea66a 40 bool is_readonly;
1a893c2b 41 bool is_ready;
0dd6fff2 42 bool is_removed;
1a893c2b
CH		 43};
44
8ae4e447
MO		 45unsigned int admin_timeout = 60;
46module_param(admin_timeout, uint, 0644);
ba0ba7d3 47MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 48EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 49
8ae4e447
MO		 50unsigned int nvme_io_timeout = 30;
51module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 52MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 53EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 54
b3b1b0b0 55static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 56module_param(shutdown_timeout, byte, 0644);
57MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
58
44e44b29
CH		 59static u8 nvme_max_retries = 5;
60module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 61MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 62
9947d6a0 63static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 64module_param(default_ps_max_latency_us, ulong, 0644);
65MODULE_PARM_DESC(default_ps_max_latency_us,
66 "max power saving latency for new devices; use PM QOS to change per device");
67
c35e30b4
AL		 68static bool force_apst;
69module_param(force_apst, bool, 0644);
70MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
71
ebd8a93a
AB		 72static unsigned long apst_primary_timeout_ms = 100;
73module_param(apst_primary_timeout_ms, ulong, 0644);
74MODULE_PARM_DESC(apst_primary_timeout_ms,
75 "primary APST timeout in ms");
76
77static unsigned long apst_secondary_timeout_ms = 2000;
78module_param(apst_secondary_timeout_ms, ulong, 0644);
79MODULE_PARM_DESC(apst_secondary_timeout_ms,
80 "secondary APST timeout in ms");
81
82static unsigned long apst_primary_latency_tol_us = 15000;
83module_param(apst_primary_latency_tol_us, ulong, 0644);
84MODULE_PARM_DESC(apst_primary_latency_tol_us,
85 "primary APST latency tolerance in us");
86
87static unsigned long apst_secondary_latency_tol_us = 100000;
88module_param(apst_secondary_latency_tol_us, ulong, 0644);
89MODULE_PARM_DESC(apst_secondary_latency_tol_us,
90 "secondary APST latency tolerance in us");
91
b227c59b
RS		 92/*
93 * nvme_wq - hosts nvme related works that are not reset or delete
94 * nvme_reset_wq - hosts nvme reset works
95 * nvme_delete_wq - hosts nvme delete works
96 *
97b2512a
NK		 97 * nvme_wq will host works such as scan, aen handling, fw activation,
98 * keep-alive, periodic reconnects etc. nvme_reset_wq
b227c59b
RS		 99 * runs reset works which also flush works hosted on nvme_wq for
100 * serialization purposes. nvme_delete_wq host controller deletion
101 * works which flush reset works for serialization.
102 */
9a6327d2
SG		 103struct workqueue_struct *nvme_wq;
104EXPORT_SYMBOL_GPL(nvme_wq);
105
b227c59b
RS		 106struct workqueue_struct *nvme_reset_wq;
107EXPORT_SYMBOL_GPL(nvme_reset_wq);
108
109struct workqueue_struct *nvme_delete_wq;
110EXPORT_SYMBOL_GPL(nvme_delete_wq);
111
ab9e00cc
CH		 112static LIST_HEAD(nvme_subsystems);
113static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 114
9843f685 115static DEFINE_IDA(nvme_instance_ida);
f68abd9c 116static dev_t nvme_ctrl_base_chr_devt;
ab21f3d9
RM		 117static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env);
118static const struct class nvme_class = {
119 .name = "nvme",
120 .dev_uevent = nvme_class_uevent,
121};
122
123static const struct class nvme_subsys_class = {
124 .name = "nvme-subsystem",
125};
f3ca80fc 126
2637baed
MI		 127static DEFINE_IDA(nvme_ns_chr_minor_ida);
128static dev_t nvme_ns_chr_devt;
ab21f3d9
RM		 129static const struct class nvme_ns_chr_class = {
130 .name = "nvme-generic",
131};
2637baed 132
12d9f070 133static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB		 134static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
135 unsigned nsid);
b58da2d2
TS		 136static void nvme_update_keep_alive(struct nvme_ctrl *ctrl,
137 struct nvme_command *cmd);
cf39a6bc 138
2405252a 139void nvme_queue_scan(struct nvme_ctrl *ctrl)
50e8d8ee
CH		 140{
141 /*
142 * Only new queue scan work when admin and IO queues are both alive
143 */
e6e7f7ac 144 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE && ctrl->tagset)
50e8d8ee
CH		 145 queue_work(nvme_wq, &ctrl->scan_work);
146}
147
4c75f877
KB		 148/*
149 * Use this function to proceed with scheduling reset_work for a controller
150 * that had previously been set to the resetting state. This is intended for
151 * code paths that can't be interrupted by other reset attempts. A hot removal
152 * may prevent this from succeeding.
153 */
c1ac9a4b 154int nvme_try_sched_reset(struct nvme_ctrl *ctrl)
4c75f877 155{
e6e7f7ac 156 if (nvme_ctrl_state(ctrl) != NVME_CTRL_RESETTING)
4c75f877
KB		 157 return -EBUSY;
158 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
159 return -EBUSY;
160 return 0;
161}
c1ac9a4b 162EXPORT_SYMBOL_GPL(nvme_try_sched_reset);
4c75f877 163
8c4dfea9
VG		 164static void nvme_failfast_work(struct work_struct *work)
165{
166 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
167 struct nvme_ctrl, failfast_work);
168
e6e7f7ac 169 if (nvme_ctrl_state(ctrl) != NVME_CTRL_CONNECTING)
8c4dfea9
VG		 170 return;
171
172 set_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
173 dev_info(ctrl->device, "failfast expired\n");
174 nvme_kick_requeue_lists(ctrl);
175}
176
177static inline void nvme_start_failfast_work(struct nvme_ctrl *ctrl)
178{
179 if (!ctrl->opts || ctrl->opts->fast_io_fail_tmo == -1)
180 return;
181
182 schedule_delayed_work(&ctrl->failfast_work,
183 ctrl->opts->fast_io_fail_tmo * HZ);
184}
185
186static inline void nvme_stop_failfast_work(struct nvme_ctrl *ctrl)
187{
188 if (!ctrl->opts)
189 return;
190
191 cancel_delayed_work_sync(&ctrl->failfast_work);
192 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
193}
194
195
d86c4d8e
CH		 196int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
197{
198 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
199 return -EBUSY;
b227c59b 200 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 201 return -EBUSY;
202 return 0;
203}
204EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
205
2405252a 206int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 207{
208 int ret;
209
210 ret = nvme_reset_ctrl(ctrl);
8000d1fd 211 if (!ret) {
d86c4d8e 212 flush_work(&ctrl->reset_work);
e6e7f7ac 213 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
8000d1fd
NC		 214 ret = -ENETRESET;
215 }
216
d86c4d8e
CH		 217 return ret;
218}
219
a686ed75 220static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
c5017e85 221{
77d0612d 222 dev_info(ctrl->device,
e5ea42fa 223 "Removing ctrl: NQN \"%s\"\n", nvmf_ctrl_subsysnqn(ctrl));
77d0612d 224
4054637c 225 flush_work(&ctrl->reset_work);
6cd53d14
CH		 226 nvme_stop_ctrl(ctrl);
227 nvme_remove_namespaces(ctrl);
c5017e85 228 ctrl->ops->delete_ctrl(ctrl);
6cd53d14 229 nvme_uninit_ctrl(ctrl);
c5017e85
CH		 230}
231
a686ed75
BVA		 232static void nvme_delete_ctrl_work(struct work_struct *work)
233{
234 struct nvme_ctrl *ctrl =
235 container_of(work, struct nvme_ctrl, delete_work);
236
237 nvme_do_delete_ctrl(ctrl);
238}
239
c5017e85
CH		 240int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
241{
242 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
243 return -EBUSY;
b227c59b 244 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 245 return -EBUSY;
246 return 0;
247}
248EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
249
942e21c0 250void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
c5017e85 251{
c5017e85 252 /*
01fc08ff
YY		 253 * Keep a reference until nvme_do_delete_ctrl() complete,
254 * since ->delete_ctrl can free the controller.
c5017e85
CH		 255 */
256 nvme_get_ctrl(ctrl);
6721c18a 257 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
b9c77583 258 nvme_do_delete_ctrl(ctrl);
c5017e85 259 nvme_put_ctrl(ctrl);
c5017e85 260}
c5017e85 261
2f9c1736 262static blk_status_t nvme_error_status(u16 status)
27fa9bc5 263{
2f9c1736 264 switch (status & 0x7ff) {
27fa9bc5 265 case NVME_SC_SUCCESS:
2a842aca 266 return BLK_STS_OK;
27fa9bc5 267 case NVME_SC_CAP_EXCEEDED:
2a842aca 268 return BLK_STS_NOSPC;
e96fef2c 269 case NVME_SC_LBA_RANGE:
35038bff
KB		 270 case NVME_SC_CMD_INTERRUPTED:
271 case NVME_SC_NS_NOT_READY:
e96fef2c
KB		 272 return BLK_STS_TARGET;
273 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 274 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 275 case NVME_SC_INVALID_OPCODE:
276 case NVME_SC_INVALID_FIELD:
277 case NVME_SC_INVALID_NS:
2a842aca 278 return BLK_STS_NOTSUPP;
e02ab023
JG		 279 case NVME_SC_WRITE_FAULT:
280 case NVME_SC_READ_ERROR:
281 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 282 case NVME_SC_ACCESS_DENIED:
283 case NVME_SC_READ_ONLY:
e96fef2c 284 case NVME_SC_COMPARE_FAILED:
2a842aca 285 return BLK_STS_MEDIUM;
a751da33
CH		 286 case NVME_SC_GUARD_CHECK:
287 case NVME_SC_APPTAG_CHECK:
288 case NVME_SC_REFTAG_CHECK:
289 case NVME_SC_INVALID_PI:
290 return BLK_STS_PROTECTION;
291 case NVME_SC_RESERVATION_CONFLICT:
7ba15083 292 return BLK_STS_RESV_CONFLICT;
1c0d12c0
SG		 293 case NVME_SC_HOST_PATH_ERROR:
294 return BLK_STS_TRANSPORT;
afaf5c6c
KB		 295 case NVME_SC_ZONE_TOO_MANY_ACTIVE:
296 return BLK_STS_ZONE_ACTIVE_RESOURCE;
297 case NVME_SC_ZONE_TOO_MANY_OPEN:
298 return BLK_STS_ZONE_OPEN_RESOURCE;
2a842aca
CH		 299 default:
300 return BLK_STS_IOERR;
27fa9bc5
CH		 301 }
302}
27fa9bc5 303
49cd84b6
KB		 304static void nvme_retry_req(struct request *req)
305{
49cd84b6
KB		 306 unsigned long delay = 0;
307 u16 crd;
308
309 /* The mask and shift result must be <= 3 */
310 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
f9063a53
MI		 311 if (crd)
312 delay = nvme_req(req)->ctrl->crdt[crd - 1] * 100;
49cd84b6
KB		 313
314 nvme_req(req)->retries++;
315 blk_mq_requeue_request(req, false);
316 blk_mq_delay_kick_requeue_list(req->q, delay);
317}
318
bd83fe6f
AA		 319static void nvme_log_error(struct request *req)
320{
321 struct nvme_ns *ns = req->q->queuedata;
322 struct nvme_request *nr = nvme_req(req);
323
324 if (ns) {
9419e71b 325 pr_err_ratelimited("%s: %s(0x%x) @ LBA %llu, %u blocks, %s (sct 0x%x / sc 0x%x) %s%s\n",
bd83fe6f
AA		 326 ns->disk ? ns->disk->disk_name : "?",
327 nvme_get_opcode_str(nr->cmd->common.opcode),
328 nr->cmd->common.opcode,
0372dd4e 329 nvme_sect_to_lba(ns->head, blk_rq_pos(req)),
9419e71b 330 blk_rq_bytes(req) >> ns->head->lba_shift,
bd83fe6f
AA		 331 nvme_get_error_status_str(nr->status),
332 nr->status >> 8 & 7, /* Status Code Type */
333 nr->status & 0xff, /* Status Code */
334 nr->status & NVME_SC_MORE ? "MORE " : "",
335 nr->status & NVME_SC_DNR ? "DNR " : "");
336 return;
337 }
338
339 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s\n",
340 dev_name(nr->ctrl->device),
341 nvme_get_admin_opcode_str(nr->cmd->common.opcode),
342 nr->cmd->common.opcode,
343 nvme_get_error_status_str(nr->status),
344 nr->status >> 8 & 7, /* Status Code Type */
345 nr->status & 0xff, /* Status Code */
346 nr->status & NVME_SC_MORE ? "MORE " : "",
347 nr->status & NVME_SC_DNR ? "DNR " : "");
348}
349
9f079dda
AA		 350static void nvme_log_err_passthru(struct request *req)
351{
352 struct nvme_ns *ns = req->q->queuedata;
353 struct nvme_request *nr = nvme_req(req);
354
355 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s"
356 "cdw10=0x%x cdw11=0x%x cdw12=0x%x cdw13=0x%x cdw14=0x%x cdw15=0x%x\n",
357 ns ? ns->disk->disk_name : dev_name(nr->ctrl->device),
358 ns ? nvme_get_opcode_str(nr->cmd->common.opcode) :
359 nvme_get_admin_opcode_str(nr->cmd->common.opcode),
360 nr->cmd->common.opcode,
361 nvme_get_error_status_str(nr->status),
362 nr->status >> 8 & 7, /* Status Code Type */
363 nr->status & 0xff, /* Status Code */
364 nr->status & NVME_SC_MORE ? "MORE " : "",
365 nr->status & NVME_SC_DNR ? "DNR " : "",
366 nr->cmd->common.cdw10,
367 nr->cmd->common.cdw11,
368 nr->cmd->common.cdw12,
369 nr->cmd->common.cdw13,
370 nr->cmd->common.cdw14,
371 nr->cmd->common.cdw14);
372}
373
5ddaabe8
CH		 374enum nvme_disposition {
375 COMPLETE,
376 RETRY,
377 FAILOVER,
f50fff73 378 AUTHENTICATE,
5ddaabe8
CH		 379};
380
381static inline enum nvme_disposition nvme_decide_disposition(struct request *req)
77f02a7a 382{
5ddaabe8
CH		 383 if (likely(nvme_req(req)->status == 0))
384 return COMPLETE;
908e4564 385
5ddaabe8
CH		 386 if (blk_noretry_request(req) ||
387 (nvme_req(req)->status & NVME_SC_DNR) ||
388 nvme_req(req)->retries >= nvme_max_retries)
389 return COMPLETE;
ca5554a6 390
44350336
HR		 391 if ((nvme_req(req)->status & 0x7ff) == NVME_SC_AUTH_REQUIRED)
392 return AUTHENTICATE;
393
5ddaabe8 394 if (req->cmd_flags & REQ_NVME_MPATH) {
5eac5f33
CL		 395 if (nvme_is_path_error(nvme_req(req)->status) ||
396 blk_queue_dying(req->q))
5ddaabe8 397 return FAILOVER;
5eac5f33
CL		 398 } else {
399 if (blk_queue_dying(req->q))
400 return COMPLETE;
5ddaabe8 401 }
16686f3a 402
5ddaabe8
CH		 403 return RETRY;
404}
6e3ca03e 405
c234a653 406static inline void nvme_end_req_zoned(struct request *req)
5ddaabe8 407{
5ddaabe8 408 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
0372dd4e
DW		 409 req_op(req) == REQ_OP_ZONE_APPEND) {
410 struct nvme_ns *ns = req->q->queuedata;
411
412 req->__sector = nvme_lba_to_sect(ns->head,
240e6ee2 413 le64_to_cpu(nvme_req(req)->result.u64));
0372dd4e 414 }
c234a653
JA		 415}
416
2fe7b422
KB		 417static inline void __nvme_end_req(struct request *req)
418{
419 nvme_end_req_zoned(req);
420 nvme_trace_bio_complete(req);
421 if (req->cmd_flags & REQ_NVME_MPATH)
422 nvme_mpath_end_request(req);
423}
424
a2e4c5f5 425void nvme_end_req(struct request *req)
c234a653
JA		 426{
427 blk_status_t status = nvme_error_status(nvme_req(req)->status);
35fe0d12 428
9f079dda
AA		 429 if (unlikely(nvme_req(req)->status && !(req->rq_flags & RQF_QUIET))) {
430 if (blk_rq_is_passthrough(req))
431 nvme_log_err_passthru(req);
432 else
433 nvme_log_error(req);
434 }
2fe7b422 435 __nvme_end_req(req);
908e4564 436 blk_mq_end_request(req, status);
77f02a7a 437}
5ddaabe8
CH		 438
439void nvme_complete_rq(struct request *req)
440{
f50fff73
HR		 441 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
442
5ddaabe8
CH		 443 trace_nvme_complete_rq(req);
444 nvme_cleanup_cmd(req);
445
774a9636
US		 446 /*
447 * Completions of long-running commands should not be able to
448 * defer sending of periodic keep alives, since the controller
449 * may have completed processing such commands a long time ago
450 * (arbitrarily close to command submission time).
451 * req->deadline - req->timeout is the command submission time
452 * in jiffies.
453 */
454 if (ctrl->kas &&
455 req->deadline - req->timeout >= ctrl->ka_last_check_time)
f50fff73 456 ctrl->comp_seen = true;
5ddaabe8
CH		 457
458 switch (nvme_decide_disposition(req)) {
459 case COMPLETE:
460 nvme_end_req(req);
461 return;
462 case RETRY:
463 nvme_retry_req(req);
464 return;
465 case FAILOVER:
466 nvme_failover_req(req);
467 return;
f50fff73 468 case AUTHENTICATE:
d6800634 469#ifdef CONFIG_NVME_HOST_AUTH
f50fff73
HR		 470 queue_work(nvme_wq, &ctrl->dhchap_auth_work);
471 nvme_retry_req(req);
472#else
473 nvme_end_req(req);
474#endif
475 return;
5ddaabe8
CH		 476 }
477}
77f02a7a
CH		 478EXPORT_SYMBOL_GPL(nvme_complete_rq);
479
c234a653
JA		 480void nvme_complete_batch_req(struct request *req)
481{
00e757b6 482 trace_nvme_complete_rq(req);
c234a653 483 nvme_cleanup_cmd(req);
2fe7b422 484 __nvme_end_req(req);
c234a653
JA		 485}
486EXPORT_SYMBOL_GPL(nvme_complete_batch_req);
487
dda3248e
CL		 488/*
489 * Called to unwind from ->queue_rq on a failed command submission so that the
490 * multipathing code gets called to potentially failover to another path.
491 * The caller needs to unwind all transport specific resource allocations and
492 * must return propagate the return value.
493 */
494blk_status_t nvme_host_path_error(struct request *req)
495{
496 nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR;
497 blk_mq_set_request_complete(req);
498 nvme_complete_rq(req);
499 return BLK_STS_OK;
500}
501EXPORT_SYMBOL_GPL(nvme_host_path_error);
502
2dd6532e 503bool nvme_cancel_request(struct request *req, void *data)
c55a2fd4 504{
c55a2fd4
ML		 505 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
506 "Cancelling I/O %d", req->tag);
507
d4f1d5f7
LY		 508 /* don't abort one completed or idle request */
509 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT)
78ca4072
ML		 510 return true;
511
2dc3947b 512 nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD;
d3589381 513 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
15f73f5b 514 blk_mq_complete_request(req);
7baa8572 515 return true;
c55a2fd4
ML		 516}
517EXPORT_SYMBOL_GPL(nvme_cancel_request);
518
25479069
CL		 519void nvme_cancel_tagset(struct nvme_ctrl *ctrl)
520{
521 if (ctrl->tagset) {
522 blk_mq_tagset_busy_iter(ctrl->tagset,
523 nvme_cancel_request, ctrl);
524 blk_mq_tagset_wait_completed_request(ctrl->tagset);
525 }
526}
527EXPORT_SYMBOL_GPL(nvme_cancel_tagset);
528
529void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl)
530{
531 if (ctrl->admin_tagset) {
532 blk_mq_tagset_busy_iter(ctrl->admin_tagset,
533 nvme_cancel_request, ctrl);
534 blk_mq_tagset_wait_completed_request(ctrl->admin_tagset);
535 }
536}
537EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset);
538
bb8d261e
CH		 539bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
540 enum nvme_ctrl_state new_state)
541{
f6b6a28e 542 enum nvme_ctrl_state old_state;
0a72bbba 543 unsigned long flags;
bb8d261e
CH		 544 bool changed = false;
545
0a72bbba 546 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e 547
e6e7f7ac 548 old_state = nvme_ctrl_state(ctrl);
bb8d261e
CH		 549 switch (new_state) {
550 case NVME_CTRL_LIVE:
551 switch (old_state) {
7d2e8008 552 case NVME_CTRL_NEW:
bb8d261e 553 case NVME_CTRL_RESETTING:
ad6a0a52 554 case NVME_CTRL_CONNECTING:
bb8d261e 555 changed = true;
df561f66 556 fallthrough;
bb8d261e
CH		 557 default:
558 break;
559 }
560 break;
561 case NVME_CTRL_RESETTING:
562 switch (old_state) {
563 case NVME_CTRL_NEW:
def61eca 564 case NVME_CTRL_LIVE:
def61eca 565 changed = true;
df561f66 566 fallthrough;
def61eca
CH		 567 default:
568 break;
569 }
570 break;
ad6a0a52 571 case NVME_CTRL_CONNECTING:
def61eca 572 switch (old_state) {
b754a32c 573 case NVME_CTRL_NEW:
3cec7f9d 574 case NVME_CTRL_RESETTING:
bb8d261e 575 changed = true;
df561f66 576 fallthrough;
bb8d261e
CH		 577 default:
578 break;
579 }
580 break;
581 case NVME_CTRL_DELETING:
582 switch (old_state) {
583 case NVME_CTRL_LIVE:
584 case NVME_CTRL_RESETTING:
ad6a0a52 585 case NVME_CTRL_CONNECTING:
bb8d261e 586 changed = true;
df561f66 587 fallthrough;
bb8d261e
CH		 588 default:
589 break;
590 }
591 break;
ecca390e
SG		 592 case NVME_CTRL_DELETING_NOIO:
593 switch (old_state) {
594 case NVME_CTRL_DELETING:
595 case NVME_CTRL_DEAD:
596 changed = true;
df561f66 597 fallthrough;
ecca390e
SG		 598 default:
599 break;
600 }
601 break;
0ff9d4e1
KB		 602 case NVME_CTRL_DEAD:
603 switch (old_state) {
604 case NVME_CTRL_DELETING:
605 changed = true;
df561f66 606 fallthrough;
0ff9d4e1
KB		 607 default:
608 break;
609 }
610 break;
bb8d261e
CH		 611 default:
612 break;
613 }
bb8d261e 614
c1ac9a4b 615 if (changed) {
e6e7f7ac 616 WRITE_ONCE(ctrl->state, new_state);
c1ac9a4b
KB		 617 wake_up_all(&ctrl->state_wq);
618 }
bb8d261e 619
0a72bbba 620 spin_unlock_irqrestore(&ctrl->lock, flags);
8c4dfea9
VG		 621 if (!changed)
622 return false;
623
e6e7f7ac 624 if (new_state == NVME_CTRL_LIVE) {
8c4dfea9
VG		 625 if (old_state == NVME_CTRL_CONNECTING)
626 nvme_stop_failfast_work(ctrl);
32acab31 627 nvme_kick_requeue_lists(ctrl);
e6e7f7ac 628 } else if (new_state == NVME_CTRL_CONNECTING &&
8c4dfea9
VG		 629 old_state == NVME_CTRL_RESETTING) {
630 nvme_start_failfast_work(ctrl);
631 }
bb8d261e
CH		 632 return changed;
633}
634EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
635
c1ac9a4b
KB		 636/*
637 * Waits for the controller state to be resetting, or returns false if it is
638 * not possible to ever transition to that state.
639 */
640bool nvme_wait_reset(struct nvme_ctrl *ctrl)
641{
642 wait_event(ctrl->state_wq,
643 nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) ||
644 nvme_state_terminal(ctrl));
e6e7f7ac 645 return nvme_ctrl_state(ctrl) == NVME_CTRL_RESETTING;
c1ac9a4b
KB		 646}
647EXPORT_SYMBOL_GPL(nvme_wait_reset);
648
ed754e5d
CH		 649static void nvme_free_ns_head(struct kref *ref)
650{
651 struct nvme_ns_head *head =
652 container_of(ref, struct nvme_ns_head, ref);
653
32acab31 654 nvme_mpath_remove_disk(head);
8b850475 655 ida_free(&head->subsys->ns_ida, head->instance);
f5ad3991 656 cleanup_srcu_struct(&head->srcu);
12d9f070 657 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 658 kfree(head);
659}
660
1496bd49 661bool nvme_tryget_ns_head(struct nvme_ns_head *head)
871ca3ef
CH		 662{
663 return kref_get_unless_zero(&head->ref);
664}
665
1496bd49 666void nvme_put_ns_head(struct nvme_ns_head *head)
ed754e5d
CH		 667{
668 kref_put(&head->ref, nvme_free_ns_head);
669}
670
1673f1f0
CH		 671static void nvme_free_ns(struct kref *kref)
672{
673 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
674
1673f1f0 675 put_disk(ns->disk);
ed754e5d 676 nvme_put_ns_head(ns->head);
075790eb 677 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 678 kfree(ns);
679}
680
be647e2c 681bool nvme_get_ns(struct nvme_ns *ns)
4c74d1f8
KJ		 682{
683 return kref_get_unless_zero(&ns->kref);
684}
685
24493b8b 686void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 687{
688 kref_put(&ns->kref, nvme_free_ns);
689}
24493b8b 690EXPORT_SYMBOL_NS_GPL(nvme_put_ns, NVME_TARGET_PASSTHRU);
1673f1f0 691
bb06ec31
JS		 692static inline void nvme_clear_nvme_request(struct request *req)
693{
ae5e6886 694 nvme_req(req)->status = 0;
c03fd85d
CK		 695 nvme_req(req)->retries = 0;
696 nvme_req(req)->flags = 0;
697 req->rq_flags |= RQF_DONTPREP;
bb06ec31
JS		 698}
699
e559398f
CH		 700/* initialize a passthrough request */
701void nvme_init_request(struct request *req, struct nvme_command *cmd)
39dfe844 702{
9f079dda
AA		 703 struct nvme_request *nr = nvme_req(req);
704 bool logging_enabled;
705
706 if (req->q->queuedata) {
707 struct nvme_ns *ns = req->q->disk->private_data;
708
1f4137e8 709 logging_enabled = ns->head->passthru_err_log_enabled;
0d2e7c84 710 req->timeout = NVME_IO_TIMEOUT;
9f079dda
AA		 711 } else { /* no queuedata implies admin queue */
712 logging_enabled = nr->ctrl->passthru_err_log_enabled;
dc96f938 713 req->timeout = NVME_ADMIN_TIMEOUT;
9f079dda
AA		 714 }
715
716 if (!logging_enabled)
717 req->rq_flags |= RQF_QUIET;
21d34711 718
f4b9e6c9
KB		 719 /* passthru commands should let the driver set the SGL flags */
720 cmd->common.flags &= ~NVME_CMD_SGL_ALL;
721
21d34711 722 req->cmd_flags |= REQ_FAILFAST_DRIVER;
be42a33b 723 if (req->mq_hctx->type == HCTX_TYPE_POLL)
6ce913fe 724 req->cmd_flags |= REQ_POLLED;
bb06ec31 725 nvme_clear_nvme_request(req);
9f079dda 726 memcpy(nr->cmd, cmd, sizeof(*cmd));
39dfe844 727}
e559398f 728EXPORT_SYMBOL_GPL(nvme_init_request);
39dfe844 729
a9715744
TC		 730/*
731 * For something we're not in a state to send to the device the default action
732 * is to busy it and retry it after the controller state is recovered. However,
733 * if the controller is deleting or if anything is marked for failfast or
734 * nvme multipath it is immediately failed.
735 *
736 * Note: commands used to initialize the controller will be marked for failfast.
737 * Note: nvme cli/ioctl commands are marked for failfast.
738 */
739blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl,
740 struct request *rq)
741{
e6e7f7ac
KB		 742 enum nvme_ctrl_state state = nvme_ctrl_state(ctrl);
743
744 if (state != NVME_CTRL_DELETING_NOIO &&
745 state != NVME_CTRL_DELETING &&
746 state != NVME_CTRL_DEAD &&
a9715744
TC		 747 !test_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags) &&
748 !blk_noretry_request(rq) && !(rq->cmd_flags & REQ_NVME_MPATH))
749 return BLK_STS_RESOURCE;
750 return nvme_host_path_error(rq);
751}
752EXPORT_SYMBOL_GPL(nvme_fail_nonready_command);
753
754bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq,
6d3c7fb1 755 bool queue_live, enum nvme_ctrl_state state)
a9715744
TC		 756{
757 struct nvme_request *req = nvme_req(rq);
758
759 /*
760 * currently we have a problem sending passthru commands
761 * on the admin_q if the controller is not LIVE because we can't
762 * make sure that they are going out after the admin connect,
763 * controller enable and/or other commands in the initialization
764 * sequence. until the controller will be LIVE, fail with
765 * BLK_STS_RESOURCE so that they will be rescheduled.
766 */
767 if (rq->q == ctrl->admin_q && (req->flags & NVME_REQ_USERCMD))
768 return false;
769
770 if (ctrl->ops->flags & NVME_F_FABRICS) {
771 /*
772 * Only allow commands on a live queue, except for the connect
773 * command, which is require to set the queue live in the
774 * appropinquate states.
775 */
6d3c7fb1 776 switch (state) {
a9715744
TC		 777 case NVME_CTRL_CONNECTING:
778 if (blk_rq_is_passthrough(rq) && nvme_is_fabrics(req->cmd) &&
f50fff73
HR		 779 (req->cmd->fabrics.fctype == nvme_fabrics_type_connect ||
780 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_send ||
781 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_receive))
a9715744
TC		 782 return true;
783 break;
784 default:
785 break;
786 case NVME_CTRL_DEAD:
787 return false;
788 }
789 }
790
791 return queue_live;
792}
793EXPORT_SYMBOL_GPL(__nvme_check_ready);
794
8093f7ca
ML		 795static inline void nvme_setup_flush(struct nvme_ns *ns,
796 struct nvme_command *cmnd)
797{
9c3d2929 798 memset(cmnd, 0, sizeof(*cmnd));
8093f7ca 799 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 800 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 801}
802
fc17b653 803static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 804 struct nvme_command *cmnd)
805{
b35ba01e 806 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 807 struct nvme_dsm_range *range;
b35ba01e 808 struct bio *bio;
8093f7ca 809
530436c4
EH		 810 /*
811 * Some devices do not consider the DSM 'Number of Ranges' field when
812 * determining how much data to DMA. Always allocate memory for maximum
813 * number of segments to prevent device reading beyond end of buffer.
814 */
815 static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES;
816
817 range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN);
cb5b7262
JA		 818 if (!range) {
819 /*
820 * If we fail allocation our range, fallback to the controller
821 * discard page. If that's also busy, it's safe to return
822 * busy, as we know we can make progress once that's freed.
823 */
824 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
825 return BLK_STS_RESOURCE;
826
827 range = page_address(ns->ctrl->discard_page);
828 }
8093f7ca 829
37f0dc2e 830 if (queue_max_discard_segments(req->q) == 1) {
0372dd4e 831 u64 slba = nvme_sect_to_lba(ns->head, blk_rq_pos(req));
9419e71b 832 u32 nlb = blk_rq_sectors(req) >> (ns->head->lba_shift - 9);
37f0dc2e
ML		 833
834 range[0].cattr = cpu_to_le32(0);
835 range[0].nlb = cpu_to_le32(nlb);
836 range[0].slba = cpu_to_le64(slba);
837 n = 1;
838 } else {
839 __rq_for_each_bio(bio, req) {
0372dd4e
DW		 840 u64 slba = nvme_sect_to_lba(ns->head,
841 bio->bi_iter.bi_sector);
9419e71b 842 u32 nlb = bio->bi_iter.bi_size >> ns->head->lba_shift;
37f0dc2e
ML		 843
844 if (n < segments) {
845 range[n].cattr = cpu_to_le32(0);
846 range[n].nlb = cpu_to_le32(nlb);
847 range[n].slba = cpu_to_le64(slba);
848 }
849 n++;
8cb6af7b 850 }
b35ba01e
CH		 851 }
852
853 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA		 854 if (virt_to_page(range) == ns->ctrl->discard_page)
855 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
856 else
857 kfree(range);
fc17b653 858 return BLK_STS_IOERR;
b35ba01e 859 }
8093f7ca 860
9c3d2929 861 memset(cmnd, 0, sizeof(*cmnd));
8093f7ca 862 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 863 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 864 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 865 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
866
4bee16da 867 bvec_set_virt(&req->special_vec, range, alloc_size);
f9d03f96 868 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 869
fc17b653 870 return BLK_STS_OK;
8093f7ca 871}
8093f7ca 872
4020aad8
KB		 873static void nvme_set_ref_tag(struct nvme_ns *ns, struct nvme_command *cmnd,
874 struct request *req)
875{
876 u32 upper, lower;
877 u64 ref48;
878
879 /* both rw and write zeroes share the same reftag format */
9419e71b 880 switch (ns->head->guard_type) {
4020aad8
KB		 881 case NVME_NVM_NS_16B_GUARD:
882 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
883 break;
884 case NVME_NVM_NS_64B_GUARD:
885 ref48 = ext_pi_ref_tag(req);
886 lower = lower_32_bits(ref48);
887 upper = upper_32_bits(ref48);
888
889 cmnd->rw.reftag = cpu_to_le32(lower);
890 cmnd->rw.cdw3 = cpu_to_le32(upper);
891 break;
892 default:
893 break;
894 }
895}
896
6e02318e
CK		 897static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
898 struct request *req, struct nvme_command *cmnd)
899{
9c3d2929
JA		 900 memset(cmnd, 0, sizeof(*cmnd));
901
6e02318e
CK		 902 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
903 return nvme_setup_discard(ns, req, cmnd);
904
905 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
906 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
907 cmnd->write_zeroes.slba =
0372dd4e 908 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req)));
6e02318e 909 cmnd->write_zeroes.length =
9419e71b 910 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1);
00b33cf3 911
9419e71b
DW		 912 if (!(req->cmd_flags & REQ_NOUNMAP) &&
913 (ns->head->features & NVME_NS_DEAC))
1b96f862
CH		 914 cmnd->write_zeroes.control |= cpu_to_le16(NVME_WZ_DEAC);
915
0372dd4e 916 if (nvme_ns_has_pi(ns->head)) {
1b96f862 917 cmnd->write_zeroes.control |= cpu_to_le16(NVME_RW_PRINFO_PRACT);
00b33cf3 918
9419e71b 919 switch (ns->head->pi_type) {
00b33cf3
KJ		 920 case NVME_NS_DPS_PI_TYPE1:
921 case NVME_NS_DPS_PI_TYPE2:
4020aad8 922 nvme_set_ref_tag(ns, cmnd, req);
00b33cf3
KJ		 923 break;
924 }
925 }
926
6e02318e
CK		 927 return BLK_STS_OK;
928}
929
ebe6d874 930static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
240e6ee2
KB		 931 struct request *req, struct nvme_command *cmnd,
932 enum nvme_opcode op)
8093f7ca
ML		 933{
934 u16 control = 0;
935 u32 dsmgmt = 0;
936
937 if (req->cmd_flags & REQ_FUA)
938 control |= NVME_RW_FUA;
939 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
940 control |= NVME_RW_LR;
941
942 if (req->cmd_flags & REQ_RAHEAD)
943 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
944
240e6ee2 945 cmnd->rw.opcode = op;
a9a7e30f 946 cmnd->rw.flags = 0;
ed754e5d 947 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
4020aad8
KB		 948 cmnd->rw.cdw2 = 0;
949 cmnd->rw.cdw3 = 0;
a9a7e30f 950 cmnd->rw.metadata = 0;
0372dd4e
DW		 951 cmnd->rw.slba =
952 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req)));
9419e71b
DW		 953 cmnd->rw.length =
954 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1);
a9a7e30f
JA		 955 cmnd->rw.reftag = 0;
956 cmnd->rw.apptag = 0;
957 cmnd->rw.appmask = 0;
8093f7ca 958
9419e71b 959 if (ns->head->ms) {
715ea9e0
CH		 960 /*
961 * If formated with metadata, the block layer always provides a
962 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
963 * we enable the PRACT bit for protection information or set the
964 * namespace capacity to zero to prevent any I/O.
965 */
966 if (!blk_integrity_rq(req)) {
0372dd4e 967 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns->head)))
715ea9e0
CH		 968 return BLK_STS_NOTSUPP;
969 control |= NVME_RW_PRINFO_PRACT;
970 }
971
9419e71b 972 switch (ns->head->pi_type) {
8093f7ca
ML		 973 case NVME_NS_DPS_PI_TYPE3:
974 control |= NVME_RW_PRINFO_PRCHK_GUARD;
975 break;
976 case NVME_NS_DPS_PI_TYPE1:
977 case NVME_NS_DPS_PI_TYPE2:
978 control |= NVME_RW_PRINFO_PRCHK_GUARD |
979 NVME_RW_PRINFO_PRCHK_REF;
240e6ee2
KB		 980 if (op == nvme_cmd_zone_append)
981 control |= NVME_RW_APPEND_PIREMAP;
4020aad8 982 nvme_set_ref_tag(ns, cmnd, req);
8093f7ca
ML		 983 break;
984 }
8093f7ca
ML		 985 }
986
987 cmnd->rw.control = cpu_to_le16(control);
988 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 989 return 0;
8093f7ca
ML		 990}
991
f7f1fc36
MG		 992void nvme_cleanup_cmd(struct request *req)
993{
f7f1fc36 994 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
fc97e942 995 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
cb5b7262 996
3973e15f 997 if (req->special_vec.bv_page == ctrl->discard_page)
fc97e942 998 clear_bit_unlock(0, &ctrl->discard_page_busy);
cb5b7262 999 else
3973e15f 1000 kfree(bvec_virt(&req->special_vec));
e5d574ab 1001 req->rq_flags &= ~RQF_SPECIAL_PAYLOAD;
f7f1fc36
MG		 1002 }
1003}
1004EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
1005
f4b9e6c9 1006blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req)
8093f7ca 1007{
f4b9e6c9 1008 struct nvme_command *cmd = nvme_req(req)->cmd;
fc17b653 1009 blk_status_t ret = BLK_STS_OK;
8093f7ca 1010
9c3d2929 1011 if (!(req->rq_flags & RQF_DONTPREP))
c03fd85d 1012 nvme_clear_nvme_request(req);
987f699a 1013
aebf526b
CH		 1014 switch (req_op(req)) {
1015 case REQ_OP_DRV_IN:
1016 case REQ_OP_DRV_OUT:
f4b9e6c9 1017 /* these are setup prior to execution in nvme_init_request() */
aebf526b
CH		 1018 break;
1019 case REQ_OP_FLUSH:
8093f7ca 1020 nvme_setup_flush(ns, cmd);
aebf526b 1021 break;
240e6ee2
KB		 1022 case REQ_OP_ZONE_RESET_ALL:
1023 case REQ_OP_ZONE_RESET:
1024 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET);
1025 break;
1026 case REQ_OP_ZONE_OPEN:
1027 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN);
1028 break;
1029 case REQ_OP_ZONE_CLOSE:
1030 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE);
1031 break;
1032 case REQ_OP_ZONE_FINISH:
1033 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH);
1034 break;
e850fd16 1035 case REQ_OP_WRITE_ZEROES:
6e02318e
CK		 1036 ret = nvme_setup_write_zeroes(ns, req, cmd);
1037 break;
aebf526b 1038 case REQ_OP_DISCARD:
8093f7ca 1039 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 1040 break;
1041 case REQ_OP_READ:
240e6ee2
KB		 1042 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read);
1043 break;
aebf526b 1044 case REQ_OP_WRITE:
240e6ee2
KB		 1045 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write);
1046 break;
1047 case REQ_OP_ZONE_APPEND:
1048 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append);
aebf526b
CH		 1049 break;
1050 default:
1051 WARN_ON_ONCE(1);
fc17b653 1052 return BLK_STS_IOERR;
aebf526b 1053 }
8093f7ca 1054
e7006de6 1055 cmd->common.command_id = nvme_cid(req);
5d87eb94 1056 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 1057 return ret;
1058}
1059EXPORT_SYMBOL_GPL(nvme_setup_cmd);
1060
ae5e6886
KB		 1061/*
1062 * Return values:
1063 * 0: success
1064 * >0: nvme controller's cqe status response
1065 * <0: kernel error in lieu of controller response
1066 */
62281b9e 1067int nvme_execute_rq(struct request *rq, bool at_head)
ae5e6886
KB		 1068{
1069 blk_status_t status;
1070
b84ba30b 1071 status = blk_execute_rq(rq, at_head);
ae5e6886
KB		 1072 if (nvme_req(rq)->flags & NVME_REQ_CANCELLED)
1073 return -EINTR;
1074 if (nvme_req(rq)->status)
1075 return nvme_req(rq)->status;
1076 return blk_status_to_errno(status);
1077}
62281b9e 1078EXPORT_SYMBOL_NS_GPL(nvme_execute_rq, NVME_TARGET_PASSTHRU);
ae5e6886 1079
4160982e
CH		 1080/*
1081 * Returns 0 on success. If the result is negative, it's a Linux error code;
1082 * if the result is positive, it's an NVM Express status code
1083 */
1084int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 1085 union nvme_result *result, void *buffer, unsigned bufflen,
bd2687f2 1086 int qid, nvme_submit_flags_t flags)
4160982e
CH		 1087{
1088 struct request *req;
1089 int ret;
bd2687f2 1090 blk_mq_req_flags_t blk_flags = 0;
4160982e 1091
bd2687f2
HR		 1092 if (flags & NVME_SUBMIT_NOWAIT)
1093 blk_flags |= BLK_MQ_REQ_NOWAIT;
1094 if (flags & NVME_SUBMIT_RESERVED)
1095 blk_flags |= BLK_MQ_REQ_RESERVED;
39dfe844 1096 if (qid == NVME_QID_ANY)
bd2687f2 1097 req = blk_mq_alloc_request(q, nvme_req_op(cmd), blk_flags);
39dfe844 1098 else
bd2687f2 1099 req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), blk_flags,
b10907b8 1100 qid - 1);
e559398f 1101
4160982e
CH		 1102 if (IS_ERR(req))
1103 return PTR_ERR(req);
e559398f 1104 nvme_init_request(req, cmd);
48dae466
HR		 1105 if (flags & NVME_SUBMIT_RETRY)
1106 req->cmd_flags &= ~REQ_FAILFAST_DRIVER;
4160982e 1107
21d34711
CH		 1108 if (buffer && bufflen) {
1109 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
1110 if (ret)
1111 goto out;
4160982e
CH		 1112 }
1113
bd2687f2 1114 ret = nvme_execute_rq(req, flags & NVME_SUBMIT_AT_HEAD);
ae5e6886 1115 if (result && ret >= 0)
d49187e9 1116 *result = nvme_req(req)->result;
4160982e
CH		 1117 out:
1118 blk_mq_free_request(req);
1119 return ret;
1120}
eb71f435 1121EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 1122
1123int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1124 void *buffer, unsigned bufflen)
1125{
6b46fa02 1126 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen,
bd2687f2 1127 NVME_QID_ANY, 0);
4160982e 1128}
576d55d6 1129EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 1130
df21b6b1
LG		 1131u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
1132{
1133 u32 effects = 0;
1134
1135 if (ns) {
cc115cbe 1136 effects = le32_to_cpu(ns->head->effects->iocs[opcode]);
df21b6b1 1137 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
ed4a854b 1138 dev_warn_once(ctrl->device,
831ed60c 1139 "IO command:%02x has unusual effects:%08x\n",
ed4a854b 1140 opcode, effects);
df21b6b1 1141
831ed60c
CH		 1142 /*
1143 * NVME_CMD_EFFECTS_CSE_MASK causes a freeze all I/O queues,
1144 * which would deadlock when done on an I/O command. Note that
1145 * We already warn about an unusual effect above.
1146 */
1147 effects &= ~NVME_CMD_EFFECTS_CSE_MASK;
1148 } else {
cc115cbe 1149 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
29f69753
KB		 1150
1151 /* Ignore execution restrictions if any relaxation bits are set */
1152 if (effects & NVME_CMD_EFFECTS_CSER_MASK)
1153 effects &= ~NVME_CMD_EFFECTS_CSE_MASK;
831ed60c 1154 }
df21b6b1
LG		 1155
1156 return effects;
1157}
1158EXPORT_SYMBOL_NS_GPL(nvme_command_effects, NVME_TARGET_PASSTHRU);
1159
62281b9e 1160u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
df21b6b1
LG		 1161{
1162 u32 effects = nvme_command_effects(ctrl, ns, opcode);
1163
1164 /*
1165 * For simplicity, IO to all namespaces is quiesced even if the command
1166 * effects say only one namespace is affected.
1167 */
af0f446d 1168 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG		 1169 mutex_lock(&ctrl->scan_lock);
1170 mutex_lock(&ctrl->subsys->lock);
1171 nvme_mpath_start_freeze(ctrl->subsys);
1172 nvme_mpath_wait_freeze(ctrl->subsys);
1173 nvme_start_freeze(ctrl);
1174 nvme_wait_freeze(ctrl);
1175 }
1176 return effects;
1177}
62281b9e 1178EXPORT_SYMBOL_NS_GPL(nvme_passthru_start, NVME_TARGET_PASSTHRU);
df21b6b1 1179
31a59782 1180void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects,
bc8fb906 1181 struct nvme_command *cmd, int status)
df21b6b1 1182{
af0f446d 1183 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG		 1184 nvme_unfreeze(ctrl);
1185 nvme_mpath_unfreeze(ctrl->subsys);
1186 mutex_unlock(&ctrl->subsys->lock);
df21b6b1
LG		 1187 mutex_unlock(&ctrl->scan_lock);
1188 }
1e37a307 1189 if (effects & NVME_CMD_EFFECTS_CCC) {
d0dd594b
BL		 1190 if (!test_and_set_bit(NVME_CTRL_DIRTY_CAPABILITY,
1191 &ctrl->flags)) {
1192 dev_info(ctrl->device,
1e37a307 1193"controller capabilities changed, reset may be required to take effect.\n");
d0dd594b 1194 }
1e37a307 1195 }
df21b6b1
LG		 1196 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) {
1197 nvme_queue_scan(ctrl);
1198 flush_work(&ctrl->scan_work);
1199 }
31a59782 1200 if (ns)
1201 return;
b58da2d2
TS		 1202
1203 switch (cmd->common.opcode) {
1204 case nvme_admin_set_features:
1205 switch (le32_to_cpu(cmd->common.cdw10) & 0xFF) {
1206 case NVME_FEAT_KATO:
1207 /*
1208 * Keep alive commands interval on the host should be
1209 * updated when KATO is modified by Set Features
1210 * commands.
1211 */
1212 if (!status)
1213 nvme_update_keep_alive(ctrl, cmd);
1214 break;
1215 default:
1216 break;
1217 }
1218 break;
1219 default:
1220 break;
1221 }
df21b6b1 1222}
bc8fb906 1223EXPORT_SYMBOL_NS_GPL(nvme_passthru_end, NVME_TARGET_PASSTHRU);
df21b6b1 1224
a70b81bd
HR		 1225/*
1226 * Recommended frequency for KATO commands per NVMe 1.4 section 7.12.1:
1227 *
1228 * The host should send Keep Alive commands at half of the Keep Alive Timeout
1229 * accounting for transport roundtrip times [..].
1230 */
ea4d453b
US		 1231static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl)
1232{
1233 unsigned long delay = ctrl->kato * HZ / 2;
1234
1235 /*
1236 * When using Traffic Based Keep Alive, we need to run
1237 * nvme_keep_alive_work at twice the normal frequency, as one
1238 * command completion can postpone sending a keep alive command
1239 * by up to twice the delay between runs.
1240 */
1241 if (ctrl->ctratt & NVME_CTRL_ATTR_TBKAS)
1242 delay /= 2;
1243 return delay;
1244}
1245
a70b81bd 1246static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl)
4160982e 1247{
136cfcb8
MD		 1248 unsigned long now = jiffies;
1249 unsigned long delay = nvme_keep_alive_work_period(ctrl);
1250 unsigned long ka_next_check_tm = ctrl->ka_last_check_time + delay;
1251
1252 if (time_after(now, ka_next_check_tm))
1253 delay = 0;
1254 else
1255 delay = ka_next_check_tm - now;
1256
1257 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay);
21d34711
CH		 1258}
1259
de671d61
JA		 1260static enum rq_end_io_ret nvme_keep_alive_end_io(struct request *rq,
1261 blk_status_t status)
038bd4cb
SG		 1262{
1263 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS		 1264 unsigned long flags;
1265 bool startka = false;
c7275ce6
US		 1266 unsigned long rtt = jiffies - (rq->deadline - rq->timeout);
1267 unsigned long delay = nvme_keep_alive_work_period(ctrl);
1268
1269 /*
1270 * Subtract off the keepalive RTT so nvme_keep_alive_work runs
1271 * at the desired frequency.
1272 */
1273 if (rtt <= delay) {
1274 delay -= rtt;
1275 } else {
1276 dev_warn(ctrl->device, "long keepalive RTT (%u ms)\n",
1277 jiffies_to_msecs(rtt));
1278 delay = 0;
1279 }
038bd4cb
SG		 1280
1281 blk_mq_free_request(rq);
1282
2a842aca 1283 if (status) {
038bd4cb 1284 dev_err(ctrl->device,
2a842aca
CH		 1285 "failed nvme_keep_alive_end_io error=%d\n",
1286 status);
de671d61 1287 return RQ_END_IO_NONE;
038bd4cb
SG		 1288 }
1289
774a9636 1290 ctrl->ka_last_check_time = jiffies;
6e3ca03e 1291 ctrl->comp_seen = false;
86880d64
JS		 1292 spin_lock_irqsave(&ctrl->lock, flags);
1293 if (ctrl->state == NVME_CTRL_LIVE ||
1294 ctrl->state == NVME_CTRL_CONNECTING)
1295 startka = true;
1296 spin_unlock_irqrestore(&ctrl->lock, flags);
1297 if (startka)
c7275ce6 1298 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay);
de671d61 1299 return RQ_END_IO_NONE;
038bd4cb
SG		 1300}
1301
038bd4cb
SG		 1302static void nvme_keep_alive_work(struct work_struct *work)
1303{
1304 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
1305 struct nvme_ctrl, ka_work);
6e3ca03e 1306 bool comp_seen = ctrl->comp_seen;
06c3c336 1307 struct request *rq;
6e3ca03e 1308
774a9636
US		 1309 ctrl->ka_last_check_time = jiffies;
1310
6e3ca03e
SG		 1311 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
1312 dev_dbg(ctrl->device,
1313 "reschedule traffic based keep-alive timer\n");
1314 ctrl->comp_seen = false;
a70b81bd 1315 nvme_queue_keep_alive_work(ctrl);
6e3ca03e
SG		 1316 return;
1317 }
038bd4cb 1318
e559398f
CH		 1319 rq = blk_mq_alloc_request(ctrl->admin_q, nvme_req_op(&ctrl->ka_cmd),
1320 BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT);
06c3c336 1321 if (IS_ERR(rq)) {
038bd4cb 1322 /* allocation failure, reset the controller */
985c5a32 1323 dev_err(ctrl->device, "keep-alive failed: %ld\n", PTR_ERR(rq));
39bdc590 1324 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 1325 return;
1326 }
e559398f 1327 nvme_init_request(rq, &ctrl->ka_cmd);
06c3c336
CH		 1328
1329 rq->timeout = ctrl->kato * HZ;
e2e53086 1330 rq->end_io = nvme_keep_alive_end_io;
06c3c336 1331 rq->end_io_data = ctrl;
e2e53086 1332 blk_execute_rq_nowait(rq, false);
038bd4cb
SG		 1333}
1334
00b683db 1335static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 1336{
1337 if (unlikely(ctrl->kato == 0))
1338 return;
1339
a70b81bd 1340 nvme_queue_keep_alive_work(ctrl);
038bd4cb 1341}
038bd4cb
SG		 1342
1343void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
1344{
1345 if (unlikely(ctrl->kato == 0))
1346 return;
1347
1348 cancel_delayed_work_sync(&ctrl->ka_work);
1349}
1350EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
1351
b58da2d2
TS		 1352static void nvme_update_keep_alive(struct nvme_ctrl *ctrl,
1353 struct nvme_command *cmd)
1354{
1355 unsigned int new_kato =
1356 DIV_ROUND_UP(le32_to_cpu(cmd->common.cdw11), 1000);
1357
1358 dev_info(ctrl->device,
1359 "keep alive interval updated from %u ms to %u ms\n",
1360 ctrl->kato * 1000 / 2, new_kato * 1000 / 2);
1361
1362 nvme_stop_keep_alive(ctrl);
1363 ctrl->kato = new_kato;
1364 nvme_start_keep_alive(ctrl);
1365}
1366
b9a5c3d4
CH		 1367/*
1368 * In NVMe 1.0 the CNS field was just a binary controller or namespace
1369 * flag, thus sending any new CNS opcodes has a big chance of not working.
1370 * Qemu unfortunately had that bug after reporting a 1.1 version compliance
1371 * (but not for any later version).
1372 */
1373static bool nvme_ctrl_limited_cns(struct nvme_ctrl *ctrl)
1374{
1375 if (ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)
1376 return ctrl->vs < NVME_VS(1, 2, 0);
1377 return ctrl->vs < NVME_VS(1, 1, 0);
1378}
1379
3f7f25a9 1380static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 1381{
1382 struct nvme_command c = { };
1383 int error;
1384
1385 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1386 c.identify.opcode = nvme_admin_identify;
986994a2 1387 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 1388
1389 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1390 if (!*id)
1391 return -ENOMEM;
1392
1393 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1394 sizeof(struct nvme_id_ctrl));
7e80eb79 1395 if (error) {
21d34711 1396 kfree(*id);
7e80eb79
KB		 1397 *id = NULL;
1398 }
21d34711
CH		 1399 return error;
1400}
1401
ad95a613 1402static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids,
71010c30 1403 struct nvme_ns_id_desc *cur, bool *csi_seen)
ad95a613
CK		 1404{
1405 const char *warn_str = "ctrl returned bogus length:";
1406 void *data = cur;
1407
1408 switch (cur->nidt) {
1409 case NVME_NIDT_EUI64:
1410 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
1411 dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n",
1412 warn_str, cur->nidl);
1413 return -1;
1414 }
00ff400e
CH		 1415 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1416 return NVME_NIDT_EUI64_LEN;
ad95a613
CK		 1417 memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN);
1418 return NVME_NIDT_EUI64_LEN;
1419 case NVME_NIDT_NGUID:
1420 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
1421 dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n",
1422 warn_str, cur->nidl);
1423 return -1;
1424 }
00ff400e
CH		 1425 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1426 return NVME_NIDT_NGUID_LEN;
ad95a613
CK		 1427 memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN);
1428 return NVME_NIDT_NGUID_LEN;
1429 case NVME_NIDT_UUID:
1430 if (cur->nidl != NVME_NIDT_UUID_LEN) {
1431 dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n",
1432 warn_str, cur->nidl);
1433 return -1;
1434 }
00ff400e
CH		 1435 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1436 return NVME_NIDT_UUID_LEN;
ad95a613
CK		 1437 uuid_copy(&ids->uuid, data + sizeof(*cur));
1438 return NVME_NIDT_UUID_LEN;
71010c30
NC		 1439 case NVME_NIDT_CSI:
1440 if (cur->nidl != NVME_NIDT_CSI_LEN) {
1441 dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n",
1442 warn_str, cur->nidl);
1443 return -1;
1444 }
1445 memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN);
1446 *csi_seen = true;
1447 return NVME_NIDT_CSI_LEN;
ad95a613
CK		 1448 default:
1449 /* Skip unknown types */
1450 return cur->nidl;
1451 }
1452}
1453
1a893c2b
CH		 1454static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl,
1455 struct nvme_ns_info *info)
3b22ba26
JT		 1456{
1457 struct nvme_command c = { };
71010c30
NC		 1458 bool csi_seen = false;
1459 int status, pos, len;
3b22ba26 1460 void *data;
3b22ba26 1461
8b7c0ff2
CH		 1462 if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl))
1463 return 0;
5bedd3af
CH		 1464 if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST)
1465 return 0;
1466
3b22ba26 1467 c.identify.opcode = nvme_admin_identify;
1a893c2b 1468 c.identify.nsid = cpu_to_le32(info->nsid);
3b22ba26
JT		 1469 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1470
1471 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1472 if (!data)
1473 return -ENOMEM;
1474
cdbff4f2 1475 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26 1476 NVME_IDENTIFY_DATA_SIZE);
fb314eb0
CH		 1477 if (status) {
1478 dev_warn(ctrl->device,
aa9d7295 1479 "Identify Descriptors failed (nsid=%u, status=0x%x)\n",
1a893c2b 1480 info->nsid, status);
3b22ba26 1481 goto free_data;
fb314eb0 1482 }
3b22ba26
JT		 1483
1484 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1485 struct nvme_ns_id_desc *cur = data + pos;
1486
1487 if (cur->nidl == 0)
1488 break;
1489
1a893c2b 1490 len = nvme_process_ns_desc(ctrl, &info->ids, cur, &csi_seen);
ad95a613 1491 if (len < 0)
71010c30 1492 break;
3b22ba26
JT		 1493
1494 len += sizeof(*cur);
1495 }
71010c30
NC		 1496
1497 if (nvme_multi_css(ctrl) && !csi_seen) {
1498 dev_warn(ctrl->device, "Command set not reported for nsid:%d\n",
1a893c2b 1499 info->nsid);
71010c30
NC		 1500 status = -EINVAL;
1501 }
1502
3b22ba26
JT		 1503free_data:
1504 kfree(data);
1505 return status;
1506}
1507
a1a825ab 1508int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid,
1a893c2b 1509 struct nvme_id_ns **id)
21d34711
CH		 1510{
1511 struct nvme_command c = { };
1512 int error;
1513
1514 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 1515 c.identify.opcode = nvme_admin_identify;
1516 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1517 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1518
331813f6
SG		 1519 *id = kmalloc(sizeof(**id), GFP_KERNEL);
1520 if (!*id)
1521 return -ENOMEM;
21d34711 1522
331813f6 1523 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id));
cdbff4f2 1524 if (error) {
d0de579c 1525 dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error);
0dd6fff2 1526 kfree(*id);
7e80eb79 1527 *id = NULL;
cdbff4f2 1528 }
1a893c2b
CH		 1529 return error;
1530}
00ff400e 1531
1a893c2b
CH		 1532static int nvme_ns_info_from_identify(struct nvme_ctrl *ctrl,
1533 struct nvme_ns_info *info)
1534{
1535 struct nvme_ns_ids *ids = &info->ids;
1536 struct nvme_id_ns *id;
1537 int ret;
1538
1539 ret = nvme_identify_ns(ctrl, info->nsid, &id);
1540 if (ret)
1541 return ret;
0dd6fff2
CH		 1542
1543 if (id->ncap == 0) {
1544 /* namespace not allocated or attached */
1545 info->is_removed = true;
e3139cef
ML		 1546 ret = -ENODEV;
1547 goto error;
0dd6fff2
CH		 1548 }
1549
1a893c2b
CH		 1550 info->anagrpid = id->anagrpid;
1551 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED;
1e4ea66a 1552 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO;
1a893c2b 1553 info->is_ready = true;
00ff400e
CH		 1554 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) {
1555 dev_info(ctrl->device,
1556 "Ignoring bogus Namespace Identifiers\n");
1557 } else {
1558 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
1559 !memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
1a893c2b 1560 memcpy(ids->eui64, id->eui64, sizeof(ids->eui64));
00ff400e
CH		 1561 if (ctrl->vs >= NVME_VS(1, 2, 0) &&
1562 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
1a893c2b 1563 memcpy(ids->nguid, id->nguid, sizeof(ids->nguid));
00ff400e 1564 }
e3139cef
ML		 1565
1566error:
1a893c2b 1567 kfree(id);
e3139cef 1568 return ret;
21d34711
CH		 1569}
1570
1a893c2b
CH		 1571static int nvme_ns_info_from_id_cs_indep(struct nvme_ctrl *ctrl,
1572 struct nvme_ns_info *info)
354201c5 1573{
1a893c2b 1574 struct nvme_id_ns_cs_indep *id;
354201c5
CH		 1575 struct nvme_command c = {
1576 .identify.opcode = nvme_admin_identify,
1a893c2b 1577 .identify.nsid = cpu_to_le32(info->nsid),
354201c5
CH		 1578 .identify.cns = NVME_ID_CNS_NS_CS_INDEP,
1579 };
1580 int ret;
1581
1a893c2b
CH		 1582 id = kmalloc(sizeof(*id), GFP_KERNEL);
1583 if (!id)
354201c5
CH		 1584 return -ENOMEM;
1585
1a893c2b
CH		 1586 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
1587 if (!ret) {
1588 info->anagrpid = id->anagrpid;
1589 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED;
1e4ea66a 1590 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO;
1a893c2b 1591 info->is_ready = id->nstat & NVME_NSTAT_NRDY;
354201c5 1592 }
1a893c2b
CH		 1593 kfree(id);
1594 return ret;
354201c5
CH		 1595}
1596
1a87ee65
KB		 1597static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
1598 unsigned int dword11, void *buffer, size_t buflen, u32 *result)
21d34711 1599{
15755854 1600 union nvme_result res = { 0 };
cc72c442 1601 struct nvme_command c = { };
1cb3cce5 1602 int ret;
21d34711 1603
1a87ee65 1604 c.features.opcode = op;
21d34711
CH		 1605 c.features.fid = cpu_to_le32(fid);
1606 c.features.dword11 = cpu_to_le32(dword11);
1607
d49187e9 1608 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
bd2687f2 1609 buffer, buflen, NVME_QID_ANY, 0);
9b47f77a 1610 if (ret >= 0 && result)
d49187e9 1611 *result = le32_to_cpu(res.u32);
1cb3cce5 1612 return ret;
21d34711
CH		 1613}
1614
1a87ee65
KB		 1615int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
1616 unsigned int dword11, void *buffer, size_t buflen,
1617 u32 *result)
1618{
1619 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer,
1620 buflen, result);
1621}
1622EXPORT_SYMBOL_GPL(nvme_set_features);
1623
1624int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
1625 unsigned int dword11, void *buffer, size_t buflen,
1626 u32 *result)
1627{
1628 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer,
1629 buflen, result);
1630}
1631EXPORT_SYMBOL_GPL(nvme_get_features);
1632
9a0be7ab
CH		 1633int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1634{
1635 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1636 u32 result;
1637 int status, nr_io_queues;
1638
1a6fe74d 1639 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1640 &result);
f5fa90dc 1641 if (status < 0)
9a0be7ab
CH		 1642 return status;
1643
f5fa90dc
CH		 1644 /*
1645 * Degraded controllers might return an error when setting the queue
1646 * count. We still want to be able to bring them online and offer
1647 * access to the admin queue, as that might be only way to fix them up.
1648 */
1649 if (status > 0) {
f0425db0 1650 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1651 *count = 0;
1652 } else {
1653 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1654 *count = min(*count, nr_io_queues);
1655 }
1656
9a0be7ab
CH		 1657 return 0;
1658}
576d55d6 1659EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1660
c0561f82 1661#define NVME_AEN_SUPPORTED \
85f8a435
SG		 1662 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \
1663 NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE)
c0561f82
HR		 1664
1665static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1666{
fa441b71 1667 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR		 1668 int status;
1669
fa441b71
WZ		 1670 if (!supported_aens)
1671 return;
1672
1673 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1674 NULL, 0, &result);
c0561f82
HR		 1675 if (status)
1676 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1677 supported_aens);
93da4023
SG		 1678
1679 queue_work(nvme_wq, &ctrl->async_event_work);
c0561f82
HR		 1680}
1681
f5b9a51d 1682static int nvme_ns_open(struct nvme_ns *ns)
c225b610 1683{
c225b610 1684
32acab31 1685 /* should never be called due to GENHD_FL_HIDDEN */
30897388 1686 if (WARN_ON_ONCE(nvme_ns_head_multipath(ns->head)))
85088c4a 1687 goto fail;
4c74d1f8 1688 if (!nvme_get_ns(ns))
85088c4a
NC		 1689 goto fail;
1690 if (!try_module_get(ns->ctrl->ops->module))
1691 goto fail_put_ns;
1692
c6424a90 1693 return 0;
85088c4a
NC		 1694
1695fail_put_ns:
1696 nvme_put_ns(ns);
1697fail:
1698 return -ENXIO;
1673f1f0
CH		 1699}
1700
f5b9a51d 1701static void nvme_ns_release(struct nvme_ns *ns)
1673f1f0 1702{
85088c4a
NC		 1703
1704 module_put(ns->ctrl->ops->module);
1705 nvme_put_ns(ns);
1673f1f0
CH		 1706}
1707
05bdb996 1708static int nvme_open(struct gendisk *disk, blk_mode_t mode)
f5b9a51d 1709{
d32e2bf8 1710 return nvme_ns_open(disk->private_data);
f5b9a51d
CH		 1711}
1712
ae220766 1713static void nvme_release(struct gendisk *disk)
f5b9a51d
CH		 1714{
1715 nvme_ns_release(disk->private_data);
1716}
1717
1496bd49 1718int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1673f1f0
CH		 1719{
1720 /* some standard values */
1721 geo->heads = 1 << 6;
1722 geo->sectors = 1 << 5;
1723 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1724 return 0;
1725}
1726
f467b48e 1727static bool nvme_init_integrity(struct gendisk *disk, struct nvme_ns_head *head)
1673f1f0 1728{
cc72c442 1729 struct blk_integrity integrity = { };
1673f1f0 1730
414c62e2
CH		 1731 blk_integrity_unregister(disk);
1732
f467b48e
CH		 1733 if (!head->ms)
1734 return true;
1735
1736 /*
1737 * PI can always be supported as we can ask the controller to simply
1738 * insert/strip it, which is not possible for other kinds of metadata.
1739 */
1740 if (!IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) ||
1741 !(head->features & NVME_NS_METADATA_SUPPORTED))
1742 return nvme_ns_has_pi(head);
1743
d386aedc 1744 switch (head->pi_type) {
1673f1f0 1745 case NVME_NS_DPS_PI_TYPE3:
d386aedc 1746 switch (head->guard_type) {
4020aad8
KB		 1747 case NVME_NVM_NS_16B_GUARD:
1748 integrity.profile = &t10_pi_type3_crc;
1749 integrity.tag_size = sizeof(u16) + sizeof(u32);
1750 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1751 break;
1752 case NVME_NVM_NS_64B_GUARD:
1753 integrity.profile = &ext_pi_type3_crc64;
1754 integrity.tag_size = sizeof(u16) + 6;
1755 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1756 break;
1757 default:
1758 integrity.profile = NULL;
1759 break;
1760 }
1673f1f0
CH		 1761 break;
1762 case NVME_NS_DPS_PI_TYPE1:
1763 case NVME_NS_DPS_PI_TYPE2:
d386aedc 1764 switch (head->guard_type) {
4020aad8
KB		 1765 case NVME_NVM_NS_16B_GUARD:
1766 integrity.profile = &t10_pi_type1_crc;
1767 integrity.tag_size = sizeof(u16);
1768 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1769 break;
1770 case NVME_NVM_NS_64B_GUARD:
1771 integrity.profile = &ext_pi_type1_crc64;
1772 integrity.tag_size = sizeof(u16);
1773 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1774 break;
1775 default:
1776 integrity.profile = NULL;
1777 break;
1778 }
1673f1f0
CH		 1779 break;
1780 default:
1781 integrity.profile = NULL;
1782 break;
1783 }
4020aad8 1784
d386aedc 1785 integrity.tuple_size = head->ms;
921e81db 1786 integrity.pi_offset = head->pi_offset;
39b7baa4 1787 blk_integrity_register(disk, &integrity);
f467b48e 1788 return true;
1673f1f0 1789}
1673f1f0 1790
e6c9b130 1791static void nvme_config_discard(struct nvme_ns *ns, struct queue_limits *lim)
1673f1f0 1792{
e6c9b130 1793 struct nvme_ctrl *ctrl = ns->ctrl;
3831761e 1794
e6c9b130
CH		 1795 if (ctrl->dmrsl && ctrl->dmrsl <= nvme_sect_to_lba(ns->head, UINT_MAX))
1796 lim->max_hw_discard_sectors =
1797 nvme_lba_to_sect(ns->head, ctrl->dmrsl);
1798 else if (ctrl->oncs & NVME_CTRL_ONCS_DSM)
1799 lim->max_hw_discard_sectors = UINT_MAX;
1800 else
1801 lim->max_hw_discard_sectors = 0;
1802
1803 lim->discard_granularity = lim->logical_block_size;
3831761e 1804
3b946fe1 1805 if (ctrl->dmrl)
e6c9b130 1806 lim->max_discard_segments = ctrl->dmrl;
3b946fe1 1807 else
e6c9b130 1808 lim->max_discard_segments = NVME_DSM_MAX_RANGES;
1673f1f0
CH		 1809}
1810
002fab04
CH		 1811static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1812{
1813 return uuid_equal(&a->uuid, &b->uuid) &&
1814 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
71010c30
NC		 1815 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 &&
1816 a->csi == b->csi;
002fab04
CH		 1817}
1818
c6fce9f1
CH		 1819static int nvme_identify_ns_nvm(struct nvme_ctrl *ctrl, unsigned int nsid,
1820 struct nvme_id_ns_nvm **nvmp)
d4609ea8 1821{
c6fce9f1
CH		 1822 struct nvme_command c = {
1823 .identify.opcode = nvme_admin_identify,
1824 .identify.nsid = cpu_to_le32(nsid),
1825 .identify.cns = NVME_ID_CNS_CS_NS,
1826 .identify.csi = NVME_CSI_NVM,
1827 };
4020aad8 1828 struct nvme_id_ns_nvm *nvm;
c6fce9f1 1829 int ret;
d4609ea8 1830
4020aad8
KB		 1831 nvm = kzalloc(sizeof(*nvm), GFP_KERNEL);
1832 if (!nvm)
1833 return -ENOMEM;
d4609ea8 1834
d386aedc 1835 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, nvm, sizeof(*nvm));
4020aad8 1836 if (ret)
c6fce9f1
CH		 1837 kfree(nvm);
1838 else
1839 *nvmp = nvm;
1840 return ret;
1841}
4020aad8 1842
27cb91a3 1843static void nvme_configure_pi_elbas(struct nvme_ns_head *head,
e5ea00a5 1844 struct nvme_id_ns *id, struct nvme_id_ns_nvm *nvm)
d4609ea8 1845{
27cb91a3 1846 u32 elbaf = le32_to_cpu(nvm->elbaf[nvme_lbaf_index(id->flbas)]);
4020aad8
KB		 1847
1848 /* no support for storage tag formats right now */
1849 if (nvme_elbaf_sts(elbaf))
27cb91a3 1850 return;
4020aad8 1851
d386aedc
DW		 1852 head->guard_type = nvme_elbaf_guard_type(elbaf);
1853 switch (head->guard_type) {
4020aad8 1854 case NVME_NVM_NS_64B_GUARD:
d386aedc 1855 head->pi_size = sizeof(struct crc64_pi_tuple);
4020aad8
KB		 1856 break;
1857 case NVME_NVM_NS_16B_GUARD:
d386aedc 1858 head->pi_size = sizeof(struct t10_pi_tuple);
4020aad8
KB		 1859 break;
1860 default:
1861 break;
1862 }
4020aad8
KB		 1863}
1864
e5ea00a5
CH		 1865static void nvme_configure_metadata(struct nvme_ctrl *ctrl,
1866 struct nvme_ns_head *head, struct nvme_id_ns *id,
1867 struct nvme_id_ns_nvm *nvm)
4020aad8 1868{
d386aedc 1869 head->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS);
27cb91a3
CH		 1870 head->pi_type = 0;
1871 head->pi_size = 0;
1872 head->pi_offset = 0;
1873 head->ms = le16_to_cpu(id->lbaf[nvme_lbaf_index(id->flbas)].ms);
d386aedc 1874 if (!head->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
e5ea00a5 1875 return;
363f6368 1876
27cb91a3
CH		 1877 if (nvm && (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)) {
1878 nvme_configure_pi_elbas(head, id, nvm);
1879 } else {
1880 head->pi_size = sizeof(struct t10_pi_tuple);
1881 head->guard_type = NVME_NVM_NS_16B_GUARD;
1882 }
1883
1884 if (head->pi_size && head->ms >= head->pi_size)
1885 head->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1886 if (!(id->dps & NVME_NS_DPS_PI_FIRST))
1887 head->pi_offset = head->ms - head->pi_size;
363f6368 1888
d4609ea8
CH		 1889 if (ctrl->ops->flags & NVME_F_FABRICS) {
1890 /*
1891 * The NVMe over Fabrics specification only supports metadata as
1892 * part of the extended data LBA. We rely on HCA/HBA support to
1893 * remap the separate metadata buffer from the block layer.
1894 */
1895 if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT)))
e5ea00a5 1896 return;
d39ad2a4 1897
d386aedc 1898 head->features |= NVME_NS_EXT_LBAS;
d39ad2a4
KB		 1899
1900 /*
1901 * The current fabrics transport drivers support namespace
1902 * metadata formats only if nvme_ns_has_pi() returns true.
1903 * Suppress support for all other formats so the namespace will
1904 * have a 0 capacity and not be usable through the block stack.
1905 *
1906 * Note, this check will need to be modified if any drivers
1907 * gain the ability to use other metadata formats.
1908 */
d386aedc
DW		 1909 if (ctrl->max_integrity_segments && nvme_ns_has_pi(head))
1910 head->features |= NVME_NS_METADATA_SUPPORTED;
d4609ea8
CH		 1911 } else {
1912 /*
1913 * For PCIe controllers, we can't easily remap the separate
1914 * metadata buffer from the block layer and thus require a
1915 * separate metadata buffer for block layer metadata/PI support.
1916 * We allow extended LBAs for the passthrough interface, though.
1917 */
1918 if (id->flbas & NVME_NS_FLBAS_META_EXT)
d386aedc 1919 head->features |= NVME_NS_EXT_LBAS;
d4609ea8 1920 else
d386aedc 1921 head->features |= NVME_NS_METADATA_SUPPORTED;
d4609ea8 1922 }
d4609ea8
CH		 1923}
1924
152694c8 1925static u32 nvme_max_drv_segments(struct nvme_ctrl *ctrl)
658d9f7c 1926{
152694c8
CH		 1927 return ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> SECTOR_SHIFT) + 1;
1928}
658d9f7c 1929
e6c9b130
CH		 1930static void nvme_set_ctrl_limits(struct nvme_ctrl *ctrl,
1931 struct queue_limits *lim)
658d9f7c 1932{
e6c9b130
CH		 1933 lim->max_hw_sectors = ctrl->max_hw_sectors;
1934 lim->max_segments = min_t(u32, USHRT_MAX,
1935 min_not_zero(nvme_max_drv_segments(ctrl), ctrl->max_segments));
1936 lim->max_integrity_segments = ctrl->max_integrity_segments;
1937 lim->virt_boundary_mask = NVME_CTRL_PAGE_SIZE - 1;
1938 lim->max_segment_size = UINT_MAX;
1939 lim->dma_alignment = 3;
658d9f7c
CH		 1940}
1941
e6c9b130
CH		 1942static bool nvme_update_disk_info(struct nvme_ns *ns, struct nvme_id_ns *id,
1943 struct queue_limits *lim)
24b0b58c 1944{
a5b1cd61 1945 struct nvme_ns_head *head = ns->head;
d386aedc 1946 u32 bs = 1U << head->lba_shift;
68ab60ca 1947 u32 atomic_bs, phys_bs, io_opt = 0;
a5b1cd61 1948 bool valid = true;
24b0b58c 1949
13f0b26b
CH		 1950 /*
1951 * The block layer can't support LBA sizes larger than the page size
74fbc88e
KB		 1952 * or smaller than a sector size yet, so catch this early and don't
1953 * allow block I/O.
13f0b26b 1954 */
01d550f0 1955 if (head->lba_shift > PAGE_SHIFT || head->lba_shift < SECTOR_SHIFT) {
01fa0174 1956 bs = (1 << 9);
a5b1cd61 1957 valid = false;
01fa0174 1958 }
f9d5f457 1959
68ab60ca 1960 atomic_bs = phys_bs = bs;
81adb863
BVA		 1961 if (id->nabo == 0) {
1962 /*
1963 * Bit 1 indicates whether NAWUPF is defined for this namespace
1964 * and whether it should be used instead of AWUPF. If NAWUPF ==
1965 * 0 then AWUPF must be used instead.
1966 */
92decf11 1967 if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf)
81adb863
BVA		 1968 atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs;
1969 else
a5b1cd61 1970 atomic_bs = (1 + ns->ctrl->subsys->awupf) * bs;
81adb863 1971 }
31fdad7b 1972
92decf11 1973 if (id->nsfeat & NVME_NS_FEAT_IO_OPT) {
81adb863 1974 /* NPWG = Namespace Preferred Write Granularity */
31fdad7b 1975 phys_bs = bs * (1 + le16_to_cpu(id->npwg));
81adb863 1976 /* NOWS = Namespace Optimal Write Size */
31fdad7b 1977 io_opt = bs * (1 + le16_to_cpu(id->nows));
81adb863
BVA		 1978 }
1979
81adb863
BVA		 1980 /*
1981 * Linux filesystems assume writing a single physical block is
1982 * an atomic operation. Hence limit the physical block size to the
1983 * value of the Atomic Write Unit Power Fail parameter.
1984 */
e6c9b130
CH		 1985 lim->logical_block_size = bs;
1986 lim->physical_block_size = min(phys_bs, atomic_bs);
1987 lim->io_min = phys_bs;
1988 lim->io_opt = io_opt;
a5b1cd61 1989 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
e6c9b130 1990 lim->max_write_zeroes_sectors = UINT_MAX;
63dfa100 1991 else
e6c9b130 1992 lim->max_write_zeroes_sectors = ns->ctrl->max_zeroes_sectors;
a5b1cd61 1993 return valid;
24b0b58c
CH		 1994}
1995
1e4ea66a
CH		 1996static bool nvme_ns_is_readonly(struct nvme_ns *ns, struct nvme_ns_info *info)
1997{
1998 return info->is_readonly || test_bit(NVME_NS_FORCE_RO, &ns->flags);
1999}
2000
e83d776f
KB		 2001static inline bool nvme_first_scan(struct gendisk *disk)
2002{
2003 /* nvme_alloc_ns() scans the disk prior to adding it */
50b4aecf 2004 return !disk_live(disk);
e83d776f
KB		 2005}
2006
e6c9b130
CH		 2007static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id,
2008 struct queue_limits *lim)
e83d776f
KB		 2009{
2010 struct nvme_ctrl *ctrl = ns->ctrl;
2011 u32 iob;
2012
2013 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
2014 is_power_of_2(ctrl->max_hw_sectors))
2015 iob = ctrl->max_hw_sectors;
2016 else
0372dd4e 2017 iob = nvme_lba_to_sect(ns->head, le16_to_cpu(id->noiob));
e83d776f
KB		 2018
2019 if (!iob)
2020 return;
2021
2022 if (!is_power_of_2(iob)) {
2023 if (nvme_first_scan(ns->disk))
2024 pr_warn("%s: ignoring unaligned IO boundary:%u\n",
2025 ns->disk->disk_name, iob);
2026 return;
2027 }
2028
2029 if (blk_queue_is_zoned(ns->disk->queue)) {
2030 if (nvme_first_scan(ns->disk))
2031 pr_warn("%s: ignoring zoned namespace IO boundary\n",
2032 ns->disk->disk_name);
2033 return;
2034 }
2035
e6c9b130 2036 lim->chunk_sectors = iob;
e83d776f
KB		 2037}
2038
eb867ee9
JG		 2039static int nvme_update_ns_info_generic(struct nvme_ns *ns,
2040 struct nvme_ns_info *info)
2041{
e6c9b130
CH		 2042 struct queue_limits lim;
2043 int ret;
2044
eb867ee9 2045 blk_mq_freeze_queue(ns->disk->queue);
e6c9b130
CH		 2046 lim = queue_limits_start_update(ns->disk->queue);
2047 nvme_set_ctrl_limits(ns->ctrl, &lim);
2048 ret = queue_limits_commit_update(ns->disk->queue, &lim);
eb867ee9
JG		 2049 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info));
2050 blk_mq_unfreeze_queue(ns->disk->queue);
2051
eb867ee9 2052 /* Hide the block-interface for these devices */
e6c9b130
CH		 2053 if (!ret)
2054 ret = -ENODEV;
2055 return ret;
eb867ee9
JG		 2056}
2057
1a893c2b
CH		 2058static int nvme_update_ns_info_block(struct nvme_ns *ns,
2059 struct nvme_ns_info *info)
ac81bfa9 2060{
d60c23e4 2061 bool vwc = ns->ctrl->vwc & NVME_CTRL_VWC_PRESENT;
e6c9b130 2062 struct queue_limits lim;
e5ea00a5 2063 struct nvme_id_ns_nvm *nvm = NULL;
c85c9ab9 2064 struct nvme_zone_info zi = {};
1a893c2b 2065 struct nvme_id_ns *id;
a5b1cd61 2066 sector_t capacity;
1a893c2b 2067 unsigned lbaf;
240e6ee2 2068 int ret;
1673f1f0 2069
1a893c2b
CH		 2070 ret = nvme_identify_ns(ns->ctrl, info->nsid, &id);
2071 if (ret)
2072 return ret;
2073
d8b90d60
EM		 2074 if (id->ncap == 0) {
2075 /* namespace not allocated or attached */
2076 info->is_removed = true;
0551ec93 2077 ret = -ENXIO;
46e7422c 2078 goto out;
d8b90d60 2079 }
c85c9ab9 2080 lbaf = nvme_lbaf_index(id->flbas);
d8b90d60 2081
e5ea00a5
CH		 2082 if (ns->ctrl->ctratt & NVME_CTRL_ATTR_ELBAS) {
2083 ret = nvme_identify_ns_nvm(ns->ctrl, info->nsid, &nvm);
2084 if (ret < 0)
2085 goto out;
d8b90d60
EM		 2086 }
2087
c85c9ab9
CH		 2088 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
2089 ns->head->ids.csi == NVME_CSI_ZNS) {
2090 ret = nvme_query_zone_info(ns, lbaf, &zi);
2091 if (ret < 0)
2092 goto out;
2093 }
2094
f9d5f457 2095 blk_mq_freeze_queue(ns->disk->queue);
9419e71b 2096 ns->head->lba_shift = id->lbaf[lbaf].ds;
a1a825ab 2097 ns->head->nuse = le64_to_cpu(id->nuse);
a5b1cd61 2098 capacity = nvme_lba_to_sect(ns->head, le64_to_cpu(id->nsze));
73d90386 2099
e6c9b130
CH		 2100 lim = queue_limits_start_update(ns->disk->queue);
2101 nvme_set_ctrl_limits(ns->ctrl, &lim);
e5ea00a5 2102 nvme_configure_metadata(ns->ctrl, ns->head, id, nvm);
e6c9b130
CH		 2103 nvme_set_chunk_sectors(ns, id, &lim);
2104 if (!nvme_update_disk_info(ns, id, &lim))
a5b1cd61 2105 capacity = 0;
e6c9b130
CH		 2106 nvme_config_discard(ns, &lim);
2107 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
c85c9ab9
CH		 2108 ns->head->ids.csi == NVME_CSI_ZNS)
2109 nvme_update_zone_info(ns, &lim, &zi);
e6c9b130
CH		 2110 ret = queue_limits_commit_update(ns->disk->queue, &lim);
2111 if (ret) {
2112 blk_mq_unfreeze_queue(ns->disk->queue);
2113 goto out;
2114 }
a5b1cd61
CH		 2115
2116 /*
2117 * Register a metadata profile for PI, or the plain non-integrity NVMe
2118 * metadata masquerading as Type 0 if supported, otherwise reject block
2119 * I/O to namespaces with metadata except when the namespace supports
2120 * PI, as it can strip/insert in that case.
2121 */
2122 if (!nvme_init_integrity(ns->disk, ns->head))
2123 capacity = 0;
2124
2125 set_capacity_and_notify(ns->disk, capacity);
71010c30 2126
1b96f862
CH		 2127 /*
2128 * Only set the DEAC bit if the device guarantees that reads from
2129 * deallocated data return zeroes. While the DEAC bit does not
2130 * require that, it must be a no-op if reads from deallocated data
2131 * do not return zeroes.
2132 */
2133 if ((id->dlfeat & 0x7) == 0x1 && (id->dlfeat & (1 << 3)))
9419e71b 2134 ns->head->features |= NVME_NS_DEAC;
1e4ea66a 2135 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info));
d60c23e4 2136 blk_queue_write_cache(ns->disk->queue, vwc, vwc);
e7d65803 2137 set_bit(NVME_NS_READY, &ns->flags);
f9d5f457 2138 blk_mq_unfreeze_queue(ns->disk->queue);
1673f1f0 2139
3a9967ba 2140 if (blk_queue_is_zoned(ns->queue)) {
9b3c08b9 2141 ret = blk_revalidate_disk_zones(ns->disk);
8685699c 2142 if (ret && !nvme_first_scan(ns->disk))
e06b425b 2143 goto out;
b29f8485
MG		 2144 }
2145
e06b425b
CH		 2146 ret = 0;
2147out:
e5ea00a5 2148 kfree(nvm);
1a893c2b 2149 kfree(id);
240e6ee2
KB		 2150 return ret;
2151}
2152
1a893c2b
CH		 2153static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_ns_info *info)
2154{
46e7422c
CH		 2155 bool unsupported = false;
2156 int ret;
2157
1a893c2b
CH		 2158 switch (info->ids.csi) {
2159 case NVME_CSI_ZNS:
2160 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
eb867ee9
JG		 2161 dev_info(ns->ctrl->device,
2162 "block device for nsid %u not supported without CONFIG_BLK_DEV_ZONED\n",
1a893c2b 2163 info->nsid);
46e7422c
CH		 2164 ret = nvme_update_ns_info_generic(ns, info);
2165 break;
1a893c2b 2166 }
46e7422c
CH		 2167 ret = nvme_update_ns_info_block(ns, info);
2168 break;
1a893c2b 2169 case NVME_CSI_NVM:
46e7422c
CH		 2170 ret = nvme_update_ns_info_block(ns, info);
2171 break;
1a893c2b 2172 default:
eb867ee9
JG		 2173 dev_info(ns->ctrl->device,
2174 "block device for nsid %u not supported (csi %u)\n",
2175 info->nsid, info->ids.csi);
46e7422c
CH		 2176 ret = nvme_update_ns_info_generic(ns, info);
2177 break;
2178 }
2179
2180 /*
2181 * If probing fails due an unsupported feature, hide the block device,
2182 * but still allow other access.
2183 */
2184 if (ret == -ENODEV) {
2185 ns->disk->flags |= GENHD_FL_HIDDEN;
2186 set_bit(NVME_NS_READY, &ns->flags);
2187 unsupported = true;
2188 ret = 0;
1a893c2b 2189 }
46e7422c
CH		 2190
2191 if (!ret && nvme_ns_head_multipath(ns->head)) {
ac229a2d 2192 struct queue_limits *ns_lim = &ns->disk->queue->limits;
f7e0a545
CH		 2193 struct queue_limits lim;
2194
46e7422c
CH		 2195 blk_mq_freeze_queue(ns->head->disk->queue);
2196 if (unsupported)
2197 ns->head->disk->flags |= GENHD_FL_HIDDEN;
2198 else
2199 nvme_init_integrity(ns->head->disk, ns->head);
2200 set_capacity_and_notify(ns->head->disk, get_capacity(ns->disk));
2201 set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info));
2202 nvme_mpath_revalidate_paths(ns);
46e7422c 2203
ac229a2d
CH		 2204 /*
2205 * queue_limits mixes values that are the hardware limitations
2206 * for bio splitting with what is the device configuration.
2207 *
2208 * For NVMe the device configuration can change after e.g. a
2209 * Format command, and we really want to pick up the new format
2210 * value here. But we must still stack the queue limits to the
2211 * least common denominator for multipathing to split the bios
2212 * properly.
2213 *
2214 * To work around this, we explicitly set the device
2215 * configuration to those that we just queried, but only stack
2216 * the splitting limits in to make sure we still obey possibly
2217 * lower limitations of other controllers.
2218 */
f7e0a545 2219 lim = queue_limits_start_update(ns->head->disk->queue);
ac229a2d
CH		 2220 lim.logical_block_size = ns_lim->logical_block_size;
2221 lim.physical_block_size = ns_lim->physical_block_size;
2222 lim.io_min = ns_lim->io_min;
2223 lim.io_opt = ns_lim->io_opt;
f7e0a545
CH		 2224 queue_limits_stack_bdev(&lim, ns->disk->part0, 0,
2225 ns->head->disk->disk_name);
2226 ret = queue_limits_commit_update(ns->head->disk->queue, &lim);
46e7422c 2227 blk_mq_unfreeze_queue(ns->head->disk->queue);
1a893c2b 2228 }
46e7422c
CH		 2229
2230 return ret;
1a893c2b
CH		 2231}
2232
a98e58e5 2233#ifdef CONFIG_BLK_SED_OPAL
94cc781f 2234static int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
4f1244c8 2235 bool send)
a98e58e5 2236{
4f1244c8 2237 struct nvme_ctrl *ctrl = data;
cc72c442 2238 struct nvme_command cmd = { };
a98e58e5 2239
a98e58e5
SB		 2240 if (send)
2241 cmd.common.opcode = nvme_admin_security_send;
2242 else
2243 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 2244 cmd.common.nsid = 0;
b7c8f366
CK		 2245 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
2246 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5 2247
6b46fa02 2248 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
bd2687f2 2249 NVME_QID_ANY, NVME_SUBMIT_AT_HEAD);
a98e58e5 2250}
94cc781f
CH		 2251
2252static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended)
2253{
2254 if (ctrl->oacs & NVME_CTRL_OACS_SEC_SUPP) {
2255 if (!ctrl->opal_dev)
2256 ctrl->opal_dev = init_opal_dev(ctrl, &nvme_sec_submit);
2257 else if (was_suspended)
2258 opal_unlock_from_suspend(ctrl->opal_dev);
2259 } else {
2260 free_opal_dev(ctrl->opal_dev);
2261 ctrl->opal_dev = NULL;
2262 }
2263}
2264#else
2265static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended)
2266{
2267}
a98e58e5
SB		 2268#endif /* CONFIG_BLK_SED_OPAL */
2269
8b4fb0f9
CH		 2270#ifdef CONFIG_BLK_DEV_ZONED
2271static int nvme_report_zones(struct gendisk *disk, sector_t sector,
2272 unsigned int nr_zones, report_zones_cb cb, void *data)
2273{
2274 return nvme_ns_report_zones(disk->private_data, sector, nr_zones, cb,
2275 data);
2276}
2277#else
2278#define nvme_report_zones NULL
2279#endif /* CONFIG_BLK_DEV_ZONED */
2280
942e21c0 2281const struct block_device_operations nvme_bdev_ops = {
1673f1f0
CH		 2282 .owner = THIS_MODULE,
2283 .ioctl = nvme_ioctl,
a25d4261 2284 .compat_ioctl = blkdev_compat_ptr_ioctl,
1673f1f0
CH		 2285 .open = nvme_open,
2286 .release = nvme_release,
2287 .getgeo = nvme_getgeo,
240e6ee2 2288 .report_zones = nvme_report_zones,
1673f1f0
CH		 2289 .pr_ops = &nvme_pr_ops,
2290};
2291
e6d275de
CH		 2292static int nvme_wait_ready(struct nvme_ctrl *ctrl, u32 mask, u32 val,
2293 u32 timeout, const char *op)
5fd4ce1b 2294{
e6d275de
CH		 2295 unsigned long timeout_jiffies = jiffies + timeout * HZ;
2296 u32 csts;
5fd4ce1b
CH		 2297 int ret;
2298
2299 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 2300 if (csts == ~0)
2301 return -ENODEV;
e6d275de 2302 if ((csts & mask) == val)
5fd4ce1b
CH		 2303 break;
2304
3e98c244 2305 usleep_range(1000, 2000);
5fd4ce1b
CH		 2306 if (fatal_signal_pending(current))
2307 return -EINTR;
354201c5 2308 if (time_after(jiffies, timeout_jiffies)) {
1b3c47c1 2309 dev_err(ctrl->device,
94d2e705 2310 "Device not ready; aborting %s, CSTS=0x%x\n",
e6d275de 2311 op, csts);
5fd4ce1b
CH		 2312 return -ENODEV;
2313 }
2314 }
2315
2316 return ret;
2317}
2318
285b6e9b 2319int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown)
5fd4ce1b
CH		 2320{
2321 int ret;
2322
2323 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
285b6e9b
CH		 2324 if (shutdown)
2325 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
2326 else
2327 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
5fd4ce1b
CH		 2328
2329 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2330 if (ret)
2331 return ret;
54adc010 2332
285b6e9b
CH		 2333 if (shutdown) {
2334 return nvme_wait_ready(ctrl, NVME_CSTS_SHST_MASK,
2335 NVME_CSTS_SHST_CMPLT,
2336 ctrl->shutdown_timeout, "shutdown");
2337 }
b5a10c5f 2338 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010 2339 msleep(NVME_QUIRK_DELAY_AMOUNT);
e6d275de
CH		 2340 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, 0,
2341 (NVME_CAP_TIMEOUT(ctrl->cap) + 1) / 2, "reset");
5fd4ce1b 2342}
576d55d6 2343EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b 2344
c0f2f45b 2345int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
5fd4ce1b 2346{
6c3c05b0 2347 unsigned dev_page_min;
354201c5 2348 u32 timeout;
5fd4ce1b
CH		 2349 int ret;
2350
c0f2f45b
SG		 2351 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2352 if (ret) {
2353 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
2354 return ret;
2355 }
2356 dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12;
2357
6c3c05b0 2358 if (NVME_CTRL_PAGE_SHIFT < dev_page_min) {
1b3c47c1 2359 dev_err(ctrl->device,
5fd4ce1b 2360 "Minimum device page size %u too large for host (%u)\n",
6c3c05b0 2361 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT);
5fd4ce1b
CH		 2362 return -ENODEV;
2363 }
2364
71010c30
NC		 2365 if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI)
2366 ctrl->ctrl_config = NVME_CC_CSS_CSI;
2367 else
2368 ctrl->ctrl_config = NVME_CC_CSS_NVM;
354201c5 2369
6cc834ba
KB		 2370 if (ctrl->cap & NVME_CAP_CRMS_CRWMS && ctrl->cap & NVME_CAP_CRMS_CRIMS)
2371 ctrl->ctrl_config |= NVME_CC_CRIME;
354201c5 2372
6c3c05b0 2373 ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
60b43f62 2374 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b 2375 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
aa41d2fe
NC		 2376 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2377 if (ret)
2378 return ret;
5fd4ce1b 2379
aa41d2fe
NC		 2380 /* Flush write to device (required if transport is PCI) */
2381 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);
2382 if (ret)
2383 return ret;
2384
6cc834ba
KB		 2385 /* CAP value may change after initial CC write */
2386 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2387 if (ret)
2388 return ret;
2389
2390 timeout = NVME_CAP_TIMEOUT(ctrl->cap);
2391 if (ctrl->cap & NVME_CAP_CRMS_CRWMS) {
2392 u32 crto, ready_timeout;
2393
2394 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CRTO, &crto);
2395 if (ret) {
2396 dev_err(ctrl->device, "Reading CRTO failed (%d)\n",
2397 ret);
2398 return ret;
2399 }
2400
2401 /*
2402 * CRTO should always be greater or equal to CAP.TO, but some
2403 * devices are known to get this wrong. Use the larger of the
2404 * two values.
2405 */
2406 if (ctrl->ctrl_config & NVME_CC_CRIME)
2407 ready_timeout = NVME_CRTO_CRIMT(crto);
2408 else
2409 ready_timeout = NVME_CRTO_CRWMT(crto);
2410
2411 if (ready_timeout < timeout)
2412 dev_warn_once(ctrl->device, "bad crto:%x cap:%llx\n",
2413 crto, ctrl->cap);
2414 else
2415 timeout = ready_timeout;
2416 }
2417
aa41d2fe 2418 ctrl->ctrl_config |= NVME_CC_ENABLE;
5fd4ce1b
CH		 2419 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2420 if (ret)
2421 return ret;
e6d275de
CH		 2422 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY,
2423 (timeout + 1) / 2, "initialisation");
5fd4ce1b 2424}
576d55d6 2425EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b 2426
dbf86b39
JD		 2427static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
2428{
2429 __le64 ts;
2430 int ret;
2431
2432 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
2433 return 0;
2434
2435 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
2436 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
2437 NULL);
2438 if (ret)
2439 dev_warn_once(ctrl->device,
2440 "could not set timestamp (%d)\n", ret);
2441 return ret;
2442}
2443
4020aad8 2444static int nvme_configure_host_options(struct nvme_ctrl *ctrl)
49cd84b6
KB		 2445{
2446 struct nvme_feat_host_behavior *host;
4020aad8 2447 u8 acre = 0, lbafee = 0;
49cd84b6
KB		 2448 int ret;
2449
2450 /* Don't bother enabling the feature if retry delay is not reported */
4020aad8
KB		 2451 if (ctrl->crdt[0])
2452 acre = NVME_ENABLE_ACRE;
2453 if (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)
2454 lbafee = NVME_ENABLE_LBAFEE;
2455
2456 if (!acre && !lbafee)
49cd84b6
KB		 2457 return 0;
2458
2459 host = kzalloc(sizeof(*host), GFP_KERNEL);
2460 if (!host)
2461 return 0;
2462
4020aad8
KB		 2463 host->acre = acre;
2464 host->lbafee = lbafee;
49cd84b6
KB		 2465 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2466 host, sizeof(*host), NULL);
2467 kfree(host);
2468 return ret;
2469}
2470
ebd8a93a
AB		 2471/*
2472 * The function checks whether the given total (exlat + enlat) latency of
2473 * a power state allows the latter to be used as an APST transition target.
2474 * It does so by comparing the latency to the primary and secondary latency
2475 * tolerances defined by module params. If there's a match, the corresponding
2476 * timeout value is returned and the matching tolerance index (1 or 2) is
2477 * reported.
2478 */
2479static bool nvme_apst_get_transition_time(u64 total_latency,
2480 u64 *transition_time, unsigned *last_index)
2481{
2482 if (total_latency <= apst_primary_latency_tol_us) {
2483 if (*last_index == 1)
2484 return false;
2485 *last_index = 1;
2486 *transition_time = apst_primary_timeout_ms;
2487 return true;
2488 }
2489 if (apst_secondary_timeout_ms &&
2490 total_latency <= apst_secondary_latency_tol_us) {
2491 if (*last_index <= 2)
2492 return false;
2493 *last_index = 2;
2494 *transition_time = apst_secondary_timeout_ms;
2495 return true;
2496 }
2497 return false;
2498}
2499
60df5de9
CH		 2500/*
2501 * APST (Autonomous Power State Transition) lets us program a table of power
2502 * state transitions that the controller will perform automatically.
ebd8a93a
AB		 2503 *
2504 * Depending on module params, one of the two supported techniques will be used:
2505 *
2506 * - If the parameters provide explicit timeouts and tolerances, they will be
2507 * used to build a table with up to 2 non-operational states to transition to.
2508 * The default parameter values were selected based on the values used by
2509 * Microsoft's and Intel's NVMe drivers. Yet, since we don't implement dynamic
2510 * regeneration of the APST table in the event of switching between external
2511 * and battery power, the timeouts and tolerances reflect a compromise
2512 * between values used by Microsoft for AC and battery scenarios.
2513 * - If not, we'll configure the table with a simple heuristic: we are willing
2514 * to spend at most 2% of the time transitioning between power states.
2515 * Therefore, when running in any given state, we will enter the next
2516 * lower-power non-operational state after waiting 50 * (enlat + exlat)
2517 * microseconds, as long as that state's exit latency is under the requested
2518 * maximum latency.
60df5de9
CH		 2519 *
2520 * We will not autonomously enter any non-operational state for which the total
2521 * latency exceeds ps_max_latency_us.
2522 *
2523 * Users can set ps_max_latency_us to zero to turn off APST.
2524 */
634b8325 2525static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde 2526{
c5552fde 2527 struct nvme_feat_auto_pst *table;
60df5de9 2528 unsigned apste = 0;
fb0dc399 2529 u64 max_lat_us = 0;
60df5de9 2530 __le64 target = 0;
fb0dc399 2531 int max_ps = -1;
60df5de9 2532 int state;
c5552fde 2533 int ret;
ebd8a93a 2534 unsigned last_lt_index = UINT_MAX;
c5552fde
AL		 2535
2536 /*
2537 * If APST isn't supported or if we haven't been initialized yet,
2538 * then don't do anything.
2539 */
2540 if (!ctrl->apsta)
634b8325 2541 return 0;
c5552fde
AL		 2542
2543 if (ctrl->npss > 31) {
2544 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2545 return 0;
c5552fde
AL		 2546 }
2547
2548 table = kzalloc(sizeof(*table), GFP_KERNEL);
2549 if (!table)
634b8325 2550 return 0;
c5552fde 2551
76a5af84 2552 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde 2553 /* Turn off APST. */
fb0dc399 2554 dev_dbg(ctrl->device, "APST disabled\n");
60df5de9
CH		 2555 goto done;
2556 }
c5552fde 2557
60df5de9
CH		 2558 /*
2559 * Walk through all states from lowest- to highest-power.
2560 * According to the spec, lower-numbered states use more power. NPSS,
2561 * despite the name, is the index of the lowest-power state, not the
2562 * number of states.
2563 */
2564 for (state = (int)ctrl->npss; state >= 0; state--) {
2565 u64 total_latency_us, exit_latency_us, transition_ms;
da87591b 2566
60df5de9
CH		 2567 if (target)
2568 table->entries[state] = target;
c5552fde 2569
c5552fde 2570 /*
60df5de9
CH		 2571 * Don't allow transitions to the deepest state if it's quirked
2572 * off.
c5552fde 2573 */
60df5de9
CH		 2574 if (state == ctrl->npss &&
2575 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2576 continue;
fb0dc399 2577
60df5de9
CH		 2578 /*
2579 * Is this state a useful non-operational state for higher-power
2580 * states to autonomously transition to?
2581 */
2582 if (!(ctrl->psd[state].flags & NVME_PS_FLAGS_NON_OP_STATE))
2583 continue;
fb0dc399 2584
60df5de9
CH		 2585 exit_latency_us = (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2586 if (exit_latency_us > ctrl->ps_max_latency_us)
2587 continue;
c5552fde 2588
60df5de9
CH		 2589 total_latency_us = exit_latency_us +
2590 le32_to_cpu(ctrl->psd[state].entry_lat);
fb0dc399 2591
60df5de9 2592 /*
ebd8a93a
AB		 2593 * This state is good. It can be used as the APST idle target
2594 * for higher power states.
60df5de9 2595 */
ebd8a93a
AB		 2596 if (apst_primary_timeout_ms && apst_primary_latency_tol_us) {
2597 if (!nvme_apst_get_transition_time(total_latency_us,
2598 &transition_ms, &last_lt_index))
2599 continue;
2600 } else {
2601 transition_ms = total_latency_us + 19;
2602 do_div(transition_ms, 20);
2603 if (transition_ms > (1 << 24) - 1)
2604 transition_ms = (1 << 24) - 1;
2605 }
60df5de9
CH		 2606
2607 target = cpu_to_le64((state << 3) | (transition_ms << 8));
2608 if (max_ps == -1)
2609 max_ps = state;
2610 if (total_latency_us > max_lat_us)
2611 max_lat_us = total_latency_us;
c5552fde
AL		 2612 }
2613
60df5de9
CH		 2614 if (max_ps == -1)
2615 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2616 else
2617 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2618 max_ps, max_lat_us, (int)sizeof(*table), table);
2619 apste = 1;
2620
2621done:
c5552fde
AL		 2622 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2623 table, sizeof(*table), NULL);
2624 if (ret)
2625 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
c5552fde 2626 kfree(table);
634b8325 2627 return ret;
c5552fde
AL		 2628}
2629
2630static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2631{
2632 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2633 u64 latency;
2634
2635 switch (val) {
2636 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2637 case PM_QOS_LATENCY_ANY:
2638 latency = U64_MAX;
2639 break;
2640
2641 default:
2642 latency = val;
2643 }
2644
2645 if (ctrl->ps_max_latency_us != latency) {
2646 ctrl->ps_max_latency_us = latency;
e6e7f7ac 2647 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE)
53fe2a30 2648 nvme_configure_apst(ctrl);
c5552fde
AL		 2649 }
2650}
2651
bd4da3ab
AL		 2652struct nvme_core_quirk_entry {
2653 /*
2654 * NVMe model and firmware strings are padded with spaces. For
2655 * simplicity, strings in the quirk table are padded with NULLs
2656 * instead.
2657 */
2658 u16 vid;
2659 const char *mn;
2660 const char *fr;
2661 unsigned long quirks;
2662};
2663
2664static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2665 {
be56945c
AL		 2666 /*
2667 * This Toshiba device seems to die using any APST states. See:
2668 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2669 */
2670 .vid = 0x1179,
2671 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2672 .quirks = NVME_QUIRK_NO_APST,
cb32de1b
ML		 2673 },
2674 {
2675 /*
2676 * This LiteON CL1-3D*-Q11 firmware version has a race
2677 * condition associated with actions related to suspend to idle
2678 * LiteON has resolved the problem in future firmware
2679 */
2680 .vid = 0x14a4,
2681 .fr = "22301111",
2682 .quirks = NVME_QUIRK_SIMPLE_SUSPEND,
5a6254d5
EM		 2683 },
2684 {
2685 /*
2686 * This Kioxia CD6-V Series / HPE PE8030 device times out and
2687 * aborts I/O during any load, but more easily reproducible
2688 * with discards (fstrim).
2689 *
2690 * The device is left in a state where it is also not possible
2691 * to use "nvme set-feature" to disable APST, but booting with
2692 * nvme_core.default_ps_max_latency=0 works.
2693 */
2694 .vid = 0x1e0f,
2695 .mn = "KCD6XVUL6T40",
2696 .quirks = NVME_QUIRK_NO_APST,
e6487833
CH		 2697 },
2698 {
2699 /*
2700 * The external Samsung X5 SSD fails initialization without a
2701 * delay before checking if it is ready and has a whole set of
2702 * other problems. To make this even more interesting, it
2703 * shares the PCI ID with internal Samsung 970 Evo Plus that
2704 * does not need or want these quirks.
2705 */
2706 .vid = 0x144d,
2707 .mn = "Samsung Portable SSD X5",
2708 .quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
2709 NVME_QUIRK_NO_DEEPEST_PS |
2710 NVME_QUIRK_IGNORE_DEV_SUBNQN,
be56945c 2711 }
bd4da3ab
AL		 2712};
2713
2714/* match is null-terminated but idstr is space-padded. */
2715static bool string_matches(const char *idstr, const char *match, size_t len)
2716{
2717 size_t matchlen;
2718
2719 if (!match)
2720 return true;
2721
2722 matchlen = strlen(match);
2723 WARN_ON_ONCE(matchlen > len);
2724
2725 if (memcmp(idstr, match, matchlen))
2726 return false;
2727
2728 for (; matchlen < len; matchlen++)
2729 if (idstr[matchlen] != ' ')
2730 return false;
2731
2732 return true;
2733}
2734
2735static bool quirk_matches(const struct nvme_id_ctrl *id,
2736 const struct nvme_core_quirk_entry *q)
2737{
2738 return q->vid == le16_to_cpu(id->vid) &&
2739 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2740 string_matches(id->fr, q->fr, sizeof(id->fr));
2741}
2742
ab9e00cc
CH		 2743static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2744 struct nvme_id_ctrl *id)
180de007
CH		 2745{
2746 size_t nqnlen;
2747 int off;
2748
6299358d
JD		 2749 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2750 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2751 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
a8817cc0 2752 strscpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
6299358d
JD		 2753 return;
2754 }
180de007 2755
6299358d
JD		 2756 if (ctrl->vs >= NVME_VS(1, 2, 1))
2757 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2758 }
180de007 2759
1abc6961
LB		 2760 /*
2761 * Generate a "fake" NQN similar to the one in Section 4.5 of the NVMe
2762 * Base Specification 2.0. It is slightly different from the format
2763 * specified there due to historic reasons, and we can't change it now.
2764 */
ab9e00cc 2765 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2766 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2767 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2768 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2769 off += sizeof(id->sn);
ab9e00cc 2770 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2771 off += sizeof(id->mn);
ab9e00cc
CH		 2772 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2773}
2774
e654dfd3 2775static void nvme_release_subsystem(struct device *dev)
ab9e00cc 2776{
e654dfd3
LG		 2777 struct nvme_subsystem *subsys =
2778 container_of(dev, struct nvme_subsystem, dev);
2779
733e4b69 2780 if (subsys->instance >= 0)
8b850475 2781 ida_free(&nvme_instance_ida, subsys->instance);
ab9e00cc
CH		 2782 kfree(subsys);
2783}
2784
ab9e00cc
CH		 2785static void nvme_destroy_subsystem(struct kref *ref)
2786{
2787 struct nvme_subsystem *subsys =
2788 container_of(ref, struct nvme_subsystem, ref);
2789
2790 mutex_lock(&nvme_subsystems_lock);
2791 list_del(&subsys->entry);
2792 mutex_unlock(&nvme_subsystems_lock);
2793
ed754e5d 2794 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2795 device_del(&subsys->dev);
2796 put_device(&subsys->dev);
2797}
2798
2799static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2800{
2801 kref_put(&subsys->ref, nvme_destroy_subsystem);
2802}
2803
2804static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2805{
2806 struct nvme_subsystem *subsys;
2807
2808 lockdep_assert_held(&nvme_subsystems_lock);
2809
c26aa572
JS		 2810 /*
2811 * Fail matches for discovery subsystems. This results
2812 * in each discovery controller bound to a unique subsystem.
2813 * This avoids issues with validating controller values
2814 * that can only be true when there is a single unique subsystem.
2815 * There may be multiple and completely independent entities
2816 * that provide discovery controllers.
2817 */
2818 if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME))
2819 return NULL;
2820
ab9e00cc
CH		 2821 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2822 if (strcmp(subsys->subnqn, subsysnqn))
2823 continue;
2824 if (!kref_get_unless_zero(&subsys->ref))
2825 continue;
2826 return subsys;
2827 }
2828
2829 return NULL;
2830}
2831
5ab25a32
SG		 2832static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl)
2833{
2834 return ctrl->opts && ctrl->opts->discovery_nqn;
2835}
2836
1b1031ca
CH		 2837static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
2838 struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
b837b283 2839{
1b1031ca 2840 struct nvme_ctrl *tmp;
b837b283 2841
32fd90c4
CH		 2842 lockdep_assert_held(&nvme_subsystems_lock);
2843
1b1031ca 2844 list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) {
e7c43fea 2845 if (nvme_state_terminal(tmp))
1b1031ca
CH		 2846 continue;
2847
2848 if (tmp->cntlid == ctrl->cntlid) {
2849 dev_err(ctrl->device,
16cc33b2
KB		 2850 "Duplicate cntlid %u with %s, subsys %s, rejecting\n",
2851 ctrl->cntlid, dev_name(tmp->device),
2852 subsys->subnqn);
1b1031ca
CH		 2853 return false;
2854 }
b837b283 2855
92decf11 2856 if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) ||
5ab25a32 2857 nvme_discovery_ctrl(ctrl))
1b1031ca
CH		 2858 continue;
2859
2860 dev_err(ctrl->device,
2861 "Subsystem does not support multiple controllers\n");
2862 return false;
b837b283 2863 }
b837b283 2864
1b1031ca 2865 return true;
b837b283
IR		 2866}
2867
ab9e00cc
CH		 2868static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2869{
2870 struct nvme_subsystem *subsys, *found;
2871 int ret;
2872
2873 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2874 if (!subsys)
2875 return -ENOMEM;
733e4b69
KB		 2876
2877 subsys->instance = -1;
ab9e00cc
CH		 2878 mutex_init(&subsys->lock);
2879 kref_init(&subsys->ref);
2880 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2881 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2882 nvme_init_subnqn(subsys, ctrl, id);
2883 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2884 memcpy(subsys->model, id->mn, sizeof(subsys->model));
ab9e00cc
CH		 2885 subsys->vendor_id = le16_to_cpu(id->vid);
2886 subsys->cmic = id->cmic;
954ae166
HR		 2887
2888 /* Versions prior to 1.4 don't necessarily report a valid type */
2889 if (id->cntrltype == NVME_CTRL_DISC ||
2890 !strcmp(subsys->subnqn, NVME_DISC_SUBSYS_NAME))
2891 subsys->subtype = NVME_NQN_DISC;
2892 else
2893 subsys->subtype = NVME_NQN_NVME;
2894
20e8b689
HR		 2895 if (nvme_discovery_ctrl(ctrl) && subsys->subtype != NVME_NQN_DISC) {
2896 dev_err(ctrl->device,
2897 "Subsystem %s is not a discovery controller",
2898 subsys->subnqn);
2899 kfree(subsys);
2900 return -EINVAL;
2901 }
81adb863 2902 subsys->awupf = le16_to_cpu(id->awupf);
e3d34794 2903 nvme_mpath_default_iopolicy(subsys);
ab9e00cc 2904
ab21f3d9 2905 subsys->dev.class = &nvme_subsys_class;
ab9e00cc 2906 subsys->dev.release = nvme_release_subsystem;
1e496938 2907 subsys->dev.groups = nvme_subsys_attrs_groups;
733e4b69 2908 dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance);
ab9e00cc
CH		 2909 device_initialize(&subsys->dev);
2910
2911 mutex_lock(&nvme_subsystems_lock);
2912 found = __nvme_find_get_subsystem(subsys->subnqn);
2913 if (found) {
e654dfd3 2914 put_device(&subsys->dev);
ab9e00cc 2915 subsys = found;
32fd90c4 2916
1b1031ca 2917 if (!nvme_validate_cntlid(subsys, ctrl, id)) {
ab9e00cc 2918 ret = -EINVAL;
32fd90c4 2919 goto out_put_subsystem;
ab9e00cc 2920 }
ab9e00cc
CH		 2921 } else {
2922 ret = device_add(&subsys->dev);
2923 if (ret) {
2924 dev_err(ctrl->device,
2925 "failed to register subsystem device.\n");
8c36e66f 2926 put_device(&subsys->dev);
ab9e00cc
CH		 2927 goto out_unlock;
2928 }
ed754e5d 2929 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2930 list_add_tail(&subsys->entry, &nvme_subsystems);
2931 }
2932
bc4f6e06
DC		 2933 ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2934 dev_name(ctrl->device));
2935 if (ret) {
ab9e00cc
CH		 2936 dev_err(ctrl->device,
2937 "failed to create sysfs link from subsystem.\n");
32fd90c4 2938 goto out_put_subsystem;
ab9e00cc
CH		 2939 }
2940
733e4b69
KB		 2941 if (!found)
2942 subsys->instance = ctrl->instance;
32fd90c4 2943 ctrl->subsys = subsys;
ab9e00cc 2944 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
32fd90c4 2945 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc
CH		 2946 return 0;
2947
32fd90c4
CH		 2948out_put_subsystem:
2949 nvme_put_subsystem(subsys);
ab9e00cc
CH		 2950out_unlock:
2951 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 2952 return ret;
180de007
CH		 2953}
2954
be93e87e 2955int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
0e98719b 2956 void *log, size_t size, u64 offset)
c627c487
KB		 2957{
2958 struct nvme_command c = { };
71fb90eb 2959 u32 dwlen = nvme_bytes_to_numd(size);
70da6094
MB		 2960
2961 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2962 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2963 c.get_log_page.lid = log_page;
0e98719b 2964 c.get_log_page.lsp = lsp;
70da6094
MB		 2965 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2966 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2967 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2968 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
be93e87e 2969 c.get_log_page.csi = csi;
c627c487
KB		 2970
2971 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2972}
2973
be93e87e
KB		 2974static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi,
2975 struct nvme_effects_log **log)
84fef62d 2976{
f6224b86 2977 struct nvme_effects_log *cel = xa_load(&ctrl->cels, csi);
84fef62d
KB		 2978 int ret;
2979
be93e87e
KB		 2980 if (cel)
2981 goto out;
84fef62d 2982
be93e87e
KB		 2983 cel = kzalloc(sizeof(*cel), GFP_KERNEL);
2984 if (!cel)
2985 return -ENOMEM;
84fef62d 2986
46d2613e 2987 ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi,
f6224b86 2988 cel, sizeof(*cel), 0);
84fef62d 2989 if (ret) {
be93e87e
KB		 2990 kfree(cel);
2991 return ret;
84fef62d 2992 }
be93e87e 2993
f6224b86 2994 xa_store(&ctrl->cels, csi, cel, GFP_KERNEL);
be93e87e 2995out:
f6224b86 2996 *log = cel;
be93e87e 2997 return 0;
180de007
CH		 2998}
2999
5befc7c2 3000static inline u32 nvme_mps_to_sectors(struct nvme_ctrl *ctrl, u32 units)
7fd8930f 3001{
8609c63f 3002 u32 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12, val;
7fd8930f 3003
8609c63f
BVA		 3004 if (check_shl_overflow(1U, units + page_shift - 9, &val))
3005 return UINT_MAX;
3006 return val;
5befc7c2
KB		 3007}
3008
3009static int nvme_init_non_mdts_limits(struct nvme_ctrl *ctrl)
3010{
3011 struct nvme_command c = { };
3012 struct nvme_id_ctrl_nvm *id;
3013 int ret;
3014
5befc7c2
KB		 3015 /*
3016 * Even though NVMe spec explicitly states that MDTS is not applicable
3017 * to the write-zeroes, we are cautious and limit the size to the
3018 * controllers max_hw_sectors value, which is based on the MDTS field
3019 * and possibly other limiting factors.
3020 */
3021 if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) &&
3022 !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES))
3023 ctrl->max_zeroes_sectors = ctrl->max_hw_sectors;
3024 else
3025 ctrl->max_zeroes_sectors = 0;
3026
def84ab6 3027 if (ctrl->subsys->subtype != NVME_NQN_NVME ||
c917dd96
KB		 3028 nvme_ctrl_limited_cns(ctrl) ||
3029 test_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags))
5befc7c2
KB		 3030 return 0;
3031
3032 id = kzalloc(sizeof(*id), GFP_KERNEL);
3033 if (!id)
bcaf434b 3034 return -ENOMEM;
5befc7c2
KB		 3035
3036 c.identify.opcode = nvme_admin_identify;
3037 c.identify.cns = NVME_ID_CNS_CS_CTRL;
3038 c.identify.csi = NVME_CSI_NVM;
3039
3040 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
3041 if (ret)
3042 goto free_data;
3043
3b946fe1 3044 ctrl->dmrl = id->dmrl;
1a86924e 3045 ctrl->dmrsl = le32_to_cpu(id->dmrsl);
5befc7c2
KB		 3046 if (id->wzsl)
3047 ctrl->max_zeroes_sectors = nvme_mps_to_sectors(ctrl, id->wzsl);
3048
3049free_data:
c917dd96
KB		 3050 if (ret > 0)
3051 set_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags);
5befc7c2
KB		 3052 kfree(id);
3053 return ret;
3054}
3055
cc115cbe
KB		 3056static void nvme_init_known_nvm_effects(struct nvme_ctrl *ctrl)
3057{
3058 struct nvme_effects_log *log = ctrl->effects;
3059
3060 log->acs[nvme_admin_format_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC |
3061 NVME_CMD_EFFECTS_NCC |
3062 NVME_CMD_EFFECTS_CSE_MASK);
3063 log->acs[nvme_admin_sanitize_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC |
3064 NVME_CMD_EFFECTS_CSE_MASK);
3065
baff6491
KB		 3066 /*
3067 * The spec says the result of a security receive command depends on
3068 * the previous security send command. As such, many vendors log this
3069 * command as one to submitted only when no other commands to the same
3070 * namespace are outstanding. The intention is to tell the host to
3071 * prevent mixing security send and receive.
3072 *
3073 * This driver can only enforce such exclusive access against IO
3074 * queues, though. We are not readily able to enforce such a rule for
3075 * two commands to the admin queue, which is the only queue that
3076 * matters for this command.
3077 *
3078 * Rather than blindly freezing the IO queues for this effect that
3079 * doesn't even apply to IO, mask it off.
3080 */
c0c33b94 3081 log->acs[nvme_admin_security_recv] &= cpu_to_le32(~NVME_CMD_EFFECTS_CSE_MASK);
baff6491 3082
cc115cbe
KB		 3083 log->iocs[nvme_cmd_write] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3084 log->iocs[nvme_cmd_write_zeroes] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3085 log->iocs[nvme_cmd_write_uncor] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3086}
3087
3088static int nvme_init_effects(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
3089{
3090 int ret = 0;
3091
3092 if (ctrl->effects)
3093 return 0;
3094
3095 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
3096 ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects);
3097 if (ret < 0)
3098 return ret;
3099 }
3100
3101 if (!ctrl->effects) {
3102 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
3103 if (!ctrl->effects)
3104 return -ENOMEM;
3105 xa_store(&ctrl->cels, NVME_CSI_NVM, ctrl->effects, GFP_KERNEL);
3106 }
3107
3108 nvme_init_known_nvm_effects(ctrl);
3109 return 0;
3110}
3111
68999d1d
GL		 3112static int nvme_check_ctrl_fabric_info(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
3113{
3114 /*
3115 * In fabrics we need to verify the cntlid matches the
3116 * admin connect
3117 */
3118 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
3119 dev_err(ctrl->device,
3120 "Mismatching cntlid: Connect %u vs Identify %u, rejecting\n",
3121 ctrl->cntlid, le16_to_cpu(id->cntlid));
3122 return -EINVAL;
3123 }
3124
3125 if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) {
3126 dev_err(ctrl->device,
3127 "keep-alive support is mandatory for fabrics\n");
3128 return -EINVAL;
3129 }
3130
7642138e 3131 if (!nvme_discovery_ctrl(ctrl) && ctrl->ioccsz < 4) {
2fcd3ab3
GL		 3132 dev_err(ctrl->device,
3133 "I/O queue command capsule supported size %d < 4\n",
3134 ctrl->ioccsz);
3135 return -EINVAL;
3136 }
3137
7642138e 3138 if (!nvme_discovery_ctrl(ctrl) && ctrl->iorcsz < 1) {
2fcd3ab3
GL		 3139 dev_err(ctrl->device,
3140 "I/O queue response capsule supported size %d < 1\n",
3141 ctrl->iorcsz);
3142 return -EINVAL;
3143 }
3144
49995681
GL		 3145 if (!ctrl->maxcmd) {
3146 dev_err(ctrl->device, "Maximum outstanding commands is 0\n");
3147 return -EINVAL;
3148 }
3149
68999d1d
GL		 3150 return 0;
3151}
3152
44ef5611 3153static int nvme_init_identify(struct nvme_ctrl *ctrl)
7fd8930f 3154{
e6c9b130 3155 struct queue_limits lim;
7fd8930f 3156 struct nvme_id_ctrl *id;
a229dbf6 3157 u32 max_hw_sectors;
76a5af84 3158 bool prev_apst_enabled;
5befc7c2 3159 int ret;
f3ca80fc 3160
7fd8930f
CH		 3161 ret = nvme_identify_ctrl(ctrl, &id);
3162 if (ret) {
1b3c47c1 3163 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 3164 return -EIO;
3165 }
3166
a89fcca8
GP		 3167 if (!(ctrl->ops->flags & NVME_F_FABRICS))
3168 ctrl->cntlid = le16_to_cpu(id->cntlid);
3169
bd4da3ab 3170 if (!ctrl->identified) {
44ef5611 3171 unsigned int i;
ab9e00cc 3172
bd4da3ab
AL		 3173 /*
3174 * Check for quirks. Quirk can depend on firmware version,
3175 * so, in principle, the set of quirks present can change
3176 * across a reset. As a possible future enhancement, we
3177 * could re-scan for quirks every time we reinitialize
3178 * the device, but we'd have to make sure that the driver
3179 * behaves intelligently if the quirks change.
3180 */
bd4da3ab
AL		 3181 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
3182 if (quirk_matches(id, &core_quirks[i]))
3183 ctrl->quirks |= core_quirks[i].quirks;
3184 }
6f2d7152
PR		 3185
3186 ret = nvme_init_subsystem(ctrl, id);
3187 if (ret)
3188 goto out_free;
cc115cbe
KB		 3189
3190 ret = nvme_init_effects(ctrl, id);
3191 if (ret)
3192 goto out_free;
bd4da3ab 3193 }
a8eb6c1b
KB		 3194 memcpy(ctrl->subsys->firmware_rev, id->fr,
3195 sizeof(ctrl->subsys->firmware_rev));
bd4da3ab 3196
c35e30b4 3197 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 3198 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 3199 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
3200 }
3201
49cd84b6
KB		 3202 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
3203 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
3204 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
3205
8a9ae523 3206 ctrl->oacs = le16_to_cpu(id->oacs);
43e2d08d 3207 ctrl->oncs = le16_to_cpu(id->oncs);
2d466c7a 3208 ctrl->mtfa = le16_to_cpu(id->mtfa);
c0561f82 3209 ctrl->oaes = le32_to_cpu(id->oaes);
400b6a7b
GR		 3210 ctrl->wctemp = le16_to_cpu(id->wctemp);
3211 ctrl->cctemp = le16_to_cpu(id->cctemp);
3212
6bf25d16 3213 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 3214 ctrl->vwc = id->vwc;
7fd8930f 3215 if (id->mdts)
5befc7c2 3216 max_hw_sectors = nvme_mps_to_sectors(ctrl, id->mdts);
7fd8930f 3217 else
a229dbf6
CH		 3218 max_hw_sectors = UINT_MAX;
3219 ctrl->max_hw_sectors =
3220 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 3221
e6c9b130
CH		 3222 lim = queue_limits_start_update(ctrl->admin_q);
3223 nvme_set_ctrl_limits(ctrl, &lim);
3224 ret = queue_limits_commit_update(ctrl->admin_q, &lim);
3225 if (ret)
3226 goto out_free;
3227
07bfcd09 3228 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 3229 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 3230 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 3231 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 3232
86c2457a
MB		 3233 ctrl->cntrltype = id->cntrltype;
3234 ctrl->dctype = id->dctype;
3235
07fbd32a
MP		 3236 if (id->rtd3e) {
3237 /* us -> s */
f5af577d 3238 u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC;
07fbd32a
MP		 3239
3240 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
3241 shutdown_timeout, 60);
3242
3243 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 3244 dev_info(ctrl->device,
34485c37 3245 "D3 entry latency set to %u seconds\n",
07fbd32a
MP		 3246 ctrl->shutdown_timeout);
3247 } else
3248 ctrl->shutdown_timeout = shutdown_timeout;
3249
c5552fde 3250 ctrl->npss = id->npss;
76a5af84
KHF		 3251 ctrl->apsta = id->apsta;
3252 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 3253 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
3254 if (force_apst && id->apsta) {
f0425db0 3255 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 3256 ctrl->apst_enabled = true;
c35e30b4 3257 } else {
76a5af84 3258 ctrl->apst_enabled = false;
c35e30b4
AL		 3259 }
3260 } else {
76a5af84 3261 ctrl->apst_enabled = id->apsta;
c35e30b4 3262 }
c5552fde
AL		 3263 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
3264
d3d5b87d 3265 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 3266 ctrl->icdoff = le16_to_cpu(id->icdoff);
3267 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
3268 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
3269 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
3270
68999d1d
GL		 3271 ret = nvme_check_ctrl_fabric_info(ctrl, id);
3272 if (ret)
634b8325 3273 goto out_free;
07bfcd09 3274 } else {
fe6d53c9
CH		 3275 ctrl->hmpre = le32_to_cpu(id->hmpre);
3276 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 3277 ctrl->hmminds = le32_to_cpu(id->hmminds);
3278 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 3279 }
da35825d 3280
5e1f6899 3281 ret = nvme_mpath_init_identify(ctrl, id);
0d0b660f 3282 if (ret < 0)
44ef5611 3283 goto out_free;
0d0b660f 3284
76a5af84 3285 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 3286 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 3287 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 3288 dev_pm_qos_hide_latency_tolerance(ctrl->device);
3289
44ef5611
CK		 3290out_free:
3291 kfree(id);
3292 return ret;
3293}
3294
3295/*
3296 * Initialize the cached copies of the Identify data and various controller
3297 * register in our nvme_ctrl structure. This should be called as soon as
3298 * the admin queue is fully up and running.
3299 */
94cc781f 3300int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended)
44ef5611
CK		 3301{
3302 int ret;
3303
3304 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
3305 if (ret) {
3306 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
3307 return ret;
3308 }
3309
3310 ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize);
3311
3312 if (ctrl->vs >= NVME_VS(1, 1, 0))
3313 ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap);
3314
3315 ret = nvme_init_identify(ctrl);
3316 if (ret)
3317 return ret;
3318
634b8325
KB		 3319 ret = nvme_configure_apst(ctrl);
3320 if (ret < 0)
3321 return ret;
95d54bd1 3322
dbf86b39
JD		 3323 ret = nvme_configure_timestamp(ctrl);
3324 if (ret < 0)
3325 return ret;
634b8325 3326
4020aad8 3327 ret = nvme_configure_host_options(ctrl);
49cd84b6
KB		 3328 if (ret < 0)
3329 return ret;
3330
94cc781f
CH		 3331 nvme_configure_opal(ctrl, was_suspended);
3332
5ab25a32 3333 if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) {
6b8cf940
CH		 3334 /*
3335 * Do not return errors unless we are in a controller reset,
3336 * the controller works perfectly fine without hwmon.
3337 */
59e330f8 3338 ret = nvme_hwmon_init(ctrl);
6b8cf940 3339 if (ret == -EINTR)
59e330f8
KB		 3340 return ret;
3341 }
400b6a7b 3342
d0dd594b 3343 clear_bit(NVME_CTRL_DIRTY_CAPABILITY, &ctrl->flags);
bd4da3ab 3344 ctrl->identified = true;
c5552fde 3345
4733b65d
HR		 3346 nvme_start_keep_alive(ctrl);
3347
634b8325 3348 return 0;
7fd8930f 3349}
f21c4769 3350EXPORT_SYMBOL_GPL(nvme_init_ctrl_finish);
7fd8930f 3351
f3ca80fc 3352static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 3353{
a6a5149b
CH		 3354 struct nvme_ctrl *ctrl =
3355 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 3356
e6e7f7ac 3357 switch (nvme_ctrl_state(ctrl)) {
2b1b7e78 3358 case NVME_CTRL_LIVE:
2b1b7e78
JW		 3359 break;
3360 default:
a6a5149b 3361 return -EWOULDBLOCK;
2b1b7e78
JW		 3362 }
3363
52a3974f 3364 nvme_get_ctrl(ctrl);
4bab6909
CK		 3365 if (!try_module_get(ctrl->ops->module)) {
3366 nvme_put_ctrl(ctrl);
52a3974f 3367 return -EINVAL;
4bab6909 3368 }
52a3974f 3369
a6a5149b 3370 file->private_data = ctrl;
f3ca80fc
CH		 3371 return 0;
3372}
3373
52a3974f
CK		 3374static int nvme_dev_release(struct inode *inode, struct file *file)
3375{
3376 struct nvme_ctrl *ctrl =
3377 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
3378
3379 module_put(ctrl->ops->module);
3380 nvme_put_ctrl(ctrl);
3381 return 0;
3382}
3383
f3ca80fc
CH		 3384static const struct file_operations nvme_dev_fops = {
3385 .owner = THIS_MODULE,
3386 .open = nvme_dev_open,
52a3974f 3387 .release = nvme_dev_release,
f3ca80fc 3388 .unlocked_ioctl = nvme_dev_ioctl,
1832f2d8 3389 .compat_ioctl = compat_ptr_ioctl,
58e5bdeb 3390 .uring_cmd = nvme_dev_uring_cmd,
f3ca80fc
CH		 3391};
3392
5974ea7c 3393static struct nvme_ns_head *nvme_find_ns_head(struct nvme_ctrl *ctrl,
ed754e5d
CH		 3394 unsigned nsid)
3395{
3396 struct nvme_ns_head *h;
3397
5974ea7c 3398 lockdep_assert_held(&ctrl->subsys->lock);
ed754e5d 3399
5974ea7c
SM		 3400 list_for_each_entry(h, &ctrl->subsys->nsheads, entry) {
3401 /*
3402 * Private namespaces can share NSIDs under some conditions.
3403 * In that case we can't use the same ns_head for namespaces
3404 * with the same NSID.
3405 */
3406 if (h->ns_id != nsid || !nvme_is_unique_nsid(ctrl, h))
9edceaf4
DW		 3407 continue;
3408 if (!list_empty(&h->list) && nvme_tryget_ns_head(h))
ed754e5d
CH		 3409 return h;
3410 }
3411
3412 return NULL;
3413}
3414
fd8099e7
CH		 3415static int nvme_subsys_check_duplicate_ids(struct nvme_subsystem *subsys,
3416 struct nvme_ns_ids *ids)
ed754e5d 3417{
e2724cb9
CH		 3418 bool has_uuid = !uuid_is_null(&ids->uuid);
3419 bool has_nguid = memchr_inv(ids->nguid, 0, sizeof(ids->nguid));
3420 bool has_eui64 = memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
ed754e5d
CH		 3421 struct nvme_ns_head *h;
3422
3423 lockdep_assert_held(&subsys->lock);
3424
3425 list_for_each_entry(h, &subsys->nsheads, entry) {
e2724cb9
CH		 3426 if (has_uuid && uuid_equal(&ids->uuid, &h->ids.uuid))
3427 return -EINVAL;
3428 if (has_nguid &&
3429 memcmp(&ids->nguid, &h->ids.nguid, sizeof(ids->nguid)) == 0)
3430 return -EINVAL;
3431 if (has_eui64 &&
3432 memcmp(&ids->eui64, &h->ids.eui64, sizeof(ids->eui64)) == 0)
ed754e5d
CH		 3433 return -EINVAL;
3434 }
3435
3436 return 0;
3437}
3438
be5eb933
AM		 3439static void nvme_cdev_rel(struct device *dev)
3440{
8b850475 3441 ida_free(&nvme_ns_chr_minor_ida, MINOR(dev->devt));
be5eb933
AM		 3442}
3443
2637baed
MI		 3444void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device)
3445{
3446 cdev_device_del(cdev, cdev_device);
be5eb933 3447 put_device(cdev_device);
2637baed
MI		 3448}
3449
3450int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device,
3451 const struct file_operations *fops, struct module *owner)
3452{
3453 int minor, ret;
3454
8b850475 3455 minor = ida_alloc(&nvme_ns_chr_minor_ida, GFP_KERNEL);
2637baed
MI		 3456 if (minor < 0)
3457 return minor;
3458 cdev_device->devt = MKDEV(MAJOR(nvme_ns_chr_devt), minor);
ab21f3d9 3459 cdev_device->class = &nvme_ns_chr_class;
be5eb933 3460 cdev_device->release = nvme_cdev_rel;
2637baed
MI		 3461 device_initialize(cdev_device);
3462 cdev_init(cdev, fops);
3463 cdev->owner = owner;
3464 ret = cdev_device_add(cdev, cdev_device);
be5eb933 3465 if (ret)
3596a065 3466 put_device(cdev_device);
be5eb933 3467
2637baed
MI		 3468 return ret;
3469}
3470
3471static int nvme_ns_chr_open(struct inode *inode, struct file *file)
3472{
3473 return nvme_ns_open(container_of(inode->i_cdev, struct nvme_ns, cdev));
3474}
3475
3476static int nvme_ns_chr_release(struct inode *inode, struct file *file)
3477{
3478 nvme_ns_release(container_of(inode->i_cdev, struct nvme_ns, cdev));
3479 return 0;
3480}
3481
3482static const struct file_operations nvme_ns_chr_fops = {
3483 .owner = THIS_MODULE,
3484 .open = nvme_ns_chr_open,
3485 .release = nvme_ns_chr_release,
3486 .unlocked_ioctl = nvme_ns_chr_ioctl,
3487 .compat_ioctl = compat_ptr_ioctl,
456cba38 3488 .uring_cmd = nvme_ns_chr_uring_cmd,
585079b6 3489 .uring_cmd_iopoll = nvme_ns_chr_uring_cmd_iopoll,
2637baed
MI		 3490};
3491
3492static int nvme_add_ns_cdev(struct nvme_ns *ns)
3493{
3494 int ret;
3495
3496 ns->cdev_device.parent = ns->ctrl->device;
3497 ret = dev_set_name(&ns->cdev_device, "ng%dn%d",
3498 ns->ctrl->instance, ns->head->instance);
3499 if (ret)
3500 return ret;
be5eb933
AM		 3501
3502 return nvme_cdev_add(&ns->cdev, &ns->cdev_device, &nvme_ns_chr_fops,
3503 ns->ctrl->ops->module);
2637baed
MI		 3504}
3505
ed754e5d 3506static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
1a893c2b 3507 struct nvme_ns_info *info)
ed754e5d
CH		 3508{
3509 struct nvme_ns_head *head;
f3334447 3510 size_t size = sizeof(*head);
ed754e5d
CH		 3511 int ret = -ENOMEM;
3512
f3334447
CH		 3513#ifdef CONFIG_NVME_MULTIPATH
3514 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3515#endif
3516
3517 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH		 3518 if (!head)
3519 goto out;
8b850475 3520 ret = ida_alloc_min(&ctrl->subsys->ns_ida, 1, GFP_KERNEL);
ed754e5d
CH		 3521 if (ret < 0)
3522 goto out_free_head;
3523 head->instance = ret;
3524 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 3525 ret = init_srcu_struct(&head->srcu);
3526 if (ret)
3527 goto out_ida_remove;
ed754e5d 3528 head->subsys = ctrl->subsys;
1a893c2b
CH		 3529 head->ns_id = info->nsid;
3530 head->ids = info->ids;
3531 head->shared = info->is_shared;
a1a825ab
DW		 3532 ratelimit_state_init(&head->rs_nuse, 5 * HZ, 1);
3533 ratelimit_set_flags(&head->rs_nuse, RATELIMIT_MSG_ON_RELEASE);
ed754e5d
CH		 3534 kref_init(&head->ref);
3535
be93e87e
KB		 3536 if (head->ids.csi) {
3537 ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects);
3538 if (ret)
3539 goto out_cleanup_srcu;
3540 } else
3541 head->effects = ctrl->effects;
3542
32acab31
CH		 3543 ret = nvme_mpath_alloc_disk(ctrl, head);
3544 if (ret)
3545 goto out_cleanup_srcu;
3546
ed754e5d 3547 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 3548
3549 kref_get(&ctrl->subsys->ref);
3550
ed754e5d
CH		 3551 return head;
3552out_cleanup_srcu:
3553 cleanup_srcu_struct(&head->srcu);
fd92c77f 3554out_ida_remove:
8b850475 3555 ida_free(&ctrl->subsys->ns_ida, head->instance);
ed754e5d
CH		 3556out_free_head:
3557 kfree(head);
3558out:
538af88e
SG		 3559 if (ret > 0)
3560 ret = blk_status_to_errno(nvme_error_status(ret));
ed754e5d
CH		 3561 return ERR_PTR(ret);
3562}
3563
2079f41e
CH		 3564static int nvme_global_check_duplicate_ids(struct nvme_subsystem *this,
3565 struct nvme_ns_ids *ids)
3566{
3567 struct nvme_subsystem *s;
3568 int ret = 0;
3569
3570 /*
3571 * Note that this check is racy as we try to avoid holding the global
3572 * lock over the whole ns_head creation. But it is only intended as
3573 * a sanity check anyway.
3574 */
3575 mutex_lock(&nvme_subsystems_lock);
3576 list_for_each_entry(s, &nvme_subsystems, entry) {
3577 if (s == this)
3578 continue;
3579 mutex_lock(&s->lock);
3580 ret = nvme_subsys_check_duplicate_ids(s, ids);
3581 mutex_unlock(&s->lock);
3582 if (ret)
3583 break;
3584 }
3585 mutex_unlock(&nvme_subsystems_lock);
3586
3587 return ret;
3588}
3589
1a893c2b 3590static int nvme_init_ns_head(struct nvme_ns *ns, struct nvme_ns_info *info)
ed754e5d
CH		 3591{
3592 struct nvme_ctrl *ctrl = ns->ctrl;
ed754e5d 3593 struct nvme_ns_head *head = NULL;
2079f41e
CH		 3594 int ret;
3595
1a893c2b 3596 ret = nvme_global_check_duplicate_ids(ctrl->subsys, &info->ids);
2079f41e 3597 if (ret) {
ac522fc6
CH		 3598 /*
3599 * We've found two different namespaces on two different
3600 * subsystems that report the same ID. This is pretty nasty
3601 * for anything that actually requires unique device
3602 * identification. In the kernel we need this for multipathing,
3603 * and in user space the /dev/disk/by-id/ links rely on it.
3604 *
3605 * If the device also claims to be multi-path capable back off
3606 * here now and refuse the probe the second device as this is a
3607 * recipe for data corruption. If not this is probably a
3608 * cheap consumer device if on the PCIe bus, so let the user
3609 * proceed and use the shiny toy, but warn that with changing
3610 * probing order (which due to our async probing could just be
3611 * device taking longer to startup) the other device could show
3612 * up at any time.
3613 */
2f0dad17 3614 nvme_print_device_info(ctrl);
ac522fc6
CH		 3615 if ((ns->ctrl->ops->flags & NVME_F_FABRICS) || /* !PCIe */
3616 ((ns->ctrl->subsys->cmic & NVME_CTRL_CMIC_MULTI_CTRL) &&
3617 info->is_shared)) {
3618 dev_err(ctrl->device,
3619 "ignoring nsid %d because of duplicate IDs\n",
3620 info->nsid);
3621 return ret;
3622 }
3623
3624 dev_err(ctrl->device,
3625 "clearing duplicate IDs for nsid %d\n", info->nsid);
3626 dev_err(ctrl->device,
3627 "use of /dev/disk/by-id/ may cause data corruption\n");
3628 memset(&info->ids.nguid, 0, sizeof(info->ids.nguid));
3629 memset(&info->ids.uuid, 0, sizeof(info->ids.uuid));
3630 memset(&info->ids.eui64, 0, sizeof(info->ids.eui64));
3631 ctrl->quirks |= NVME_QUIRK_BOGUS_NID;
2079f41e 3632 }
ed754e5d
CH		 3633
3634 mutex_lock(&ctrl->subsys->lock);
1a893c2b 3635 head = nvme_find_ns_head(ctrl, info->nsid);
ed754e5d 3636 if (!head) {
1a893c2b 3637 ret = nvme_subsys_check_duplicate_ids(ctrl->subsys, &info->ids);
e2d77d2e
CH		 3638 if (ret) {
3639 dev_err(ctrl->device,
2079f41e 3640 "duplicate IDs in subsystem for nsid %d\n",
1a893c2b 3641 info->nsid);
e2d77d2e
CH		 3642 goto out_unlock;
3643 }
1a893c2b 3644 head = nvme_alloc_ns_head(ctrl, info);
ed754e5d
CH		 3645 if (IS_ERR(head)) {
3646 ret = PTR_ERR(head);
3647 goto out_unlock;
3648 }
ed754e5d 3649 } else {
6623c5b3 3650 ret = -EINVAL;
1a893c2b 3651 if (!info->is_shared || !head->shared) {
9ad1927a 3652 dev_err(ctrl->device,
1a893c2b
CH		 3653 "Duplicate unshared namespace %d\n",
3654 info->nsid);
6623c5b3 3655 goto out_put_ns_head;
9ad1927a 3656 }
1a893c2b 3657 if (!nvme_ns_ids_equal(&head->ids, &info->ids)) {
ed754e5d
CH		 3658 dev_err(ctrl->device,
3659 "IDs don't match for shared namespace %d\n",
1a893c2b 3660 info->nsid);
6623c5b3 3661 goto out_put_ns_head;
ed754e5d 3662 }
ce8d7861 3663
2110a6bc 3664 if (!multipath) {
ce8d7861
CH		 3665 dev_warn(ctrl->device,
3666 "Found shared namespace %d, but multipathing not supported.\n",
1a893c2b 3667 info->nsid);
ce8d7861 3668 dev_warn_once(ctrl->device,
0bc2e80b 3669 "Support for shared namespaces without CONFIG_NVME_MULTIPATH is deprecated and will be removed in Linux 6.0.\n");
ce8d7861 3670 }
ed754e5d
CH		 3671 }
3672
772ea326 3673 list_add_tail_rcu(&ns->siblings, &head->list);
ed754e5d 3674 ns->head = head;
6623c5b3
CH		 3675 mutex_unlock(&ctrl->subsys->lock);
3676 return 0;
ed754e5d 3677
6623c5b3
CH		 3678out_put_ns_head:
3679 nvme_put_ns_head(head);
ed754e5d
CH		 3680out_unlock:
3681 mutex_unlock(&ctrl->subsys->lock);
3682 return ret;
3683}
3684
24493b8b 3685struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3686{
32f0c4af 3687 struct nvme_ns *ns, *ret = NULL;
be647e2c 3688 int srcu_idx;
69d3b8ac 3689
be647e2c
KB		 3690 srcu_idx = srcu_read_lock(&ctrl->srcu);
3691 list_for_each_entry_rcu(ns, &ctrl->namespaces, list) {
ed754e5d 3692 if (ns->head->ns_id == nsid) {
4c74d1f8 3693 if (!nvme_get_ns(ns))
2dd41228 3694 continue;
32f0c4af
KB		 3695 ret = ns;
3696 break;
3697 }
ed754e5d 3698 if (ns->head->ns_id > nsid)
5bae7f73
CH		 3699 break;
3700 }
be647e2c 3701 srcu_read_unlock(&ctrl->srcu, srcu_idx);
32f0c4af 3702 return ret;
5bae7f73 3703}
24493b8b 3704EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU);
5bae7f73 3705
298ba0e3
CH		 3706/*
3707 * Add the namespace to the controller list while keeping the list ordered.
3708 */
3709static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns)
3710{
3711 struct nvme_ns *tmp;
3712
3713 list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) {
3714 if (tmp->head->ns_id < ns->head->ns_id) {
be647e2c 3715 list_add_rcu(&ns->list, &tmp->list);
298ba0e3
CH		 3716 return;
3717 }
3718 }
3719 list_add(&ns->list, &ns->ctrl->namespaces);
3720}
3721
1a893c2b 3722static void nvme_alloc_ns(struct nvme_ctrl *ctrl, struct nvme_ns_info *info)
5bae7f73
CH		 3723{
3724 struct nvme_ns *ns;
3725 struct gendisk *disk;
9953ab0c 3726 int node = ctrl->numa_node;
5bae7f73
CH		 3727
3728 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3729 if (!ns)
1a893c2b 3730 return;
5bae7f73 3731
27e32cd2 3732 disk = blk_mq_alloc_disk(ctrl->tagset, NULL, ns);
5f432cce 3733 if (IS_ERR(disk))
ed754e5d 3734 goto out_free_ns;
5f432cce
CH		 3735 disk->fops = &nvme_bdev_ops;
3736 disk->private_data = ns;
3737
3738 ns->disk = disk;
3739 ns->queue = disk->queue;
e0596ab2 3740
7d30c81b 3741 if (ctrl->opts && ctrl->opts->data_digest)
1cb039f3 3742 blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, ns->queue);
958f2a0f 3743
8b904b5b 3744 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
2f859441
LG		 3745 if (ctrl->ops->supports_pci_p2pdma &&
3746 ctrl->ops->supports_pci_p2pdma(ctrl))
e0596ab2
LG		 3747 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3748
5bae7f73 3749 ns->ctrl = ctrl;
5bae7f73 3750 kref_init(&ns->kref);
5bae7f73 3751
1a893c2b 3752 if (nvme_init_ns_head(ns, info))
5f432cce 3753 goto out_cleanup_disk;
ac81bfa9 3754
9953ab0c 3755 /*
b739e137
CH		 3756 * If multipathing is enabled, the device name for all disks and not
3757 * just those that represent shared namespaces needs to be based on the
3758 * subsystem instance. Using the controller instance for private
3759 * namespaces could lead to naming collisions between shared and private
3760 * namespaces if they don't use a common numbering scheme.
3761 *
3762 * If multipathing is not enabled, disk names must use the controller
3763 * instance as shared namespaces will show up as multiple block
3764 * devices.
9953ab0c 3765 */
35e797b0 3766 if (nvme_ns_head_multipath(ns->head)) {
b739e137
CH		 3767 sprintf(disk->disk_name, "nvme%dc%dn%d", ctrl->subsys->instance,
3768 ctrl->instance, ns->head->instance);
3769 disk->flags |= GENHD_FL_HIDDEN;
3770 } else if (multipath) {
3771 sprintf(disk->disk_name, "nvme%dn%d", ctrl->subsys->instance,
3772 ns->head->instance);
3773 } else {
9953ab0c
CH		 3774 sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance,
3775 ns->head->instance);
b739e137 3776 }
3dc87dd0 3777
1a893c2b 3778 if (nvme_update_ns_info(ns, info))
5f432cce 3779 goto out_unlink_ns;
5bae7f73 3780
be647e2c 3781 mutex_lock(&ctrl->namespaces_lock);
839a40d1
BH		 3782 /*
3783 * Ensure that no namespaces are added to the ctrl list after the queues
3784 * are frozen, thereby avoiding a deadlock between scan and reset.
3785 */
3786 if (test_bit(NVME_CTRL_FROZEN, &ctrl->flags)) {
be647e2c 3787 mutex_unlock(&ctrl->namespaces_lock);
839a40d1
BH		 3788 goto out_unlink_ns;
3789 }
298ba0e3 3790 nvme_ns_add_to_ctrl_list(ns);
be647e2c
KB		 3791 mutex_unlock(&ctrl->namespaces_lock);
3792 synchronize_srcu(&ctrl->srcu);
d22524a4 3793 nvme_get_ctrl(ctrl);
ac81bfa9 3794
83ac678e 3795 if (device_add_disk(ctrl->device, ns->disk, nvme_ns_attr_groups))
ab3994f6
LC		 3796 goto out_cleanup_ns_from_list;
3797
2637baed
MI		 3798 if (!nvme_ns_head_multipath(ns->head))
3799 nvme_add_ns_cdev(ns);
32acab31 3800
1a893c2b 3801 nvme_mpath_add_disk(ns, info->anagrpid);
a3646451 3802 nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name);
0d0b660f 3803
9f079dda
AA		 3804 /*
3805 * Set ns->disk->device->driver_data to ns so we can access
e8c263ed
CK		 3806 * ns->head->passthru_err_log_enabled in
3807 * nvme_io_passthru_err_log_enabled_[store | show]().
9f079dda
AA		 3808 */
3809 dev_set_drvdata(disk_to_dev(ns->disk), ns);
3810
adce7e98 3811 return;
5f432cce 3812
ab3994f6
LC		 3813 out_cleanup_ns_from_list:
3814 nvme_put_ctrl(ctrl);
be647e2c
KB		 3815 mutex_lock(&ctrl->namespaces_lock);
3816 list_del_rcu(&ns->list);
3817 mutex_unlock(&ctrl->namespaces_lock);
3818 synchronize_srcu(&ctrl->srcu);
ed754e5d
CH		 3819 out_unlink_ns:
3820 mutex_lock(&ctrl->subsys->lock);
3821 list_del_rcu(&ns->siblings);
d5675729
KB		 3822 if (list_empty(&ns->head->list))
3823 list_del_init(&ns->head->entry);
ed754e5d 3824 mutex_unlock(&ctrl->subsys->lock);
a63b8370 3825 nvme_put_ns_head(ns->head);
5f432cce 3826 out_cleanup_disk:
8b9ab626 3827 put_disk(disk);
5bae7f73
CH		 3828 out_free_ns:
3829 kfree(ns);
3830}
3831
3832static void nvme_ns_remove(struct nvme_ns *ns)
3833{
5396fdac
HR		 3834 bool last_path = false;
3835
646017a6
KB		 3836 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3837 return;
69d3b8ac 3838
e7d65803 3839 clear_bit(NVME_NS_READY, &ns->flags);
0a05226a 3840 set_capacity(ns->disk, 0);
a3646451 3841 nvme_fault_inject_fini(&ns->fault_inject);
2181e455 3842
d6d67427
CL		 3843 /*
3844 * Ensure that !NVME_NS_READY is seen by other threads to prevent
3845 * this ns going back into current_path.
3846 */
3847 synchronize_srcu(&ns->head->srcu);
3848
3849 /* wait for concurrent submissions */
3850 if (nvme_mpath_clear_current_path(ns))
3851 synchronize_srcu(&ns->head->srcu);
3852
2181e455
AE		 3853 mutex_lock(&ns->ctrl->subsys->lock);
3854 list_del_rcu(&ns->siblings);
9edceaf4
DW		 3855 if (list_empty(&ns->head->list)) {
3856 list_del_init(&ns->head->entry);
3857 last_path = true;
3858 }
2181e455 3859 mutex_unlock(&ns->ctrl->subsys->lock);
d5675729 3860
041bd1a1 3861 /* guarantee not available in head->list */
899d2a05 3862 synchronize_srcu(&ns->head->srcu);
041bd1a1 3863
5eba2005
CH		 3864 if (!nvme_ns_head_multipath(ns->head))
3865 nvme_cdev_del(&ns->cdev, &ns->cdev_device);
3866 del_gendisk(ns->disk);
32f0c4af 3867
be647e2c
KB		 3868 mutex_lock(&ns->ctrl->namespaces_lock);
3869 list_del_rcu(&ns->list);
3870 mutex_unlock(&ns->ctrl->namespaces_lock);
3871 synchronize_srcu(&ns->ctrl->srcu);
32f0c4af 3872
5396fdac
HR		 3873 if (last_path)
3874 nvme_mpath_shutdown_disk(ns->head);
5bae7f73
CH		 3875 nvme_put_ns(ns);
3876}
3877
4450ba3b
CH		 3878static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid)
3879{
3880 struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid);
3881
3882 if (ns) {
3883 nvme_ns_remove(ns);
3884 nvme_put_ns(ns);
3885 }
3886}
3887
1a893c2b 3888static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_info *info)
b2dc748a 3889{
d95c1f41 3890 int ret = NVME_SC_INVALID_NS | NVME_SC_DNR;
b2dc748a 3891
1a893c2b 3892 if (!nvme_ns_ids_equal(&ns->head->ids, &info->ids)) {
af5d6f7b 3893 dev_err(ns->ctrl->device,
b2dc748a 3894 "identifiers changed for nsid %d\n", ns->head->ns_id);
1a893c2b 3895 goto out;
b2dc748a
CH		 3896 }
3897
1a893c2b 3898 ret = nvme_update_ns_info(ns, info);
b2dc748a
CH		 3899out:
3900 /*
0a05226a 3901 * Only remove the namespace if we got a fatal error back from the
b2dc748a 3902 * device, otherwise ignore the error and just move on.
0a05226a
CH		 3903 *
3904 * TODO: we should probably schedule a delayed retry here.
b2dc748a 3905 */
d95c1f41 3906 if (ret > 0 && (ret & NVME_SC_DNR))
0a05226a 3907 nvme_ns_remove(ns);
b2dc748a
CH		 3908}
3909
04c170f6 3910static void nvme_scan_ns(struct nvme_ctrl *ctrl, unsigned nsid)
540c801c 3911{
1a893c2b 3912 struct nvme_ns_info info = { .nsid = nsid };
540c801c 3913 struct nvme_ns *ns;
0dd6fff2 3914 int ret;
540c801c 3915
1a893c2b 3916 if (nvme_identify_ns_descs(ctrl, &info))
8b7c0ff2 3917 return;
540c801c 3918
1a893c2b 3919 if (info.ids.csi != NVME_CSI_NVM && !nvme_multi_css(ctrl)) {
71882e7d
CH		 3920 dev_warn(ctrl->device,
3921 "command set not reported for nsid: %d\n", nsid);
3922 return;
3923 }
3924
354201c5 3925 /*
1a893c2b
CH		 3926 * If available try to use the Command Set Idependent Identify Namespace
3927 * data structure to find all the generic information that is needed to
3928 * set up a namespace. If not fall back to the legacy version.
354201c5 3929 */
eb867ee9 3930 if ((ctrl->cap & NVME_CAP_CRMS_CRIMS) ||
0dd6fff2
CH		 3931 (info.ids.csi != NVME_CSI_NVM && info.ids.csi != NVME_CSI_ZNS))
3932 ret = nvme_ns_info_from_id_cs_indep(ctrl, &info);
3933 else
3934 ret = nvme_ns_info_from_identify(ctrl, &info);
3935
3936 if (info.is_removed)
3937 nvme_ns_remove_by_nsid(ctrl, nsid);
354201c5 3938
1a893c2b
CH		 3939 /*
3940 * Ignore the namespace if it is not ready. We will get an AEN once it
3941 * becomes ready and restart the scan.
3942 */
0dd6fff2 3943 if (ret || !info.is_ready)
354201c5
CH		 3944 return;
3945
32f0c4af 3946 ns = nvme_find_get_ns(ctrl, nsid);
8b7c0ff2 3947 if (ns) {
1a893c2b 3948 nvme_validate_ns(ns, &info);
8b7c0ff2 3949 nvme_put_ns(ns);
1a893c2b
CH		 3950 } else {
3951 nvme_alloc_ns(ctrl, &info);
8b7c0ff2 3952 }
540c801c
KB		 3953}
3954
47b0e50a
SB		 3955static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3956 unsigned nsid)
3957{
3958 struct nvme_ns *ns, *next;
6f8e0d78 3959 LIST_HEAD(rm_list);
47b0e50a 3960
be647e2c 3961 mutex_lock(&ctrl->namespaces_lock);
47b0e50a 3962 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
ff0ffe5b
KB		 3963 if (ns->head->ns_id > nsid) {
3964 list_del_rcu(&ns->list);
3965 synchronize_srcu(&ctrl->srcu);
3966 list_add_tail_rcu(&ns->list, &rm_list);
3967 }
47b0e50a 3968 }
be647e2c 3969 mutex_unlock(&ctrl->namespaces_lock);
6f8e0d78
JW		 3970
3971 list_for_each_entry_safe(ns, next, &rm_list, list)
3972 nvme_ns_remove(ns);
47b0e50a
SB		 3973}
3974
4005f28d 3975static int nvme_scan_ns_list(struct nvme_ctrl *ctrl)
540c801c 3976{
aec459b4 3977 const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32);
540c801c 3978 __le32 *ns_list;
4005f28d
CH		 3979 u32 prev = 0;
3980 int ret = 0, i;
540c801c 3981
42595eb7 3982 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3983 if (!ns_list)
3984 return -ENOMEM;
3985
4005f28d 3986 for (;;) {
7b153362
CH		 3987 struct nvme_command cmd = {
3988 .identify.opcode = nvme_admin_identify,
3989 .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST,
3990 .identify.nsid = cpu_to_le32(prev),
3991 };
3992
3993 ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list,
3994 NVME_IDENTIFY_DATA_SIZE);
f781f3dd
MI		 3995 if (ret) {
3996 dev_warn(ctrl->device,
3997 "Identify NS List failed (status=0x%x)\n", ret);
47b0e50a 3998 goto free;
f781f3dd 3999 }
540c801c 4000
aec459b4 4001 for (i = 0; i < nr_entries; i++) {
4005f28d 4002 u32 nsid = le32_to_cpu(ns_list[i]);
540c801c 4003
4005f28d
CH		 4004 if (!nsid) /* end of the list? */
4005 goto out;
04c170f6 4006 nvme_scan_ns(ctrl, nsid);
4450ba3b
CH		 4007 while (++prev < nsid)
4008 nvme_ns_remove_by_nsid(ctrl, prev);
540c801c 4009 }
540c801c
KB		 4010 }
4011 out:
47b0e50a
SB		 4012 nvme_remove_invalid_namespaces(ctrl, prev);
4013 free:
540c801c
KB		 4014 kfree(ns_list);
4015 return ret;
4016}
4017
4005f28d 4018static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl)
5bae7f73 4019{
4005f28d
CH		 4020 struct nvme_id_ctrl *id;
4021 u32 nn, i;
4022
4023 if (nvme_identify_ctrl(ctrl, &id))
4024 return;
4025 nn = le32_to_cpu(id->nn);
4026 kfree(id);
5bae7f73 4027
540c801c 4028 for (i = 1; i <= nn; i++)
04c170f6 4029 nvme_scan_ns(ctrl, i);
540c801c 4030
47b0e50a 4031 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 4032}
4033
f493af37 4034static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 4035{
4036 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
4037 __le32 *log;
f493af37 4038 int error;
30d90964
CH		 4039
4040 log = kzalloc(log_size, GFP_KERNEL);
4041 if (!log)
f493af37 4042 return;
30d90964 4043
f493af37
CH		 4044 /*
4045 * We need to read the log to clear the AEN, but we don't want to rely
4046 * on it for the changed namespace information as userspace could have
4047 * raced with us in reading the log page, which could cause us to miss
4048 * updates.
4049 */
be93e87e
KB		 4050 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0,
4051 NVME_CSI_NVM, log, log_size, 0);
f493af37 4052 if (error)
30d90964
CH		 4053 dev_warn(ctrl->device,
4054 "reading changed ns log failed: %d\n", error);
30d90964 4055
30d90964 4056 kfree(log);
30d90964
CH		 4057}
4058
5955be21 4059static void nvme_scan_work(struct work_struct *work)
5bae7f73 4060{
5955be21
CH		 4061 struct nvme_ctrl *ctrl =
4062 container_of(work, struct nvme_ctrl, scan_work);
78288665 4063 int ret;
5bae7f73 4064
5d02a5c1 4065 /* No tagset on a live ctrl means IO queues could not created */
e6e7f7ac 4066 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE || !ctrl->tagset)
5955be21
CH		 4067 return;
4068
78288665
CK		 4069 /*
4070 * Identify controller limits can change at controller reset due to
4071 * new firmware download, even though it is not common we cannot ignore
4072 * such scenario. Controller's non-mdts limits are reported in the unit
4073 * of logical blocks that is dependent on the format of attached
4074 * namespace. Hence re-read the limits at the time of ns allocation.
4075 */
4076 ret = nvme_init_non_mdts_limits(ctrl);
4077 if (ret < 0) {
4078 dev_warn(ctrl->device,
4079 "reading non-mdts-limits failed: %d\n", ret);
4080 return;
4081 }
4082
77016199 4083 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 4084 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 4085 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 4086 }
4087
e7ad43c3 4088 mutex_lock(&ctrl->scan_lock);
811f4de0 4089 if (nvme_ctrl_limited_cns(ctrl)) {
4005f28d 4090 nvme_scan_ns_sequential(ctrl);
811f4de0
US		 4091 } else {
4092 /*
4093 * Fall back to sequential scan if DNR is set to handle broken
4094 * devices which should support Identify NS List (as per the VS
4095 * they report) but don't actually support it.
4096 */
4097 ret = nvme_scan_ns_list(ctrl);
4098 if (ret > 0 && ret & NVME_SC_DNR)
4099 nvme_scan_ns_sequential(ctrl);
4100 }
e7ad43c3 4101 mutex_unlock(&ctrl->scan_lock);
5955be21 4102}
5bae7f73 4103
32f0c4af
KB		 4104/*
4105 * This function iterates the namespace list unlocked to allow recovery from
4106 * controller failure. It is up to the caller to ensure the namespace list is
4107 * not modified by scan work while this function is executing.
4108 */
5bae7f73
CH		 4109void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
4110{
4111 struct nvme_ns *ns, *next;
6f8e0d78 4112 LIST_HEAD(ns_list);
5bae7f73 4113
0157ec8d
SG		 4114 /*
4115 * make sure to requeue I/O to all namespaces as these
4116 * might result from the scan itself and must complete
4117 * for the scan_work to make progress
4118 */
4119 nvme_mpath_clear_ctrl_paths(ctrl);
4120
1b95e817
ML		 4121 /*
4122 * Unquiesce io queues so any pending IO won't hang, especially
4123 * those submitted from scan work
4124 */
4125 nvme_unquiesce_io_queues(ctrl);
4126
f6c8e432
SG		 4127 /* prevent racing with ns scanning */
4128 flush_work(&ctrl->scan_work);
4129
0ff9d4e1
KB		 4130 /*
4131 * The dead states indicates the controller was not gracefully
4132 * disconnected. In that case, we won't be able to flush any data while
4133 * removing the namespaces' disks; fail all the queues now to avoid
4134 * potentially having to clean up the failed sync later.
4135 */
e6e7f7ac 4136 if (nvme_ctrl_state(ctrl) == NVME_CTRL_DEAD)
cd50f9b2 4137 nvme_mark_namespaces_dead(ctrl);
0ff9d4e1 4138
ecca390e
SG		 4139 /* this is a no-op when called from the controller reset handler */
4140 nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO);
4141
be647e2c
KB		 4142 mutex_lock(&ctrl->namespaces_lock);
4143 list_splice_init_rcu(&ctrl->namespaces, &ns_list, synchronize_rcu);
4144 mutex_unlock(&ctrl->namespaces_lock);
4145 synchronize_srcu(&ctrl->srcu);
6f8e0d78
JW		 4146
4147 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 4148 nvme_ns_remove(ns);
4149}
576d55d6 4150EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 4151
23680f0b 4152static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env)
a42f42e5 4153{
23680f0b 4154 const struct nvme_ctrl *ctrl =
a42f42e5
SG		 4155 container_of(dev, struct nvme_ctrl, ctrl_device);
4156 struct nvmf_ctrl_options *opts = ctrl->opts;
4157 int ret;
4158
4159 ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name);
4160 if (ret)
4161 return ret;
4162
4163 if (opts) {
4164 ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr);
4165 if (ret)
4166 return ret;
4167
4168 ret = add_uevent_var(env, "NVME_TRSVCID=%s",
4169 opts->trsvcid ?: "none");
4170 if (ret)
4171 return ret;
4172
4173 ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s",
4174 opts->host_traddr ?: "none");
3ede8f72
MB		 4175 if (ret)
4176 return ret;
4177
4178 ret = add_uevent_var(env, "NVME_HOST_IFACE=%s",
4179 opts->host_iface ?: "none");
a42f42e5
SG		 4180 }
4181 return ret;
4182}
4183
20d64911
MB		 4184static void nvme_change_uevent(struct nvme_ctrl *ctrl, char *envdata)
4185{
4186 char *envp[2] = { envdata, NULL };
4187
4188 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4189}
4190
e3d7874d
KB		 4191static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
4192{
4193 char *envp[2] = { NULL, NULL };
4194 u32 aen_result = ctrl->aen_result;
4195
4196 ctrl->aen_result = 0;
4197 if (!aen_result)
4198 return;
4199
4200 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
4201 if (!envp[0])
4202 return;
4203 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4204 kfree(envp[0]);
4205}
4206
f866fc42
CH		 4207static void nvme_async_event_work(struct work_struct *work)
4208{
4209 struct nvme_ctrl *ctrl =
4210 container_of(work, struct nvme_ctrl, async_event_work);
4211
e3d7874d 4212 nvme_aen_uevent(ctrl);
0fa0f99f
SG		 4213
4214 /*
4215 * The transport drivers must guarantee AER submission here is safe by
4216 * flushing ctrl async_event_work after changing the controller state
4217 * from LIVE and before freeing the admin queue.
4218 */
e6e7f7ac 4219 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE)
0fa0f99f 4220 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 4221}
4222
b6dccf7f
AD		 4223static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
4224{
4225
4226 u32 csts;
4227
4228 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
4229 return false;
4230
4231 if (csts == ~0)
4232 return false;
4233
4234 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
4235}
4236
4237static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
4238{
b6dccf7f 4239 struct nvme_fw_slot_info_log *log;
f0377ff9 4240 u8 next_fw_slot, cur_fw_slot;
b6dccf7f
AD		 4241
4242 log = kmalloc(sizeof(*log), GFP_KERNEL);
4243 if (!log)
4244 return;
4245
be93e87e 4246 if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM,
983a338b 4247 log, sizeof(*log), 0)) {
0e98719b 4248 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
983a338b
DW		 4249 goto out_free_log;
4250 }
4251
f0377ff9
ML		 4252 cur_fw_slot = log->afi & 0x7;
4253 next_fw_slot = (log->afi & 0x70) >> 4;
4254 if (!cur_fw_slot || (next_fw_slot && (cur_fw_slot != next_fw_slot))) {
983a338b
DW		 4255 dev_info(ctrl->device,
4256 "Firmware is activated after next Controller Level Reset\n");
4257 goto out_free_log;
4258 }
4259
f0377ff9 4260 memcpy(ctrl->subsys->firmware_rev, &log->frs[cur_fw_slot - 1],
983a338b
DW		 4261 sizeof(ctrl->subsys->firmware_rev));
4262
4263out_free_log:
b6dccf7f
AD		 4264 kfree(log);
4265}
4266
4267static void nvme_fw_act_work(struct work_struct *work)
4268{
4269 struct nvme_ctrl *ctrl = container_of(work,
4270 struct nvme_ctrl, fw_act_work);
4271 unsigned long fw_act_timeout;
4272
f6fe0b2d
ML		 4273 nvme_auth_stop(ctrl);
4274
b6dccf7f
AD		 4275 if (ctrl->mtfa)
4276 fw_act_timeout = jiffies +
4277 msecs_to_jiffies(ctrl->mtfa * 100);
4278 else
4279 fw_act_timeout = jiffies +
4280 msecs_to_jiffies(admin_timeout * 1000);
4281
9f27bd70 4282 nvme_quiesce_io_queues(ctrl);
b6dccf7f
AD		 4283 while (nvme_ctrl_pp_status(ctrl)) {
4284 if (time_after(jiffies, fw_act_timeout)) {
4285 dev_warn(ctrl->device,
4286 "Fw activation timeout, reset controller\n");
4c75f877
KB		 4287 nvme_try_sched_reset(ctrl);
4288 return;
b6dccf7f
AD		 4289 }
4290 msleep(100);
4291 }
4292
4c75f877 4293 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE))
b6dccf7f
AD		 4294 return;
4295
9f27bd70 4296 nvme_unquiesce_io_queues(ctrl);
a806c6c8 4297 /* read FW slot information to clear the AER */
b6dccf7f 4298 nvme_get_fw_slot_info(ctrl);
371a982c
KB		 4299
4300 queue_work(nvme_wq, &ctrl->async_event_work);
b6dccf7f
AD		 4301}
4302
2c61c97f
MK		 4303static u32 nvme_aer_type(u32 result)
4304{
4305 return result & 0x7;
4306}
4307
4308static u32 nvme_aer_subtype(u32 result)
4309{
4310 return (result & 0xff00) >> 8;
4311}
4312
371a982c 4313static bool nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
868c2392 4314{
2c61c97f 4315 u32 aer_notice_type = nvme_aer_subtype(result);
371a982c 4316 bool requeue = true;
09bd1ff4
CK		 4317
4318 switch (aer_notice_type) {
868c2392 4319 case NVME_AER_NOTICE_NS_CHANGED:
77016199 4320 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 4321 nvme_queue_scan(ctrl);
4322 break;
4323 case NVME_AER_NOTICE_FW_ACT_STARTING:
4c75f877
KB		 4324 /*
4325 * We are (ab)using the RESETTING state to prevent subsequent
4326 * recovery actions from interfering with the controller's
4327 * firmware activation.
4328 */
f50fff73 4329 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) {
371a982c 4330 requeue = false;
4c75f877 4331 queue_work(nvme_wq, &ctrl->fw_act_work);
f50fff73 4332 }
868c2392 4333 break;
0d0b660f
CH		 4334#ifdef CONFIG_NVME_MULTIPATH
4335 case NVME_AER_NOTICE_ANA:
4336 if (!ctrl->ana_log_buf)
4337 break;
4338 queue_work(nvme_wq, &ctrl->ana_work);
4339 break;
4340#endif
85f8a435
SG		 4341 case NVME_AER_NOTICE_DISC_CHANGED:
4342 ctrl->aen_result = result;
4343 break;
868c2392
CH		 4344 default:
4345 dev_warn(ctrl->device, "async event result %08x\n", result);
4346 }
371a982c 4347 return requeue;
868c2392
CH		 4348}
4349
2c61c97f
MK		 4350static void nvme_handle_aer_persistent_error(struct nvme_ctrl *ctrl)
4351{
2c61c97f
MK		 4352 dev_warn(ctrl->device, "resetting controller due to AER\n");
4353 nvme_reset_ctrl(ctrl);
4354}
4355
7bf58533 4356void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 4357 volatile union nvme_result *res)
f866fc42 4358{
7bf58533 4359 u32 result = le32_to_cpu(res->u32);
2c61c97f
MK		 4360 u32 aer_type = nvme_aer_type(result);
4361 u32 aer_subtype = nvme_aer_subtype(result);
371a982c 4362 bool requeue = true;
f866fc42 4363
ad22c355 4364 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 4365 return;
4366
6622b76f 4367 trace_nvme_async_event(ctrl, result);
09bd1ff4 4368 switch (aer_type) {
868c2392 4369 case NVME_AER_NOTICE:
371a982c 4370 requeue = nvme_handle_aen_notice(ctrl, result);
868c2392 4371 break;
e3d7874d 4372 case NVME_AER_ERROR:
2c61c97f
MK		 4373 /*
4374 * For a persistent internal error, don't run async_event_work
4375 * to submit a new AER. The controller reset will do it.
4376 */
4377 if (aer_subtype == NVME_AER_ERROR_PERSIST_INT_ERR) {
4378 nvme_handle_aer_persistent_error(ctrl);
4379 return;
4380 }
4381 fallthrough;
e3d7874d
KB		 4382 case NVME_AER_SMART:
4383 case NVME_AER_CSS:
4384 case NVME_AER_VS:
4385 ctrl->aen_result = result;
7bf58533
CH		 4386 break;
4387 default:
4388 break;
f866fc42 4389 }
371a982c
KB		 4390
4391 if (requeue)
4392 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 4393}
f866fc42 4394EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 4395
fe60e8c5 4396int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
db45e1a5 4397 const struct blk_mq_ops *ops, unsigned int cmd_size)
fe60e8c5 4398{
e6c9b130 4399 struct queue_limits lim = {};
fe60e8c5
CH		 4400 int ret;
4401
4402 memset(set, 0, sizeof(*set));
4403 set->ops = ops;
4404 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
4405 if (ctrl->ops->flags & NVME_F_FABRICS)
de105068
CX		 4406 /* Reserved for fabric connect and keep alive */
4407 set->reserved_tags = 2;
fe60e8c5 4408 set->numa_node = ctrl->numa_node;
db45e1a5
CH		 4409 set->flags = BLK_MQ_F_NO_SCHED;
4410 if (ctrl->ops->flags & NVME_F_BLOCKING)
4411 set->flags |= BLK_MQ_F_BLOCKING;
fe60e8c5
CH		 4412 set->cmd_size = cmd_size;
4413 set->driver_data = ctrl;
4414 set->nr_hw_queues = 1;
4415 set->timeout = NVME_ADMIN_TIMEOUT;
4416 ret = blk_mq_alloc_tag_set(set);
4417 if (ret)
4418 return ret;
4419
e6c9b130 4420 ctrl->admin_q = blk_mq_alloc_queue(set, &lim, NULL);
fe60e8c5
CH		 4421 if (IS_ERR(ctrl->admin_q)) {
4422 ret = PTR_ERR(ctrl->admin_q);
4423 goto out_free_tagset;
4424 }
4425
4426 if (ctrl->ops->flags & NVME_F_FABRICS) {
9ac4dd8c 4427 ctrl->fabrics_q = blk_mq_alloc_queue(set, NULL, NULL);
fe60e8c5
CH		 4428 if (IS_ERR(ctrl->fabrics_q)) {
4429 ret = PTR_ERR(ctrl->fabrics_q);
4430 goto out_cleanup_admin_q;
4431 }
4432 }
4433
4434 ctrl->admin_tagset = set;
4435 return 0;
4436
4437out_cleanup_admin_q:
4739824e 4438 blk_mq_destroy_queue(ctrl->admin_q);
2b3f056f 4439 blk_put_queue(ctrl->admin_q);
fe60e8c5 4440out_free_tagset:
fd62678a
ML		 4441 blk_mq_free_tag_set(set);
4442 ctrl->admin_q = NULL;
4443 ctrl->fabrics_q = NULL;
fe60e8c5
CH		 4444 return ret;
4445}
4446EXPORT_SYMBOL_GPL(nvme_alloc_admin_tag_set);
4447
4448void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl)
4449{
4450 blk_mq_destroy_queue(ctrl->admin_q);
2b3f056f
CH		 4451 blk_put_queue(ctrl->admin_q);
4452 if (ctrl->ops->flags & NVME_F_FABRICS) {
fe60e8c5 4453 blk_mq_destroy_queue(ctrl->fabrics_q);
2b3f056f
CH		 4454 blk_put_queue(ctrl->fabrics_q);
4455 }
fe60e8c5
CH		 4456 blk_mq_free_tag_set(ctrl->admin_tagset);
4457}
4458EXPORT_SYMBOL_GPL(nvme_remove_admin_tag_set);
4459
4460int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
db45e1a5 4461 const struct blk_mq_ops *ops, unsigned int nr_maps,
fe60e8c5
CH		 4462 unsigned int cmd_size)
4463{
4464 int ret;
4465
4466 memset(set, 0, sizeof(*set));
4467 set->ops = ops;
33b93727 4468 set->queue_depth = min_t(unsigned, ctrl->sqsize, BLK_MQ_MAX_DEPTH - 1);
93b24f57
CH		 4469 /*
4470 * Some Apple controllers requires tags to be unique across admin and
4471 * the (only) I/O queue, so reserve the first 32 tags of the I/O queue.
4472 */
4473 if (ctrl->quirks & NVME_QUIRK_SHARED_TAGS)
4474 set->reserved_tags = NVME_AQ_DEPTH;
4475 else if (ctrl->ops->flags & NVME_F_FABRICS)
de105068
CX		 4476 /* Reserved for fabric connect */
4477 set->reserved_tags = 1;
fe60e8c5 4478 set->numa_node = ctrl->numa_node;
db45e1a5
CH		 4479 set->flags = BLK_MQ_F_SHOULD_MERGE;
4480 if (ctrl->ops->flags & NVME_F_BLOCKING)
4481 set->flags |= BLK_MQ_F_BLOCKING;
fe60e8c5
CH		 4482 set->cmd_size = cmd_size,
4483 set->driver_data = ctrl;
4484 set->nr_hw_queues = ctrl->queue_count - 1;
4485 set->timeout = NVME_IO_TIMEOUT;
dcef7727 4486 set->nr_maps = nr_maps;
fe60e8c5
CH		 4487 ret = blk_mq_alloc_tag_set(set);
4488 if (ret)
4489 return ret;
4490
4491 if (ctrl->ops->flags & NVME_F_FABRICS) {
9ac4dd8c 4492 ctrl->connect_q = blk_mq_alloc_queue(set, NULL, NULL);
fe60e8c5
CH		 4493 if (IS_ERR(ctrl->connect_q)) {
4494 ret = PTR_ERR(ctrl->connect_q);
4495 goto out_free_tag_set;
4496 }
98d81f0d
CL		 4497 blk_queue_flag_set(QUEUE_FLAG_SKIP_TAGSET_QUIESCE,
4498 ctrl->connect_q);
fe60e8c5
CH		 4499 }
4500
4501 ctrl->tagset = set;
4502 return 0;
4503
4504out_free_tag_set:
4505 blk_mq_free_tag_set(set);
6fbf13c0 4506 ctrl->connect_q = NULL;
fe60e8c5
CH		 4507 return ret;
4508}
4509EXPORT_SYMBOL_GPL(nvme_alloc_io_tag_set);
4510
4511void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl)
4512{
2b3f056f 4513 if (ctrl->ops->flags & NVME_F_FABRICS) {
fe60e8c5 4514 blk_mq_destroy_queue(ctrl->connect_q);
2b3f056f
CH		 4515 blk_put_queue(ctrl->connect_q);
4516 }
fe60e8c5
CH		 4517 blk_mq_free_tag_set(ctrl->tagset);
4518}
4519EXPORT_SYMBOL_GPL(nvme_remove_io_tag_set);
4520
d09f2b45 4521void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 4522{
0d0b660f 4523 nvme_mpath_stop(ctrl);
f50fff73 4524 nvme_auth_stop(ctrl);
3af755a4 4525 nvme_stop_keep_alive(ctrl);
8c4dfea9 4526 nvme_stop_failfast_work(ctrl);
f866fc42 4527 flush_work(&ctrl->async_event_work);
b6dccf7f 4528 cancel_work_sync(&ctrl->fw_act_work);
f7f70f4a
RL		 4529 if (ctrl->ops->stop_ctrl)
4530 ctrl->ops->stop_ctrl(ctrl);
d09f2b45
SG		 4531}
4532EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
4533
4534void nvme_start_ctrl(struct nvme_ctrl *ctrl)
4535{
93da4023
SG		 4536 nvme_enable_aen(ctrl);
4537
f46ef9e8
SG		 4538 /*
4539 * persistent discovery controllers need to send indication to userspace
4540 * to re-read the discovery log page to learn about possible changes
4541 * that were missed. We identify persistent discovery controllers by
4542 * checking that they started once before, hence are reconnecting back.
4543 */
2eb94dd5 4544 if (test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) &&
f46ef9e8
SG		 4545 nvme_discovery_ctrl(ctrl))
4546 nvme_change_uevent(ctrl, "NVME_EVENT=rediscover");
4547
d09f2b45
SG		 4548 if (ctrl->queue_count > 1) {
4549 nvme_queue_scan(ctrl);
9f27bd70 4550 nvme_unquiesce_io_queues(ctrl);
a4a6f3c8 4551 nvme_mpath_update(ctrl);
d09f2b45 4552 }
20d64911
MB		 4553
4554 nvme_change_uevent(ctrl, "NVME_EVENT=connected");
2eb94dd5 4555 set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags);
d09f2b45
SG		 4556}
4557EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 4558
d09f2b45
SG		 4559void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
4560{
ed7770f6 4561 nvme_hwmon_exit(ctrl);
f79d5fda 4562 nvme_fault_inject_fini(&ctrl->fault_inject);
510a405d 4563 dev_pm_qos_hide_latency_tolerance(ctrl->device);
a6a5149b 4564 cdev_device_del(&ctrl->cdev, ctrl->device);
726612b6 4565 nvme_put_ctrl(ctrl);
53029b04 4566}
576d55d6 4567EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 4568
8168d23f
KB		 4569static void nvme_free_cels(struct nvme_ctrl *ctrl)
4570{
4571 struct nvme_effects_log *cel;
4572 unsigned long i;
4573
8f8ea928 4574 xa_for_each(&ctrl->cels, i, cel) {
8168d23f
KB		 4575 xa_erase(&ctrl->cels, i);
4576 kfree(cel);
4577 }
4578
4579 xa_destroy(&ctrl->cels);
4580}
4581
d22524a4 4582static void nvme_free_ctrl(struct device *dev)
53029b04 4583{
d22524a4
CH		 4584 struct nvme_ctrl *ctrl =
4585 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 4586 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 4587
192f6c29 4588 if (!subsys || ctrl->instance != subsys->instance)
8b850475 4589 ida_free(&nvme_instance_ida, ctrl->instance);
be8e82ca 4590 key_put(ctrl->tls_key);
8168d23f 4591 nvme_free_cels(ctrl);
0d0b660f 4592 nvme_mpath_uninit(ctrl);
be647e2c 4593 cleanup_srcu_struct(&ctrl->srcu);
f50fff73
HR		 4594 nvme_auth_stop(ctrl);
4595 nvme_auth_free(ctrl);
092ff052 4596 __free_page(ctrl->discard_page);
94cc781f 4597 free_opal_dev(ctrl->opal_dev);
f3ca80fc 4598
ab9e00cc 4599 if (subsys) {
32fd90c4 4600 mutex_lock(&nvme_subsystems_lock);
ab9e00cc 4601 list_del(&ctrl->subsys_entry);
ab9e00cc 4602 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
32fd90c4 4603 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 4604 }
f3ca80fc
CH		 4605
4606 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 4607
ab9e00cc
CH		 4608 if (subsys)
4609 nvme_put_subsystem(subsys);
f3ca80fc
CH		 4610}
4611
4612/*
4613 * Initialize a NVMe controller structures. This needs to be called during
4614 * earliest initialization so that we have the initialized structured around
4615 * during probing.
4616 */
4617int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
4618 const struct nvme_ctrl_ops *ops, unsigned long quirks)
4619{
4620 int ret;
4621
e6e7f7ac 4622 WRITE_ONCE(ctrl->state, NVME_CTRL_NEW);
9f079dda 4623 ctrl->passthru_err_log_enabled = false;
8c4dfea9 4624 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
bb8d261e 4625 spin_lock_init(&ctrl->lock);
be647e2c
KB		 4626 mutex_init(&ctrl->namespaces_lock);
4627
4628 ret = init_srcu_struct(&ctrl->srcu);
4629 if (ret)
4630 return ret;
4631
e7ad43c3 4632 mutex_init(&ctrl->scan_lock);
f3ca80fc 4633 INIT_LIST_HEAD(&ctrl->namespaces);
1cf7a12e 4634 xa_init(&ctrl->cels);
f3ca80fc
CH		 4635 ctrl->dev = dev;
4636 ctrl->ops = ops;
4637 ctrl->quirks = quirks;
4fea243e 4638 ctrl->numa_node = NUMA_NO_NODE;
5955be21 4639 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 4640 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 4641 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 4642 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
c1ac9a4b 4643 init_waitqueue_head(&ctrl->state_wq);
f3ca80fc 4644
230f1f9e 4645 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
8c4dfea9 4646 INIT_DELAYED_WORK(&ctrl->failfast_work, nvme_failfast_work);
230f1f9e
JS		 4647 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
4648 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
136cfcb8 4649 ctrl->ka_last_check_time = jiffies;
230f1f9e 4650
cb5b7262
JA		 4651 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
4652 PAGE_SIZE);
4653 ctrl->discard_page = alloc_page(GFP_KERNEL);
4654 if (!ctrl->discard_page) {
4655 ret = -ENOMEM;
4656 goto out;
4657 }
4658
8b850475 4659 ret = ida_alloc(&nvme_instance_ida, GFP_KERNEL);
9843f685 4660 if (ret < 0)
f3ca80fc 4661 goto out;
9843f685 4662 ctrl->instance = ret;
f3ca80fc 4663
d22524a4
CH		 4664 device_initialize(&ctrl->ctrl_device);
4665 ctrl->device = &ctrl->ctrl_device;
f68abd9c
JG		 4666 ctrl->device->devt = MKDEV(MAJOR(nvme_ctrl_base_chr_devt),
4667 ctrl->instance);
ab21f3d9 4668 ctrl->device->class = &nvme_class;
d22524a4 4669 ctrl->device->parent = ctrl->dev;
86adbf0c
CH		 4670 if (ops->dev_attr_groups)
4671 ctrl->device->groups = ops->dev_attr_groups;
4672 else
4673 ctrl->device->groups = nvme_dev_attr_groups;
d22524a4
CH		 4674 ctrl->device->release = nvme_free_ctrl;
4675 dev_set_drvdata(ctrl->device, ctrl);
4676 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
4677 if (ret)
f3ca80fc 4678 goto out_release_instance;
f3ca80fc 4679
b780d741 4680 nvme_get_ctrl(ctrl);
a6a5149b
CH		 4681 cdev_init(&ctrl->cdev, &nvme_dev_fops);
4682 ctrl->cdev.owner = ops->module;
4683 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 4684 if (ret)
4685 goto out_free_name;
f3ca80fc 4686
c5552fde
AL		 4687 /*
4688 * Initialize latency tolerance controls. The sysfs files won't
4689 * be visible to userspace unless the device actually supports APST.
4690 */
4691 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
4692 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
4693 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
4694
f79d5fda 4695 nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device));
5e1f6899 4696 nvme_mpath_init_ctrl(ctrl);
193a8c7e
SG		 4697 ret = nvme_auth_init_ctrl(ctrl);
4698 if (ret)
4699 goto out_free_cdev;
f79d5fda 4700
f3ca80fc 4701 return 0;
193a8c7e 4702out_free_cdev:
3a12a0b8 4703 nvme_fault_inject_fini(&ctrl->fault_inject);
7ed5cf8e 4704 dev_pm_qos_hide_latency_tolerance(ctrl->device);
193a8c7e 4705 cdev_device_del(&ctrl->cdev, ctrl->device);
d22524a4 4706out_free_name:
b780d741 4707 nvme_put_ctrl(ctrl);
d6a2b953 4708 kfree_const(ctrl->device->kobj.name);
f3ca80fc 4709out_release_instance:
8b850475 4710 ida_free(&nvme_instance_ida, ctrl->instance);
f3ca80fc 4711out:
cb5b7262
JA		 4712 if (ctrl->discard_page)
4713 __free_page(ctrl->discard_page);
be647e2c 4714 cleanup_srcu_struct(&ctrl->srcu);
f3ca80fc
CH		 4715 return ret;
4716}
576d55d6 4717EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 4718
cd50f9b2
CH		 4719/* let I/O to all namespaces fail in preparation for surprise removal */
4720void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl)
69d9a99c
KB		 4721{
4722 struct nvme_ns *ns;
be647e2c 4723 int srcu_idx;
69d9a99c 4724
be647e2c
KB		 4725 srcu_idx = srcu_read_lock(&ctrl->srcu);
4726 list_for_each_entry_rcu(ns, &ctrl->namespaces, list)
cd50f9b2 4727 blk_mark_disk_dead(ns->disk);
be647e2c 4728 srcu_read_unlock(&ctrl->srcu, srcu_idx);
69d9a99c 4729}
cd50f9b2 4730EXPORT_SYMBOL_GPL(nvme_mark_namespaces_dead);
69d9a99c 4731
302ad8cc
KB		 4732void nvme_unfreeze(struct nvme_ctrl *ctrl)
4733{
4734 struct nvme_ns *ns;
be647e2c 4735 int srcu_idx;
302ad8cc 4736
be647e2c
KB		 4737 srcu_idx = srcu_read_lock(&ctrl->srcu);
4738 list_for_each_entry_rcu(ns, &ctrl->namespaces, list)
302ad8cc 4739 blk_mq_unfreeze_queue(ns->queue);
be647e2c 4740 srcu_read_unlock(&ctrl->srcu, srcu_idx);
839a40d1 4741 clear_bit(NVME_CTRL_FROZEN, &ctrl->flags);
302ad8cc
KB		 4742}
4743EXPORT_SYMBOL_GPL(nvme_unfreeze);
4744
7cf0d7c0 4745int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
302ad8cc
KB		 4746{
4747 struct nvme_ns *ns;
be647e2c 4748 int srcu_idx;
302ad8cc 4749
be647e2c
KB		 4750 srcu_idx = srcu_read_lock(&ctrl->srcu);
4751 list_for_each_entry_rcu(ns, &ctrl->namespaces, list) {
302ad8cc
KB		 4752 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
4753 if (timeout <= 0)
4754 break;
4755 }
be647e2c 4756 srcu_read_unlock(&ctrl->srcu, srcu_idx);
7cf0d7c0 4757 return timeout;
302ad8cc
KB		 4758}
4759EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
4760
4761void nvme_wait_freeze(struct nvme_ctrl *ctrl)
4762{
4763 struct nvme_ns *ns;
be647e2c 4764 int srcu_idx;
302ad8cc 4765
be647e2c
KB		 4766 srcu_idx = srcu_read_lock(&ctrl->srcu);
4767 list_for_each_entry_rcu(ns, &ctrl->namespaces, list)
302ad8cc 4768 blk_mq_freeze_queue_wait(ns->queue);
be647e2c 4769 srcu_read_unlock(&ctrl->srcu, srcu_idx);
302ad8cc
KB		 4770}
4771EXPORT_SYMBOL_GPL(nvme_wait_freeze);
4772
4773void nvme_start_freeze(struct nvme_ctrl *ctrl)
4774{
4775 struct nvme_ns *ns;
be647e2c 4776 int srcu_idx;
302ad8cc 4777
839a40d1 4778 set_bit(NVME_CTRL_FROZEN, &ctrl->flags);
be647e2c
KB		 4779 srcu_idx = srcu_read_lock(&ctrl->srcu);
4780 list_for_each_entry_rcu(ns, &ctrl->namespaces, list)
1671d522 4781 blk_freeze_queue_start(ns->queue);
be647e2c 4782 srcu_read_unlock(&ctrl->srcu, srcu_idx);
302ad8cc
KB		 4783}
4784EXPORT_SYMBOL_GPL(nvme_start_freeze);
4785
9f27bd70 4786void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl)
363c9aac 4787{
ba0718a6
CH		 4788 if (!ctrl->tagset)
4789 return;
98d81f0d
CL		 4790 if (!test_and_set_bit(NVME_CTRL_STOPPED, &ctrl->flags))
4791 blk_mq_quiesce_tagset(ctrl->tagset);
4792 else
4793 blk_mq_wait_quiesce_done(ctrl->tagset);
363c9aac 4794}
9f27bd70 4795EXPORT_SYMBOL_GPL(nvme_quiesce_io_queues);
363c9aac 4796
9f27bd70 4797void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl)
363c9aac 4798{
ba0718a6
CH		 4799 if (!ctrl->tagset)
4800 return;
98d81f0d
CL		 4801 if (test_and_clear_bit(NVME_CTRL_STOPPED, &ctrl->flags))
4802 blk_mq_unquiesce_tagset(ctrl->tagset);
363c9aac 4803}
9f27bd70 4804EXPORT_SYMBOL_GPL(nvme_unquiesce_io_queues);
363c9aac 4805
9f27bd70 4806void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl)
a277654b 4807{
9e6a6b12
ML		 4808 if (!test_and_set_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags))
4809 blk_mq_quiesce_queue(ctrl->admin_q);
26af1cd0 4810 else
483239c7 4811 blk_mq_wait_quiesce_done(ctrl->admin_q->tag_set);
a277654b 4812}
9f27bd70 4813EXPORT_SYMBOL_GPL(nvme_quiesce_admin_queue);
a277654b 4814
9f27bd70 4815void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl)
a277654b 4816{
9e6a6b12
ML		 4817 if (test_and_clear_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags))
4818 blk_mq_unquiesce_queue(ctrl->admin_q);
a277654b 4819}
9f27bd70 4820EXPORT_SYMBOL_GPL(nvme_unquiesce_admin_queue);
a277654b 4821
04800fbf 4822void nvme_sync_io_queues(struct nvme_ctrl *ctrl)
d6135c3a
KB		 4823{
4824 struct nvme_ns *ns;
be647e2c 4825 int srcu_idx;
d6135c3a 4826
be647e2c
KB		 4827 srcu_idx = srcu_read_lock(&ctrl->srcu);
4828 list_for_each_entry_rcu(ns, &ctrl->namespaces, list)
d6135c3a 4829 blk_sync_queue(ns->queue);
be647e2c 4830 srcu_read_unlock(&ctrl->srcu, srcu_idx);
04800fbf
CL		 4831}
4832EXPORT_SYMBOL_GPL(nvme_sync_io_queues);
03894b7a 4833
04800fbf
CL		 4834void nvme_sync_queues(struct nvme_ctrl *ctrl)
4835{
4836 nvme_sync_io_queues(ctrl);
03894b7a
EN		 4837 if (ctrl->admin_q)
4838 blk_sync_queue(ctrl->admin_q);
d6135c3a
KB		 4839}
4840EXPORT_SYMBOL_GPL(nvme_sync_queues);
4841
b2702aaa 4842struct nvme_ctrl *nvme_ctrl_from_file(struct file *file)
f783f444 4843{
b2702aaa
CK		 4844 if (file->f_op != &nvme_dev_fops)
4845 return NULL;
4846 return file->private_data;
f783f444 4847}
b2702aaa 4848EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, NVME_TARGET_PASSTHRU);
f783f444 4849
81101540
CH		 4850/*
4851 * Check we didn't inadvertently grow the command structure sizes:
4852 */
4853static inline void _nvme_check_size(void)
4854{
4855 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64);
4856 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
4857 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64);
4858 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
4859 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64);
4860 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
4861 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64);
4862 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64);
4863 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
4864 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64);
4865 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
4866 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
4867 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
354201c5
CH		 4868 BUILD_BUG_ON(sizeof(struct nvme_id_ns_cs_indep) !=
4869 NVME_IDENTIFY_DATA_SIZE);
240e6ee2 4870 BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE);
4020aad8 4871 BUILD_BUG_ON(sizeof(struct nvme_id_ns_nvm) != NVME_IDENTIFY_DATA_SIZE);
240e6ee2 4872 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE);
5befc7c2 4873 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_nvm) != NVME_IDENTIFY_DATA_SIZE);
81101540
CH		 4874 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
4875 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
4876 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
4877 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64);
4020aad8 4878 BUILD_BUG_ON(sizeof(struct nvme_feat_host_behavior) != 512);
81101540
CH		 4879}
4880
4881
893a74b7 4882static int __init nvme_core_init(void)
5bae7f73 4883{
b227c59b 4884 int result = -ENOMEM;
5bae7f73 4885
81101540
CH		 4886 _nvme_check_size();
4887
9a6327d2
SG		 4888 nvme_wq = alloc_workqueue("nvme-wq",
4889 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4890 if (!nvme_wq)
b227c59b
RS		 4891 goto out;
4892
4893 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
4894 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4895 if (!nvme_reset_wq)
4896 goto destroy_wq;
4897
4898 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
4899 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4900 if (!nvme_delete_wq)
4901 goto destroy_reset_wq;
9a6327d2 4902
f68abd9c
JG		 4903 result = alloc_chrdev_region(&nvme_ctrl_base_chr_devt, 0,
4904 NVME_MINORS, "nvme");
f3ca80fc 4905 if (result < 0)
b227c59b 4906 goto destroy_delete_wq;
f3ca80fc 4907
ab21f3d9
RM		 4908 result = class_register(&nvme_class);
4909 if (result)
f3ca80fc 4910 goto unregister_chrdev;
f3ca80fc 4911
ab21f3d9
RM		 4912 result = class_register(&nvme_subsys_class);
4913 if (result)
ab9e00cc 4914 goto destroy_class;
2637baed
MI		 4915
4916 result = alloc_chrdev_region(&nvme_ns_chr_devt, 0, NVME_MINORS,
4917 "nvme-generic");
4918 if (result < 0)
4919 goto destroy_subsys_class;
4920
ab21f3d9
RM		 4921 result = class_register(&nvme_ns_chr_class);
4922 if (result)
2637baed 4923 goto unregister_generic_ns;
ab21f3d9 4924
9d77eb52
HR		 4925 result = nvme_init_auth();
4926 if (result)
706add13 4927 goto destroy_ns_chr;
5bae7f73 4928 return 0;
f3ca80fc 4929
e481fc0a 4930destroy_ns_chr:
ab21f3d9 4931 class_unregister(&nvme_ns_chr_class);
2637baed
MI		 4932unregister_generic_ns:
4933 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
4934destroy_subsys_class:
ab21f3d9 4935 class_unregister(&nvme_subsys_class);
ab9e00cc 4936destroy_class:
ab21f3d9 4937 class_unregister(&nvme_class);
9a6327d2 4938unregister_chrdev:
f68abd9c 4939 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS		 4940destroy_delete_wq:
4941 destroy_workqueue(nvme_delete_wq);
4942destroy_reset_wq:
4943 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 4944destroy_wq:
4945 destroy_workqueue(nvme_wq);
b227c59b 4946out:
f3ca80fc 4947 return result;
5bae7f73
CH		 4948}
4949
893a74b7 4950static void __exit nvme_core_exit(void)
5bae7f73 4951{
e481fc0a 4952 nvme_exit_auth();
ab21f3d9
RM		 4953 class_unregister(&nvme_ns_chr_class);
4954 class_unregister(&nvme_subsys_class);
4955 class_unregister(&nvme_class);
2637baed 4956 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
f68abd9c 4957 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS		 4958 destroy_workqueue(nvme_delete_wq);
4959 destroy_workqueue(nvme_reset_wq);
9a6327d2 4960 destroy_workqueue(nvme_wq);
2637baed 4961 ida_destroy(&nvme_ns_chr_minor_ida);
f41cfd5d 4962 ida_destroy(&nvme_instance_ida);
5bae7f73 4963}
576d55d6
ML		 4964
4965MODULE_LICENSE("GPL");
4966MODULE_VERSION("1.0");
92b0b0ff 4967MODULE_DESCRIPTION("NVMe host core framework");
576d55d6
ML		 4968module_init(nvme_core_init);
4969module_exit(nvme_core_exit);
Linux 6.x block layer and io_uring tree(s)