blk-mq: switch ->queue_rq return value to blk_status_t
[linux-block.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH
1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH
21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH
23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH
25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0
CH
30#include <scsi/sg.h>
31#include <asm/unaligned.h>
21d34711
CH
32
33#include "nvme.h"
038bd4cb 34#include "fabrics.h"
21d34711 35
f3ca80fc
CH
36#define NVME_MINORS (1U << MINORBITS)
37
ba0ba7d3
ML
38unsigned char admin_timeout = 60;
39module_param(admin_timeout, byte, 0644);
40MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 41EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3
ML
42
43unsigned char nvme_io_timeout = 30;
44module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
45MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 46EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3
ML
47
48unsigned char shutdown_timeout = 5;
49module_param(shutdown_timeout, byte, 0644);
50MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
51
44e44b29
CH
52static u8 nvme_max_retries = 5;
53module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 54MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 55
f3ca80fc
CH
56static int nvme_char_major;
57module_param(nvme_char_major, int, 0);
58
c5552fde
AL
59static unsigned long default_ps_max_latency_us = 25000;
60module_param(default_ps_max_latency_us, ulong, 0644);
61MODULE_PARM_DESC(default_ps_max_latency_us,
62 "max power saving latency for new devices; use PM QOS to change per device");
63
c35e30b4
AL
64static bool force_apst;
65module_param(force_apst, bool, 0644);
66MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
67
f3ca80fc 68static LIST_HEAD(nvme_ctrl_list);
9f2482b9 69static DEFINE_SPINLOCK(dev_list_lock);
1673f1f0 70
f3ca80fc
CH
71static struct class *nvme_class;
72
2a842aca 73static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH
74{
75 switch (nvme_req(req)->status & 0x7ff) {
76 case NVME_SC_SUCCESS:
2a842aca 77 return BLK_STS_OK;
27fa9bc5 78 case NVME_SC_CAP_EXCEEDED:
2a842aca 79 return BLK_STS_NOSPC;
e02ab023 80 case NVME_SC_ONCS_NOT_SUPPORTED:
2a842aca 81 return BLK_STS_NOTSUPP;
e02ab023
JG
82 case NVME_SC_WRITE_FAULT:
83 case NVME_SC_READ_ERROR:
84 case NVME_SC_UNWRITTEN_BLOCK:
2a842aca
CH
85 return BLK_STS_MEDIUM;
86 default:
87 return BLK_STS_IOERR;
27fa9bc5
CH
88 }
89}
27fa9bc5 90
f6324b1b 91static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 92{
f6324b1b
CH
93 if (blk_noretry_request(req))
94 return false;
27fa9bc5 95 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b
CH
96 return false;
97 if (jiffies - req->start_time >= req->timeout)
98 return false;
44e44b29 99 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH
100 return false;
101 return true;
77f02a7a
CH
102}
103
104void nvme_complete_rq(struct request *req)
105{
27fa9bc5
CH
106 if (unlikely(nvme_req(req)->status && nvme_req_needs_retry(req))) {
107 nvme_req(req)->retries++;
108 blk_mq_requeue_request(req, !blk_mq_queue_stopped(req->q));
109 return;
77f02a7a
CH
110 }
111
27fa9bc5 112 blk_mq_end_request(req, nvme_error_status(req));
77f02a7a
CH
113}
114EXPORT_SYMBOL_GPL(nvme_complete_rq);
115
c55a2fd4
ML
116void nvme_cancel_request(struct request *req, void *data, bool reserved)
117{
118 int status;
119
120 if (!blk_mq_request_started(req))
121 return;
122
123 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
124 "Cancelling I/O %d", req->tag);
125
126 status = NVME_SC_ABORT_REQ;
127 if (blk_queue_dying(req->q))
128 status |= NVME_SC_DNR;
27fa9bc5 129 nvme_req(req)->status = status;
08e0029a 130 blk_mq_complete_request(req);
27fa9bc5 131
c55a2fd4
ML
132}
133EXPORT_SYMBOL_GPL(nvme_cancel_request);
134
bb8d261e
CH
135bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
136 enum nvme_ctrl_state new_state)
137{
f6b6a28e 138 enum nvme_ctrl_state old_state;
bb8d261e
CH
139 bool changed = false;
140
141 spin_lock_irq(&ctrl->lock);
f6b6a28e
GKB
142
143 old_state = ctrl->state;
bb8d261e
CH
144 switch (new_state) {
145 case NVME_CTRL_LIVE:
146 switch (old_state) {
7d2e8008 147 case NVME_CTRL_NEW:
bb8d261e 148 case NVME_CTRL_RESETTING:
def61eca 149 case NVME_CTRL_RECONNECTING:
bb8d261e
CH
150 changed = true;
151 /* FALLTHRU */
152 default:
153 break;
154 }
155 break;
156 case NVME_CTRL_RESETTING:
157 switch (old_state) {
158 case NVME_CTRL_NEW:
def61eca
CH
159 case NVME_CTRL_LIVE:
160 case NVME_CTRL_RECONNECTING:
161 changed = true;
162 /* FALLTHRU */
163 default:
164 break;
165 }
166 break;
167 case NVME_CTRL_RECONNECTING:
168 switch (old_state) {
bb8d261e
CH
169 case NVME_CTRL_LIVE:
170 changed = true;
171 /* FALLTHRU */
172 default:
173 break;
174 }
175 break;
176 case NVME_CTRL_DELETING:
177 switch (old_state) {
178 case NVME_CTRL_LIVE:
179 case NVME_CTRL_RESETTING:
def61eca 180 case NVME_CTRL_RECONNECTING:
bb8d261e
CH
181 changed = true;
182 /* FALLTHRU */
183 default:
184 break;
185 }
186 break;
0ff9d4e1
KB
187 case NVME_CTRL_DEAD:
188 switch (old_state) {
189 case NVME_CTRL_DELETING:
190 changed = true;
191 /* FALLTHRU */
192 default:
193 break;
194 }
195 break;
bb8d261e
CH
196 default:
197 break;
198 }
bb8d261e
CH
199
200 if (changed)
201 ctrl->state = new_state;
202
f6b6a28e
GKB
203 spin_unlock_irq(&ctrl->lock);
204
bb8d261e
CH
205 return changed;
206}
207EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
208
1673f1f0
CH
209static void nvme_free_ns(struct kref *kref)
210{
211 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
212
b0b4e09c
MB
213 if (ns->ndev)
214 nvme_nvm_unregister(ns);
1673f1f0 215
b0b4e09c
MB
216 if (ns->disk) {
217 spin_lock(&dev_list_lock);
218 ns->disk->private_data = NULL;
219 spin_unlock(&dev_list_lock);
220 }
1673f1f0 221
1673f1f0 222 put_disk(ns->disk);
075790eb
KB
223 ida_simple_remove(&ns->ctrl->ns_ida, ns->instance);
224 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH
225 kfree(ns);
226}
227
5bae7f73 228static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH
229{
230 kref_put(&ns->kref, nvme_free_ns);
231}
232
233static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk)
234{
235 struct nvme_ns *ns;
236
237 spin_lock(&dev_list_lock);
238 ns = disk->private_data;
e439bb12
SG
239 if (ns) {
240 if (!kref_get_unless_zero(&ns->kref))
241 goto fail;
242 if (!try_module_get(ns->ctrl->ops->module))
243 goto fail_put_ns;
244 }
1673f1f0
CH
245 spin_unlock(&dev_list_lock);
246
247 return ns;
e439bb12
SG
248
249fail_put_ns:
250 kref_put(&ns->kref, nvme_free_ns);
251fail:
252 spin_unlock(&dev_list_lock);
253 return NULL;
1673f1f0
CH
254}
255
4160982e 256struct request *nvme_alloc_request(struct request_queue *q,
eb71f435 257 struct nvme_command *cmd, unsigned int flags, int qid)
21d34711 258{
aebf526b 259 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 260 struct request *req;
21d34711 261
eb71f435 262 if (qid == NVME_QID_ANY) {
aebf526b 263 req = blk_mq_alloc_request(q, op, flags);
eb71f435 264 } else {
aebf526b 265 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH
266 qid ? qid - 1 : 0);
267 }
21d34711 268 if (IS_ERR(req))
4160982e 269 return req;
21d34711 270
21d34711 271 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 272 nvme_req(req)->cmd = cmd;
21d34711 273
4160982e
CH
274 return req;
275}
576d55d6 276EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 277
8093f7ca
ML
278static inline void nvme_setup_flush(struct nvme_ns *ns,
279 struct nvme_command *cmnd)
280{
281 memset(cmnd, 0, sizeof(*cmnd));
282 cmnd->common.opcode = nvme_cmd_flush;
283 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
284}
285
fc17b653 286static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML
287 struct nvme_command *cmnd)
288{
b35ba01e 289 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 290 struct nvme_dsm_range *range;
b35ba01e 291 struct bio *bio;
8093f7ca 292
b35ba01e 293 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca 294 if (!range)
fc17b653 295 return BLK_STS_RESOURCE;
8093f7ca 296
b35ba01e
CH
297 __rq_for_each_bio(bio, req) {
298 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
299 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
300
301 range[n].cattr = cpu_to_le32(0);
302 range[n].nlb = cpu_to_le32(nlb);
303 range[n].slba = cpu_to_le64(slba);
304 n++;
305 }
306
307 if (WARN_ON_ONCE(n != segments)) {
308 kfree(range);
fc17b653 309 return BLK_STS_IOERR;
b35ba01e 310 }
8093f7ca
ML
311
312 memset(cmnd, 0, sizeof(*cmnd));
313 cmnd->dsm.opcode = nvme_cmd_dsm;
314 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
f1dd03a8 315 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML
316 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
317
f9d03f96
CH
318 req->special_vec.bv_page = virt_to_page(range);
319 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 320 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 321 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 322
fc17b653 323 return BLK_STS_OK;
8093f7ca 324}
8093f7ca 325
8093f7ca
ML
326static inline void nvme_setup_rw(struct nvme_ns *ns, struct request *req,
327 struct nvme_command *cmnd)
328{
329 u16 control = 0;
330 u32 dsmgmt = 0;
331
332 if (req->cmd_flags & REQ_FUA)
333 control |= NVME_RW_FUA;
334 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
335 control |= NVME_RW_LR;
336
337 if (req->cmd_flags & REQ_RAHEAD)
338 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
339
340 memset(cmnd, 0, sizeof(*cmnd));
341 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
8093f7ca
ML
342 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
343 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
344 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
345
346 if (ns->ms) {
347 switch (ns->pi_type) {
348 case NVME_NS_DPS_PI_TYPE3:
349 control |= NVME_RW_PRINFO_PRCHK_GUARD;
350 break;
351 case NVME_NS_DPS_PI_TYPE1:
352 case NVME_NS_DPS_PI_TYPE2:
353 control |= NVME_RW_PRINFO_PRCHK_GUARD |
354 NVME_RW_PRINFO_PRCHK_REF;
355 cmnd->rw.reftag = cpu_to_le32(
356 nvme_block_nr(ns, blk_rq_pos(req)));
357 break;
358 }
359 if (!blk_integrity_rq(req))
360 control |= NVME_RW_PRINFO_PRACT;
361 }
362
363 cmnd->rw.control = cpu_to_le16(control);
364 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
365}
366
fc17b653 367blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML
368 struct nvme_command *cmd)
369{
fc17b653 370 blk_status_t ret = BLK_STS_OK;
8093f7ca 371
987f699a 372 if (!(req->rq_flags & RQF_DONTPREP)) {
44e44b29 373 nvme_req(req)->retries = 0;
27fa9bc5 374 nvme_req(req)->flags = 0;
987f699a
CH
375 req->rq_flags |= RQF_DONTPREP;
376 }
377
aebf526b
CH
378 switch (req_op(req)) {
379 case REQ_OP_DRV_IN:
380 case REQ_OP_DRV_OUT:
d49187e9 381 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH
382 break;
383 case REQ_OP_FLUSH:
8093f7ca 384 nvme_setup_flush(ns, cmd);
aebf526b 385 break;
e850fd16
CH
386 case REQ_OP_WRITE_ZEROES:
387 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 388 case REQ_OP_DISCARD:
8093f7ca 389 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH
390 break;
391 case REQ_OP_READ:
392 case REQ_OP_WRITE:
8093f7ca 393 nvme_setup_rw(ns, req, cmd);
aebf526b
CH
394 break;
395 default:
396 WARN_ON_ONCE(1);
fc17b653 397 return BLK_STS_IOERR;
aebf526b 398 }
8093f7ca 399
721b3917 400 cmd->common.command_id = req->tag;
8093f7ca
ML
401 return ret;
402}
403EXPORT_SYMBOL_GPL(nvme_setup_cmd);
404
4160982e
CH
405/*
406 * Returns 0 on success. If the result is negative, it's a Linux error code;
407 * if the result is positive, it's an NVM Express status code
408 */
409int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 410 union nvme_result *result, void *buffer, unsigned bufflen,
eb71f435 411 unsigned timeout, int qid, int at_head, int flags)
4160982e
CH
412{
413 struct request *req;
414 int ret;
415
eb71f435 416 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH
417 if (IS_ERR(req))
418 return PTR_ERR(req);
419
420 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
421
21d34711
CH
422 if (buffer && bufflen) {
423 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
424 if (ret)
425 goto out;
4160982e
CH
426 }
427
eb71f435 428 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH
429 if (result)
430 *result = nvme_req(req)->result;
27fa9bc5
CH
431 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
432 ret = -EINTR;
433 else
434 ret = nvme_req(req)->status;
4160982e
CH
435 out:
436 blk_mq_free_request(req);
437 return ret;
438}
eb71f435 439EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH
440
441int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
442 void *buffer, unsigned bufflen)
443{
eb71f435
CH
444 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
445 NVME_QID_ANY, 0, 0);
4160982e 446}
576d55d6 447EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 448
0b7f1f26
KB
449int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
450 void __user *ubuffer, unsigned bufflen,
451 void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
452 u32 *result, unsigned timeout)
4160982e 453{
7a5abb4b 454 bool write = nvme_is_write(cmd);
0b7f1f26
KB
455 struct nvme_ns *ns = q->queuedata;
456 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 457 struct request *req;
0b7f1f26
KB
458 struct bio *bio = NULL;
459 void *meta = NULL;
4160982e
CH
460 int ret;
461
eb71f435 462 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH
463 if (IS_ERR(req))
464 return PTR_ERR(req);
465
466 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
467
468 if (ubuffer && bufflen) {
21d34711
CH
469 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
470 GFP_KERNEL);
471 if (ret)
472 goto out;
473 bio = req->bio;
21d34711 474
0b7f1f26
KB
475 if (!disk)
476 goto submit;
477 bio->bi_bdev = bdget_disk(disk, 0);
478 if (!bio->bi_bdev) {
479 ret = -ENODEV;
480 goto out_unmap;
481 }
482
e9fc63d6 483 if (meta_buffer && meta_len) {
0b7f1f26
KB
484 struct bio_integrity_payload *bip;
485
486 meta = kmalloc(meta_len, GFP_KERNEL);
487 if (!meta) {
488 ret = -ENOMEM;
489 goto out_unmap;
490 }
491
492 if (write) {
493 if (copy_from_user(meta, meta_buffer,
494 meta_len)) {
495 ret = -EFAULT;
496 goto out_free_meta;
497 }
498 }
499
500 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
06c1e390
KB
501 if (IS_ERR(bip)) {
502 ret = PTR_ERR(bip);
0b7f1f26
KB
503 goto out_free_meta;
504 }
505
506 bip->bip_iter.bi_size = meta_len;
507 bip->bip_iter.bi_sector = meta_seed;
508
509 ret = bio_integrity_add_page(bio, virt_to_page(meta),
510 meta_len, offset_in_page(meta));
511 if (ret != meta_len) {
512 ret = -ENOMEM;
513 goto out_free_meta;
514 }
515 }
516 }
517 submit:
518 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH
519 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
520 ret = -EINTR;
521 else
522 ret = nvme_req(req)->status;
21d34711 523 if (result)
d49187e9 524 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB
525 if (meta && !ret && !write) {
526 if (copy_to_user(meta_buffer, meta, meta_len))
527 ret = -EFAULT;
528 }
529 out_free_meta:
530 kfree(meta);
531 out_unmap:
532 if (bio) {
533 if (disk && bio->bi_bdev)
534 bdput(bio->bi_bdev);
535 blk_rq_unmap_user(bio);
536 }
21d34711
CH
537 out:
538 blk_mq_free_request(req);
539 return ret;
540}
541
0b7f1f26
KB
542int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
543 void __user *ubuffer, unsigned bufflen, u32 *result,
544 unsigned timeout)
545{
546 return __nvme_submit_user_cmd(q, cmd, ubuffer, bufflen, NULL, 0, 0,
547 result, timeout);
548}
549
2a842aca 550static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG
551{
552 struct nvme_ctrl *ctrl = rq->end_io_data;
553
554 blk_mq_free_request(rq);
555
2a842aca 556 if (status) {
038bd4cb 557 dev_err(ctrl->device,
2a842aca
CH
558 "failed nvme_keep_alive_end_io error=%d\n",
559 status);
038bd4cb
SG
560 return;
561 }
562
563 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
564}
565
566static int nvme_keep_alive(struct nvme_ctrl *ctrl)
567{
568 struct nvme_command c;
569 struct request *rq;
570
571 memset(&c, 0, sizeof(c));
572 c.common.opcode = nvme_admin_keep_alive;
573
574 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
575 NVME_QID_ANY);
576 if (IS_ERR(rq))
577 return PTR_ERR(rq);
578
579 rq->timeout = ctrl->kato * HZ;
580 rq->end_io_data = ctrl;
581
582 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
583
584 return 0;
585}
586
587static void nvme_keep_alive_work(struct work_struct *work)
588{
589 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
590 struct nvme_ctrl, ka_work);
591
592 if (nvme_keep_alive(ctrl)) {
593 /* allocation failure, reset the controller */
594 dev_err(ctrl->device, "keep-alive failed\n");
595 ctrl->ops->reset_ctrl(ctrl);
596 return;
597 }
598}
599
600void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
601{
602 if (unlikely(ctrl->kato == 0))
603 return;
604
605 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
606 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
607}
608EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
609
610void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
611{
612 if (unlikely(ctrl->kato == 0))
613 return;
614
615 cancel_delayed_work_sync(&ctrl->ka_work);
616}
617EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
618
1c63dc66 619int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH
620{
621 struct nvme_command c = { };
622 int error;
623
624 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
625 c.identify.opcode = nvme_admin_identify;
986994a2 626 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH
627
628 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
629 if (!*id)
630 return -ENOMEM;
631
632 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
633 sizeof(struct nvme_id_ctrl));
634 if (error)
635 kfree(*id);
636 return error;
637}
638
540c801c
KB
639static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
640{
641 struct nvme_command c = { };
642
643 c.identify.opcode = nvme_admin_identify;
986994a2 644 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c
KB
645 c.identify.nsid = cpu_to_le32(nsid);
646 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
647}
648
1c63dc66 649int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
21d34711
CH
650 struct nvme_id_ns **id)
651{
652 struct nvme_command c = { };
653 int error;
654
655 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG
656 c.identify.opcode = nvme_admin_identify;
657 c.identify.nsid = cpu_to_le32(nsid);
986994a2 658 c.identify.cns = NVME_ID_CNS_NS;
21d34711
CH
659
660 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
661 if (!*id)
662 return -ENOMEM;
663
664 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
665 sizeof(struct nvme_id_ns));
666 if (error)
667 kfree(*id);
668 return error;
669}
670
1c63dc66 671int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
1a6fe74d 672 void *buffer, size_t buflen, u32 *result)
21d34711
CH
673{
674 struct nvme_command c;
d49187e9 675 union nvme_result res;
1cb3cce5 676 int ret;
21d34711
CH
677
678 memset(&c, 0, sizeof(c));
679 c.features.opcode = nvme_admin_get_features;
680 c.features.nsid = cpu_to_le32(nsid);
21d34711
CH
681 c.features.fid = cpu_to_le32(fid);
682
d49187e9 683 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res, buffer, buflen, 0,
eb71f435 684 NVME_QID_ANY, 0, 0);
9b47f77a 685 if (ret >= 0 && result)
d49187e9 686 *result = le32_to_cpu(res.u32);
1cb3cce5 687 return ret;
21d34711
CH
688}
689
1c63dc66 690int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 691 void *buffer, size_t buflen, u32 *result)
21d34711
CH
692{
693 struct nvme_command c;
d49187e9 694 union nvme_result res;
1cb3cce5 695 int ret;
21d34711
CH
696
697 memset(&c, 0, sizeof(c));
698 c.features.opcode = nvme_admin_set_features;
21d34711
CH
699 c.features.fid = cpu_to_le32(fid);
700 c.features.dword11 = cpu_to_le32(dword11);
701
d49187e9 702 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 703 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 704 if (ret >= 0 && result)
d49187e9 705 *result = le32_to_cpu(res.u32);
1cb3cce5 706 return ret;
21d34711
CH
707}
708
1c63dc66 709int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log)
21d34711
CH
710{
711 struct nvme_command c = { };
712 int error;
713
714 c.common.opcode = nvme_admin_get_log_page,
715 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
716 c.common.cdw10[0] = cpu_to_le32(
717 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
718 NVME_LOG_SMART),
719
720 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
721 if (!*log)
722 return -ENOMEM;
723
724 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
725 sizeof(struct nvme_smart_log));
726 if (error)
727 kfree(*log);
728 return error;
729}
1673f1f0 730
9a0be7ab
CH
731int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
732{
733 u32 q_count = (*count - 1) | ((*count - 1) << 16);
734 u32 result;
735 int status, nr_io_queues;
736
1a6fe74d 737 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 738 &result);
f5fa90dc 739 if (status < 0)
9a0be7ab
CH
740 return status;
741
f5fa90dc
CH
742 /*
743 * Degraded controllers might return an error when setting the queue
744 * count. We still want to be able to bring them online and offer
745 * access to the admin queue, as that might be only way to fix them up.
746 */
747 if (status > 0) {
748 dev_err(ctrl->dev, "Could not set queue count (%d)\n", status);
749 *count = 0;
750 } else {
751 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
752 *count = min(*count, nr_io_queues);
753 }
754
9a0be7ab
CH
755 return 0;
756}
576d55d6 757EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 758
1673f1f0
CH
759static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
760{
761 struct nvme_user_io io;
762 struct nvme_command c;
763 unsigned length, meta_len;
764 void __user *metadata;
765
766 if (copy_from_user(&io, uio, sizeof(io)))
767 return -EFAULT;
63088ec7
KB
768 if (io.flags)
769 return -EINVAL;
1673f1f0
CH
770
771 switch (io.opcode) {
772 case nvme_cmd_write:
773 case nvme_cmd_read:
774 case nvme_cmd_compare:
775 break;
776 default:
777 return -EINVAL;
778 }
779
780 length = (io.nblocks + 1) << ns->lba_shift;
781 meta_len = (io.nblocks + 1) * ns->ms;
782 metadata = (void __user *)(uintptr_t)io.metadata;
783
784 if (ns->ext) {
785 length += meta_len;
786 meta_len = 0;
787 } else if (meta_len) {
788 if ((io.metadata & 3) || !io.metadata)
789 return -EINVAL;
790 }
791
792 memset(&c, 0, sizeof(c));
793 c.rw.opcode = io.opcode;
794 c.rw.flags = io.flags;
795 c.rw.nsid = cpu_to_le32(ns->ns_id);
796 c.rw.slba = cpu_to_le64(io.slba);
797 c.rw.length = cpu_to_le16(io.nblocks);
798 c.rw.control = cpu_to_le16(io.control);
799 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
800 c.rw.reftag = cpu_to_le32(io.reftag);
801 c.rw.apptag = cpu_to_le16(io.apptag);
802 c.rw.appmask = cpu_to_le16(io.appmask);
803
804 return __nvme_submit_user_cmd(ns->queue, &c,
805 (void __user *)(uintptr_t)io.addr, length,
806 metadata, meta_len, io.slba, NULL, 0);
807}
808
f3ca80fc 809static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH
810 struct nvme_passthru_cmd __user *ucmd)
811{
812 struct nvme_passthru_cmd cmd;
813 struct nvme_command c;
814 unsigned timeout = 0;
815 int status;
816
817 if (!capable(CAP_SYS_ADMIN))
818 return -EACCES;
819 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
820 return -EFAULT;
63088ec7
KB
821 if (cmd.flags)
822 return -EINVAL;
1673f1f0
CH
823
824 memset(&c, 0, sizeof(c));
825 c.common.opcode = cmd.opcode;
826 c.common.flags = cmd.flags;
827 c.common.nsid = cpu_to_le32(cmd.nsid);
828 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
829 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
830 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
831 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
832 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
833 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
834 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
835 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
836
837 if (cmd.timeout_ms)
838 timeout = msecs_to_jiffies(cmd.timeout_ms);
839
840 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 841 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1673f1f0
CH
842 &cmd.result, timeout);
843 if (status >= 0) {
844 if (put_user(cmd.result, &ucmd->result))
845 return -EFAULT;
846 }
847
848 return status;
849}
850
851static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
852 unsigned int cmd, unsigned long arg)
853{
854 struct nvme_ns *ns = bdev->bd_disk->private_data;
855
856 switch (cmd) {
857 case NVME_IOCTL_ID:
858 force_successful_syscall_return();
859 return ns->ns_id;
860 case NVME_IOCTL_ADMIN_CMD:
861 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
862 case NVME_IOCTL_IO_CMD:
863 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
864 case NVME_IOCTL_SUBMIT_IO:
865 return nvme_submit_io(ns, (void __user *)arg);
44907332 866#ifdef CONFIG_BLK_DEV_NVME_SCSI
1673f1f0
CH
867 case SG_GET_VERSION_NUM:
868 return nvme_sg_get_version_num((void __user *)arg);
869 case SG_IO:
870 return nvme_sg_io(ns, (void __user *)arg);
44907332 871#endif
1673f1f0 872 default:
84d4add7
MB
873#ifdef CONFIG_NVM
874 if (ns->ndev)
875 return nvme_nvm_ioctl(ns, cmd, arg);
876#endif
a98e58e5 877 if (is_sed_ioctl(cmd))
4f1244c8 878 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 879 (void __user *) arg);
1673f1f0
CH
880 return -ENOTTY;
881 }
882}
883
884#ifdef CONFIG_COMPAT
885static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
886 unsigned int cmd, unsigned long arg)
887{
888 switch (cmd) {
889 case SG_IO:
890 return -ENOIOCTLCMD;
891 }
892 return nvme_ioctl(bdev, mode, cmd, arg);
893}
894#else
895#define nvme_compat_ioctl NULL
896#endif
897
898static int nvme_open(struct block_device *bdev, fmode_t mode)
899{
900 return nvme_get_ns_from_disk(bdev->bd_disk) ? 0 : -ENXIO;
901}
902
903static void nvme_release(struct gendisk *disk, fmode_t mode)
904{
e439bb12
SG
905 struct nvme_ns *ns = disk->private_data;
906
907 module_put(ns->ctrl->ops->module);
908 nvme_put_ns(ns);
1673f1f0
CH
909}
910
911static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
912{
913 /* some standard values */
914 geo->heads = 1 << 6;
915 geo->sectors = 1 << 5;
916 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
917 return 0;
918}
919
920#ifdef CONFIG_BLK_DEV_INTEGRITY
c81bfba9
CH
921static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
922 u16 bs)
923{
924 struct nvme_ns *ns = disk->private_data;
925 u16 old_ms = ns->ms;
926 u8 pi_type = 0;
927
928 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
929 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
930
931 /* PI implementation requires metadata equal t10 pi tuple size */
932 if (ns->ms == sizeof(struct t10_pi_tuple))
933 pi_type = id->dps & NVME_NS_DPS_PI_MASK;
934
935 if (blk_get_integrity(disk) &&
936 (ns->pi_type != pi_type || ns->ms != old_ms ||
937 bs != queue_logical_block_size(disk->queue) ||
938 (ns->ms && ns->ext)))
939 blk_integrity_unregister(disk);
940
941 ns->pi_type = pi_type;
942}
943
1673f1f0
CH
944static void nvme_init_integrity(struct nvme_ns *ns)
945{
946 struct blk_integrity integrity;
947
fa9a89fc 948 memset(&integrity, 0, sizeof(integrity));
1673f1f0
CH
949 switch (ns->pi_type) {
950 case NVME_NS_DPS_PI_TYPE3:
951 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB
952 integrity.tag_size = sizeof(u16) + sizeof(u32);
953 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH
954 break;
955 case NVME_NS_DPS_PI_TYPE1:
956 case NVME_NS_DPS_PI_TYPE2:
957 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB
958 integrity.tag_size = sizeof(u16);
959 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH
960 break;
961 default:
962 integrity.profile = NULL;
963 break;
964 }
965 integrity.tuple_size = ns->ms;
966 blk_integrity_register(ns->disk, &integrity);
967 blk_queue_max_integrity_segments(ns->queue, 1);
968}
969#else
c81bfba9
CH
970static void nvme_prep_integrity(struct gendisk *disk, struct nvme_id_ns *id,
971 u16 bs)
972{
973}
1673f1f0
CH
974static void nvme_init_integrity(struct nvme_ns *ns)
975{
976}
977#endif /* CONFIG_BLK_DEV_INTEGRITY */
978
979static void nvme_config_discard(struct nvme_ns *ns)
980{
08095e70 981 struct nvme_ctrl *ctrl = ns->ctrl;
1673f1f0 982 u32 logical_block_size = queue_logical_block_size(ns->queue);
08095e70 983
b35ba01e
CH
984 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
985 NVME_DSM_MAX_RANGES);
986
1673f1f0
CH
987 ns->queue->limits.discard_alignment = logical_block_size;
988 ns->queue->limits.discard_granularity = logical_block_size;
bd0fc288 989 blk_queue_max_discard_sectors(ns->queue, UINT_MAX);
b35ba01e 990 blk_queue_max_discard_segments(ns->queue, NVME_DSM_MAX_RANGES);
1673f1f0 991 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
e850fd16
CH
992
993 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
994 blk_queue_max_write_zeroes_sectors(ns->queue, UINT_MAX);
1673f1f0
CH
995}
996
ac81bfa9 997static int nvme_revalidate_ns(struct nvme_ns *ns, struct nvme_id_ns **id)
1673f1f0 998{
ac81bfa9 999 if (nvme_identify_ns(ns->ctrl, ns->ns_id, id)) {
b0b4e09c 1000 dev_warn(ns->ctrl->dev, "%s: Identify failure\n", __func__);
1673f1f0
CH
1001 return -ENODEV;
1002 }
1673f1f0 1003
ac81bfa9
MB
1004 if ((*id)->ncap == 0) {
1005 kfree(*id);
1006 return -ENODEV;
1673f1f0
CH
1007 }
1008
8ef2074d 1009 if (ns->ctrl->vs >= NVME_VS(1, 1, 0))
ac81bfa9 1010 memcpy(ns->eui, (*id)->eui64, sizeof(ns->eui));
8ef2074d 1011 if (ns->ctrl->vs >= NVME_VS(1, 2, 0))
ac81bfa9
MB
1012 memcpy(ns->uuid, (*id)->nguid, sizeof(ns->uuid));
1013
1014 return 0;
1015}
1016
1017static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1018{
1019 struct nvme_ns *ns = disk->private_data;
c81bfba9 1020 u16 bs;
1673f1f0
CH
1021
1022 /*
1023 * If identify namespace failed, use default 512 byte block size so
1024 * block layer can use before failing read/write for 0 capacity.
1025 */
c81bfba9 1026 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH
1027 if (ns->lba_shift == 0)
1028 ns->lba_shift = 9;
1029 bs = 1 << ns->lba_shift;
1673f1f0
CH
1030
1031 blk_mq_freeze_queue(disk->queue);
1673f1f0 1032
c81bfba9
CH
1033 if (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED)
1034 nvme_prep_integrity(disk, id, bs);
1673f1f0 1035 blk_queue_logical_block_size(ns->queue, bs);
4b9d5b15 1036 if (ns->ms && !blk_get_integrity(disk) && !ns->ext)
1673f1f0 1037 nvme_init_integrity(ns);
1673f1f0
CH
1038 if (ns->ms && !(ns->ms == 8 && ns->pi_type) && !blk_get_integrity(disk))
1039 set_capacity(disk, 0);
1040 else
1041 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1042
1043 if (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)
1044 nvme_config_discard(ns);
1045 blk_mq_unfreeze_queue(disk->queue);
ac81bfa9 1046}
1673f1f0 1047
ac81bfa9
MB
1048static int nvme_revalidate_disk(struct gendisk *disk)
1049{
1050 struct nvme_ns *ns = disk->private_data;
1051 struct nvme_id_ns *id = NULL;
1052 int ret;
1053
1054 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1055 set_capacity(disk, 0);
1056 return -ENODEV;
1057 }
1058
1059 ret = nvme_revalidate_ns(ns, &id);
1060 if (ret)
1061 return ret;
1062
1063 __nvme_revalidate_disk(disk, id);
1673f1f0 1064 kfree(id);
ac81bfa9 1065
1673f1f0
CH
1066 return 0;
1067}
1068
1069static char nvme_pr_type(enum pr_type type)
1070{
1071 switch (type) {
1072 case PR_WRITE_EXCLUSIVE:
1073 return 1;
1074 case PR_EXCLUSIVE_ACCESS:
1075 return 2;
1076 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1077 return 3;
1078 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1079 return 4;
1080 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1081 return 5;
1082 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1083 return 6;
1084 default:
1085 return 0;
1086 }
1087};
1088
1089static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1090 u64 key, u64 sa_key, u8 op)
1091{
1092 struct nvme_ns *ns = bdev->bd_disk->private_data;
1093 struct nvme_command c;
1094 u8 data[16] = { 0, };
1095
1096 put_unaligned_le64(key, &data[0]);
1097 put_unaligned_le64(sa_key, &data[8]);
1098
1099 memset(&c, 0, sizeof(c));
1100 c.common.opcode = op;
1101 c.common.nsid = cpu_to_le32(ns->ns_id);
1102 c.common.cdw10[0] = cpu_to_le32(cdw10);
1103
1104 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
1105}
1106
1107static int nvme_pr_register(struct block_device *bdev, u64 old,
1108 u64 new, unsigned flags)
1109{
1110 u32 cdw10;
1111
1112 if (flags & ~PR_FL_IGNORE_KEY)
1113 return -EOPNOTSUPP;
1114
1115 cdw10 = old ? 2 : 0;
1116 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1117 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1118 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1119}
1120
1121static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1122 enum pr_type type, unsigned flags)
1123{
1124 u32 cdw10;
1125
1126 if (flags & ~PR_FL_IGNORE_KEY)
1127 return -EOPNOTSUPP;
1128
1129 cdw10 = nvme_pr_type(type) << 8;
1130 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1131 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1132}
1133
1134static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1135 enum pr_type type, bool abort)
1136{
1137 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1138 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1139}
1140
1141static int nvme_pr_clear(struct block_device *bdev, u64 key)
1142{
8c0b3915 1143 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH
1144 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1145}
1146
1147static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1148{
1149 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1150 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1151}
1152
1153static const struct pr_ops nvme_pr_ops = {
1154 .pr_register = nvme_pr_register,
1155 .pr_reserve = nvme_pr_reserve,
1156 .pr_release = nvme_pr_release,
1157 .pr_preempt = nvme_pr_preempt,
1158 .pr_clear = nvme_pr_clear,
1159};
1160
a98e58e5 1161#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH
1162int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1163 bool send)
a98e58e5 1164{
4f1244c8 1165 struct nvme_ctrl *ctrl = data;
a98e58e5 1166 struct nvme_command cmd;
a98e58e5
SB
1167
1168 memset(&cmd, 0, sizeof(cmd));
1169 if (send)
1170 cmd.common.opcode = nvme_admin_security_send;
1171 else
1172 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB
1173 cmd.common.nsid = 0;
1174 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1175 cmd.common.cdw10[1] = cpu_to_le32(len);
1176
1177 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1178 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1179}
1180EXPORT_SYMBOL_GPL(nvme_sec_submit);
1181#endif /* CONFIG_BLK_SED_OPAL */
1182
5bae7f73 1183static const struct block_device_operations nvme_fops = {
1673f1f0
CH
1184 .owner = THIS_MODULE,
1185 .ioctl = nvme_ioctl,
1186 .compat_ioctl = nvme_compat_ioctl,
1187 .open = nvme_open,
1188 .release = nvme_release,
1189 .getgeo = nvme_getgeo,
1190 .revalidate_disk= nvme_revalidate_disk,
1191 .pr_ops = &nvme_pr_ops,
1192};
1193
5fd4ce1b
CH
1194static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1195{
1196 unsigned long timeout =
1197 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1198 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1199 int ret;
1200
1201 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB
1202 if (csts == ~0)
1203 return -ENODEV;
5fd4ce1b
CH
1204 if ((csts & NVME_CSTS_RDY) == bit)
1205 break;
1206
1207 msleep(100);
1208 if (fatal_signal_pending(current))
1209 return -EINTR;
1210 if (time_after(jiffies, timeout)) {
1b3c47c1 1211 dev_err(ctrl->device,
5fd4ce1b
CH
1212 "Device not ready; aborting %s\n", enabled ?
1213 "initialisation" : "reset");
1214 return -ENODEV;
1215 }
1216 }
1217
1218 return ret;
1219}
1220
1221/*
1222 * If the device has been passed off to us in an enabled state, just clear
1223 * the enabled bit. The spec says we should set the 'shutdown notification
1224 * bits', but doing so may cause the device to complete commands to the
1225 * admin queue ... and we don't know what memory that might be pointing at!
1226 */
1227int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1228{
1229 int ret;
1230
1231 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1232 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1233
1234 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1235 if (ret)
1236 return ret;
54adc010 1237
b5a10c5f 1238 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP
1239 msleep(NVME_QUIRK_DELAY_AMOUNT);
1240
5fd4ce1b
CH
1241 return nvme_wait_ready(ctrl, cap, false);
1242}
576d55d6 1243EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH
1244
1245int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1246{
1247 /*
1248 * Default to a 4K page size, with the intention to update this
1249 * path in the future to accomodate architectures with differing
1250 * kernel and IO page sizes.
1251 */
1252 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1253 int ret;
1254
1255 if (page_shift < dev_page_min) {
1b3c47c1 1256 dev_err(ctrl->device,
5fd4ce1b
CH
1257 "Minimum device page size %u too large for host (%u)\n",
1258 1 << dev_page_min, 1 << page_shift);
1259 return -ENODEV;
1260 }
1261
1262 ctrl->page_size = 1 << page_shift;
1263
1264 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1265 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1266 ctrl->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1267 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1268 ctrl->ctrl_config |= NVME_CC_ENABLE;
1269
1270 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1271 if (ret)
1272 return ret;
1273 return nvme_wait_ready(ctrl, cap, true);
1274}
576d55d6 1275EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH
1276
1277int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1278{
1279 unsigned long timeout = SHUTDOWN_TIMEOUT + jiffies;
1280 u32 csts;
1281 int ret;
1282
1283 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1284 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1285
1286 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1287 if (ret)
1288 return ret;
1289
1290 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1291 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1292 break;
1293
1294 msleep(100);
1295 if (fatal_signal_pending(current))
1296 return -EINTR;
1297 if (time_after(jiffies, timeout)) {
1b3c47c1 1298 dev_err(ctrl->device,
5fd4ce1b
CH
1299 "Device shutdown incomplete; abort shutdown\n");
1300 return -ENODEV;
1301 }
1302 }
1303
1304 return ret;
1305}
576d55d6 1306EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1307
da35825d
CH
1308static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1309 struct request_queue *q)
1310{
7c88cb00
JA
1311 bool vwc = false;
1312
da35825d 1313 if (ctrl->max_hw_sectors) {
45686b61
CH
1314 u32 max_segments =
1315 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1316
da35825d 1317 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1318 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1319 }
e6282aef
KB
1320 if (ctrl->quirks & NVME_QUIRK_STRIPE_SIZE)
1321 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1322 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA
1323 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1324 vwc = true;
1325 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH
1326}
1327
c5552fde
AL
1328static void nvme_configure_apst(struct nvme_ctrl *ctrl)
1329{
1330 /*
1331 * APST (Autonomous Power State Transition) lets us program a
1332 * table of power state transitions that the controller will
1333 * perform automatically. We configure it with a simple
1334 * heuristic: we are willing to spend at most 2% of the time
1335 * transitioning between power states. Therefore, when running
1336 * in any given state, we will enter the next lower-power
76e4ad09 1337 * non-operational state after waiting 50 * (enlat + exlat)
c5552fde
AL
1338 * microseconds, as long as that state's total latency is under
1339 * the requested maximum latency.
1340 *
1341 * We will not autonomously enter any non-operational state for
1342 * which the total latency exceeds ps_max_latency_us. Users
1343 * can set ps_max_latency_us to zero to turn off APST.
1344 */
1345
1346 unsigned apste;
1347 struct nvme_feat_auto_pst *table;
fb0dc399
AL
1348 u64 max_lat_us = 0;
1349 int max_ps = -1;
c5552fde
AL
1350 int ret;
1351
1352 /*
1353 * If APST isn't supported or if we haven't been initialized yet,
1354 * then don't do anything.
1355 */
1356 if (!ctrl->apsta)
1357 return;
1358
1359 if (ctrl->npss > 31) {
1360 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
1361 return;
1362 }
1363
1364 table = kzalloc(sizeof(*table), GFP_KERNEL);
1365 if (!table)
1366 return;
1367
1368 if (ctrl->ps_max_latency_us == 0) {
1369 /* Turn off APST. */
1370 apste = 0;
fb0dc399 1371 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL
1372 } else {
1373 __le64 target = cpu_to_le64(0);
1374 int state;
1375
1376 /*
1377 * Walk through all states from lowest- to highest-power.
1378 * According to the spec, lower-numbered states use more
1379 * power. NPSS, despite the name, is the index of the
1380 * lowest-power state, not the number of states.
1381 */
1382 for (state = (int)ctrl->npss; state >= 0; state--) {
1383 u64 total_latency_us, transition_ms;
1384
1385 if (target)
1386 table->entries[state] = target;
1387
ff5350a8
AL
1388 /*
1389 * Don't allow transitions to the deepest state
1390 * if it's quirked off.
1391 */
1392 if (state == ctrl->npss &&
1393 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1394 continue;
1395
c5552fde
AL
1396 /*
1397 * Is this state a useful non-operational state for
1398 * higher-power states to autonomously transition to?
1399 */
1400 if (!(ctrl->psd[state].flags &
1401 NVME_PS_FLAGS_NON_OP_STATE))
1402 continue;
1403
1404 total_latency_us =
1405 (u64)le32_to_cpu(ctrl->psd[state].entry_lat) +
1406 + le32_to_cpu(ctrl->psd[state].exit_lat);
1407 if (total_latency_us > ctrl->ps_max_latency_us)
1408 continue;
1409
1410 /*
1411 * This state is good. Use it as the APST idle
1412 * target for higher power states.
1413 */
1414 transition_ms = total_latency_us + 19;
1415 do_div(transition_ms, 20);
1416 if (transition_ms > (1 << 24) - 1)
1417 transition_ms = (1 << 24) - 1;
1418
1419 target = cpu_to_le64((state << 3) |
1420 (transition_ms << 8));
fb0dc399
AL
1421
1422 if (max_ps == -1)
1423 max_ps = state;
1424
1425 if (total_latency_us > max_lat_us)
1426 max_lat_us = total_latency_us;
c5552fde
AL
1427 }
1428
1429 apste = 1;
fb0dc399
AL
1430
1431 if (max_ps == -1) {
1432 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1433 } else {
1434 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1435 max_ps, max_lat_us, (int)sizeof(*table), table);
1436 }
c5552fde
AL
1437 }
1438
1439 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1440 table, sizeof(*table), NULL);
1441 if (ret)
1442 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1443
1444 kfree(table);
1445}
1446
1447static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1448{
1449 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1450 u64 latency;
1451
1452 switch (val) {
1453 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1454 case PM_QOS_LATENCY_ANY:
1455 latency = U64_MAX;
1456 break;
1457
1458 default:
1459 latency = val;
1460 }
1461
1462 if (ctrl->ps_max_latency_us != latency) {
1463 ctrl->ps_max_latency_us = latency;
1464 nvme_configure_apst(ctrl);
1465 }
1466}
1467
bd4da3ab
AL
1468struct nvme_core_quirk_entry {
1469 /*
1470 * NVMe model and firmware strings are padded with spaces. For
1471 * simplicity, strings in the quirk table are padded with NULLs
1472 * instead.
1473 */
1474 u16 vid;
1475 const char *mn;
1476 const char *fr;
1477 unsigned long quirks;
1478};
1479
1480static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1481 {
be56945c
AL
1482 /*
1483 * This Toshiba device seems to die using any APST states. See:
1484 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1485 */
1486 .vid = 0x1179,
1487 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1488 .quirks = NVME_QUIRK_NO_APST,
be56945c 1489 }
bd4da3ab
AL
1490};
1491
1492/* match is null-terminated but idstr is space-padded. */
1493static bool string_matches(const char *idstr, const char *match, size_t len)
1494{
1495 size_t matchlen;
1496
1497 if (!match)
1498 return true;
1499
1500 matchlen = strlen(match);
1501 WARN_ON_ONCE(matchlen > len);
1502
1503 if (memcmp(idstr, match, matchlen))
1504 return false;
1505
1506 for (; matchlen < len; matchlen++)
1507 if (idstr[matchlen] != ' ')
1508 return false;
1509
1510 return true;
1511}
1512
1513static bool quirk_matches(const struct nvme_id_ctrl *id,
1514 const struct nvme_core_quirk_entry *q)
1515{
1516 return q->vid == le16_to_cpu(id->vid) &&
1517 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1518 string_matches(id->fr, q->fr, sizeof(id->fr));
1519}
1520
7fd8930f
CH
1521/*
1522 * Initialize the cached copies of the Identify data and various controller
1523 * register in our nvme_ctrl structure. This should be called as soon as
1524 * the admin queue is fully up and running.
1525 */
1526int nvme_init_identify(struct nvme_ctrl *ctrl)
1527{
1528 struct nvme_id_ctrl *id;
1529 u64 cap;
1530 int ret, page_shift;
a229dbf6 1531 u32 max_hw_sectors;
c5552fde 1532 u8 prev_apsta;
7fd8930f 1533
f3ca80fc
CH
1534 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
1535 if (ret) {
1b3c47c1 1536 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH
1537 return ret;
1538 }
1539
7fd8930f
CH
1540 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
1541 if (ret) {
1b3c47c1 1542 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH
1543 return ret;
1544 }
1545 page_shift = NVME_CAP_MPSMIN(cap) + 12;
1546
8ef2074d 1547 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH
1548 ctrl->subsystem = NVME_CAP_NSSRC(cap);
1549
7fd8930f
CH
1550 ret = nvme_identify_ctrl(ctrl, &id);
1551 if (ret) {
1b3c47c1 1552 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH
1553 return -EIO;
1554 }
1555
bd4da3ab
AL
1556 if (!ctrl->identified) {
1557 /*
1558 * Check for quirks. Quirk can depend on firmware version,
1559 * so, in principle, the set of quirks present can change
1560 * across a reset. As a possible future enhancement, we
1561 * could re-scan for quirks every time we reinitialize
1562 * the device, but we'd have to make sure that the driver
1563 * behaves intelligently if the quirks change.
1564 */
1565
1566 int i;
1567
1568 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
1569 if (quirk_matches(id, &core_quirks[i]))
1570 ctrl->quirks |= core_quirks[i].quirks;
1571 }
1572 }
1573
c35e30b4
AL
1574 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
1575 dev_warn(ctrl->dev, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
1576 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
1577 }
1578
8a9ae523 1579 ctrl->oacs = le16_to_cpu(id->oacs);
118472ab 1580 ctrl->vid = le16_to_cpu(id->vid);
7fd8930f 1581 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 1582 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 1583 ctrl->vwc = id->vwc;
931e1c22 1584 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f
CH
1585 memcpy(ctrl->serial, id->sn, sizeof(id->sn));
1586 memcpy(ctrl->model, id->mn, sizeof(id->mn));
1587 memcpy(ctrl->firmware_rev, id->fr, sizeof(id->fr));
1588 if (id->mdts)
a229dbf6 1589 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 1590 else
a229dbf6
CH
1591 max_hw_sectors = UINT_MAX;
1592 ctrl->max_hw_sectors =
1593 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 1594
da35825d 1595 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 1596 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 1597 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 1598
c5552fde
AL
1599 ctrl->npss = id->npss;
1600 prev_apsta = ctrl->apsta;
c35e30b4
AL
1601 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
1602 if (force_apst && id->apsta) {
1603 dev_warn(ctrl->dev, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
1604 ctrl->apsta = 1;
1605 } else {
1606 ctrl->apsta = 0;
1607 }
1608 } else {
1609 ctrl->apsta = id->apsta;
1610 }
c5552fde
AL
1611 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
1612
d3d5b87d 1613 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH
1614 ctrl->icdoff = le16_to_cpu(id->icdoff);
1615 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
1616 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
1617 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
1618
1619 /*
1620 * In fabrics we need to verify the cntlid matches the
1621 * admin connect
1622 */
1623 if (ctrl->cntlid != le16_to_cpu(id->cntlid))
1624 ret = -EINVAL;
038bd4cb
SG
1625
1626 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
1627 dev_err(ctrl->dev,
1628 "keep-alive support is mandatory for fabrics\n");
1629 ret = -EINVAL;
1630 }
07bfcd09
CH
1631 } else {
1632 ctrl->cntlid = le16_to_cpu(id->cntlid);
1633 }
da35825d 1634
7fd8930f 1635 kfree(id);
bd4da3ab 1636
c5552fde
AL
1637 if (ctrl->apsta && !prev_apsta)
1638 dev_pm_qos_expose_latency_tolerance(ctrl->device);
1639 else if (!ctrl->apsta && prev_apsta)
1640 dev_pm_qos_hide_latency_tolerance(ctrl->device);
1641
1642 nvme_configure_apst(ctrl);
1643
bd4da3ab 1644 ctrl->identified = true;
c5552fde 1645
07bfcd09 1646 return ret;
7fd8930f 1647}
576d55d6 1648EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 1649
f3ca80fc 1650static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 1651{
f3ca80fc
CH
1652 struct nvme_ctrl *ctrl;
1653 int instance = iminor(inode);
1654 int ret = -ENODEV;
1673f1f0 1655
f3ca80fc
CH
1656 spin_lock(&dev_list_lock);
1657 list_for_each_entry(ctrl, &nvme_ctrl_list, node) {
1658 if (ctrl->instance != instance)
1659 continue;
1660
1661 if (!ctrl->admin_q) {
1662 ret = -EWOULDBLOCK;
1663 break;
1664 }
1665 if (!kref_get_unless_zero(&ctrl->kref))
1666 break;
1667 file->private_data = ctrl;
1668 ret = 0;
1669 break;
1670 }
1671 spin_unlock(&dev_list_lock);
1672
1673 return ret;
1673f1f0
CH
1674}
1675
f3ca80fc 1676static int nvme_dev_release(struct inode *inode, struct file *file)
1673f1f0 1677{
f3ca80fc
CH
1678 nvme_put_ctrl(file->private_data);
1679 return 0;
1680}
1681
bfd89471
CH
1682static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
1683{
1684 struct nvme_ns *ns;
1685 int ret;
1686
1687 mutex_lock(&ctrl->namespaces_mutex);
1688 if (list_empty(&ctrl->namespaces)) {
1689 ret = -ENOTTY;
1690 goto out_unlock;
1691 }
1692
1693 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
1694 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 1695 dev_warn(ctrl->device,
bfd89471
CH
1696 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
1697 ret = -EINVAL;
1698 goto out_unlock;
1699 }
1700
1b3c47c1 1701 dev_warn(ctrl->device,
bfd89471
CH
1702 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
1703 kref_get(&ns->kref);
1704 mutex_unlock(&ctrl->namespaces_mutex);
1705
1706 ret = nvme_user_cmd(ctrl, ns, argp);
1707 nvme_put_ns(ns);
1708 return ret;
1709
1710out_unlock:
1711 mutex_unlock(&ctrl->namespaces_mutex);
1712 return ret;
1713}
1714
f3ca80fc
CH
1715static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
1716 unsigned long arg)
1717{
1718 struct nvme_ctrl *ctrl = file->private_data;
1719 void __user *argp = (void __user *)arg;
f3ca80fc
CH
1720
1721 switch (cmd) {
1722 case NVME_IOCTL_ADMIN_CMD:
1723 return nvme_user_cmd(ctrl, NULL, argp);
1724 case NVME_IOCTL_IO_CMD:
bfd89471 1725 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 1726 case NVME_IOCTL_RESET:
1b3c47c1 1727 dev_warn(ctrl->device, "resetting controller\n");
f3ca80fc
CH
1728 return ctrl->ops->reset_ctrl(ctrl);
1729 case NVME_IOCTL_SUBSYS_RESET:
1730 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB
1731 case NVME_IOCTL_RESCAN:
1732 nvme_queue_scan(ctrl);
1733 return 0;
f3ca80fc
CH
1734 default:
1735 return -ENOTTY;
1736 }
1737}
1738
1739static const struct file_operations nvme_dev_fops = {
1740 .owner = THIS_MODULE,
1741 .open = nvme_dev_open,
1742 .release = nvme_dev_release,
1743 .unlocked_ioctl = nvme_dev_ioctl,
1744 .compat_ioctl = nvme_dev_ioctl,
1745};
1746
1747static ssize_t nvme_sysfs_reset(struct device *dev,
1748 struct device_attribute *attr, const char *buf,
1749 size_t count)
1750{
1751 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1752 int ret;
1753
1754 ret = ctrl->ops->reset_ctrl(ctrl);
1755 if (ret < 0)
1756 return ret;
1757 return count;
1673f1f0 1758}
f3ca80fc 1759static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 1760
9ec3bb2f
KB
1761static ssize_t nvme_sysfs_rescan(struct device *dev,
1762 struct device_attribute *attr, const char *buf,
1763 size_t count)
1764{
1765 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1766
1767 nvme_queue_scan(ctrl);
1768 return count;
1769}
1770static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
1771
118472ab
KB
1772static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
1773 char *buf)
1774{
40267efd 1775 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
118472ab
KB
1776 struct nvme_ctrl *ctrl = ns->ctrl;
1777 int serial_len = sizeof(ctrl->serial);
1778 int model_len = sizeof(ctrl->model);
1779
1780 if (memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1781 return sprintf(buf, "eui.%16phN\n", ns->uuid);
1782
1783 if (memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1784 return sprintf(buf, "eui.%8phN\n", ns->eui);
1785
1786 while (ctrl->serial[serial_len - 1] == ' ')
1787 serial_len--;
1788 while (ctrl->model[model_len - 1] == ' ')
1789 model_len--;
1790
1791 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", ctrl->vid,
1792 serial_len, ctrl->serial, model_len, ctrl->model, ns->ns_id);
1793}
1794static DEVICE_ATTR(wwid, S_IRUGO, wwid_show, NULL);
1795
2b9b6e86
KB
1796static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
1797 char *buf)
1798{
40267efd 1799 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB
1800 return sprintf(buf, "%pU\n", ns->uuid);
1801}
1802static DEVICE_ATTR(uuid, S_IRUGO, uuid_show, NULL);
1803
1804static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
1805 char *buf)
1806{
40267efd 1807 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB
1808 return sprintf(buf, "%8phd\n", ns->eui);
1809}
1810static DEVICE_ATTR(eui, S_IRUGO, eui_show, NULL);
1811
1812static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
1813 char *buf)
1814{
40267efd 1815 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB
1816 return sprintf(buf, "%d\n", ns->ns_id);
1817}
1818static DEVICE_ATTR(nsid, S_IRUGO, nsid_show, NULL);
1819
1820static struct attribute *nvme_ns_attrs[] = {
118472ab 1821 &dev_attr_wwid.attr,
2b9b6e86
KB
1822 &dev_attr_uuid.attr,
1823 &dev_attr_eui.attr,
1824 &dev_attr_nsid.attr,
1825 NULL,
1826};
1827
1a353d85 1828static umode_t nvme_ns_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB
1829 struct attribute *a, int n)
1830{
1831 struct device *dev = container_of(kobj, struct device, kobj);
40267efd 1832 struct nvme_ns *ns = nvme_get_ns_from_dev(dev);
2b9b6e86
KB
1833
1834 if (a == &dev_attr_uuid.attr) {
1835 if (!memchr_inv(ns->uuid, 0, sizeof(ns->uuid)))
1836 return 0;
1837 }
1838 if (a == &dev_attr_eui.attr) {
1839 if (!memchr_inv(ns->eui, 0, sizeof(ns->eui)))
1840 return 0;
1841 }
1842 return a->mode;
1843}
1844
1845static const struct attribute_group nvme_ns_attr_group = {
1846 .attrs = nvme_ns_attrs,
1a353d85 1847 .is_visible = nvme_ns_attrs_are_visible,
2b9b6e86
KB
1848};
1849
931e1c22 1850#define nvme_show_str_function(field) \
779ff756
KB
1851static ssize_t field##_show(struct device *dev, \
1852 struct device_attribute *attr, char *buf) \
1853{ \
1854 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1855 return sprintf(buf, "%.*s\n", (int)sizeof(ctrl->field), ctrl->field); \
1856} \
1857static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1858
931e1c22
ML
1859#define nvme_show_int_function(field) \
1860static ssize_t field##_show(struct device *dev, \
1861 struct device_attribute *attr, char *buf) \
1862{ \
1863 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
1864 return sprintf(buf, "%d\n", ctrl->field); \
1865} \
1866static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
1867
1868nvme_show_str_function(model);
1869nvme_show_str_function(serial);
1870nvme_show_str_function(firmware_rev);
1871nvme_show_int_function(cntlid);
779ff756 1872
1a353d85
ML
1873static ssize_t nvme_sysfs_delete(struct device *dev,
1874 struct device_attribute *attr, const char *buf,
1875 size_t count)
1876{
1877 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1878
1879 if (device_remove_file_self(dev, attr))
1880 ctrl->ops->delete_ctrl(ctrl);
1881 return count;
1882}
1883static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
1884
1885static ssize_t nvme_sysfs_show_transport(struct device *dev,
1886 struct device_attribute *attr,
1887 char *buf)
1888{
1889 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1890
1891 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
1892}
1893static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
1894
8432bdb2
SG
1895static ssize_t nvme_sysfs_show_state(struct device *dev,
1896 struct device_attribute *attr,
1897 char *buf)
1898{
1899 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1900 static const char *const state_name[] = {
1901 [NVME_CTRL_NEW] = "new",
1902 [NVME_CTRL_LIVE] = "live",
1903 [NVME_CTRL_RESETTING] = "resetting",
1904 [NVME_CTRL_RECONNECTING]= "reconnecting",
1905 [NVME_CTRL_DELETING] = "deleting",
1906 [NVME_CTRL_DEAD] = "dead",
1907 };
1908
1909 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
1910 state_name[ctrl->state])
1911 return sprintf(buf, "%s\n", state_name[ctrl->state]);
1912
1913 return sprintf(buf, "unknown state\n");
1914}
1915
1916static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
1917
1a353d85
ML
1918static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
1919 struct device_attribute *attr,
1920 char *buf)
1921{
1922 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1923
1924 return snprintf(buf, PAGE_SIZE, "%s\n",
1925 ctrl->ops->get_subsysnqn(ctrl));
1926}
1927static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
1928
1929static ssize_t nvme_sysfs_show_address(struct device *dev,
1930 struct device_attribute *attr,
1931 char *buf)
1932{
1933 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1934
1935 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
1936}
1937static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
1938
779ff756
KB
1939static struct attribute *nvme_dev_attrs[] = {
1940 &dev_attr_reset_controller.attr,
9ec3bb2f 1941 &dev_attr_rescan_controller.attr,
779ff756
KB
1942 &dev_attr_model.attr,
1943 &dev_attr_serial.attr,
1944 &dev_attr_firmware_rev.attr,
931e1c22 1945 &dev_attr_cntlid.attr,
1a353d85
ML
1946 &dev_attr_delete_controller.attr,
1947 &dev_attr_transport.attr,
1948 &dev_attr_subsysnqn.attr,
1949 &dev_attr_address.attr,
8432bdb2 1950 &dev_attr_state.attr,
779ff756
KB
1951 NULL
1952};
1953
1a353d85
ML
1954#define CHECK_ATTR(ctrl, a, name) \
1955 if ((a) == &dev_attr_##name.attr && \
1956 !(ctrl)->ops->get_##name) \
1957 return 0
1958
1959static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
1960 struct attribute *a, int n)
1961{
1962 struct device *dev = container_of(kobj, struct device, kobj);
1963 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1964
1965 if (a == &dev_attr_delete_controller.attr) {
1966 if (!ctrl->ops->delete_ctrl)
1967 return 0;
1968 }
1969
1970 CHECK_ATTR(ctrl, a, subsysnqn);
1971 CHECK_ATTR(ctrl, a, address);
1972
1973 return a->mode;
1974}
1975
779ff756 1976static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML
1977 .attrs = nvme_dev_attrs,
1978 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB
1979};
1980
1981static const struct attribute_group *nvme_dev_attr_groups[] = {
1982 &nvme_dev_attrs_group,
1983 NULL,
1984};
1985
5bae7f73
CH
1986static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
1987{
1988 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
1989 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
1990
1991 return nsa->ns_id - nsb->ns_id;
1992}
1993
32f0c4af 1994static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 1995{
32f0c4af 1996 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 1997
32f0c4af 1998 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 1999 list_for_each_entry(ns, &ctrl->namespaces, list) {
32f0c4af
KB
2000 if (ns->ns_id == nsid) {
2001 kref_get(&ns->kref);
2002 ret = ns;
2003 break;
2004 }
5bae7f73
CH
2005 if (ns->ns_id > nsid)
2006 break;
2007 }
32f0c4af
KB
2008 mutex_unlock(&ctrl->namespaces_mutex);
2009 return ret;
5bae7f73
CH
2010}
2011
2012static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2013{
2014 struct nvme_ns *ns;
2015 struct gendisk *disk;
ac81bfa9
MB
2016 struct nvme_id_ns *id;
2017 char disk_name[DISK_NAME_LEN];
5bae7f73
CH
2018 int node = dev_to_node(ctrl->dev);
2019
2020 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2021 if (!ns)
2022 return;
2023
075790eb
KB
2024 ns->instance = ida_simple_get(&ctrl->ns_ida, 1, 0, GFP_KERNEL);
2025 if (ns->instance < 0)
2026 goto out_free_ns;
2027
5bae7f73
CH
2028 ns->queue = blk_mq_init_queue(ctrl->tagset);
2029 if (IS_ERR(ns->queue))
075790eb 2030 goto out_release_instance;
5bae7f73
CH
2031 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2032 ns->queue->queuedata = ns;
2033 ns->ctrl = ctrl;
2034
5bae7f73
CH
2035 kref_init(&ns->kref);
2036 ns->ns_id = nsid;
5bae7f73 2037 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH
2038
2039 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 2040 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 2041
ac81bfa9 2042 sprintf(disk_name, "nvme%dn%d", ctrl->instance, ns->instance);
5bae7f73 2043
ac81bfa9
MB
2044 if (nvme_revalidate_ns(ns, &id))
2045 goto out_free_queue;
2046
3dc87dd0
MB
2047 if (nvme_nvm_ns_supported(ns, id) &&
2048 nvme_nvm_register(ns, disk_name, node)) {
2049 dev_warn(ctrl->dev, "%s: LightNVM init failure\n", __func__);
2050 goto out_free_id;
2051 }
ac81bfa9 2052
3dc87dd0
MB
2053 disk = alloc_disk_node(0, node);
2054 if (!disk)
2055 goto out_free_id;
ac81bfa9 2056
3dc87dd0
MB
2057 disk->fops = &nvme_fops;
2058 disk->private_data = ns;
2059 disk->queue = ns->queue;
2060 disk->flags = GENHD_FL_EXT_DEVT;
2061 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
2062 ns->disk = disk;
2063
2064 __nvme_revalidate_disk(disk, id);
5bae7f73 2065
32f0c4af
KB
2066 mutex_lock(&ctrl->namespaces_mutex);
2067 list_add_tail(&ns->list, &ctrl->namespaces);
2068 mutex_unlock(&ctrl->namespaces_mutex);
2069
5bae7f73 2070 kref_get(&ctrl->kref);
ac81bfa9
MB
2071
2072 kfree(id);
2073
0d52c756 2074 device_add_disk(ctrl->device, ns->disk);
2b9b6e86
KB
2075 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
2076 &nvme_ns_attr_group))
2077 pr_warn("%s: failed to create sysfs group for identification\n",
2078 ns->disk->disk_name);
3dc87dd0
MB
2079 if (ns->ndev && nvme_nvm_register_sysfs(ns))
2080 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
2081 ns->disk->disk_name);
5bae7f73 2082 return;
ac81bfa9
MB
2083 out_free_id:
2084 kfree(id);
5bae7f73
CH
2085 out_free_queue:
2086 blk_cleanup_queue(ns->queue);
075790eb
KB
2087 out_release_instance:
2088 ida_simple_remove(&ctrl->ns_ida, ns->instance);
5bae7f73
CH
2089 out_free_ns:
2090 kfree(ns);
2091}
2092
2093static void nvme_ns_remove(struct nvme_ns *ns)
2094{
646017a6
KB
2095 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
2096 return;
69d3b8ac 2097
b0b4e09c 2098 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73
CH
2099 if (blk_get_integrity(ns->disk))
2100 blk_integrity_unregister(ns->disk);
2b9b6e86
KB
2101 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
2102 &nvme_ns_attr_group);
3dc87dd0
MB
2103 if (ns->ndev)
2104 nvme_nvm_unregister_sysfs(ns);
5bae7f73 2105 del_gendisk(ns->disk);
5bae7f73
CH
2106 blk_cleanup_queue(ns->queue);
2107 }
32f0c4af
KB
2108
2109 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 2110 list_del_init(&ns->list);
32f0c4af
KB
2111 mutex_unlock(&ns->ctrl->namespaces_mutex);
2112
5bae7f73
CH
2113 nvme_put_ns(ns);
2114}
2115
540c801c
KB
2116static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2117{
2118 struct nvme_ns *ns;
2119
32f0c4af 2120 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 2121 if (ns) {
b0b4e09c 2122 if (ns->disk && revalidate_disk(ns->disk))
540c801c 2123 nvme_ns_remove(ns);
32f0c4af 2124 nvme_put_ns(ns);
540c801c
KB
2125 } else
2126 nvme_alloc_ns(ctrl, nsid);
2127}
2128
47b0e50a
SB
2129static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
2130 unsigned nsid)
2131{
2132 struct nvme_ns *ns, *next;
2133
2134 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
2135 if (ns->ns_id > nsid)
2136 nvme_ns_remove(ns);
2137 }
2138}
2139
540c801c
KB
2140static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
2141{
2142 struct nvme_ns *ns;
2143 __le32 *ns_list;
2144 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
2145 int ret = 0;
2146
2147 ns_list = kzalloc(0x1000, GFP_KERNEL);
2148 if (!ns_list)
2149 return -ENOMEM;
2150
2151 for (i = 0; i < num_lists; i++) {
2152 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
2153 if (ret)
47b0e50a 2154 goto free;
540c801c
KB
2155
2156 for (j = 0; j < min(nn, 1024U); j++) {
2157 nsid = le32_to_cpu(ns_list[j]);
2158 if (!nsid)
2159 goto out;
2160
2161 nvme_validate_ns(ctrl, nsid);
2162
2163 while (++prev < nsid) {
32f0c4af
KB
2164 ns = nvme_find_get_ns(ctrl, prev);
2165 if (ns) {
540c801c 2166 nvme_ns_remove(ns);
32f0c4af
KB
2167 nvme_put_ns(ns);
2168 }
540c801c
KB
2169 }
2170 }
2171 nn -= j;
2172 }
2173 out:
47b0e50a
SB
2174 nvme_remove_invalid_namespaces(ctrl, prev);
2175 free:
540c801c
KB
2176 kfree(ns_list);
2177 return ret;
2178}
2179
5955be21 2180static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 2181{
5bae7f73
CH
2182 unsigned i;
2183
540c801c
KB
2184 for (i = 1; i <= nn; i++)
2185 nvme_validate_ns(ctrl, i);
2186
47b0e50a 2187 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH
2188}
2189
5955be21 2190static void nvme_scan_work(struct work_struct *work)
5bae7f73 2191{
5955be21
CH
2192 struct nvme_ctrl *ctrl =
2193 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 2194 struct nvme_id_ctrl *id;
540c801c 2195 unsigned nn;
5bae7f73 2196
5955be21
CH
2197 if (ctrl->state != NVME_CTRL_LIVE)
2198 return;
2199
5bae7f73
CH
2200 if (nvme_identify_ctrl(ctrl, &id))
2201 return;
540c801c
KB
2202
2203 nn = le32_to_cpu(id->nn);
8ef2074d 2204 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB
2205 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
2206 if (!nvme_scan_ns_list(ctrl, nn))
2207 goto done;
2208 }
5955be21 2209 nvme_scan_ns_sequential(ctrl, nn);
540c801c 2210 done:
32f0c4af 2211 mutex_lock(&ctrl->namespaces_mutex);
540c801c 2212 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 2213 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH
2214 kfree(id);
2215}
5955be21
CH
2216
2217void nvme_queue_scan(struct nvme_ctrl *ctrl)
2218{
2219 /*
2220 * Do not queue new scan work when a controller is reset during
2221 * removal.
2222 */
2223 if (ctrl->state == NVME_CTRL_LIVE)
2224 schedule_work(&ctrl->scan_work);
2225}
2226EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 2227
32f0c4af
KB
2228/*
2229 * This function iterates the namespace list unlocked to allow recovery from
2230 * controller failure. It is up to the caller to ensure the namespace list is
2231 * not modified by scan work while this function is executing.
2232 */
5bae7f73
CH
2233void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
2234{
2235 struct nvme_ns *ns, *next;
2236
0ff9d4e1
KB
2237 /*
2238 * The dead states indicates the controller was not gracefully
2239 * disconnected. In that case, we won't be able to flush any data while
2240 * removing the namespaces' disks; fail all the queues now to avoid
2241 * potentially having to clean up the failed sync later.
2242 */
2243 if (ctrl->state == NVME_CTRL_DEAD)
2244 nvme_kill_queues(ctrl);
2245
5bae7f73
CH
2246 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
2247 nvme_ns_remove(ns);
2248}
576d55d6 2249EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 2250
f866fc42
CH
2251static void nvme_async_event_work(struct work_struct *work)
2252{
2253 struct nvme_ctrl *ctrl =
2254 container_of(work, struct nvme_ctrl, async_event_work);
2255
2256 spin_lock_irq(&ctrl->lock);
2257 while (ctrl->event_limit > 0) {
2258 int aer_idx = --ctrl->event_limit;
2259
2260 spin_unlock_irq(&ctrl->lock);
2261 ctrl->ops->submit_async_event(ctrl, aer_idx);
2262 spin_lock_irq(&ctrl->lock);
2263 }
2264 spin_unlock_irq(&ctrl->lock);
2265}
2266
7bf58533
CH
2267void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
2268 union nvme_result *res)
f866fc42 2269{
7bf58533
CH
2270 u32 result = le32_to_cpu(res->u32);
2271 bool done = true;
f866fc42 2272
7bf58533
CH
2273 switch (le16_to_cpu(status) >> 1) {
2274 case NVME_SC_SUCCESS:
2275 done = false;
2276 /*FALLTHRU*/
2277 case NVME_SC_ABORT_REQ:
f866fc42
CH
2278 ++ctrl->event_limit;
2279 schedule_work(&ctrl->async_event_work);
7bf58533
CH
2280 break;
2281 default:
2282 break;
f866fc42
CH
2283 }
2284
7bf58533 2285 if (done)
f866fc42
CH
2286 return;
2287
2288 switch (result & 0xff07) {
2289 case NVME_AER_NOTICE_NS_CHANGED:
2290 dev_info(ctrl->device, "rescanning\n");
2291 nvme_queue_scan(ctrl);
2292 break;
2293 default:
2294 dev_warn(ctrl->device, "async event result %08x\n", result);
2295 }
2296}
2297EXPORT_SYMBOL_GPL(nvme_complete_async_event);
2298
2299void nvme_queue_async_events(struct nvme_ctrl *ctrl)
2300{
2301 ctrl->event_limit = NVME_NR_AERS;
2302 schedule_work(&ctrl->async_event_work);
2303}
2304EXPORT_SYMBOL_GPL(nvme_queue_async_events);
2305
f3ca80fc
CH
2306static DEFINE_IDA(nvme_instance_ida);
2307
2308static int nvme_set_instance(struct nvme_ctrl *ctrl)
2309{
2310 int instance, error;
2311
2312 do {
2313 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2314 return -ENODEV;
2315
2316 spin_lock(&dev_list_lock);
2317 error = ida_get_new(&nvme_instance_ida, &instance);
2318 spin_unlock(&dev_list_lock);
2319 } while (error == -EAGAIN);
2320
2321 if (error)
2322 return -ENODEV;
2323
2324 ctrl->instance = instance;
2325 return 0;
2326}
2327
2328static void nvme_release_instance(struct nvme_ctrl *ctrl)
2329{
2330 spin_lock(&dev_list_lock);
2331 ida_remove(&nvme_instance_ida, ctrl->instance);
2332 spin_unlock(&dev_list_lock);
2333}
2334
53029b04 2335void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
576d55d6 2336{
f866fc42 2337 flush_work(&ctrl->async_event_work);
5955be21
CH
2338 flush_work(&ctrl->scan_work);
2339 nvme_remove_namespaces(ctrl);
2340
53029b04 2341 device_destroy(nvme_class, MKDEV(nvme_char_major, ctrl->instance));
f3ca80fc
CH
2342
2343 spin_lock(&dev_list_lock);
2344 list_del(&ctrl->node);
2345 spin_unlock(&dev_list_lock);
53029b04 2346}
576d55d6 2347EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04
KB
2348
2349static void nvme_free_ctrl(struct kref *kref)
2350{
2351 struct nvme_ctrl *ctrl = container_of(kref, struct nvme_ctrl, kref);
f3ca80fc
CH
2352
2353 put_device(ctrl->device);
2354 nvme_release_instance(ctrl);
075790eb 2355 ida_destroy(&ctrl->ns_ida);
f3ca80fc
CH
2356
2357 ctrl->ops->free_ctrl(ctrl);
2358}
2359
2360void nvme_put_ctrl(struct nvme_ctrl *ctrl)
2361{
2362 kref_put(&ctrl->kref, nvme_free_ctrl);
2363}
576d55d6 2364EXPORT_SYMBOL_GPL(nvme_put_ctrl);
f3ca80fc
CH
2365
2366/*
2367 * Initialize a NVMe controller structures. This needs to be called during
2368 * earliest initialization so that we have the initialized structured around
2369 * during probing.
2370 */
2371int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
2372 const struct nvme_ctrl_ops *ops, unsigned long quirks)
2373{
2374 int ret;
2375
bb8d261e
CH
2376 ctrl->state = NVME_CTRL_NEW;
2377 spin_lock_init(&ctrl->lock);
f3ca80fc 2378 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 2379 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH
2380 kref_init(&ctrl->kref);
2381 ctrl->dev = dev;
2382 ctrl->ops = ops;
2383 ctrl->quirks = quirks;
5955be21 2384 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 2385 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
f3ca80fc
CH
2386
2387 ret = nvme_set_instance(ctrl);
2388 if (ret)
2389 goto out;
2390
779ff756 2391 ctrl->device = device_create_with_groups(nvme_class, ctrl->dev,
f3ca80fc 2392 MKDEV(nvme_char_major, ctrl->instance),
f4f0f63e 2393 ctrl, nvme_dev_attr_groups,
779ff756 2394 "nvme%d", ctrl->instance);
f3ca80fc
CH
2395 if (IS_ERR(ctrl->device)) {
2396 ret = PTR_ERR(ctrl->device);
2397 goto out_release_instance;
2398 }
2399 get_device(ctrl->device);
075790eb 2400 ida_init(&ctrl->ns_ida);
f3ca80fc 2401
f3ca80fc
CH
2402 spin_lock(&dev_list_lock);
2403 list_add_tail(&ctrl->node, &nvme_ctrl_list);
2404 spin_unlock(&dev_list_lock);
2405
c5552fde
AL
2406 /*
2407 * Initialize latency tolerance controls. The sysfs files won't
2408 * be visible to userspace unless the device actually supports APST.
2409 */
2410 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
2411 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
2412 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
2413
f3ca80fc 2414 return 0;
f3ca80fc
CH
2415out_release_instance:
2416 nvme_release_instance(ctrl);
2417out:
2418 return ret;
2419}
576d55d6 2420EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 2421
69d9a99c
KB
2422/**
2423 * nvme_kill_queues(): Ends all namespace queues
2424 * @ctrl: the dead controller that needs to end
2425 *
2426 * Call this function when the driver determines it is unable to get the
2427 * controller in a state capable of servicing IO.
2428 */
2429void nvme_kill_queues(struct nvme_ctrl *ctrl)
2430{
2431 struct nvme_ns *ns;
2432
32f0c4af
KB
2433 mutex_lock(&ctrl->namespaces_mutex);
2434 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB
2435 /*
2436 * Revalidating a dead namespace sets capacity to 0. This will
2437 * end buffered writers dirtying pages that can't be synced.
2438 */
f33447b9
KB
2439 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
2440 continue;
2441 revalidate_disk(ns->disk);
69d9a99c 2442 blk_set_queue_dying(ns->queue);
806f026f
ML
2443
2444 /*
2445 * Forcibly start all queues to avoid having stuck requests.
2446 * Note that we must ensure the queues are not stopped
2447 * when the final removal happens.
2448 */
2449 blk_mq_start_hw_queues(ns->queue);
986f75c8
ML
2450
2451 /* draining requests in requeue list */
2452 blk_mq_kick_requeue_list(ns->queue);
69d9a99c 2453 }
32f0c4af 2454 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 2455}
237045fc 2456EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 2457
302ad8cc
KB
2458void nvme_unfreeze(struct nvme_ctrl *ctrl)
2459{
2460 struct nvme_ns *ns;
2461
2462 mutex_lock(&ctrl->namespaces_mutex);
2463 list_for_each_entry(ns, &ctrl->namespaces, list)
2464 blk_mq_unfreeze_queue(ns->queue);
2465 mutex_unlock(&ctrl->namespaces_mutex);
2466}
2467EXPORT_SYMBOL_GPL(nvme_unfreeze);
2468
2469void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
2470{
2471 struct nvme_ns *ns;
2472
2473 mutex_lock(&ctrl->namespaces_mutex);
2474 list_for_each_entry(ns, &ctrl->namespaces, list) {
2475 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
2476 if (timeout <= 0)
2477 break;
2478 }
2479 mutex_unlock(&ctrl->namespaces_mutex);
2480}
2481EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
2482
2483void nvme_wait_freeze(struct nvme_ctrl *ctrl)
2484{
2485 struct nvme_ns *ns;
2486
2487 mutex_lock(&ctrl->namespaces_mutex);
2488 list_for_each_entry(ns, &ctrl->namespaces, list)
2489 blk_mq_freeze_queue_wait(ns->queue);
2490 mutex_unlock(&ctrl->namespaces_mutex);
2491}
2492EXPORT_SYMBOL_GPL(nvme_wait_freeze);
2493
2494void nvme_start_freeze(struct nvme_ctrl *ctrl)
2495{
2496 struct nvme_ns *ns;
2497
2498 mutex_lock(&ctrl->namespaces_mutex);
2499 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 2500 blk_freeze_queue_start(ns->queue);
302ad8cc
KB
2501 mutex_unlock(&ctrl->namespaces_mutex);
2502}
2503EXPORT_SYMBOL_GPL(nvme_start_freeze);
2504
25646264 2505void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG
2506{
2507 struct nvme_ns *ns;
2508
32f0c4af 2509 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 2510 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 2511 blk_mq_quiesce_queue(ns->queue);
32f0c4af 2512 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2513}
576d55d6 2514EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 2515
25646264 2516void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG
2517{
2518 struct nvme_ns *ns;
2519
32f0c4af
KB
2520 mutex_lock(&ctrl->namespaces_mutex);
2521 list_for_each_entry(ns, &ctrl->namespaces, list) {
363c9aac
SG
2522 blk_mq_start_stopped_hw_queues(ns->queue, true);
2523 blk_mq_kick_requeue_list(ns->queue);
2524 }
32f0c4af 2525 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 2526}
576d55d6 2527EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 2528
5bae7f73
CH
2529int __init nvme_core_init(void)
2530{
2531 int result;
2532
f3ca80fc
CH
2533 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
2534 &nvme_dev_fops);
2535 if (result < 0)
b09dcf58 2536 return result;
f3ca80fc
CH
2537 else if (result > 0)
2538 nvme_char_major = result;
2539
2540 nvme_class = class_create(THIS_MODULE, "nvme");
2541 if (IS_ERR(nvme_class)) {
2542 result = PTR_ERR(nvme_class);
2543 goto unregister_chrdev;
2544 }
2545
5bae7f73 2546 return 0;
f3ca80fc
CH
2547
2548 unregister_chrdev:
2549 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
f3ca80fc 2550 return result;
5bae7f73
CH
2551}
2552
2553void nvme_core_exit(void)
2554{
f3ca80fc
CH
2555 class_destroy(nvme_class);
2556 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
5bae7f73 2557}
576d55d6
ML
2558
2559MODULE_LICENSE("GPL");
2560MODULE_VERSION("1.0");
2561module_init(nvme_core_init);
2562module_exit(nvme_core_exit);