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block: move ref_tag calculation func to the block layer
[linux-2.6-block.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0 30#include <asm/unaligned.h>
21d34711 31
3d030e41
JT		 32#define CREATE_TRACE_POINTS
33#include "trace.h"
34
21d34711 35#include "nvme.h"
038bd4cb 36#include "fabrics.h"
21d34711 37
f3ca80fc
CH		 38#define NVME_MINORS (1U << MINORBITS)
39
8ae4e447
MO		 40unsigned int admin_timeout = 60;
41module_param(admin_timeout, uint, 0644);
ba0ba7d3 42MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 43EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 44
8ae4e447
MO		 45unsigned int nvme_io_timeout = 30;
46module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 47MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 48EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 49
b3b1b0b0 50static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 51module_param(shutdown_timeout, byte, 0644);
52MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
53
44e44b29
CH		 54static u8 nvme_max_retries = 5;
55module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 56MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 57
9947d6a0 58static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 59module_param(default_ps_max_latency_us, ulong, 0644);
60MODULE_PARM_DESC(default_ps_max_latency_us,
61 "max power saving latency for new devices; use PM QOS to change per device");
62
c35e30b4
AL		 63static bool force_apst;
64module_param(force_apst, bool, 0644);
65MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
66
f5d11840
JA		 67static bool streams;
68module_param(streams, bool, 0644);
69MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
70
b227c59b
RS		 71/*
72 * nvme_wq - hosts nvme related works that are not reset or delete
73 * nvme_reset_wq - hosts nvme reset works
74 * nvme_delete_wq - hosts nvme delete works
75 *
76 * nvme_wq will host works such are scan, aen handling, fw activation,
77 * keep-alive error recovery, periodic reconnects etc. nvme_reset_wq
78 * runs reset works which also flush works hosted on nvme_wq for
79 * serialization purposes. nvme_delete_wq host controller deletion
80 * works which flush reset works for serialization.
81 */
9a6327d2
SG		 82struct workqueue_struct *nvme_wq;
83EXPORT_SYMBOL_GPL(nvme_wq);
84
b227c59b
RS		 85struct workqueue_struct *nvme_reset_wq;
86EXPORT_SYMBOL_GPL(nvme_reset_wq);
87
88struct workqueue_struct *nvme_delete_wq;
89EXPORT_SYMBOL_GPL(nvme_delete_wq);
90
ab9e00cc
CH		 91static DEFINE_IDA(nvme_subsystems_ida);
92static LIST_HEAD(nvme_subsystems);
93static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 94
9843f685 95static DEFINE_IDA(nvme_instance_ida);
a6a5149b 96static dev_t nvme_chr_devt;
f3ca80fc 97static struct class *nvme_class;
ab9e00cc 98static struct class *nvme_subsys_class;
f3ca80fc 99
84fef62d
KB		 100static void nvme_ns_remove(struct nvme_ns *ns);
101static int nvme_revalidate_disk(struct gendisk *disk);
12d9f070 102static void nvme_put_subsystem(struct nvme_subsystem *subsys);
f3ca80fc 103
50e8d8ee
CH		 104static void nvme_queue_scan(struct nvme_ctrl *ctrl)
105{
106 /*
107 * Only new queue scan work when admin and IO queues are both alive
108 */
109 if (ctrl->state == NVME_CTRL_LIVE)
110 queue_work(nvme_wq, &ctrl->scan_work);
111}
112
d86c4d8e
CH		 113int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
114{
115 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
116 return -EBUSY;
b227c59b 117 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 118 return -EBUSY;
119 return 0;
120}
121EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
122
79c48ccf 123int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 124{
125 int ret;
126
127 ret = nvme_reset_ctrl(ctrl);
8000d1fd 128 if (!ret) {
d86c4d8e 129 flush_work(&ctrl->reset_work);
4e50d9eb
CM		 130 if (ctrl->state != NVME_CTRL_LIVE &&
131 ctrl->state != NVME_CTRL_ADMIN_ONLY)
8000d1fd
NC		 132 ret = -ENETRESET;
133 }
134
d86c4d8e
CH		 135 return ret;
136}
79c48ccf 137EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
d86c4d8e 138
c5017e85
CH		 139static void nvme_delete_ctrl_work(struct work_struct *work)
140{
141 struct nvme_ctrl *ctrl =
142 container_of(work, struct nvme_ctrl, delete_work);
143
77d0612d
MG		 144 dev_info(ctrl->device,
145 "Removing ctrl: NQN \"%s\"\n", ctrl->opts->subsysnqn);
146
4054637c 147 flush_work(&ctrl->reset_work);
6cd53d14
CH		 148 nvme_stop_ctrl(ctrl);
149 nvme_remove_namespaces(ctrl);
c5017e85 150 ctrl->ops->delete_ctrl(ctrl);
6cd53d14
CH		 151 nvme_uninit_ctrl(ctrl);
152 nvme_put_ctrl(ctrl);
c5017e85
CH		 153}
154
155int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
156{
157 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
158 return -EBUSY;
b227c59b 159 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 160 return -EBUSY;
161 return 0;
162}
163EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
164
165int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
166{
167 int ret = 0;
168
169 /*
170 * Keep a reference until the work is flushed since ->delete_ctrl
171 * can free the controller.
172 */
173 nvme_get_ctrl(ctrl);
174 ret = nvme_delete_ctrl(ctrl);
175 if (!ret)
176 flush_work(&ctrl->delete_work);
177 nvme_put_ctrl(ctrl);
178 return ret;
179}
180EXPORT_SYMBOL_GPL(nvme_delete_ctrl_sync);
181
715ea9e0
CH		 182static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
183{
184 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
185}
186
2a842aca 187static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 188{
189 switch (nvme_req(req)->status & 0x7ff) {
190 case NVME_SC_SUCCESS:
2a842aca 191 return BLK_STS_OK;
27fa9bc5 192 case NVME_SC_CAP_EXCEEDED:
2a842aca 193 return BLK_STS_NOSPC;
e96fef2c
KB		 194 case NVME_SC_LBA_RANGE:
195 return BLK_STS_TARGET;
196 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 197 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 198 case NVME_SC_INVALID_OPCODE:
199 case NVME_SC_INVALID_FIELD:
200 case NVME_SC_INVALID_NS:
2a842aca 201 return BLK_STS_NOTSUPP;
e02ab023
JG		 202 case NVME_SC_WRITE_FAULT:
203 case NVME_SC_READ_ERROR:
204 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 205 case NVME_SC_ACCESS_DENIED:
206 case NVME_SC_READ_ONLY:
e96fef2c 207 case NVME_SC_COMPARE_FAILED:
2a842aca 208 return BLK_STS_MEDIUM;
a751da33
CH		 209 case NVME_SC_GUARD_CHECK:
210 case NVME_SC_APPTAG_CHECK:
211 case NVME_SC_REFTAG_CHECK:
212 case NVME_SC_INVALID_PI:
213 return BLK_STS_PROTECTION;
214 case NVME_SC_RESERVATION_CONFLICT:
215 return BLK_STS_NEXUS;
2a842aca
CH		 216 default:
217 return BLK_STS_IOERR;
27fa9bc5
CH		 218 }
219}
27fa9bc5 220
f6324b1b 221static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 222{
f6324b1b
CH		 223 if (blk_noretry_request(req))
224 return false;
27fa9bc5 225 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b 226 return false;
44e44b29 227 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 228 return false;
229 return true;
77f02a7a
CH		 230}
231
232void nvme_complete_rq(struct request *req)
233{
908e4564
KB		 234 blk_status_t status = nvme_error_status(req);
235
ca5554a6
JT		 236 trace_nvme_complete_rq(req);
237
908e4564
KB		 238 if (unlikely(status != BLK_STS_OK && nvme_req_needs_retry(req))) {
239 if (nvme_req_needs_failover(req, status)) {
32acab31
CH		 240 nvme_failover_req(req);
241 return;
242 }
243
244 if (!blk_queue_dying(req->q)) {
245 nvme_req(req)->retries++;
246 blk_mq_requeue_request(req, true);
247 return;
248 }
77f02a7a 249 }
908e4564 250 blk_mq_end_request(req, status);
77f02a7a
CH		 251}
252EXPORT_SYMBOL_GPL(nvme_complete_rq);
253
c55a2fd4
ML		 254void nvme_cancel_request(struct request *req, void *data, bool reserved)
255{
c55a2fd4
ML		 256 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
257 "Cancelling I/O %d", req->tag);
258
e54b064c 259 nvme_req(req)->status = NVME_SC_ABORT_REQ;
08e0029a 260 blk_mq_complete_request(req);
27fa9bc5 261
c55a2fd4
ML		 262}
263EXPORT_SYMBOL_GPL(nvme_cancel_request);
264
bb8d261e
CH		 265bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
266 enum nvme_ctrl_state new_state)
267{
f6b6a28e 268 enum nvme_ctrl_state old_state;
0a72bbba 269 unsigned long flags;
bb8d261e
CH		 270 bool changed = false;
271
0a72bbba 272 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 273
274 old_state = ctrl->state;
bb8d261e 275 switch (new_state) {
2b1b7e78
JW		 276 case NVME_CTRL_ADMIN_ONLY:
277 switch (old_state) {
ad6a0a52 278 case NVME_CTRL_CONNECTING:
2b1b7e78
JW		 279 changed = true;
280 /* FALLTHRU */
281 default:
282 break;
283 }
284 break;
bb8d261e
CH		 285 case NVME_CTRL_LIVE:
286 switch (old_state) {
7d2e8008 287 case NVME_CTRL_NEW:
bb8d261e 288 case NVME_CTRL_RESETTING:
ad6a0a52 289 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 290 changed = true;
291 /* FALLTHRU */
292 default:
293 break;
294 }
295 break;
296 case NVME_CTRL_RESETTING:
297 switch (old_state) {
298 case NVME_CTRL_NEW:
def61eca 299 case NVME_CTRL_LIVE:
2b1b7e78 300 case NVME_CTRL_ADMIN_ONLY:
def61eca
CH		 301 changed = true;
302 /* FALLTHRU */
303 default:
304 break;
305 }
306 break;
ad6a0a52 307 case NVME_CTRL_CONNECTING:
def61eca 308 switch (old_state) {
b754a32c 309 case NVME_CTRL_NEW:
3cec7f9d 310 case NVME_CTRL_RESETTING:
bb8d261e
CH		 311 changed = true;
312 /* FALLTHRU */
313 default:
314 break;
315 }
316 break;
317 case NVME_CTRL_DELETING:
318 switch (old_state) {
319 case NVME_CTRL_LIVE:
2b1b7e78 320 case NVME_CTRL_ADMIN_ONLY:
bb8d261e 321 case NVME_CTRL_RESETTING:
ad6a0a52 322 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 323 changed = true;
324 /* FALLTHRU */
325 default:
326 break;
327 }
328 break;
0ff9d4e1
KB		 329 case NVME_CTRL_DEAD:
330 switch (old_state) {
331 case NVME_CTRL_DELETING:
332 changed = true;
333 /* FALLTHRU */
334 default:
335 break;
336 }
337 break;
bb8d261e
CH		 338 default:
339 break;
340 }
bb8d261e
CH		 341
342 if (changed)
343 ctrl->state = new_state;
344
0a72bbba 345 spin_unlock_irqrestore(&ctrl->lock, flags);
32acab31
CH		 346 if (changed && ctrl->state == NVME_CTRL_LIVE)
347 nvme_kick_requeue_lists(ctrl);
bb8d261e
CH		 348 return changed;
349}
350EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
351
ed754e5d
CH		 352static void nvme_free_ns_head(struct kref *ref)
353{
354 struct nvme_ns_head *head =
355 container_of(ref, struct nvme_ns_head, ref);
356
32acab31 357 nvme_mpath_remove_disk(head);
ed754e5d
CH		 358 ida_simple_remove(&head->subsys->ns_ida, head->instance);
359 list_del_init(&head->entry);
4317228a 360 cleanup_srcu_struct_quiesced(&head->srcu);
12d9f070 361 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 362 kfree(head);
363}
364
365static void nvme_put_ns_head(struct nvme_ns_head *head)
366{
367 kref_put(&head->ref, nvme_free_ns_head);
368}
369
1673f1f0
CH		 370static void nvme_free_ns(struct kref *kref)
371{
372 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
373
b0b4e09c
MB		 374 if (ns->ndev)
375 nvme_nvm_unregister(ns);
1673f1f0 376
1673f1f0 377 put_disk(ns->disk);
ed754e5d 378 nvme_put_ns_head(ns->head);
075790eb 379 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 380 kfree(ns);
381}
382
5bae7f73 383static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 384{
385 kref_put(&ns->kref, nvme_free_ns);
386}
387
bb06ec31
JS		 388static inline void nvme_clear_nvme_request(struct request *req)
389{
390 if (!(req->rq_flags & RQF_DONTPREP)) {
391 nvme_req(req)->retries = 0;
392 nvme_req(req)->flags = 0;
393 req->rq_flags |= RQF_DONTPREP;
394 }
395}
396
4160982e 397struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 398 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
21d34711 399{
aebf526b 400 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 401 struct request *req;
21d34711 402
eb71f435 403 if (qid == NVME_QID_ANY) {
aebf526b 404 req = blk_mq_alloc_request(q, op, flags);
eb71f435 405 } else {
aebf526b 406 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 407 qid ? qid - 1 : 0);
408 }
21d34711 409 if (IS_ERR(req))
4160982e 410 return req;
21d34711 411
21d34711 412 req->cmd_flags |= REQ_FAILFAST_DRIVER;
bb06ec31 413 nvme_clear_nvme_request(req);
d49187e9 414 nvme_req(req)->cmd = cmd;
21d34711 415
4160982e
CH		 416 return req;
417}
576d55d6 418EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 419
f5d11840
JA		 420static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
421{
422 struct nvme_command c;
423
424 memset(&c, 0, sizeof(c));
425
426 c.directive.opcode = nvme_admin_directive_send;
62346eae 427 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 428 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
429 c.directive.dtype = NVME_DIR_IDENTIFY;
430 c.directive.tdtype = NVME_DIR_STREAMS;
431 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
432
433 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
434}
435
436static int nvme_disable_streams(struct nvme_ctrl *ctrl)
437{
438 return nvme_toggle_streams(ctrl, false);
439}
440
441static int nvme_enable_streams(struct nvme_ctrl *ctrl)
442{
443 return nvme_toggle_streams(ctrl, true);
444}
445
446static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
447 struct streams_directive_params *s, u32 nsid)
448{
449 struct nvme_command c;
450
451 memset(&c, 0, sizeof(c));
452 memset(s, 0, sizeof(*s));
453
454 c.directive.opcode = nvme_admin_directive_recv;
455 c.directive.nsid = cpu_to_le32(nsid);
a082b426 456 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 457 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
458 c.directive.dtype = NVME_DIR_STREAMS;
459
460 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
461}
462
463static int nvme_configure_directives(struct nvme_ctrl *ctrl)
464{
465 struct streams_directive_params s;
466 int ret;
467
468 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
469 return 0;
470 if (!streams)
471 return 0;
472
473 ret = nvme_enable_streams(ctrl);
474 if (ret)
475 return ret;
476
62346eae 477 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 478 if (ret)
479 return ret;
480
481 ctrl->nssa = le16_to_cpu(s.nssa);
482 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
483 dev_info(ctrl->device, "too few streams (%u) available\n",
484 ctrl->nssa);
485 nvme_disable_streams(ctrl);
486 return 0;
487 }
488
489 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
490 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
491 return 0;
492}
493
494/*
495 * Check if 'req' has a write hint associated with it. If it does, assign
496 * a valid namespace stream to the write.
497 */
498static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
499 struct request *req, u16 *control,
500 u32 *dsmgmt)
501{
502 enum rw_hint streamid = req->write_hint;
503
504 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
505 streamid = 0;
506 else {
507 streamid--;
508 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
509 return;
510
511 *control |= NVME_RW_DTYPE_STREAMS;
512 *dsmgmt |= streamid << 16;
513 }
514
515 if (streamid < ARRAY_SIZE(req->q->write_hints))
516 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
517}
518
8093f7ca
ML		 519static inline void nvme_setup_flush(struct nvme_ns *ns,
520 struct nvme_command *cmnd)
521{
522 memset(cmnd, 0, sizeof(*cmnd));
523 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 524 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 525}
526
fc17b653 527static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 528 struct nvme_command *cmnd)
529{
b35ba01e 530 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 531 struct nvme_dsm_range *range;
b35ba01e 532 struct bio *bio;
8093f7ca 533
b35ba01e 534 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca 535 if (!range)
fc17b653 536 return BLK_STS_RESOURCE;
8093f7ca 537
b35ba01e
CH		 538 __rq_for_each_bio(bio, req) {
539 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
540 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
541
8cb6af7b
KB		 542 if (n < segments) {
543 range[n].cattr = cpu_to_le32(0);
544 range[n].nlb = cpu_to_le32(nlb);
545 range[n].slba = cpu_to_le64(slba);
546 }
b35ba01e
CH		 547 n++;
548 }
549
550 if (WARN_ON_ONCE(n != segments)) {
551 kfree(range);
fc17b653 552 return BLK_STS_IOERR;
b35ba01e 553 }
8093f7ca
ML		 554
555 memset(cmnd, 0, sizeof(*cmnd));
556 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 557 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 558 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 559 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
560
f9d03f96
CH		 561 req->special_vec.bv_page = virt_to_page(range);
562 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 563 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 564 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 565
fc17b653 566 return BLK_STS_OK;
8093f7ca 567}
8093f7ca 568
ebe6d874
CH		 569static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
570 struct request *req, struct nvme_command *cmnd)
8093f7ca 571{
f5d11840 572 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 573 u16 control = 0;
574 u32 dsmgmt = 0;
575
576 if (req->cmd_flags & REQ_FUA)
577 control |= NVME_RW_FUA;
578 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
579 control |= NVME_RW_LR;
580
581 if (req->cmd_flags & REQ_RAHEAD)
582 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
583
584 memset(cmnd, 0, sizeof(*cmnd));
585 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
ed754e5d 586 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 587 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
588 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
589
f5d11840
JA		 590 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
591 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
592
8093f7ca 593 if (ns->ms) {
715ea9e0
CH		 594 /*
595 * If formated with metadata, the block layer always provides a
596 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
597 * we enable the PRACT bit for protection information or set the
598 * namespace capacity to zero to prevent any I/O.
599 */
600 if (!blk_integrity_rq(req)) {
601 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
602 return BLK_STS_NOTSUPP;
603 control |= NVME_RW_PRINFO_PRACT;
604 }
605
8093f7ca
ML		 606 switch (ns->pi_type) {
607 case NVME_NS_DPS_PI_TYPE3:
608 control |= NVME_RW_PRINFO_PRCHK_GUARD;
609 break;
610 case NVME_NS_DPS_PI_TYPE1:
611 case NVME_NS_DPS_PI_TYPE2:
612 control |= NVME_RW_PRINFO_PRCHK_GUARD |
613 NVME_RW_PRINFO_PRCHK_REF;
ddd0bc75 614 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
8093f7ca
ML		 615 break;
616 }
8093f7ca
ML		 617 }
618
619 cmnd->rw.control = cpu_to_le16(control);
620 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 621 return 0;
8093f7ca
ML		 622}
623
fc17b653 624blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 625 struct nvme_command *cmd)
626{
fc17b653 627 blk_status_t ret = BLK_STS_OK;
8093f7ca 628
bb06ec31 629 nvme_clear_nvme_request(req);
987f699a 630
aebf526b
CH		 631 switch (req_op(req)) {
632 case REQ_OP_DRV_IN:
633 case REQ_OP_DRV_OUT:
d49187e9 634 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 635 break;
636 case REQ_OP_FLUSH:
8093f7ca 637 nvme_setup_flush(ns, cmd);
aebf526b 638 break;
e850fd16
CH		 639 case REQ_OP_WRITE_ZEROES:
640 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 641 case REQ_OP_DISCARD:
8093f7ca 642 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 643 break;
644 case REQ_OP_READ:
645 case REQ_OP_WRITE:
ebe6d874 646 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 647 break;
648 default:
649 WARN_ON_ONCE(1);
fc17b653 650 return BLK_STS_IOERR;
aebf526b 651 }
8093f7ca 652
721b3917 653 cmd->common.command_id = req->tag;
5d87eb94 654 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 655 return ret;
656}
657EXPORT_SYMBOL_GPL(nvme_setup_cmd);
658
4160982e
CH		 659/*
660 * Returns 0 on success. If the result is negative, it's a Linux error code;
661 * if the result is positive, it's an NVM Express status code
662 */
663int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 664 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef
BVA		 665 unsigned timeout, int qid, int at_head,
666 blk_mq_req_flags_t flags)
4160982e
CH		 667{
668 struct request *req;
669 int ret;
670
eb71f435 671 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 672 if (IS_ERR(req))
673 return PTR_ERR(req);
674
675 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
676
21d34711
CH		 677 if (buffer && bufflen) {
678 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
679 if (ret)
680 goto out;
4160982e
CH		 681 }
682
eb71f435 683 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 684 if (result)
685 *result = nvme_req(req)->result;
27fa9bc5
CH		 686 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
687 ret = -EINTR;
688 else
689 ret = nvme_req(req)->status;
4160982e
CH		 690 out:
691 blk_mq_free_request(req);
692 return ret;
693}
eb71f435 694EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 695
696int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
697 void *buffer, unsigned bufflen)
698{
eb71f435
CH		 699 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
700 NVME_QID_ANY, 0, 0);
4160982e 701}
576d55d6 702EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 703
1cad6562
CH		 704static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
705 unsigned len, u32 seed, bool write)
706{
707 struct bio_integrity_payload *bip;
708 int ret = -ENOMEM;
709 void *buf;
710
711 buf = kmalloc(len, GFP_KERNEL);
712 if (!buf)
713 goto out;
714
715 ret = -EFAULT;
716 if (write && copy_from_user(buf, ubuf, len))
717 goto out_free_meta;
718
719 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
720 if (IS_ERR(bip)) {
721 ret = PTR_ERR(bip);
722 goto out_free_meta;
723 }
724
725 bip->bip_iter.bi_size = len;
726 bip->bip_iter.bi_sector = seed;
727 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
728 offset_in_page(buf));
729 if (ret == len)
730 return buf;
731 ret = -ENOMEM;
732out_free_meta:
733 kfree(buf);
734out:
735 return ERR_PTR(ret);
736}
737
63263d60 738static int nvme_submit_user_cmd(struct request_queue *q,
485783ca
KB		 739 struct nvme_command *cmd, void __user *ubuffer,
740 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
741 u32 meta_seed, u32 *result, unsigned timeout)
4160982e 742{
7a5abb4b 743 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 744 struct nvme_ns *ns = q->queuedata;
745 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 746 struct request *req;
0b7f1f26
KB		 747 struct bio *bio = NULL;
748 void *meta = NULL;
4160982e
CH		 749 int ret;
750
eb71f435 751 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 752 if (IS_ERR(req))
753 return PTR_ERR(req);
754
755 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
bb06ec31 756 nvme_req(req)->flags |= NVME_REQ_USERCMD;
4160982e
CH		 757
758 if (ubuffer && bufflen) {
21d34711
CH		 759 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
760 GFP_KERNEL);
761 if (ret)
762 goto out;
763 bio = req->bio;
74d46992 764 bio->bi_disk = disk;
1cad6562
CH		 765 if (disk && meta_buffer && meta_len) {
766 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
767 meta_seed, write);
768 if (IS_ERR(meta)) {
769 ret = PTR_ERR(meta);
0b7f1f26
KB		 770 goto out_unmap;
771 }
f31a2110 772 req->cmd_flags |= REQ_INTEGRITY;
0b7f1f26
KB		 773 }
774 }
1cad6562 775
0b7f1f26 776 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 777 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
778 ret = -EINTR;
779 else
780 ret = nvme_req(req)->status;
21d34711 781 if (result)
d49187e9 782 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 783 if (meta && !ret && !write) {
784 if (copy_to_user(meta_buffer, meta, meta_len))
785 ret = -EFAULT;
786 }
0b7f1f26
KB		 787 kfree(meta);
788 out_unmap:
74d46992 789 if (bio)
0b7f1f26 790 blk_rq_unmap_user(bio);
21d34711
CH		 791 out:
792 blk_mq_free_request(req);
793 return ret;
794}
795
2a842aca 796static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 797{
798 struct nvme_ctrl *ctrl = rq->end_io_data;
799
800 blk_mq_free_request(rq);
801
2a842aca 802 if (status) {
038bd4cb 803 dev_err(ctrl->device,
2a842aca
CH		 804 "failed nvme_keep_alive_end_io error=%d\n",
805 status);
038bd4cb
SG		 806 return;
807 }
808
809 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
810}
811
812static int nvme_keep_alive(struct nvme_ctrl *ctrl)
813{
038bd4cb
SG		 814 struct request *rq;
815
0a34e466 816 rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd, BLK_MQ_REQ_RESERVED,
038bd4cb
SG		 817 NVME_QID_ANY);
818 if (IS_ERR(rq))
819 return PTR_ERR(rq);
820
821 rq->timeout = ctrl->kato * HZ;
822 rq->end_io_data = ctrl;
823
824 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
825
826 return 0;
827}
828
829static void nvme_keep_alive_work(struct work_struct *work)
830{
831 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
832 struct nvme_ctrl, ka_work);
833
834 if (nvme_keep_alive(ctrl)) {
835 /* allocation failure, reset the controller */
836 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 837 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 838 return;
839 }
840}
841
00b683db 842static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 843{
844 if (unlikely(ctrl->kato == 0))
845 return;
846
038bd4cb
SG		 847 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
848}
038bd4cb
SG		 849
850void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
851{
852 if (unlikely(ctrl->kato == 0))
853 return;
854
855 cancel_delayed_work_sync(&ctrl->ka_work);
856}
857EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
858
3f7f25a9 859static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 860{
861 struct nvme_command c = { };
862 int error;
863
864 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
865 c.identify.opcode = nvme_admin_identify;
986994a2 866 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 867
868 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
869 if (!*id)
870 return -ENOMEM;
871
872 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
873 sizeof(struct nvme_id_ctrl));
874 if (error)
875 kfree(*id);
876 return error;
877}
878
cdbff4f2 879static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 880 struct nvme_ns_ids *ids)
3b22ba26
JT		 881{
882 struct nvme_command c = { };
883 int status;
884 void *data;
885 int pos;
886 int len;
887
888 c.identify.opcode = nvme_admin_identify;
889 c.identify.nsid = cpu_to_le32(nsid);
890 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
891
892 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
893 if (!data)
894 return -ENOMEM;
895
cdbff4f2 896 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 897 NVME_IDENTIFY_DATA_SIZE);
898 if (status)
899 goto free_data;
900
901 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
902 struct nvme_ns_id_desc *cur = data + pos;
903
904 if (cur->nidl == 0)
905 break;
906
907 switch (cur->nidt) {
908 case NVME_NIDT_EUI64:
909 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 910 dev_warn(ctrl->device,
3b22ba26
JT		 911 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
912 cur->nidl);
913 goto free_data;
914 }
915 len = NVME_NIDT_EUI64_LEN;
002fab04 916 memcpy(ids->eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 917 break;
918 case NVME_NIDT_NGUID:
919 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 920 dev_warn(ctrl->device,
3b22ba26
JT		 921 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
922 cur->nidl);
923 goto free_data;
924 }
925 len = NVME_NIDT_NGUID_LEN;
002fab04 926 memcpy(ids->nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 927 break;
928 case NVME_NIDT_UUID:
929 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 930 dev_warn(ctrl->device,
3b22ba26
JT		 931 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
932 cur->nidl);
933 goto free_data;
934 }
935 len = NVME_NIDT_UUID_LEN;
002fab04 936 uuid_copy(&ids->uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 937 break;
938 default:
939 /* Skip unnkown types */
940 len = cur->nidl;
941 break;
942 }
943
944 len += sizeof(*cur);
945 }
946free_data:
947 kfree(data);
948 return status;
949}
950
540c801c
KB		 951static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
952{
953 struct nvme_command c = { };
954
955 c.identify.opcode = nvme_admin_identify;
986994a2 956 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c 957 c.identify.nsid = cpu_to_le32(nsid);
42595eb7
MI		 958 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list,
959 NVME_IDENTIFY_DATA_SIZE);
540c801c
KB		 960}
961
cdbff4f2
CH		 962static struct nvme_id_ns *nvme_identify_ns(struct nvme_ctrl *ctrl,
963 unsigned nsid)
21d34711 964{
cdbff4f2 965 struct nvme_id_ns *id;
21d34711
CH		 966 struct nvme_command c = { };
967 int error;
968
969 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 970 c.identify.opcode = nvme_admin_identify;
971 c.identify.nsid = cpu_to_le32(nsid);
986994a2 972 c.identify.cns = NVME_ID_CNS_NS;
21d34711 973
cdbff4f2
CH		 974 id = kmalloc(sizeof(*id), GFP_KERNEL);
975 if (!id)
976 return NULL;
21d34711 977
cdbff4f2
CH		 978 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
979 if (error) {
980 dev_warn(ctrl->device, "Identify namespace failed\n");
981 kfree(id);
982 return NULL;
983 }
984
985 return id;
21d34711
CH		 986}
987
3f7f25a9 988static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 989 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 990{
991 struct nvme_command c;
d49187e9 992 union nvme_result res;
1cb3cce5 993 int ret;
21d34711
CH		 994
995 memset(&c, 0, sizeof(c));
996 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 997 c.features.fid = cpu_to_le32(fid);
998 c.features.dword11 = cpu_to_le32(dword11);
999
d49187e9 1000 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 1001 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 1002 if (ret >= 0 && result)
d49187e9 1003 *result = le32_to_cpu(res.u32);
1cb3cce5 1004 return ret;
21d34711
CH		 1005}
1006
9a0be7ab
CH		 1007int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1008{
1009 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1010 u32 result;
1011 int status, nr_io_queues;
1012
1a6fe74d 1013 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1014 &result);
f5fa90dc 1015 if (status < 0)
9a0be7ab
CH		 1016 return status;
1017
f5fa90dc
CH		 1018 /*
1019 * Degraded controllers might return an error when setting the queue
1020 * count. We still want to be able to bring them online and offer
1021 * access to the admin queue, as that might be only way to fix them up.
1022 */
1023 if (status > 0) {
f0425db0 1024 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1025 *count = 0;
1026 } else {
1027 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1028 *count = min(*count, nr_io_queues);
1029 }
1030
9a0be7ab
CH		 1031 return 0;
1032}
576d55d6 1033EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1034
c0561f82
HR		 1035#define NVME_AEN_SUPPORTED \
1036 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT)
1037
1038static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1039{
1040 u32 result;
1041 int status;
1042
1043 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT,
1044 ctrl->oaes & NVME_AEN_SUPPORTED, NULL, 0, &result);
1045 if (status)
1046 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
1047 ctrl->oaes & NVME_AEN_SUPPORTED);
1048}
1049
1673f1f0
CH		 1050static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1051{
1052 struct nvme_user_io io;
1053 struct nvme_command c;
1054 unsigned length, meta_len;
1055 void __user *metadata;
1056
1057 if (copy_from_user(&io, uio, sizeof(io)))
1058 return -EFAULT;
63088ec7
KB		 1059 if (io.flags)
1060 return -EINVAL;
1673f1f0
CH		 1061
1062 switch (io.opcode) {
1063 case nvme_cmd_write:
1064 case nvme_cmd_read:
1065 case nvme_cmd_compare:
1066 break;
1067 default:
1068 return -EINVAL;
1069 }
1070
1071 length = (io.nblocks + 1) << ns->lba_shift;
1072 meta_len = (io.nblocks + 1) * ns->ms;
1073 metadata = (void __user *)(uintptr_t)io.metadata;
1074
1075 if (ns->ext) {
1076 length += meta_len;
1077 meta_len = 0;
1078 } else if (meta_len) {
1079 if ((io.metadata & 3) || !io.metadata)
1080 return -EINVAL;
1081 }
1082
1083 memset(&c, 0, sizeof(c));
1084 c.rw.opcode = io.opcode;
1085 c.rw.flags = io.flags;
ed754e5d 1086 c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1087 c.rw.slba = cpu_to_le64(io.slba);
1088 c.rw.length = cpu_to_le16(io.nblocks);
1089 c.rw.control = cpu_to_le16(io.control);
1090 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1091 c.rw.reftag = cpu_to_le32(io.reftag);
1092 c.rw.apptag = cpu_to_le16(io.apptag);
1093 c.rw.appmask = cpu_to_le16(io.appmask);
1094
63263d60 1095 return nvme_submit_user_cmd(ns->queue, &c,
1673f1f0
CH		 1096 (void __user *)(uintptr_t)io.addr, length,
1097 metadata, meta_len, io.slba, NULL, 0);
1098}
1099
84fef62d
KB		 1100static u32 nvme_known_admin_effects(u8 opcode)
1101{
1102 switch (opcode) {
1103 case nvme_admin_format_nvm:
1104 return NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
1105 NVME_CMD_EFFECTS_CSE_MASK;
1106 case nvme_admin_sanitize_nvm:
1107 return NVME_CMD_EFFECTS_CSE_MASK;
1108 default:
1109 break;
1110 }
1111 return 0;
1112}
1113
1114static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1115 u8 opcode)
1116{
1117 u32 effects = 0;
1118
1119 if (ns) {
1120 if (ctrl->effects)
1121 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
1122 if (effects & ~NVME_CMD_EFFECTS_CSUPP)
1123 dev_warn(ctrl->device,
1124 "IO command:%02x has unhandled effects:%08x\n",
1125 opcode, effects);
1126 return 0;
1127 }
1128
1129 if (ctrl->effects)
62843c2e 1130 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
84fef62d
KB		 1131 else
1132 effects = nvme_known_admin_effects(opcode);
1133
1134 /*
1135 * For simplicity, IO to all namespaces is quiesced even if the command
1136 * effects say only one namespace is affected.
1137 */
1138 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
1139 nvme_start_freeze(ctrl);
1140 nvme_wait_freeze(ctrl);
1141 }
1142 return effects;
1143}
1144
1145static void nvme_update_formats(struct nvme_ctrl *ctrl)
1146{
3fd176b7
JW		 1147 struct nvme_ns *ns, *next;
1148 LIST_HEAD(rm_list);
84fef62d 1149
765cc031 1150 down_write(&ctrl->namespaces_rwsem);
84fef62d 1151 list_for_each_entry(ns, &ctrl->namespaces, list) {
3fd176b7
JW		 1152 if (ns->disk && nvme_revalidate_disk(ns->disk)) {
1153 list_move_tail(&ns->list, &rm_list);
1154 }
84fef62d 1155 }
765cc031 1156 up_write(&ctrl->namespaces_rwsem);
3fd176b7
JW		 1157
1158 list_for_each_entry_safe(ns, next, &rm_list, list)
1159 nvme_ns_remove(ns);
84fef62d
KB		 1160}
1161
1162static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1163{
1164 /*
1165 * Revalidate LBA changes prior to unfreezing. This is necessary to
1166 * prevent memory corruption if a logical block size was changed by
1167 * this command.
1168 */
1169 if (effects & NVME_CMD_EFFECTS_LBCC)
1170 nvme_update_formats(ctrl);
1171 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK))
1172 nvme_unfreeze(ctrl);
1173 if (effects & NVME_CMD_EFFECTS_CCC)
1174 nvme_init_identify(ctrl);
1175 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC))
1176 nvme_queue_scan(ctrl);
1177}
1178
f3ca80fc 1179static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 1180 struct nvme_passthru_cmd __user *ucmd)
1181{
1182 struct nvme_passthru_cmd cmd;
1183 struct nvme_command c;
1184 unsigned timeout = 0;
84fef62d 1185 u32 effects;
1673f1f0
CH		 1186 int status;
1187
1188 if (!capable(CAP_SYS_ADMIN))
1189 return -EACCES;
1190 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1191 return -EFAULT;
63088ec7
KB		 1192 if (cmd.flags)
1193 return -EINVAL;
1673f1f0
CH		 1194
1195 memset(&c, 0, sizeof(c));
1196 c.common.opcode = cmd.opcode;
1197 c.common.flags = cmd.flags;
1198 c.common.nsid = cpu_to_le32(cmd.nsid);
1199 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1200 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1201 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1202 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1203 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1204 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1205 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1206 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1207
1208 if (cmd.timeout_ms)
1209 timeout = msecs_to_jiffies(cmd.timeout_ms);
1210
84fef62d 1211 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1673f1f0 1212 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1213 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
63263d60
KB		 1214 (void __user *)(uintptr_t)cmd.metadata, cmd.metadata,
1215 0, &cmd.result, timeout);
84fef62d
KB		 1216 nvme_passthru_end(ctrl, effects);
1217
1673f1f0
CH		 1218 if (status >= 0) {
1219 if (put_user(cmd.result, &ucmd->result))
1220 return -EFAULT;
1221 }
1222
1223 return status;
1224}
1225
32acab31
CH		 1226/*
1227 * Issue ioctl requests on the first available path. Note that unlike normal
1228 * block layer requests we will not retry failed request on another controller.
1229 */
1230static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1231 struct nvme_ns_head **head, int *srcu_idx)
1673f1f0 1232{
32acab31
CH		 1233#ifdef CONFIG_NVME_MULTIPATH
1234 if (disk->fops == &nvme_ns_head_ops) {
1235 *head = disk->private_data;
1236 *srcu_idx = srcu_read_lock(&(*head)->srcu);
1237 return nvme_find_path(*head);
1238 }
1239#endif
1240 *head = NULL;
1241 *srcu_idx = -1;
1242 return disk->private_data;
1243}
1673f1f0 1244
32acab31
CH		 1245static void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1246{
1247 if (head)
1248 srcu_read_unlock(&head->srcu, idx);
1249}
1673f1f0 1250
32acab31
CH		 1251static int nvme_ns_ioctl(struct nvme_ns *ns, unsigned cmd, unsigned long arg)
1252{
1673f1f0
CH		 1253 switch (cmd) {
1254 case NVME_IOCTL_ID:
1255 force_successful_syscall_return();
ed754e5d 1256 return ns->head->ns_id;
1673f1f0
CH		 1257 case NVME_IOCTL_ADMIN_CMD:
1258 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1259 case NVME_IOCTL_IO_CMD:
1260 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1261 case NVME_IOCTL_SUBMIT_IO:
1262 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1263 default:
84d4add7
MB		 1264#ifdef CONFIG_NVM
1265 if (ns->ndev)
1266 return nvme_nvm_ioctl(ns, cmd, arg);
1267#endif
a98e58e5 1268 if (is_sed_ioctl(cmd))
4f1244c8 1269 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1270 (void __user *) arg);
1673f1f0
CH		 1271 return -ENOTTY;
1272 }
1273}
1274
32acab31
CH		 1275static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1276 unsigned int cmd, unsigned long arg)
1673f1f0 1277{
32acab31
CH		 1278 struct nvme_ns_head *head = NULL;
1279 struct nvme_ns *ns;
1280 int srcu_idx, ret;
1281
1282 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1283 if (unlikely(!ns))
1284 ret = -EWOULDBLOCK;
1285 else
1286 ret = nvme_ns_ioctl(ns, cmd, arg);
1287 nvme_put_ns_from_disk(head, srcu_idx);
1288 return ret;
1673f1f0 1289}
1673f1f0
CH		 1290
1291static int nvme_open(struct block_device *bdev, fmode_t mode)
1292{
c6424a90
CH		 1293 struct nvme_ns *ns = bdev->bd_disk->private_data;
1294
32acab31
CH		 1295#ifdef CONFIG_NVME_MULTIPATH
1296 /* should never be called due to GENHD_FL_HIDDEN */
1297 if (WARN_ON_ONCE(ns->head->disk))
85088c4a 1298 goto fail;
32acab31 1299#endif
c6424a90 1300 if (!kref_get_unless_zero(&ns->kref))
85088c4a
NC		 1301 goto fail;
1302 if (!try_module_get(ns->ctrl->ops->module))
1303 goto fail_put_ns;
1304
c6424a90 1305 return 0;
85088c4a
NC		 1306
1307fail_put_ns:
1308 nvme_put_ns(ns);
1309fail:
1310 return -ENXIO;
1673f1f0
CH		 1311}
1312
1313static void nvme_release(struct gendisk *disk, fmode_t mode)
1314{
85088c4a
NC		 1315 struct nvme_ns *ns = disk->private_data;
1316
1317 module_put(ns->ctrl->ops->module);
1318 nvme_put_ns(ns);
1673f1f0
CH		 1319}
1320
1321static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1322{
1323 /* some standard values */
1324 geo->heads = 1 << 6;
1325 geo->sectors = 1 << 5;
1326 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1327 return 0;
1328}
1329
1330#ifdef CONFIG_BLK_DEV_INTEGRITY
39b7baa4 1331static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1332{
1333 struct blk_integrity integrity;
1334
fa9a89fc 1335 memset(&integrity, 0, sizeof(integrity));
39b7baa4 1336 switch (pi_type) {
1673f1f0
CH		 1337 case NVME_NS_DPS_PI_TYPE3:
1338 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1339 integrity.tag_size = sizeof(u16) + sizeof(u32);
1340 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1341 break;
1342 case NVME_NS_DPS_PI_TYPE1:
1343 case NVME_NS_DPS_PI_TYPE2:
1344 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1345 integrity.tag_size = sizeof(u16);
1346 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1347 break;
1348 default:
1349 integrity.profile = NULL;
1350 break;
1351 }
39b7baa4
CH		 1352 integrity.tuple_size = ms;
1353 blk_integrity_register(disk, &integrity);
1354 blk_queue_max_integrity_segments(disk->queue, 1);
1673f1f0
CH		 1355}
1356#else
39b7baa4 1357static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1358{
1359}
1360#endif /* CONFIG_BLK_DEV_INTEGRITY */
1361
6b8190d6
SB		 1362static void nvme_set_chunk_size(struct nvme_ns *ns)
1363{
1364 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1365 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1366}
1367
3831761e 1368static void nvme_config_discard(struct nvme_ns *ns)
1673f1f0 1369{
3831761e
JA		 1370 struct nvme_ctrl *ctrl = ns->ctrl;
1371 struct request_queue *queue = ns->queue;
30e5e929
CH		 1372 u32 size = queue_logical_block_size(queue);
1373
3831761e
JA		 1374 if (!(ctrl->oncs & NVME_CTRL_ONCS_DSM)) {
1375 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, queue);
1376 return;
1377 }
1378
1379 if (ctrl->nr_streams && ns->sws && ns->sgs)
1380 size *= ns->sws * ns->sgs;
08095e70 1381
b35ba01e
CH		 1382 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1383 NVME_DSM_MAX_RANGES);
1384
b224f613 1385 queue->limits.discard_alignment = 0;
30e5e929 1386 queue->limits.discard_granularity = size;
f5d11840 1387
3831761e
JA		 1388 /* If discard is already enabled, don't reset queue limits */
1389 if (blk_queue_flag_test_and_set(QUEUE_FLAG_DISCARD, queue))
1390 return;
1391
30e5e929
CH		 1392 blk_queue_max_discard_sectors(queue, UINT_MAX);
1393 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
e850fd16
CH		 1394
1395 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1396 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1397}
1398
cdbff4f2 1399static void nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
002fab04 1400 struct nvme_id_ns *id, struct nvme_ns_ids *ids)
1673f1f0 1401{
002fab04
CH		 1402 memset(ids, 0, sizeof(*ids));
1403
cdbff4f2 1404 if (ctrl->vs >= NVME_VS(1, 1, 0))
002fab04 1405 memcpy(ids->eui64, id->eui64, sizeof(id->eui64));
cdbff4f2 1406 if (ctrl->vs >= NVME_VS(1, 2, 0))
002fab04 1407 memcpy(ids->nguid, id->nguid, sizeof(id->nguid));
cdbff4f2 1408 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1409 /* Don't treat error as fatal we potentially
1410 * already have a NGUID or EUI-64
1411 */
002fab04 1412 if (nvme_identify_ns_descs(ctrl, nsid, ids))
cdbff4f2 1413 dev_warn(ctrl->device,
3b22ba26
JT		 1414 "%s: Identify Descriptors failed\n", __func__);
1415 }
ac81bfa9
MB		 1416}
1417
ed754e5d
CH		 1418static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1419{
1420 return !uuid_is_null(&ids->uuid) ||
1421 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1422 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1423}
1424
002fab04
CH		 1425static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1426{
1427 return uuid_equal(&a->uuid, &b->uuid) &&
1428 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1429 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0;
1430}
1431
24b0b58c
CH		 1432static void nvme_update_disk_info(struct gendisk *disk,
1433 struct nvme_ns *ns, struct nvme_id_ns *id)
1434{
1435 sector_t capacity = le64_to_cpup(&id->nsze) << (ns->lba_shift - 9);
cee160fd 1436 unsigned short bs = 1 << ns->lba_shift;
24b0b58c
CH		 1437
1438 blk_mq_freeze_queue(disk->queue);
1439 blk_integrity_unregister(disk);
1440
cee160fd
JL		 1441 blk_queue_logical_block_size(disk->queue, bs);
1442 blk_queue_physical_block_size(disk->queue, bs);
1443 blk_queue_io_min(disk->queue, bs);
1444
24b0b58c
CH		 1445 if (ns->ms && !ns->ext &&
1446 (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1447 nvme_init_integrity(disk, ns->ms, ns->pi_type);
715ea9e0 1448 if (ns->ms && !nvme_ns_has_pi(ns) && !blk_get_integrity(disk))
24b0b58c 1449 capacity = 0;
24b0b58c 1450
3831761e
JA		 1451 set_capacity(disk, capacity);
1452 nvme_config_discard(ns);
24b0b58c
CH		 1453 blk_mq_unfreeze_queue(disk->queue);
1454}
1455
ac81bfa9
MB		 1456static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1457{
1458 struct nvme_ns *ns = disk->private_data;
1673f1f0
CH		 1459
1460 /*
1461 * If identify namespace failed, use default 512 byte block size so
1462 * block layer can use before failing read/write for 0 capacity.
1463 */
c81bfba9 1464 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1465 if (ns->lba_shift == 0)
1466 ns->lba_shift = 9;
6b8190d6 1467 ns->noiob = le16_to_cpu(id->noiob);
b5be3b39 1468 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
c97f414c 1469 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
b5be3b39
CH		 1470 /* the PI implementation requires metadata equal t10 pi tuple size */
1471 if (ns->ms == sizeof(struct t10_pi_tuple))
1472 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1473 else
1474 ns->pi_type = 0;
1673f1f0 1475
6b8190d6
SB		 1476 if (ns->noiob)
1477 nvme_set_chunk_size(ns);
24b0b58c 1478 nvme_update_disk_info(disk, ns, id);
96257a8a
MB		 1479 if (ns->ndev)
1480 nvme_nvm_update_nvm_info(ns);
32acab31
CH		 1481#ifdef CONFIG_NVME_MULTIPATH
1482 if (ns->head->disk)
1483 nvme_update_disk_info(ns->head->disk, ns, id);
1484#endif
ac81bfa9 1485}
1673f1f0 1486
ac81bfa9
MB		 1487static int nvme_revalidate_disk(struct gendisk *disk)
1488{
1489 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1490 struct nvme_ctrl *ctrl = ns->ctrl;
1491 struct nvme_id_ns *id;
002fab04 1492 struct nvme_ns_ids ids;
cdbff4f2 1493 int ret = 0;
ac81bfa9
MB		 1494
1495 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1496 set_capacity(disk, 0);
1497 return -ENODEV;
1498 }
1499
ed754e5d 1500 id = nvme_identify_ns(ctrl, ns->head->ns_id);
cdbff4f2
CH		 1501 if (!id)
1502 return -ENODEV;
ac81bfa9 1503
cdbff4f2
CH		 1504 if (id->ncap == 0) {
1505 ret = -ENODEV;
1506 goto out;
1507 }
ac81bfa9 1508
5e0fab57 1509 __nvme_revalidate_disk(disk, id);
ed754e5d
CH		 1510 nvme_report_ns_ids(ctrl, ns->head->ns_id, id, &ids);
1511 if (!nvme_ns_ids_equal(&ns->head->ids, &ids)) {
1d5df6af 1512 dev_err(ctrl->device,
ed754e5d 1513 "identifiers changed for nsid %d\n", ns->head->ns_id);
1d5df6af
CH		 1514 ret = -ENODEV;
1515 }
1516
cdbff4f2
CH		 1517out:
1518 kfree(id);
1519 return ret;
1673f1f0
CH		 1520}
1521
1522static char nvme_pr_type(enum pr_type type)
1523{
1524 switch (type) {
1525 case PR_WRITE_EXCLUSIVE:
1526 return 1;
1527 case PR_EXCLUSIVE_ACCESS:
1528 return 2;
1529 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1530 return 3;
1531 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1532 return 4;
1533 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1534 return 5;
1535 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1536 return 6;
1537 default:
1538 return 0;
1539 }
1540};
1541
1542static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1543 u64 key, u64 sa_key, u8 op)
1544{
32acab31
CH		 1545 struct nvme_ns_head *head = NULL;
1546 struct nvme_ns *ns;
1673f1f0 1547 struct nvme_command c;
32acab31 1548 int srcu_idx, ret;
1673f1f0
CH		 1549 u8 data[16] = { 0, };
1550
b0d61d58
KB		 1551 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1552 if (unlikely(!ns))
1553 return -EWOULDBLOCK;
1554
1673f1f0
CH		 1555 put_unaligned_le64(key, &data[0]);
1556 put_unaligned_le64(sa_key, &data[8]);
1557
1558 memset(&c, 0, sizeof(c));
1559 c.common.opcode = op;
b0d61d58 1560 c.common.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1561 c.common.cdw10[0] = cpu_to_le32(cdw10);
1562
b0d61d58 1563 ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
32acab31
CH		 1564 nvme_put_ns_from_disk(head, srcu_idx);
1565 return ret;
1673f1f0
CH		 1566}
1567
1568static int nvme_pr_register(struct block_device *bdev, u64 old,
1569 u64 new, unsigned flags)
1570{
1571 u32 cdw10;
1572
1573 if (flags & ~PR_FL_IGNORE_KEY)
1574 return -EOPNOTSUPP;
1575
1576 cdw10 = old ? 2 : 0;
1577 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1578 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1579 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1580}
1581
1582static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1583 enum pr_type type, unsigned flags)
1584{
1585 u32 cdw10;
1586
1587 if (flags & ~PR_FL_IGNORE_KEY)
1588 return -EOPNOTSUPP;
1589
1590 cdw10 = nvme_pr_type(type) << 8;
1591 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1592 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1593}
1594
1595static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1596 enum pr_type type, bool abort)
1597{
e9a9853c 1598 u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
1673f1f0
CH		 1599 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1600}
1601
1602static int nvme_pr_clear(struct block_device *bdev, u64 key)
1603{
8c0b3915 1604 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1605 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1606}
1607
1608static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1609{
e9a9853c 1610 u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1611 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1612}
1613
1614static const struct pr_ops nvme_pr_ops = {
1615 .pr_register = nvme_pr_register,
1616 .pr_reserve = nvme_pr_reserve,
1617 .pr_release = nvme_pr_release,
1618 .pr_preempt = nvme_pr_preempt,
1619 .pr_clear = nvme_pr_clear,
1620};
1621
a98e58e5 1622#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1623int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1624 bool send)
a98e58e5 1625{
4f1244c8 1626 struct nvme_ctrl *ctrl = data;
a98e58e5 1627 struct nvme_command cmd;
a98e58e5
SB		 1628
1629 memset(&cmd, 0, sizeof(cmd));
1630 if (send)
1631 cmd.common.opcode = nvme_admin_security_send;
1632 else
1633 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1634 cmd.common.nsid = 0;
1635 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1636 cmd.common.cdw10[1] = cpu_to_le32(len);
1637
1638 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1639 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1640}
1641EXPORT_SYMBOL_GPL(nvme_sec_submit);
1642#endif /* CONFIG_BLK_SED_OPAL */
1643
5bae7f73 1644static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1645 .owner = THIS_MODULE,
1646 .ioctl = nvme_ioctl,
761f2e1e 1647 .compat_ioctl = nvme_ioctl,
1673f1f0
CH		 1648 .open = nvme_open,
1649 .release = nvme_release,
1650 .getgeo = nvme_getgeo,
1651 .revalidate_disk= nvme_revalidate_disk,
1652 .pr_ops = &nvme_pr_ops,
1653};
1654
32acab31
CH		 1655#ifdef CONFIG_NVME_MULTIPATH
1656static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
1657{
1658 struct nvme_ns_head *head = bdev->bd_disk->private_data;
1659
1660 if (!kref_get_unless_zero(&head->ref))
1661 return -ENXIO;
1662 return 0;
1663}
1664
1665static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
1666{
1667 nvme_put_ns_head(disk->private_data);
1668}
1669
1670const struct block_device_operations nvme_ns_head_ops = {
1671 .owner = THIS_MODULE,
1672 .open = nvme_ns_head_open,
1673 .release = nvme_ns_head_release,
1674 .ioctl = nvme_ioctl,
1675 .compat_ioctl = nvme_ioctl,
1676 .getgeo = nvme_getgeo,
1677 .pr_ops = &nvme_pr_ops,
1678};
1679#endif /* CONFIG_NVME_MULTIPATH */
1680
5fd4ce1b
CH		 1681static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1682{
1683 unsigned long timeout =
1684 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1685 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1686 int ret;
1687
1688 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1689 if (csts == ~0)
1690 return -ENODEV;
5fd4ce1b
CH		 1691 if ((csts & NVME_CSTS_RDY) == bit)
1692 break;
1693
1694 msleep(100);
1695 if (fatal_signal_pending(current))
1696 return -EINTR;
1697 if (time_after(jiffies, timeout)) {
1b3c47c1 1698 dev_err(ctrl->device,
5fd4ce1b
CH		 1699 "Device not ready; aborting %s\n", enabled ?
1700 "initialisation" : "reset");
1701 return -ENODEV;
1702 }
1703 }
1704
1705 return ret;
1706}
1707
1708/*
1709 * If the device has been passed off to us in an enabled state, just clear
1710 * the enabled bit. The spec says we should set the 'shutdown notification
1711 * bits', but doing so may cause the device to complete commands to the
1712 * admin queue ... and we don't know what memory that might be pointing at!
1713 */
1714int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1715{
1716 int ret;
1717
1718 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1719 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1720
1721 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1722 if (ret)
1723 return ret;
54adc010 1724
b5a10c5f 1725 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1726 msleep(NVME_QUIRK_DELAY_AMOUNT);
1727
5fd4ce1b
CH		 1728 return nvme_wait_ready(ctrl, cap, false);
1729}
576d55d6 1730EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1731
1732int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1733{
1734 /*
1735 * Default to a 4K page size, with the intention to update this
1736 * path in the future to accomodate architectures with differing
1737 * kernel and IO page sizes.
1738 */
1739 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1740 int ret;
1741
1742 if (page_shift < dev_page_min) {
1b3c47c1 1743 dev_err(ctrl->device,
5fd4ce1b
CH		 1744 "Minimum device page size %u too large for host (%u)\n",
1745 1 << dev_page_min, 1 << page_shift);
1746 return -ENODEV;
1747 }
1748
1749 ctrl->page_size = 1 << page_shift;
1750
1751 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1752 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 1753 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 1754 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1755 ctrl->ctrl_config |= NVME_CC_ENABLE;
1756
1757 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1758 if (ret)
1759 return ret;
1760 return nvme_wait_ready(ctrl, cap, true);
1761}
576d55d6 1762EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1763
1764int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1765{
07fbd32a 1766 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 1767 u32 csts;
1768 int ret;
1769
1770 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1771 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1772
1773 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1774 if (ret)
1775 return ret;
1776
1777 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1778 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1779 break;
1780
1781 msleep(100);
1782 if (fatal_signal_pending(current))
1783 return -EINTR;
1784 if (time_after(jiffies, timeout)) {
1b3c47c1 1785 dev_err(ctrl->device,
5fd4ce1b
CH		 1786 "Device shutdown incomplete; abort shutdown\n");
1787 return -ENODEV;
1788 }
1789 }
1790
1791 return ret;
1792}
576d55d6 1793EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1794
da35825d
CH		 1795static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1796 struct request_queue *q)
1797{
7c88cb00
JA		 1798 bool vwc = false;
1799
da35825d 1800 if (ctrl->max_hw_sectors) {
45686b61
CH		 1801 u32 max_segments =
1802 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1803
943e942e 1804 max_segments = min_not_zero(max_segments, ctrl->max_segments);
da35825d 1805 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1806 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1807 }
249159c5
KB		 1808 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
1809 is_power_of_2(ctrl->max_hw_sectors))
e6282aef 1810 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1811 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1812 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1813 vwc = true;
1814 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1815}
1816
dbf86b39
JD		 1817static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1818{
1819 __le64 ts;
1820 int ret;
1821
1822 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1823 return 0;
1824
1825 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1826 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
1827 NULL);
1828 if (ret)
1829 dev_warn_once(ctrl->device,
1830 "could not set timestamp (%d)\n", ret);
1831 return ret;
1832}
1833
634b8325 1834static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 1835{
1836 /*
1837 * APST (Autonomous Power State Transition) lets us program a
1838 * table of power state transitions that the controller will
1839 * perform automatically. We configure it with a simple
1840 * heuristic: we are willing to spend at most 2% of the time
1841 * transitioning between power states. Therefore, when running
1842 * in any given state, we will enter the next lower-power
76e4ad09 1843 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 1844 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 1845 * the requested maximum latency.
1846 *
1847 * We will not autonomously enter any non-operational state for
1848 * which the total latency exceeds ps_max_latency_us. Users
1849 * can set ps_max_latency_us to zero to turn off APST.
1850 */
1851
1852 unsigned apste;
1853 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1854 u64 max_lat_us = 0;
1855 int max_ps = -1;
c5552fde
AL		 1856 int ret;
1857
1858 /*
1859 * If APST isn't supported or if we haven't been initialized yet,
1860 * then don't do anything.
1861 */
1862 if (!ctrl->apsta)
634b8325 1863 return 0;
c5552fde
AL		 1864
1865 if (ctrl->npss > 31) {
1866 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 1867 return 0;
c5552fde
AL		 1868 }
1869
1870 table = kzalloc(sizeof(*table), GFP_KERNEL);
1871 if (!table)
634b8325 1872 return 0;
c5552fde 1873
76a5af84 1874 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 1875 /* Turn off APST. */
1876 apste = 0;
fb0dc399 1877 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 1878 } else {
1879 __le64 target = cpu_to_le64(0);
1880 int state;
1881
1882 /*
1883 * Walk through all states from lowest- to highest-power.
1884 * According to the spec, lower-numbered states use more
1885 * power. NPSS, despite the name, is the index of the
1886 * lowest-power state, not the number of states.
1887 */
1888 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 1889 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 1890
1891 if (target)
1892 table->entries[state] = target;
1893
ff5350a8
AL		 1894 /*
1895 * Don't allow transitions to the deepest state
1896 * if it's quirked off.
1897 */
1898 if (state == ctrl->npss &&
1899 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1900 continue;
1901
c5552fde
AL		 1902 /*
1903 * Is this state a useful non-operational state for
1904 * higher-power states to autonomously transition to?
1905 */
1906 if (!(ctrl->psd[state].flags &
1907 NVME_PS_FLAGS_NON_OP_STATE))
1908 continue;
1909
da87591b
KHF		 1910 exit_latency_us =
1911 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
1912 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 1913 continue;
1914
da87591b
KHF		 1915 total_latency_us =
1916 exit_latency_us +
1917 le32_to_cpu(ctrl->psd[state].entry_lat);
1918
c5552fde
AL		 1919 /*
1920 * This state is good. Use it as the APST idle
1921 * target for higher power states.
1922 */
1923 transition_ms = total_latency_us + 19;
1924 do_div(transition_ms, 20);
1925 if (transition_ms > (1 << 24) - 1)
1926 transition_ms = (1 << 24) - 1;
1927
1928 target = cpu_to_le64((state << 3) |
1929 (transition_ms << 8));
fb0dc399
AL		 1930
1931 if (max_ps == -1)
1932 max_ps = state;
1933
1934 if (total_latency_us > max_lat_us)
1935 max_lat_us = total_latency_us;
c5552fde
AL		 1936 }
1937
1938 apste = 1;
fb0dc399
AL		 1939
1940 if (max_ps == -1) {
1941 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1942 } else {
1943 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1944 max_ps, max_lat_us, (int)sizeof(*table), table);
1945 }
c5552fde
AL		 1946 }
1947
1948 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1949 table, sizeof(*table), NULL);
1950 if (ret)
1951 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1952
1953 kfree(table);
634b8325 1954 return ret;
c5552fde
AL		 1955}
1956
1957static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1958{
1959 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1960 u64 latency;
1961
1962 switch (val) {
1963 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1964 case PM_QOS_LATENCY_ANY:
1965 latency = U64_MAX;
1966 break;
1967
1968 default:
1969 latency = val;
1970 }
1971
1972 if (ctrl->ps_max_latency_us != latency) {
1973 ctrl->ps_max_latency_us = latency;
1974 nvme_configure_apst(ctrl);
1975 }
1976}
1977
bd4da3ab
AL		 1978struct nvme_core_quirk_entry {
1979 /*
1980 * NVMe model and firmware strings are padded with spaces. For
1981 * simplicity, strings in the quirk table are padded with NULLs
1982 * instead.
1983 */
1984 u16 vid;
1985 const char *mn;
1986 const char *fr;
1987 unsigned long quirks;
1988};
1989
1990static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1991 {
be56945c
AL		 1992 /*
1993 * This Toshiba device seems to die using any APST states. See:
1994 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1995 */
1996 .vid = 0x1179,
1997 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1998 .quirks = NVME_QUIRK_NO_APST,
be56945c 1999 }
bd4da3ab
AL		 2000};
2001
2002/* match is null-terminated but idstr is space-padded. */
2003static bool string_matches(const char *idstr, const char *match, size_t len)
2004{
2005 size_t matchlen;
2006
2007 if (!match)
2008 return true;
2009
2010 matchlen = strlen(match);
2011 WARN_ON_ONCE(matchlen > len);
2012
2013 if (memcmp(idstr, match, matchlen))
2014 return false;
2015
2016 for (; matchlen < len; matchlen++)
2017 if (idstr[matchlen] != ' ')
2018 return false;
2019
2020 return true;
2021}
2022
2023static bool quirk_matches(const struct nvme_id_ctrl *id,
2024 const struct nvme_core_quirk_entry *q)
2025{
2026 return q->vid == le16_to_cpu(id->vid) &&
2027 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2028 string_matches(id->fr, q->fr, sizeof(id->fr));
2029}
2030
ab9e00cc
CH		 2031static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2032 struct nvme_id_ctrl *id)
180de007
CH		 2033{
2034 size_t nqnlen;
2035 int off;
2036
2037 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2038 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
ab9e00cc 2039 strncpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
180de007
CH		 2040 return;
2041 }
2042
2043 if (ctrl->vs >= NVME_VS(1, 2, 1))
2044 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2045
2046 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 2047 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
180de007
CH		 2048 "nqn.2014.08.org.nvmexpress:%4x%4x",
2049 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2050 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2051 off += sizeof(id->sn);
ab9e00cc 2052 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2053 off += sizeof(id->mn);
ab9e00cc
CH		 2054 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2055}
2056
2057static void __nvme_release_subsystem(struct nvme_subsystem *subsys)
2058{
2059 ida_simple_remove(&nvme_subsystems_ida, subsys->instance);
2060 kfree(subsys);
2061}
2062
2063static void nvme_release_subsystem(struct device *dev)
2064{
2065 __nvme_release_subsystem(container_of(dev, struct nvme_subsystem, dev));
2066}
2067
2068static void nvme_destroy_subsystem(struct kref *ref)
2069{
2070 struct nvme_subsystem *subsys =
2071 container_of(ref, struct nvme_subsystem, ref);
2072
2073 mutex_lock(&nvme_subsystems_lock);
2074 list_del(&subsys->entry);
2075 mutex_unlock(&nvme_subsystems_lock);
2076
ed754e5d 2077 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2078 device_del(&subsys->dev);
2079 put_device(&subsys->dev);
2080}
2081
2082static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2083{
2084 kref_put(&subsys->ref, nvme_destroy_subsystem);
2085}
2086
2087static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2088{
2089 struct nvme_subsystem *subsys;
2090
2091 lockdep_assert_held(&nvme_subsystems_lock);
2092
2093 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2094 if (strcmp(subsys->subnqn, subsysnqn))
2095 continue;
2096 if (!kref_get_unless_zero(&subsys->ref))
2097 continue;
2098 return subsys;
2099 }
2100
2101 return NULL;
2102}
2103
1e496938
HR		 2104#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2105 struct device_attribute subsys_attr_##_name = \
2106 __ATTR(_name, _mode, _show, NULL)
2107
2108static ssize_t nvme_subsys_show_nqn(struct device *dev,
2109 struct device_attribute *attr,
2110 char *buf)
2111{
2112 struct nvme_subsystem *subsys =
2113 container_of(dev, struct nvme_subsystem, dev);
2114
2115 return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2116}
2117static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2118
2119#define nvme_subsys_show_str_function(field) \
2120static ssize_t subsys_##field##_show(struct device *dev, \
2121 struct device_attribute *attr, char *buf) \
2122{ \
2123 struct nvme_subsystem *subsys = \
2124 container_of(dev, struct nvme_subsystem, dev); \
2125 return sprintf(buf, "%.*s\n", \
2126 (int)sizeof(subsys->field), subsys->field); \
2127} \
2128static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2129
2130nvme_subsys_show_str_function(model);
2131nvme_subsys_show_str_function(serial);
2132nvme_subsys_show_str_function(firmware_rev);
2133
2134static struct attribute *nvme_subsys_attrs[] = {
2135 &subsys_attr_model.attr,
2136 &subsys_attr_serial.attr,
2137 &subsys_attr_firmware_rev.attr,
2138 &subsys_attr_subsysnqn.attr,
2139 NULL,
2140};
2141
2142static struct attribute_group nvme_subsys_attrs_group = {
2143 .attrs = nvme_subsys_attrs,
2144};
2145
2146static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2147 &nvme_subsys_attrs_group,
2148 NULL,
2149};
2150
b837b283
IR		 2151static int nvme_active_ctrls(struct nvme_subsystem *subsys)
2152{
2153 int count = 0;
2154 struct nvme_ctrl *ctrl;
2155
2156 mutex_lock(&subsys->lock);
2157 list_for_each_entry(ctrl, &subsys->ctrls, subsys_entry) {
2158 if (ctrl->state != NVME_CTRL_DELETING &&
2159 ctrl->state != NVME_CTRL_DEAD)
2160 count++;
2161 }
2162 mutex_unlock(&subsys->lock);
2163
2164 return count;
2165}
2166
ab9e00cc
CH		 2167static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2168{
2169 struct nvme_subsystem *subsys, *found;
2170 int ret;
2171
2172 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2173 if (!subsys)
2174 return -ENOMEM;
2175 ret = ida_simple_get(&nvme_subsystems_ida, 0, 0, GFP_KERNEL);
2176 if (ret < 0) {
2177 kfree(subsys);
2178 return ret;
2179 }
2180 subsys->instance = ret;
2181 mutex_init(&subsys->lock);
2182 kref_init(&subsys->ref);
2183 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2184 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2185 nvme_init_subnqn(subsys, ctrl, id);
2186 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2187 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2188 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2189 subsys->vendor_id = le16_to_cpu(id->vid);
2190 subsys->cmic = id->cmic;
2191
2192 subsys->dev.class = nvme_subsys_class;
2193 subsys->dev.release = nvme_release_subsystem;
1e496938 2194 subsys->dev.groups = nvme_subsys_attrs_groups;
ab9e00cc
CH		 2195 dev_set_name(&subsys->dev, "nvme-subsys%d", subsys->instance);
2196 device_initialize(&subsys->dev);
2197
2198 mutex_lock(&nvme_subsystems_lock);
2199 found = __nvme_find_get_subsystem(subsys->subnqn);
2200 if (found) {
2201 /*
2202 * Verify that the subsystem actually supports multiple
2203 * controllers, else bail out.
2204 */
16001c10 2205 if (!(ctrl->opts && ctrl->opts->discovery_nqn) &&
181303d0 2206 nvme_active_ctrls(found) && !(id->cmic & (1 << 1))) {
ab9e00cc
CH		 2207 dev_err(ctrl->device,
2208 "ignoring ctrl due to duplicate subnqn (%s).\n",
2209 found->subnqn);
2210 nvme_put_subsystem(found);
2211 ret = -EINVAL;
2212 goto out_unlock;
2213 }
2214
2215 __nvme_release_subsystem(subsys);
2216 subsys = found;
2217 } else {
2218 ret = device_add(&subsys->dev);
2219 if (ret) {
2220 dev_err(ctrl->device,
2221 "failed to register subsystem device.\n");
2222 goto out_unlock;
2223 }
ed754e5d 2224 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2225 list_add_tail(&subsys->entry, &nvme_subsystems);
2226 }
2227
2228 ctrl->subsys = subsys;
2229 mutex_unlock(&nvme_subsystems_lock);
2230
2231 if (sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2232 dev_name(ctrl->device))) {
2233 dev_err(ctrl->device,
2234 "failed to create sysfs link from subsystem.\n");
2235 /* the transport driver will eventually put the subsystem */
2236 return -EINVAL;
2237 }
2238
2239 mutex_lock(&subsys->lock);
2240 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
2241 mutex_unlock(&subsys->lock);
2242
2243 return 0;
2244
2245out_unlock:
2246 mutex_unlock(&nvme_subsystems_lock);
2247 put_device(&subsys->dev);
2248 return ret;
180de007
CH		 2249}
2250
d558fb51 2251int nvme_get_log_ext(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
a294c199 2252 u8 log_page, void *log,
7ec6074f 2253 size_t size, u64 offset)
c627c487
KB		 2254{
2255 struct nvme_command c = { };
70da6094
MB		 2256 unsigned long dwlen = size / 4 - 1;
2257
2258 c.get_log_page.opcode = nvme_admin_get_log_page;
2259
2260 if (ns)
2261 c.get_log_page.nsid = cpu_to_le32(ns->head->ns_id);
2262 else
2263 c.get_log_page.nsid = cpu_to_le32(NVME_NSID_ALL);
c627c487 2264
70da6094
MB		 2265 c.get_log_page.lid = log_page;
2266 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2267 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2268 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2269 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
c627c487
KB		 2270
2271 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2272}
2273
70da6094
MB		 2274static int nvme_get_log(struct nvme_ctrl *ctrl, u8 log_page, void *log,
2275 size_t size)
2276{
2277 return nvme_get_log_ext(ctrl, NULL, log_page, log, size, 0);
2278}
2279
84fef62d
KB		 2280static int nvme_get_effects_log(struct nvme_ctrl *ctrl)
2281{
2282 int ret;
2283
2284 if (!ctrl->effects)
2285 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
2286
2287 if (!ctrl->effects)
2288 return 0;
2289
2290 ret = nvme_get_log(ctrl, NVME_LOG_CMD_EFFECTS, ctrl->effects,
2291 sizeof(*ctrl->effects));
2292 if (ret) {
2293 kfree(ctrl->effects);
2294 ctrl->effects = NULL;
2295 }
2296 return ret;
180de007
CH		 2297}
2298
7fd8930f
CH		 2299/*
2300 * Initialize the cached copies of the Identify data and various controller
2301 * register in our nvme_ctrl structure. This should be called as soon as
2302 * the admin queue is fully up and running.
2303 */
2304int nvme_init_identify(struct nvme_ctrl *ctrl)
2305{
2306 struct nvme_id_ctrl *id;
2307 u64 cap;
2308 int ret, page_shift;
a229dbf6 2309 u32 max_hw_sectors;
76a5af84 2310 bool prev_apst_enabled;
7fd8930f 2311
f3ca80fc
CH		 2312 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2313 if (ret) {
1b3c47c1 2314 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 2315 return ret;
2316 }
2317
7fd8930f
CH		 2318 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
2319 if (ret) {
1b3c47c1 2320 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 2321 return ret;
2322 }
2323 page_shift = NVME_CAP_MPSMIN(cap) + 12;
2324
8ef2074d 2325 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 2326 ctrl->subsystem = NVME_CAP_NSSRC(cap);
2327
7fd8930f
CH		 2328 ret = nvme_identify_ctrl(ctrl, &id);
2329 if (ret) {
1b3c47c1 2330 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 2331 return -EIO;
2332 }
2333
84fef62d
KB		 2334 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
2335 ret = nvme_get_effects_log(ctrl);
2336 if (ret < 0)
75c8b19a 2337 goto out_free;
84fef62d 2338 }
180de007 2339
bd4da3ab 2340 if (!ctrl->identified) {
ab9e00cc
CH		 2341 int i;
2342
2343 ret = nvme_init_subsystem(ctrl, id);
2344 if (ret)
2345 goto out_free;
2346
bd4da3ab
AL		 2347 /*
2348 * Check for quirks. Quirk can depend on firmware version,
2349 * so, in principle, the set of quirks present can change
2350 * across a reset. As a possible future enhancement, we
2351 * could re-scan for quirks every time we reinitialize
2352 * the device, but we'd have to make sure that the driver
2353 * behaves intelligently if the quirks change.
2354 */
bd4da3ab
AL		 2355 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2356 if (quirk_matches(id, &core_quirks[i]))
2357 ctrl->quirks |= core_quirks[i].quirks;
2358 }
2359 }
2360
c35e30b4 2361 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2362 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 2363 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2364 }
2365
8a9ae523 2366 ctrl->oacs = le16_to_cpu(id->oacs);
7fd8930f 2367 ctrl->oncs = le16_to_cpup(&id->oncs);
c0561f82 2368 ctrl->oaes = le32_to_cpu(id->oaes);
6bf25d16 2369 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2370 ctrl->vwc = id->vwc;
931e1c22 2371 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f 2372 if (id->mdts)
a229dbf6 2373 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 2374 else
a229dbf6
CH		 2375 max_hw_sectors = UINT_MAX;
2376 ctrl->max_hw_sectors =
2377 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2378
da35825d 2379 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2380 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2381 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 2382
07fbd32a
MP		 2383 if (id->rtd3e) {
2384 /* us -> s */
2385 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
2386
2387 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2388 shutdown_timeout, 60);
2389
2390 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 2391 dev_info(ctrl->device,
07fbd32a
MP		 2392 "Shutdown timeout set to %u seconds\n",
2393 ctrl->shutdown_timeout);
2394 } else
2395 ctrl->shutdown_timeout = shutdown_timeout;
2396
c5552fde 2397 ctrl->npss = id->npss;
76a5af84
KHF		 2398 ctrl->apsta = id->apsta;
2399 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 2400 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2401 if (force_apst && id->apsta) {
f0425db0 2402 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2403 ctrl->apst_enabled = true;
c35e30b4 2404 } else {
76a5af84 2405 ctrl->apst_enabled = false;
c35e30b4
AL		 2406 }
2407 } else {
76a5af84 2408 ctrl->apst_enabled = id->apsta;
c35e30b4 2409 }
c5552fde
AL		 2410 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2411
d3d5b87d 2412 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 2413 ctrl->icdoff = le16_to_cpu(id->icdoff);
2414 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2415 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2416 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2417
2418 /*
2419 * In fabrics we need to verify the cntlid matches the
2420 * admin connect
2421 */
634b8325 2422 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 2423 ret = -EINVAL;
634b8325
KB		 2424 goto out_free;
2425 }
038bd4cb
SG		 2426
2427 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 2428 dev_err(ctrl->device,
038bd4cb
SG		 2429 "keep-alive support is mandatory for fabrics\n");
2430 ret = -EINVAL;
634b8325 2431 goto out_free;
038bd4cb 2432 }
07bfcd09
CH		 2433 } else {
2434 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 2435 ctrl->hmpre = le32_to_cpu(id->hmpre);
2436 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 2437 ctrl->hmminds = le32_to_cpu(id->hmminds);
2438 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2439 }
da35825d 2440
7fd8930f 2441 kfree(id);
bd4da3ab 2442
76a5af84 2443 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2444 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2445 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 2446 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2447
634b8325
KB		 2448 ret = nvme_configure_apst(ctrl);
2449 if (ret < 0)
2450 return ret;
dbf86b39
JD		 2451
2452 ret = nvme_configure_timestamp(ctrl);
2453 if (ret < 0)
2454 return ret;
634b8325
KB		 2455
2456 ret = nvme_configure_directives(ctrl);
2457 if (ret < 0)
2458 return ret;
c5552fde 2459
bd4da3ab 2460 ctrl->identified = true;
c5552fde 2461
634b8325
KB		 2462 return 0;
2463
2464out_free:
2465 kfree(id);
07bfcd09 2466 return ret;
7fd8930f 2467}
576d55d6 2468EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 2469
f3ca80fc 2470static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 2471{
a6a5149b
CH		 2472 struct nvme_ctrl *ctrl =
2473 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 2474
2b1b7e78
JW		 2475 switch (ctrl->state) {
2476 case NVME_CTRL_LIVE:
2477 case NVME_CTRL_ADMIN_ONLY:
2478 break;
2479 default:
a6a5149b 2480 return -EWOULDBLOCK;
2b1b7e78
JW		 2481 }
2482
a6a5149b 2483 file->private_data = ctrl;
f3ca80fc
CH		 2484 return 0;
2485}
2486
bfd89471
CH		 2487static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
2488{
2489 struct nvme_ns *ns;
2490 int ret;
2491
765cc031 2492 down_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2493 if (list_empty(&ctrl->namespaces)) {
2494 ret = -ENOTTY;
2495 goto out_unlock;
2496 }
2497
2498 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
2499 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 2500 dev_warn(ctrl->device,
bfd89471
CH		 2501 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
2502 ret = -EINVAL;
2503 goto out_unlock;
2504 }
2505
1b3c47c1 2506 dev_warn(ctrl->device,
bfd89471
CH		 2507 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
2508 kref_get(&ns->kref);
765cc031 2509 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2510
2511 ret = nvme_user_cmd(ctrl, ns, argp);
2512 nvme_put_ns(ns);
2513 return ret;
2514
2515out_unlock:
765cc031 2516 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2517 return ret;
2518}
2519
f3ca80fc
CH		 2520static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2521 unsigned long arg)
2522{
2523 struct nvme_ctrl *ctrl = file->private_data;
2524 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2525
2526 switch (cmd) {
2527 case NVME_IOCTL_ADMIN_CMD:
2528 return nvme_user_cmd(ctrl, NULL, argp);
2529 case NVME_IOCTL_IO_CMD:
bfd89471 2530 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2531 case NVME_IOCTL_RESET:
1b3c47c1 2532 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2533 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2534 case NVME_IOCTL_SUBSYS_RESET:
2535 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2536 case NVME_IOCTL_RESCAN:
2537 nvme_queue_scan(ctrl);
2538 return 0;
f3ca80fc
CH		 2539 default:
2540 return -ENOTTY;
2541 }
2542}
2543
2544static const struct file_operations nvme_dev_fops = {
2545 .owner = THIS_MODULE,
2546 .open = nvme_dev_open,
f3ca80fc
CH		 2547 .unlocked_ioctl = nvme_dev_ioctl,
2548 .compat_ioctl = nvme_dev_ioctl,
2549};
2550
2551static ssize_t nvme_sysfs_reset(struct device *dev,
2552 struct device_attribute *attr, const char *buf,
2553 size_t count)
2554{
2555 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2556 int ret;
2557
d86c4d8e 2558 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2559 if (ret < 0)
2560 return ret;
2561 return count;
1673f1f0 2562}
f3ca80fc 2563static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2564
9ec3bb2f
KB		 2565static ssize_t nvme_sysfs_rescan(struct device *dev,
2566 struct device_attribute *attr, const char *buf,
2567 size_t count)
2568{
2569 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2570
2571 nvme_queue_scan(ctrl);
2572 return count;
2573}
2574static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2575
5b85b826
CH		 2576static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
2577{
2578 struct gendisk *disk = dev_to_disk(dev);
2579
2580 if (disk->fops == &nvme_fops)
2581 return nvme_get_ns_from_dev(dev)->head;
2582 else
2583 return disk->private_data;
2584}
2585
118472ab 2586static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2587 char *buf)
118472ab 2588{
5b85b826
CH		 2589 struct nvme_ns_head *head = dev_to_ns_head(dev);
2590 struct nvme_ns_ids *ids = &head->ids;
2591 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH		 2592 int serial_len = sizeof(subsys->serial);
2593 int model_len = sizeof(subsys->model);
118472ab 2594
002fab04
CH		 2595 if (!uuid_is_null(&ids->uuid))
2596 return sprintf(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 2597
002fab04
CH		 2598 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2599 return sprintf(buf, "eui.%16phN\n", ids->nguid);
118472ab 2600
002fab04
CH		 2601 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2602 return sprintf(buf, "eui.%8phN\n", ids->eui64);
118472ab 2603
ab9e00cc
CH		 2604 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
2605 subsys->serial[serial_len - 1] == '\0'))
118472ab 2606 serial_len--;
ab9e00cc
CH		 2607 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
2608 subsys->model[model_len - 1] == '\0'))
118472ab
KB		 2609 model_len--;
2610
ab9e00cc
CH		 2611 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
2612 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 2613 head->ns_id);
118472ab 2614}
c828a892 2615static DEVICE_ATTR_RO(wwid);
118472ab 2616
d934f984 2617static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2618 char *buf)
d934f984 2619{
5b85b826 2620 return sprintf(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 2621}
c828a892 2622static DEVICE_ATTR_RO(nguid);
d934f984 2623
2b9b6e86 2624static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2625 char *buf)
2b9b6e86 2626{
5b85b826 2627 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT		 2628
2629 /* For backward compatibility expose the NGUID to userspace if
2630 * we have no UUID set
2631 */
002fab04 2632 if (uuid_is_null(&ids->uuid)) {
d934f984
JT		 2633 printk_ratelimited(KERN_WARNING
2634 "No UUID available providing old NGUID\n");
002fab04 2635 return sprintf(buf, "%pU\n", ids->nguid);
d934f984 2636 }
002fab04 2637 return sprintf(buf, "%pU\n", &ids->uuid);
2b9b6e86 2638}
c828a892 2639static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB		 2640
2641static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 2642 char *buf)
2b9b6e86 2643{
5b85b826 2644 return sprintf(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 2645}
c828a892 2646static DEVICE_ATTR_RO(eui);
2b9b6e86
KB		 2647
2648static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2649 char *buf)
2b9b6e86 2650{
5b85b826 2651 return sprintf(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 2652}
c828a892 2653static DEVICE_ATTR_RO(nsid);
2b9b6e86 2654
5b85b826 2655static struct attribute *nvme_ns_id_attrs[] = {
118472ab 2656 &dev_attr_wwid.attr,
2b9b6e86 2657 &dev_attr_uuid.attr,
d934f984 2658 &dev_attr_nguid.attr,
2b9b6e86
KB		 2659 &dev_attr_eui.attr,
2660 &dev_attr_nsid.attr,
2661 NULL,
2662};
2663
5b85b826 2664static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2665 struct attribute *a, int n)
2666{
2667 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 2668 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB		 2669
2670 if (a == &dev_attr_uuid.attr) {
a04b5de5 2671 if (uuid_is_null(&ids->uuid) &&
002fab04 2672 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT		 2673 return 0;
2674 }
2675 if (a == &dev_attr_nguid.attr) {
002fab04 2676 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB		 2677 return 0;
2678 }
2679 if (a == &dev_attr_eui.attr) {
002fab04 2680 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB		 2681 return 0;
2682 }
2683 return a->mode;
2684}
2685
5b85b826
CH		 2686const struct attribute_group nvme_ns_id_attr_group = {
2687 .attrs = nvme_ns_id_attrs,
2688 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB		 2689};
2690
931e1c22 2691#define nvme_show_str_function(field) \
779ff756
KB		 2692static ssize_t field##_show(struct device *dev, \
2693 struct device_attribute *attr, char *buf) \
2694{ \
2695 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
ab9e00cc
CH		 2696 return sprintf(buf, "%.*s\n", \
2697 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB		 2698} \
2699static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2700
ab9e00cc
CH		 2701nvme_show_str_function(model);
2702nvme_show_str_function(serial);
2703nvme_show_str_function(firmware_rev);
2704
931e1c22
ML		 2705#define nvme_show_int_function(field) \
2706static ssize_t field##_show(struct device *dev, \
2707 struct device_attribute *attr, char *buf) \
2708{ \
2709 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2710 return sprintf(buf, "%d\n", ctrl->field); \
2711} \
2712static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2713
931e1c22 2714nvme_show_int_function(cntlid);
779ff756 2715
1a353d85
ML		 2716static ssize_t nvme_sysfs_delete(struct device *dev,
2717 struct device_attribute *attr, const char *buf,
2718 size_t count)
2719{
2720 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2721
2722 if (device_remove_file_self(dev, attr))
c5017e85 2723 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML		 2724 return count;
2725}
2726static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2727
2728static ssize_t nvme_sysfs_show_transport(struct device *dev,
2729 struct device_attribute *attr,
2730 char *buf)
2731{
2732 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2733
2734 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2735}
2736static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2737
8432bdb2
SG		 2738static ssize_t nvme_sysfs_show_state(struct device *dev,
2739 struct device_attribute *attr,
2740 char *buf)
2741{
2742 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2743 static const char *const state_name[] = {
2744 [NVME_CTRL_NEW] = "new",
2745 [NVME_CTRL_LIVE] = "live",
2b1b7e78 2746 [NVME_CTRL_ADMIN_ONLY] = "only-admin",
8432bdb2 2747 [NVME_CTRL_RESETTING] = "resetting",
ad6a0a52 2748 [NVME_CTRL_CONNECTING] = "connecting",
8432bdb2
SG		 2749 [NVME_CTRL_DELETING] = "deleting",
2750 [NVME_CTRL_DEAD] = "dead",
2751 };
2752
2753 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2754 state_name[ctrl->state])
2755 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2756
2757 return sprintf(buf, "unknown state\n");
2758}
2759
2760static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2761
1a353d85
ML		 2762static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2763 struct device_attribute *attr,
2764 char *buf)
2765{
2766 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2767
ab9e00cc 2768 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML		 2769}
2770static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2771
2772static ssize_t nvme_sysfs_show_address(struct device *dev,
2773 struct device_attribute *attr,
2774 char *buf)
2775{
2776 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2777
2778 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2779}
2780static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2781
779ff756
KB		 2782static struct attribute *nvme_dev_attrs[] = {
2783 &dev_attr_reset_controller.attr,
9ec3bb2f 2784 &dev_attr_rescan_controller.attr,
779ff756
KB		 2785 &dev_attr_model.attr,
2786 &dev_attr_serial.attr,
2787 &dev_attr_firmware_rev.attr,
931e1c22 2788 &dev_attr_cntlid.attr,
1a353d85
ML		 2789 &dev_attr_delete_controller.attr,
2790 &dev_attr_transport.attr,
2791 &dev_attr_subsysnqn.attr,
2792 &dev_attr_address.attr,
8432bdb2 2793 &dev_attr_state.attr,
779ff756
KB		 2794 NULL
2795};
2796
1a353d85
ML		 2797static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
2798 struct attribute *a, int n)
2799{
2800 struct device *dev = container_of(kobj, struct device, kobj);
2801 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2802
49d3d50b
CH		 2803 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
2804 return 0;
2805 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
2806 return 0;
1a353d85
ML		 2807
2808 return a->mode;
2809}
2810
779ff756 2811static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 2812 .attrs = nvme_dev_attrs,
2813 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 2814};
2815
2816static const struct attribute_group *nvme_dev_attr_groups[] = {
2817 &nvme_dev_attrs_group,
2818 NULL,
2819};
2820
ed754e5d
CH		 2821static struct nvme_ns_head *__nvme_find_ns_head(struct nvme_subsystem *subsys,
2822 unsigned nsid)
2823{
2824 struct nvme_ns_head *h;
2825
2826 lockdep_assert_held(&subsys->lock);
2827
2828 list_for_each_entry(h, &subsys->nsheads, entry) {
2829 if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
2830 return h;
2831 }
2832
2833 return NULL;
2834}
2835
2836static int __nvme_check_ids(struct nvme_subsystem *subsys,
2837 struct nvme_ns_head *new)
2838{
2839 struct nvme_ns_head *h;
2840
2841 lockdep_assert_held(&subsys->lock);
2842
2843 list_for_each_entry(h, &subsys->nsheads, entry) {
2844 if (nvme_ns_ids_valid(&new->ids) &&
2079699c 2845 !list_empty(&h->list) &&
ed754e5d
CH		 2846 nvme_ns_ids_equal(&new->ids, &h->ids))
2847 return -EINVAL;
2848 }
2849
2850 return 0;
2851}
2852
2853static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
2854 unsigned nsid, struct nvme_id_ns *id)
2855{
2856 struct nvme_ns_head *head;
2857 int ret = -ENOMEM;
2858
2859 head = kzalloc(sizeof(*head), GFP_KERNEL);
2860 if (!head)
2861 goto out;
2862 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
2863 if (ret < 0)
2864 goto out_free_head;
2865 head->instance = ret;
2866 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 2867 ret = init_srcu_struct(&head->srcu);
2868 if (ret)
2869 goto out_ida_remove;
ed754e5d
CH		 2870 head->subsys = ctrl->subsys;
2871 head->ns_id = nsid;
2872 kref_init(&head->ref);
2873
2874 nvme_report_ns_ids(ctrl, nsid, id, &head->ids);
2875
2876 ret = __nvme_check_ids(ctrl->subsys, head);
2877 if (ret) {
2878 dev_err(ctrl->device,
2879 "duplicate IDs for nsid %d\n", nsid);
2880 goto out_cleanup_srcu;
2881 }
2882
32acab31
CH		 2883 ret = nvme_mpath_alloc_disk(ctrl, head);
2884 if (ret)
2885 goto out_cleanup_srcu;
2886
ed754e5d 2887 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 2888
2889 kref_get(&ctrl->subsys->ref);
2890
ed754e5d
CH		 2891 return head;
2892out_cleanup_srcu:
2893 cleanup_srcu_struct(&head->srcu);
fd92c77f 2894out_ida_remove:
ed754e5d
CH		 2895 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
2896out_free_head:
2897 kfree(head);
2898out:
2899 return ERR_PTR(ret);
2900}
2901
2902static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
9bd82b1a 2903 struct nvme_id_ns *id)
ed754e5d
CH		 2904{
2905 struct nvme_ctrl *ctrl = ns->ctrl;
2906 bool is_shared = id->nmic & (1 << 0);
2907 struct nvme_ns_head *head = NULL;
2908 int ret = 0;
2909
2910 mutex_lock(&ctrl->subsys->lock);
2911 if (is_shared)
2912 head = __nvme_find_ns_head(ctrl->subsys, nsid);
2913 if (!head) {
2914 head = nvme_alloc_ns_head(ctrl, nsid, id);
2915 if (IS_ERR(head)) {
2916 ret = PTR_ERR(head);
2917 goto out_unlock;
2918 }
ed754e5d
CH		 2919 } else {
2920 struct nvme_ns_ids ids;
2921
2922 nvme_report_ns_ids(ctrl, nsid, id, &ids);
2923 if (!nvme_ns_ids_equal(&head->ids, &ids)) {
2924 dev_err(ctrl->device,
2925 "IDs don't match for shared namespace %d\n",
2926 nsid);
2927 ret = -EINVAL;
2928 goto out_unlock;
2929 }
ed754e5d
CH		 2930 }
2931
2932 list_add_tail(&ns->siblings, &head->list);
2933 ns->head = head;
2934
2935out_unlock:
2936 mutex_unlock(&ctrl->subsys->lock);
2937 return ret;
2938}
2939
5bae7f73
CH		 2940static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2941{
2942 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2943 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2944
ed754e5d 2945 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH		 2946}
2947
32f0c4af 2948static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 2949{
32f0c4af 2950 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 2951
765cc031 2952 down_read(&ctrl->namespaces_rwsem);
5bae7f73 2953 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 2954 if (ns->head->ns_id == nsid) {
2dd41228
CH		 2955 if (!kref_get_unless_zero(&ns->kref))
2956 continue;
32f0c4af
KB		 2957 ret = ns;
2958 break;
2959 }
ed754e5d 2960 if (ns->head->ns_id > nsid)
5bae7f73
CH		 2961 break;
2962 }
765cc031 2963 up_read(&ctrl->namespaces_rwsem);
32f0c4af 2964 return ret;
5bae7f73
CH		 2965}
2966
f5d11840
JA		 2967static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
2968{
2969 struct streams_directive_params s;
2970 int ret;
2971
2972 if (!ctrl->nr_streams)
2973 return 0;
2974
ed754e5d 2975 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
f5d11840
JA		 2976 if (ret)
2977 return ret;
2978
2979 ns->sws = le32_to_cpu(s.sws);
2980 ns->sgs = le16_to_cpu(s.sgs);
2981
2982 if (ns->sws) {
2983 unsigned int bs = 1 << ns->lba_shift;
2984
2985 blk_queue_io_min(ns->queue, bs * ns->sws);
2986 if (ns->sgs)
2987 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
2988 }
2989
2990 return 0;
2991}
2992
5bae7f73
CH		 2993static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2994{
2995 struct nvme_ns *ns;
2996 struct gendisk *disk;
ac81bfa9
MB		 2997 struct nvme_id_ns *id;
2998 char disk_name[DISK_NAME_LEN];
32acab31 2999 int node = dev_to_node(ctrl->dev), flags = GENHD_FL_EXT_DEVT;
5bae7f73
CH		 3000
3001 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3002 if (!ns)
3003 return;
3004
3005 ns->queue = blk_mq_init_queue(ctrl->tagset);
3006 if (IS_ERR(ns->queue))
ed754e5d 3007 goto out_free_ns;
8b904b5b 3008 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
5bae7f73
CH		 3009 ns->queue->queuedata = ns;
3010 ns->ctrl = ctrl;
3011
5bae7f73 3012 kref_init(&ns->kref);
5bae7f73 3013 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 3014
3015 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 3016 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 3017
cdbff4f2
CH		 3018 id = nvme_identify_ns(ctrl, nsid);
3019 if (!id)
ac81bfa9
MB		 3020 goto out_free_queue;
3021
cdbff4f2
CH		 3022 if (id->ncap == 0)
3023 goto out_free_id;
3024
9bd82b1a 3025 if (nvme_init_ns_head(ns, nsid, id))
ed754e5d 3026 goto out_free_id;
654b4a4a 3027 nvme_setup_streams_ns(ctrl, ns);
a785dbcc 3028 nvme_set_disk_name(disk_name, ns, ctrl, &flags);
cdbff4f2 3029
608cc4b1
CH		 3030 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
3031 if (nvme_nvm_register(ns, disk_name, node)) {
3032 dev_warn(ctrl->device, "LightNVM init failure\n");
ed754e5d 3033 goto out_unlink_ns;
608cc4b1 3034 }
3dc87dd0 3035 }
ac81bfa9 3036
3dc87dd0
MB		 3037 disk = alloc_disk_node(0, node);
3038 if (!disk)
ed754e5d 3039 goto out_unlink_ns;
ac81bfa9 3040
3dc87dd0
MB		 3041 disk->fops = &nvme_fops;
3042 disk->private_data = ns;
3043 disk->queue = ns->queue;
32acab31 3044 disk->flags = flags;
3dc87dd0
MB		 3045 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
3046 ns->disk = disk;
3047
3048 __nvme_revalidate_disk(disk, id);
5bae7f73 3049
765cc031 3050 down_write(&ctrl->namespaces_rwsem);
32f0c4af 3051 list_add_tail(&ns->list, &ctrl->namespaces);
765cc031 3052 up_write(&ctrl->namespaces_rwsem);
32f0c4af 3053
d22524a4 3054 nvme_get_ctrl(ctrl);
ac81bfa9
MB		 3055
3056 kfree(id);
3057
0d52c756 3058 device_add_disk(ctrl->device, ns->disk);
2b9b6e86 3059 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
5b85b826 3060 &nvme_ns_id_attr_group))
2b9b6e86
KB		 3061 pr_warn("%s: failed to create sysfs group for identification\n",
3062 ns->disk->disk_name);
3dc87dd0
MB		 3063 if (ns->ndev && nvme_nvm_register_sysfs(ns))
3064 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
3065 ns->disk->disk_name);
32acab31 3066
9bd82b1a 3067 nvme_mpath_add_disk(ns->head);
b9e03857 3068 nvme_fault_inject_init(ns);
5bae7f73 3069 return;
ed754e5d
CH		 3070 out_unlink_ns:
3071 mutex_lock(&ctrl->subsys->lock);
3072 list_del_rcu(&ns->siblings);
3073 mutex_unlock(&ctrl->subsys->lock);
ac81bfa9
MB		 3074 out_free_id:
3075 kfree(id);
5bae7f73
CH		 3076 out_free_queue:
3077 blk_cleanup_queue(ns->queue);
3078 out_free_ns:
3079 kfree(ns);
3080}
3081
3082static void nvme_ns_remove(struct nvme_ns *ns)
3083{
646017a6
KB		 3084 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3085 return;
69d3b8ac 3086
b9e03857 3087 nvme_fault_inject_fini(ns);
b0b4e09c 3088 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
2b9b6e86 3089 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
5b85b826 3090 &nvme_ns_id_attr_group);
3dc87dd0
MB		 3091 if (ns->ndev)
3092 nvme_nvm_unregister_sysfs(ns);
5bae7f73 3093 del_gendisk(ns->disk);
5bae7f73 3094 blk_cleanup_queue(ns->queue);
bd9f5d65
ML		 3095 if (blk_get_integrity(ns->disk))
3096 blk_integrity_unregister(ns->disk);
5bae7f73 3097 }
32f0c4af 3098
ed754e5d 3099 mutex_lock(&ns->ctrl->subsys->lock);
32acab31 3100 nvme_mpath_clear_current_path(ns);
9941a862 3101 list_del_rcu(&ns->siblings);
ed754e5d
CH		 3102 mutex_unlock(&ns->ctrl->subsys->lock);
3103
765cc031 3104 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3105 list_del_init(&ns->list);
765cc031 3106 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3107
9941a862 3108 synchronize_srcu(&ns->head->srcu);
479a322f 3109 nvme_mpath_check_last_path(ns);
5bae7f73
CH		 3110 nvme_put_ns(ns);
3111}
3112
540c801c
KB		 3113static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3114{
3115 struct nvme_ns *ns;
3116
32f0c4af 3117 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 3118 if (ns) {
b0b4e09c 3119 if (ns->disk && revalidate_disk(ns->disk))
540c801c 3120 nvme_ns_remove(ns);
32f0c4af 3121 nvme_put_ns(ns);
540c801c
KB		 3122 } else
3123 nvme_alloc_ns(ctrl, nsid);
3124}
3125
47b0e50a
SB		 3126static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3127 unsigned nsid)
3128{
3129 struct nvme_ns *ns, *next;
6f8e0d78 3130 LIST_HEAD(rm_list);
47b0e50a 3131
765cc031 3132 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3133 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
ed754e5d 3134 if (ns->head->ns_id > nsid)
6f8e0d78 3135 list_move_tail(&ns->list, &rm_list);
47b0e50a 3136 }
765cc031 3137 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3138
3139 list_for_each_entry_safe(ns, next, &rm_list, list)
3140 nvme_ns_remove(ns);
3141
47b0e50a
SB		 3142}
3143
540c801c
KB		 3144static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
3145{
3146 struct nvme_ns *ns;
3147 __le32 *ns_list;
3148 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
3149 int ret = 0;
3150
42595eb7 3151 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3152 if (!ns_list)
3153 return -ENOMEM;
3154
3155 for (i = 0; i < num_lists; i++) {
3156 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
3157 if (ret)
47b0e50a 3158 goto free;
540c801c
KB		 3159
3160 for (j = 0; j < min(nn, 1024U); j++) {
3161 nsid = le32_to_cpu(ns_list[j]);
3162 if (!nsid)
3163 goto out;
3164
3165 nvme_validate_ns(ctrl, nsid);
3166
3167 while (++prev < nsid) {
32f0c4af
KB		 3168 ns = nvme_find_get_ns(ctrl, prev);
3169 if (ns) {
540c801c 3170 nvme_ns_remove(ns);
32f0c4af
KB		 3171 nvme_put_ns(ns);
3172 }
540c801c
KB		 3173 }
3174 }
3175 nn -= j;
3176 }
3177 out:
47b0e50a
SB		 3178 nvme_remove_invalid_namespaces(ctrl, prev);
3179 free:
540c801c
KB		 3180 kfree(ns_list);
3181 return ret;
3182}
3183
5955be21 3184static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 3185{
5bae7f73
CH		 3186 unsigned i;
3187
540c801c
KB		 3188 for (i = 1; i <= nn; i++)
3189 nvme_validate_ns(ctrl, i);
3190
47b0e50a 3191 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3192}
3193
f493af37 3194static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 3195{
3196 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
3197 __le32 *log;
f493af37 3198 int error;
30d90964
CH		 3199
3200 log = kzalloc(log_size, GFP_KERNEL);
3201 if (!log)
f493af37 3202 return;
30d90964 3203
f493af37
CH		 3204 /*
3205 * We need to read the log to clear the AEN, but we don't want to rely
3206 * on it for the changed namespace information as userspace could have
3207 * raced with us in reading the log page, which could cause us to miss
3208 * updates.
3209 */
30d90964 3210 error = nvme_get_log(ctrl, NVME_LOG_CHANGED_NS, log, log_size);
f493af37 3211 if (error)
30d90964
CH		 3212 dev_warn(ctrl->device,
3213 "reading changed ns log failed: %d\n", error);
30d90964 3214
30d90964 3215 kfree(log);
30d90964
CH		 3216}
3217
5955be21 3218static void nvme_scan_work(struct work_struct *work)
5bae7f73 3219{
5955be21
CH		 3220 struct nvme_ctrl *ctrl =
3221 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 3222 struct nvme_id_ctrl *id;
540c801c 3223 unsigned nn;
5bae7f73 3224
5955be21
CH		 3225 if (ctrl->state != NVME_CTRL_LIVE)
3226 return;
3227
2b1b7e78
JW		 3228 WARN_ON_ONCE(!ctrl->tagset);
3229
77016199 3230 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 3231 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 3232 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 3233 }
3234
5bae7f73
CH		 3235 if (nvme_identify_ctrl(ctrl, &id))
3236 return;
540c801c
KB		 3237
3238 nn = le32_to_cpu(id->nn);
8ef2074d 3239 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 3240 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
3241 if (!nvme_scan_ns_list(ctrl, nn))
30d90964 3242 goto out_free_id;
540c801c 3243 }
5955be21 3244 nvme_scan_ns_sequential(ctrl, nn);
30d90964
CH		 3245out_free_id:
3246 kfree(id);
765cc031 3247 down_write(&ctrl->namespaces_rwsem);
540c801c 3248 list_sort(NULL, &ctrl->namespaces, ns_cmp);
765cc031 3249 up_write(&ctrl->namespaces_rwsem);
5955be21 3250}
5bae7f73 3251
32f0c4af
KB		 3252/*
3253 * This function iterates the namespace list unlocked to allow recovery from
3254 * controller failure. It is up to the caller to ensure the namespace list is
3255 * not modified by scan work while this function is executing.
3256 */
5bae7f73
CH		 3257void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
3258{
3259 struct nvme_ns *ns, *next;
6f8e0d78 3260 LIST_HEAD(ns_list);
5bae7f73 3261
0ff9d4e1
KB		 3262 /*
3263 * The dead states indicates the controller was not gracefully
3264 * disconnected. In that case, we won't be able to flush any data while
3265 * removing the namespaces' disks; fail all the queues now to avoid
3266 * potentially having to clean up the failed sync later.
3267 */
3268 if (ctrl->state == NVME_CTRL_DEAD)
3269 nvme_kill_queues(ctrl);
3270
765cc031 3271 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 3272 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 3273 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3274
3275 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 3276 nvme_ns_remove(ns);
3277}
576d55d6 3278EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 3279
e3d7874d
KB		 3280static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
3281{
3282 char *envp[2] = { NULL, NULL };
3283 u32 aen_result = ctrl->aen_result;
3284
3285 ctrl->aen_result = 0;
3286 if (!aen_result)
3287 return;
3288
3289 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
3290 if (!envp[0])
3291 return;
3292 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
3293 kfree(envp[0]);
3294}
3295
f866fc42
CH		 3296static void nvme_async_event_work(struct work_struct *work)
3297{
3298 struct nvme_ctrl *ctrl =
3299 container_of(work, struct nvme_ctrl, async_event_work);
3300
e3d7874d 3301 nvme_aen_uevent(ctrl);
ad22c355 3302 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 3303}
3304
b6dccf7f
AD		 3305static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
3306{
3307
3308 u32 csts;
3309
3310 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
3311 return false;
3312
3313 if (csts == ~0)
3314 return false;
3315
3316 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
3317}
3318
3319static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
3320{
b6dccf7f
AD		 3321 struct nvme_fw_slot_info_log *log;
3322
3323 log = kmalloc(sizeof(*log), GFP_KERNEL);
3324 if (!log)
3325 return;
3326
c627c487 3327 if (nvme_get_log(ctrl, NVME_LOG_FW_SLOT, log, sizeof(*log)))
b6dccf7f
AD		 3328 dev_warn(ctrl->device,
3329 "Get FW SLOT INFO log error\n");
3330 kfree(log);
3331}
3332
3333static void nvme_fw_act_work(struct work_struct *work)
3334{
3335 struct nvme_ctrl *ctrl = container_of(work,
3336 struct nvme_ctrl, fw_act_work);
3337 unsigned long fw_act_timeout;
3338
3339 if (ctrl->mtfa)
3340 fw_act_timeout = jiffies +
3341 msecs_to_jiffies(ctrl->mtfa * 100);
3342 else
3343 fw_act_timeout = jiffies +
3344 msecs_to_jiffies(admin_timeout * 1000);
3345
3346 nvme_stop_queues(ctrl);
3347 while (nvme_ctrl_pp_status(ctrl)) {
3348 if (time_after(jiffies, fw_act_timeout)) {
3349 dev_warn(ctrl->device,
3350 "Fw activation timeout, reset controller\n");
3351 nvme_reset_ctrl(ctrl);
3352 break;
3353 }
3354 msleep(100);
3355 }
3356
3357 if (ctrl->state != NVME_CTRL_LIVE)
3358 return;
3359
3360 nvme_start_queues(ctrl);
a806c6c8 3361 /* read FW slot information to clear the AER */
b6dccf7f
AD		 3362 nvme_get_fw_slot_info(ctrl);
3363}
3364
868c2392
CH		 3365static void nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
3366{
3367 switch ((result & 0xff00) >> 8) {
3368 case NVME_AER_NOTICE_NS_CHANGED:
77016199 3369 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 3370 nvme_queue_scan(ctrl);
3371 break;
3372 case NVME_AER_NOTICE_FW_ACT_STARTING:
3373 queue_work(nvme_wq, &ctrl->fw_act_work);
3374 break;
3375 default:
3376 dev_warn(ctrl->device, "async event result %08x\n", result);
3377 }
3378}
3379
7bf58533 3380void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 3381 volatile union nvme_result *res)
f866fc42 3382{
7bf58533 3383 u32 result = le32_to_cpu(res->u32);
f866fc42 3384
ad22c355 3385 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 3386 return;
3387
e3d7874d 3388 switch (result & 0x7) {
868c2392
CH		 3389 case NVME_AER_NOTICE:
3390 nvme_handle_aen_notice(ctrl, result);
3391 break;
e3d7874d
KB		 3392 case NVME_AER_ERROR:
3393 case NVME_AER_SMART:
3394 case NVME_AER_CSS:
3395 case NVME_AER_VS:
3396 ctrl->aen_result = result;
7bf58533
CH		 3397 break;
3398 default:
3399 break;
f866fc42 3400 }
c669ccdc 3401 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 3402}
f866fc42 3403EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 3404
d09f2b45 3405void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 3406{
d09f2b45 3407 nvme_stop_keep_alive(ctrl);
f866fc42 3408 flush_work(&ctrl->async_event_work);
5955be21 3409 flush_work(&ctrl->scan_work);
b6dccf7f 3410 cancel_work_sync(&ctrl->fw_act_work);
b435ecea
NC		 3411 if (ctrl->ops->stop_ctrl)
3412 ctrl->ops->stop_ctrl(ctrl);
d09f2b45
SG		 3413}
3414EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
3415
3416void nvme_start_ctrl(struct nvme_ctrl *ctrl)
3417{
3418 if (ctrl->kato)
3419 nvme_start_keep_alive(ctrl);
3420
3421 if (ctrl->queue_count > 1) {
3422 nvme_queue_scan(ctrl);
c0561f82 3423 nvme_enable_aen(ctrl);
d99ca609 3424 queue_work(nvme_wq, &ctrl->async_event_work);
d09f2b45
SG		 3425 nvme_start_queues(ctrl);
3426 }
3427}
3428EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 3429
d09f2b45
SG		 3430void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
3431{
a6a5149b 3432 cdev_device_del(&ctrl->cdev, ctrl->device);
53029b04 3433}
576d55d6 3434EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 3435
d22524a4 3436static void nvme_free_ctrl(struct device *dev)
53029b04 3437{
d22524a4
CH		 3438 struct nvme_ctrl *ctrl =
3439 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 3440 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 3441
9843f685 3442 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
84fef62d 3443 kfree(ctrl->effects);
f3ca80fc 3444
ab9e00cc
CH		 3445 if (subsys) {
3446 mutex_lock(&subsys->lock);
3447 list_del(&ctrl->subsys_entry);
3448 mutex_unlock(&subsys->lock);
3449 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
3450 }
f3ca80fc
CH		 3451
3452 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 3453
ab9e00cc
CH		 3454 if (subsys)
3455 nvme_put_subsystem(subsys);
f3ca80fc
CH		 3456}
3457
3458/*
3459 * Initialize a NVMe controller structures. This needs to be called during
3460 * earliest initialization so that we have the initialized structured around
3461 * during probing.
3462 */
3463int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
3464 const struct nvme_ctrl_ops *ops, unsigned long quirks)
3465{
3466 int ret;
3467
bb8d261e
CH		 3468 ctrl->state = NVME_CTRL_NEW;
3469 spin_lock_init(&ctrl->lock);
f3ca80fc 3470 INIT_LIST_HEAD(&ctrl->namespaces);
765cc031 3471 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 3472 ctrl->dev = dev;
3473 ctrl->ops = ops;
3474 ctrl->quirks = quirks;
5955be21 3475 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 3476 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 3477 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 3478 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
f3ca80fc 3479
230f1f9e
JS		 3480 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
3481 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
3482 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
3483
9843f685
CH		 3484 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
3485 if (ret < 0)
f3ca80fc 3486 goto out;
9843f685 3487 ctrl->instance = ret;
f3ca80fc 3488
d22524a4
CH		 3489 device_initialize(&ctrl->ctrl_device);
3490 ctrl->device = &ctrl->ctrl_device;
a6a5149b 3491 ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
d22524a4
CH		 3492 ctrl->device->class = nvme_class;
3493 ctrl->device->parent = ctrl->dev;
3494 ctrl->device->groups = nvme_dev_attr_groups;
3495 ctrl->device->release = nvme_free_ctrl;
3496 dev_set_drvdata(ctrl->device, ctrl);
3497 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
3498 if (ret)
f3ca80fc 3499 goto out_release_instance;
f3ca80fc 3500
a6a5149b
CH		 3501 cdev_init(&ctrl->cdev, &nvme_dev_fops);
3502 ctrl->cdev.owner = ops->module;
3503 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 3504 if (ret)
3505 goto out_free_name;
f3ca80fc 3506
c5552fde
AL		 3507 /*
3508 * Initialize latency tolerance controls. The sysfs files won't
3509 * be visible to userspace unless the device actually supports APST.
3510 */
3511 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
3512 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
3513 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
3514
f3ca80fc 3515 return 0;
d22524a4
CH		 3516out_free_name:
3517 kfree_const(dev->kobj.name);
f3ca80fc 3518out_release_instance:
9843f685 3519 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc
CH		 3520out:
3521 return ret;
3522}
576d55d6 3523EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 3524
69d9a99c
KB		 3525/**
3526 * nvme_kill_queues(): Ends all namespace queues
3527 * @ctrl: the dead controller that needs to end
3528 *
3529 * Call this function when the driver determines it is unable to get the
3530 * controller in a state capable of servicing IO.
3531 */
3532void nvme_kill_queues(struct nvme_ctrl *ctrl)
3533{
3534 struct nvme_ns *ns;
3535
765cc031 3536 down_read(&ctrl->namespaces_rwsem);
82654b6b 3537
443bd90f 3538 /* Forcibly unquiesce queues to avoid blocking dispatch */
7dd1ab16
SB		 3539 if (ctrl->admin_q)
3540 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 3541
32f0c4af 3542 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 3543 /*
3544 * Revalidating a dead namespace sets capacity to 0. This will
3545 * end buffered writers dirtying pages that can't be synced.
3546 */
f33447b9
KB		 3547 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
3548 continue;
3549 revalidate_disk(ns->disk);
69d9a99c 3550 blk_set_queue_dying(ns->queue);
806f026f 3551
443bd90f
ML		 3552 /* Forcibly unquiesce queues to avoid blocking dispatch */
3553 blk_mq_unquiesce_queue(ns->queue);
69d9a99c 3554 }
765cc031 3555 up_read(&ctrl->namespaces_rwsem);
69d9a99c 3556}
237045fc 3557EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 3558
302ad8cc
KB		 3559void nvme_unfreeze(struct nvme_ctrl *ctrl)
3560{
3561 struct nvme_ns *ns;
3562
765cc031 3563 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3564 list_for_each_entry(ns, &ctrl->namespaces, list)
3565 blk_mq_unfreeze_queue(ns->queue);
765cc031 3566 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3567}
3568EXPORT_SYMBOL_GPL(nvme_unfreeze);
3569
3570void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
3571{
3572 struct nvme_ns *ns;
3573
765cc031 3574 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3575 list_for_each_entry(ns, &ctrl->namespaces, list) {
3576 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
3577 if (timeout <= 0)
3578 break;
3579 }
765cc031 3580 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3581}
3582EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
3583
3584void nvme_wait_freeze(struct nvme_ctrl *ctrl)
3585{
3586 struct nvme_ns *ns;
3587
765cc031 3588 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3589 list_for_each_entry(ns, &ctrl->namespaces, list)
3590 blk_mq_freeze_queue_wait(ns->queue);
765cc031 3591 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3592}
3593EXPORT_SYMBOL_GPL(nvme_wait_freeze);
3594
3595void nvme_start_freeze(struct nvme_ctrl *ctrl)
3596{
3597 struct nvme_ns *ns;
3598
765cc031 3599 down_read(&ctrl->namespaces_rwsem);
302ad8cc 3600 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 3601 blk_freeze_queue_start(ns->queue);
765cc031 3602 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3603}
3604EXPORT_SYMBOL_GPL(nvme_start_freeze);
3605
25646264 3606void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3607{
3608 struct nvme_ns *ns;
3609
765cc031 3610 down_read(&ctrl->namespaces_rwsem);
a6eaa884 3611 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 3612 blk_mq_quiesce_queue(ns->queue);
765cc031 3613 up_read(&ctrl->namespaces_rwsem);
363c9aac 3614}
576d55d6 3615EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 3616
25646264 3617void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3618{
3619 struct nvme_ns *ns;
3620
765cc031 3621 down_read(&ctrl->namespaces_rwsem);
8d7b8faf 3622 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 3623 blk_mq_unquiesce_queue(ns->queue);
765cc031 3624 up_read(&ctrl->namespaces_rwsem);
363c9aac 3625}
576d55d6 3626EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 3627
5bae7f73
CH		 3628int __init nvme_core_init(void)
3629{
b227c59b 3630 int result = -ENOMEM;
5bae7f73 3631
9a6327d2
SG		 3632 nvme_wq = alloc_workqueue("nvme-wq",
3633 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3634 if (!nvme_wq)
b227c59b
RS		 3635 goto out;
3636
3637 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
3638 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3639 if (!nvme_reset_wq)
3640 goto destroy_wq;
3641
3642 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
3643 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3644 if (!nvme_delete_wq)
3645 goto destroy_reset_wq;
9a6327d2 3646
a6a5149b 3647 result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
f3ca80fc 3648 if (result < 0)
b227c59b 3649 goto destroy_delete_wq;
f3ca80fc
CH		 3650
3651 nvme_class = class_create(THIS_MODULE, "nvme");
3652 if (IS_ERR(nvme_class)) {
3653 result = PTR_ERR(nvme_class);
3654 goto unregister_chrdev;
3655 }
3656
ab9e00cc
CH		 3657 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
3658 if (IS_ERR(nvme_subsys_class)) {
3659 result = PTR_ERR(nvme_subsys_class);
3660 goto destroy_class;
3661 }
5bae7f73 3662 return 0;
f3ca80fc 3663
ab9e00cc
CH		 3664destroy_class:
3665 class_destroy(nvme_class);
9a6327d2 3666unregister_chrdev:
a6a5149b 3667 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3668destroy_delete_wq:
3669 destroy_workqueue(nvme_delete_wq);
3670destroy_reset_wq:
3671 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 3672destroy_wq:
3673 destroy_workqueue(nvme_wq);
b227c59b 3674out:
f3ca80fc 3675 return result;
5bae7f73
CH		 3676}
3677
3678void nvme_core_exit(void)
3679{
ab9e00cc
CH		 3680 ida_destroy(&nvme_subsystems_ida);
3681 class_destroy(nvme_subsys_class);
f3ca80fc 3682 class_destroy(nvme_class);
a6a5149b 3683 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3684 destroy_workqueue(nvme_delete_wq);
3685 destroy_workqueue(nvme_reset_wq);
9a6327d2 3686 destroy_workqueue(nvme_wq);
5bae7f73 3687}
576d55d6
ML		 3688
3689MODULE_LICENSE("GPL");
3690MODULE_VERSION("1.0");
3691module_init(nvme_core_init);
3692module_exit(nvme_core_exit);
Linux 6.x block layer and io_uring tree(s)