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Merge tag 'kvm-x86-misc-6.9' of https://github.com/kvm-x86/linux into HEAD
[linux-2.6-block.git] / drivers / nvme / host / core.c
CommitLineData
bc50ad75 1// SPDX-License-Identifier: GPL-2.0
21d34711
CH		 2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
21d34711
CH		 5 */
6
7#include <linux/blkdev.h>
8#include <linux/blk-mq.h>
fe45e630 9#include <linux/blk-integrity.h>
c95b708d 10#include <linux/compat.h>
5fd4ce1b 11#include <linux/delay.h>
21d34711 12#include <linux/errno.h>
1673f1f0 13#include <linux/hdreg.h>
21d34711 14#include <linux/kernel.h>
5bae7f73 15#include <linux/module.h>
958f2a0f 16#include <linux/backing-dev.h>
21d34711
CH		 17#include <linux/slab.h>
18#include <linux/types.h>
1673f1f0
CH		 19#include <linux/pr.h>
20#include <linux/ptrace.h>
21#include <linux/nvme_ioctl.h>
c5552fde 22#include <linux/pm_qos.h>
a1a825ab 23#include <linux/ratelimit.h>
1673f1f0 24#include <asm/unaligned.h>
21d34711
CH		 25
26#include "nvme.h"
038bd4cb 27#include "fabrics.h"
f50fff73 28#include <linux/nvme-auth.h>
21d34711 29
35fe0d12
HR		 30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
f3ca80fc
CH		 33#define NVME_MINORS (1U << MINORBITS)
34
1a893c2b
CH		 35struct nvme_ns_info {
36 struct nvme_ns_ids ids;
37 u32 nsid;
38 __le32 anagrpid;
39 bool is_shared;
1e4ea66a 40 bool is_readonly;
1a893c2b 41 bool is_ready;
0dd6fff2 42 bool is_removed;
1a893c2b
CH		 43};
44
8ae4e447
MO		 45unsigned int admin_timeout = 60;
46module_param(admin_timeout, uint, 0644);
ba0ba7d3 47MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 48EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 49
8ae4e447
MO		 50unsigned int nvme_io_timeout = 30;
51module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 52MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 53EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 54
b3b1b0b0 55static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 56module_param(shutdown_timeout, byte, 0644);
57MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
58
44e44b29
CH		 59static u8 nvme_max_retries = 5;
60module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 61MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 62
9947d6a0 63static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 64module_param(default_ps_max_latency_us, ulong, 0644);
65MODULE_PARM_DESC(default_ps_max_latency_us,
66 "max power saving latency for new devices; use PM QOS to change per device");
67
c35e30b4
AL		 68static bool force_apst;
69module_param(force_apst, bool, 0644);
70MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
71
ebd8a93a
AB		 72static unsigned long apst_primary_timeout_ms = 100;
73module_param(apst_primary_timeout_ms, ulong, 0644);
74MODULE_PARM_DESC(apst_primary_timeout_ms,
75 "primary APST timeout in ms");
76
77static unsigned long apst_secondary_timeout_ms = 2000;
78module_param(apst_secondary_timeout_ms, ulong, 0644);
79MODULE_PARM_DESC(apst_secondary_timeout_ms,
80 "secondary APST timeout in ms");
81
82static unsigned long apst_primary_latency_tol_us = 15000;
83module_param(apst_primary_latency_tol_us, ulong, 0644);
84MODULE_PARM_DESC(apst_primary_latency_tol_us,
85 "primary APST latency tolerance in us");
86
87static unsigned long apst_secondary_latency_tol_us = 100000;
88module_param(apst_secondary_latency_tol_us, ulong, 0644);
89MODULE_PARM_DESC(apst_secondary_latency_tol_us,
90 "secondary APST latency tolerance in us");
91
b227c59b
RS		 92/*
93 * nvme_wq - hosts nvme related works that are not reset or delete
94 * nvme_reset_wq - hosts nvme reset works
95 * nvme_delete_wq - hosts nvme delete works
96 *
97b2512a
NK		 97 * nvme_wq will host works such as scan, aen handling, fw activation,
98 * keep-alive, periodic reconnects etc. nvme_reset_wq
b227c59b
RS		 99 * runs reset works which also flush works hosted on nvme_wq for
100 * serialization purposes. nvme_delete_wq host controller deletion
101 * works which flush reset works for serialization.
102 */
9a6327d2
SG		 103struct workqueue_struct *nvme_wq;
104EXPORT_SYMBOL_GPL(nvme_wq);
105
b227c59b
RS		 106struct workqueue_struct *nvme_reset_wq;
107EXPORT_SYMBOL_GPL(nvme_reset_wq);
108
109struct workqueue_struct *nvme_delete_wq;
110EXPORT_SYMBOL_GPL(nvme_delete_wq);
111
ab9e00cc
CH		 112static LIST_HEAD(nvme_subsystems);
113static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 114
9843f685 115static DEFINE_IDA(nvme_instance_ida);
f68abd9c 116static dev_t nvme_ctrl_base_chr_devt;
f3ca80fc 117static struct class *nvme_class;
ab9e00cc 118static struct class *nvme_subsys_class;
f3ca80fc 119
2637baed
MI		 120static DEFINE_IDA(nvme_ns_chr_minor_ida);
121static dev_t nvme_ns_chr_devt;
122static struct class *nvme_ns_chr_class;
123
12d9f070 124static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB		 125static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
126 unsigned nsid);
b58da2d2
TS		 127static void nvme_update_keep_alive(struct nvme_ctrl *ctrl,
128 struct nvme_command *cmd);
cf39a6bc 129
2405252a 130void nvme_queue_scan(struct nvme_ctrl *ctrl)
50e8d8ee
CH		 131{
132 /*
133 * Only new queue scan work when admin and IO queues are both alive
134 */
e6e7f7ac 135 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE && ctrl->tagset)
50e8d8ee
CH		 136 queue_work(nvme_wq, &ctrl->scan_work);
137}
138
4c75f877
KB		 139/*
140 * Use this function to proceed with scheduling reset_work for a controller
141 * that had previously been set to the resetting state. This is intended for
142 * code paths that can't be interrupted by other reset attempts. A hot removal
143 * may prevent this from succeeding.
144 */
c1ac9a4b 145int nvme_try_sched_reset(struct nvme_ctrl *ctrl)
4c75f877 146{
e6e7f7ac 147 if (nvme_ctrl_state(ctrl) != NVME_CTRL_RESETTING)
4c75f877
KB		 148 return -EBUSY;
149 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
150 return -EBUSY;
151 return 0;
152}
c1ac9a4b 153EXPORT_SYMBOL_GPL(nvme_try_sched_reset);
4c75f877 154
8c4dfea9
VG		 155static void nvme_failfast_work(struct work_struct *work)
156{
157 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
158 struct nvme_ctrl, failfast_work);
159
e6e7f7ac 160 if (nvme_ctrl_state(ctrl) != NVME_CTRL_CONNECTING)
8c4dfea9
VG		 161 return;
162
163 set_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
164 dev_info(ctrl->device, "failfast expired\n");
165 nvme_kick_requeue_lists(ctrl);
166}
167
168static inline void nvme_start_failfast_work(struct nvme_ctrl *ctrl)
169{
170 if (!ctrl->opts || ctrl->opts->fast_io_fail_tmo == -1)
171 return;
172
173 schedule_delayed_work(&ctrl->failfast_work,
174 ctrl->opts->fast_io_fail_tmo * HZ);
175}
176
177static inline void nvme_stop_failfast_work(struct nvme_ctrl *ctrl)
178{
179 if (!ctrl->opts)
180 return;
181
182 cancel_delayed_work_sync(&ctrl->failfast_work);
183 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
184}
185
186
d86c4d8e
CH		 187int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
188{
189 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
190 return -EBUSY;
b227c59b 191 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 192 return -EBUSY;
193 return 0;
194}
195EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
196
2405252a 197int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 198{
199 int ret;
200
201 ret = nvme_reset_ctrl(ctrl);
8000d1fd 202 if (!ret) {
d86c4d8e 203 flush_work(&ctrl->reset_work);
e6e7f7ac 204 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
8000d1fd
NC		 205 ret = -ENETRESET;
206 }
207
d86c4d8e
CH		 208 return ret;
209}
210
a686ed75 211static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
c5017e85 212{
77d0612d 213 dev_info(ctrl->device,
e5ea42fa 214 "Removing ctrl: NQN \"%s\"\n", nvmf_ctrl_subsysnqn(ctrl));
77d0612d 215
4054637c 216 flush_work(&ctrl->reset_work);
6cd53d14
CH		 217 nvme_stop_ctrl(ctrl);
218 nvme_remove_namespaces(ctrl);
c5017e85 219 ctrl->ops->delete_ctrl(ctrl);
6cd53d14 220 nvme_uninit_ctrl(ctrl);
c5017e85
CH		 221}
222
a686ed75
BVA		 223static void nvme_delete_ctrl_work(struct work_struct *work)
224{
225 struct nvme_ctrl *ctrl =
226 container_of(work, struct nvme_ctrl, delete_work);
227
228 nvme_do_delete_ctrl(ctrl);
229}
230
c5017e85
CH		 231int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
232{
233 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
234 return -EBUSY;
b227c59b 235 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 236 return -EBUSY;
237 return 0;
238}
239EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
240
942e21c0 241void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
c5017e85 242{
c5017e85 243 /*
01fc08ff
YY		 244 * Keep a reference until nvme_do_delete_ctrl() complete,
245 * since ->delete_ctrl can free the controller.
c5017e85
CH		 246 */
247 nvme_get_ctrl(ctrl);
6721c18a 248 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
b9c77583 249 nvme_do_delete_ctrl(ctrl);
c5017e85 250 nvme_put_ctrl(ctrl);
c5017e85 251}
c5017e85 252
2f9c1736 253static blk_status_t nvme_error_status(u16 status)
27fa9bc5 254{
2f9c1736 255 switch (status & 0x7ff) {
27fa9bc5 256 case NVME_SC_SUCCESS:
2a842aca 257 return BLK_STS_OK;
27fa9bc5 258 case NVME_SC_CAP_EXCEEDED:
2a842aca 259 return BLK_STS_NOSPC;
e96fef2c 260 case NVME_SC_LBA_RANGE:
35038bff
KB		 261 case NVME_SC_CMD_INTERRUPTED:
262 case NVME_SC_NS_NOT_READY:
e96fef2c
KB		 263 return BLK_STS_TARGET;
264 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 265 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 266 case NVME_SC_INVALID_OPCODE:
267 case NVME_SC_INVALID_FIELD:
268 case NVME_SC_INVALID_NS:
2a842aca 269 return BLK_STS_NOTSUPP;
e02ab023
JG		 270 case NVME_SC_WRITE_FAULT:
271 case NVME_SC_READ_ERROR:
272 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 273 case NVME_SC_ACCESS_DENIED:
274 case NVME_SC_READ_ONLY:
e96fef2c 275 case NVME_SC_COMPARE_FAILED:
2a842aca 276 return BLK_STS_MEDIUM;
a751da33
CH		 277 case NVME_SC_GUARD_CHECK:
278 case NVME_SC_APPTAG_CHECK:
279 case NVME_SC_REFTAG_CHECK:
280 case NVME_SC_INVALID_PI:
281 return BLK_STS_PROTECTION;
282 case NVME_SC_RESERVATION_CONFLICT:
7ba15083 283 return BLK_STS_RESV_CONFLICT;
1c0d12c0
SG		 284 case NVME_SC_HOST_PATH_ERROR:
285 return BLK_STS_TRANSPORT;
afaf5c6c
KB		 286 case NVME_SC_ZONE_TOO_MANY_ACTIVE:
287 return BLK_STS_ZONE_ACTIVE_RESOURCE;
288 case NVME_SC_ZONE_TOO_MANY_OPEN:
289 return BLK_STS_ZONE_OPEN_RESOURCE;
2a842aca
CH		 290 default:
291 return BLK_STS_IOERR;
27fa9bc5
CH		 292 }
293}
27fa9bc5 294
49cd84b6
KB		 295static void nvme_retry_req(struct request *req)
296{
49cd84b6
KB		 297 unsigned long delay = 0;
298 u16 crd;
299
300 /* The mask and shift result must be <= 3 */
301 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
f9063a53
MI		 302 if (crd)
303 delay = nvme_req(req)->ctrl->crdt[crd - 1] * 100;
49cd84b6
KB		 304
305 nvme_req(req)->retries++;
306 blk_mq_requeue_request(req, false);
307 blk_mq_delay_kick_requeue_list(req->q, delay);
308}
309
bd83fe6f
AA		 310static void nvme_log_error(struct request *req)
311{
312 struct nvme_ns *ns = req->q->queuedata;
313 struct nvme_request *nr = nvme_req(req);
314
315 if (ns) {
9419e71b 316 pr_err_ratelimited("%s: %s(0x%x) @ LBA %llu, %u blocks, %s (sct 0x%x / sc 0x%x) %s%s\n",
bd83fe6f
AA		 317 ns->disk ? ns->disk->disk_name : "?",
318 nvme_get_opcode_str(nr->cmd->common.opcode),
319 nr->cmd->common.opcode,
0372dd4e 320 nvme_sect_to_lba(ns->head, blk_rq_pos(req)),
9419e71b 321 blk_rq_bytes(req) >> ns->head->lba_shift,
bd83fe6f
AA		 322 nvme_get_error_status_str(nr->status),
323 nr->status >> 8 & 7, /* Status Code Type */
324 nr->status & 0xff, /* Status Code */
325 nr->status & NVME_SC_MORE ? "MORE " : "",
326 nr->status & NVME_SC_DNR ? "DNR " : "");
327 return;
328 }
329
330 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s\n",
331 dev_name(nr->ctrl->device),
332 nvme_get_admin_opcode_str(nr->cmd->common.opcode),
333 nr->cmd->common.opcode,
334 nvme_get_error_status_str(nr->status),
335 nr->status >> 8 & 7, /* Status Code Type */
336 nr->status & 0xff, /* Status Code */
337 nr->status & NVME_SC_MORE ? "MORE " : "",
338 nr->status & NVME_SC_DNR ? "DNR " : "");
339}
340
9f079dda
AA		 341static void nvme_log_err_passthru(struct request *req)
342{
343 struct nvme_ns *ns = req->q->queuedata;
344 struct nvme_request *nr = nvme_req(req);
345
346 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s"
347 "cdw10=0x%x cdw11=0x%x cdw12=0x%x cdw13=0x%x cdw14=0x%x cdw15=0x%x\n",
348 ns ? ns->disk->disk_name : dev_name(nr->ctrl->device),
349 ns ? nvme_get_opcode_str(nr->cmd->common.opcode) :
350 nvme_get_admin_opcode_str(nr->cmd->common.opcode),
351 nr->cmd->common.opcode,
352 nvme_get_error_status_str(nr->status),
353 nr->status >> 8 & 7, /* Status Code Type */
354 nr->status & 0xff, /* Status Code */
355 nr->status & NVME_SC_MORE ? "MORE " : "",
356 nr->status & NVME_SC_DNR ? "DNR " : "",
357 nr->cmd->common.cdw10,
358 nr->cmd->common.cdw11,
359 nr->cmd->common.cdw12,
360 nr->cmd->common.cdw13,
361 nr->cmd->common.cdw14,
362 nr->cmd->common.cdw14);
363}
364
5ddaabe8
CH		 365enum nvme_disposition {
366 COMPLETE,
367 RETRY,
368 FAILOVER,
f50fff73 369 AUTHENTICATE,
5ddaabe8
CH		 370};
371
372static inline enum nvme_disposition nvme_decide_disposition(struct request *req)
77f02a7a 373{
5ddaabe8
CH		 374 if (likely(nvme_req(req)->status == 0))
375 return COMPLETE;
908e4564 376
f50fff73
HR		 377 if ((nvme_req(req)->status & 0x7ff) == NVME_SC_AUTH_REQUIRED)
378 return AUTHENTICATE;
379
5ddaabe8
CH		 380 if (blk_noretry_request(req) ||
381 (nvme_req(req)->status & NVME_SC_DNR) ||
382 nvme_req(req)->retries >= nvme_max_retries)
383 return COMPLETE;
ca5554a6 384
5ddaabe8 385 if (req->cmd_flags & REQ_NVME_MPATH) {
5eac5f33
CL		 386 if (nvme_is_path_error(nvme_req(req)->status) ||
387 blk_queue_dying(req->q))
5ddaabe8 388 return FAILOVER;
5eac5f33
CL		 389 } else {
390 if (blk_queue_dying(req->q))
391 return COMPLETE;
5ddaabe8 392 }
16686f3a 393
5ddaabe8
CH		 394 return RETRY;
395}
6e3ca03e 396
c234a653 397static inline void nvme_end_req_zoned(struct request *req)
5ddaabe8 398{
5ddaabe8 399 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
0372dd4e
DW		 400 req_op(req) == REQ_OP_ZONE_APPEND) {
401 struct nvme_ns *ns = req->q->queuedata;
402
403 req->__sector = nvme_lba_to_sect(ns->head,
240e6ee2 404 le64_to_cpu(nvme_req(req)->result.u64));
0372dd4e 405 }
c234a653
JA		 406}
407
408static inline void nvme_end_req(struct request *req)
409{
410 blk_status_t status = nvme_error_status(nvme_req(req)->status);
35fe0d12 411
9f079dda
AA		 412 if (unlikely(nvme_req(req)->status && !(req->rq_flags & RQF_QUIET))) {
413 if (blk_rq_is_passthrough(req))
414 nvme_log_err_passthru(req);
415 else
416 nvme_log_error(req);
417 }
c234a653 418 nvme_end_req_zoned(req);
2b59787a 419 nvme_trace_bio_complete(req);
d4d957b5
SG		 420 if (req->cmd_flags & REQ_NVME_MPATH)
421 nvme_mpath_end_request(req);
908e4564 422 blk_mq_end_request(req, status);
77f02a7a 423}
5ddaabe8
CH		 424
425void nvme_complete_rq(struct request *req)
426{
f50fff73
HR		 427 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
428
5ddaabe8
CH		 429 trace_nvme_complete_rq(req);
430 nvme_cleanup_cmd(req);
431
774a9636
US		 432 /*
433 * Completions of long-running commands should not be able to
434 * defer sending of periodic keep alives, since the controller
435 * may have completed processing such commands a long time ago
436 * (arbitrarily close to command submission time).
437 * req->deadline - req->timeout is the command submission time
438 * in jiffies.
439 */
440 if (ctrl->kas &&
441 req->deadline - req->timeout >= ctrl->ka_last_check_time)
f50fff73 442 ctrl->comp_seen = true;
5ddaabe8
CH		 443
444 switch (nvme_decide_disposition(req)) {
445 case COMPLETE:
446 nvme_end_req(req);
447 return;
448 case RETRY:
449 nvme_retry_req(req);
450 return;
451 case FAILOVER:
452 nvme_failover_req(req);
453 return;
f50fff73 454 case AUTHENTICATE:
d6800634 455#ifdef CONFIG_NVME_HOST_AUTH
f50fff73
HR		 456 queue_work(nvme_wq, &ctrl->dhchap_auth_work);
457 nvme_retry_req(req);
458#else
459 nvme_end_req(req);
460#endif
461 return;
5ddaabe8
CH		 462 }
463}
77f02a7a
CH		 464EXPORT_SYMBOL_GPL(nvme_complete_rq);
465
c234a653
JA		 466void nvme_complete_batch_req(struct request *req)
467{
00e757b6 468 trace_nvme_complete_rq(req);
c234a653
JA		 469 nvme_cleanup_cmd(req);
470 nvme_end_req_zoned(req);
471}
472EXPORT_SYMBOL_GPL(nvme_complete_batch_req);
473
dda3248e
CL		 474/*
475 * Called to unwind from ->queue_rq on a failed command submission so that the
476 * multipathing code gets called to potentially failover to another path.
477 * The caller needs to unwind all transport specific resource allocations and
478 * must return propagate the return value.
479 */
480blk_status_t nvme_host_path_error(struct request *req)
481{
482 nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR;
483 blk_mq_set_request_complete(req);
484 nvme_complete_rq(req);
485 return BLK_STS_OK;
486}
487EXPORT_SYMBOL_GPL(nvme_host_path_error);
488
2dd6532e 489bool nvme_cancel_request(struct request *req, void *data)
c55a2fd4 490{
c55a2fd4
ML		 491 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
492 "Cancelling I/O %d", req->tag);
493
d4f1d5f7
LY		 494 /* don't abort one completed or idle request */
495 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT)
78ca4072
ML		 496 return true;
497
2dc3947b 498 nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD;
d3589381 499 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
15f73f5b 500 blk_mq_complete_request(req);
7baa8572 501 return true;
c55a2fd4
ML		 502}
503EXPORT_SYMBOL_GPL(nvme_cancel_request);
504
25479069
CL		 505void nvme_cancel_tagset(struct nvme_ctrl *ctrl)
506{
507 if (ctrl->tagset) {
508 blk_mq_tagset_busy_iter(ctrl->tagset,
509 nvme_cancel_request, ctrl);
510 blk_mq_tagset_wait_completed_request(ctrl->tagset);
511 }
512}
513EXPORT_SYMBOL_GPL(nvme_cancel_tagset);
514
515void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl)
516{
517 if (ctrl->admin_tagset) {
518 blk_mq_tagset_busy_iter(ctrl->admin_tagset,
519 nvme_cancel_request, ctrl);
520 blk_mq_tagset_wait_completed_request(ctrl->admin_tagset);
521 }
522}
523EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset);
524
bb8d261e
CH		 525bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
526 enum nvme_ctrl_state new_state)
527{
f6b6a28e 528 enum nvme_ctrl_state old_state;
0a72bbba 529 unsigned long flags;
bb8d261e
CH		 530 bool changed = false;
531
0a72bbba 532 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e 533
e6e7f7ac 534 old_state = nvme_ctrl_state(ctrl);
bb8d261e
CH		 535 switch (new_state) {
536 case NVME_CTRL_LIVE:
537 switch (old_state) {
7d2e8008 538 case NVME_CTRL_NEW:
bb8d261e 539 case NVME_CTRL_RESETTING:
ad6a0a52 540 case NVME_CTRL_CONNECTING:
bb8d261e 541 changed = true;
df561f66 542 fallthrough;
bb8d261e
CH		 543 default:
544 break;
545 }
546 break;
547 case NVME_CTRL_RESETTING:
548 switch (old_state) {
549 case NVME_CTRL_NEW:
def61eca 550 case NVME_CTRL_LIVE:
def61eca 551 changed = true;
df561f66 552 fallthrough;
def61eca
CH		 553 default:
554 break;
555 }
556 break;
ad6a0a52 557 case NVME_CTRL_CONNECTING:
def61eca 558 switch (old_state) {
b754a32c 559 case NVME_CTRL_NEW:
3cec7f9d 560 case NVME_CTRL_RESETTING:
bb8d261e 561 changed = true;
df561f66 562 fallthrough;
bb8d261e
CH		 563 default:
564 break;
565 }
566 break;
567 case NVME_CTRL_DELETING:
568 switch (old_state) {
569 case NVME_CTRL_LIVE:
570 case NVME_CTRL_RESETTING:
ad6a0a52 571 case NVME_CTRL_CONNECTING:
bb8d261e 572 changed = true;
df561f66 573 fallthrough;
bb8d261e
CH		 574 default:
575 break;
576 }
577 break;
ecca390e
SG		 578 case NVME_CTRL_DELETING_NOIO:
579 switch (old_state) {
580 case NVME_CTRL_DELETING:
581 case NVME_CTRL_DEAD:
582 changed = true;
df561f66 583 fallthrough;
ecca390e
SG		 584 default:
585 break;
586 }
587 break;
0ff9d4e1
KB		 588 case NVME_CTRL_DEAD:
589 switch (old_state) {
590 case NVME_CTRL_DELETING:
591 changed = true;
df561f66 592 fallthrough;
0ff9d4e1
KB		 593 default:
594 break;
595 }
596 break;
bb8d261e
CH		 597 default:
598 break;
599 }
bb8d261e 600
c1ac9a4b 601 if (changed) {
e6e7f7ac 602 WRITE_ONCE(ctrl->state, new_state);
c1ac9a4b
KB		 603 wake_up_all(&ctrl->state_wq);
604 }
bb8d261e 605
0a72bbba 606 spin_unlock_irqrestore(&ctrl->lock, flags);
8c4dfea9
VG		 607 if (!changed)
608 return false;
609
e6e7f7ac 610 if (new_state == NVME_CTRL_LIVE) {
8c4dfea9
VG		 611 if (old_state == NVME_CTRL_CONNECTING)
612 nvme_stop_failfast_work(ctrl);
32acab31 613 nvme_kick_requeue_lists(ctrl);
e6e7f7ac 614 } else if (new_state == NVME_CTRL_CONNECTING &&
8c4dfea9
VG		 615 old_state == NVME_CTRL_RESETTING) {
616 nvme_start_failfast_work(ctrl);
617 }
bb8d261e
CH		 618 return changed;
619}
620EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
621
c1ac9a4b
KB		 622/*
623 * Returns true for sink states that can't ever transition back to live.
624 */
625static bool nvme_state_terminal(struct nvme_ctrl *ctrl)
626{
e6e7f7ac 627 switch (nvme_ctrl_state(ctrl)) {
c1ac9a4b
KB		 628 case NVME_CTRL_NEW:
629 case NVME_CTRL_LIVE:
630 case NVME_CTRL_RESETTING:
631 case NVME_CTRL_CONNECTING:
632 return false;
633 case NVME_CTRL_DELETING:
ecca390e 634 case NVME_CTRL_DELETING_NOIO:
c1ac9a4b
KB		 635 case NVME_CTRL_DEAD:
636 return true;
637 default:
638 WARN_ONCE(1, "Unhandled ctrl state:%d", ctrl->state);
639 return true;
640 }
641}
642
643/*
644 * Waits for the controller state to be resetting, or returns false if it is
645 * not possible to ever transition to that state.
646 */
647bool nvme_wait_reset(struct nvme_ctrl *ctrl)
648{
649 wait_event(ctrl->state_wq,
650 nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) ||
651 nvme_state_terminal(ctrl));
e6e7f7ac 652 return nvme_ctrl_state(ctrl) == NVME_CTRL_RESETTING;
c1ac9a4b
KB		 653}
654EXPORT_SYMBOL_GPL(nvme_wait_reset);
655
ed754e5d
CH		 656static void nvme_free_ns_head(struct kref *ref)
657{
658 struct nvme_ns_head *head =
659 container_of(ref, struct nvme_ns_head, ref);
660
32acab31 661 nvme_mpath_remove_disk(head);
8b850475 662 ida_free(&head->subsys->ns_ida, head->instance);
f5ad3991 663 cleanup_srcu_struct(&head->srcu);
12d9f070 664 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 665 kfree(head);
666}
667
1496bd49 668bool nvme_tryget_ns_head(struct nvme_ns_head *head)
871ca3ef
CH		 669{
670 return kref_get_unless_zero(&head->ref);
671}
672
1496bd49 673void nvme_put_ns_head(struct nvme_ns_head *head)
ed754e5d
CH		 674{
675 kref_put(&head->ref, nvme_free_ns_head);
676}
677
1673f1f0
CH		 678static void nvme_free_ns(struct kref *kref)
679{
680 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
681
1673f1f0 682 put_disk(ns->disk);
ed754e5d 683 nvme_put_ns_head(ns->head);
075790eb 684 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 685 kfree(ns);
686}
687
4c74d1f8
KJ		 688static inline bool nvme_get_ns(struct nvme_ns *ns)
689{
690 return kref_get_unless_zero(&ns->kref);
691}
692
24493b8b 693void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 694{
695 kref_put(&ns->kref, nvme_free_ns);
696}
24493b8b 697EXPORT_SYMBOL_NS_GPL(nvme_put_ns, NVME_TARGET_PASSTHRU);
1673f1f0 698
bb06ec31
JS		 699static inline void nvme_clear_nvme_request(struct request *req)
700{
ae5e6886 701 nvme_req(req)->status = 0;
c03fd85d
CK		 702 nvme_req(req)->retries = 0;
703 nvme_req(req)->flags = 0;
704 req->rq_flags |= RQF_DONTPREP;
bb06ec31
JS		 705}
706
e559398f
CH		 707/* initialize a passthrough request */
708void nvme_init_request(struct request *req, struct nvme_command *cmd)
39dfe844 709{
9f079dda
AA		 710 struct nvme_request *nr = nvme_req(req);
711 bool logging_enabled;
712
713 if (req->q->queuedata) {
714 struct nvme_ns *ns = req->q->disk->private_data;
715
1f4137e8 716 logging_enabled = ns->head->passthru_err_log_enabled;
0d2e7c84 717 req->timeout = NVME_IO_TIMEOUT;
9f079dda
AA		 718 } else { /* no queuedata implies admin queue */
719 logging_enabled = nr->ctrl->passthru_err_log_enabled;
dc96f938 720 req->timeout = NVME_ADMIN_TIMEOUT;
9f079dda
AA		 721 }
722
723 if (!logging_enabled)
724 req->rq_flags |= RQF_QUIET;
21d34711 725
f4b9e6c9
KB		 726 /* passthru commands should let the driver set the SGL flags */
727 cmd->common.flags &= ~NVME_CMD_SGL_ALL;
728
21d34711 729 req->cmd_flags |= REQ_FAILFAST_DRIVER;
be42a33b 730 if (req->mq_hctx->type == HCTX_TYPE_POLL)
6ce913fe 731 req->cmd_flags |= REQ_POLLED;
bb06ec31 732 nvme_clear_nvme_request(req);
9f079dda 733 memcpy(nr->cmd, cmd, sizeof(*cmd));
39dfe844 734}
e559398f 735EXPORT_SYMBOL_GPL(nvme_init_request);
39dfe844 736
a9715744
TC		 737/*
738 * For something we're not in a state to send to the device the default action
739 * is to busy it and retry it after the controller state is recovered. However,
740 * if the controller is deleting or if anything is marked for failfast or
741 * nvme multipath it is immediately failed.
742 *
743 * Note: commands used to initialize the controller will be marked for failfast.
744 * Note: nvme cli/ioctl commands are marked for failfast.
745 */
746blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl,
747 struct request *rq)
748{
e6e7f7ac
KB		 749 enum nvme_ctrl_state state = nvme_ctrl_state(ctrl);
750
751 if (state != NVME_CTRL_DELETING_NOIO &&
752 state != NVME_CTRL_DELETING &&
753 state != NVME_CTRL_DEAD &&
a9715744
TC		 754 !test_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags) &&
755 !blk_noretry_request(rq) && !(rq->cmd_flags & REQ_NVME_MPATH))
756 return BLK_STS_RESOURCE;
757 return nvme_host_path_error(rq);
758}
759EXPORT_SYMBOL_GPL(nvme_fail_nonready_command);
760
761bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq,
6d3c7fb1 762 bool queue_live, enum nvme_ctrl_state state)
a9715744
TC		 763{
764 struct nvme_request *req = nvme_req(rq);
765
766 /*
767 * currently we have a problem sending passthru commands
768 * on the admin_q if the controller is not LIVE because we can't
769 * make sure that they are going out after the admin connect,
770 * controller enable and/or other commands in the initialization
771 * sequence. until the controller will be LIVE, fail with
772 * BLK_STS_RESOURCE so that they will be rescheduled.
773 */
774 if (rq->q == ctrl->admin_q && (req->flags & NVME_REQ_USERCMD))
775 return false;
776
777 if (ctrl->ops->flags & NVME_F_FABRICS) {
778 /*
779 * Only allow commands on a live queue, except for the connect
780 * command, which is require to set the queue live in the
781 * appropinquate states.
782 */
6d3c7fb1 783 switch (state) {
a9715744
TC		 784 case NVME_CTRL_CONNECTING:
785 if (blk_rq_is_passthrough(rq) && nvme_is_fabrics(req->cmd) &&
f50fff73
HR		 786 (req->cmd->fabrics.fctype == nvme_fabrics_type_connect ||
787 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_send ||
788 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_receive))
a9715744
TC		 789 return true;
790 break;
791 default:
792 break;
793 case NVME_CTRL_DEAD:
794 return false;
795 }
796 }
797
798 return queue_live;
799}
800EXPORT_SYMBOL_GPL(__nvme_check_ready);
801
8093f7ca
ML		 802static inline void nvme_setup_flush(struct nvme_ns *ns,
803 struct nvme_command *cmnd)
804{
9c3d2929 805 memset(cmnd, 0, sizeof(*cmnd));
8093f7ca 806 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 807 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 808}
809
fc17b653 810static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 811 struct nvme_command *cmnd)
812{
b35ba01e 813 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 814 struct nvme_dsm_range *range;
b35ba01e 815 struct bio *bio;
8093f7ca 816
530436c4
EH		 817 /*
818 * Some devices do not consider the DSM 'Number of Ranges' field when
819 * determining how much data to DMA. Always allocate memory for maximum
820 * number of segments to prevent device reading beyond end of buffer.
821 */
822 static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES;
823
824 range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN);
cb5b7262
JA		 825 if (!range) {
826 /*
827 * If we fail allocation our range, fallback to the controller
828 * discard page. If that's also busy, it's safe to return
829 * busy, as we know we can make progress once that's freed.
830 */
831 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
832 return BLK_STS_RESOURCE;
833
834 range = page_address(ns->ctrl->discard_page);
835 }
8093f7ca 836
37f0dc2e 837 if (queue_max_discard_segments(req->q) == 1) {
0372dd4e 838 u64 slba = nvme_sect_to_lba(ns->head, blk_rq_pos(req));
9419e71b 839 u32 nlb = blk_rq_sectors(req) >> (ns->head->lba_shift - 9);
37f0dc2e
ML		 840
841 range[0].cattr = cpu_to_le32(0);
842 range[0].nlb = cpu_to_le32(nlb);
843 range[0].slba = cpu_to_le64(slba);
844 n = 1;
845 } else {
846 __rq_for_each_bio(bio, req) {
0372dd4e
DW		 847 u64 slba = nvme_sect_to_lba(ns->head,
848 bio->bi_iter.bi_sector);
9419e71b 849 u32 nlb = bio->bi_iter.bi_size >> ns->head->lba_shift;
37f0dc2e
ML		 850
851 if (n < segments) {
852 range[n].cattr = cpu_to_le32(0);
853 range[n].nlb = cpu_to_le32(nlb);
854 range[n].slba = cpu_to_le64(slba);
855 }
856 n++;
8cb6af7b 857 }
b35ba01e
CH		 858 }
859
860 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA		 861 if (virt_to_page(range) == ns->ctrl->discard_page)
862 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
863 else
864 kfree(range);
fc17b653 865 return BLK_STS_IOERR;
b35ba01e 866 }
8093f7ca 867
9c3d2929 868 memset(cmnd, 0, sizeof(*cmnd));
8093f7ca 869 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 870 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 871 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 872 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
873
4bee16da 874 bvec_set_virt(&req->special_vec, range, alloc_size);
f9d03f96 875 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 876
fc17b653 877 return BLK_STS_OK;
8093f7ca 878}
8093f7ca 879
4020aad8
KB		 880static void nvme_set_ref_tag(struct nvme_ns *ns, struct nvme_command *cmnd,
881 struct request *req)
882{
883 u32 upper, lower;
884 u64 ref48;
885
886 /* both rw and write zeroes share the same reftag format */
9419e71b 887 switch (ns->head->guard_type) {
4020aad8
KB		 888 case NVME_NVM_NS_16B_GUARD:
889 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
890 break;
891 case NVME_NVM_NS_64B_GUARD:
892 ref48 = ext_pi_ref_tag(req);
893 lower = lower_32_bits(ref48);
894 upper = upper_32_bits(ref48);
895
896 cmnd->rw.reftag = cpu_to_le32(lower);
897 cmnd->rw.cdw3 = cpu_to_le32(upper);
898 break;
899 default:
900 break;
901 }
902}
903
6e02318e
CK		 904static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
905 struct request *req, struct nvme_command *cmnd)
906{
9c3d2929
JA		 907 memset(cmnd, 0, sizeof(*cmnd));
908
6e02318e
CK		 909 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
910 return nvme_setup_discard(ns, req, cmnd);
911
912 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
913 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
914 cmnd->write_zeroes.slba =
0372dd4e 915 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req)));
6e02318e 916 cmnd->write_zeroes.length =
9419e71b 917 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1);
00b33cf3 918
9419e71b
DW		 919 if (!(req->cmd_flags & REQ_NOUNMAP) &&
920 (ns->head->features & NVME_NS_DEAC))
1b96f862
CH		 921 cmnd->write_zeroes.control |= cpu_to_le16(NVME_WZ_DEAC);
922
0372dd4e 923 if (nvme_ns_has_pi(ns->head)) {
1b96f862 924 cmnd->write_zeroes.control |= cpu_to_le16(NVME_RW_PRINFO_PRACT);
00b33cf3 925
9419e71b 926 switch (ns->head->pi_type) {
00b33cf3
KJ		 927 case NVME_NS_DPS_PI_TYPE1:
928 case NVME_NS_DPS_PI_TYPE2:
4020aad8 929 nvme_set_ref_tag(ns, cmnd, req);
00b33cf3
KJ		 930 break;
931 }
932 }
933
6e02318e
CK		 934 return BLK_STS_OK;
935}
936
ebe6d874 937static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
240e6ee2
KB		 938 struct request *req, struct nvme_command *cmnd,
939 enum nvme_opcode op)
8093f7ca
ML		 940{
941 u16 control = 0;
942 u32 dsmgmt = 0;
943
944 if (req->cmd_flags & REQ_FUA)
945 control |= NVME_RW_FUA;
946 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
947 control |= NVME_RW_LR;
948
949 if (req->cmd_flags & REQ_RAHEAD)
950 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
951
240e6ee2 952 cmnd->rw.opcode = op;
a9a7e30f 953 cmnd->rw.flags = 0;
ed754e5d 954 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
4020aad8
KB		 955 cmnd->rw.cdw2 = 0;
956 cmnd->rw.cdw3 = 0;
a9a7e30f 957 cmnd->rw.metadata = 0;
0372dd4e
DW		 958 cmnd->rw.slba =
959 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req)));
9419e71b
DW		 960 cmnd->rw.length =
961 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1);
a9a7e30f
JA		 962 cmnd->rw.reftag = 0;
963 cmnd->rw.apptag = 0;
964 cmnd->rw.appmask = 0;
8093f7ca 965
9419e71b 966 if (ns->head->ms) {
715ea9e0
CH		 967 /*
968 * If formated with metadata, the block layer always provides a
969 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
970 * we enable the PRACT bit for protection information or set the
971 * namespace capacity to zero to prevent any I/O.
972 */
973 if (!blk_integrity_rq(req)) {
0372dd4e 974 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns->head)))
715ea9e0
CH		 975 return BLK_STS_NOTSUPP;
976 control |= NVME_RW_PRINFO_PRACT;
977 }
978
9419e71b 979 switch (ns->head->pi_type) {
8093f7ca
ML		 980 case NVME_NS_DPS_PI_TYPE3:
981 control |= NVME_RW_PRINFO_PRCHK_GUARD;
982 break;
983 case NVME_NS_DPS_PI_TYPE1:
984 case NVME_NS_DPS_PI_TYPE2:
985 control |= NVME_RW_PRINFO_PRCHK_GUARD |
986 NVME_RW_PRINFO_PRCHK_REF;
240e6ee2
KB		 987 if (op == nvme_cmd_zone_append)
988 control |= NVME_RW_APPEND_PIREMAP;
4020aad8 989 nvme_set_ref_tag(ns, cmnd, req);
8093f7ca
ML		 990 break;
991 }
8093f7ca
ML		 992 }
993
994 cmnd->rw.control = cpu_to_le16(control);
995 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 996 return 0;
8093f7ca
ML		 997}
998
f7f1fc36
MG		 999void nvme_cleanup_cmd(struct request *req)
1000{
f7f1fc36 1001 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
fc97e942 1002 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
cb5b7262 1003
3973e15f 1004 if (req->special_vec.bv_page == ctrl->discard_page)
fc97e942 1005 clear_bit_unlock(0, &ctrl->discard_page_busy);
cb5b7262 1006 else
3973e15f 1007 kfree(bvec_virt(&req->special_vec));
f7f1fc36
MG		 1008 }
1009}
1010EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
1011
f4b9e6c9 1012blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req)
8093f7ca 1013{
f4b9e6c9 1014 struct nvme_command *cmd = nvme_req(req)->cmd;
fc17b653 1015 blk_status_t ret = BLK_STS_OK;
8093f7ca 1016
9c3d2929 1017 if (!(req->rq_flags & RQF_DONTPREP))
c03fd85d 1018 nvme_clear_nvme_request(req);
987f699a 1019
aebf526b
CH		 1020 switch (req_op(req)) {
1021 case REQ_OP_DRV_IN:
1022 case REQ_OP_DRV_OUT:
f4b9e6c9 1023 /* these are setup prior to execution in nvme_init_request() */
aebf526b
CH		 1024 break;
1025 case REQ_OP_FLUSH:
8093f7ca 1026 nvme_setup_flush(ns, cmd);
aebf526b 1027 break;
240e6ee2
KB		 1028 case REQ_OP_ZONE_RESET_ALL:
1029 case REQ_OP_ZONE_RESET:
1030 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET);
1031 break;
1032 case REQ_OP_ZONE_OPEN:
1033 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN);
1034 break;
1035 case REQ_OP_ZONE_CLOSE:
1036 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE);
1037 break;
1038 case REQ_OP_ZONE_FINISH:
1039 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH);
1040 break;
e850fd16 1041 case REQ_OP_WRITE_ZEROES:
6e02318e
CK		 1042 ret = nvme_setup_write_zeroes(ns, req, cmd);
1043 break;
aebf526b 1044 case REQ_OP_DISCARD:
8093f7ca 1045 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 1046 break;
1047 case REQ_OP_READ:
240e6ee2
KB		 1048 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read);
1049 break;
aebf526b 1050 case REQ_OP_WRITE:
240e6ee2
KB		 1051 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write);
1052 break;
1053 case REQ_OP_ZONE_APPEND:
1054 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append);
aebf526b
CH		 1055 break;
1056 default:
1057 WARN_ON_ONCE(1);
fc17b653 1058 return BLK_STS_IOERR;
aebf526b 1059 }
8093f7ca 1060
e7006de6 1061 cmd->common.command_id = nvme_cid(req);
5d87eb94 1062 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 1063 return ret;
1064}
1065EXPORT_SYMBOL_GPL(nvme_setup_cmd);
1066
ae5e6886
KB		 1067/*
1068 * Return values:
1069 * 0: success
1070 * >0: nvme controller's cqe status response
1071 * <0: kernel error in lieu of controller response
1072 */
62281b9e 1073int nvme_execute_rq(struct request *rq, bool at_head)
ae5e6886
KB		 1074{
1075 blk_status_t status;
1076
b84ba30b 1077 status = blk_execute_rq(rq, at_head);
ae5e6886
KB		 1078 if (nvme_req(rq)->flags & NVME_REQ_CANCELLED)
1079 return -EINTR;
1080 if (nvme_req(rq)->status)
1081 return nvme_req(rq)->status;
1082 return blk_status_to_errno(status);
1083}
62281b9e 1084EXPORT_SYMBOL_NS_GPL(nvme_execute_rq, NVME_TARGET_PASSTHRU);
ae5e6886 1085
4160982e
CH		 1086/*
1087 * Returns 0 on success. If the result is negative, it's a Linux error code;
1088 * if the result is positive, it's an NVM Express status code
1089 */
1090int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 1091 union nvme_result *result, void *buffer, unsigned bufflen,
bd2687f2 1092 int qid, nvme_submit_flags_t flags)
4160982e
CH		 1093{
1094 struct request *req;
1095 int ret;
bd2687f2 1096 blk_mq_req_flags_t blk_flags = 0;
4160982e 1097
bd2687f2
HR		 1098 if (flags & NVME_SUBMIT_NOWAIT)
1099 blk_flags |= BLK_MQ_REQ_NOWAIT;
1100 if (flags & NVME_SUBMIT_RESERVED)
1101 blk_flags |= BLK_MQ_REQ_RESERVED;
39dfe844 1102 if (qid == NVME_QID_ANY)
bd2687f2 1103 req = blk_mq_alloc_request(q, nvme_req_op(cmd), blk_flags);
39dfe844 1104 else
bd2687f2 1105 req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), blk_flags,
b10907b8 1106 qid - 1);
e559398f 1107
4160982e
CH		 1108 if (IS_ERR(req))
1109 return PTR_ERR(req);
e559398f 1110 nvme_init_request(req, cmd);
48dae466
HR		 1111 if (flags & NVME_SUBMIT_RETRY)
1112 req->cmd_flags &= ~REQ_FAILFAST_DRIVER;
4160982e 1113
21d34711
CH		 1114 if (buffer && bufflen) {
1115 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
1116 if (ret)
1117 goto out;
4160982e
CH		 1118 }
1119
bd2687f2 1120 ret = nvme_execute_rq(req, flags & NVME_SUBMIT_AT_HEAD);
ae5e6886 1121 if (result && ret >= 0)
d49187e9 1122 *result = nvme_req(req)->result;
4160982e
CH		 1123 out:
1124 blk_mq_free_request(req);
1125 return ret;
1126}
eb71f435 1127EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 1128
1129int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1130 void *buffer, unsigned bufflen)
1131{
6b46fa02 1132 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen,
bd2687f2 1133 NVME_QID_ANY, 0);
4160982e 1134}
576d55d6 1135EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 1136
df21b6b1
LG		 1137u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
1138{
1139 u32 effects = 0;
1140
1141 if (ns) {
cc115cbe 1142 effects = le32_to_cpu(ns->head->effects->iocs[opcode]);
df21b6b1 1143 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
ed4a854b 1144 dev_warn_once(ctrl->device,
831ed60c 1145 "IO command:%02x has unusual effects:%08x\n",
ed4a854b 1146 opcode, effects);
df21b6b1 1147
831ed60c
CH		 1148 /*
1149 * NVME_CMD_EFFECTS_CSE_MASK causes a freeze all I/O queues,
1150 * which would deadlock when done on an I/O command. Note that
1151 * We already warn about an unusual effect above.
1152 */
1153 effects &= ~NVME_CMD_EFFECTS_CSE_MASK;
1154 } else {
cc115cbe 1155 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
29f69753
KB		 1156
1157 /* Ignore execution restrictions if any relaxation bits are set */
1158 if (effects & NVME_CMD_EFFECTS_CSER_MASK)
1159 effects &= ~NVME_CMD_EFFECTS_CSE_MASK;
831ed60c 1160 }
df21b6b1
LG		 1161
1162 return effects;
1163}
1164EXPORT_SYMBOL_NS_GPL(nvme_command_effects, NVME_TARGET_PASSTHRU);
1165
62281b9e 1166u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
df21b6b1
LG		 1167{
1168 u32 effects = nvme_command_effects(ctrl, ns, opcode);
1169
1170 /*
1171 * For simplicity, IO to all namespaces is quiesced even if the command
1172 * effects say only one namespace is affected.
1173 */
af0f446d 1174 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG		 1175 mutex_lock(&ctrl->scan_lock);
1176 mutex_lock(&ctrl->subsys->lock);
1177 nvme_mpath_start_freeze(ctrl->subsys);
1178 nvme_mpath_wait_freeze(ctrl->subsys);
1179 nvme_start_freeze(ctrl);
1180 nvme_wait_freeze(ctrl);
1181 }
1182 return effects;
1183}
62281b9e 1184EXPORT_SYMBOL_NS_GPL(nvme_passthru_start, NVME_TARGET_PASSTHRU);
df21b6b1 1185
31a59782 1186void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects,
bc8fb906 1187 struct nvme_command *cmd, int status)
df21b6b1 1188{
af0f446d 1189 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG		 1190 nvme_unfreeze(ctrl);
1191 nvme_mpath_unfreeze(ctrl->subsys);
1192 mutex_unlock(&ctrl->subsys->lock);
df21b6b1
LG		 1193 mutex_unlock(&ctrl->scan_lock);
1194 }
1e37a307 1195 if (effects & NVME_CMD_EFFECTS_CCC) {
d0dd594b
BL		 1196 if (!test_and_set_bit(NVME_CTRL_DIRTY_CAPABILITY,
1197 &ctrl->flags)) {
1198 dev_info(ctrl->device,
1e37a307 1199"controller capabilities changed, reset may be required to take effect.\n");
d0dd594b 1200 }
1e37a307 1201 }
df21b6b1
LG		 1202 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) {
1203 nvme_queue_scan(ctrl);
1204 flush_work(&ctrl->scan_work);
1205 }
31a59782 1206 if (ns)
1207 return;
b58da2d2
TS		 1208
1209 switch (cmd->common.opcode) {
1210 case nvme_admin_set_features:
1211 switch (le32_to_cpu(cmd->common.cdw10) & 0xFF) {
1212 case NVME_FEAT_KATO:
1213 /*
1214 * Keep alive commands interval on the host should be
1215 * updated when KATO is modified by Set Features
1216 * commands.
1217 */
1218 if (!status)
1219 nvme_update_keep_alive(ctrl, cmd);
1220 break;
1221 default:
1222 break;
1223 }
1224 break;
1225 default:
1226 break;
1227 }
df21b6b1 1228}
bc8fb906 1229EXPORT_SYMBOL_NS_GPL(nvme_passthru_end, NVME_TARGET_PASSTHRU);
df21b6b1 1230
a70b81bd
HR		 1231/*
1232 * Recommended frequency for KATO commands per NVMe 1.4 section 7.12.1:
1233 *
1234 * The host should send Keep Alive commands at half of the Keep Alive Timeout
1235 * accounting for transport roundtrip times [..].
1236 */
ea4d453b
US		 1237static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl)
1238{
1239 unsigned long delay = ctrl->kato * HZ / 2;
1240
1241 /*
1242 * When using Traffic Based Keep Alive, we need to run
1243 * nvme_keep_alive_work at twice the normal frequency, as one
1244 * command completion can postpone sending a keep alive command
1245 * by up to twice the delay between runs.
1246 */
1247 if (ctrl->ctratt & NVME_CTRL_ATTR_TBKAS)
1248 delay /= 2;
1249 return delay;
1250}
1251
a70b81bd 1252static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl)
4160982e 1253{
136cfcb8
MD		 1254 unsigned long now = jiffies;
1255 unsigned long delay = nvme_keep_alive_work_period(ctrl);
1256 unsigned long ka_next_check_tm = ctrl->ka_last_check_time + delay;
1257
1258 if (time_after(now, ka_next_check_tm))
1259 delay = 0;
1260 else
1261 delay = ka_next_check_tm - now;
1262
1263 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay);
21d34711
CH		 1264}
1265
de671d61
JA		 1266static enum rq_end_io_ret nvme_keep_alive_end_io(struct request *rq,
1267 blk_status_t status)
038bd4cb
SG		 1268{
1269 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS		 1270 unsigned long flags;
1271 bool startka = false;
c7275ce6
US		 1272 unsigned long rtt = jiffies - (rq->deadline - rq->timeout);
1273 unsigned long delay = nvme_keep_alive_work_period(ctrl);
1274
1275 /*
1276 * Subtract off the keepalive RTT so nvme_keep_alive_work runs
1277 * at the desired frequency.
1278 */
1279 if (rtt <= delay) {
1280 delay -= rtt;
1281 } else {
1282 dev_warn(ctrl->device, "long keepalive RTT (%u ms)\n",
1283 jiffies_to_msecs(rtt));
1284 delay = 0;
1285 }
038bd4cb
SG		 1286
1287 blk_mq_free_request(rq);
1288
2a842aca 1289 if (status) {
038bd4cb 1290 dev_err(ctrl->device,
2a842aca
CH		 1291 "failed nvme_keep_alive_end_io error=%d\n",
1292 status);
de671d61 1293 return RQ_END_IO_NONE;
038bd4cb
SG		 1294 }
1295
774a9636 1296 ctrl->ka_last_check_time = jiffies;
6e3ca03e 1297 ctrl->comp_seen = false;
86880d64
JS		 1298 spin_lock_irqsave(&ctrl->lock, flags);
1299 if (ctrl->state == NVME_CTRL_LIVE ||
1300 ctrl->state == NVME_CTRL_CONNECTING)
1301 startka = true;
1302 spin_unlock_irqrestore(&ctrl->lock, flags);
1303 if (startka)
c7275ce6 1304 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay);
de671d61 1305 return RQ_END_IO_NONE;
038bd4cb
SG		 1306}
1307
038bd4cb
SG		 1308static void nvme_keep_alive_work(struct work_struct *work)
1309{
1310 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
1311 struct nvme_ctrl, ka_work);
6e3ca03e 1312 bool comp_seen = ctrl->comp_seen;
06c3c336 1313 struct request *rq;
6e3ca03e 1314
774a9636
US		 1315 ctrl->ka_last_check_time = jiffies;
1316
6e3ca03e
SG		 1317 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
1318 dev_dbg(ctrl->device,
1319 "reschedule traffic based keep-alive timer\n");
1320 ctrl->comp_seen = false;
a70b81bd 1321 nvme_queue_keep_alive_work(ctrl);
6e3ca03e
SG		 1322 return;
1323 }
038bd4cb 1324
e559398f
CH		 1325 rq = blk_mq_alloc_request(ctrl->admin_q, nvme_req_op(&ctrl->ka_cmd),
1326 BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT);
06c3c336 1327 if (IS_ERR(rq)) {
038bd4cb 1328 /* allocation failure, reset the controller */
985c5a32 1329 dev_err(ctrl->device, "keep-alive failed: %ld\n", PTR_ERR(rq));
39bdc590 1330 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 1331 return;
1332 }
e559398f 1333 nvme_init_request(rq, &ctrl->ka_cmd);
06c3c336
CH		 1334
1335 rq->timeout = ctrl->kato * HZ;
e2e53086 1336 rq->end_io = nvme_keep_alive_end_io;
06c3c336 1337 rq->end_io_data = ctrl;
e2e53086 1338 blk_execute_rq_nowait(rq, false);
038bd4cb
SG		 1339}
1340
00b683db 1341static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 1342{
1343 if (unlikely(ctrl->kato == 0))
1344 return;
1345
a70b81bd 1346 nvme_queue_keep_alive_work(ctrl);
038bd4cb 1347}
038bd4cb
SG		 1348
1349void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
1350{
1351 if (unlikely(ctrl->kato == 0))
1352 return;
1353
1354 cancel_delayed_work_sync(&ctrl->ka_work);
1355}
1356EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
1357
b58da2d2
TS		 1358static void nvme_update_keep_alive(struct nvme_ctrl *ctrl,
1359 struct nvme_command *cmd)
1360{
1361 unsigned int new_kato =
1362 DIV_ROUND_UP(le32_to_cpu(cmd->common.cdw11), 1000);
1363
1364 dev_info(ctrl->device,
1365 "keep alive interval updated from %u ms to %u ms\n",
1366 ctrl->kato * 1000 / 2, new_kato * 1000 / 2);
1367
1368 nvme_stop_keep_alive(ctrl);
1369 ctrl->kato = new_kato;
1370 nvme_start_keep_alive(ctrl);
1371}
1372
b9a5c3d4
CH		 1373/*
1374 * In NVMe 1.0 the CNS field was just a binary controller or namespace
1375 * flag, thus sending any new CNS opcodes has a big chance of not working.
1376 * Qemu unfortunately had that bug after reporting a 1.1 version compliance
1377 * (but not for any later version).
1378 */
1379static bool nvme_ctrl_limited_cns(struct nvme_ctrl *ctrl)
1380{
1381 if (ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)
1382 return ctrl->vs < NVME_VS(1, 2, 0);
1383 return ctrl->vs < NVME_VS(1, 1, 0);
1384}
1385
3f7f25a9 1386static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 1387{
1388 struct nvme_command c = { };
1389 int error;
1390
1391 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1392 c.identify.opcode = nvme_admin_identify;
986994a2 1393 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 1394
1395 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1396 if (!*id)
1397 return -ENOMEM;
1398
1399 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1400 sizeof(struct nvme_id_ctrl));
1401 if (error)
1402 kfree(*id);
1403 return error;
1404}
1405
ad95a613 1406static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids,
71010c30 1407 struct nvme_ns_id_desc *cur, bool *csi_seen)
ad95a613
CK		 1408{
1409 const char *warn_str = "ctrl returned bogus length:";
1410 void *data = cur;
1411
1412 switch (cur->nidt) {
1413 case NVME_NIDT_EUI64:
1414 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
1415 dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n",
1416 warn_str, cur->nidl);
1417 return -1;
1418 }
00ff400e
CH		 1419 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1420 return NVME_NIDT_EUI64_LEN;
ad95a613
CK		 1421 memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN);
1422 return NVME_NIDT_EUI64_LEN;
1423 case NVME_NIDT_NGUID:
1424 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
1425 dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n",
1426 warn_str, cur->nidl);
1427 return -1;
1428 }
00ff400e
CH		 1429 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1430 return NVME_NIDT_NGUID_LEN;
ad95a613
CK		 1431 memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN);
1432 return NVME_NIDT_NGUID_LEN;
1433 case NVME_NIDT_UUID:
1434 if (cur->nidl != NVME_NIDT_UUID_LEN) {
1435 dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n",
1436 warn_str, cur->nidl);
1437 return -1;
1438 }
00ff400e
CH		 1439 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1440 return NVME_NIDT_UUID_LEN;
ad95a613
CK		 1441 uuid_copy(&ids->uuid, data + sizeof(*cur));
1442 return NVME_NIDT_UUID_LEN;
71010c30
NC		 1443 case NVME_NIDT_CSI:
1444 if (cur->nidl != NVME_NIDT_CSI_LEN) {
1445 dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n",
1446 warn_str, cur->nidl);
1447 return -1;
1448 }
1449 memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN);
1450 *csi_seen = true;
1451 return NVME_NIDT_CSI_LEN;
ad95a613
CK		 1452 default:
1453 /* Skip unknown types */
1454 return cur->nidl;
1455 }
1456}
1457
1a893c2b
CH		 1458static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl,
1459 struct nvme_ns_info *info)
3b22ba26
JT		 1460{
1461 struct nvme_command c = { };
71010c30
NC		 1462 bool csi_seen = false;
1463 int status, pos, len;
3b22ba26 1464 void *data;
3b22ba26 1465
8b7c0ff2
CH		 1466 if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl))
1467 return 0;
5bedd3af
CH		 1468 if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST)
1469 return 0;
1470
3b22ba26 1471 c.identify.opcode = nvme_admin_identify;
1a893c2b 1472 c.identify.nsid = cpu_to_le32(info->nsid);
3b22ba26
JT		 1473 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1474
1475 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1476 if (!data)
1477 return -ENOMEM;
1478
cdbff4f2 1479 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26 1480 NVME_IDENTIFY_DATA_SIZE);
fb314eb0
CH		 1481 if (status) {
1482 dev_warn(ctrl->device,
aa9d7295 1483 "Identify Descriptors failed (nsid=%u, status=0x%x)\n",
1a893c2b 1484 info->nsid, status);
3b22ba26 1485 goto free_data;
fb314eb0 1486 }
3b22ba26
JT		 1487
1488 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1489 struct nvme_ns_id_desc *cur = data + pos;
1490
1491 if (cur->nidl == 0)
1492 break;
1493
1a893c2b 1494 len = nvme_process_ns_desc(ctrl, &info->ids, cur, &csi_seen);
ad95a613 1495 if (len < 0)
71010c30 1496 break;
3b22ba26
JT		 1497
1498 len += sizeof(*cur);
1499 }
71010c30
NC		 1500
1501 if (nvme_multi_css(ctrl) && !csi_seen) {
1502 dev_warn(ctrl->device, "Command set not reported for nsid:%d\n",
1a893c2b 1503 info->nsid);
71010c30
NC		 1504 status = -EINVAL;
1505 }
1506
3b22ba26
JT		 1507free_data:
1508 kfree(data);
1509 return status;
1510}
1511
a1a825ab 1512int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid,
1a893c2b 1513 struct nvme_id_ns **id)
21d34711
CH		 1514{
1515 struct nvme_command c = { };
1516 int error;
1517
1518 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 1519 c.identify.opcode = nvme_admin_identify;
1520 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1521 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1522
331813f6
SG		 1523 *id = kmalloc(sizeof(**id), GFP_KERNEL);
1524 if (!*id)
1525 return -ENOMEM;
21d34711 1526
331813f6 1527 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id));
cdbff4f2 1528 if (error) {
d0de579c 1529 dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error);
0dd6fff2 1530 kfree(*id);
cdbff4f2 1531 }
1a893c2b
CH		 1532 return error;
1533}
00ff400e 1534
1a893c2b
CH		 1535static int nvme_ns_info_from_identify(struct nvme_ctrl *ctrl,
1536 struct nvme_ns_info *info)
1537{
1538 struct nvme_ns_ids *ids = &info->ids;
1539 struct nvme_id_ns *id;
1540 int ret;
1541
1542 ret = nvme_identify_ns(ctrl, info->nsid, &id);
1543 if (ret)
1544 return ret;
0dd6fff2
CH		 1545
1546 if (id->ncap == 0) {
1547 /* namespace not allocated or attached */
1548 info->is_removed = true;
e3139cef
ML		 1549 ret = -ENODEV;
1550 goto error;
0dd6fff2
CH		 1551 }
1552
1a893c2b
CH		 1553 info->anagrpid = id->anagrpid;
1554 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED;
1e4ea66a 1555 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO;
1a893c2b 1556 info->is_ready = true;
00ff400e
CH		 1557 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) {
1558 dev_info(ctrl->device,
1559 "Ignoring bogus Namespace Identifiers\n");
1560 } else {
1561 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
1562 !memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
1a893c2b 1563 memcpy(ids->eui64, id->eui64, sizeof(ids->eui64));
00ff400e
CH		 1564 if (ctrl->vs >= NVME_VS(1, 2, 0) &&
1565 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
1a893c2b 1566 memcpy(ids->nguid, id->nguid, sizeof(ids->nguid));
00ff400e 1567 }
e3139cef
ML		 1568
1569error:
1a893c2b 1570 kfree(id);
e3139cef 1571 return ret;
21d34711
CH		 1572}
1573
1a893c2b
CH		 1574static int nvme_ns_info_from_id_cs_indep(struct nvme_ctrl *ctrl,
1575 struct nvme_ns_info *info)
354201c5 1576{
1a893c2b 1577 struct nvme_id_ns_cs_indep *id;
354201c5
CH		 1578 struct nvme_command c = {
1579 .identify.opcode = nvme_admin_identify,
1a893c2b 1580 .identify.nsid = cpu_to_le32(info->nsid),
354201c5
CH		 1581 .identify.cns = NVME_ID_CNS_NS_CS_INDEP,
1582 };
1583 int ret;
1584
1a893c2b
CH		 1585 id = kmalloc(sizeof(*id), GFP_KERNEL);
1586 if (!id)
354201c5
CH		 1587 return -ENOMEM;
1588
1a893c2b
CH		 1589 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
1590 if (!ret) {
1591 info->anagrpid = id->anagrpid;
1592 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED;
1e4ea66a 1593 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO;
1a893c2b 1594 info->is_ready = id->nstat & NVME_NSTAT_NRDY;
354201c5 1595 }
1a893c2b
CH		 1596 kfree(id);
1597 return ret;
354201c5
CH		 1598}
1599
1a87ee65
KB		 1600static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
1601 unsigned int dword11, void *buffer, size_t buflen, u32 *result)
21d34711 1602{
15755854 1603 union nvme_result res = { 0 };
cc72c442 1604 struct nvme_command c = { };
1cb3cce5 1605 int ret;
21d34711 1606
1a87ee65 1607 c.features.opcode = op;
21d34711
CH		 1608 c.features.fid = cpu_to_le32(fid);
1609 c.features.dword11 = cpu_to_le32(dword11);
1610
d49187e9 1611 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
bd2687f2 1612 buffer, buflen, NVME_QID_ANY, 0);
9b47f77a 1613 if (ret >= 0 && result)
d49187e9 1614 *result = le32_to_cpu(res.u32);
1cb3cce5 1615 return ret;
21d34711
CH		 1616}
1617
1a87ee65
KB		 1618int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
1619 unsigned int dword11, void *buffer, size_t buflen,
1620 u32 *result)
1621{
1622 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer,
1623 buflen, result);
1624}
1625EXPORT_SYMBOL_GPL(nvme_set_features);
1626
1627int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
1628 unsigned int dword11, void *buffer, size_t buflen,
1629 u32 *result)
1630{
1631 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer,
1632 buflen, result);
1633}
1634EXPORT_SYMBOL_GPL(nvme_get_features);
1635
9a0be7ab
CH		 1636int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1637{
1638 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1639 u32 result;
1640 int status, nr_io_queues;
1641
1a6fe74d 1642 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1643 &result);
f5fa90dc 1644 if (status < 0)
9a0be7ab
CH		 1645 return status;
1646
f5fa90dc
CH		 1647 /*
1648 * Degraded controllers might return an error when setting the queue
1649 * count. We still want to be able to bring them online and offer
1650 * access to the admin queue, as that might be only way to fix them up.
1651 */
1652 if (status > 0) {
f0425db0 1653 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1654 *count = 0;
1655 } else {
1656 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1657 *count = min(*count, nr_io_queues);
1658 }
1659
9a0be7ab
CH		 1660 return 0;
1661}
576d55d6 1662EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1663
c0561f82 1664#define NVME_AEN_SUPPORTED \
85f8a435
SG		 1665 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \
1666 NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE)
c0561f82
HR		 1667
1668static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1669{
fa441b71 1670 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR		 1671 int status;
1672
fa441b71
WZ		 1673 if (!supported_aens)
1674 return;
1675
1676 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1677 NULL, 0, &result);
c0561f82
HR		 1678 if (status)
1679 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1680 supported_aens);
93da4023
SG		 1681
1682 queue_work(nvme_wq, &ctrl->async_event_work);
c0561f82
HR		 1683}
1684
f5b9a51d 1685static int nvme_ns_open(struct nvme_ns *ns)
c225b610 1686{
c225b610 1687
32acab31 1688 /* should never be called due to GENHD_FL_HIDDEN */
30897388 1689 if (WARN_ON_ONCE(nvme_ns_head_multipath(ns->head)))
85088c4a 1690 goto fail;
4c74d1f8 1691 if (!nvme_get_ns(ns))
85088c4a
NC		 1692 goto fail;
1693 if (!try_module_get(ns->ctrl->ops->module))
1694 goto fail_put_ns;
1695
c6424a90 1696 return 0;
85088c4a
NC		 1697
1698fail_put_ns:
1699 nvme_put_ns(ns);
1700fail:
1701 return -ENXIO;
1673f1f0
CH		 1702}
1703
f5b9a51d 1704static void nvme_ns_release(struct nvme_ns *ns)
1673f1f0 1705{
85088c4a
NC		 1706
1707 module_put(ns->ctrl->ops->module);
1708 nvme_put_ns(ns);
1673f1f0
CH		 1709}
1710
05bdb996 1711static int nvme_open(struct gendisk *disk, blk_mode_t mode)
f5b9a51d 1712{
d32e2bf8 1713 return nvme_ns_open(disk->private_data);
f5b9a51d
CH		 1714}
1715
ae220766 1716static void nvme_release(struct gendisk *disk)
f5b9a51d
CH		 1717{
1718 nvme_ns_release(disk->private_data);
1719}
1720
1496bd49 1721int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1673f1f0
CH		 1722{
1723 /* some standard values */
1724 geo->heads = 1 << 6;
1725 geo->sectors = 1 << 5;
1726 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1727 return 0;
1728}
1729
1730#ifdef CONFIG_BLK_DEV_INTEGRITY
d386aedc
DW		 1731static void nvme_init_integrity(struct gendisk *disk,
1732 struct nvme_ns_head *head, u32 max_integrity_segments)
1673f1f0 1733{
cc72c442 1734 struct blk_integrity integrity = { };
1673f1f0 1735
d386aedc 1736 switch (head->pi_type) {
1673f1f0 1737 case NVME_NS_DPS_PI_TYPE3:
d386aedc 1738 switch (head->guard_type) {
4020aad8
KB		 1739 case NVME_NVM_NS_16B_GUARD:
1740 integrity.profile = &t10_pi_type3_crc;
1741 integrity.tag_size = sizeof(u16) + sizeof(u32);
1742 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1743 break;
1744 case NVME_NVM_NS_64B_GUARD:
1745 integrity.profile = &ext_pi_type3_crc64;
1746 integrity.tag_size = sizeof(u16) + 6;
1747 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1748 break;
1749 default:
1750 integrity.profile = NULL;
1751 break;
1752 }
1673f1f0
CH		 1753 break;
1754 case NVME_NS_DPS_PI_TYPE1:
1755 case NVME_NS_DPS_PI_TYPE2:
d386aedc 1756 switch (head->guard_type) {
4020aad8
KB		 1757 case NVME_NVM_NS_16B_GUARD:
1758 integrity.profile = &t10_pi_type1_crc;
1759 integrity.tag_size = sizeof(u16);
1760 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1761 break;
1762 case NVME_NVM_NS_64B_GUARD:
1763 integrity.profile = &ext_pi_type1_crc64;
1764 integrity.tag_size = sizeof(u16);
1765 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1766 break;
1767 default:
1768 integrity.profile = NULL;
1769 break;
1770 }
1673f1f0
CH		 1771 break;
1772 default:
1773 integrity.profile = NULL;
1774 break;
1775 }
4020aad8 1776
d386aedc 1777 integrity.tuple_size = head->ms;
39b7baa4 1778 blk_integrity_register(disk, &integrity);
95093350 1779 blk_queue_max_integrity_segments(disk->queue, max_integrity_segments);
1673f1f0
CH		 1780}
1781#else
d386aedc
DW		 1782static void nvme_init_integrity(struct gendisk *disk,
1783 struct nvme_ns_head *head, u32 max_integrity_segments)
1673f1f0
CH		 1784{
1785}
1786#endif /* CONFIG_BLK_DEV_INTEGRITY */
1787
d386aedc
DW		 1788static void nvme_config_discard(struct nvme_ctrl *ctrl, struct gendisk *disk,
1789 struct nvme_ns_head *head)
1673f1f0 1790{
26318571 1791 struct request_queue *queue = disk->queue;
f29886c2 1792 u32 max_discard_sectors;
30e5e929 1793
f29886c2
CH		 1794 if (ctrl->dmrsl && ctrl->dmrsl <= nvme_sect_to_lba(head, UINT_MAX)) {
1795 max_discard_sectors = nvme_lba_to_sect(head, ctrl->dmrsl);
1796 } else if (ctrl->oncs & NVME_CTRL_ONCS_DSM) {
1797 max_discard_sectors = UINT_MAX;
1798 } else {
70200574 1799 blk_queue_max_discard_sectors(queue, 0);
3831761e
JA		 1800 return;
1801 }
1802
b35ba01e
CH		 1803 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1804 NVME_DSM_MAX_RANGES);
1805
d3074e9a
CH		 1806 /*
1807 * If discard is already enabled, don't reset queue limits.
1808 *
1809 * This works around the fact that the block layer can't cope well with
1810 * updating the hardware limits when overridden through sysfs. This is
1811 * harmless because discard limits in NVMe are purely advisory.
1812 */
70200574 1813 if (queue->limits.max_discard_sectors)
3831761e
JA		 1814 return;
1815
f29886c2 1816 blk_queue_max_discard_sectors(queue, max_discard_sectors);
3b946fe1
CH		 1817 if (ctrl->dmrl)
1818 blk_queue_max_discard_segments(queue, ctrl->dmrl);
1819 else
1820 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
a4be9679 1821 queue->limits.discard_granularity = queue_logical_block_size(queue);
e850fd16
CH		 1822
1823 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1824 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1825}
1826
002fab04
CH		 1827static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1828{
1829 return uuid_equal(&a->uuid, &b->uuid) &&
1830 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
71010c30
NC		 1831 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 &&
1832 a->csi == b->csi;
002fab04
CH		 1833}
1834
d386aedc
DW		 1835static int nvme_init_ms(struct nvme_ctrl *ctrl, struct nvme_ns_head *head,
1836 struct nvme_id_ns *id)
d4609ea8 1837{
4020aad8
KB		 1838 bool first = id->dps & NVME_NS_DPS_PI_FIRST;
1839 unsigned lbaf = nvme_lbaf_index(id->flbas);
4020aad8
KB		 1840 struct nvme_command c = { };
1841 struct nvme_id_ns_nvm *nvm;
1842 int ret = 0;
1843 u32 elbaf;
1844
d386aedc
DW		 1845 head->pi_size = 0;
1846 head->ms = le16_to_cpu(id->lbaf[lbaf].ms);
4020aad8 1847 if (!(ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)) {
d386aedc
DW		 1848 head->pi_size = sizeof(struct t10_pi_tuple);
1849 head->guard_type = NVME_NVM_NS_16B_GUARD;
4020aad8
KB		 1850 goto set_pi;
1851 }
d4609ea8 1852
4020aad8
KB		 1853 nvm = kzalloc(sizeof(*nvm), GFP_KERNEL);
1854 if (!nvm)
1855 return -ENOMEM;
d4609ea8 1856
4020aad8 1857 c.identify.opcode = nvme_admin_identify;
d386aedc 1858 c.identify.nsid = cpu_to_le32(head->ns_id);
4020aad8
KB		 1859 c.identify.cns = NVME_ID_CNS_CS_NS;
1860 c.identify.csi = NVME_CSI_NVM;
1861
d386aedc 1862 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, nvm, sizeof(*nvm));
4020aad8
KB		 1863 if (ret)
1864 goto free_data;
1865
1866 elbaf = le32_to_cpu(nvm->elbaf[lbaf]);
1867
1868 /* no support for storage tag formats right now */
1869 if (nvme_elbaf_sts(elbaf))
1870 goto free_data;
1871
d386aedc
DW		 1872 head->guard_type = nvme_elbaf_guard_type(elbaf);
1873 switch (head->guard_type) {
4020aad8 1874 case NVME_NVM_NS_64B_GUARD:
d386aedc 1875 head->pi_size = sizeof(struct crc64_pi_tuple);
4020aad8
KB		 1876 break;
1877 case NVME_NVM_NS_16B_GUARD:
d386aedc 1878 head->pi_size = sizeof(struct t10_pi_tuple);
4020aad8
KB		 1879 break;
1880 default:
1881 break;
1882 }
1883
1884free_data:
1885 kfree(nvm);
1886set_pi:
d386aedc
DW		 1887 if (head->pi_size && (first || head->ms == head->pi_size))
1888 head->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
d4609ea8 1889 else
d386aedc 1890 head->pi_type = 0;
d4609ea8 1891
4020aad8
KB		 1892 return ret;
1893}
1894
d386aedc
DW		 1895static int nvme_configure_metadata(struct nvme_ctrl *ctrl,
1896 struct nvme_ns_head *head, struct nvme_id_ns *id)
4020aad8 1897{
cd9aed60 1898 int ret;
4020aad8 1899
d386aedc 1900 ret = nvme_init_ms(ctrl, head, id);
cd9aed60
HR		 1901 if (ret)
1902 return ret;
4020aad8 1903
d386aedc
DW		 1904 head->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS);
1905 if (!head->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
cd9aed60 1906 return 0;
363f6368 1907
d4609ea8
CH		 1908 if (ctrl->ops->flags & NVME_F_FABRICS) {
1909 /*
1910 * The NVMe over Fabrics specification only supports metadata as
1911 * part of the extended data LBA. We rely on HCA/HBA support to
1912 * remap the separate metadata buffer from the block layer.
1913 */
1914 if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT)))
cd9aed60 1915 return 0;
d39ad2a4 1916
d386aedc 1917 head->features |= NVME_NS_EXT_LBAS;
d39ad2a4
KB		 1918
1919 /*
1920 * The current fabrics transport drivers support namespace
1921 * metadata formats only if nvme_ns_has_pi() returns true.
1922 * Suppress support for all other formats so the namespace will
1923 * have a 0 capacity and not be usable through the block stack.
1924 *
1925 * Note, this check will need to be modified if any drivers
1926 * gain the ability to use other metadata formats.
1927 */
d386aedc
DW		 1928 if (ctrl->max_integrity_segments && nvme_ns_has_pi(head))
1929 head->features |= NVME_NS_METADATA_SUPPORTED;
d4609ea8
CH		 1930 } else {
1931 /*
1932 * For PCIe controllers, we can't easily remap the separate
1933 * metadata buffer from the block layer and thus require a
1934 * separate metadata buffer for block layer metadata/PI support.
1935 * We allow extended LBAs for the passthrough interface, though.
1936 */
1937 if (id->flbas & NVME_NS_FLBAS_META_EXT)
d386aedc 1938 head->features |= NVME_NS_EXT_LBAS;
d4609ea8 1939 else
d386aedc 1940 head->features |= NVME_NS_METADATA_SUPPORTED;
d4609ea8 1941 }
cd9aed60 1942 return 0;
d4609ea8
CH		 1943}
1944
658d9f7c
CH		 1945static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1946 struct request_queue *q)
1947{
c4485252 1948 bool vwc = ctrl->vwc & NVME_CTRL_VWC_PRESENT;
658d9f7c
CH		 1949
1950 if (ctrl->max_hw_sectors) {
1951 u32 max_segments =
1952 (ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> 9)) + 1;
1953
1954 max_segments = min_not_zero(max_segments, ctrl->max_segments);
1955 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
1956 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
1957 }
1958 blk_queue_virt_boundary(q, NVME_CTRL_PAGE_SIZE - 1);
52fde2c0 1959 blk_queue_dma_alignment(q, 3);
658d9f7c
CH		 1960 blk_queue_write_cache(q, vwc, vwc);
1961}
1962
d386aedc
DW		 1963static void nvme_update_disk_info(struct nvme_ctrl *ctrl, struct gendisk *disk,
1964 struct nvme_ns_head *head, struct nvme_id_ns *id)
24b0b58c 1965{
d386aedc
DW		 1966 sector_t capacity = nvme_lba_to_sect(head, le64_to_cpu(id->nsze));
1967 u32 bs = 1U << head->lba_shift;
68ab60ca 1968 u32 atomic_bs, phys_bs, io_opt = 0;
24b0b58c 1969
13f0b26b
CH		 1970 /*
1971 * The block layer can't support LBA sizes larger than the page size
74fbc88e
KB		 1972 * or smaller than a sector size yet, so catch this early and don't
1973 * allow block I/O.
13f0b26b 1974 */
01d550f0 1975 if (head->lba_shift > PAGE_SHIFT || head->lba_shift < SECTOR_SHIFT) {
13f0b26b 1976 capacity = 0;
01fa0174
SG		 1977 bs = (1 << 9);
1978 }
f9d5f457 1979
24b0b58c
CH		 1980 blk_integrity_unregister(disk);
1981
68ab60ca 1982 atomic_bs = phys_bs = bs;
81adb863
BVA		 1983 if (id->nabo == 0) {
1984 /*
1985 * Bit 1 indicates whether NAWUPF is defined for this namespace
1986 * and whether it should be used instead of AWUPF. If NAWUPF ==
1987 * 0 then AWUPF must be used instead.
1988 */
92decf11 1989 if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf)
81adb863
BVA		 1990 atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs;
1991 else
d386aedc 1992 atomic_bs = (1 + ctrl->subsys->awupf) * bs;
81adb863 1993 }
31fdad7b 1994
92decf11 1995 if (id->nsfeat & NVME_NS_FEAT_IO_OPT) {
81adb863 1996 /* NPWG = Namespace Preferred Write Granularity */
31fdad7b 1997 phys_bs = bs * (1 + le16_to_cpu(id->npwg));
81adb863 1998 /* NOWS = Namespace Optimal Write Size */
31fdad7b 1999 io_opt = bs * (1 + le16_to_cpu(id->nows));
81adb863
BVA		 2000 }
2001
cee160fd 2002 blk_queue_logical_block_size(disk->queue, bs);
81adb863
BVA		 2003 /*
2004 * Linux filesystems assume writing a single physical block is
2005 * an atomic operation. Hence limit the physical block size to the
2006 * value of the Atomic Write Unit Power Fail parameter.
2007 */
2008 blk_queue_physical_block_size(disk->queue, min(phys_bs, atomic_bs));
2009 blk_queue_io_min(disk->queue, phys_bs);
2010 blk_queue_io_opt(disk->queue, io_opt);
cee160fd 2011
b29f8485
MG		 2012 /*
2013 * Register a metadata profile for PI, or the plain non-integrity NVMe
2014 * metadata masquerading as Type 0 if supported, otherwise reject block
2015 * I/O to namespaces with metadata except when the namespace supports
2016 * PI, as it can strip/insert in that case.
2017 */
d386aedc 2018 if (head->ms) {
b29f8485 2019 if (IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) &&
d386aedc
DW		 2020 (head->features & NVME_NS_METADATA_SUPPORTED))
2021 nvme_init_integrity(disk, head,
2022 ctrl->max_integrity_segments);
2023 else if (!nvme_ns_has_pi(head))
b29f8485
MG		 2024 capacity = 0;
2025 }
2026
449f4ec9 2027 set_capacity_and_notify(disk, capacity);
b1aafb35 2028
d386aedc 2029 nvme_config_discard(ctrl, disk, head);
5befc7c2 2030 blk_queue_max_write_zeroes_sectors(disk->queue,
d386aedc 2031 ctrl->max_zeroes_sectors);
24b0b58c
CH		 2032}
2033
1e4ea66a
CH		 2034static bool nvme_ns_is_readonly(struct nvme_ns *ns, struct nvme_ns_info *info)
2035{
2036 return info->is_readonly || test_bit(NVME_NS_FORCE_RO, &ns->flags);
2037}
2038
e83d776f
KB		 2039static inline bool nvme_first_scan(struct gendisk *disk)
2040{
2041 /* nvme_alloc_ns() scans the disk prior to adding it */
50b4aecf 2042 return !disk_live(disk);
e83d776f
KB		 2043}
2044
2045static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id)
2046{
2047 struct nvme_ctrl *ctrl = ns->ctrl;
2048 u32 iob;
2049
2050 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
2051 is_power_of_2(ctrl->max_hw_sectors))
2052 iob = ctrl->max_hw_sectors;
2053 else
0372dd4e 2054 iob = nvme_lba_to_sect(ns->head, le16_to_cpu(id->noiob));
e83d776f
KB		 2055
2056 if (!iob)
2057 return;
2058
2059 if (!is_power_of_2(iob)) {
2060 if (nvme_first_scan(ns->disk))
2061 pr_warn("%s: ignoring unaligned IO boundary:%u\n",
2062 ns->disk->disk_name, iob);
2063 return;
2064 }
2065
2066 if (blk_queue_is_zoned(ns->disk->queue)) {
2067 if (nvme_first_scan(ns->disk))
2068 pr_warn("%s: ignoring zoned namespace IO boundary\n",
2069 ns->disk->disk_name);
2070 return;
2071 }
2072
2073 blk_queue_chunk_sectors(ns->queue, iob);
2074}
2075
eb867ee9
JG		 2076static int nvme_update_ns_info_generic(struct nvme_ns *ns,
2077 struct nvme_ns_info *info)
2078{
2079 blk_mq_freeze_queue(ns->disk->queue);
2080 nvme_set_queue_limits(ns->ctrl, ns->queue);
2081 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info));
2082 blk_mq_unfreeze_queue(ns->disk->queue);
2083
2084 if (nvme_ns_head_multipath(ns->head)) {
2085 blk_mq_freeze_queue(ns->head->disk->queue);
2086 set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info));
2087 nvme_mpath_revalidate_paths(ns);
2088 blk_stack_limits(&ns->head->disk->queue->limits,
2089 &ns->queue->limits, 0);
2090 ns->head->disk->flags |= GENHD_FL_HIDDEN;
2091 blk_mq_unfreeze_queue(ns->head->disk->queue);
2092 }
2093
2094 /* Hide the block-interface for these devices */
2095 ns->disk->flags |= GENHD_FL_HIDDEN;
2096 set_bit(NVME_NS_READY, &ns->flags);
2097
2098 return 0;
2099}
2100
1a893c2b
CH		 2101static int nvme_update_ns_info_block(struct nvme_ns *ns,
2102 struct nvme_ns_info *info)
ac81bfa9 2103{
1a893c2b
CH		 2104 struct nvme_id_ns *id;
2105 unsigned lbaf;
240e6ee2 2106 int ret;
1673f1f0 2107
1a893c2b
CH		 2108 ret = nvme_identify_ns(ns->ctrl, info->nsid, &id);
2109 if (ret)
2110 return ret;
2111
d8b90d60
EM		 2112 if (id->ncap == 0) {
2113 /* namespace not allocated or attached */
2114 info->is_removed = true;
2115 ret = -ENODEV;
2116 goto error;
2117 }
2118
f9d5f457 2119 blk_mq_freeze_queue(ns->disk->queue);
1a893c2b 2120 lbaf = nvme_lbaf_index(id->flbas);
9419e71b 2121 ns->head->lba_shift = id->lbaf[lbaf].ds;
a1a825ab 2122 ns->head->nuse = le64_to_cpu(id->nuse);
8b7c0ff2 2123 nvme_set_queue_limits(ns->ctrl, ns->queue);
38adf94e 2124
d386aedc 2125 ret = nvme_configure_metadata(ns->ctrl, ns->head, id);
cd9aed60
HR		 2126 if (ret < 0) {
2127 blk_mq_unfreeze_queue(ns->disk->queue);
2128 goto out;
2129 }
73d90386 2130 nvme_set_chunk_sectors(ns, id);
d386aedc 2131 nvme_update_disk_info(ns->ctrl, ns->disk, ns->head, id);
73d90386 2132
8b7c0ff2 2133 if (ns->head->ids.csi == NVME_CSI_ZNS) {
d525c3c0 2134 ret = nvme_update_zone_info(ns, lbaf);
e06b425b
CH		 2135 if (ret) {
2136 blk_mq_unfreeze_queue(ns->disk->queue);
2137 goto out;
2138 }
71010c30
NC		 2139 }
2140
1b96f862
CH		 2141 /*
2142 * Only set the DEAC bit if the device guarantees that reads from
2143 * deallocated data return zeroes. While the DEAC bit does not
2144 * require that, it must be a no-op if reads from deallocated data
2145 * do not return zeroes.
2146 */
2147 if ((id->dlfeat & 0x7) == 0x1 && (id->dlfeat & (1 << 3)))
9419e71b 2148 ns->head->features |= NVME_NS_DEAC;
1e4ea66a 2149 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info));
e7d65803 2150 set_bit(NVME_NS_READY, &ns->flags);
f9d5f457 2151 blk_mq_unfreeze_queue(ns->disk->queue);
1673f1f0 2152
3a9967ba
CH		 2153 if (blk_queue_is_zoned(ns->queue)) {
2154 ret = nvme_revalidate_zones(ns);
8685699c 2155 if (ret && !nvme_first_scan(ns->disk))
e06b425b 2156 goto out;
b29f8485
MG		 2157 }
2158
30897388 2159 if (nvme_ns_head_multipath(ns->head)) {
f9d5f457 2160 blk_mq_freeze_queue(ns->head->disk->queue);
d386aedc 2161 nvme_update_disk_info(ns->ctrl, ns->head->disk, ns->head, id);
1e4ea66a 2162 set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info));
e7d65803 2163 nvme_mpath_revalidate_paths(ns);
b9b1a5d7
CH		 2164 blk_stack_limits(&ns->head->disk->queue->limits,
2165 &ns->queue->limits, 0);
471aa704 2166 disk_update_readahead(ns->head->disk);
f9d5f457 2167 blk_mq_unfreeze_queue(ns->head->disk->queue);
8f676b85 2168 }
ac81bfa9 2169
e06b425b
CH		 2170 ret = 0;
2171out:
a9e0e6bc
CH		 2172 /*
2173 * If probing fails due an unsupported feature, hide the block device,
2174 * but still allow other access.
2175 */
2176 if (ret == -ENODEV) {
2177 ns->disk->flags |= GENHD_FL_HIDDEN;
602e57c9 2178 set_bit(NVME_NS_READY, &ns->flags);
a9e0e6bc
CH		 2179 ret = 0;
2180 }
d8b90d60
EM		 2181
2182error:
1a893c2b 2183 kfree(id);
240e6ee2
KB		 2184 return ret;
2185}
2186
1a893c2b
CH		 2187static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_ns_info *info)
2188{
2189 switch (info->ids.csi) {
2190 case NVME_CSI_ZNS:
2191 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
eb867ee9
JG		 2192 dev_info(ns->ctrl->device,
2193 "block device for nsid %u not supported without CONFIG_BLK_DEV_ZONED\n",
1a893c2b 2194 info->nsid);
eb867ee9 2195 return nvme_update_ns_info_generic(ns, info);
1a893c2b
CH		 2196 }
2197 return nvme_update_ns_info_block(ns, info);
2198 case NVME_CSI_NVM:
2199 return nvme_update_ns_info_block(ns, info);
2200 default:
eb867ee9
JG		 2201 dev_info(ns->ctrl->device,
2202 "block device for nsid %u not supported (csi %u)\n",
2203 info->nsid, info->ids.csi);
2204 return nvme_update_ns_info_generic(ns, info);
1a893c2b
CH		 2205 }
2206}
2207
a98e58e5 2208#ifdef CONFIG_BLK_SED_OPAL
94cc781f 2209static int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
4f1244c8 2210 bool send)
a98e58e5 2211{
4f1244c8 2212 struct nvme_ctrl *ctrl = data;
cc72c442 2213 struct nvme_command cmd = { };
a98e58e5 2214
a98e58e5
SB		 2215 if (send)
2216 cmd.common.opcode = nvme_admin_security_send;
2217 else
2218 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 2219 cmd.common.nsid = 0;
b7c8f366
CK		 2220 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
2221 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5 2222
6b46fa02 2223 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
bd2687f2 2224 NVME_QID_ANY, NVME_SUBMIT_AT_HEAD);
a98e58e5 2225}
94cc781f
CH		 2226
2227static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended)
2228{
2229 if (ctrl->oacs & NVME_CTRL_OACS_SEC_SUPP) {
2230 if (!ctrl->opal_dev)
2231 ctrl->opal_dev = init_opal_dev(ctrl, &nvme_sec_submit);
2232 else if (was_suspended)
2233 opal_unlock_from_suspend(ctrl->opal_dev);
2234 } else {
2235 free_opal_dev(ctrl->opal_dev);
2236 ctrl->opal_dev = NULL;
2237 }
2238}
2239#else
2240static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended)
2241{
2242}
a98e58e5
SB		 2243#endif /* CONFIG_BLK_SED_OPAL */
2244
8b4fb0f9
CH		 2245#ifdef CONFIG_BLK_DEV_ZONED
2246static int nvme_report_zones(struct gendisk *disk, sector_t sector,
2247 unsigned int nr_zones, report_zones_cb cb, void *data)
2248{
2249 return nvme_ns_report_zones(disk->private_data, sector, nr_zones, cb,
2250 data);
2251}
2252#else
2253#define nvme_report_zones NULL
2254#endif /* CONFIG_BLK_DEV_ZONED */
2255
942e21c0 2256const struct block_device_operations nvme_bdev_ops = {
1673f1f0
CH		 2257 .owner = THIS_MODULE,
2258 .ioctl = nvme_ioctl,
a25d4261 2259 .compat_ioctl = blkdev_compat_ptr_ioctl,
1673f1f0
CH		 2260 .open = nvme_open,
2261 .release = nvme_release,
2262 .getgeo = nvme_getgeo,
240e6ee2 2263 .report_zones = nvme_report_zones,
1673f1f0
CH		 2264 .pr_ops = &nvme_pr_ops,
2265};
2266
e6d275de
CH		 2267static int nvme_wait_ready(struct nvme_ctrl *ctrl, u32 mask, u32 val,
2268 u32 timeout, const char *op)
5fd4ce1b 2269{
e6d275de
CH		 2270 unsigned long timeout_jiffies = jiffies + timeout * HZ;
2271 u32 csts;
5fd4ce1b
CH		 2272 int ret;
2273
2274 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 2275 if (csts == ~0)
2276 return -ENODEV;
e6d275de 2277 if ((csts & mask) == val)
5fd4ce1b
CH		 2278 break;
2279
3e98c244 2280 usleep_range(1000, 2000);
5fd4ce1b
CH		 2281 if (fatal_signal_pending(current))
2282 return -EINTR;
354201c5 2283 if (time_after(jiffies, timeout_jiffies)) {
1b3c47c1 2284 dev_err(ctrl->device,
94d2e705 2285 "Device not ready; aborting %s, CSTS=0x%x\n",
e6d275de 2286 op, csts);
5fd4ce1b
CH		 2287 return -ENODEV;
2288 }
2289 }
2290
2291 return ret;
2292}
2293
285b6e9b 2294int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown)
5fd4ce1b
CH		 2295{
2296 int ret;
2297
2298 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
285b6e9b
CH		 2299 if (shutdown)
2300 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
2301 else
2302 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
5fd4ce1b
CH		 2303
2304 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2305 if (ret)
2306 return ret;
54adc010 2307
285b6e9b
CH		 2308 if (shutdown) {
2309 return nvme_wait_ready(ctrl, NVME_CSTS_SHST_MASK,
2310 NVME_CSTS_SHST_CMPLT,
2311 ctrl->shutdown_timeout, "shutdown");
2312 }
b5a10c5f 2313 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010 2314 msleep(NVME_QUIRK_DELAY_AMOUNT);
e6d275de
CH		 2315 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, 0,
2316 (NVME_CAP_TIMEOUT(ctrl->cap) + 1) / 2, "reset");
5fd4ce1b 2317}
576d55d6 2318EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b 2319
c0f2f45b 2320int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
5fd4ce1b 2321{
6c3c05b0 2322 unsigned dev_page_min;
354201c5 2323 u32 timeout;
5fd4ce1b
CH		 2324 int ret;
2325
c0f2f45b
SG		 2326 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2327 if (ret) {
2328 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
2329 return ret;
2330 }
2331 dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12;
2332
6c3c05b0 2333 if (NVME_CTRL_PAGE_SHIFT < dev_page_min) {
1b3c47c1 2334 dev_err(ctrl->device,
5fd4ce1b 2335 "Minimum device page size %u too large for host (%u)\n",
6c3c05b0 2336 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT);
5fd4ce1b
CH		 2337 return -ENODEV;
2338 }
2339
71010c30
NC		 2340 if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI)
2341 ctrl->ctrl_config = NVME_CC_CSS_CSI;
2342 else
2343 ctrl->ctrl_config = NVME_CC_CSS_NVM;
354201c5 2344
6cc834ba
KB		 2345 if (ctrl->cap & NVME_CAP_CRMS_CRWMS && ctrl->cap & NVME_CAP_CRMS_CRIMS)
2346 ctrl->ctrl_config |= NVME_CC_CRIME;
354201c5 2347
6c3c05b0 2348 ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
60b43f62 2349 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b 2350 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
aa41d2fe
NC		 2351 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2352 if (ret)
2353 return ret;
5fd4ce1b 2354
aa41d2fe
NC		 2355 /* Flush write to device (required if transport is PCI) */
2356 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);
2357 if (ret)
2358 return ret;
2359
6cc834ba
KB		 2360 /* CAP value may change after initial CC write */
2361 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2362 if (ret)
2363 return ret;
2364
2365 timeout = NVME_CAP_TIMEOUT(ctrl->cap);
2366 if (ctrl->cap & NVME_CAP_CRMS_CRWMS) {
2367 u32 crto, ready_timeout;
2368
2369 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CRTO, &crto);
2370 if (ret) {
2371 dev_err(ctrl->device, "Reading CRTO failed (%d)\n",
2372 ret);
2373 return ret;
2374 }
2375
2376 /*
2377 * CRTO should always be greater or equal to CAP.TO, but some
2378 * devices are known to get this wrong. Use the larger of the
2379 * two values.
2380 */
2381 if (ctrl->ctrl_config & NVME_CC_CRIME)
2382 ready_timeout = NVME_CRTO_CRIMT(crto);
2383 else
2384 ready_timeout = NVME_CRTO_CRWMT(crto);
2385
2386 if (ready_timeout < timeout)
2387 dev_warn_once(ctrl->device, "bad crto:%x cap:%llx\n",
2388 crto, ctrl->cap);
2389 else
2390 timeout = ready_timeout;
2391 }
2392
aa41d2fe 2393 ctrl->ctrl_config |= NVME_CC_ENABLE;
5fd4ce1b
CH		 2394 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2395 if (ret)
2396 return ret;
e6d275de
CH		 2397 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY,
2398 (timeout + 1) / 2, "initialisation");
5fd4ce1b 2399}
576d55d6 2400EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b 2401
dbf86b39
JD		 2402static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
2403{
2404 __le64 ts;
2405 int ret;
2406
2407 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
2408 return 0;
2409
2410 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
2411 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
2412 NULL);
2413 if (ret)
2414 dev_warn_once(ctrl->device,
2415 "could not set timestamp (%d)\n", ret);
2416 return ret;
2417}
2418
4020aad8 2419static int nvme_configure_host_options(struct nvme_ctrl *ctrl)
49cd84b6
KB		 2420{
2421 struct nvme_feat_host_behavior *host;
4020aad8 2422 u8 acre = 0, lbafee = 0;
49cd84b6
KB		 2423 int ret;
2424
2425 /* Don't bother enabling the feature if retry delay is not reported */
4020aad8
KB		 2426 if (ctrl->crdt[0])
2427 acre = NVME_ENABLE_ACRE;
2428 if (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)
2429 lbafee = NVME_ENABLE_LBAFEE;
2430
2431 if (!acre && !lbafee)
49cd84b6
KB		 2432 return 0;
2433
2434 host = kzalloc(sizeof(*host), GFP_KERNEL);
2435 if (!host)
2436 return 0;
2437
4020aad8
KB		 2438 host->acre = acre;
2439 host->lbafee = lbafee;
49cd84b6
KB		 2440 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2441 host, sizeof(*host), NULL);
2442 kfree(host);
2443 return ret;
2444}
2445
ebd8a93a
AB		 2446/*
2447 * The function checks whether the given total (exlat + enlat) latency of
2448 * a power state allows the latter to be used as an APST transition target.
2449 * It does so by comparing the latency to the primary and secondary latency
2450 * tolerances defined by module params. If there's a match, the corresponding
2451 * timeout value is returned and the matching tolerance index (1 or 2) is
2452 * reported.
2453 */
2454static bool nvme_apst_get_transition_time(u64 total_latency,
2455 u64 *transition_time, unsigned *last_index)
2456{
2457 if (total_latency <= apst_primary_latency_tol_us) {
2458 if (*last_index == 1)
2459 return false;
2460 *last_index = 1;
2461 *transition_time = apst_primary_timeout_ms;
2462 return true;
2463 }
2464 if (apst_secondary_timeout_ms &&
2465 total_latency <= apst_secondary_latency_tol_us) {
2466 if (*last_index <= 2)
2467 return false;
2468 *last_index = 2;
2469 *transition_time = apst_secondary_timeout_ms;
2470 return true;
2471 }
2472 return false;
2473}
2474
60df5de9
CH		 2475/*
2476 * APST (Autonomous Power State Transition) lets us program a table of power
2477 * state transitions that the controller will perform automatically.
ebd8a93a
AB		 2478 *
2479 * Depending on module params, one of the two supported techniques will be used:
2480 *
2481 * - If the parameters provide explicit timeouts and tolerances, they will be
2482 * used to build a table with up to 2 non-operational states to transition to.
2483 * The default parameter values were selected based on the values used by
2484 * Microsoft's and Intel's NVMe drivers. Yet, since we don't implement dynamic
2485 * regeneration of the APST table in the event of switching between external
2486 * and battery power, the timeouts and tolerances reflect a compromise
2487 * between values used by Microsoft for AC and battery scenarios.
2488 * - If not, we'll configure the table with a simple heuristic: we are willing
2489 * to spend at most 2% of the time transitioning between power states.
2490 * Therefore, when running in any given state, we will enter the next
2491 * lower-power non-operational state after waiting 50 * (enlat + exlat)
2492 * microseconds, as long as that state's exit latency is under the requested
2493 * maximum latency.
60df5de9
CH		 2494 *
2495 * We will not autonomously enter any non-operational state for which the total
2496 * latency exceeds ps_max_latency_us.
2497 *
2498 * Users can set ps_max_latency_us to zero to turn off APST.
2499 */
634b8325 2500static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde 2501{
c5552fde 2502 struct nvme_feat_auto_pst *table;
60df5de9 2503 unsigned apste = 0;
fb0dc399 2504 u64 max_lat_us = 0;
60df5de9 2505 __le64 target = 0;
fb0dc399 2506 int max_ps = -1;
60df5de9 2507 int state;
c5552fde 2508 int ret;
ebd8a93a 2509 unsigned last_lt_index = UINT_MAX;
c5552fde
AL		 2510
2511 /*
2512 * If APST isn't supported or if we haven't been initialized yet,
2513 * then don't do anything.
2514 */
2515 if (!ctrl->apsta)
634b8325 2516 return 0;
c5552fde
AL		 2517
2518 if (ctrl->npss > 31) {
2519 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2520 return 0;
c5552fde
AL		 2521 }
2522
2523 table = kzalloc(sizeof(*table), GFP_KERNEL);
2524 if (!table)
634b8325 2525 return 0;
c5552fde 2526
76a5af84 2527 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde 2528 /* Turn off APST. */
fb0dc399 2529 dev_dbg(ctrl->device, "APST disabled\n");
60df5de9
CH		 2530 goto done;
2531 }
c5552fde 2532
60df5de9
CH		 2533 /*
2534 * Walk through all states from lowest- to highest-power.
2535 * According to the spec, lower-numbered states use more power. NPSS,
2536 * despite the name, is the index of the lowest-power state, not the
2537 * number of states.
2538 */
2539 for (state = (int)ctrl->npss; state >= 0; state--) {
2540 u64 total_latency_us, exit_latency_us, transition_ms;
da87591b 2541
60df5de9
CH		 2542 if (target)
2543 table->entries[state] = target;
c5552fde 2544
c5552fde 2545 /*
60df5de9
CH		 2546 * Don't allow transitions to the deepest state if it's quirked
2547 * off.
c5552fde 2548 */
60df5de9
CH		 2549 if (state == ctrl->npss &&
2550 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2551 continue;
fb0dc399 2552
60df5de9
CH		 2553 /*
2554 * Is this state a useful non-operational state for higher-power
2555 * states to autonomously transition to?
2556 */
2557 if (!(ctrl->psd[state].flags & NVME_PS_FLAGS_NON_OP_STATE))
2558 continue;
fb0dc399 2559
60df5de9
CH		 2560 exit_latency_us = (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2561 if (exit_latency_us > ctrl->ps_max_latency_us)
2562 continue;
c5552fde 2563
60df5de9
CH		 2564 total_latency_us = exit_latency_us +
2565 le32_to_cpu(ctrl->psd[state].entry_lat);
fb0dc399 2566
60df5de9 2567 /*
ebd8a93a
AB		 2568 * This state is good. It can be used as the APST idle target
2569 * for higher power states.
60df5de9 2570 */
ebd8a93a
AB		 2571 if (apst_primary_timeout_ms && apst_primary_latency_tol_us) {
2572 if (!nvme_apst_get_transition_time(total_latency_us,
2573 &transition_ms, &last_lt_index))
2574 continue;
2575 } else {
2576 transition_ms = total_latency_us + 19;
2577 do_div(transition_ms, 20);
2578 if (transition_ms > (1 << 24) - 1)
2579 transition_ms = (1 << 24) - 1;
2580 }
60df5de9
CH		 2581
2582 target = cpu_to_le64((state << 3) | (transition_ms << 8));
2583 if (max_ps == -1)
2584 max_ps = state;
2585 if (total_latency_us > max_lat_us)
2586 max_lat_us = total_latency_us;
c5552fde
AL		 2587 }
2588
60df5de9
CH		 2589 if (max_ps == -1)
2590 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2591 else
2592 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2593 max_ps, max_lat_us, (int)sizeof(*table), table);
2594 apste = 1;
2595
2596done:
c5552fde
AL		 2597 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2598 table, sizeof(*table), NULL);
2599 if (ret)
2600 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
c5552fde 2601 kfree(table);
634b8325 2602 return ret;
c5552fde
AL		 2603}
2604
2605static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2606{
2607 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2608 u64 latency;
2609
2610 switch (val) {
2611 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2612 case PM_QOS_LATENCY_ANY:
2613 latency = U64_MAX;
2614 break;
2615
2616 default:
2617 latency = val;
2618 }
2619
2620 if (ctrl->ps_max_latency_us != latency) {
2621 ctrl->ps_max_latency_us = latency;
e6e7f7ac 2622 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE)
53fe2a30 2623 nvme_configure_apst(ctrl);
c5552fde
AL		 2624 }
2625}
2626
bd4da3ab
AL		 2627struct nvme_core_quirk_entry {
2628 /*
2629 * NVMe model and firmware strings are padded with spaces. For
2630 * simplicity, strings in the quirk table are padded with NULLs
2631 * instead.
2632 */
2633 u16 vid;
2634 const char *mn;
2635 const char *fr;
2636 unsigned long quirks;
2637};
2638
2639static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2640 {
be56945c
AL		 2641 /*
2642 * This Toshiba device seems to die using any APST states. See:
2643 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2644 */
2645 .vid = 0x1179,
2646 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2647 .quirks = NVME_QUIRK_NO_APST,
cb32de1b
ML		 2648 },
2649 {
2650 /*
2651 * This LiteON CL1-3D*-Q11 firmware version has a race
2652 * condition associated with actions related to suspend to idle
2653 * LiteON has resolved the problem in future firmware
2654 */
2655 .vid = 0x14a4,
2656 .fr = "22301111",
2657 .quirks = NVME_QUIRK_SIMPLE_SUSPEND,
5a6254d5
EM		 2658 },
2659 {
2660 /*
2661 * This Kioxia CD6-V Series / HPE PE8030 device times out and
2662 * aborts I/O during any load, but more easily reproducible
2663 * with discards (fstrim).
2664 *
2665 * The device is left in a state where it is also not possible
2666 * to use "nvme set-feature" to disable APST, but booting with
2667 * nvme_core.default_ps_max_latency=0 works.
2668 */
2669 .vid = 0x1e0f,
2670 .mn = "KCD6XVUL6T40",
2671 .quirks = NVME_QUIRK_NO_APST,
e6487833
CH		 2672 },
2673 {
2674 /*
2675 * The external Samsung X5 SSD fails initialization without a
2676 * delay before checking if it is ready and has a whole set of
2677 * other problems. To make this even more interesting, it
2678 * shares the PCI ID with internal Samsung 970 Evo Plus that
2679 * does not need or want these quirks.
2680 */
2681 .vid = 0x144d,
2682 .mn = "Samsung Portable SSD X5",
2683 .quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
2684 NVME_QUIRK_NO_DEEPEST_PS |
2685 NVME_QUIRK_IGNORE_DEV_SUBNQN,
be56945c 2686 }
bd4da3ab
AL		 2687};
2688
2689/* match is null-terminated but idstr is space-padded. */
2690static bool string_matches(const char *idstr, const char *match, size_t len)
2691{
2692 size_t matchlen;
2693
2694 if (!match)
2695 return true;
2696
2697 matchlen = strlen(match);
2698 WARN_ON_ONCE(matchlen > len);
2699
2700 if (memcmp(idstr, match, matchlen))
2701 return false;
2702
2703 for (; matchlen < len; matchlen++)
2704 if (idstr[matchlen] != ' ')
2705 return false;
2706
2707 return true;
2708}
2709
2710static bool quirk_matches(const struct nvme_id_ctrl *id,
2711 const struct nvme_core_quirk_entry *q)
2712{
2713 return q->vid == le16_to_cpu(id->vid) &&
2714 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2715 string_matches(id->fr, q->fr, sizeof(id->fr));
2716}
2717
ab9e00cc
CH		 2718static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2719 struct nvme_id_ctrl *id)
180de007
CH		 2720{
2721 size_t nqnlen;
2722 int off;
2723
6299358d
JD		 2724 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2725 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2726 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
a8817cc0 2727 strscpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
6299358d
JD		 2728 return;
2729 }
180de007 2730
6299358d
JD		 2731 if (ctrl->vs >= NVME_VS(1, 2, 1))
2732 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2733 }
180de007 2734
1abc6961
LB		 2735 /*
2736 * Generate a "fake" NQN similar to the one in Section 4.5 of the NVMe
2737 * Base Specification 2.0. It is slightly different from the format
2738 * specified there due to historic reasons, and we can't change it now.
2739 */
ab9e00cc 2740 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2741 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2742 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2743 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2744 off += sizeof(id->sn);
ab9e00cc 2745 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2746 off += sizeof(id->mn);
ab9e00cc
CH		 2747 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2748}
2749
e654dfd3 2750static void nvme_release_subsystem(struct device *dev)
ab9e00cc 2751{
e654dfd3
LG		 2752 struct nvme_subsystem *subsys =
2753 container_of(dev, struct nvme_subsystem, dev);
2754
733e4b69 2755 if (subsys->instance >= 0)
8b850475 2756 ida_free(&nvme_instance_ida, subsys->instance);
ab9e00cc
CH		 2757 kfree(subsys);
2758}
2759
ab9e00cc
CH		 2760static void nvme_destroy_subsystem(struct kref *ref)
2761{
2762 struct nvme_subsystem *subsys =
2763 container_of(ref, struct nvme_subsystem, ref);
2764
2765 mutex_lock(&nvme_subsystems_lock);
2766 list_del(&subsys->entry);
2767 mutex_unlock(&nvme_subsystems_lock);
2768
ed754e5d 2769 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2770 device_del(&subsys->dev);
2771 put_device(&subsys->dev);
2772}
2773
2774static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2775{
2776 kref_put(&subsys->ref, nvme_destroy_subsystem);
2777}
2778
2779static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2780{
2781 struct nvme_subsystem *subsys;
2782
2783 lockdep_assert_held(&nvme_subsystems_lock);
2784
c26aa572
JS		 2785 /*
2786 * Fail matches for discovery subsystems. This results
2787 * in each discovery controller bound to a unique subsystem.
2788 * This avoids issues with validating controller values
2789 * that can only be true when there is a single unique subsystem.
2790 * There may be multiple and completely independent entities
2791 * that provide discovery controllers.
2792 */
2793 if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME))
2794 return NULL;
2795
ab9e00cc
CH		 2796 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2797 if (strcmp(subsys->subnqn, subsysnqn))
2798 continue;
2799 if (!kref_get_unless_zero(&subsys->ref))
2800 continue;
2801 return subsys;
2802 }
2803
2804 return NULL;
2805}
2806
5ab25a32
SG		 2807static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl)
2808{
2809 return ctrl->opts && ctrl->opts->discovery_nqn;
2810}
2811
1b1031ca
CH		 2812static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
2813 struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
b837b283 2814{
1b1031ca 2815 struct nvme_ctrl *tmp;
b837b283 2816
32fd90c4
CH		 2817 lockdep_assert_held(&nvme_subsystems_lock);
2818
1b1031ca 2819 list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) {
e7c43fea 2820 if (nvme_state_terminal(tmp))
1b1031ca
CH		 2821 continue;
2822
2823 if (tmp->cntlid == ctrl->cntlid) {
2824 dev_err(ctrl->device,
16cc33b2
KB		 2825 "Duplicate cntlid %u with %s, subsys %s, rejecting\n",
2826 ctrl->cntlid, dev_name(tmp->device),
2827 subsys->subnqn);
1b1031ca
CH		 2828 return false;
2829 }
b837b283 2830
92decf11 2831 if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) ||
5ab25a32 2832 nvme_discovery_ctrl(ctrl))
1b1031ca
CH		 2833 continue;
2834
2835 dev_err(ctrl->device,
2836 "Subsystem does not support multiple controllers\n");
2837 return false;
b837b283 2838 }
b837b283 2839
1b1031ca 2840 return true;
b837b283
IR		 2841}
2842
ab9e00cc
CH		 2843static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2844{
2845 struct nvme_subsystem *subsys, *found;
2846 int ret;
2847
2848 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2849 if (!subsys)
2850 return -ENOMEM;
733e4b69
KB		 2851
2852 subsys->instance = -1;
ab9e00cc
CH		 2853 mutex_init(&subsys->lock);
2854 kref_init(&subsys->ref);
2855 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2856 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2857 nvme_init_subnqn(subsys, ctrl, id);
2858 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2859 memcpy(subsys->model, id->mn, sizeof(subsys->model));
ab9e00cc
CH		 2860 subsys->vendor_id = le16_to_cpu(id->vid);
2861 subsys->cmic = id->cmic;
954ae166
HR		 2862
2863 /* Versions prior to 1.4 don't necessarily report a valid type */
2864 if (id->cntrltype == NVME_CTRL_DISC ||
2865 !strcmp(subsys->subnqn, NVME_DISC_SUBSYS_NAME))
2866 subsys->subtype = NVME_NQN_DISC;
2867 else
2868 subsys->subtype = NVME_NQN_NVME;
2869
20e8b689
HR		 2870 if (nvme_discovery_ctrl(ctrl) && subsys->subtype != NVME_NQN_DISC) {
2871 dev_err(ctrl->device,
2872 "Subsystem %s is not a discovery controller",
2873 subsys->subnqn);
2874 kfree(subsys);
2875 return -EINVAL;
2876 }
81adb863 2877 subsys->awupf = le16_to_cpu(id->awupf);
e3d34794 2878 nvme_mpath_default_iopolicy(subsys);
ab9e00cc
CH		 2879
2880 subsys->dev.class = nvme_subsys_class;
2881 subsys->dev.release = nvme_release_subsystem;
1e496938 2882 subsys->dev.groups = nvme_subsys_attrs_groups;
733e4b69 2883 dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance);
ab9e00cc
CH		 2884 device_initialize(&subsys->dev);
2885
2886 mutex_lock(&nvme_subsystems_lock);
2887 found = __nvme_find_get_subsystem(subsys->subnqn);
2888 if (found) {
e654dfd3 2889 put_device(&subsys->dev);
ab9e00cc 2890 subsys = found;
32fd90c4 2891
1b1031ca 2892 if (!nvme_validate_cntlid(subsys, ctrl, id)) {
ab9e00cc 2893 ret = -EINVAL;
32fd90c4 2894 goto out_put_subsystem;
ab9e00cc 2895 }
ab9e00cc
CH		 2896 } else {
2897 ret = device_add(&subsys->dev);
2898 if (ret) {
2899 dev_err(ctrl->device,
2900 "failed to register subsystem device.\n");
8c36e66f 2901 put_device(&subsys->dev);
ab9e00cc
CH		 2902 goto out_unlock;
2903 }
ed754e5d 2904 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2905 list_add_tail(&subsys->entry, &nvme_subsystems);
2906 }
2907
bc4f6e06
DC		 2908 ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2909 dev_name(ctrl->device));
2910 if (ret) {
ab9e00cc
CH		 2911 dev_err(ctrl->device,
2912 "failed to create sysfs link from subsystem.\n");
32fd90c4 2913 goto out_put_subsystem;
ab9e00cc
CH		 2914 }
2915
733e4b69
KB		 2916 if (!found)
2917 subsys->instance = ctrl->instance;
32fd90c4 2918 ctrl->subsys = subsys;
ab9e00cc 2919 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
32fd90c4 2920 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc
CH		 2921 return 0;
2922
32fd90c4
CH		 2923out_put_subsystem:
2924 nvme_put_subsystem(subsys);
ab9e00cc
CH		 2925out_unlock:
2926 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 2927 return ret;
180de007
CH		 2928}
2929
be93e87e 2930int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
0e98719b 2931 void *log, size_t size, u64 offset)
c627c487
KB		 2932{
2933 struct nvme_command c = { };
71fb90eb 2934 u32 dwlen = nvme_bytes_to_numd(size);
70da6094
MB		 2935
2936 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2937 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2938 c.get_log_page.lid = log_page;
0e98719b 2939 c.get_log_page.lsp = lsp;
70da6094
MB		 2940 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2941 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2942 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2943 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
be93e87e 2944 c.get_log_page.csi = csi;
c627c487
KB		 2945
2946 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2947}
2948
be93e87e
KB		 2949static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi,
2950 struct nvme_effects_log **log)
84fef62d 2951{
f6224b86 2952 struct nvme_effects_log *cel = xa_load(&ctrl->cels, csi);
84fef62d
KB		 2953 int ret;
2954
be93e87e
KB		 2955 if (cel)
2956 goto out;
84fef62d 2957
be93e87e
KB		 2958 cel = kzalloc(sizeof(*cel), GFP_KERNEL);
2959 if (!cel)
2960 return -ENOMEM;
84fef62d 2961
46d2613e 2962 ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi,
f6224b86 2963 cel, sizeof(*cel), 0);
84fef62d 2964 if (ret) {
be93e87e
KB		 2965 kfree(cel);
2966 return ret;
84fef62d 2967 }
be93e87e 2968
f6224b86 2969 xa_store(&ctrl->cels, csi, cel, GFP_KERNEL);
be93e87e 2970out:
f6224b86 2971 *log = cel;
be93e87e 2972 return 0;
180de007
CH		 2973}
2974
5befc7c2 2975static inline u32 nvme_mps_to_sectors(struct nvme_ctrl *ctrl, u32 units)
7fd8930f 2976{
8609c63f 2977 u32 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12, val;
7fd8930f 2978
8609c63f
BVA		 2979 if (check_shl_overflow(1U, units + page_shift - 9, &val))
2980 return UINT_MAX;
2981 return val;
5befc7c2
KB		 2982}
2983
2984static int nvme_init_non_mdts_limits(struct nvme_ctrl *ctrl)
2985{
2986 struct nvme_command c = { };
2987 struct nvme_id_ctrl_nvm *id;
2988 int ret;
2989
5befc7c2
KB		 2990 /*
2991 * Even though NVMe spec explicitly states that MDTS is not applicable
2992 * to the write-zeroes, we are cautious and limit the size to the
2993 * controllers max_hw_sectors value, which is based on the MDTS field
2994 * and possibly other limiting factors.
2995 */
2996 if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) &&
2997 !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES))
2998 ctrl->max_zeroes_sectors = ctrl->max_hw_sectors;
2999 else
3000 ctrl->max_zeroes_sectors = 0;
3001
def84ab6 3002 if (ctrl->subsys->subtype != NVME_NQN_NVME ||
c917dd96
KB		 3003 nvme_ctrl_limited_cns(ctrl) ||
3004 test_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags))
5befc7c2
KB		 3005 return 0;
3006
3007 id = kzalloc(sizeof(*id), GFP_KERNEL);
3008 if (!id)
bcaf434b 3009 return -ENOMEM;
5befc7c2
KB		 3010
3011 c.identify.opcode = nvme_admin_identify;
3012 c.identify.cns = NVME_ID_CNS_CS_CTRL;
3013 c.identify.csi = NVME_CSI_NVM;
3014
3015 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
3016 if (ret)
3017 goto free_data;
3018
3b946fe1 3019 ctrl->dmrl = id->dmrl;
1a86924e 3020 ctrl->dmrsl = le32_to_cpu(id->dmrsl);
5befc7c2
KB		 3021 if (id->wzsl)
3022 ctrl->max_zeroes_sectors = nvme_mps_to_sectors(ctrl, id->wzsl);
3023
3024free_data:
c917dd96
KB		 3025 if (ret > 0)
3026 set_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags);
5befc7c2
KB		 3027 kfree(id);
3028 return ret;
3029}
3030
cc115cbe
KB		 3031static void nvme_init_known_nvm_effects(struct nvme_ctrl *ctrl)
3032{
3033 struct nvme_effects_log *log = ctrl->effects;
3034
3035 log->acs[nvme_admin_format_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC |
3036 NVME_CMD_EFFECTS_NCC |
3037 NVME_CMD_EFFECTS_CSE_MASK);
3038 log->acs[nvme_admin_sanitize_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC |
3039 NVME_CMD_EFFECTS_CSE_MASK);
3040
baff6491
KB		 3041 /*
3042 * The spec says the result of a security receive command depends on
3043 * the previous security send command. As such, many vendors log this
3044 * command as one to submitted only when no other commands to the same
3045 * namespace are outstanding. The intention is to tell the host to
3046 * prevent mixing security send and receive.
3047 *
3048 * This driver can only enforce such exclusive access against IO
3049 * queues, though. We are not readily able to enforce such a rule for
3050 * two commands to the admin queue, which is the only queue that
3051 * matters for this command.
3052 *
3053 * Rather than blindly freezing the IO queues for this effect that
3054 * doesn't even apply to IO, mask it off.
3055 */
c0c33b94 3056 log->acs[nvme_admin_security_recv] &= cpu_to_le32(~NVME_CMD_EFFECTS_CSE_MASK);
baff6491 3057
cc115cbe
KB		 3058 log->iocs[nvme_cmd_write] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3059 log->iocs[nvme_cmd_write_zeroes] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3060 log->iocs[nvme_cmd_write_uncor] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3061}
3062
3063static int nvme_init_effects(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
3064{
3065 int ret = 0;
3066
3067 if (ctrl->effects)
3068 return 0;
3069
3070 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
3071 ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects);
3072 if (ret < 0)
3073 return ret;
3074 }
3075
3076 if (!ctrl->effects) {
3077 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
3078 if (!ctrl->effects)
3079 return -ENOMEM;
3080 xa_store(&ctrl->cels, NVME_CSI_NVM, ctrl->effects, GFP_KERNEL);
3081 }
3082
3083 nvme_init_known_nvm_effects(ctrl);
3084 return 0;
3085}
3086
68999d1d
GL		 3087static int nvme_check_ctrl_fabric_info(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
3088{
3089 /*
3090 * In fabrics we need to verify the cntlid matches the
3091 * admin connect
3092 */
3093 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
3094 dev_err(ctrl->device,
3095 "Mismatching cntlid: Connect %u vs Identify %u, rejecting\n",
3096 ctrl->cntlid, le16_to_cpu(id->cntlid));
3097 return -EINVAL;
3098 }
3099
3100 if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) {
3101 dev_err(ctrl->device,
3102 "keep-alive support is mandatory for fabrics\n");
3103 return -EINVAL;
3104 }
3105
7642138e 3106 if (!nvme_discovery_ctrl(ctrl) && ctrl->ioccsz < 4) {
2fcd3ab3
GL		 3107 dev_err(ctrl->device,
3108 "I/O queue command capsule supported size %d < 4\n",
3109 ctrl->ioccsz);
3110 return -EINVAL;
3111 }
3112
7642138e 3113 if (!nvme_discovery_ctrl(ctrl) && ctrl->iorcsz < 1) {
2fcd3ab3
GL		 3114 dev_err(ctrl->device,
3115 "I/O queue response capsule supported size %d < 1\n",
3116 ctrl->iorcsz);
3117 return -EINVAL;
3118 }
3119
68999d1d
GL		 3120 return 0;
3121}
3122
44ef5611 3123static int nvme_init_identify(struct nvme_ctrl *ctrl)
7fd8930f
CH		 3124{
3125 struct nvme_id_ctrl *id;
a229dbf6 3126 u32 max_hw_sectors;
76a5af84 3127 bool prev_apst_enabled;
5befc7c2 3128 int ret;
f3ca80fc 3129
7fd8930f
CH		 3130 ret = nvme_identify_ctrl(ctrl, &id);
3131 if (ret) {
1b3c47c1 3132 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 3133 return -EIO;
3134 }
3135
a89fcca8
GP		 3136 if (!(ctrl->ops->flags & NVME_F_FABRICS))
3137 ctrl->cntlid = le16_to_cpu(id->cntlid);
3138
bd4da3ab 3139 if (!ctrl->identified) {
44ef5611 3140 unsigned int i;
ab9e00cc 3141
bd4da3ab
AL		 3142 /*
3143 * Check for quirks. Quirk can depend on firmware version,
3144 * so, in principle, the set of quirks present can change
3145 * across a reset. As a possible future enhancement, we
3146 * could re-scan for quirks every time we reinitialize
3147 * the device, but we'd have to make sure that the driver
3148 * behaves intelligently if the quirks change.
3149 */
bd4da3ab
AL		 3150 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
3151 if (quirk_matches(id, &core_quirks[i]))
3152 ctrl->quirks |= core_quirks[i].quirks;
3153 }
6f2d7152
PR		 3154
3155 ret = nvme_init_subsystem(ctrl, id);
3156 if (ret)
3157 goto out_free;
cc115cbe
KB		 3158
3159 ret = nvme_init_effects(ctrl, id);
3160 if (ret)
3161 goto out_free;
bd4da3ab 3162 }
a8eb6c1b
KB		 3163 memcpy(ctrl->subsys->firmware_rev, id->fr,
3164 sizeof(ctrl->subsys->firmware_rev));
bd4da3ab 3165
c35e30b4 3166 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 3167 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 3168 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
3169 }
3170
49cd84b6
KB		 3171 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
3172 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
3173 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
3174
8a9ae523 3175 ctrl->oacs = le16_to_cpu(id->oacs);
43e2d08d 3176 ctrl->oncs = le16_to_cpu(id->oncs);
2d466c7a 3177 ctrl->mtfa = le16_to_cpu(id->mtfa);
c0561f82 3178 ctrl->oaes = le32_to_cpu(id->oaes);
400b6a7b
GR		 3179 ctrl->wctemp = le16_to_cpu(id->wctemp);
3180 ctrl->cctemp = le16_to_cpu(id->cctemp);
3181
6bf25d16 3182 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 3183 ctrl->vwc = id->vwc;
7fd8930f 3184 if (id->mdts)
5befc7c2 3185 max_hw_sectors = nvme_mps_to_sectors(ctrl, id->mdts);
7fd8930f 3186 else
a229dbf6
CH		 3187 max_hw_sectors = UINT_MAX;
3188 ctrl->max_hw_sectors =
3189 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 3190
da35825d 3191 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 3192 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 3193 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 3194 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 3195 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 3196
86c2457a
MB		 3197 ctrl->cntrltype = id->cntrltype;
3198 ctrl->dctype = id->dctype;
3199
07fbd32a
MP		 3200 if (id->rtd3e) {
3201 /* us -> s */
f5af577d 3202 u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC;
07fbd32a
MP		 3203
3204 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
3205 shutdown_timeout, 60);
3206
3207 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 3208 dev_info(ctrl->device,
07fbd32a
MP		 3209 "Shutdown timeout set to %u seconds\n",
3210 ctrl->shutdown_timeout);
3211 } else
3212 ctrl->shutdown_timeout = shutdown_timeout;
3213
c5552fde 3214 ctrl->npss = id->npss;
76a5af84
KHF		 3215 ctrl->apsta = id->apsta;
3216 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 3217 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
3218 if (force_apst && id->apsta) {
f0425db0 3219 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 3220 ctrl->apst_enabled = true;
c35e30b4 3221 } else {
76a5af84 3222 ctrl->apst_enabled = false;
c35e30b4
AL		 3223 }
3224 } else {
76a5af84 3225 ctrl->apst_enabled = id->apsta;
c35e30b4 3226 }
c5552fde
AL		 3227 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
3228
d3d5b87d 3229 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 3230 ctrl->icdoff = le16_to_cpu(id->icdoff);
3231 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
3232 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
3233 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
3234
68999d1d
GL		 3235 ret = nvme_check_ctrl_fabric_info(ctrl, id);
3236 if (ret)
634b8325 3237 goto out_free;
07bfcd09 3238 } else {
fe6d53c9
CH		 3239 ctrl->hmpre = le32_to_cpu(id->hmpre);
3240 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 3241 ctrl->hmminds = le32_to_cpu(id->hmminds);
3242 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 3243 }
da35825d 3244
5e1f6899 3245 ret = nvme_mpath_init_identify(ctrl, id);
0d0b660f 3246 if (ret < 0)
44ef5611 3247 goto out_free;
0d0b660f 3248
76a5af84 3249 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 3250 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 3251 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 3252 dev_pm_qos_hide_latency_tolerance(ctrl->device);
3253
44ef5611
CK		 3254out_free:
3255 kfree(id);
3256 return ret;
3257}
3258
3259/*
3260 * Initialize the cached copies of the Identify data and various controller
3261 * register in our nvme_ctrl structure. This should be called as soon as
3262 * the admin queue is fully up and running.
3263 */
94cc781f 3264int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended)
44ef5611
CK		 3265{
3266 int ret;
3267
3268 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
3269 if (ret) {
3270 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
3271 return ret;
3272 }
3273
3274 ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize);
3275
3276 if (ctrl->vs >= NVME_VS(1, 1, 0))
3277 ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap);
3278
3279 ret = nvme_init_identify(ctrl);
3280 if (ret)
3281 return ret;
3282
634b8325
KB		 3283 ret = nvme_configure_apst(ctrl);
3284 if (ret < 0)
3285 return ret;
95d54bd1 3286
dbf86b39
JD		 3287 ret = nvme_configure_timestamp(ctrl);
3288 if (ret < 0)
3289 return ret;
634b8325 3290
4020aad8 3291 ret = nvme_configure_host_options(ctrl);
49cd84b6
KB		 3292 if (ret < 0)
3293 return ret;
3294
94cc781f
CH		 3295 nvme_configure_opal(ctrl, was_suspended);
3296
5ab25a32 3297 if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) {
6b8cf940
CH		 3298 /*
3299 * Do not return errors unless we are in a controller reset,
3300 * the controller works perfectly fine without hwmon.
3301 */
59e330f8 3302 ret = nvme_hwmon_init(ctrl);
6b8cf940 3303 if (ret == -EINTR)
59e330f8
KB		 3304 return ret;
3305 }
400b6a7b 3306
d0dd594b 3307 clear_bit(NVME_CTRL_DIRTY_CAPABILITY, &ctrl->flags);
bd4da3ab 3308 ctrl->identified = true;
c5552fde 3309
4733b65d
HR		 3310 nvme_start_keep_alive(ctrl);
3311
634b8325 3312 return 0;
7fd8930f 3313}
f21c4769 3314EXPORT_SYMBOL_GPL(nvme_init_ctrl_finish);
7fd8930f 3315
f3ca80fc 3316static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 3317{
a6a5149b
CH		 3318 struct nvme_ctrl *ctrl =
3319 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 3320
e6e7f7ac 3321 switch (nvme_ctrl_state(ctrl)) {
2b1b7e78 3322 case NVME_CTRL_LIVE:
2b1b7e78
JW		 3323 break;
3324 default:
a6a5149b 3325 return -EWOULDBLOCK;
2b1b7e78
JW		 3326 }
3327
52a3974f 3328 nvme_get_ctrl(ctrl);
4bab6909
CK		 3329 if (!try_module_get(ctrl->ops->module)) {
3330 nvme_put_ctrl(ctrl);
52a3974f 3331 return -EINVAL;
4bab6909 3332 }
52a3974f 3333
a6a5149b 3334 file->private_data = ctrl;
f3ca80fc
CH		 3335 return 0;
3336}
3337
52a3974f
CK		 3338static int nvme_dev_release(struct inode *inode, struct file *file)
3339{
3340 struct nvme_ctrl *ctrl =
3341 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
3342
3343 module_put(ctrl->ops->module);
3344 nvme_put_ctrl(ctrl);
3345 return 0;
3346}
3347
f3ca80fc
CH		 3348static const struct file_operations nvme_dev_fops = {
3349 .owner = THIS_MODULE,
3350 .open = nvme_dev_open,
52a3974f 3351 .release = nvme_dev_release,
f3ca80fc 3352 .unlocked_ioctl = nvme_dev_ioctl,
1832f2d8 3353 .compat_ioctl = compat_ptr_ioctl,
58e5bdeb 3354 .uring_cmd = nvme_dev_uring_cmd,
f3ca80fc
CH		 3355};
3356
5974ea7c 3357static struct nvme_ns_head *nvme_find_ns_head(struct nvme_ctrl *ctrl,
ed754e5d
CH		 3358 unsigned nsid)
3359{
3360 struct nvme_ns_head *h;
3361
5974ea7c 3362 lockdep_assert_held(&ctrl->subsys->lock);
ed754e5d 3363
5974ea7c
SM		 3364 list_for_each_entry(h, &ctrl->subsys->nsheads, entry) {
3365 /*
3366 * Private namespaces can share NSIDs under some conditions.
3367 * In that case we can't use the same ns_head for namespaces
3368 * with the same NSID.
3369 */
3370 if (h->ns_id != nsid || !nvme_is_unique_nsid(ctrl, h))
9edceaf4
DW		 3371 continue;
3372 if (!list_empty(&h->list) && nvme_tryget_ns_head(h))
ed754e5d
CH		 3373 return h;
3374 }
3375
3376 return NULL;
3377}
3378
fd8099e7
CH		 3379static int nvme_subsys_check_duplicate_ids(struct nvme_subsystem *subsys,
3380 struct nvme_ns_ids *ids)
ed754e5d 3381{
e2724cb9
CH		 3382 bool has_uuid = !uuid_is_null(&ids->uuid);
3383 bool has_nguid = memchr_inv(ids->nguid, 0, sizeof(ids->nguid));
3384 bool has_eui64 = memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
ed754e5d
CH		 3385 struct nvme_ns_head *h;
3386
3387 lockdep_assert_held(&subsys->lock);
3388
3389 list_for_each_entry(h, &subsys->nsheads, entry) {
e2724cb9
CH		 3390 if (has_uuid && uuid_equal(&ids->uuid, &h->ids.uuid))
3391 return -EINVAL;
3392 if (has_nguid &&
3393 memcmp(&ids->nguid, &h->ids.nguid, sizeof(ids->nguid)) == 0)
3394 return -EINVAL;
3395 if (has_eui64 &&
3396 memcmp(&ids->eui64, &h->ids.eui64, sizeof(ids->eui64)) == 0)
ed754e5d
CH		 3397 return -EINVAL;
3398 }
3399
3400 return 0;
3401}
3402
be5eb933
AM		 3403static void nvme_cdev_rel(struct device *dev)
3404{
8b850475 3405 ida_free(&nvme_ns_chr_minor_ida, MINOR(dev->devt));
be5eb933
AM		 3406}
3407
2637baed
MI		 3408void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device)
3409{
3410 cdev_device_del(cdev, cdev_device);
be5eb933 3411 put_device(cdev_device);
2637baed
MI		 3412}
3413
3414int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device,
3415 const struct file_operations *fops, struct module *owner)
3416{
3417 int minor, ret;
3418
8b850475 3419 minor = ida_alloc(&nvme_ns_chr_minor_ida, GFP_KERNEL);
2637baed
MI		 3420 if (minor < 0)
3421 return minor;
3422 cdev_device->devt = MKDEV(MAJOR(nvme_ns_chr_devt), minor);
3423 cdev_device->class = nvme_ns_chr_class;
be5eb933 3424 cdev_device->release = nvme_cdev_rel;
2637baed
MI		 3425 device_initialize(cdev_device);
3426 cdev_init(cdev, fops);
3427 cdev->owner = owner;
3428 ret = cdev_device_add(cdev, cdev_device);
be5eb933 3429 if (ret)
3596a065 3430 put_device(cdev_device);
be5eb933 3431
2637baed
MI		 3432 return ret;
3433}
3434
3435static int nvme_ns_chr_open(struct inode *inode, struct file *file)
3436{
3437 return nvme_ns_open(container_of(inode->i_cdev, struct nvme_ns, cdev));
3438}
3439
3440static int nvme_ns_chr_release(struct inode *inode, struct file *file)
3441{
3442 nvme_ns_release(container_of(inode->i_cdev, struct nvme_ns, cdev));
3443 return 0;
3444}
3445
3446static const struct file_operations nvme_ns_chr_fops = {
3447 .owner = THIS_MODULE,
3448 .open = nvme_ns_chr_open,
3449 .release = nvme_ns_chr_release,
3450 .unlocked_ioctl = nvme_ns_chr_ioctl,
3451 .compat_ioctl = compat_ptr_ioctl,
456cba38 3452 .uring_cmd = nvme_ns_chr_uring_cmd,
585079b6 3453 .uring_cmd_iopoll = nvme_ns_chr_uring_cmd_iopoll,
2637baed
MI		 3454};
3455
3456static int nvme_add_ns_cdev(struct nvme_ns *ns)
3457{
3458 int ret;
3459
3460 ns->cdev_device.parent = ns->ctrl->device;
3461 ret = dev_set_name(&ns->cdev_device, "ng%dn%d",
3462 ns->ctrl->instance, ns->head->instance);
3463 if (ret)
3464 return ret;
be5eb933
AM		 3465
3466 return nvme_cdev_add(&ns->cdev, &ns->cdev_device, &nvme_ns_chr_fops,
3467 ns->ctrl->ops->module);
2637baed
MI		 3468}
3469
ed754e5d 3470static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
1a893c2b 3471 struct nvme_ns_info *info)
ed754e5d
CH		 3472{
3473 struct nvme_ns_head *head;
f3334447 3474 size_t size = sizeof(*head);
ed754e5d
CH		 3475 int ret = -ENOMEM;
3476
f3334447
CH		 3477#ifdef CONFIG_NVME_MULTIPATH
3478 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3479#endif
3480
3481 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH		 3482 if (!head)
3483 goto out;
8b850475 3484 ret = ida_alloc_min(&ctrl->subsys->ns_ida, 1, GFP_KERNEL);
ed754e5d
CH		 3485 if (ret < 0)
3486 goto out_free_head;
3487 head->instance = ret;
3488 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 3489 ret = init_srcu_struct(&head->srcu);
3490 if (ret)
3491 goto out_ida_remove;
ed754e5d 3492 head->subsys = ctrl->subsys;
1a893c2b
CH		 3493 head->ns_id = info->nsid;
3494 head->ids = info->ids;
3495 head->shared = info->is_shared;
a1a825ab
DW		 3496 ratelimit_state_init(&head->rs_nuse, 5 * HZ, 1);
3497 ratelimit_set_flags(&head->rs_nuse, RATELIMIT_MSG_ON_RELEASE);
ed754e5d
CH		 3498 kref_init(&head->ref);
3499
be93e87e
KB		 3500 if (head->ids.csi) {
3501 ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects);
3502 if (ret)
3503 goto out_cleanup_srcu;
3504 } else
3505 head->effects = ctrl->effects;
3506
32acab31
CH		 3507 ret = nvme_mpath_alloc_disk(ctrl, head);
3508 if (ret)
3509 goto out_cleanup_srcu;
3510
ed754e5d 3511 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 3512
3513 kref_get(&ctrl->subsys->ref);
3514
ed754e5d
CH		 3515 return head;
3516out_cleanup_srcu:
3517 cleanup_srcu_struct(&head->srcu);
fd92c77f 3518out_ida_remove:
8b850475 3519 ida_free(&ctrl->subsys->ns_ida, head->instance);
ed754e5d
CH		 3520out_free_head:
3521 kfree(head);
3522out:
538af88e
SG		 3523 if (ret > 0)
3524 ret = blk_status_to_errno(nvme_error_status(ret));
ed754e5d
CH		 3525 return ERR_PTR(ret);
3526}
3527
2079f41e
CH		 3528static int nvme_global_check_duplicate_ids(struct nvme_subsystem *this,
3529 struct nvme_ns_ids *ids)
3530{
3531 struct nvme_subsystem *s;
3532 int ret = 0;
3533
3534 /*
3535 * Note that this check is racy as we try to avoid holding the global
3536 * lock over the whole ns_head creation. But it is only intended as
3537 * a sanity check anyway.
3538 */
3539 mutex_lock(&nvme_subsystems_lock);
3540 list_for_each_entry(s, &nvme_subsystems, entry) {
3541 if (s == this)
3542 continue;
3543 mutex_lock(&s->lock);
3544 ret = nvme_subsys_check_duplicate_ids(s, ids);
3545 mutex_unlock(&s->lock);
3546 if (ret)
3547 break;
3548 }
3549 mutex_unlock(&nvme_subsystems_lock);
3550
3551 return ret;
3552}
3553
1a893c2b 3554static int nvme_init_ns_head(struct nvme_ns *ns, struct nvme_ns_info *info)
ed754e5d
CH		 3555{
3556 struct nvme_ctrl *ctrl = ns->ctrl;
ed754e5d 3557 struct nvme_ns_head *head = NULL;
2079f41e
CH		 3558 int ret;
3559
1a893c2b 3560 ret = nvme_global_check_duplicate_ids(ctrl->subsys, &info->ids);
2079f41e 3561 if (ret) {
ac522fc6
CH		 3562 /*
3563 * We've found two different namespaces on two different
3564 * subsystems that report the same ID. This is pretty nasty
3565 * for anything that actually requires unique device
3566 * identification. In the kernel we need this for multipathing,
3567 * and in user space the /dev/disk/by-id/ links rely on it.
3568 *
3569 * If the device also claims to be multi-path capable back off
3570 * here now and refuse the probe the second device as this is a
3571 * recipe for data corruption. If not this is probably a
3572 * cheap consumer device if on the PCIe bus, so let the user
3573 * proceed and use the shiny toy, but warn that with changing
3574 * probing order (which due to our async probing could just be
3575 * device taking longer to startup) the other device could show
3576 * up at any time.
3577 */
2f0dad17 3578 nvme_print_device_info(ctrl);
ac522fc6
CH		 3579 if ((ns->ctrl->ops->flags & NVME_F_FABRICS) || /* !PCIe */
3580 ((ns->ctrl->subsys->cmic & NVME_CTRL_CMIC_MULTI_CTRL) &&
3581 info->is_shared)) {
3582 dev_err(ctrl->device,
3583 "ignoring nsid %d because of duplicate IDs\n",
3584 info->nsid);
3585 return ret;
3586 }
3587
3588 dev_err(ctrl->device,
3589 "clearing duplicate IDs for nsid %d\n", info->nsid);
3590 dev_err(ctrl->device,
3591 "use of /dev/disk/by-id/ may cause data corruption\n");
3592 memset(&info->ids.nguid, 0, sizeof(info->ids.nguid));
3593 memset(&info->ids.uuid, 0, sizeof(info->ids.uuid));
3594 memset(&info->ids.eui64, 0, sizeof(info->ids.eui64));
3595 ctrl->quirks |= NVME_QUIRK_BOGUS_NID;
2079f41e 3596 }
ed754e5d
CH		 3597
3598 mutex_lock(&ctrl->subsys->lock);
1a893c2b 3599 head = nvme_find_ns_head(ctrl, info->nsid);
ed754e5d 3600 if (!head) {
1a893c2b 3601 ret = nvme_subsys_check_duplicate_ids(ctrl->subsys, &info->ids);
e2d77d2e
CH		 3602 if (ret) {
3603 dev_err(ctrl->device,
2079f41e 3604 "duplicate IDs in subsystem for nsid %d\n",
1a893c2b 3605 info->nsid);
e2d77d2e
CH		 3606 goto out_unlock;
3607 }
1a893c2b 3608 head = nvme_alloc_ns_head(ctrl, info);
ed754e5d
CH		 3609 if (IS_ERR(head)) {
3610 ret = PTR_ERR(head);
3611 goto out_unlock;
3612 }
ed754e5d 3613 } else {
6623c5b3 3614 ret = -EINVAL;
1a893c2b 3615 if (!info->is_shared || !head->shared) {
9ad1927a 3616 dev_err(ctrl->device,
1a893c2b
CH		 3617 "Duplicate unshared namespace %d\n",
3618 info->nsid);
6623c5b3 3619 goto out_put_ns_head;
9ad1927a 3620 }
1a893c2b 3621 if (!nvme_ns_ids_equal(&head->ids, &info->ids)) {
ed754e5d
CH		 3622 dev_err(ctrl->device,
3623 "IDs don't match for shared namespace %d\n",
1a893c2b 3624 info->nsid);
6623c5b3 3625 goto out_put_ns_head;
ed754e5d 3626 }
ce8d7861 3627
2110a6bc 3628 if (!multipath) {
ce8d7861
CH		 3629 dev_warn(ctrl->device,
3630 "Found shared namespace %d, but multipathing not supported.\n",
1a893c2b 3631 info->nsid);
ce8d7861
CH		 3632 dev_warn_once(ctrl->device,
3633 "Support for shared namespaces without CONFIG_NVME_MULTIPATH is deprecated and will be removed in Linux 6.0\n.");
3634 }
ed754e5d
CH		 3635 }
3636
772ea326 3637 list_add_tail_rcu(&ns->siblings, &head->list);
ed754e5d 3638 ns->head = head;
6623c5b3
CH		 3639 mutex_unlock(&ctrl->subsys->lock);
3640 return 0;
ed754e5d 3641
6623c5b3
CH		 3642out_put_ns_head:
3643 nvme_put_ns_head(head);
ed754e5d
CH		 3644out_unlock:
3645 mutex_unlock(&ctrl->subsys->lock);
3646 return ret;
3647}
3648
24493b8b 3649struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3650{
32f0c4af 3651 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 3652
765cc031 3653 down_read(&ctrl->namespaces_rwsem);
5bae7f73 3654 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 3655 if (ns->head->ns_id == nsid) {
4c74d1f8 3656 if (!nvme_get_ns(ns))
2dd41228 3657 continue;
32f0c4af
KB		 3658 ret = ns;
3659 break;
3660 }
ed754e5d 3661 if (ns->head->ns_id > nsid)
5bae7f73
CH		 3662 break;
3663 }
765cc031 3664 up_read(&ctrl->namespaces_rwsem);
32f0c4af 3665 return ret;
5bae7f73 3666}
24493b8b 3667EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU);
5bae7f73 3668
298ba0e3
CH		 3669/*
3670 * Add the namespace to the controller list while keeping the list ordered.
3671 */
3672static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns)
3673{
3674 struct nvme_ns *tmp;
3675
3676 list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) {
3677 if (tmp->head->ns_id < ns->head->ns_id) {
3678 list_add(&ns->list, &tmp->list);
3679 return;
3680 }
3681 }
3682 list_add(&ns->list, &ns->ctrl->namespaces);
3683}
3684
1a893c2b 3685static void nvme_alloc_ns(struct nvme_ctrl *ctrl, struct nvme_ns_info *info)
5bae7f73
CH		 3686{
3687 struct nvme_ns *ns;
3688 struct gendisk *disk;
9953ab0c 3689 int node = ctrl->numa_node;
5bae7f73
CH		 3690
3691 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3692 if (!ns)
1a893c2b 3693 return;
5bae7f73 3694
5f432cce
CH		 3695 disk = blk_mq_alloc_disk(ctrl->tagset, ns);
3696 if (IS_ERR(disk))
ed754e5d 3697 goto out_free_ns;
5f432cce
CH		 3698 disk->fops = &nvme_bdev_ops;
3699 disk->private_data = ns;
3700
3701 ns->disk = disk;
3702 ns->queue = disk->queue;
e0596ab2 3703
7d30c81b 3704 if (ctrl->opts && ctrl->opts->data_digest)
1cb039f3 3705 blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, ns->queue);
958f2a0f 3706
8b904b5b 3707 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
2f859441
LG		 3708 if (ctrl->ops->supports_pci_p2pdma &&
3709 ctrl->ops->supports_pci_p2pdma(ctrl))
e0596ab2
LG		 3710 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3711
5bae7f73 3712 ns->ctrl = ctrl;
5bae7f73 3713 kref_init(&ns->kref);
5bae7f73 3714
1a893c2b 3715 if (nvme_init_ns_head(ns, info))
5f432cce 3716 goto out_cleanup_disk;
ac81bfa9 3717
9953ab0c 3718 /*
b739e137
CH		 3719 * If multipathing is enabled, the device name for all disks and not
3720 * just those that represent shared namespaces needs to be based on the
3721 * subsystem instance. Using the controller instance for private
3722 * namespaces could lead to naming collisions between shared and private
3723 * namespaces if they don't use a common numbering scheme.
3724 *
3725 * If multipathing is not enabled, disk names must use the controller
3726 * instance as shared namespaces will show up as multiple block
3727 * devices.
9953ab0c 3728 */
35e797b0 3729 if (nvme_ns_head_multipath(ns->head)) {
b739e137
CH		 3730 sprintf(disk->disk_name, "nvme%dc%dn%d", ctrl->subsys->instance,
3731 ctrl->instance, ns->head->instance);
3732 disk->flags |= GENHD_FL_HIDDEN;
3733 } else if (multipath) {
3734 sprintf(disk->disk_name, "nvme%dn%d", ctrl->subsys->instance,
3735 ns->head->instance);
3736 } else {
9953ab0c
CH		 3737 sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance,
3738 ns->head->instance);
b739e137 3739 }
3dc87dd0 3740
1a893c2b 3741 if (nvme_update_ns_info(ns, info))
5f432cce 3742 goto out_unlink_ns;
5bae7f73 3743
765cc031 3744 down_write(&ctrl->namespaces_rwsem);
839a40d1
BH		 3745 /*
3746 * Ensure that no namespaces are added to the ctrl list after the queues
3747 * are frozen, thereby avoiding a deadlock between scan and reset.
3748 */
3749 if (test_bit(NVME_CTRL_FROZEN, &ctrl->flags)) {
3750 up_write(&ctrl->namespaces_rwsem);
3751 goto out_unlink_ns;
3752 }
298ba0e3 3753 nvme_ns_add_to_ctrl_list(ns);
765cc031 3754 up_write(&ctrl->namespaces_rwsem);
d22524a4 3755 nvme_get_ctrl(ctrl);
ac81bfa9 3756
83ac678e 3757 if (device_add_disk(ctrl->device, ns->disk, nvme_ns_attr_groups))
ab3994f6
LC		 3758 goto out_cleanup_ns_from_list;
3759
2637baed
MI		 3760 if (!nvme_ns_head_multipath(ns->head))
3761 nvme_add_ns_cdev(ns);
32acab31 3762
1a893c2b 3763 nvme_mpath_add_disk(ns, info->anagrpid);
a3646451 3764 nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name);
0d0b660f 3765
9f079dda
AA		 3766 /*
3767 * Set ns->disk->device->driver_data to ns so we can access
e8c263ed
CK		 3768 * ns->head->passthru_err_log_enabled in
3769 * nvme_io_passthru_err_log_enabled_[store | show]().
9f079dda
AA		 3770 */
3771 dev_set_drvdata(disk_to_dev(ns->disk), ns);
3772
adce7e98 3773 return;
5f432cce 3774
ab3994f6
LC		 3775 out_cleanup_ns_from_list:
3776 nvme_put_ctrl(ctrl);
3777 down_write(&ctrl->namespaces_rwsem);
3778 list_del_init(&ns->list);
3779 up_write(&ctrl->namespaces_rwsem);
ed754e5d
CH		 3780 out_unlink_ns:
3781 mutex_lock(&ctrl->subsys->lock);
3782 list_del_rcu(&ns->siblings);
d5675729
KB		 3783 if (list_empty(&ns->head->list))
3784 list_del_init(&ns->head->entry);
ed754e5d 3785 mutex_unlock(&ctrl->subsys->lock);
a63b8370 3786 nvme_put_ns_head(ns->head);
5f432cce 3787 out_cleanup_disk:
8b9ab626 3788 put_disk(disk);
5bae7f73
CH		 3789 out_free_ns:
3790 kfree(ns);
3791}
3792
3793static void nvme_ns_remove(struct nvme_ns *ns)
3794{
5396fdac
HR		 3795 bool last_path = false;
3796
646017a6
KB		 3797 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3798 return;
69d3b8ac 3799
e7d65803 3800 clear_bit(NVME_NS_READY, &ns->flags);
0a05226a 3801 set_capacity(ns->disk, 0);
a3646451 3802 nvme_fault_inject_fini(&ns->fault_inject);
2181e455 3803
d6d67427
CL		 3804 /*
3805 * Ensure that !NVME_NS_READY is seen by other threads to prevent
3806 * this ns going back into current_path.
3807 */
3808 synchronize_srcu(&ns->head->srcu);
3809
3810 /* wait for concurrent submissions */
3811 if (nvme_mpath_clear_current_path(ns))
3812 synchronize_srcu(&ns->head->srcu);
3813
2181e455
AE		 3814 mutex_lock(&ns->ctrl->subsys->lock);
3815 list_del_rcu(&ns->siblings);
9edceaf4
DW		 3816 if (list_empty(&ns->head->list)) {
3817 list_del_init(&ns->head->entry);
3818 last_path = true;
3819 }
2181e455 3820 mutex_unlock(&ns->ctrl->subsys->lock);
d5675729 3821
041bd1a1 3822 /* guarantee not available in head->list */
899d2a05 3823 synchronize_srcu(&ns->head->srcu);
041bd1a1 3824
5eba2005
CH		 3825 if (!nvme_ns_head_multipath(ns->head))
3826 nvme_cdev_del(&ns->cdev, &ns->cdev_device);
3827 del_gendisk(ns->disk);
32f0c4af 3828
765cc031 3829 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3830 list_del_init(&ns->list);
765cc031 3831 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3832
5396fdac
HR		 3833 if (last_path)
3834 nvme_mpath_shutdown_disk(ns->head);
5bae7f73
CH		 3835 nvme_put_ns(ns);
3836}
3837
4450ba3b
CH		 3838static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid)
3839{
3840 struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid);
3841
3842 if (ns) {
3843 nvme_ns_remove(ns);
3844 nvme_put_ns(ns);
3845 }
3846}
3847
1a893c2b 3848static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_info *info)
b2dc748a 3849{
d95c1f41 3850 int ret = NVME_SC_INVALID_NS | NVME_SC_DNR;
b2dc748a 3851
1a893c2b 3852 if (!nvme_ns_ids_equal(&ns->head->ids, &info->ids)) {
af5d6f7b 3853 dev_err(ns->ctrl->device,
b2dc748a 3854 "identifiers changed for nsid %d\n", ns->head->ns_id);
1a893c2b 3855 goto out;
b2dc748a
CH		 3856 }
3857
1a893c2b 3858 ret = nvme_update_ns_info(ns, info);
b2dc748a
CH		 3859out:
3860 /*
0a05226a 3861 * Only remove the namespace if we got a fatal error back from the
b2dc748a 3862 * device, otherwise ignore the error and just move on.
0a05226a
CH		 3863 *
3864 * TODO: we should probably schedule a delayed retry here.
b2dc748a 3865 */
d95c1f41 3866 if (ret > 0 && (ret & NVME_SC_DNR))
0a05226a 3867 nvme_ns_remove(ns);
b2dc748a
CH		 3868}
3869
04c170f6 3870static void nvme_scan_ns(struct nvme_ctrl *ctrl, unsigned nsid)
540c801c 3871{
1a893c2b 3872 struct nvme_ns_info info = { .nsid = nsid };
540c801c 3873 struct nvme_ns *ns;
0dd6fff2 3874 int ret;
540c801c 3875
1a893c2b 3876 if (nvme_identify_ns_descs(ctrl, &info))
8b7c0ff2 3877 return;
540c801c 3878
1a893c2b 3879 if (info.ids.csi != NVME_CSI_NVM && !nvme_multi_css(ctrl)) {
71882e7d
CH		 3880 dev_warn(ctrl->device,
3881 "command set not reported for nsid: %d\n", nsid);
3882 return;
3883 }
3884
354201c5 3885 /*
1a893c2b
CH		 3886 * If available try to use the Command Set Idependent Identify Namespace
3887 * data structure to find all the generic information that is needed to
3888 * set up a namespace. If not fall back to the legacy version.
354201c5 3889 */
eb867ee9 3890 if ((ctrl->cap & NVME_CAP_CRMS_CRIMS) ||
0dd6fff2
CH		 3891 (info.ids.csi != NVME_CSI_NVM && info.ids.csi != NVME_CSI_ZNS))
3892 ret = nvme_ns_info_from_id_cs_indep(ctrl, &info);
3893 else
3894 ret = nvme_ns_info_from_identify(ctrl, &info);
3895
3896 if (info.is_removed)
3897 nvme_ns_remove_by_nsid(ctrl, nsid);
354201c5 3898
1a893c2b
CH		 3899 /*
3900 * Ignore the namespace if it is not ready. We will get an AEN once it
3901 * becomes ready and restart the scan.
3902 */
0dd6fff2 3903 if (ret || !info.is_ready)
354201c5
CH		 3904 return;
3905
32f0c4af 3906 ns = nvme_find_get_ns(ctrl, nsid);
8b7c0ff2 3907 if (ns) {
1a893c2b 3908 nvme_validate_ns(ns, &info);
8b7c0ff2 3909 nvme_put_ns(ns);
1a893c2b
CH		 3910 } else {
3911 nvme_alloc_ns(ctrl, &info);
8b7c0ff2 3912 }
540c801c
KB		 3913}
3914
47b0e50a
SB		 3915static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3916 unsigned nsid)
3917{
3918 struct nvme_ns *ns, *next;
6f8e0d78 3919 LIST_HEAD(rm_list);
47b0e50a 3920
765cc031 3921 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3922 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
4f17344e 3923 if (ns->head->ns_id > nsid)
6f8e0d78 3924 list_move_tail(&ns->list, &rm_list);
47b0e50a 3925 }
765cc031 3926 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3927
3928 list_for_each_entry_safe(ns, next, &rm_list, list)
3929 nvme_ns_remove(ns);
3930
47b0e50a
SB		 3931}
3932
4005f28d 3933static int nvme_scan_ns_list(struct nvme_ctrl *ctrl)
540c801c 3934{
aec459b4 3935 const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32);
540c801c 3936 __le32 *ns_list;
4005f28d
CH		 3937 u32 prev = 0;
3938 int ret = 0, i;
540c801c 3939
42595eb7 3940 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3941 if (!ns_list)
3942 return -ENOMEM;
3943
4005f28d 3944 for (;;) {
7b153362
CH		 3945 struct nvme_command cmd = {
3946 .identify.opcode = nvme_admin_identify,
3947 .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST,
3948 .identify.nsid = cpu_to_le32(prev),
3949 };
3950
3951 ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list,
3952 NVME_IDENTIFY_DATA_SIZE);
f781f3dd
MI		 3953 if (ret) {
3954 dev_warn(ctrl->device,
3955 "Identify NS List failed (status=0x%x)\n", ret);
47b0e50a 3956 goto free;
f781f3dd 3957 }
540c801c 3958
aec459b4 3959 for (i = 0; i < nr_entries; i++) {
4005f28d 3960 u32 nsid = le32_to_cpu(ns_list[i]);
540c801c 3961
4005f28d
CH		 3962 if (!nsid) /* end of the list? */
3963 goto out;
04c170f6 3964 nvme_scan_ns(ctrl, nsid);
4450ba3b
CH		 3965 while (++prev < nsid)
3966 nvme_ns_remove_by_nsid(ctrl, prev);
540c801c 3967 }
540c801c
KB		 3968 }
3969 out:
47b0e50a
SB		 3970 nvme_remove_invalid_namespaces(ctrl, prev);
3971 free:
540c801c
KB		 3972 kfree(ns_list);
3973 return ret;
3974}
3975
4005f28d 3976static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl)
5bae7f73 3977{
4005f28d
CH		 3978 struct nvme_id_ctrl *id;
3979 u32 nn, i;
3980
3981 if (nvme_identify_ctrl(ctrl, &id))
3982 return;
3983 nn = le32_to_cpu(id->nn);
3984 kfree(id);
5bae7f73 3985
540c801c 3986 for (i = 1; i <= nn; i++)
04c170f6 3987 nvme_scan_ns(ctrl, i);
540c801c 3988
47b0e50a 3989 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3990}
3991
f493af37 3992static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 3993{
3994 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
3995 __le32 *log;
f493af37 3996 int error;
30d90964
CH		 3997
3998 log = kzalloc(log_size, GFP_KERNEL);
3999 if (!log)
f493af37 4000 return;
30d90964 4001
f493af37
CH		 4002 /*
4003 * We need to read the log to clear the AEN, but we don't want to rely
4004 * on it for the changed namespace information as userspace could have
4005 * raced with us in reading the log page, which could cause us to miss
4006 * updates.
4007 */
be93e87e
KB		 4008 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0,
4009 NVME_CSI_NVM, log, log_size, 0);
f493af37 4010 if (error)
30d90964
CH		 4011 dev_warn(ctrl->device,
4012 "reading changed ns log failed: %d\n", error);
30d90964 4013
30d90964 4014 kfree(log);
30d90964
CH		 4015}
4016
5955be21 4017static void nvme_scan_work(struct work_struct *work)
5bae7f73 4018{
5955be21
CH		 4019 struct nvme_ctrl *ctrl =
4020 container_of(work, struct nvme_ctrl, scan_work);
78288665 4021 int ret;
5bae7f73 4022
5d02a5c1 4023 /* No tagset on a live ctrl means IO queues could not created */
e6e7f7ac 4024 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE || !ctrl->tagset)
5955be21
CH		 4025 return;
4026
78288665
CK		 4027 /*
4028 * Identify controller limits can change at controller reset due to
4029 * new firmware download, even though it is not common we cannot ignore
4030 * such scenario. Controller's non-mdts limits are reported in the unit
4031 * of logical blocks that is dependent on the format of attached
4032 * namespace. Hence re-read the limits at the time of ns allocation.
4033 */
4034 ret = nvme_init_non_mdts_limits(ctrl);
4035 if (ret < 0) {
4036 dev_warn(ctrl->device,
4037 "reading non-mdts-limits failed: %d\n", ret);
4038 return;
4039 }
4040
77016199 4041 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 4042 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 4043 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 4044 }
4045
e7ad43c3 4046 mutex_lock(&ctrl->scan_lock);
811f4de0 4047 if (nvme_ctrl_limited_cns(ctrl)) {
4005f28d 4048 nvme_scan_ns_sequential(ctrl);
811f4de0
US		 4049 } else {
4050 /*
4051 * Fall back to sequential scan if DNR is set to handle broken
4052 * devices which should support Identify NS List (as per the VS
4053 * they report) but don't actually support it.
4054 */
4055 ret = nvme_scan_ns_list(ctrl);
4056 if (ret > 0 && ret & NVME_SC_DNR)
4057 nvme_scan_ns_sequential(ctrl);
4058 }
e7ad43c3 4059 mutex_unlock(&ctrl->scan_lock);
5955be21 4060}
5bae7f73 4061
32f0c4af
KB		 4062/*
4063 * This function iterates the namespace list unlocked to allow recovery from
4064 * controller failure. It is up to the caller to ensure the namespace list is
4065 * not modified by scan work while this function is executing.
4066 */
5bae7f73
CH		 4067void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
4068{
4069 struct nvme_ns *ns, *next;
6f8e0d78 4070 LIST_HEAD(ns_list);
5bae7f73 4071
0157ec8d
SG		 4072 /*
4073 * make sure to requeue I/O to all namespaces as these
4074 * might result from the scan itself and must complete
4075 * for the scan_work to make progress
4076 */
4077 nvme_mpath_clear_ctrl_paths(ctrl);
4078
1b95e817
ML		 4079 /*
4080 * Unquiesce io queues so any pending IO won't hang, especially
4081 * those submitted from scan work
4082 */
4083 nvme_unquiesce_io_queues(ctrl);
4084
f6c8e432
SG		 4085 /* prevent racing with ns scanning */
4086 flush_work(&ctrl->scan_work);
4087
0ff9d4e1
KB		 4088 /*
4089 * The dead states indicates the controller was not gracefully
4090 * disconnected. In that case, we won't be able to flush any data while
4091 * removing the namespaces' disks; fail all the queues now to avoid
4092 * potentially having to clean up the failed sync later.
4093 */
e6e7f7ac 4094 if (nvme_ctrl_state(ctrl) == NVME_CTRL_DEAD)
cd50f9b2 4095 nvme_mark_namespaces_dead(ctrl);
0ff9d4e1 4096
ecca390e
SG		 4097 /* this is a no-op when called from the controller reset handler */
4098 nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO);
4099
765cc031 4100 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 4101 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 4102 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 4103
4104 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 4105 nvme_ns_remove(ns);
4106}
576d55d6 4107EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 4108
23680f0b 4109static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env)
a42f42e5 4110{
23680f0b 4111 const struct nvme_ctrl *ctrl =
a42f42e5
SG		 4112 container_of(dev, struct nvme_ctrl, ctrl_device);
4113 struct nvmf_ctrl_options *opts = ctrl->opts;
4114 int ret;
4115
4116 ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name);
4117 if (ret)
4118 return ret;
4119
4120 if (opts) {
4121 ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr);
4122 if (ret)
4123 return ret;
4124
4125 ret = add_uevent_var(env, "NVME_TRSVCID=%s",
4126 opts->trsvcid ?: "none");
4127 if (ret)
4128 return ret;
4129
4130 ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s",
4131 opts->host_traddr ?: "none");
3ede8f72
MB		 4132 if (ret)
4133 return ret;
4134
4135 ret = add_uevent_var(env, "NVME_HOST_IFACE=%s",
4136 opts->host_iface ?: "none");
a42f42e5
SG		 4137 }
4138 return ret;
4139}
4140
20d64911
MB		 4141static void nvme_change_uevent(struct nvme_ctrl *ctrl, char *envdata)
4142{
4143 char *envp[2] = { envdata, NULL };
4144
4145 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4146}
4147
e3d7874d
KB		 4148static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
4149{
4150 char *envp[2] = { NULL, NULL };
4151 u32 aen_result = ctrl->aen_result;
4152
4153 ctrl->aen_result = 0;
4154 if (!aen_result)
4155 return;
4156
4157 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
4158 if (!envp[0])
4159 return;
4160 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4161 kfree(envp[0]);
4162}
4163
f866fc42
CH		 4164static void nvme_async_event_work(struct work_struct *work)
4165{
4166 struct nvme_ctrl *ctrl =
4167 container_of(work, struct nvme_ctrl, async_event_work);
4168
e3d7874d 4169 nvme_aen_uevent(ctrl);
0fa0f99f
SG		 4170
4171 /*
4172 * The transport drivers must guarantee AER submission here is safe by
4173 * flushing ctrl async_event_work after changing the controller state
4174 * from LIVE and before freeing the admin queue.
4175 */
e6e7f7ac 4176 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE)
0fa0f99f 4177 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 4178}
4179
b6dccf7f
AD		 4180static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
4181{
4182
4183 u32 csts;
4184
4185 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
4186 return false;
4187
4188 if (csts == ~0)
4189 return false;
4190
4191 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
4192}
4193
4194static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
4195{
b6dccf7f 4196 struct nvme_fw_slot_info_log *log;
f0377ff9 4197 u8 next_fw_slot, cur_fw_slot;
b6dccf7f
AD		 4198
4199 log = kmalloc(sizeof(*log), GFP_KERNEL);
4200 if (!log)
4201 return;
4202
be93e87e 4203 if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM,
983a338b 4204 log, sizeof(*log), 0)) {
0e98719b 4205 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
983a338b
DW		 4206 goto out_free_log;
4207 }
4208
f0377ff9
ML		 4209 cur_fw_slot = log->afi & 0x7;
4210 next_fw_slot = (log->afi & 0x70) >> 4;
4211 if (!cur_fw_slot || (next_fw_slot && (cur_fw_slot != next_fw_slot))) {
983a338b
DW		 4212 dev_info(ctrl->device,
4213 "Firmware is activated after next Controller Level Reset\n");
4214 goto out_free_log;
4215 }
4216
f0377ff9 4217 memcpy(ctrl->subsys->firmware_rev, &log->frs[cur_fw_slot - 1],
983a338b
DW		 4218 sizeof(ctrl->subsys->firmware_rev));
4219
4220out_free_log:
b6dccf7f
AD		 4221 kfree(log);
4222}
4223
4224static void nvme_fw_act_work(struct work_struct *work)
4225{
4226 struct nvme_ctrl *ctrl = container_of(work,
4227 struct nvme_ctrl, fw_act_work);
4228 unsigned long fw_act_timeout;
4229
f6fe0b2d
ML		 4230 nvme_auth_stop(ctrl);
4231
b6dccf7f
AD		 4232 if (ctrl->mtfa)
4233 fw_act_timeout = jiffies +
4234 msecs_to_jiffies(ctrl->mtfa * 100);
4235 else
4236 fw_act_timeout = jiffies +
4237 msecs_to_jiffies(admin_timeout * 1000);
4238
9f27bd70 4239 nvme_quiesce_io_queues(ctrl);
b6dccf7f
AD		 4240 while (nvme_ctrl_pp_status(ctrl)) {
4241 if (time_after(jiffies, fw_act_timeout)) {
4242 dev_warn(ctrl->device,
4243 "Fw activation timeout, reset controller\n");
4c75f877
KB		 4244 nvme_try_sched_reset(ctrl);
4245 return;
b6dccf7f
AD		 4246 }
4247 msleep(100);
4248 }
4249
4c75f877 4250 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE))
b6dccf7f
AD		 4251 return;
4252
9f27bd70 4253 nvme_unquiesce_io_queues(ctrl);
a806c6c8 4254 /* read FW slot information to clear the AER */
b6dccf7f 4255 nvme_get_fw_slot_info(ctrl);
371a982c
KB		 4256
4257 queue_work(nvme_wq, &ctrl->async_event_work);
b6dccf7f
AD		 4258}
4259
2c61c97f
MK		 4260static u32 nvme_aer_type(u32 result)
4261{
4262 return result & 0x7;
4263}
4264
4265static u32 nvme_aer_subtype(u32 result)
4266{
4267 return (result & 0xff00) >> 8;
4268}
4269
371a982c 4270static bool nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
868c2392 4271{
2c61c97f 4272 u32 aer_notice_type = nvme_aer_subtype(result);
371a982c 4273 bool requeue = true;
09bd1ff4
CK		 4274
4275 switch (aer_notice_type) {
868c2392 4276 case NVME_AER_NOTICE_NS_CHANGED:
77016199 4277 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 4278 nvme_queue_scan(ctrl);
4279 break;
4280 case NVME_AER_NOTICE_FW_ACT_STARTING:
4c75f877
KB		 4281 /*
4282 * We are (ab)using the RESETTING state to prevent subsequent
4283 * recovery actions from interfering with the controller's
4284 * firmware activation.
4285 */
f50fff73 4286 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) {
371a982c 4287 requeue = false;
4c75f877 4288 queue_work(nvme_wq, &ctrl->fw_act_work);
f50fff73 4289 }
868c2392 4290 break;
0d0b660f
CH		 4291#ifdef CONFIG_NVME_MULTIPATH
4292 case NVME_AER_NOTICE_ANA:
4293 if (!ctrl->ana_log_buf)
4294 break;
4295 queue_work(nvme_wq, &ctrl->ana_work);
4296 break;
4297#endif
85f8a435
SG		 4298 case NVME_AER_NOTICE_DISC_CHANGED:
4299 ctrl->aen_result = result;
4300 break;
868c2392
CH		 4301 default:
4302 dev_warn(ctrl->device, "async event result %08x\n", result);
4303 }
371a982c 4304 return requeue;
868c2392
CH		 4305}
4306
2c61c97f
MK		 4307static void nvme_handle_aer_persistent_error(struct nvme_ctrl *ctrl)
4308{
2c61c97f
MK		 4309 dev_warn(ctrl->device, "resetting controller due to AER\n");
4310 nvme_reset_ctrl(ctrl);
4311}
4312
7bf58533 4313void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 4314 volatile union nvme_result *res)
f866fc42 4315{
7bf58533 4316 u32 result = le32_to_cpu(res->u32);
2c61c97f
MK		 4317 u32 aer_type = nvme_aer_type(result);
4318 u32 aer_subtype = nvme_aer_subtype(result);
371a982c 4319 bool requeue = true;
f866fc42 4320
ad22c355 4321 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 4322 return;
4323
6622b76f 4324 trace_nvme_async_event(ctrl, result);
09bd1ff4 4325 switch (aer_type) {
868c2392 4326 case NVME_AER_NOTICE:
371a982c 4327 requeue = nvme_handle_aen_notice(ctrl, result);
868c2392 4328 break;
e3d7874d 4329 case NVME_AER_ERROR:
2c61c97f
MK		 4330 /*
4331 * For a persistent internal error, don't run async_event_work
4332 * to submit a new AER. The controller reset will do it.
4333 */
4334 if (aer_subtype == NVME_AER_ERROR_PERSIST_INT_ERR) {
4335 nvme_handle_aer_persistent_error(ctrl);
4336 return;
4337 }
4338 fallthrough;
e3d7874d
KB		 4339 case NVME_AER_SMART:
4340 case NVME_AER_CSS:
4341 case NVME_AER_VS:
4342 ctrl->aen_result = result;
7bf58533
CH		 4343 break;
4344 default:
4345 break;
f866fc42 4346 }
371a982c
KB		 4347
4348 if (requeue)
4349 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 4350}
f866fc42 4351EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 4352
fe60e8c5 4353int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
db45e1a5 4354 const struct blk_mq_ops *ops, unsigned int cmd_size)
fe60e8c5
CH		 4355{
4356 int ret;
4357
4358 memset(set, 0, sizeof(*set));
4359 set->ops = ops;
4360 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
4361 if (ctrl->ops->flags & NVME_F_FABRICS)
4362 set->reserved_tags = NVMF_RESERVED_TAGS;
4363 set->numa_node = ctrl->numa_node;
db45e1a5
CH		 4364 set->flags = BLK_MQ_F_NO_SCHED;
4365 if (ctrl->ops->flags & NVME_F_BLOCKING)
4366 set->flags |= BLK_MQ_F_BLOCKING;
fe60e8c5
CH		 4367 set->cmd_size = cmd_size;
4368 set->driver_data = ctrl;
4369 set->nr_hw_queues = 1;
4370 set->timeout = NVME_ADMIN_TIMEOUT;
4371 ret = blk_mq_alloc_tag_set(set);
4372 if (ret)
4373 return ret;
4374
4375 ctrl->admin_q = blk_mq_init_queue(set);
4376 if (IS_ERR(ctrl->admin_q)) {
4377 ret = PTR_ERR(ctrl->admin_q);
4378 goto out_free_tagset;
4379 }
4380
4381 if (ctrl->ops->flags & NVME_F_FABRICS) {
4382 ctrl->fabrics_q = blk_mq_init_queue(set);
4383 if (IS_ERR(ctrl->fabrics_q)) {
4384 ret = PTR_ERR(ctrl->fabrics_q);
4385 goto out_cleanup_admin_q;
4386 }
4387 }
4388
4389 ctrl->admin_tagset = set;
4390 return 0;
4391
4392out_cleanup_admin_q:
4739824e 4393 blk_mq_destroy_queue(ctrl->admin_q);
2b3f056f 4394 blk_put_queue(ctrl->admin_q);
fe60e8c5 4395out_free_tagset:
fd62678a
ML		 4396 blk_mq_free_tag_set(set);
4397 ctrl->admin_q = NULL;
4398 ctrl->fabrics_q = NULL;
fe60e8c5
CH		 4399 return ret;
4400}
4401EXPORT_SYMBOL_GPL(nvme_alloc_admin_tag_set);
4402
4403void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl)
4404{
4405 blk_mq_destroy_queue(ctrl->admin_q);
2b3f056f
CH		 4406 blk_put_queue(ctrl->admin_q);
4407 if (ctrl->ops->flags & NVME_F_FABRICS) {
fe60e8c5 4408 blk_mq_destroy_queue(ctrl->fabrics_q);
2b3f056f
CH		 4409 blk_put_queue(ctrl->fabrics_q);
4410 }
fe60e8c5
CH		 4411 blk_mq_free_tag_set(ctrl->admin_tagset);
4412}
4413EXPORT_SYMBOL_GPL(nvme_remove_admin_tag_set);
4414
4415int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
db45e1a5 4416 const struct blk_mq_ops *ops, unsigned int nr_maps,
fe60e8c5
CH		 4417 unsigned int cmd_size)
4418{
4419 int ret;
4420
4421 memset(set, 0, sizeof(*set));
4422 set->ops = ops;
33b93727 4423 set->queue_depth = min_t(unsigned, ctrl->sqsize, BLK_MQ_MAX_DEPTH - 1);
93b24f57
CH		 4424 /*
4425 * Some Apple controllers requires tags to be unique across admin and
4426 * the (only) I/O queue, so reserve the first 32 tags of the I/O queue.
4427 */
4428 if (ctrl->quirks & NVME_QUIRK_SHARED_TAGS)
4429 set->reserved_tags = NVME_AQ_DEPTH;
4430 else if (ctrl->ops->flags & NVME_F_FABRICS)
b794d1c2 4431 set->reserved_tags = NVMF_RESERVED_TAGS;
fe60e8c5 4432 set->numa_node = ctrl->numa_node;
db45e1a5
CH		 4433 set->flags = BLK_MQ_F_SHOULD_MERGE;
4434 if (ctrl->ops->flags & NVME_F_BLOCKING)
4435 set->flags |= BLK_MQ_F_BLOCKING;
fe60e8c5
CH		 4436 set->cmd_size = cmd_size,
4437 set->driver_data = ctrl;
4438 set->nr_hw_queues = ctrl->queue_count - 1;
4439 set->timeout = NVME_IO_TIMEOUT;
dcef7727 4440 set->nr_maps = nr_maps;
fe60e8c5
CH		 4441 ret = blk_mq_alloc_tag_set(set);
4442 if (ret)
4443 return ret;
4444
4445 if (ctrl->ops->flags & NVME_F_FABRICS) {
4446 ctrl->connect_q = blk_mq_init_queue(set);
4447 if (IS_ERR(ctrl->connect_q)) {
4448 ret = PTR_ERR(ctrl->connect_q);
4449 goto out_free_tag_set;
4450 }
98d81f0d
CL		 4451 blk_queue_flag_set(QUEUE_FLAG_SKIP_TAGSET_QUIESCE,
4452 ctrl->connect_q);
fe60e8c5
CH		 4453 }
4454
4455 ctrl->tagset = set;
4456 return 0;
4457
4458out_free_tag_set:
4459 blk_mq_free_tag_set(set);
6fbf13c0 4460 ctrl->connect_q = NULL;
fe60e8c5
CH		 4461 return ret;
4462}
4463EXPORT_SYMBOL_GPL(nvme_alloc_io_tag_set);
4464
4465void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl)
4466{
2b3f056f 4467 if (ctrl->ops->flags & NVME_F_FABRICS) {
fe60e8c5 4468 blk_mq_destroy_queue(ctrl->connect_q);
2b3f056f
CH		 4469 blk_put_queue(ctrl->connect_q);
4470 }
fe60e8c5
CH		 4471 blk_mq_free_tag_set(ctrl->tagset);
4472}
4473EXPORT_SYMBOL_GPL(nvme_remove_io_tag_set);
4474
d09f2b45 4475void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 4476{
0d0b660f 4477 nvme_mpath_stop(ctrl);
f50fff73 4478 nvme_auth_stop(ctrl);
3af755a4 4479 nvme_stop_keep_alive(ctrl);
8c4dfea9 4480 nvme_stop_failfast_work(ctrl);
f866fc42 4481 flush_work(&ctrl->async_event_work);
b6dccf7f 4482 cancel_work_sync(&ctrl->fw_act_work);
f7f70f4a
RL		 4483 if (ctrl->ops->stop_ctrl)
4484 ctrl->ops->stop_ctrl(ctrl);
d09f2b45
SG		 4485}
4486EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
4487
4488void nvme_start_ctrl(struct nvme_ctrl *ctrl)
4489{
93da4023
SG		 4490 nvme_enable_aen(ctrl);
4491
f46ef9e8
SG		 4492 /*
4493 * persistent discovery controllers need to send indication to userspace
4494 * to re-read the discovery log page to learn about possible changes
4495 * that were missed. We identify persistent discovery controllers by
4496 * checking that they started once before, hence are reconnecting back.
4497 */
2eb94dd5 4498 if (test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) &&
f46ef9e8
SG		 4499 nvme_discovery_ctrl(ctrl))
4500 nvme_change_uevent(ctrl, "NVME_EVENT=rediscover");
4501
d09f2b45
SG		 4502 if (ctrl->queue_count > 1) {
4503 nvme_queue_scan(ctrl);
9f27bd70 4504 nvme_unquiesce_io_queues(ctrl);
a4a6f3c8 4505 nvme_mpath_update(ctrl);
d09f2b45 4506 }
20d64911
MB		 4507
4508 nvme_change_uevent(ctrl, "NVME_EVENT=connected");
2eb94dd5 4509 set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags);
d09f2b45
SG		 4510}
4511EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 4512
d09f2b45
SG		 4513void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
4514{
ed7770f6 4515 nvme_hwmon_exit(ctrl);
f79d5fda 4516 nvme_fault_inject_fini(&ctrl->fault_inject);
510a405d 4517 dev_pm_qos_hide_latency_tolerance(ctrl->device);
a6a5149b 4518 cdev_device_del(&ctrl->cdev, ctrl->device);
726612b6 4519 nvme_put_ctrl(ctrl);
53029b04 4520}
576d55d6 4521EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 4522
8168d23f
KB		 4523static void nvme_free_cels(struct nvme_ctrl *ctrl)
4524{
4525 struct nvme_effects_log *cel;
4526 unsigned long i;
4527
8f8ea928 4528 xa_for_each(&ctrl->cels, i, cel) {
8168d23f
KB		 4529 xa_erase(&ctrl->cels, i);
4530 kfree(cel);
4531 }
4532
4533 xa_destroy(&ctrl->cels);
4534}
4535
d22524a4 4536static void nvme_free_ctrl(struct device *dev)
53029b04 4537{
d22524a4
CH		 4538 struct nvme_ctrl *ctrl =
4539 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 4540 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 4541
192f6c29 4542 if (!subsys || ctrl->instance != subsys->instance)
8b850475 4543 ida_free(&nvme_instance_ida, ctrl->instance);
be8e82ca 4544 key_put(ctrl->tls_key);
8168d23f 4545 nvme_free_cels(ctrl);
0d0b660f 4546 nvme_mpath_uninit(ctrl);
f50fff73
HR		 4547 nvme_auth_stop(ctrl);
4548 nvme_auth_free(ctrl);
092ff052 4549 __free_page(ctrl->discard_page);
94cc781f 4550 free_opal_dev(ctrl->opal_dev);
f3ca80fc 4551
ab9e00cc 4552 if (subsys) {
32fd90c4 4553 mutex_lock(&nvme_subsystems_lock);
ab9e00cc 4554 list_del(&ctrl->subsys_entry);
ab9e00cc 4555 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
32fd90c4 4556 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 4557 }
f3ca80fc
CH		 4558
4559 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 4560
ab9e00cc
CH		 4561 if (subsys)
4562 nvme_put_subsystem(subsys);
f3ca80fc
CH		 4563}
4564
4565/*
4566 * Initialize a NVMe controller structures. This needs to be called during
4567 * earliest initialization so that we have the initialized structured around
4568 * during probing.
4569 */
4570int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
4571 const struct nvme_ctrl_ops *ops, unsigned long quirks)
4572{
4573 int ret;
4574
e6e7f7ac 4575 WRITE_ONCE(ctrl->state, NVME_CTRL_NEW);
9f079dda 4576 ctrl->passthru_err_log_enabled = false;
8c4dfea9 4577 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
bb8d261e 4578 spin_lock_init(&ctrl->lock);
e7ad43c3 4579 mutex_init(&ctrl->scan_lock);
f3ca80fc 4580 INIT_LIST_HEAD(&ctrl->namespaces);
1cf7a12e 4581 xa_init(&ctrl->cels);
765cc031 4582 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 4583 ctrl->dev = dev;
4584 ctrl->ops = ops;
4585 ctrl->quirks = quirks;
4fea243e 4586 ctrl->numa_node = NUMA_NO_NODE;
5955be21 4587 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 4588 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 4589 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 4590 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
c1ac9a4b 4591 init_waitqueue_head(&ctrl->state_wq);
f3ca80fc 4592
230f1f9e 4593 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
8c4dfea9 4594 INIT_DELAYED_WORK(&ctrl->failfast_work, nvme_failfast_work);
230f1f9e
JS		 4595 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
4596 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
136cfcb8 4597 ctrl->ka_last_check_time = jiffies;
230f1f9e 4598
cb5b7262
JA		 4599 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
4600 PAGE_SIZE);
4601 ctrl->discard_page = alloc_page(GFP_KERNEL);
4602 if (!ctrl->discard_page) {
4603 ret = -ENOMEM;
4604 goto out;
4605 }
4606
8b850475 4607 ret = ida_alloc(&nvme_instance_ida, GFP_KERNEL);
9843f685 4608 if (ret < 0)
f3ca80fc 4609 goto out;
9843f685 4610 ctrl->instance = ret;
f3ca80fc 4611
d22524a4
CH		 4612 device_initialize(&ctrl->ctrl_device);
4613 ctrl->device = &ctrl->ctrl_device;
f68abd9c
JG		 4614 ctrl->device->devt = MKDEV(MAJOR(nvme_ctrl_base_chr_devt),
4615 ctrl->instance);
d22524a4
CH		 4616 ctrl->device->class = nvme_class;
4617 ctrl->device->parent = ctrl->dev;
86adbf0c
CH		 4618 if (ops->dev_attr_groups)
4619 ctrl->device->groups = ops->dev_attr_groups;
4620 else
4621 ctrl->device->groups = nvme_dev_attr_groups;
d22524a4
CH		 4622 ctrl->device->release = nvme_free_ctrl;
4623 dev_set_drvdata(ctrl->device, ctrl);
4624 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
4625 if (ret)
f3ca80fc 4626 goto out_release_instance;
f3ca80fc 4627
b780d741 4628 nvme_get_ctrl(ctrl);
a6a5149b
CH		 4629 cdev_init(&ctrl->cdev, &nvme_dev_fops);
4630 ctrl->cdev.owner = ops->module;
4631 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 4632 if (ret)
4633 goto out_free_name;
f3ca80fc 4634
c5552fde
AL		 4635 /*
4636 * Initialize latency tolerance controls. The sysfs files won't
4637 * be visible to userspace unless the device actually supports APST.
4638 */
4639 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
4640 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
4641 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
4642
f79d5fda 4643 nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device));
5e1f6899 4644 nvme_mpath_init_ctrl(ctrl);
193a8c7e
SG		 4645 ret = nvme_auth_init_ctrl(ctrl);
4646 if (ret)
4647 goto out_free_cdev;
f79d5fda 4648
f3ca80fc 4649 return 0;
193a8c7e 4650out_free_cdev:
3a12a0b8 4651 nvme_fault_inject_fini(&ctrl->fault_inject);
7ed5cf8e 4652 dev_pm_qos_hide_latency_tolerance(ctrl->device);
193a8c7e 4653 cdev_device_del(&ctrl->cdev, ctrl->device);
d22524a4 4654out_free_name:
b780d741 4655 nvme_put_ctrl(ctrl);
d6a2b953 4656 kfree_const(ctrl->device->kobj.name);
f3ca80fc 4657out_release_instance:
8b850475 4658 ida_free(&nvme_instance_ida, ctrl->instance);
f3ca80fc 4659out:
cb5b7262
JA		 4660 if (ctrl->discard_page)
4661 __free_page(ctrl->discard_page);
f3ca80fc
CH		 4662 return ret;
4663}
576d55d6 4664EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 4665
cd50f9b2
CH		 4666/* let I/O to all namespaces fail in preparation for surprise removal */
4667void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl)
69d9a99c
KB		 4668{
4669 struct nvme_ns *ns;
4670
765cc031 4671 down_read(&ctrl->namespaces_rwsem);
cf39a6bc 4672 list_for_each_entry(ns, &ctrl->namespaces, list)
cd50f9b2 4673 blk_mark_disk_dead(ns->disk);
765cc031 4674 up_read(&ctrl->namespaces_rwsem);
69d9a99c 4675}
cd50f9b2 4676EXPORT_SYMBOL_GPL(nvme_mark_namespaces_dead);
69d9a99c 4677
302ad8cc
KB		 4678void nvme_unfreeze(struct nvme_ctrl *ctrl)
4679{
4680 struct nvme_ns *ns;
4681
765cc031 4682 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4683 list_for_each_entry(ns, &ctrl->namespaces, list)
4684 blk_mq_unfreeze_queue(ns->queue);
765cc031 4685 up_read(&ctrl->namespaces_rwsem);
839a40d1 4686 clear_bit(NVME_CTRL_FROZEN, &ctrl->flags);
302ad8cc
KB		 4687}
4688EXPORT_SYMBOL_GPL(nvme_unfreeze);
4689
7cf0d7c0 4690int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
302ad8cc
KB		 4691{
4692 struct nvme_ns *ns;
4693
765cc031 4694 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4695 list_for_each_entry(ns, &ctrl->namespaces, list) {
4696 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
4697 if (timeout <= 0)
4698 break;
4699 }
765cc031 4700 up_read(&ctrl->namespaces_rwsem);
7cf0d7c0 4701 return timeout;
302ad8cc
KB		 4702}
4703EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
4704
4705void nvme_wait_freeze(struct nvme_ctrl *ctrl)
4706{
4707 struct nvme_ns *ns;
4708
765cc031 4709 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4710 list_for_each_entry(ns, &ctrl->namespaces, list)
4711 blk_mq_freeze_queue_wait(ns->queue);
765cc031 4712 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4713}
4714EXPORT_SYMBOL_GPL(nvme_wait_freeze);
4715
4716void nvme_start_freeze(struct nvme_ctrl *ctrl)
4717{
4718 struct nvme_ns *ns;
4719
839a40d1 4720 set_bit(NVME_CTRL_FROZEN, &ctrl->flags);
765cc031 4721 down_read(&ctrl->namespaces_rwsem);
302ad8cc 4722 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 4723 blk_freeze_queue_start(ns->queue);
765cc031 4724 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4725}
4726EXPORT_SYMBOL_GPL(nvme_start_freeze);
4727
9f27bd70 4728void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl)
363c9aac 4729{
ba0718a6
CH		 4730 if (!ctrl->tagset)
4731 return;
98d81f0d
CL		 4732 if (!test_and_set_bit(NVME_CTRL_STOPPED, &ctrl->flags))
4733 blk_mq_quiesce_tagset(ctrl->tagset);
4734 else
4735 blk_mq_wait_quiesce_done(ctrl->tagset);
363c9aac 4736}
9f27bd70 4737EXPORT_SYMBOL_GPL(nvme_quiesce_io_queues);
363c9aac 4738
9f27bd70 4739void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl)
363c9aac 4740{
ba0718a6
CH		 4741 if (!ctrl->tagset)
4742 return;
98d81f0d
CL		 4743 if (test_and_clear_bit(NVME_CTRL_STOPPED, &ctrl->flags))
4744 blk_mq_unquiesce_tagset(ctrl->tagset);
363c9aac 4745}
9f27bd70 4746EXPORT_SYMBOL_GPL(nvme_unquiesce_io_queues);
363c9aac 4747
9f27bd70 4748void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl)
a277654b 4749{
9e6a6b12
ML		 4750 if (!test_and_set_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags))
4751 blk_mq_quiesce_queue(ctrl->admin_q);
26af1cd0 4752 else
483239c7 4753 blk_mq_wait_quiesce_done(ctrl->admin_q->tag_set);
a277654b 4754}
9f27bd70 4755EXPORT_SYMBOL_GPL(nvme_quiesce_admin_queue);
a277654b 4756
9f27bd70 4757void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl)
a277654b 4758{
9e6a6b12
ML		 4759 if (test_and_clear_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags))
4760 blk_mq_unquiesce_queue(ctrl->admin_q);
a277654b 4761}
9f27bd70 4762EXPORT_SYMBOL_GPL(nvme_unquiesce_admin_queue);
a277654b 4763
04800fbf 4764void nvme_sync_io_queues(struct nvme_ctrl *ctrl)
d6135c3a
KB		 4765{
4766 struct nvme_ns *ns;
4767
4768 down_read(&ctrl->namespaces_rwsem);
4769 list_for_each_entry(ns, &ctrl->namespaces, list)
4770 blk_sync_queue(ns->queue);
4771 up_read(&ctrl->namespaces_rwsem);
04800fbf
CL		 4772}
4773EXPORT_SYMBOL_GPL(nvme_sync_io_queues);
03894b7a 4774
04800fbf
CL		 4775void nvme_sync_queues(struct nvme_ctrl *ctrl)
4776{
4777 nvme_sync_io_queues(ctrl);
03894b7a
EN		 4778 if (ctrl->admin_q)
4779 blk_sync_queue(ctrl->admin_q);
d6135c3a
KB		 4780}
4781EXPORT_SYMBOL_GPL(nvme_sync_queues);
4782
b2702aaa 4783struct nvme_ctrl *nvme_ctrl_from_file(struct file *file)
f783f444 4784{
b2702aaa
CK		 4785 if (file->f_op != &nvme_dev_fops)
4786 return NULL;
4787 return file->private_data;
f783f444 4788}
b2702aaa 4789EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, NVME_TARGET_PASSTHRU);
f783f444 4790
81101540
CH		 4791/*
4792 * Check we didn't inadvertently grow the command structure sizes:
4793 */
4794static inline void _nvme_check_size(void)
4795{
4796 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64);
4797 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
4798 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64);
4799 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
4800 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64);
4801 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
4802 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64);
4803 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64);
4804 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
4805 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64);
4806 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
4807 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
4808 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
354201c5
CH		 4809 BUILD_BUG_ON(sizeof(struct nvme_id_ns_cs_indep) !=
4810 NVME_IDENTIFY_DATA_SIZE);
240e6ee2 4811 BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE);
4020aad8 4812 BUILD_BUG_ON(sizeof(struct nvme_id_ns_nvm) != NVME_IDENTIFY_DATA_SIZE);
240e6ee2 4813 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE);
5befc7c2 4814 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_nvm) != NVME_IDENTIFY_DATA_SIZE);
81101540
CH		 4815 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
4816 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
4817 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
4818 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64);
4020aad8 4819 BUILD_BUG_ON(sizeof(struct nvme_feat_host_behavior) != 512);
81101540
CH		 4820}
4821
4822
893a74b7 4823static int __init nvme_core_init(void)
5bae7f73 4824{
b227c59b 4825 int result = -ENOMEM;
5bae7f73 4826
81101540
CH		 4827 _nvme_check_size();
4828
9a6327d2
SG		 4829 nvme_wq = alloc_workqueue("nvme-wq",
4830 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4831 if (!nvme_wq)
b227c59b
RS		 4832 goto out;
4833
4834 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
4835 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4836 if (!nvme_reset_wq)
4837 goto destroy_wq;
4838
4839 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
4840 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4841 if (!nvme_delete_wq)
4842 goto destroy_reset_wq;
9a6327d2 4843
f68abd9c
JG		 4844 result = alloc_chrdev_region(&nvme_ctrl_base_chr_devt, 0,
4845 NVME_MINORS, "nvme");
f3ca80fc 4846 if (result < 0)
b227c59b 4847 goto destroy_delete_wq;
f3ca80fc 4848
1aaba11d 4849 nvme_class = class_create("nvme");
f3ca80fc
CH		 4850 if (IS_ERR(nvme_class)) {
4851 result = PTR_ERR(nvme_class);
4852 goto unregister_chrdev;
4853 }
a42f42e5 4854 nvme_class->dev_uevent = nvme_class_uevent;
f3ca80fc 4855
1aaba11d 4856 nvme_subsys_class = class_create("nvme-subsystem");
ab9e00cc
CH		 4857 if (IS_ERR(nvme_subsys_class)) {
4858 result = PTR_ERR(nvme_subsys_class);
4859 goto destroy_class;
4860 }
2637baed
MI		 4861
4862 result = alloc_chrdev_region(&nvme_ns_chr_devt, 0, NVME_MINORS,
4863 "nvme-generic");
4864 if (result < 0)
4865 goto destroy_subsys_class;
4866
1aaba11d 4867 nvme_ns_chr_class = class_create("nvme-generic");
2637baed
MI		 4868 if (IS_ERR(nvme_ns_chr_class)) {
4869 result = PTR_ERR(nvme_ns_chr_class);
4870 goto unregister_generic_ns;
4871 }
9d77eb52
HR		 4872 result = nvme_init_auth();
4873 if (result)
706add13 4874 goto destroy_ns_chr;
5bae7f73 4875 return 0;
f3ca80fc 4876
e481fc0a
SG		 4877destroy_ns_chr:
4878 class_destroy(nvme_ns_chr_class);
2637baed
MI		 4879unregister_generic_ns:
4880 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
4881destroy_subsys_class:
4882 class_destroy(nvme_subsys_class);
ab9e00cc
CH		 4883destroy_class:
4884 class_destroy(nvme_class);
9a6327d2 4885unregister_chrdev:
f68abd9c 4886 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS		 4887destroy_delete_wq:
4888 destroy_workqueue(nvme_delete_wq);
4889destroy_reset_wq:
4890 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 4891destroy_wq:
4892 destroy_workqueue(nvme_wq);
b227c59b 4893out:
f3ca80fc 4894 return result;
5bae7f73
CH		 4895}
4896
893a74b7 4897static void __exit nvme_core_exit(void)
5bae7f73 4898{
e481fc0a 4899 nvme_exit_auth();
2637baed 4900 class_destroy(nvme_ns_chr_class);
ab9e00cc 4901 class_destroy(nvme_subsys_class);
f3ca80fc 4902 class_destroy(nvme_class);
2637baed 4903 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
f68abd9c 4904 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS		 4905 destroy_workqueue(nvme_delete_wq);
4906 destroy_workqueue(nvme_reset_wq);
9a6327d2 4907 destroy_workqueue(nvme_wq);
2637baed 4908 ida_destroy(&nvme_ns_chr_minor_ida);
f41cfd5d 4909 ida_destroy(&nvme_instance_ida);
5bae7f73 4910}
576d55d6
ML		 4911
4912MODULE_LICENSE("GPL");
4913MODULE_VERSION("1.0");
92b0b0ff 4914MODULE_DESCRIPTION("NVMe host core framework");
576d55d6
ML		 4915module_init(nvme_core_init);
4916module_exit(nvme_core_exit);
Linux 6.x block layer and io_uring tree(s)