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nvme: put ns_head ref if namespace fails allocation
[linux-2.6-block.git] / drivers / nvme / host / core.c
CommitLineData
bc50ad75 1// SPDX-License-Identifier: GPL-2.0
21d34711
CH		 2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
21d34711
CH		 5 */
6
7#include <linux/blkdev.h>
8#include <linux/blk-mq.h>
5fd4ce1b 9#include <linux/delay.h>
21d34711 10#include <linux/errno.h>
1673f1f0 11#include <linux/hdreg.h>
21d34711 12#include <linux/kernel.h>
5bae7f73
CH		 13#include <linux/module.h>
14#include <linux/list_sort.h>
21d34711
CH		 15#include <linux/slab.h>
16#include <linux/types.h>
1673f1f0
CH		 17#include <linux/pr.h>
18#include <linux/ptrace.h>
19#include <linux/nvme_ioctl.h>
20#include <linux/t10-pi.h>
c5552fde 21#include <linux/pm_qos.h>
1673f1f0 22#include <asm/unaligned.h>
21d34711 23
3d030e41
JT		 24#define CREATE_TRACE_POINTS
25#include "trace.h"
26
21d34711 27#include "nvme.h"
038bd4cb 28#include "fabrics.h"
21d34711 29
f3ca80fc
CH		 30#define NVME_MINORS (1U << MINORBITS)
31
8ae4e447
MO		 32unsigned int admin_timeout = 60;
33module_param(admin_timeout, uint, 0644);
ba0ba7d3 34MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 35EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 36
8ae4e447
MO		 37unsigned int nvme_io_timeout = 30;
38module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 39MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 40EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 41
b3b1b0b0 42static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 43module_param(shutdown_timeout, byte, 0644);
44MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
45
44e44b29
CH		 46static u8 nvme_max_retries = 5;
47module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 48MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 49
9947d6a0 50static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 51module_param(default_ps_max_latency_us, ulong, 0644);
52MODULE_PARM_DESC(default_ps_max_latency_us,
53 "max power saving latency for new devices; use PM QOS to change per device");
54
c35e30b4
AL		 55static bool force_apst;
56module_param(force_apst, bool, 0644);
57MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
58
f5d11840
JA		 59static bool streams;
60module_param(streams, bool, 0644);
61MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
62
b227c59b
RS		 63/*
64 * nvme_wq - hosts nvme related works that are not reset or delete
65 * nvme_reset_wq - hosts nvme reset works
66 * nvme_delete_wq - hosts nvme delete works
67 *
68 * nvme_wq will host works such are scan, aen handling, fw activation,
69 * keep-alive error recovery, periodic reconnects etc. nvme_reset_wq
70 * runs reset works which also flush works hosted on nvme_wq for
71 * serialization purposes. nvme_delete_wq host controller deletion
72 * works which flush reset works for serialization.
73 */
9a6327d2
SG		 74struct workqueue_struct *nvme_wq;
75EXPORT_SYMBOL_GPL(nvme_wq);
76
b227c59b
RS		 77struct workqueue_struct *nvme_reset_wq;
78EXPORT_SYMBOL_GPL(nvme_reset_wq);
79
80struct workqueue_struct *nvme_delete_wq;
81EXPORT_SYMBOL_GPL(nvme_delete_wq);
82
ab9e00cc
CH		 83static DEFINE_IDA(nvme_subsystems_ida);
84static LIST_HEAD(nvme_subsystems);
85static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 86
9843f685 87static DEFINE_IDA(nvme_instance_ida);
a6a5149b 88static dev_t nvme_chr_devt;
f3ca80fc 89static struct class *nvme_class;
ab9e00cc 90static struct class *nvme_subsys_class;
f3ca80fc 91
84fef62d 92static int nvme_revalidate_disk(struct gendisk *disk);
12d9f070 93static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB		 94static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
95 unsigned nsid);
96
97static void nvme_set_queue_dying(struct nvme_ns *ns)
98{
99 /*
100 * Revalidating a dead namespace sets capacity to 0. This will end
101 * buffered writers dirtying pages that can't be synced.
102 */
103 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
104 return;
105 revalidate_disk(ns->disk);
106 blk_set_queue_dying(ns->queue);
107 /* Forcibly unquiesce queues to avoid blocking dispatch */
108 blk_mq_unquiesce_queue(ns->queue);
109}
f3ca80fc 110
50e8d8ee
CH		 111static void nvme_queue_scan(struct nvme_ctrl *ctrl)
112{
113 /*
114 * Only new queue scan work when admin and IO queues are both alive
115 */
116 if (ctrl->state == NVME_CTRL_LIVE)
117 queue_work(nvme_wq, &ctrl->scan_work);
118}
119
d86c4d8e
CH		 120int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
121{
122 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
123 return -EBUSY;
b227c59b 124 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 125 return -EBUSY;
126 return 0;
127}
128EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
129
79c48ccf 130int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 131{
132 int ret;
133
134 ret = nvme_reset_ctrl(ctrl);
8000d1fd 135 if (!ret) {
d86c4d8e 136 flush_work(&ctrl->reset_work);
4e50d9eb
CM		 137 if (ctrl->state != NVME_CTRL_LIVE &&
138 ctrl->state != NVME_CTRL_ADMIN_ONLY)
8000d1fd
NC		 139 ret = -ENETRESET;
140 }
141
d86c4d8e
CH		 142 return ret;
143}
79c48ccf 144EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
d86c4d8e 145
a686ed75 146static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
c5017e85 147{
77d0612d
MG		 148 dev_info(ctrl->device,
149 "Removing ctrl: NQN \"%s\"\n", ctrl->opts->subsysnqn);
150
4054637c 151 flush_work(&ctrl->reset_work);
6cd53d14
CH		 152 nvme_stop_ctrl(ctrl);
153 nvme_remove_namespaces(ctrl);
c5017e85 154 ctrl->ops->delete_ctrl(ctrl);
6cd53d14
CH		 155 nvme_uninit_ctrl(ctrl);
156 nvme_put_ctrl(ctrl);
c5017e85
CH		 157}
158
a686ed75
BVA		 159static void nvme_delete_ctrl_work(struct work_struct *work)
160{
161 struct nvme_ctrl *ctrl =
162 container_of(work, struct nvme_ctrl, delete_work);
163
164 nvme_do_delete_ctrl(ctrl);
165}
166
c5017e85
CH		 167int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
168{
169 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
170 return -EBUSY;
b227c59b 171 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 172 return -EBUSY;
173 return 0;
174}
175EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
176
d84c4b02 177static int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
c5017e85
CH		 178{
179 int ret = 0;
180
181 /*
182 * Keep a reference until the work is flushed since ->delete_ctrl
183 * can free the controller.
184 */
185 nvme_get_ctrl(ctrl);
b9c77583
BVA		 186 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
187 ret = -EBUSY;
c5017e85 188 if (!ret)
b9c77583 189 nvme_do_delete_ctrl(ctrl);
c5017e85
CH		 190 nvme_put_ctrl(ctrl);
191 return ret;
192}
c5017e85 193
715ea9e0
CH		 194static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
195{
196 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
197}
198
2a842aca 199static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 200{
201 switch (nvme_req(req)->status & 0x7ff) {
202 case NVME_SC_SUCCESS:
2a842aca 203 return BLK_STS_OK;
27fa9bc5 204 case NVME_SC_CAP_EXCEEDED:
2a842aca 205 return BLK_STS_NOSPC;
e96fef2c
KB		 206 case NVME_SC_LBA_RANGE:
207 return BLK_STS_TARGET;
208 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 209 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 210 case NVME_SC_INVALID_OPCODE:
211 case NVME_SC_INVALID_FIELD:
212 case NVME_SC_INVALID_NS:
2a842aca 213 return BLK_STS_NOTSUPP;
e02ab023
JG		 214 case NVME_SC_WRITE_FAULT:
215 case NVME_SC_READ_ERROR:
216 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 217 case NVME_SC_ACCESS_DENIED:
218 case NVME_SC_READ_ONLY:
e96fef2c 219 case NVME_SC_COMPARE_FAILED:
2a842aca 220 return BLK_STS_MEDIUM;
a751da33
CH		 221 case NVME_SC_GUARD_CHECK:
222 case NVME_SC_APPTAG_CHECK:
223 case NVME_SC_REFTAG_CHECK:
224 case NVME_SC_INVALID_PI:
225 return BLK_STS_PROTECTION;
226 case NVME_SC_RESERVATION_CONFLICT:
227 return BLK_STS_NEXUS;
2a842aca
CH		 228 default:
229 return BLK_STS_IOERR;
27fa9bc5
CH		 230 }
231}
27fa9bc5 232
f6324b1b 233static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 234{
f6324b1b
CH		 235 if (blk_noretry_request(req))
236 return false;
27fa9bc5 237 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b 238 return false;
44e44b29 239 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 240 return false;
241 return true;
77f02a7a
CH		 242}
243
49cd84b6
KB		 244static void nvme_retry_req(struct request *req)
245{
246 struct nvme_ns *ns = req->q->queuedata;
247 unsigned long delay = 0;
248 u16 crd;
249
250 /* The mask and shift result must be <= 3 */
251 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
252 if (ns && crd)
253 delay = ns->ctrl->crdt[crd - 1] * 100;
254
255 nvme_req(req)->retries++;
256 blk_mq_requeue_request(req, false);
257 blk_mq_delay_kick_requeue_list(req->q, delay);
258}
259
77f02a7a
CH		 260void nvme_complete_rq(struct request *req)
261{
908e4564
KB		 262 blk_status_t status = nvme_error_status(req);
263
ca5554a6
JT		 264 trace_nvme_complete_rq(req);
265
6e3ca03e
SG		 266 if (nvme_req(req)->ctrl->kas)
267 nvme_req(req)->ctrl->comp_seen = true;
268
908e4564 269 if (unlikely(status != BLK_STS_OK && nvme_req_needs_retry(req))) {
8decf5d5
CH		 270 if ((req->cmd_flags & REQ_NVME_MPATH) &&
271 blk_path_error(status)) {
32acab31
CH		 272 nvme_failover_req(req);
273 return;
274 }
275
276 if (!blk_queue_dying(req->q)) {
49cd84b6 277 nvme_retry_req(req);
32acab31
CH		 278 return;
279 }
77f02a7a 280 }
908e4564 281 blk_mq_end_request(req, status);
77f02a7a
CH		 282}
283EXPORT_SYMBOL_GPL(nvme_complete_rq);
284
7baa8572 285bool nvme_cancel_request(struct request *req, void *data, bool reserved)
c55a2fd4 286{
c55a2fd4
ML		 287 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
288 "Cancelling I/O %d", req->tag);
289
e54b064c 290 nvme_req(req)->status = NVME_SC_ABORT_REQ;
08e0029a 291 blk_mq_complete_request(req);
7baa8572 292 return true;
c55a2fd4
ML		 293}
294EXPORT_SYMBOL_GPL(nvme_cancel_request);
295
bb8d261e
CH		 296bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
297 enum nvme_ctrl_state new_state)
298{
f6b6a28e 299 enum nvme_ctrl_state old_state;
0a72bbba 300 unsigned long flags;
bb8d261e
CH		 301 bool changed = false;
302
0a72bbba 303 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 304
305 old_state = ctrl->state;
bb8d261e 306 switch (new_state) {
2b1b7e78
JW		 307 case NVME_CTRL_ADMIN_ONLY:
308 switch (old_state) {
ad6a0a52 309 case NVME_CTRL_CONNECTING:
2b1b7e78
JW		 310 changed = true;
311 /* FALLTHRU */
312 default:
313 break;
314 }
315 break;
bb8d261e
CH		 316 case NVME_CTRL_LIVE:
317 switch (old_state) {
7d2e8008 318 case NVME_CTRL_NEW:
bb8d261e 319 case NVME_CTRL_RESETTING:
ad6a0a52 320 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 321 changed = true;
322 /* FALLTHRU */
323 default:
324 break;
325 }
326 break;
327 case NVME_CTRL_RESETTING:
328 switch (old_state) {
329 case NVME_CTRL_NEW:
def61eca 330 case NVME_CTRL_LIVE:
2b1b7e78 331 case NVME_CTRL_ADMIN_ONLY:
def61eca
CH		 332 changed = true;
333 /* FALLTHRU */
334 default:
335 break;
336 }
337 break;
ad6a0a52 338 case NVME_CTRL_CONNECTING:
def61eca 339 switch (old_state) {
b754a32c 340 case NVME_CTRL_NEW:
3cec7f9d 341 case NVME_CTRL_RESETTING:
bb8d261e
CH		 342 changed = true;
343 /* FALLTHRU */
344 default:
345 break;
346 }
347 break;
348 case NVME_CTRL_DELETING:
349 switch (old_state) {
350 case NVME_CTRL_LIVE:
2b1b7e78 351 case NVME_CTRL_ADMIN_ONLY:
bb8d261e 352 case NVME_CTRL_RESETTING:
ad6a0a52 353 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 354 changed = true;
355 /* FALLTHRU */
356 default:
357 break;
358 }
359 break;
0ff9d4e1
KB		 360 case NVME_CTRL_DEAD:
361 switch (old_state) {
362 case NVME_CTRL_DELETING:
363 changed = true;
364 /* FALLTHRU */
365 default:
366 break;
367 }
368 break;
bb8d261e
CH		 369 default:
370 break;
371 }
bb8d261e
CH		 372
373 if (changed)
374 ctrl->state = new_state;
375
0a72bbba 376 spin_unlock_irqrestore(&ctrl->lock, flags);
32acab31
CH		 377 if (changed && ctrl->state == NVME_CTRL_LIVE)
378 nvme_kick_requeue_lists(ctrl);
bb8d261e
CH		 379 return changed;
380}
381EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
382
ed754e5d
CH		 383static void nvme_free_ns_head(struct kref *ref)
384{
385 struct nvme_ns_head *head =
386 container_of(ref, struct nvme_ns_head, ref);
387
32acab31 388 nvme_mpath_remove_disk(head);
ed754e5d
CH		 389 ida_simple_remove(&head->subsys->ns_ida, head->instance);
390 list_del_init(&head->entry);
4317228a 391 cleanup_srcu_struct_quiesced(&head->srcu);
12d9f070 392 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 393 kfree(head);
394}
395
396static void nvme_put_ns_head(struct nvme_ns_head *head)
397{
398 kref_put(&head->ref, nvme_free_ns_head);
399}
400
1673f1f0
CH		 401static void nvme_free_ns(struct kref *kref)
402{
403 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
404
b0b4e09c
MB		 405 if (ns->ndev)
406 nvme_nvm_unregister(ns);
1673f1f0 407
1673f1f0 408 put_disk(ns->disk);
ed754e5d 409 nvme_put_ns_head(ns->head);
075790eb 410 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 411 kfree(ns);
412}
413
5bae7f73 414static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 415{
416 kref_put(&ns->kref, nvme_free_ns);
417}
418
bb06ec31
JS		 419static inline void nvme_clear_nvme_request(struct request *req)
420{
421 if (!(req->rq_flags & RQF_DONTPREP)) {
422 nvme_req(req)->retries = 0;
423 nvme_req(req)->flags = 0;
424 req->rq_flags |= RQF_DONTPREP;
425 }
426}
427
4160982e 428struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 429 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
21d34711 430{
aebf526b 431 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 432 struct request *req;
21d34711 433
eb71f435 434 if (qid == NVME_QID_ANY) {
aebf526b 435 req = blk_mq_alloc_request(q, op, flags);
eb71f435 436 } else {
aebf526b 437 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 438 qid ? qid - 1 : 0);
439 }
21d34711 440 if (IS_ERR(req))
4160982e 441 return req;
21d34711 442
21d34711 443 req->cmd_flags |= REQ_FAILFAST_DRIVER;
bb06ec31 444 nvme_clear_nvme_request(req);
d49187e9 445 nvme_req(req)->cmd = cmd;
21d34711 446
4160982e
CH		 447 return req;
448}
576d55d6 449EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 450
f5d11840
JA		 451static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
452{
453 struct nvme_command c;
454
455 memset(&c, 0, sizeof(c));
456
457 c.directive.opcode = nvme_admin_directive_send;
62346eae 458 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 459 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
460 c.directive.dtype = NVME_DIR_IDENTIFY;
461 c.directive.tdtype = NVME_DIR_STREAMS;
462 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
463
464 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
465}
466
467static int nvme_disable_streams(struct nvme_ctrl *ctrl)
468{
469 return nvme_toggle_streams(ctrl, false);
470}
471
472static int nvme_enable_streams(struct nvme_ctrl *ctrl)
473{
474 return nvme_toggle_streams(ctrl, true);
475}
476
477static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
478 struct streams_directive_params *s, u32 nsid)
479{
480 struct nvme_command c;
481
482 memset(&c, 0, sizeof(c));
483 memset(s, 0, sizeof(*s));
484
485 c.directive.opcode = nvme_admin_directive_recv;
486 c.directive.nsid = cpu_to_le32(nsid);
a082b426 487 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 488 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
489 c.directive.dtype = NVME_DIR_STREAMS;
490
491 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
492}
493
494static int nvme_configure_directives(struct nvme_ctrl *ctrl)
495{
496 struct streams_directive_params s;
497 int ret;
498
499 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
500 return 0;
501 if (!streams)
502 return 0;
503
504 ret = nvme_enable_streams(ctrl);
505 if (ret)
506 return ret;
507
62346eae 508 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 509 if (ret)
510 return ret;
511
512 ctrl->nssa = le16_to_cpu(s.nssa);
513 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
514 dev_info(ctrl->device, "too few streams (%u) available\n",
515 ctrl->nssa);
516 nvme_disable_streams(ctrl);
517 return 0;
518 }
519
520 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
521 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
522 return 0;
523}
524
525/*
526 * Check if 'req' has a write hint associated with it. If it does, assign
527 * a valid namespace stream to the write.
528 */
529static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
530 struct request *req, u16 *control,
531 u32 *dsmgmt)
532{
533 enum rw_hint streamid = req->write_hint;
534
535 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
536 streamid = 0;
537 else {
538 streamid--;
539 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
540 return;
541
542 *control |= NVME_RW_DTYPE_STREAMS;
543 *dsmgmt |= streamid << 16;
544 }
545
546 if (streamid < ARRAY_SIZE(req->q->write_hints))
547 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
548}
549
8093f7ca
ML		 550static inline void nvme_setup_flush(struct nvme_ns *ns,
551 struct nvme_command *cmnd)
552{
8093f7ca 553 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 554 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 555}
556
fc17b653 557static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 558 struct nvme_command *cmnd)
559{
b35ba01e 560 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 561 struct nvme_dsm_range *range;
b35ba01e 562 struct bio *bio;
8093f7ca 563
cb5b7262
JA		 564 range = kmalloc_array(segments, sizeof(*range),
565 GFP_ATOMIC | __GFP_NOWARN);
566 if (!range) {
567 /*
568 * If we fail allocation our range, fallback to the controller
569 * discard page. If that's also busy, it's safe to return
570 * busy, as we know we can make progress once that's freed.
571 */
572 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
573 return BLK_STS_RESOURCE;
574
575 range = page_address(ns->ctrl->discard_page);
576 }
8093f7ca 577
b35ba01e
CH		 578 __rq_for_each_bio(bio, req) {
579 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
580 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
581
8cb6af7b
KB		 582 if (n < segments) {
583 range[n].cattr = cpu_to_le32(0);
584 range[n].nlb = cpu_to_le32(nlb);
585 range[n].slba = cpu_to_le64(slba);
586 }
b35ba01e
CH		 587 n++;
588 }
589
590 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA		 591 if (virt_to_page(range) == ns->ctrl->discard_page)
592 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
593 else
594 kfree(range);
fc17b653 595 return BLK_STS_IOERR;
b35ba01e 596 }
8093f7ca 597
8093f7ca 598 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 599 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 600 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 601 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
602
f9d03f96
CH		 603 req->special_vec.bv_page = virt_to_page(range);
604 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 605 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 606 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 607
fc17b653 608 return BLK_STS_OK;
8093f7ca 609}
8093f7ca 610
6e02318e
CK		 611static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
612 struct request *req, struct nvme_command *cmnd)
613{
614 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
615 return nvme_setup_discard(ns, req, cmnd);
616
617 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
618 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
619 cmnd->write_zeroes.slba =
620 cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
621 cmnd->write_zeroes.length =
622 cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
623 cmnd->write_zeroes.control = 0;
624 return BLK_STS_OK;
625}
626
ebe6d874
CH		 627static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
628 struct request *req, struct nvme_command *cmnd)
8093f7ca 629{
f5d11840 630 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 631 u16 control = 0;
632 u32 dsmgmt = 0;
633
634 if (req->cmd_flags & REQ_FUA)
635 control |= NVME_RW_FUA;
636 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
637 control |= NVME_RW_LR;
638
639 if (req->cmd_flags & REQ_RAHEAD)
640 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
641
8093f7ca 642 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
ed754e5d 643 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 644 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
645 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
646
f5d11840
JA		 647 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
648 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
649
8093f7ca 650 if (ns->ms) {
715ea9e0
CH		 651 /*
652 * If formated with metadata, the block layer always provides a
653 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
654 * we enable the PRACT bit for protection information or set the
655 * namespace capacity to zero to prevent any I/O.
656 */
657 if (!blk_integrity_rq(req)) {
658 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
659 return BLK_STS_NOTSUPP;
660 control |= NVME_RW_PRINFO_PRACT;
f7f1fc36
MG		 661 } else if (req_op(req) == REQ_OP_WRITE) {
662 t10_pi_prepare(req, ns->pi_type);
715ea9e0
CH		 663 }
664
8093f7ca
ML		 665 switch (ns->pi_type) {
666 case NVME_NS_DPS_PI_TYPE3:
667 control |= NVME_RW_PRINFO_PRCHK_GUARD;
668 break;
669 case NVME_NS_DPS_PI_TYPE1:
670 case NVME_NS_DPS_PI_TYPE2:
671 control |= NVME_RW_PRINFO_PRCHK_GUARD |
672 NVME_RW_PRINFO_PRCHK_REF;
ddd0bc75 673 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
8093f7ca
ML		 674 break;
675 }
8093f7ca
ML		 676 }
677
678 cmnd->rw.control = cpu_to_le16(control);
679 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 680 return 0;
8093f7ca
ML		 681}
682
f7f1fc36
MG		 683void nvme_cleanup_cmd(struct request *req)
684{
685 if (blk_integrity_rq(req) && req_op(req) == REQ_OP_READ &&
686 nvme_req(req)->status == 0) {
687 struct nvme_ns *ns = req->rq_disk->private_data;
688
689 t10_pi_complete(req, ns->pi_type,
690 blk_rq_bytes(req) >> ns->lba_shift);
691 }
692 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
cb5b7262
JA		 693 struct nvme_ns *ns = req->rq_disk->private_data;
694 struct page *page = req->special_vec.bv_page;
695
696 if (page == ns->ctrl->discard_page)
697 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
698 else
699 kfree(page_address(page) + req->special_vec.bv_offset);
f7f1fc36
MG		 700 }
701}
702EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
703
fc17b653 704blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 705 struct nvme_command *cmd)
706{
fc17b653 707 blk_status_t ret = BLK_STS_OK;
8093f7ca 708
bb06ec31 709 nvme_clear_nvme_request(req);
987f699a 710
11902035 711 memset(cmd, 0, sizeof(*cmd));
aebf526b
CH		 712 switch (req_op(req)) {
713 case REQ_OP_DRV_IN:
714 case REQ_OP_DRV_OUT:
d49187e9 715 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 716 break;
717 case REQ_OP_FLUSH:
8093f7ca 718 nvme_setup_flush(ns, cmd);
aebf526b 719 break;
e850fd16 720 case REQ_OP_WRITE_ZEROES:
6e02318e
CK		 721 ret = nvme_setup_write_zeroes(ns, req, cmd);
722 break;
aebf526b 723 case REQ_OP_DISCARD:
8093f7ca 724 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 725 break;
726 case REQ_OP_READ:
727 case REQ_OP_WRITE:
ebe6d874 728 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 729 break;
730 default:
731 WARN_ON_ONCE(1);
fc17b653 732 return BLK_STS_IOERR;
aebf526b 733 }
8093f7ca 734
721b3917 735 cmd->common.command_id = req->tag;
5d87eb94 736 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 737 return ret;
738}
739EXPORT_SYMBOL_GPL(nvme_setup_cmd);
740
6287b51c
SG		 741static void nvme_end_sync_rq(struct request *rq, blk_status_t error)
742{
743 struct completion *waiting = rq->end_io_data;
744
745 rq->end_io_data = NULL;
746 complete(waiting);
747}
748
749static void nvme_execute_rq_polled(struct request_queue *q,
750 struct gendisk *bd_disk, struct request *rq, int at_head)
751{
752 DECLARE_COMPLETION_ONSTACK(wait);
753
754 WARN_ON_ONCE(!test_bit(QUEUE_FLAG_POLL, &q->queue_flags));
755
756 rq->cmd_flags |= REQ_HIPRI;
757 rq->end_io_data = &wait;
758 blk_execute_rq_nowait(q, bd_disk, rq, at_head, nvme_end_sync_rq);
759
760 while (!completion_done(&wait)) {
761 blk_poll(q, request_to_qc_t(rq->mq_hctx, rq), true);
762 cond_resched();
763 }
764}
765
4160982e
CH		 766/*
767 * Returns 0 on success. If the result is negative, it's a Linux error code;
768 * if the result is positive, it's an NVM Express status code
769 */
770int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 771 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef 772 unsigned timeout, int qid, int at_head,
6287b51c 773 blk_mq_req_flags_t flags, bool poll)
4160982e
CH		 774{
775 struct request *req;
776 int ret;
777
eb71f435 778 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 779 if (IS_ERR(req))
780 return PTR_ERR(req);
781
782 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
783
21d34711
CH		 784 if (buffer && bufflen) {
785 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
786 if (ret)
787 goto out;
4160982e
CH		 788 }
789
6287b51c
SG		 790 if (poll)
791 nvme_execute_rq_polled(req->q, NULL, req, at_head);
792 else
793 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 794 if (result)
795 *result = nvme_req(req)->result;
27fa9bc5
CH		 796 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
797 ret = -EINTR;
798 else
799 ret = nvme_req(req)->status;
4160982e
CH		 800 out:
801 blk_mq_free_request(req);
802 return ret;
803}
eb71f435 804EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 805
806int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
807 void *buffer, unsigned bufflen)
808{
eb71f435 809 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
6287b51c 810 NVME_QID_ANY, 0, 0, false);
4160982e 811}
576d55d6 812EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 813
1cad6562
CH		 814static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
815 unsigned len, u32 seed, bool write)
816{
817 struct bio_integrity_payload *bip;
818 int ret = -ENOMEM;
819 void *buf;
820
821 buf = kmalloc(len, GFP_KERNEL);
822 if (!buf)
823 goto out;
824
825 ret = -EFAULT;
826 if (write && copy_from_user(buf, ubuf, len))
827 goto out_free_meta;
828
829 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
830 if (IS_ERR(bip)) {
831 ret = PTR_ERR(bip);
832 goto out_free_meta;
833 }
834
835 bip->bip_iter.bi_size = len;
836 bip->bip_iter.bi_sector = seed;
837 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
838 offset_in_page(buf));
839 if (ret == len)
840 return buf;
841 ret = -ENOMEM;
842out_free_meta:
843 kfree(buf);
844out:
845 return ERR_PTR(ret);
846}
847
63263d60 848static int nvme_submit_user_cmd(struct request_queue *q,
485783ca
KB		 849 struct nvme_command *cmd, void __user *ubuffer,
850 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
851 u32 meta_seed, u32 *result, unsigned timeout)
4160982e 852{
7a5abb4b 853 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 854 struct nvme_ns *ns = q->queuedata;
855 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 856 struct request *req;
0b7f1f26
KB		 857 struct bio *bio = NULL;
858 void *meta = NULL;
4160982e
CH		 859 int ret;
860
eb71f435 861 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 862 if (IS_ERR(req))
863 return PTR_ERR(req);
864
865 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
bb06ec31 866 nvme_req(req)->flags |= NVME_REQ_USERCMD;
4160982e
CH		 867
868 if (ubuffer && bufflen) {
21d34711
CH		 869 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
870 GFP_KERNEL);
871 if (ret)
872 goto out;
873 bio = req->bio;
74d46992 874 bio->bi_disk = disk;
1cad6562
CH		 875 if (disk && meta_buffer && meta_len) {
876 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
877 meta_seed, write);
878 if (IS_ERR(meta)) {
879 ret = PTR_ERR(meta);
0b7f1f26
KB		 880 goto out_unmap;
881 }
f31a2110 882 req->cmd_flags |= REQ_INTEGRITY;
0b7f1f26
KB		 883 }
884 }
1cad6562 885
0b7f1f26 886 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 887 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
888 ret = -EINTR;
889 else
890 ret = nvme_req(req)->status;
21d34711 891 if (result)
d49187e9 892 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 893 if (meta && !ret && !write) {
894 if (copy_to_user(meta_buffer, meta, meta_len))
895 ret = -EFAULT;
896 }
0b7f1f26
KB		 897 kfree(meta);
898 out_unmap:
74d46992 899 if (bio)
0b7f1f26 900 blk_rq_unmap_user(bio);
21d34711
CH		 901 out:
902 blk_mq_free_request(req);
903 return ret;
904}
905
2a842aca 906static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 907{
908 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS		 909 unsigned long flags;
910 bool startka = false;
038bd4cb
SG		 911
912 blk_mq_free_request(rq);
913
2a842aca 914 if (status) {
038bd4cb 915 dev_err(ctrl->device,
2a842aca
CH		 916 "failed nvme_keep_alive_end_io error=%d\n",
917 status);
038bd4cb
SG		 918 return;
919 }
920
6e3ca03e 921 ctrl->comp_seen = false;
86880d64
JS		 922 spin_lock_irqsave(&ctrl->lock, flags);
923 if (ctrl->state == NVME_CTRL_LIVE ||
924 ctrl->state == NVME_CTRL_CONNECTING)
925 startka = true;
926 spin_unlock_irqrestore(&ctrl->lock, flags);
927 if (startka)
928 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
038bd4cb
SG		 929}
930
931static int nvme_keep_alive(struct nvme_ctrl *ctrl)
932{
038bd4cb
SG		 933 struct request *rq;
934
0a34e466 935 rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd, BLK_MQ_REQ_RESERVED,
038bd4cb
SG		 936 NVME_QID_ANY);
937 if (IS_ERR(rq))
938 return PTR_ERR(rq);
939
940 rq->timeout = ctrl->kato * HZ;
941 rq->end_io_data = ctrl;
942
943 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
944
945 return 0;
946}
947
948static void nvme_keep_alive_work(struct work_struct *work)
949{
950 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
951 struct nvme_ctrl, ka_work);
6e3ca03e
SG		 952 bool comp_seen = ctrl->comp_seen;
953
954 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
955 dev_dbg(ctrl->device,
956 "reschedule traffic based keep-alive timer\n");
957 ctrl->comp_seen = false;
958 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
959 return;
960 }
038bd4cb
SG		 961
962 if (nvme_keep_alive(ctrl)) {
963 /* allocation failure, reset the controller */
964 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 965 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 966 return;
967 }
968}
969
00b683db 970static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 971{
972 if (unlikely(ctrl->kato == 0))
973 return;
974
038bd4cb
SG		 975 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
976}
038bd4cb
SG		 977
978void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
979{
980 if (unlikely(ctrl->kato == 0))
981 return;
982
983 cancel_delayed_work_sync(&ctrl->ka_work);
984}
985EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
986
3f7f25a9 987static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 988{
989 struct nvme_command c = { };
990 int error;
991
992 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
993 c.identify.opcode = nvme_admin_identify;
986994a2 994 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 995
996 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
997 if (!*id)
998 return -ENOMEM;
999
1000 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1001 sizeof(struct nvme_id_ctrl));
1002 if (error)
1003 kfree(*id);
1004 return error;
1005}
1006
cdbff4f2 1007static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 1008 struct nvme_ns_ids *ids)
3b22ba26
JT		 1009{
1010 struct nvme_command c = { };
1011 int status;
1012 void *data;
1013 int pos;
1014 int len;
1015
1016 c.identify.opcode = nvme_admin_identify;
1017 c.identify.nsid = cpu_to_le32(nsid);
1018 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1019
1020 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1021 if (!data)
1022 return -ENOMEM;
1023
cdbff4f2 1024 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 1025 NVME_IDENTIFY_DATA_SIZE);
1026 if (status)
1027 goto free_data;
1028
1029 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1030 struct nvme_ns_id_desc *cur = data + pos;
1031
1032 if (cur->nidl == 0)
1033 break;
1034
1035 switch (cur->nidt) {
1036 case NVME_NIDT_EUI64:
1037 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 1038 dev_warn(ctrl->device,
3b22ba26
JT		 1039 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
1040 cur->nidl);
1041 goto free_data;
1042 }
1043 len = NVME_NIDT_EUI64_LEN;
002fab04 1044 memcpy(ids->eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 1045 break;
1046 case NVME_NIDT_NGUID:
1047 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 1048 dev_warn(ctrl->device,
3b22ba26
JT		 1049 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
1050 cur->nidl);
1051 goto free_data;
1052 }
1053 len = NVME_NIDT_NGUID_LEN;
002fab04 1054 memcpy(ids->nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 1055 break;
1056 case NVME_NIDT_UUID:
1057 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 1058 dev_warn(ctrl->device,
3b22ba26
JT		 1059 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
1060 cur->nidl);
1061 goto free_data;
1062 }
1063 len = NVME_NIDT_UUID_LEN;
002fab04 1064 uuid_copy(&ids->uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 1065 break;
1066 default:
53b3a661 1067 /* Skip unknown types */
3b22ba26
JT		 1068 len = cur->nidl;
1069 break;
1070 }
1071
1072 len += sizeof(*cur);
1073 }
1074free_data:
1075 kfree(data);
1076 return status;
1077}
1078
540c801c
KB		 1079static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
1080{
1081 struct nvme_command c = { };
1082
1083 c.identify.opcode = nvme_admin_identify;
986994a2 1084 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c 1085 c.identify.nsid = cpu_to_le32(nsid);
42595eb7
MI		 1086 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list,
1087 NVME_IDENTIFY_DATA_SIZE);
540c801c
KB		 1088}
1089
cdbff4f2
CH		 1090static struct nvme_id_ns *nvme_identify_ns(struct nvme_ctrl *ctrl,
1091 unsigned nsid)
21d34711 1092{
cdbff4f2 1093 struct nvme_id_ns *id;
21d34711
CH		 1094 struct nvme_command c = { };
1095 int error;
1096
1097 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 1098 c.identify.opcode = nvme_admin_identify;
1099 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1100 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1101
cdbff4f2
CH		 1102 id = kmalloc(sizeof(*id), GFP_KERNEL);
1103 if (!id)
1104 return NULL;
21d34711 1105
cdbff4f2
CH		 1106 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
1107 if (error) {
1108 dev_warn(ctrl->device, "Identify namespace failed\n");
1109 kfree(id);
1110 return NULL;
1111 }
1112
1113 return id;
21d34711
CH		 1114}
1115
3f7f25a9 1116static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 1117 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 1118{
1119 struct nvme_command c;
d49187e9 1120 union nvme_result res;
1cb3cce5 1121 int ret;
21d34711
CH		 1122
1123 memset(&c, 0, sizeof(c));
1124 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 1125 c.features.fid = cpu_to_le32(fid);
1126 c.features.dword11 = cpu_to_le32(dword11);
1127
d49187e9 1128 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
6287b51c 1129 buffer, buflen, 0, NVME_QID_ANY, 0, 0, false);
9b47f77a 1130 if (ret >= 0 && result)
d49187e9 1131 *result = le32_to_cpu(res.u32);
1cb3cce5 1132 return ret;
21d34711
CH		 1133}
1134
9a0be7ab
CH		 1135int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1136{
1137 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1138 u32 result;
1139 int status, nr_io_queues;
1140
1a6fe74d 1141 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1142 &result);
f5fa90dc 1143 if (status < 0)
9a0be7ab
CH		 1144 return status;
1145
f5fa90dc
CH		 1146 /*
1147 * Degraded controllers might return an error when setting the queue
1148 * count. We still want to be able to bring them online and offer
1149 * access to the admin queue, as that might be only way to fix them up.
1150 */
1151 if (status > 0) {
f0425db0 1152 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1153 *count = 0;
1154 } else {
1155 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1156 *count = min(*count, nr_io_queues);
1157 }
1158
9a0be7ab
CH		 1159 return 0;
1160}
576d55d6 1161EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1162
c0561f82 1163#define NVME_AEN_SUPPORTED \
0d0b660f 1164 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | NVME_AEN_CFG_ANA_CHANGE)
c0561f82
HR		 1165
1166static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1167{
fa441b71 1168 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR		 1169 int status;
1170
fa441b71
WZ		 1171 if (!supported_aens)
1172 return;
1173
1174 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1175 NULL, 0, &result);
c0561f82
HR		 1176 if (status)
1177 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1178 supported_aens);
c0561f82
HR		 1179}
1180
1673f1f0
CH		 1181static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1182{
1183 struct nvme_user_io io;
1184 struct nvme_command c;
1185 unsigned length, meta_len;
1186 void __user *metadata;
1187
1188 if (copy_from_user(&io, uio, sizeof(io)))
1189 return -EFAULT;
63088ec7
KB		 1190 if (io.flags)
1191 return -EINVAL;
1673f1f0
CH		 1192
1193 switch (io.opcode) {
1194 case nvme_cmd_write:
1195 case nvme_cmd_read:
1196 case nvme_cmd_compare:
1197 break;
1198 default:
1199 return -EINVAL;
1200 }
1201
1202 length = (io.nblocks + 1) << ns->lba_shift;
1203 meta_len = (io.nblocks + 1) * ns->ms;
1204 metadata = (void __user *)(uintptr_t)io.metadata;
1205
1206 if (ns->ext) {
1207 length += meta_len;
1208 meta_len = 0;
1209 } else if (meta_len) {
1210 if ((io.metadata & 3) || !io.metadata)
1211 return -EINVAL;
1212 }
1213
1214 memset(&c, 0, sizeof(c));
1215 c.rw.opcode = io.opcode;
1216 c.rw.flags = io.flags;
ed754e5d 1217 c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1218 c.rw.slba = cpu_to_le64(io.slba);
1219 c.rw.length = cpu_to_le16(io.nblocks);
1220 c.rw.control = cpu_to_le16(io.control);
1221 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1222 c.rw.reftag = cpu_to_le32(io.reftag);
1223 c.rw.apptag = cpu_to_le16(io.apptag);
1224 c.rw.appmask = cpu_to_le16(io.appmask);
1225
63263d60 1226 return nvme_submit_user_cmd(ns->queue, &c,
1673f1f0 1227 (void __user *)(uintptr_t)io.addr, length,
202359c0 1228 metadata, meta_len, lower_32_bits(io.slba), NULL, 0);
1673f1f0
CH		 1229}
1230
84fef62d
KB		 1231static u32 nvme_known_admin_effects(u8 opcode)
1232{
1233 switch (opcode) {
1234 case nvme_admin_format_nvm:
1235 return NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
1236 NVME_CMD_EFFECTS_CSE_MASK;
1237 case nvme_admin_sanitize_nvm:
1238 return NVME_CMD_EFFECTS_CSE_MASK;
1239 default:
1240 break;
1241 }
1242 return 0;
1243}
1244
1245static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1246 u8 opcode)
1247{
1248 u32 effects = 0;
1249
1250 if (ns) {
1251 if (ctrl->effects)
1252 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
415df90b 1253 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
84fef62d
KB		 1254 dev_warn(ctrl->device,
1255 "IO command:%02x has unhandled effects:%08x\n",
1256 opcode, effects);
1257 return 0;
1258 }
1259
1260 if (ctrl->effects)
62843c2e 1261 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
84fef62d
KB		 1262 else
1263 effects = nvme_known_admin_effects(opcode);
1264
1265 /*
1266 * For simplicity, IO to all namespaces is quiesced even if the command
1267 * effects say only one namespace is affected.
1268 */
1269 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
e7ad43c3 1270 mutex_lock(&ctrl->scan_lock);
84fef62d
KB		 1271 nvme_start_freeze(ctrl);
1272 nvme_wait_freeze(ctrl);
1273 }
1274 return effects;
1275}
1276
1277static void nvme_update_formats(struct nvme_ctrl *ctrl)
1278{
cf39a6bc 1279 struct nvme_ns *ns;
84fef62d 1280
cf39a6bc
SB		 1281 down_read(&ctrl->namespaces_rwsem);
1282 list_for_each_entry(ns, &ctrl->namespaces, list)
1283 if (ns->disk && nvme_revalidate_disk(ns->disk))
1284 nvme_set_queue_dying(ns);
1285 up_read(&ctrl->namespaces_rwsem);
3fd176b7 1286
cf39a6bc 1287 nvme_remove_invalid_namespaces(ctrl, NVME_NSID_ALL);
84fef62d
KB		 1288}
1289
1290static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1291{
1292 /*
1293 * Revalidate LBA changes prior to unfreezing. This is necessary to
1294 * prevent memory corruption if a logical block size was changed by
1295 * this command.
1296 */
1297 if (effects & NVME_CMD_EFFECTS_LBCC)
1298 nvme_update_formats(ctrl);
e7ad43c3 1299 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
84fef62d 1300 nvme_unfreeze(ctrl);
e7ad43c3
KB		 1301 mutex_unlock(&ctrl->scan_lock);
1302 }
84fef62d
KB		 1303 if (effects & NVME_CMD_EFFECTS_CCC)
1304 nvme_init_identify(ctrl);
1305 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC))
1306 nvme_queue_scan(ctrl);
1307}
1308
f3ca80fc 1309static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 1310 struct nvme_passthru_cmd __user *ucmd)
1311{
1312 struct nvme_passthru_cmd cmd;
1313 struct nvme_command c;
1314 unsigned timeout = 0;
84fef62d 1315 u32 effects;
1673f1f0
CH		 1316 int status;
1317
1318 if (!capable(CAP_SYS_ADMIN))
1319 return -EACCES;
1320 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1321 return -EFAULT;
63088ec7
KB		 1322 if (cmd.flags)
1323 return -EINVAL;
1673f1f0
CH		 1324
1325 memset(&c, 0, sizeof(c));
1326 c.common.opcode = cmd.opcode;
1327 c.common.flags = cmd.flags;
1328 c.common.nsid = cpu_to_le32(cmd.nsid);
1329 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1330 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
b7c8f366
CK		 1331 c.common.cdw10 = cpu_to_le32(cmd.cdw10);
1332 c.common.cdw11 = cpu_to_le32(cmd.cdw11);
1333 c.common.cdw12 = cpu_to_le32(cmd.cdw12);
1334 c.common.cdw13 = cpu_to_le32(cmd.cdw13);
1335 c.common.cdw14 = cpu_to_le32(cmd.cdw14);
1336 c.common.cdw15 = cpu_to_le32(cmd.cdw15);
1673f1f0
CH		 1337
1338 if (cmd.timeout_ms)
1339 timeout = msecs_to_jiffies(cmd.timeout_ms);
1340
84fef62d 1341 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1673f1f0 1342 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1343 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
9b382768 1344 (void __user *)(uintptr_t)cmd.metadata, cmd.metadata_len,
63263d60 1345 0, &cmd.result, timeout);
84fef62d
KB		 1346 nvme_passthru_end(ctrl, effects);
1347
1673f1f0
CH		 1348 if (status >= 0) {
1349 if (put_user(cmd.result, &ucmd->result))
1350 return -EFAULT;
1351 }
1352
1353 return status;
1354}
1355
32acab31
CH		 1356/*
1357 * Issue ioctl requests on the first available path. Note that unlike normal
1358 * block layer requests we will not retry failed request on another controller.
1359 */
1360static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1361 struct nvme_ns_head **head, int *srcu_idx)
1673f1f0 1362{
32acab31
CH		 1363#ifdef CONFIG_NVME_MULTIPATH
1364 if (disk->fops == &nvme_ns_head_ops) {
1365 *head = disk->private_data;
1366 *srcu_idx = srcu_read_lock(&(*head)->srcu);
1367 return nvme_find_path(*head);
1368 }
1369#endif
1370 *head = NULL;
1371 *srcu_idx = -1;
1372 return disk->private_data;
1373}
1673f1f0 1374
32acab31
CH		 1375static void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1376{
1377 if (head)
1378 srcu_read_unlock(&head->srcu, idx);
1379}
1673f1f0 1380
32acab31
CH		 1381static int nvme_ns_ioctl(struct nvme_ns *ns, unsigned cmd, unsigned long arg)
1382{
1673f1f0
CH		 1383 switch (cmd) {
1384 case NVME_IOCTL_ID:
1385 force_successful_syscall_return();
ed754e5d 1386 return ns->head->ns_id;
1673f1f0
CH		 1387 case NVME_IOCTL_ADMIN_CMD:
1388 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1389 case NVME_IOCTL_IO_CMD:
1390 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1391 case NVME_IOCTL_SUBMIT_IO:
1392 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1393 default:
84d4add7
MB		 1394#ifdef CONFIG_NVM
1395 if (ns->ndev)
1396 return nvme_nvm_ioctl(ns, cmd, arg);
1397#endif
a98e58e5 1398 if (is_sed_ioctl(cmd))
4f1244c8 1399 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1400 (void __user *) arg);
1673f1f0
CH		 1401 return -ENOTTY;
1402 }
1403}
1404
32acab31
CH		 1405static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1406 unsigned int cmd, unsigned long arg)
1673f1f0 1407{
32acab31
CH		 1408 struct nvme_ns_head *head = NULL;
1409 struct nvme_ns *ns;
1410 int srcu_idx, ret;
1411
1412 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1413 if (unlikely(!ns))
1414 ret = -EWOULDBLOCK;
1415 else
1416 ret = nvme_ns_ioctl(ns, cmd, arg);
1417 nvme_put_ns_from_disk(head, srcu_idx);
1418 return ret;
1673f1f0 1419}
1673f1f0
CH		 1420
1421static int nvme_open(struct block_device *bdev, fmode_t mode)
1422{
c6424a90
CH		 1423 struct nvme_ns *ns = bdev->bd_disk->private_data;
1424
32acab31
CH		 1425#ifdef CONFIG_NVME_MULTIPATH
1426 /* should never be called due to GENHD_FL_HIDDEN */
1427 if (WARN_ON_ONCE(ns->head->disk))
85088c4a 1428 goto fail;
32acab31 1429#endif
c6424a90 1430 if (!kref_get_unless_zero(&ns->kref))
85088c4a
NC		 1431 goto fail;
1432 if (!try_module_get(ns->ctrl->ops->module))
1433 goto fail_put_ns;
1434
c6424a90 1435 return 0;
85088c4a
NC		 1436
1437fail_put_ns:
1438 nvme_put_ns(ns);
1439fail:
1440 return -ENXIO;
1673f1f0
CH		 1441}
1442
1443static void nvme_release(struct gendisk *disk, fmode_t mode)
1444{
85088c4a
NC		 1445 struct nvme_ns *ns = disk->private_data;
1446
1447 module_put(ns->ctrl->ops->module);
1448 nvme_put_ns(ns);
1673f1f0
CH		 1449}
1450
1451static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1452{
1453 /* some standard values */
1454 geo->heads = 1 << 6;
1455 geo->sectors = 1 << 5;
1456 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1457 return 0;
1458}
1459
1460#ifdef CONFIG_BLK_DEV_INTEGRITY
39b7baa4 1461static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1462{
1463 struct blk_integrity integrity;
1464
fa9a89fc 1465 memset(&integrity, 0, sizeof(integrity));
39b7baa4 1466 switch (pi_type) {
1673f1f0
CH		 1467 case NVME_NS_DPS_PI_TYPE3:
1468 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1469 integrity.tag_size = sizeof(u16) + sizeof(u32);
1470 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1471 break;
1472 case NVME_NS_DPS_PI_TYPE1:
1473 case NVME_NS_DPS_PI_TYPE2:
1474 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1475 integrity.tag_size = sizeof(u16);
1476 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1477 break;
1478 default:
1479 integrity.profile = NULL;
1480 break;
1481 }
39b7baa4
CH		 1482 integrity.tuple_size = ms;
1483 blk_integrity_register(disk, &integrity);
1484 blk_queue_max_integrity_segments(disk->queue, 1);
1673f1f0
CH		 1485}
1486#else
39b7baa4 1487static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1488{
1489}
1490#endif /* CONFIG_BLK_DEV_INTEGRITY */
1491
6b8190d6
SB		 1492static void nvme_set_chunk_size(struct nvme_ns *ns)
1493{
1494 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1495 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1496}
1497
3831761e 1498static void nvme_config_discard(struct nvme_ns *ns)
1673f1f0 1499{
3831761e
JA		 1500 struct nvme_ctrl *ctrl = ns->ctrl;
1501 struct request_queue *queue = ns->queue;
30e5e929
CH		 1502 u32 size = queue_logical_block_size(queue);
1503
3831761e
JA		 1504 if (!(ctrl->oncs & NVME_CTRL_ONCS_DSM)) {
1505 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, queue);
1506 return;
1507 }
1508
1509 if (ctrl->nr_streams && ns->sws && ns->sgs)
1510 size *= ns->sws * ns->sgs;
08095e70 1511
b35ba01e
CH		 1512 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1513 NVME_DSM_MAX_RANGES);
1514
b224f613 1515 queue->limits.discard_alignment = 0;
30e5e929 1516 queue->limits.discard_granularity = size;
f5d11840 1517
3831761e
JA		 1518 /* If discard is already enabled, don't reset queue limits */
1519 if (blk_queue_flag_test_and_set(QUEUE_FLAG_DISCARD, queue))
1520 return;
1521
30e5e929
CH		 1522 blk_queue_max_discard_sectors(queue, UINT_MAX);
1523 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
e850fd16
CH		 1524
1525 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1526 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1527}
1528
6e02318e
CK		 1529static inline void nvme_config_write_zeroes(struct nvme_ns *ns)
1530{
1531 u32 max_sectors;
1532 unsigned short bs = 1 << ns->lba_shift;
1533
1534 if (!(ns->ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES))
1535 return;
1536 /*
1537 * Even though NVMe spec explicitly states that MDTS is not
1538 * applicable to the write-zeroes:- "The restriction does not apply to
1539 * commands that do not transfer data between the host and the
1540 * controller (e.g., Write Uncorrectable ro Write Zeroes command).".
1541 * In order to be more cautious use controller's max_hw_sectors value
1542 * to configure the maximum sectors for the write-zeroes which is
1543 * configured based on the controller's MDTS field in the
1544 * nvme_init_identify() if available.
1545 */
1546 if (ns->ctrl->max_hw_sectors == UINT_MAX)
1547 max_sectors = ((u32)(USHRT_MAX + 1) * bs) >> 9;
1548 else
1549 max_sectors = ((u32)(ns->ctrl->max_hw_sectors + 1) * bs) >> 9;
1550
1551 blk_queue_max_write_zeroes_sectors(ns->queue, max_sectors);
1552}
1553
1554static inline void nvme_ns_config_oncs(struct nvme_ns *ns)
1555{
1556 nvme_config_discard(ns);
1557 nvme_config_write_zeroes(ns);
1558}
1559
cdbff4f2 1560static void nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
002fab04 1561 struct nvme_id_ns *id, struct nvme_ns_ids *ids)
1673f1f0 1562{
002fab04
CH		 1563 memset(ids, 0, sizeof(*ids));
1564
cdbff4f2 1565 if (ctrl->vs >= NVME_VS(1, 1, 0))
002fab04 1566 memcpy(ids->eui64, id->eui64, sizeof(id->eui64));
cdbff4f2 1567 if (ctrl->vs >= NVME_VS(1, 2, 0))
002fab04 1568 memcpy(ids->nguid, id->nguid, sizeof(id->nguid));
cdbff4f2 1569 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1570 /* Don't treat error as fatal we potentially
1571 * already have a NGUID or EUI-64
1572 */
002fab04 1573 if (nvme_identify_ns_descs(ctrl, nsid, ids))
cdbff4f2 1574 dev_warn(ctrl->device,
3b22ba26
JT		 1575 "%s: Identify Descriptors failed\n", __func__);
1576 }
ac81bfa9
MB		 1577}
1578
ed754e5d
CH		 1579static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1580{
1581 return !uuid_is_null(&ids->uuid) ||
1582 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1583 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1584}
1585
002fab04
CH		 1586static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1587{
1588 return uuid_equal(&a->uuid, &b->uuid) &&
1589 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1590 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0;
1591}
1592
24b0b58c
CH		 1593static void nvme_update_disk_info(struct gendisk *disk,
1594 struct nvme_ns *ns, struct nvme_id_ns *id)
1595{
1596 sector_t capacity = le64_to_cpup(&id->nsze) << (ns->lba_shift - 9);
cee160fd 1597 unsigned short bs = 1 << ns->lba_shift;
24b0b58c
CH		 1598
1599 blk_mq_freeze_queue(disk->queue);
1600 blk_integrity_unregister(disk);
1601
cee160fd
JL		 1602 blk_queue_logical_block_size(disk->queue, bs);
1603 blk_queue_physical_block_size(disk->queue, bs);
1604 blk_queue_io_min(disk->queue, bs);
1605
24b0b58c
CH		 1606 if (ns->ms && !ns->ext &&
1607 (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1608 nvme_init_integrity(disk, ns->ms, ns->pi_type);
715ea9e0 1609 if (ns->ms && !nvme_ns_has_pi(ns) && !blk_get_integrity(disk))
24b0b58c 1610 capacity = 0;
24b0b58c 1611
3831761e 1612 set_capacity(disk, capacity);
6e02318e 1613 nvme_ns_config_oncs(ns);
1293477f
CK		 1614
1615 if (id->nsattr & (1 << 0))
1616 set_disk_ro(disk, true);
1617 else
1618 set_disk_ro(disk, false);
1619
24b0b58c
CH		 1620 blk_mq_unfreeze_queue(disk->queue);
1621}
1622
ac81bfa9
MB		 1623static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1624{
1625 struct nvme_ns *ns = disk->private_data;
1673f1f0
CH		 1626
1627 /*
1628 * If identify namespace failed, use default 512 byte block size so
1629 * block layer can use before failing read/write for 0 capacity.
1630 */
c81bfba9 1631 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1632 if (ns->lba_shift == 0)
1633 ns->lba_shift = 9;
6b8190d6 1634 ns->noiob = le16_to_cpu(id->noiob);
b5be3b39 1635 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
c97f414c 1636 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
b5be3b39
CH		 1637 /* the PI implementation requires metadata equal t10 pi tuple size */
1638 if (ns->ms == sizeof(struct t10_pi_tuple))
1639 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1640 else
1641 ns->pi_type = 0;
1673f1f0 1642
6b8190d6
SB		 1643 if (ns->noiob)
1644 nvme_set_chunk_size(ns);
24b0b58c 1645 nvme_update_disk_info(disk, ns, id);
32acab31 1646#ifdef CONFIG_NVME_MULTIPATH
8f676b85 1647 if (ns->head->disk) {
32acab31 1648 nvme_update_disk_info(ns->head->disk, ns, id);
8f676b85
SG		 1649 blk_queue_stack_limits(ns->head->disk->queue, ns->queue);
1650 }
32acab31 1651#endif
ac81bfa9 1652}
1673f1f0 1653
ac81bfa9
MB		 1654static int nvme_revalidate_disk(struct gendisk *disk)
1655{
1656 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1657 struct nvme_ctrl *ctrl = ns->ctrl;
1658 struct nvme_id_ns *id;
002fab04 1659 struct nvme_ns_ids ids;
cdbff4f2 1660 int ret = 0;
ac81bfa9
MB		 1661
1662 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1663 set_capacity(disk, 0);
1664 return -ENODEV;
1665 }
1666
ed754e5d 1667 id = nvme_identify_ns(ctrl, ns->head->ns_id);
cdbff4f2
CH		 1668 if (!id)
1669 return -ENODEV;
ac81bfa9 1670
cdbff4f2
CH		 1671 if (id->ncap == 0) {
1672 ret = -ENODEV;
1673 goto out;
1674 }
ac81bfa9 1675
5e0fab57 1676 __nvme_revalidate_disk(disk, id);
ed754e5d
CH		 1677 nvme_report_ns_ids(ctrl, ns->head->ns_id, id, &ids);
1678 if (!nvme_ns_ids_equal(&ns->head->ids, &ids)) {
1d5df6af 1679 dev_err(ctrl->device,
ed754e5d 1680 "identifiers changed for nsid %d\n", ns->head->ns_id);
1d5df6af
CH		 1681 ret = -ENODEV;
1682 }
1683
cdbff4f2
CH		 1684out:
1685 kfree(id);
1686 return ret;
1673f1f0
CH		 1687}
1688
1689static char nvme_pr_type(enum pr_type type)
1690{
1691 switch (type) {
1692 case PR_WRITE_EXCLUSIVE:
1693 return 1;
1694 case PR_EXCLUSIVE_ACCESS:
1695 return 2;
1696 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1697 return 3;
1698 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1699 return 4;
1700 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1701 return 5;
1702 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1703 return 6;
1704 default:
1705 return 0;
1706 }
1707};
1708
1709static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1710 u64 key, u64 sa_key, u8 op)
1711{
32acab31
CH		 1712 struct nvme_ns_head *head = NULL;
1713 struct nvme_ns *ns;
1673f1f0 1714 struct nvme_command c;
32acab31 1715 int srcu_idx, ret;
1673f1f0
CH		 1716 u8 data[16] = { 0, };
1717
b0d61d58
KB		 1718 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1719 if (unlikely(!ns))
1720 return -EWOULDBLOCK;
1721
1673f1f0
CH		 1722 put_unaligned_le64(key, &data[0]);
1723 put_unaligned_le64(sa_key, &data[8]);
1724
1725 memset(&c, 0, sizeof(c));
1726 c.common.opcode = op;
b0d61d58 1727 c.common.nsid = cpu_to_le32(ns->head->ns_id);
b7c8f366 1728 c.common.cdw10 = cpu_to_le32(cdw10);
1673f1f0 1729
b0d61d58 1730 ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
32acab31
CH		 1731 nvme_put_ns_from_disk(head, srcu_idx);
1732 return ret;
1673f1f0
CH		 1733}
1734
1735static int nvme_pr_register(struct block_device *bdev, u64 old,
1736 u64 new, unsigned flags)
1737{
1738 u32 cdw10;
1739
1740 if (flags & ~PR_FL_IGNORE_KEY)
1741 return -EOPNOTSUPP;
1742
1743 cdw10 = old ? 2 : 0;
1744 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1745 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1746 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1747}
1748
1749static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1750 enum pr_type type, unsigned flags)
1751{
1752 u32 cdw10;
1753
1754 if (flags & ~PR_FL_IGNORE_KEY)
1755 return -EOPNOTSUPP;
1756
1757 cdw10 = nvme_pr_type(type) << 8;
1758 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1759 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1760}
1761
1762static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1763 enum pr_type type, bool abort)
1764{
e9a9853c 1765 u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
1673f1f0
CH		 1766 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1767}
1768
1769static int nvme_pr_clear(struct block_device *bdev, u64 key)
1770{
8c0b3915 1771 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1772 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1773}
1774
1775static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1776{
e9a9853c 1777 u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1778 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1779}
1780
1781static const struct pr_ops nvme_pr_ops = {
1782 .pr_register = nvme_pr_register,
1783 .pr_reserve = nvme_pr_reserve,
1784 .pr_release = nvme_pr_release,
1785 .pr_preempt = nvme_pr_preempt,
1786 .pr_clear = nvme_pr_clear,
1787};
1788
a98e58e5 1789#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1790int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1791 bool send)
a98e58e5 1792{
4f1244c8 1793 struct nvme_ctrl *ctrl = data;
a98e58e5 1794 struct nvme_command cmd;
a98e58e5
SB		 1795
1796 memset(&cmd, 0, sizeof(cmd));
1797 if (send)
1798 cmd.common.opcode = nvme_admin_security_send;
1799 else
1800 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 1801 cmd.common.nsid = 0;
b7c8f366
CK		 1802 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1803 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5
SB		 1804
1805 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
6287b51c 1806 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0, false);
a98e58e5
SB		 1807}
1808EXPORT_SYMBOL_GPL(nvme_sec_submit);
1809#endif /* CONFIG_BLK_SED_OPAL */
1810
5bae7f73 1811static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1812 .owner = THIS_MODULE,
1813 .ioctl = nvme_ioctl,
761f2e1e 1814 .compat_ioctl = nvme_ioctl,
1673f1f0
CH		 1815 .open = nvme_open,
1816 .release = nvme_release,
1817 .getgeo = nvme_getgeo,
1818 .revalidate_disk= nvme_revalidate_disk,
1819 .pr_ops = &nvme_pr_ops,
1820};
1821
32acab31
CH		 1822#ifdef CONFIG_NVME_MULTIPATH
1823static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
1824{
1825 struct nvme_ns_head *head = bdev->bd_disk->private_data;
1826
1827 if (!kref_get_unless_zero(&head->ref))
1828 return -ENXIO;
1829 return 0;
1830}
1831
1832static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
1833{
1834 nvme_put_ns_head(disk->private_data);
1835}
1836
1837const struct block_device_operations nvme_ns_head_ops = {
1838 .owner = THIS_MODULE,
1839 .open = nvme_ns_head_open,
1840 .release = nvme_ns_head_release,
1841 .ioctl = nvme_ioctl,
1842 .compat_ioctl = nvme_ioctl,
1843 .getgeo = nvme_getgeo,
1844 .pr_ops = &nvme_pr_ops,
1845};
1846#endif /* CONFIG_NVME_MULTIPATH */
1847
5fd4ce1b
CH		 1848static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1849{
1850 unsigned long timeout =
1851 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1852 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1853 int ret;
1854
1855 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1856 if (csts == ~0)
1857 return -ENODEV;
5fd4ce1b
CH		 1858 if ((csts & NVME_CSTS_RDY) == bit)
1859 break;
1860
1861 msleep(100);
1862 if (fatal_signal_pending(current))
1863 return -EINTR;
1864 if (time_after(jiffies, timeout)) {
1b3c47c1 1865 dev_err(ctrl->device,
5fd4ce1b
CH		 1866 "Device not ready; aborting %s\n", enabled ?
1867 "initialisation" : "reset");
1868 return -ENODEV;
1869 }
1870 }
1871
1872 return ret;
1873}
1874
1875/*
1876 * If the device has been passed off to us in an enabled state, just clear
1877 * the enabled bit. The spec says we should set the 'shutdown notification
1878 * bits', but doing so may cause the device to complete commands to the
1879 * admin queue ... and we don't know what memory that might be pointing at!
1880 */
1881int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1882{
1883 int ret;
1884
1885 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1886 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1887
1888 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1889 if (ret)
1890 return ret;
54adc010 1891
b5a10c5f 1892 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1893 msleep(NVME_QUIRK_DELAY_AMOUNT);
1894
5fd4ce1b
CH		 1895 return nvme_wait_ready(ctrl, cap, false);
1896}
576d55d6 1897EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1898
1899int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1900{
1901 /*
1902 * Default to a 4K page size, with the intention to update this
1903 * path in the future to accomodate architectures with differing
1904 * kernel and IO page sizes.
1905 */
1906 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1907 int ret;
1908
1909 if (page_shift < dev_page_min) {
1b3c47c1 1910 dev_err(ctrl->device,
5fd4ce1b
CH		 1911 "Minimum device page size %u too large for host (%u)\n",
1912 1 << dev_page_min, 1 << page_shift);
1913 return -ENODEV;
1914 }
1915
1916 ctrl->page_size = 1 << page_shift;
1917
1918 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1919 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 1920 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 1921 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1922 ctrl->ctrl_config |= NVME_CC_ENABLE;
1923
1924 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1925 if (ret)
1926 return ret;
1927 return nvme_wait_ready(ctrl, cap, true);
1928}
576d55d6 1929EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1930
1931int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1932{
07fbd32a 1933 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 1934 u32 csts;
1935 int ret;
1936
1937 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1938 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1939
1940 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1941 if (ret)
1942 return ret;
1943
1944 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1945 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1946 break;
1947
1948 msleep(100);
1949 if (fatal_signal_pending(current))
1950 return -EINTR;
1951 if (time_after(jiffies, timeout)) {
1b3c47c1 1952 dev_err(ctrl->device,
5fd4ce1b
CH		 1953 "Device shutdown incomplete; abort shutdown\n");
1954 return -ENODEV;
1955 }
1956 }
1957
1958 return ret;
1959}
576d55d6 1960EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1961
da35825d
CH		 1962static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1963 struct request_queue *q)
1964{
7c88cb00
JA		 1965 bool vwc = false;
1966
da35825d 1967 if (ctrl->max_hw_sectors) {
45686b61
CH		 1968 u32 max_segments =
1969 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1970
943e942e 1971 max_segments = min_not_zero(max_segments, ctrl->max_segments);
da35825d 1972 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1973 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1974 }
249159c5
KB		 1975 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
1976 is_power_of_2(ctrl->max_hw_sectors))
e6282aef 1977 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1978 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1979 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1980 vwc = true;
1981 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1982}
1983
dbf86b39
JD		 1984static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1985{
1986 __le64 ts;
1987 int ret;
1988
1989 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1990 return 0;
1991
1992 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1993 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
1994 NULL);
1995 if (ret)
1996 dev_warn_once(ctrl->device,
1997 "could not set timestamp (%d)\n", ret);
1998 return ret;
1999}
2000
49cd84b6
KB		 2001static int nvme_configure_acre(struct nvme_ctrl *ctrl)
2002{
2003 struct nvme_feat_host_behavior *host;
2004 int ret;
2005
2006 /* Don't bother enabling the feature if retry delay is not reported */
2007 if (!ctrl->crdt[0])
2008 return 0;
2009
2010 host = kzalloc(sizeof(*host), GFP_KERNEL);
2011 if (!host)
2012 return 0;
2013
2014 host->acre = NVME_ENABLE_ACRE;
2015 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2016 host, sizeof(*host), NULL);
2017 kfree(host);
2018 return ret;
2019}
2020
634b8325 2021static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 2022{
2023 /*
2024 * APST (Autonomous Power State Transition) lets us program a
2025 * table of power state transitions that the controller will
2026 * perform automatically. We configure it with a simple
2027 * heuristic: we are willing to spend at most 2% of the time
2028 * transitioning between power states. Therefore, when running
2029 * in any given state, we will enter the next lower-power
76e4ad09 2030 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 2031 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 2032 * the requested maximum latency.
2033 *
2034 * We will not autonomously enter any non-operational state for
2035 * which the total latency exceeds ps_max_latency_us. Users
2036 * can set ps_max_latency_us to zero to turn off APST.
2037 */
2038
2039 unsigned apste;
2040 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 2041 u64 max_lat_us = 0;
2042 int max_ps = -1;
c5552fde
AL		 2043 int ret;
2044
2045 /*
2046 * If APST isn't supported or if we haven't been initialized yet,
2047 * then don't do anything.
2048 */
2049 if (!ctrl->apsta)
634b8325 2050 return 0;
c5552fde
AL		 2051
2052 if (ctrl->npss > 31) {
2053 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2054 return 0;
c5552fde
AL		 2055 }
2056
2057 table = kzalloc(sizeof(*table), GFP_KERNEL);
2058 if (!table)
634b8325 2059 return 0;
c5552fde 2060
76a5af84 2061 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 2062 /* Turn off APST. */
2063 apste = 0;
fb0dc399 2064 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 2065 } else {
2066 __le64 target = cpu_to_le64(0);
2067 int state;
2068
2069 /*
2070 * Walk through all states from lowest- to highest-power.
2071 * According to the spec, lower-numbered states use more
2072 * power. NPSS, despite the name, is the index of the
2073 * lowest-power state, not the number of states.
2074 */
2075 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 2076 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 2077
2078 if (target)
2079 table->entries[state] = target;
2080
ff5350a8
AL		 2081 /*
2082 * Don't allow transitions to the deepest state
2083 * if it's quirked off.
2084 */
2085 if (state == ctrl->npss &&
2086 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2087 continue;
2088
c5552fde
AL		 2089 /*
2090 * Is this state a useful non-operational state for
2091 * higher-power states to autonomously transition to?
2092 */
2093 if (!(ctrl->psd[state].flags &
2094 NVME_PS_FLAGS_NON_OP_STATE))
2095 continue;
2096
da87591b
KHF		 2097 exit_latency_us =
2098 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2099 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 2100 continue;
2101
da87591b
KHF		 2102 total_latency_us =
2103 exit_latency_us +
2104 le32_to_cpu(ctrl->psd[state].entry_lat);
2105
c5552fde
AL		 2106 /*
2107 * This state is good. Use it as the APST idle
2108 * target for higher power states.
2109 */
2110 transition_ms = total_latency_us + 19;
2111 do_div(transition_ms, 20);
2112 if (transition_ms > (1 << 24) - 1)
2113 transition_ms = (1 << 24) - 1;
2114
2115 target = cpu_to_le64((state << 3) |
2116 (transition_ms << 8));
fb0dc399
AL		 2117
2118 if (max_ps == -1)
2119 max_ps = state;
2120
2121 if (total_latency_us > max_lat_us)
2122 max_lat_us = total_latency_us;
c5552fde
AL		 2123 }
2124
2125 apste = 1;
fb0dc399
AL		 2126
2127 if (max_ps == -1) {
2128 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2129 } else {
2130 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2131 max_ps, max_lat_us, (int)sizeof(*table), table);
2132 }
c5552fde
AL		 2133 }
2134
2135 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2136 table, sizeof(*table), NULL);
2137 if (ret)
2138 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
2139
2140 kfree(table);
634b8325 2141 return ret;
c5552fde
AL		 2142}
2143
2144static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2145{
2146 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2147 u64 latency;
2148
2149 switch (val) {
2150 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2151 case PM_QOS_LATENCY_ANY:
2152 latency = U64_MAX;
2153 break;
2154
2155 default:
2156 latency = val;
2157 }
2158
2159 if (ctrl->ps_max_latency_us != latency) {
2160 ctrl->ps_max_latency_us = latency;
2161 nvme_configure_apst(ctrl);
2162 }
2163}
2164
bd4da3ab
AL		 2165struct nvme_core_quirk_entry {
2166 /*
2167 * NVMe model and firmware strings are padded with spaces. For
2168 * simplicity, strings in the quirk table are padded with NULLs
2169 * instead.
2170 */
2171 u16 vid;
2172 const char *mn;
2173 const char *fr;
2174 unsigned long quirks;
2175};
2176
2177static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2178 {
be56945c
AL		 2179 /*
2180 * This Toshiba device seems to die using any APST states. See:
2181 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2182 */
2183 .vid = 0x1179,
2184 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2185 .quirks = NVME_QUIRK_NO_APST,
be56945c 2186 }
bd4da3ab
AL		 2187};
2188
2189/* match is null-terminated but idstr is space-padded. */
2190static bool string_matches(const char *idstr, const char *match, size_t len)
2191{
2192 size_t matchlen;
2193
2194 if (!match)
2195 return true;
2196
2197 matchlen = strlen(match);
2198 WARN_ON_ONCE(matchlen > len);
2199
2200 if (memcmp(idstr, match, matchlen))
2201 return false;
2202
2203 for (; matchlen < len; matchlen++)
2204 if (idstr[matchlen] != ' ')
2205 return false;
2206
2207 return true;
2208}
2209
2210static bool quirk_matches(const struct nvme_id_ctrl *id,
2211 const struct nvme_core_quirk_entry *q)
2212{
2213 return q->vid == le16_to_cpu(id->vid) &&
2214 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2215 string_matches(id->fr, q->fr, sizeof(id->fr));
2216}
2217
ab9e00cc
CH		 2218static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2219 struct nvme_id_ctrl *id)
180de007
CH		 2220{
2221 size_t nqnlen;
2222 int off;
2223
6299358d
JD		 2224 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2225 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2226 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
2227 strlcpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
2228 return;
2229 }
180de007 2230
6299358d
JD		 2231 if (ctrl->vs >= NVME_VS(1, 2, 1))
2232 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2233 }
180de007
CH		 2234
2235 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 2236 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2237 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2238 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2239 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2240 off += sizeof(id->sn);
ab9e00cc 2241 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2242 off += sizeof(id->mn);
ab9e00cc
CH		 2243 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2244}
2245
2246static void __nvme_release_subsystem(struct nvme_subsystem *subsys)
2247{
2248 ida_simple_remove(&nvme_subsystems_ida, subsys->instance);
2249 kfree(subsys);
2250}
2251
2252static void nvme_release_subsystem(struct device *dev)
2253{
2254 __nvme_release_subsystem(container_of(dev, struct nvme_subsystem, dev));
2255}
2256
2257static void nvme_destroy_subsystem(struct kref *ref)
2258{
2259 struct nvme_subsystem *subsys =
2260 container_of(ref, struct nvme_subsystem, ref);
2261
2262 mutex_lock(&nvme_subsystems_lock);
2263 list_del(&subsys->entry);
2264 mutex_unlock(&nvme_subsystems_lock);
2265
ed754e5d 2266 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2267 device_del(&subsys->dev);
2268 put_device(&subsys->dev);
2269}
2270
2271static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2272{
2273 kref_put(&subsys->ref, nvme_destroy_subsystem);
2274}
2275
2276static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2277{
2278 struct nvme_subsystem *subsys;
2279
2280 lockdep_assert_held(&nvme_subsystems_lock);
2281
2282 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2283 if (strcmp(subsys->subnqn, subsysnqn))
2284 continue;
2285 if (!kref_get_unless_zero(&subsys->ref))
2286 continue;
2287 return subsys;
2288 }
2289
2290 return NULL;
2291}
2292
1e496938
HR		 2293#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2294 struct device_attribute subsys_attr_##_name = \
2295 __ATTR(_name, _mode, _show, NULL)
2296
2297static ssize_t nvme_subsys_show_nqn(struct device *dev,
2298 struct device_attribute *attr,
2299 char *buf)
2300{
2301 struct nvme_subsystem *subsys =
2302 container_of(dev, struct nvme_subsystem, dev);
2303
2304 return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2305}
2306static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2307
2308#define nvme_subsys_show_str_function(field) \
2309static ssize_t subsys_##field##_show(struct device *dev, \
2310 struct device_attribute *attr, char *buf) \
2311{ \
2312 struct nvme_subsystem *subsys = \
2313 container_of(dev, struct nvme_subsystem, dev); \
2314 return sprintf(buf, "%.*s\n", \
2315 (int)sizeof(subsys->field), subsys->field); \
2316} \
2317static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2318
2319nvme_subsys_show_str_function(model);
2320nvme_subsys_show_str_function(serial);
2321nvme_subsys_show_str_function(firmware_rev);
2322
2323static struct attribute *nvme_subsys_attrs[] = {
2324 &subsys_attr_model.attr,
2325 &subsys_attr_serial.attr,
2326 &subsys_attr_firmware_rev.attr,
2327 &subsys_attr_subsysnqn.attr,
75c10e73
HR		 2328#ifdef CONFIG_NVME_MULTIPATH
2329 &subsys_attr_iopolicy.attr,
2330#endif
1e496938
HR		 2331 NULL,
2332};
2333
2334static struct attribute_group nvme_subsys_attrs_group = {
2335 .attrs = nvme_subsys_attrs,
2336};
2337
2338static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2339 &nvme_subsys_attrs_group,
2340 NULL,
2341};
2342
b837b283
IR		 2343static int nvme_active_ctrls(struct nvme_subsystem *subsys)
2344{
2345 int count = 0;
2346 struct nvme_ctrl *ctrl;
2347
2348 mutex_lock(&subsys->lock);
2349 list_for_each_entry(ctrl, &subsys->ctrls, subsys_entry) {
2350 if (ctrl->state != NVME_CTRL_DELETING &&
2351 ctrl->state != NVME_CTRL_DEAD)
2352 count++;
2353 }
2354 mutex_unlock(&subsys->lock);
2355
2356 return count;
2357}
2358
ab9e00cc
CH		 2359static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2360{
2361 struct nvme_subsystem *subsys, *found;
2362 int ret;
2363
2364 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2365 if (!subsys)
2366 return -ENOMEM;
2367 ret = ida_simple_get(&nvme_subsystems_ida, 0, 0, GFP_KERNEL);
2368 if (ret < 0) {
2369 kfree(subsys);
2370 return ret;
2371 }
2372 subsys->instance = ret;
2373 mutex_init(&subsys->lock);
2374 kref_init(&subsys->ref);
2375 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2376 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2377 nvme_init_subnqn(subsys, ctrl, id);
2378 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2379 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2380 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2381 subsys->vendor_id = le16_to_cpu(id->vid);
2382 subsys->cmic = id->cmic;
75c10e73
HR		 2383#ifdef CONFIG_NVME_MULTIPATH
2384 subsys->iopolicy = NVME_IOPOLICY_NUMA;
2385#endif
ab9e00cc
CH		 2386
2387 subsys->dev.class = nvme_subsys_class;
2388 subsys->dev.release = nvme_release_subsystem;
1e496938 2389 subsys->dev.groups = nvme_subsys_attrs_groups;
ab9e00cc
CH		 2390 dev_set_name(&subsys->dev, "nvme-subsys%d", subsys->instance);
2391 device_initialize(&subsys->dev);
2392
2393 mutex_lock(&nvme_subsystems_lock);
2394 found = __nvme_find_get_subsystem(subsys->subnqn);
2395 if (found) {
2396 /*
2397 * Verify that the subsystem actually supports multiple
2398 * controllers, else bail out.
2399 */
16001c10 2400 if (!(ctrl->opts && ctrl->opts->discovery_nqn) &&
181303d0 2401 nvme_active_ctrls(found) && !(id->cmic & (1 << 1))) {
ab9e00cc
CH		 2402 dev_err(ctrl->device,
2403 "ignoring ctrl due to duplicate subnqn (%s).\n",
2404 found->subnqn);
2405 nvme_put_subsystem(found);
2406 ret = -EINVAL;
2407 goto out_unlock;
2408 }
2409
2410 __nvme_release_subsystem(subsys);
2411 subsys = found;
2412 } else {
2413 ret = device_add(&subsys->dev);
2414 if (ret) {
2415 dev_err(ctrl->device,
2416 "failed to register subsystem device.\n");
2417 goto out_unlock;
2418 }
ed754e5d 2419 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2420 list_add_tail(&subsys->entry, &nvme_subsystems);
2421 }
2422
2423 ctrl->subsys = subsys;
2424 mutex_unlock(&nvme_subsystems_lock);
2425
2426 if (sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2427 dev_name(ctrl->device))) {
2428 dev_err(ctrl->device,
2429 "failed to create sysfs link from subsystem.\n");
2430 /* the transport driver will eventually put the subsystem */
2431 return -EINVAL;
2432 }
2433
2434 mutex_lock(&subsys->lock);
2435 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
2436 mutex_unlock(&subsys->lock);
2437
2438 return 0;
2439
2440out_unlock:
2441 mutex_unlock(&nvme_subsystems_lock);
2442 put_device(&subsys->dev);
2443 return ret;
180de007
CH		 2444}
2445
0e98719b
CH		 2446int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp,
2447 void *log, size_t size, u64 offset)
c627c487
KB		 2448{
2449 struct nvme_command c = { };
70da6094
MB		 2450 unsigned long dwlen = size / 4 - 1;
2451
2452 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2453 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2454 c.get_log_page.lid = log_page;
0e98719b 2455 c.get_log_page.lsp = lsp;
70da6094
MB		 2456 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2457 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2458 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2459 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
c627c487
KB		 2460
2461 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2462}
2463
84fef62d
KB		 2464static int nvme_get_effects_log(struct nvme_ctrl *ctrl)
2465{
2466 int ret;
2467
2468 if (!ctrl->effects)
2469 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
2470
2471 if (!ctrl->effects)
2472 return 0;
2473
0e98719b
CH		 2474 ret = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CMD_EFFECTS, 0,
2475 ctrl->effects, sizeof(*ctrl->effects), 0);
84fef62d
KB		 2476 if (ret) {
2477 kfree(ctrl->effects);
2478 ctrl->effects = NULL;
2479 }
2480 return ret;
180de007
CH		 2481}
2482
7fd8930f
CH		 2483/*
2484 * Initialize the cached copies of the Identify data and various controller
2485 * register in our nvme_ctrl structure. This should be called as soon as
2486 * the admin queue is fully up and running.
2487 */
2488int nvme_init_identify(struct nvme_ctrl *ctrl)
2489{
2490 struct nvme_id_ctrl *id;
2491 u64 cap;
2492 int ret, page_shift;
a229dbf6 2493 u32 max_hw_sectors;
76a5af84 2494 bool prev_apst_enabled;
7fd8930f 2495
f3ca80fc
CH		 2496 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2497 if (ret) {
1b3c47c1 2498 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 2499 return ret;
2500 }
2501
7fd8930f
CH		 2502 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
2503 if (ret) {
1b3c47c1 2504 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 2505 return ret;
2506 }
2507 page_shift = NVME_CAP_MPSMIN(cap) + 12;
2508
8ef2074d 2509 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 2510 ctrl->subsystem = NVME_CAP_NSSRC(cap);
2511
7fd8930f
CH		 2512 ret = nvme_identify_ctrl(ctrl, &id);
2513 if (ret) {
1b3c47c1 2514 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 2515 return -EIO;
2516 }
2517
84fef62d
KB		 2518 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
2519 ret = nvme_get_effects_log(ctrl);
2520 if (ret < 0)
75c8b19a 2521 goto out_free;
84fef62d 2522 }
180de007 2523
bd4da3ab 2524 if (!ctrl->identified) {
ab9e00cc
CH		 2525 int i;
2526
2527 ret = nvme_init_subsystem(ctrl, id);
2528 if (ret)
2529 goto out_free;
2530
bd4da3ab
AL		 2531 /*
2532 * Check for quirks. Quirk can depend on firmware version,
2533 * so, in principle, the set of quirks present can change
2534 * across a reset. As a possible future enhancement, we
2535 * could re-scan for quirks every time we reinitialize
2536 * the device, but we'd have to make sure that the driver
2537 * behaves intelligently if the quirks change.
2538 */
bd4da3ab
AL		 2539 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2540 if (quirk_matches(id, &core_quirks[i]))
2541 ctrl->quirks |= core_quirks[i].quirks;
2542 }
2543 }
2544
c35e30b4 2545 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2546 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 2547 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2548 }
2549
49cd84b6
KB		 2550 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
2551 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
2552 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
2553
8a9ae523 2554 ctrl->oacs = le16_to_cpu(id->oacs);
7fd8930f 2555 ctrl->oncs = le16_to_cpup(&id->oncs);
c0561f82 2556 ctrl->oaes = le32_to_cpu(id->oaes);
6bf25d16 2557 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2558 ctrl->vwc = id->vwc;
7fd8930f 2559 if (id->mdts)
a229dbf6 2560 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 2561 else
a229dbf6
CH		 2562 max_hw_sectors = UINT_MAX;
2563 ctrl->max_hw_sectors =
2564 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2565
da35825d 2566 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2567 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2568 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 2569 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 2570 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 2571
07fbd32a
MP		 2572 if (id->rtd3e) {
2573 /* us -> s */
2574 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
2575
2576 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2577 shutdown_timeout, 60);
2578
2579 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 2580 dev_info(ctrl->device,
07fbd32a
MP		 2581 "Shutdown timeout set to %u seconds\n",
2582 ctrl->shutdown_timeout);
2583 } else
2584 ctrl->shutdown_timeout = shutdown_timeout;
2585
c5552fde 2586 ctrl->npss = id->npss;
76a5af84
KHF		 2587 ctrl->apsta = id->apsta;
2588 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 2589 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2590 if (force_apst && id->apsta) {
f0425db0 2591 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2592 ctrl->apst_enabled = true;
c35e30b4 2593 } else {
76a5af84 2594 ctrl->apst_enabled = false;
c35e30b4
AL		 2595 }
2596 } else {
76a5af84 2597 ctrl->apst_enabled = id->apsta;
c35e30b4 2598 }
c5552fde
AL		 2599 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2600
d3d5b87d 2601 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 2602 ctrl->icdoff = le16_to_cpu(id->icdoff);
2603 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2604 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2605 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2606
2607 /*
2608 * In fabrics we need to verify the cntlid matches the
2609 * admin connect
2610 */
634b8325 2611 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 2612 ret = -EINVAL;
634b8325
KB		 2613 goto out_free;
2614 }
038bd4cb
SG		 2615
2616 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 2617 dev_err(ctrl->device,
038bd4cb
SG		 2618 "keep-alive support is mandatory for fabrics\n");
2619 ret = -EINVAL;
634b8325 2620 goto out_free;
038bd4cb 2621 }
07bfcd09
CH		 2622 } else {
2623 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 2624 ctrl->hmpre = le32_to_cpu(id->hmpre);
2625 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 2626 ctrl->hmminds = le32_to_cpu(id->hmminds);
2627 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2628 }
da35825d 2629
0d0b660f 2630 ret = nvme_mpath_init(ctrl, id);
7fd8930f 2631 kfree(id);
bd4da3ab 2632
0d0b660f
CH		 2633 if (ret < 0)
2634 return ret;
2635
76a5af84 2636 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2637 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2638 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 2639 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2640
634b8325
KB		 2641 ret = nvme_configure_apst(ctrl);
2642 if (ret < 0)
2643 return ret;
dbf86b39
JD		 2644
2645 ret = nvme_configure_timestamp(ctrl);
2646 if (ret < 0)
2647 return ret;
634b8325
KB		 2648
2649 ret = nvme_configure_directives(ctrl);
2650 if (ret < 0)
2651 return ret;
c5552fde 2652
49cd84b6
KB		 2653 ret = nvme_configure_acre(ctrl);
2654 if (ret < 0)
2655 return ret;
2656
bd4da3ab 2657 ctrl->identified = true;
c5552fde 2658
634b8325
KB		 2659 return 0;
2660
2661out_free:
2662 kfree(id);
07bfcd09 2663 return ret;
7fd8930f 2664}
576d55d6 2665EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 2666
f3ca80fc 2667static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 2668{
a6a5149b
CH		 2669 struct nvme_ctrl *ctrl =
2670 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 2671
2b1b7e78
JW		 2672 switch (ctrl->state) {
2673 case NVME_CTRL_LIVE:
2674 case NVME_CTRL_ADMIN_ONLY:
2675 break;
2676 default:
a6a5149b 2677 return -EWOULDBLOCK;
2b1b7e78
JW		 2678 }
2679
a6a5149b 2680 file->private_data = ctrl;
f3ca80fc
CH		 2681 return 0;
2682}
2683
bfd89471
CH		 2684static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
2685{
2686 struct nvme_ns *ns;
2687 int ret;
2688
765cc031 2689 down_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2690 if (list_empty(&ctrl->namespaces)) {
2691 ret = -ENOTTY;
2692 goto out_unlock;
2693 }
2694
2695 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
2696 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 2697 dev_warn(ctrl->device,
bfd89471
CH		 2698 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
2699 ret = -EINVAL;
2700 goto out_unlock;
2701 }
2702
1b3c47c1 2703 dev_warn(ctrl->device,
bfd89471
CH		 2704 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
2705 kref_get(&ns->kref);
765cc031 2706 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2707
2708 ret = nvme_user_cmd(ctrl, ns, argp);
2709 nvme_put_ns(ns);
2710 return ret;
2711
2712out_unlock:
765cc031 2713 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2714 return ret;
2715}
2716
f3ca80fc
CH		 2717static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2718 unsigned long arg)
2719{
2720 struct nvme_ctrl *ctrl = file->private_data;
2721 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2722
2723 switch (cmd) {
2724 case NVME_IOCTL_ADMIN_CMD:
2725 return nvme_user_cmd(ctrl, NULL, argp);
2726 case NVME_IOCTL_IO_CMD:
bfd89471 2727 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2728 case NVME_IOCTL_RESET:
1b3c47c1 2729 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2730 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2731 case NVME_IOCTL_SUBSYS_RESET:
2732 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2733 case NVME_IOCTL_RESCAN:
2734 nvme_queue_scan(ctrl);
2735 return 0;
f3ca80fc
CH		 2736 default:
2737 return -ENOTTY;
2738 }
2739}
2740
2741static const struct file_operations nvme_dev_fops = {
2742 .owner = THIS_MODULE,
2743 .open = nvme_dev_open,
f3ca80fc
CH		 2744 .unlocked_ioctl = nvme_dev_ioctl,
2745 .compat_ioctl = nvme_dev_ioctl,
2746};
2747
2748static ssize_t nvme_sysfs_reset(struct device *dev,
2749 struct device_attribute *attr, const char *buf,
2750 size_t count)
2751{
2752 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2753 int ret;
2754
d86c4d8e 2755 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2756 if (ret < 0)
2757 return ret;
2758 return count;
1673f1f0 2759}
f3ca80fc 2760static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2761
9ec3bb2f
KB		 2762static ssize_t nvme_sysfs_rescan(struct device *dev,
2763 struct device_attribute *attr, const char *buf,
2764 size_t count)
2765{
2766 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2767
2768 nvme_queue_scan(ctrl);
2769 return count;
2770}
2771static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2772
5b85b826
CH		 2773static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
2774{
2775 struct gendisk *disk = dev_to_disk(dev);
2776
2777 if (disk->fops == &nvme_fops)
2778 return nvme_get_ns_from_dev(dev)->head;
2779 else
2780 return disk->private_data;
2781}
2782
118472ab 2783static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2784 char *buf)
118472ab 2785{
5b85b826
CH		 2786 struct nvme_ns_head *head = dev_to_ns_head(dev);
2787 struct nvme_ns_ids *ids = &head->ids;
2788 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH		 2789 int serial_len = sizeof(subsys->serial);
2790 int model_len = sizeof(subsys->model);
118472ab 2791
002fab04
CH		 2792 if (!uuid_is_null(&ids->uuid))
2793 return sprintf(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 2794
002fab04
CH		 2795 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2796 return sprintf(buf, "eui.%16phN\n", ids->nguid);
118472ab 2797
002fab04
CH		 2798 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2799 return sprintf(buf, "eui.%8phN\n", ids->eui64);
118472ab 2800
ab9e00cc
CH		 2801 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
2802 subsys->serial[serial_len - 1] == '\0'))
118472ab 2803 serial_len--;
ab9e00cc
CH		 2804 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
2805 subsys->model[model_len - 1] == '\0'))
118472ab
KB		 2806 model_len--;
2807
ab9e00cc
CH		 2808 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
2809 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 2810 head->ns_id);
118472ab 2811}
c828a892 2812static DEVICE_ATTR_RO(wwid);
118472ab 2813
d934f984 2814static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2815 char *buf)
d934f984 2816{
5b85b826 2817 return sprintf(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 2818}
c828a892 2819static DEVICE_ATTR_RO(nguid);
d934f984 2820
2b9b6e86 2821static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2822 char *buf)
2b9b6e86 2823{
5b85b826 2824 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT		 2825
2826 /* For backward compatibility expose the NGUID to userspace if
2827 * we have no UUID set
2828 */
002fab04 2829 if (uuid_is_null(&ids->uuid)) {
d934f984
JT		 2830 printk_ratelimited(KERN_WARNING
2831 "No UUID available providing old NGUID\n");
002fab04 2832 return sprintf(buf, "%pU\n", ids->nguid);
d934f984 2833 }
002fab04 2834 return sprintf(buf, "%pU\n", &ids->uuid);
2b9b6e86 2835}
c828a892 2836static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB		 2837
2838static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 2839 char *buf)
2b9b6e86 2840{
5b85b826 2841 return sprintf(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 2842}
c828a892 2843static DEVICE_ATTR_RO(eui);
2b9b6e86
KB		 2844
2845static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2846 char *buf)
2b9b6e86 2847{
5b85b826 2848 return sprintf(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 2849}
c828a892 2850static DEVICE_ATTR_RO(nsid);
2b9b6e86 2851
5b85b826 2852static struct attribute *nvme_ns_id_attrs[] = {
118472ab 2853 &dev_attr_wwid.attr,
2b9b6e86 2854 &dev_attr_uuid.attr,
d934f984 2855 &dev_attr_nguid.attr,
2b9b6e86
KB		 2856 &dev_attr_eui.attr,
2857 &dev_attr_nsid.attr,
0d0b660f
CH		 2858#ifdef CONFIG_NVME_MULTIPATH
2859 &dev_attr_ana_grpid.attr,
2860 &dev_attr_ana_state.attr,
2861#endif
2b9b6e86
KB		 2862 NULL,
2863};
2864
5b85b826 2865static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2866 struct attribute *a, int n)
2867{
2868 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 2869 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB		 2870
2871 if (a == &dev_attr_uuid.attr) {
a04b5de5 2872 if (uuid_is_null(&ids->uuid) &&
002fab04 2873 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT		 2874 return 0;
2875 }
2876 if (a == &dev_attr_nguid.attr) {
002fab04 2877 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB		 2878 return 0;
2879 }
2880 if (a == &dev_attr_eui.attr) {
002fab04 2881 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB		 2882 return 0;
2883 }
0d0b660f
CH		 2884#ifdef CONFIG_NVME_MULTIPATH
2885 if (a == &dev_attr_ana_grpid.attr || a == &dev_attr_ana_state.attr) {
2886 if (dev_to_disk(dev)->fops != &nvme_fops) /* per-path attr */
2887 return 0;
2888 if (!nvme_ctrl_use_ana(nvme_get_ns_from_dev(dev)->ctrl))
2889 return 0;
2890 }
2891#endif
2b9b6e86
KB		 2892 return a->mode;
2893}
2894
eb090c4c 2895static const struct attribute_group nvme_ns_id_attr_group = {
5b85b826
CH		 2896 .attrs = nvme_ns_id_attrs,
2897 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB		 2898};
2899
33b14f67
HR		 2900const struct attribute_group *nvme_ns_id_attr_groups[] = {
2901 &nvme_ns_id_attr_group,
2902#ifdef CONFIG_NVM
2903 &nvme_nvm_attr_group,
2904#endif
2905 NULL,
2906};
2907
931e1c22 2908#define nvme_show_str_function(field) \
779ff756
KB		 2909static ssize_t field##_show(struct device *dev, \
2910 struct device_attribute *attr, char *buf) \
2911{ \
2912 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
ab9e00cc
CH		 2913 return sprintf(buf, "%.*s\n", \
2914 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB		 2915} \
2916static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2917
ab9e00cc
CH		 2918nvme_show_str_function(model);
2919nvme_show_str_function(serial);
2920nvme_show_str_function(firmware_rev);
2921
931e1c22
ML		 2922#define nvme_show_int_function(field) \
2923static ssize_t field##_show(struct device *dev, \
2924 struct device_attribute *attr, char *buf) \
2925{ \
2926 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2927 return sprintf(buf, "%d\n", ctrl->field); \
2928} \
2929static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2930
931e1c22 2931nvme_show_int_function(cntlid);
103e515e 2932nvme_show_int_function(numa_node);
779ff756 2933
1a353d85
ML		 2934static ssize_t nvme_sysfs_delete(struct device *dev,
2935 struct device_attribute *attr, const char *buf,
2936 size_t count)
2937{
2938 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2939
2940 if (device_remove_file_self(dev, attr))
c5017e85 2941 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML		 2942 return count;
2943}
2944static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2945
2946static ssize_t nvme_sysfs_show_transport(struct device *dev,
2947 struct device_attribute *attr,
2948 char *buf)
2949{
2950 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2951
2952 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2953}
2954static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2955
8432bdb2
SG		 2956static ssize_t nvme_sysfs_show_state(struct device *dev,
2957 struct device_attribute *attr,
2958 char *buf)
2959{
2960 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2961 static const char *const state_name[] = {
2962 [NVME_CTRL_NEW] = "new",
2963 [NVME_CTRL_LIVE] = "live",
2b1b7e78 2964 [NVME_CTRL_ADMIN_ONLY] = "only-admin",
8432bdb2 2965 [NVME_CTRL_RESETTING] = "resetting",
ad6a0a52 2966 [NVME_CTRL_CONNECTING] = "connecting",
8432bdb2
SG		 2967 [NVME_CTRL_DELETING] = "deleting",
2968 [NVME_CTRL_DEAD] = "dead",
2969 };
2970
2971 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2972 state_name[ctrl->state])
2973 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2974
2975 return sprintf(buf, "unknown state\n");
2976}
2977
2978static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2979
1a353d85
ML		 2980static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2981 struct device_attribute *attr,
2982 char *buf)
2983{
2984 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2985
ab9e00cc 2986 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML		 2987}
2988static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2989
2990static ssize_t nvme_sysfs_show_address(struct device *dev,
2991 struct device_attribute *attr,
2992 char *buf)
2993{
2994 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2995
2996 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2997}
2998static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2999
779ff756
KB		 3000static struct attribute *nvme_dev_attrs[] = {
3001 &dev_attr_reset_controller.attr,
9ec3bb2f 3002 &dev_attr_rescan_controller.attr,
779ff756
KB		 3003 &dev_attr_model.attr,
3004 &dev_attr_serial.attr,
3005 &dev_attr_firmware_rev.attr,
931e1c22 3006 &dev_attr_cntlid.attr,
1a353d85
ML		 3007 &dev_attr_delete_controller.attr,
3008 &dev_attr_transport.attr,
3009 &dev_attr_subsysnqn.attr,
3010 &dev_attr_address.attr,
8432bdb2 3011 &dev_attr_state.attr,
103e515e 3012 &dev_attr_numa_node.attr,
779ff756
KB		 3013 NULL
3014};
3015
1a353d85
ML		 3016static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
3017 struct attribute *a, int n)
3018{
3019 struct device *dev = container_of(kobj, struct device, kobj);
3020 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
3021
49d3d50b
CH		 3022 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
3023 return 0;
3024 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
3025 return 0;
1a353d85
ML		 3026
3027 return a->mode;
3028}
3029
779ff756 3030static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 3031 .attrs = nvme_dev_attrs,
3032 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 3033};
3034
3035static const struct attribute_group *nvme_dev_attr_groups[] = {
3036 &nvme_dev_attrs_group,
3037 NULL,
3038};
3039
ed754e5d
CH		 3040static struct nvme_ns_head *__nvme_find_ns_head(struct nvme_subsystem *subsys,
3041 unsigned nsid)
3042{
3043 struct nvme_ns_head *h;
3044
3045 lockdep_assert_held(&subsys->lock);
3046
3047 list_for_each_entry(h, &subsys->nsheads, entry) {
3048 if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
3049 return h;
3050 }
3051
3052 return NULL;
3053}
3054
3055static int __nvme_check_ids(struct nvme_subsystem *subsys,
3056 struct nvme_ns_head *new)
3057{
3058 struct nvme_ns_head *h;
3059
3060 lockdep_assert_held(&subsys->lock);
3061
3062 list_for_each_entry(h, &subsys->nsheads, entry) {
3063 if (nvme_ns_ids_valid(&new->ids) &&
2079699c 3064 !list_empty(&h->list) &&
ed754e5d
CH		 3065 nvme_ns_ids_equal(&new->ids, &h->ids))
3066 return -EINVAL;
3067 }
3068
3069 return 0;
3070}
3071
3072static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
3073 unsigned nsid, struct nvme_id_ns *id)
3074{
3075 struct nvme_ns_head *head;
f3334447 3076 size_t size = sizeof(*head);
ed754e5d
CH		 3077 int ret = -ENOMEM;
3078
f3334447
CH		 3079#ifdef CONFIG_NVME_MULTIPATH
3080 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3081#endif
3082
3083 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH		 3084 if (!head)
3085 goto out;
3086 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
3087 if (ret < 0)
3088 goto out_free_head;
3089 head->instance = ret;
3090 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 3091 ret = init_srcu_struct(&head->srcu);
3092 if (ret)
3093 goto out_ida_remove;
ed754e5d
CH		 3094 head->subsys = ctrl->subsys;
3095 head->ns_id = nsid;
3096 kref_init(&head->ref);
3097
3098 nvme_report_ns_ids(ctrl, nsid, id, &head->ids);
3099
3100 ret = __nvme_check_ids(ctrl->subsys, head);
3101 if (ret) {
3102 dev_err(ctrl->device,
3103 "duplicate IDs for nsid %d\n", nsid);
3104 goto out_cleanup_srcu;
3105 }
3106
32acab31
CH		 3107 ret = nvme_mpath_alloc_disk(ctrl, head);
3108 if (ret)
3109 goto out_cleanup_srcu;
3110
ed754e5d 3111 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 3112
3113 kref_get(&ctrl->subsys->ref);
3114
ed754e5d
CH		 3115 return head;
3116out_cleanup_srcu:
3117 cleanup_srcu_struct(&head->srcu);
fd92c77f 3118out_ida_remove:
ed754e5d
CH		 3119 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
3120out_free_head:
3121 kfree(head);
3122out:
3123 return ERR_PTR(ret);
3124}
3125
3126static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
9bd82b1a 3127 struct nvme_id_ns *id)
ed754e5d
CH		 3128{
3129 struct nvme_ctrl *ctrl = ns->ctrl;
3130 bool is_shared = id->nmic & (1 << 0);
3131 struct nvme_ns_head *head = NULL;
3132 int ret = 0;
3133
3134 mutex_lock(&ctrl->subsys->lock);
3135 if (is_shared)
3136 head = __nvme_find_ns_head(ctrl->subsys, nsid);
3137 if (!head) {
3138 head = nvme_alloc_ns_head(ctrl, nsid, id);
3139 if (IS_ERR(head)) {
3140 ret = PTR_ERR(head);
3141 goto out_unlock;
3142 }
ed754e5d
CH		 3143 } else {
3144 struct nvme_ns_ids ids;
3145
3146 nvme_report_ns_ids(ctrl, nsid, id, &ids);
3147 if (!nvme_ns_ids_equal(&head->ids, &ids)) {
3148 dev_err(ctrl->device,
3149 "IDs don't match for shared namespace %d\n",
3150 nsid);
3151 ret = -EINVAL;
3152 goto out_unlock;
3153 }
ed754e5d
CH		 3154 }
3155
3156 list_add_tail(&ns->siblings, &head->list);
3157 ns->head = head;
3158
3159out_unlock:
3160 mutex_unlock(&ctrl->subsys->lock);
3161 return ret;
3162}
3163
5bae7f73
CH		 3164static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
3165{
3166 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
3167 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
3168
ed754e5d 3169 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH		 3170}
3171
32f0c4af 3172static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3173{
32f0c4af 3174 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 3175
765cc031 3176 down_read(&ctrl->namespaces_rwsem);
5bae7f73 3177 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 3178 if (ns->head->ns_id == nsid) {
2dd41228
CH		 3179 if (!kref_get_unless_zero(&ns->kref))
3180 continue;
32f0c4af
KB		 3181 ret = ns;
3182 break;
3183 }
ed754e5d 3184 if (ns->head->ns_id > nsid)
5bae7f73
CH		 3185 break;
3186 }
765cc031 3187 up_read(&ctrl->namespaces_rwsem);
32f0c4af 3188 return ret;
5bae7f73
CH		 3189}
3190
f5d11840
JA		 3191static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
3192{
3193 struct streams_directive_params s;
3194 int ret;
3195
3196 if (!ctrl->nr_streams)
3197 return 0;
3198
ed754e5d 3199 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
f5d11840
JA		 3200 if (ret)
3201 return ret;
3202
3203 ns->sws = le32_to_cpu(s.sws);
3204 ns->sgs = le16_to_cpu(s.sgs);
3205
3206 if (ns->sws) {
3207 unsigned int bs = 1 << ns->lba_shift;
3208
3209 blk_queue_io_min(ns->queue, bs * ns->sws);
3210 if (ns->sgs)
3211 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
3212 }
3213
3214 return 0;
3215}
3216
ab4ab09c 3217static int nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73
CH		 3218{
3219 struct nvme_ns *ns;
3220 struct gendisk *disk;
ac81bfa9
MB		 3221 struct nvme_id_ns *id;
3222 char disk_name[DISK_NAME_LEN];
ab4ab09c 3223 int node = ctrl->numa_node, flags = GENHD_FL_EXT_DEVT, ret;
5bae7f73
CH		 3224
3225 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3226 if (!ns)
ab4ab09c 3227 return -ENOMEM;
5bae7f73
CH		 3228
3229 ns->queue = blk_mq_init_queue(ctrl->tagset);
ab4ab09c
HR		 3230 if (IS_ERR(ns->queue)) {
3231 ret = PTR_ERR(ns->queue);
ed754e5d 3232 goto out_free_ns;
ab4ab09c 3233 }
e0596ab2 3234
8b904b5b 3235 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
e0596ab2
LG		 3236 if (ctrl->ops->flags & NVME_F_PCI_P2PDMA)
3237 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3238
5bae7f73
CH		 3239 ns->queue->queuedata = ns;
3240 ns->ctrl = ctrl;
3241
5bae7f73 3242 kref_init(&ns->kref);
5bae7f73 3243 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 3244
3245 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 3246 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 3247
cdbff4f2 3248 id = nvme_identify_ns(ctrl, nsid);
ab4ab09c
HR		 3249 if (!id) {
3250 ret = -EIO;
ac81bfa9 3251 goto out_free_queue;
ab4ab09c 3252 }
ac81bfa9 3253
ab4ab09c
HR		 3254 if (id->ncap == 0) {
3255 ret = -EINVAL;
cdbff4f2 3256 goto out_free_id;
ab4ab09c 3257 }
cdbff4f2 3258
ab4ab09c
HR		 3259 ret = nvme_init_ns_head(ns, nsid, id);
3260 if (ret)
ed754e5d 3261 goto out_free_id;
654b4a4a 3262 nvme_setup_streams_ns(ctrl, ns);
a785dbcc 3263 nvme_set_disk_name(disk_name, ns, ctrl, &flags);
cdbff4f2 3264
3dc87dd0 3265 disk = alloc_disk_node(0, node);
ab4ab09c
HR		 3266 if (!disk) {
3267 ret = -ENOMEM;
ed754e5d 3268 goto out_unlink_ns;
ab4ab09c 3269 }
ac81bfa9 3270
3dc87dd0
MB		 3271 disk->fops = &nvme_fops;
3272 disk->private_data = ns;
3273 disk->queue = ns->queue;
32acab31 3274 disk->flags = flags;
3dc87dd0
MB		 3275 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
3276 ns->disk = disk;
3277
3278 __nvme_revalidate_disk(disk, id);
5bae7f73 3279
85136c01 3280 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
ab4ab09c
HR		 3281 ret = nvme_nvm_register(ns, disk_name, node);
3282 if (ret) {
85136c01
MB		 3283 dev_warn(ctrl->device, "LightNVM init failure\n");
3284 goto out_put_disk;
3285 }
3286 }
3287
765cc031 3288 down_write(&ctrl->namespaces_rwsem);
32f0c4af 3289 list_add_tail(&ns->list, &ctrl->namespaces);
765cc031 3290 up_write(&ctrl->namespaces_rwsem);
32f0c4af 3291
d22524a4 3292 nvme_get_ctrl(ctrl);
ac81bfa9 3293
33b14f67 3294 device_add_disk(ctrl->device, ns->disk, nvme_ns_id_attr_groups);
32acab31 3295
0d0b660f 3296 nvme_mpath_add_disk(ns, id);
b9e03857 3297 nvme_fault_inject_init(ns);
0d0b660f
CH		 3298 kfree(id);
3299
ab4ab09c 3300 return 0;
85136c01
MB		 3301 out_put_disk:
3302 put_disk(ns->disk);
ed754e5d
CH		 3303 out_unlink_ns:
3304 mutex_lock(&ctrl->subsys->lock);
3305 list_del_rcu(&ns->siblings);
3306 mutex_unlock(&ctrl->subsys->lock);
a63b8370 3307 nvme_put_ns_head(ns->head);
ac81bfa9
MB		 3308 out_free_id:
3309 kfree(id);
5bae7f73
CH		 3310 out_free_queue:
3311 blk_cleanup_queue(ns->queue);
3312 out_free_ns:
3313 kfree(ns);
ab4ab09c 3314 return ret;
5bae7f73
CH		 3315}
3316
3317static void nvme_ns_remove(struct nvme_ns *ns)
3318{
646017a6
KB		 3319 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3320 return;
69d3b8ac 3321
b9e03857 3322 nvme_fault_inject_fini(ns);
b0b4e09c 3323 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
5bae7f73 3324 del_gendisk(ns->disk);
5bae7f73 3325 blk_cleanup_queue(ns->queue);
bd9f5d65
ML		 3326 if (blk_get_integrity(ns->disk))
3327 blk_integrity_unregister(ns->disk);
5bae7f73 3328 }
32f0c4af 3329
ed754e5d 3330 mutex_lock(&ns->ctrl->subsys->lock);
9941a862 3331 list_del_rcu(&ns->siblings);
48f78be3 3332 nvme_mpath_clear_current_path(ns);
ed754e5d
CH		 3333 mutex_unlock(&ns->ctrl->subsys->lock);
3334
765cc031 3335 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3336 list_del_init(&ns->list);
765cc031 3337 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3338
9941a862 3339 synchronize_srcu(&ns->head->srcu);
479a322f 3340 nvme_mpath_check_last_path(ns);
5bae7f73
CH		 3341 nvme_put_ns(ns);
3342}
3343
540c801c
KB		 3344static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3345{
3346 struct nvme_ns *ns;
3347
32f0c4af 3348 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 3349 if (ns) {
b0b4e09c 3350 if (ns->disk && revalidate_disk(ns->disk))
540c801c 3351 nvme_ns_remove(ns);
32f0c4af 3352 nvme_put_ns(ns);
540c801c
KB		 3353 } else
3354 nvme_alloc_ns(ctrl, nsid);
3355}
3356
47b0e50a
SB		 3357static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3358 unsigned nsid)
3359{
3360 struct nvme_ns *ns, *next;
6f8e0d78 3361 LIST_HEAD(rm_list);
47b0e50a 3362
765cc031 3363 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3364 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
cf39a6bc 3365 if (ns->head->ns_id > nsid || test_bit(NVME_NS_DEAD, &ns->flags))
6f8e0d78 3366 list_move_tail(&ns->list, &rm_list);
47b0e50a 3367 }
765cc031 3368 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3369
3370 list_for_each_entry_safe(ns, next, &rm_list, list)
3371 nvme_ns_remove(ns);
3372
47b0e50a
SB		 3373}
3374
540c801c
KB		 3375static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
3376{
3377 struct nvme_ns *ns;
3378 __le32 *ns_list;
3379 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
3380 int ret = 0;
3381
42595eb7 3382 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3383 if (!ns_list)
3384 return -ENOMEM;
3385
3386 for (i = 0; i < num_lists; i++) {
3387 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
3388 if (ret)
47b0e50a 3389 goto free;
540c801c
KB		 3390
3391 for (j = 0; j < min(nn, 1024U); j++) {
3392 nsid = le32_to_cpu(ns_list[j]);
3393 if (!nsid)
3394 goto out;
3395
3396 nvme_validate_ns(ctrl, nsid);
3397
3398 while (++prev < nsid) {
32f0c4af
KB		 3399 ns = nvme_find_get_ns(ctrl, prev);
3400 if (ns) {
540c801c 3401 nvme_ns_remove(ns);
32f0c4af
KB		 3402 nvme_put_ns(ns);
3403 }
540c801c
KB		 3404 }
3405 }
3406 nn -= j;
3407 }
3408 out:
47b0e50a
SB		 3409 nvme_remove_invalid_namespaces(ctrl, prev);
3410 free:
540c801c
KB		 3411 kfree(ns_list);
3412 return ret;
3413}
3414
5955be21 3415static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 3416{
5bae7f73
CH		 3417 unsigned i;
3418
540c801c
KB		 3419 for (i = 1; i <= nn; i++)
3420 nvme_validate_ns(ctrl, i);
3421
47b0e50a 3422 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3423}
3424
f493af37 3425static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 3426{
3427 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
3428 __le32 *log;
f493af37 3429 int error;
30d90964
CH		 3430
3431 log = kzalloc(log_size, GFP_KERNEL);
3432 if (!log)
f493af37 3433 return;
30d90964 3434
f493af37
CH		 3435 /*
3436 * We need to read the log to clear the AEN, but we don't want to rely
3437 * on it for the changed namespace information as userspace could have
3438 * raced with us in reading the log page, which could cause us to miss
3439 * updates.
3440 */
0e98719b
CH		 3441 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0, log,
3442 log_size, 0);
f493af37 3443 if (error)
30d90964
CH		 3444 dev_warn(ctrl->device,
3445 "reading changed ns log failed: %d\n", error);
30d90964 3446
30d90964 3447 kfree(log);
30d90964
CH		 3448}
3449
5955be21 3450static void nvme_scan_work(struct work_struct *work)
5bae7f73 3451{
5955be21
CH		 3452 struct nvme_ctrl *ctrl =
3453 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 3454 struct nvme_id_ctrl *id;
540c801c 3455 unsigned nn;
5bae7f73 3456
5955be21
CH		 3457 if (ctrl->state != NVME_CTRL_LIVE)
3458 return;
3459
2b1b7e78
JW		 3460 WARN_ON_ONCE(!ctrl->tagset);
3461
77016199 3462 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 3463 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 3464 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 3465 }
3466
5bae7f73
CH		 3467 if (nvme_identify_ctrl(ctrl, &id))
3468 return;
540c801c 3469
e7ad43c3 3470 mutex_lock(&ctrl->scan_lock);
540c801c 3471 nn = le32_to_cpu(id->nn);
8ef2074d 3472 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 3473 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
3474 if (!nvme_scan_ns_list(ctrl, nn))
30d90964 3475 goto out_free_id;
540c801c 3476 }
5955be21 3477 nvme_scan_ns_sequential(ctrl, nn);
30d90964 3478out_free_id:
e7ad43c3 3479 mutex_unlock(&ctrl->scan_lock);
30d90964 3480 kfree(id);
765cc031 3481 down_write(&ctrl->namespaces_rwsem);
540c801c 3482 list_sort(NULL, &ctrl->namespaces, ns_cmp);
765cc031 3483 up_write(&ctrl->namespaces_rwsem);
5955be21 3484}
5bae7f73 3485
32f0c4af
KB		 3486/*
3487 * This function iterates the namespace list unlocked to allow recovery from
3488 * controller failure. It is up to the caller to ensure the namespace list is
3489 * not modified by scan work while this function is executing.
3490 */
5bae7f73
CH		 3491void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
3492{
3493 struct nvme_ns *ns, *next;
6f8e0d78 3494 LIST_HEAD(ns_list);
5bae7f73 3495
f6c8e432
SG		 3496 /* prevent racing with ns scanning */
3497 flush_work(&ctrl->scan_work);
3498
0ff9d4e1
KB		 3499 /*
3500 * The dead states indicates the controller was not gracefully
3501 * disconnected. In that case, we won't be able to flush any data while
3502 * removing the namespaces' disks; fail all the queues now to avoid
3503 * potentially having to clean up the failed sync later.
3504 */
3505 if (ctrl->state == NVME_CTRL_DEAD)
3506 nvme_kill_queues(ctrl);
3507
765cc031 3508 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 3509 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 3510 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3511
3512 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 3513 nvme_ns_remove(ns);
3514}
576d55d6 3515EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 3516
e3d7874d
KB		 3517static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
3518{
3519 char *envp[2] = { NULL, NULL };
3520 u32 aen_result = ctrl->aen_result;
3521
3522 ctrl->aen_result = 0;
3523 if (!aen_result)
3524 return;
3525
3526 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
3527 if (!envp[0])
3528 return;
3529 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
3530 kfree(envp[0]);
3531}
3532
f866fc42
CH		 3533static void nvme_async_event_work(struct work_struct *work)
3534{
3535 struct nvme_ctrl *ctrl =
3536 container_of(work, struct nvme_ctrl, async_event_work);
3537
e3d7874d 3538 nvme_aen_uevent(ctrl);
ad22c355 3539 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 3540}
3541
b6dccf7f
AD		 3542static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
3543{
3544
3545 u32 csts;
3546
3547 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
3548 return false;
3549
3550 if (csts == ~0)
3551 return false;
3552
3553 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
3554}
3555
3556static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
3557{
b6dccf7f
AD		 3558 struct nvme_fw_slot_info_log *log;
3559
3560 log = kmalloc(sizeof(*log), GFP_KERNEL);
3561 if (!log)
3562 return;
3563
0e98719b
CH		 3564 if (nvme_get_log(ctrl, NVME_NSID_ALL, 0, NVME_LOG_FW_SLOT, log,
3565 sizeof(*log), 0))
3566 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
b6dccf7f
AD		 3567 kfree(log);
3568}
3569
3570static void nvme_fw_act_work(struct work_struct *work)
3571{
3572 struct nvme_ctrl *ctrl = container_of(work,
3573 struct nvme_ctrl, fw_act_work);
3574 unsigned long fw_act_timeout;
3575
3576 if (ctrl->mtfa)
3577 fw_act_timeout = jiffies +
3578 msecs_to_jiffies(ctrl->mtfa * 100);
3579 else
3580 fw_act_timeout = jiffies +
3581 msecs_to_jiffies(admin_timeout * 1000);
3582
3583 nvme_stop_queues(ctrl);
3584 while (nvme_ctrl_pp_status(ctrl)) {
3585 if (time_after(jiffies, fw_act_timeout)) {
3586 dev_warn(ctrl->device,
3587 "Fw activation timeout, reset controller\n");
3588 nvme_reset_ctrl(ctrl);
3589 break;
3590 }
3591 msleep(100);
3592 }
3593
3594 if (ctrl->state != NVME_CTRL_LIVE)
3595 return;
3596
3597 nvme_start_queues(ctrl);
a806c6c8 3598 /* read FW slot information to clear the AER */
b6dccf7f
AD		 3599 nvme_get_fw_slot_info(ctrl);
3600}
3601
868c2392
CH		 3602static void nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
3603{
09bd1ff4
CK		 3604 u32 aer_notice_type = (result & 0xff00) >> 8;
3605
3606 switch (aer_notice_type) {
868c2392 3607 case NVME_AER_NOTICE_NS_CHANGED:
09bd1ff4 3608 trace_nvme_async_event(ctrl, aer_notice_type);
77016199 3609 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 3610 nvme_queue_scan(ctrl);
3611 break;
3612 case NVME_AER_NOTICE_FW_ACT_STARTING:
09bd1ff4 3613 trace_nvme_async_event(ctrl, aer_notice_type);
868c2392
CH		 3614 queue_work(nvme_wq, &ctrl->fw_act_work);
3615 break;
0d0b660f
CH		 3616#ifdef CONFIG_NVME_MULTIPATH
3617 case NVME_AER_NOTICE_ANA:
09bd1ff4 3618 trace_nvme_async_event(ctrl, aer_notice_type);
0d0b660f
CH		 3619 if (!ctrl->ana_log_buf)
3620 break;
3621 queue_work(nvme_wq, &ctrl->ana_work);
3622 break;
3623#endif
868c2392
CH		 3624 default:
3625 dev_warn(ctrl->device, "async event result %08x\n", result);
3626 }
3627}
3628
7bf58533 3629void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 3630 volatile union nvme_result *res)
f866fc42 3631{
7bf58533 3632 u32 result = le32_to_cpu(res->u32);
09bd1ff4 3633 u32 aer_type = result & 0x07;
f866fc42 3634
ad22c355 3635 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 3636 return;
3637
09bd1ff4 3638 switch (aer_type) {
868c2392
CH		 3639 case NVME_AER_NOTICE:
3640 nvme_handle_aen_notice(ctrl, result);
3641 break;
e3d7874d
KB		 3642 case NVME_AER_ERROR:
3643 case NVME_AER_SMART:
3644 case NVME_AER_CSS:
3645 case NVME_AER_VS:
09bd1ff4 3646 trace_nvme_async_event(ctrl, aer_type);
e3d7874d 3647 ctrl->aen_result = result;
7bf58533
CH		 3648 break;
3649 default:
3650 break;
f866fc42 3651 }
c669ccdc 3652 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 3653}
f866fc42 3654EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 3655
d09f2b45 3656void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 3657{
0d0b660f 3658 nvme_mpath_stop(ctrl);
d09f2b45 3659 nvme_stop_keep_alive(ctrl);
f866fc42 3660 flush_work(&ctrl->async_event_work);
b6dccf7f 3661 cancel_work_sync(&ctrl->fw_act_work);
d09f2b45
SG		 3662}
3663EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
3664
3665void nvme_start_ctrl(struct nvme_ctrl *ctrl)
3666{
3667 if (ctrl->kato)
3668 nvme_start_keep_alive(ctrl);
3669
3670 if (ctrl->queue_count > 1) {
3671 nvme_queue_scan(ctrl);
c0561f82 3672 nvme_enable_aen(ctrl);
d99ca609 3673 queue_work(nvme_wq, &ctrl->async_event_work);
d09f2b45
SG		 3674 nvme_start_queues(ctrl);
3675 }
3676}
3677EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 3678
d09f2b45
SG		 3679void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
3680{
a6a5149b 3681 cdev_device_del(&ctrl->cdev, ctrl->device);
53029b04 3682}
576d55d6 3683EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 3684
d22524a4 3685static void nvme_free_ctrl(struct device *dev)
53029b04 3686{
d22524a4
CH		 3687 struct nvme_ctrl *ctrl =
3688 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 3689 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 3690
9843f685 3691 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
84fef62d 3692 kfree(ctrl->effects);
0d0b660f 3693 nvme_mpath_uninit(ctrl);
092ff052 3694 __free_page(ctrl->discard_page);
f3ca80fc 3695
ab9e00cc
CH		 3696 if (subsys) {
3697 mutex_lock(&subsys->lock);
3698 list_del(&ctrl->subsys_entry);
3699 mutex_unlock(&subsys->lock);
3700 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
3701 }
f3ca80fc
CH		 3702
3703 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 3704
ab9e00cc
CH		 3705 if (subsys)
3706 nvme_put_subsystem(subsys);
f3ca80fc
CH		 3707}
3708
3709/*
3710 * Initialize a NVMe controller structures. This needs to be called during
3711 * earliest initialization so that we have the initialized structured around
3712 * during probing.
3713 */
3714int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
3715 const struct nvme_ctrl_ops *ops, unsigned long quirks)
3716{
3717 int ret;
3718
bb8d261e
CH		 3719 ctrl->state = NVME_CTRL_NEW;
3720 spin_lock_init(&ctrl->lock);
e7ad43c3 3721 mutex_init(&ctrl->scan_lock);
f3ca80fc 3722 INIT_LIST_HEAD(&ctrl->namespaces);
765cc031 3723 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 3724 ctrl->dev = dev;
3725 ctrl->ops = ops;
3726 ctrl->quirks = quirks;
5955be21 3727 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 3728 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 3729 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 3730 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
f3ca80fc 3731
230f1f9e
JS		 3732 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
3733 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
3734 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
3735
cb5b7262
JA		 3736 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
3737 PAGE_SIZE);
3738 ctrl->discard_page = alloc_page(GFP_KERNEL);
3739 if (!ctrl->discard_page) {
3740 ret = -ENOMEM;
3741 goto out;
3742 }
3743
9843f685
CH		 3744 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
3745 if (ret < 0)
f3ca80fc 3746 goto out;
9843f685 3747 ctrl->instance = ret;
f3ca80fc 3748
d22524a4
CH		 3749 device_initialize(&ctrl->ctrl_device);
3750 ctrl->device = &ctrl->ctrl_device;
a6a5149b 3751 ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
d22524a4
CH		 3752 ctrl->device->class = nvme_class;
3753 ctrl->device->parent = ctrl->dev;
3754 ctrl->device->groups = nvme_dev_attr_groups;
3755 ctrl->device->release = nvme_free_ctrl;
3756 dev_set_drvdata(ctrl->device, ctrl);
3757 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
3758 if (ret)
f3ca80fc 3759 goto out_release_instance;
f3ca80fc 3760
a6a5149b
CH		 3761 cdev_init(&ctrl->cdev, &nvme_dev_fops);
3762 ctrl->cdev.owner = ops->module;
3763 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 3764 if (ret)
3765 goto out_free_name;
f3ca80fc 3766
c5552fde
AL		 3767 /*
3768 * Initialize latency tolerance controls. The sysfs files won't
3769 * be visible to userspace unless the device actually supports APST.
3770 */
3771 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
3772 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
3773 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
3774
f3ca80fc 3775 return 0;
d22524a4 3776out_free_name:
d6a2b953 3777 kfree_const(ctrl->device->kobj.name);
f3ca80fc 3778out_release_instance:
9843f685 3779 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc 3780out:
cb5b7262
JA		 3781 if (ctrl->discard_page)
3782 __free_page(ctrl->discard_page);
f3ca80fc
CH		 3783 return ret;
3784}
576d55d6 3785EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 3786
69d9a99c
KB		 3787/**
3788 * nvme_kill_queues(): Ends all namespace queues
3789 * @ctrl: the dead controller that needs to end
3790 *
3791 * Call this function when the driver determines it is unable to get the
3792 * controller in a state capable of servicing IO.
3793 */
3794void nvme_kill_queues(struct nvme_ctrl *ctrl)
3795{
3796 struct nvme_ns *ns;
3797
765cc031 3798 down_read(&ctrl->namespaces_rwsem);
82654b6b 3799
443bd90f 3800 /* Forcibly unquiesce queues to avoid blocking dispatch */
751a0cc0 3801 if (ctrl->admin_q && !blk_queue_dying(ctrl->admin_q))
7dd1ab16 3802 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 3803
cf39a6bc
SB		 3804 list_for_each_entry(ns, &ctrl->namespaces, list)
3805 nvme_set_queue_dying(ns);
806f026f 3806
765cc031 3807 up_read(&ctrl->namespaces_rwsem);
69d9a99c 3808}
237045fc 3809EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 3810
302ad8cc
KB		 3811void nvme_unfreeze(struct nvme_ctrl *ctrl)
3812{
3813 struct nvme_ns *ns;
3814
765cc031 3815 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3816 list_for_each_entry(ns, &ctrl->namespaces, list)
3817 blk_mq_unfreeze_queue(ns->queue);
765cc031 3818 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3819}
3820EXPORT_SYMBOL_GPL(nvme_unfreeze);
3821
3822void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
3823{
3824 struct nvme_ns *ns;
3825
765cc031 3826 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3827 list_for_each_entry(ns, &ctrl->namespaces, list) {
3828 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
3829 if (timeout <= 0)
3830 break;
3831 }
765cc031 3832 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3833}
3834EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
3835
3836void nvme_wait_freeze(struct nvme_ctrl *ctrl)
3837{
3838 struct nvme_ns *ns;
3839
765cc031 3840 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3841 list_for_each_entry(ns, &ctrl->namespaces, list)
3842 blk_mq_freeze_queue_wait(ns->queue);
765cc031 3843 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3844}
3845EXPORT_SYMBOL_GPL(nvme_wait_freeze);
3846
3847void nvme_start_freeze(struct nvme_ctrl *ctrl)
3848{
3849 struct nvme_ns *ns;
3850
765cc031 3851 down_read(&ctrl->namespaces_rwsem);
302ad8cc 3852 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 3853 blk_freeze_queue_start(ns->queue);
765cc031 3854 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3855}
3856EXPORT_SYMBOL_GPL(nvme_start_freeze);
3857
25646264 3858void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3859{
3860 struct nvme_ns *ns;
3861
765cc031 3862 down_read(&ctrl->namespaces_rwsem);
a6eaa884 3863 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 3864 blk_mq_quiesce_queue(ns->queue);
765cc031 3865 up_read(&ctrl->namespaces_rwsem);
363c9aac 3866}
576d55d6 3867EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 3868
25646264 3869void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3870{
3871 struct nvme_ns *ns;
3872
765cc031 3873 down_read(&ctrl->namespaces_rwsem);
8d7b8faf 3874 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 3875 blk_mq_unquiesce_queue(ns->queue);
765cc031 3876 up_read(&ctrl->namespaces_rwsem);
363c9aac 3877}
576d55d6 3878EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 3879
5bae7f73
CH		 3880int __init nvme_core_init(void)
3881{
b227c59b 3882 int result = -ENOMEM;
5bae7f73 3883
9a6327d2
SG		 3884 nvme_wq = alloc_workqueue("nvme-wq",
3885 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3886 if (!nvme_wq)
b227c59b
RS		 3887 goto out;
3888
3889 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
3890 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3891 if (!nvme_reset_wq)
3892 goto destroy_wq;
3893
3894 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
3895 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3896 if (!nvme_delete_wq)
3897 goto destroy_reset_wq;
9a6327d2 3898
a6a5149b 3899 result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
f3ca80fc 3900 if (result < 0)
b227c59b 3901 goto destroy_delete_wq;
f3ca80fc
CH		 3902
3903 nvme_class = class_create(THIS_MODULE, "nvme");
3904 if (IS_ERR(nvme_class)) {
3905 result = PTR_ERR(nvme_class);
3906 goto unregister_chrdev;
3907 }
3908
ab9e00cc
CH		 3909 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
3910 if (IS_ERR(nvme_subsys_class)) {
3911 result = PTR_ERR(nvme_subsys_class);
3912 goto destroy_class;
3913 }
5bae7f73 3914 return 0;
f3ca80fc 3915
ab9e00cc
CH		 3916destroy_class:
3917 class_destroy(nvme_class);
9a6327d2 3918unregister_chrdev:
a6a5149b 3919 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3920destroy_delete_wq:
3921 destroy_workqueue(nvme_delete_wq);
3922destroy_reset_wq:
3923 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 3924destroy_wq:
3925 destroy_workqueue(nvme_wq);
b227c59b 3926out:
f3ca80fc 3927 return result;
5bae7f73
CH		 3928}
3929
8eb5d89f 3930void __exit nvme_core_exit(void)
5bae7f73 3931{
ab9e00cc
CH		 3932 ida_destroy(&nvme_subsystems_ida);
3933 class_destroy(nvme_subsys_class);
f3ca80fc 3934 class_destroy(nvme_class);
a6a5149b 3935 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3936 destroy_workqueue(nvme_delete_wq);
3937 destroy_workqueue(nvme_reset_wq);
9a6327d2 3938 destroy_workqueue(nvme_wq);
5bae7f73 3939}
576d55d6
ML		 3940
3941MODULE_LICENSE("GPL");
3942MODULE_VERSION("1.0");
3943module_init(nvme_core_init);
3944module_exit(nvme_core_exit);
Linux 6.x block layer and io_uring tree(s)