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bc50ad75 | 1 | // SPDX-License-Identifier: GPL-2.0 |
21d34711 CH |
2 | /* |
3 | * NVM Express device driver | |
4 | * Copyright (c) 2011-2014, Intel Corporation. | |
21d34711 CH |
5 | */ |
6 | ||
7 | #include <linux/blkdev.h> | |
8 | #include <linux/blk-mq.h> | |
fe45e630 | 9 | #include <linux/blk-integrity.h> |
c95b708d | 10 | #include <linux/compat.h> |
5fd4ce1b | 11 | #include <linux/delay.h> |
21d34711 | 12 | #include <linux/errno.h> |
1673f1f0 | 13 | #include <linux/hdreg.h> |
21d34711 | 14 | #include <linux/kernel.h> |
5bae7f73 | 15 | #include <linux/module.h> |
958f2a0f | 16 | #include <linux/backing-dev.h> |
21d34711 CH |
17 | #include <linux/slab.h> |
18 | #include <linux/types.h> | |
1673f1f0 CH |
19 | #include <linux/pr.h> |
20 | #include <linux/ptrace.h> | |
21 | #include <linux/nvme_ioctl.h> | |
c5552fde | 22 | #include <linux/pm_qos.h> |
a1a825ab | 23 | #include <linux/ratelimit.h> |
1673f1f0 | 24 | #include <asm/unaligned.h> |
21d34711 CH |
25 | |
26 | #include "nvme.h" | |
038bd4cb | 27 | #include "fabrics.h" |
f50fff73 | 28 | #include <linux/nvme-auth.h> |
21d34711 | 29 | |
35fe0d12 HR |
30 | #define CREATE_TRACE_POINTS |
31 | #include "trace.h" | |
32 | ||
f3ca80fc CH |
33 | #define NVME_MINORS (1U << MINORBITS) |
34 | ||
1a893c2b CH |
35 | struct nvme_ns_info { |
36 | struct nvme_ns_ids ids; | |
37 | u32 nsid; | |
38 | __le32 anagrpid; | |
39 | bool is_shared; | |
1e4ea66a | 40 | bool is_readonly; |
1a893c2b | 41 | bool is_ready; |
0dd6fff2 | 42 | bool is_removed; |
1a893c2b CH |
43 | }; |
44 | ||
8ae4e447 MO |
45 | unsigned int admin_timeout = 60; |
46 | module_param(admin_timeout, uint, 0644); | |
ba0ba7d3 | 47 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); |
576d55d6 | 48 | EXPORT_SYMBOL_GPL(admin_timeout); |
ba0ba7d3 | 49 | |
8ae4e447 MO |
50 | unsigned int nvme_io_timeout = 30; |
51 | module_param_named(io_timeout, nvme_io_timeout, uint, 0644); | |
ba0ba7d3 | 52 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
576d55d6 | 53 | EXPORT_SYMBOL_GPL(nvme_io_timeout); |
ba0ba7d3 | 54 | |
b3b1b0b0 | 55 | static unsigned char shutdown_timeout = 5; |
ba0ba7d3 ML |
56 | module_param(shutdown_timeout, byte, 0644); |
57 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
58 | ||
44e44b29 CH |
59 | static u8 nvme_max_retries = 5; |
60 | module_param_named(max_retries, nvme_max_retries, byte, 0644); | |
f80ec966 | 61 | MODULE_PARM_DESC(max_retries, "max number of retries a command may have"); |
5bae7f73 | 62 | |
9947d6a0 | 63 | static unsigned long default_ps_max_latency_us = 100000; |
c5552fde AL |
64 | module_param(default_ps_max_latency_us, ulong, 0644); |
65 | MODULE_PARM_DESC(default_ps_max_latency_us, | |
66 | "max power saving latency for new devices; use PM QOS to change per device"); | |
67 | ||
c35e30b4 AL |
68 | static bool force_apst; |
69 | module_param(force_apst, bool, 0644); | |
70 | MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off"); | |
71 | ||
ebd8a93a AB |
72 | static unsigned long apst_primary_timeout_ms = 100; |
73 | module_param(apst_primary_timeout_ms, ulong, 0644); | |
74 | MODULE_PARM_DESC(apst_primary_timeout_ms, | |
75 | "primary APST timeout in ms"); | |
76 | ||
77 | static unsigned long apst_secondary_timeout_ms = 2000; | |
78 | module_param(apst_secondary_timeout_ms, ulong, 0644); | |
79 | MODULE_PARM_DESC(apst_secondary_timeout_ms, | |
80 | "secondary APST timeout in ms"); | |
81 | ||
82 | static unsigned long apst_primary_latency_tol_us = 15000; | |
83 | module_param(apst_primary_latency_tol_us, ulong, 0644); | |
84 | MODULE_PARM_DESC(apst_primary_latency_tol_us, | |
85 | "primary APST latency tolerance in us"); | |
86 | ||
87 | static unsigned long apst_secondary_latency_tol_us = 100000; | |
88 | module_param(apst_secondary_latency_tol_us, ulong, 0644); | |
89 | MODULE_PARM_DESC(apst_secondary_latency_tol_us, | |
90 | "secondary APST latency tolerance in us"); | |
91 | ||
b227c59b RS |
92 | /* |
93 | * nvme_wq - hosts nvme related works that are not reset or delete | |
94 | * nvme_reset_wq - hosts nvme reset works | |
95 | * nvme_delete_wq - hosts nvme delete works | |
96 | * | |
97b2512a NK |
97 | * nvme_wq will host works such as scan, aen handling, fw activation, |
98 | * keep-alive, periodic reconnects etc. nvme_reset_wq | |
b227c59b RS |
99 | * runs reset works which also flush works hosted on nvme_wq for |
100 | * serialization purposes. nvme_delete_wq host controller deletion | |
101 | * works which flush reset works for serialization. | |
102 | */ | |
9a6327d2 SG |
103 | struct workqueue_struct *nvme_wq; |
104 | EXPORT_SYMBOL_GPL(nvme_wq); | |
105 | ||
b227c59b RS |
106 | struct workqueue_struct *nvme_reset_wq; |
107 | EXPORT_SYMBOL_GPL(nvme_reset_wq); | |
108 | ||
109 | struct workqueue_struct *nvme_delete_wq; | |
110 | EXPORT_SYMBOL_GPL(nvme_delete_wq); | |
111 | ||
ab9e00cc CH |
112 | static LIST_HEAD(nvme_subsystems); |
113 | static DEFINE_MUTEX(nvme_subsystems_lock); | |
1673f1f0 | 114 | |
9843f685 | 115 | static DEFINE_IDA(nvme_instance_ida); |
f68abd9c | 116 | static dev_t nvme_ctrl_base_chr_devt; |
f3ca80fc | 117 | static struct class *nvme_class; |
ab9e00cc | 118 | static struct class *nvme_subsys_class; |
f3ca80fc | 119 | |
2637baed MI |
120 | static DEFINE_IDA(nvme_ns_chr_minor_ida); |
121 | static dev_t nvme_ns_chr_devt; | |
122 | static struct class *nvme_ns_chr_class; | |
123 | ||
12d9f070 | 124 | static void nvme_put_subsystem(struct nvme_subsystem *subsys); |
cf39a6bc SB |
125 | static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl, |
126 | unsigned nsid); | |
b58da2d2 TS |
127 | static void nvme_update_keep_alive(struct nvme_ctrl *ctrl, |
128 | struct nvme_command *cmd); | |
cf39a6bc | 129 | |
2405252a | 130 | void nvme_queue_scan(struct nvme_ctrl *ctrl) |
50e8d8ee CH |
131 | { |
132 | /* | |
133 | * Only new queue scan work when admin and IO queues are both alive | |
134 | */ | |
e6e7f7ac | 135 | if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE && ctrl->tagset) |
50e8d8ee CH |
136 | queue_work(nvme_wq, &ctrl->scan_work); |
137 | } | |
138 | ||
4c75f877 KB |
139 | /* |
140 | * Use this function to proceed with scheduling reset_work for a controller | |
141 | * that had previously been set to the resetting state. This is intended for | |
142 | * code paths that can't be interrupted by other reset attempts. A hot removal | |
143 | * may prevent this from succeeding. | |
144 | */ | |
c1ac9a4b | 145 | int nvme_try_sched_reset(struct nvme_ctrl *ctrl) |
4c75f877 | 146 | { |
e6e7f7ac | 147 | if (nvme_ctrl_state(ctrl) != NVME_CTRL_RESETTING) |
4c75f877 KB |
148 | return -EBUSY; |
149 | if (!queue_work(nvme_reset_wq, &ctrl->reset_work)) | |
150 | return -EBUSY; | |
151 | return 0; | |
152 | } | |
c1ac9a4b | 153 | EXPORT_SYMBOL_GPL(nvme_try_sched_reset); |
4c75f877 | 154 | |
8c4dfea9 VG |
155 | static void nvme_failfast_work(struct work_struct *work) |
156 | { | |
157 | struct nvme_ctrl *ctrl = container_of(to_delayed_work(work), | |
158 | struct nvme_ctrl, failfast_work); | |
159 | ||
e6e7f7ac | 160 | if (nvme_ctrl_state(ctrl) != NVME_CTRL_CONNECTING) |
8c4dfea9 VG |
161 | return; |
162 | ||
163 | set_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); | |
164 | dev_info(ctrl->device, "failfast expired\n"); | |
165 | nvme_kick_requeue_lists(ctrl); | |
166 | } | |
167 | ||
168 | static inline void nvme_start_failfast_work(struct nvme_ctrl *ctrl) | |
169 | { | |
170 | if (!ctrl->opts || ctrl->opts->fast_io_fail_tmo == -1) | |
171 | return; | |
172 | ||
173 | schedule_delayed_work(&ctrl->failfast_work, | |
174 | ctrl->opts->fast_io_fail_tmo * HZ); | |
175 | } | |
176 | ||
177 | static inline void nvme_stop_failfast_work(struct nvme_ctrl *ctrl) | |
178 | { | |
179 | if (!ctrl->opts) | |
180 | return; | |
181 | ||
182 | cancel_delayed_work_sync(&ctrl->failfast_work); | |
183 | clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); | |
184 | } | |
185 | ||
186 | ||
d86c4d8e CH |
187 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl) |
188 | { | |
189 | if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) | |
190 | return -EBUSY; | |
b227c59b | 191 | if (!queue_work(nvme_reset_wq, &ctrl->reset_work)) |
d86c4d8e CH |
192 | return -EBUSY; |
193 | return 0; | |
194 | } | |
195 | EXPORT_SYMBOL_GPL(nvme_reset_ctrl); | |
196 | ||
2405252a | 197 | int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl) |
d86c4d8e CH |
198 | { |
199 | int ret; | |
200 | ||
201 | ret = nvme_reset_ctrl(ctrl); | |
8000d1fd | 202 | if (!ret) { |
d86c4d8e | 203 | flush_work(&ctrl->reset_work); |
e6e7f7ac | 204 | if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE) |
8000d1fd NC |
205 | ret = -ENETRESET; |
206 | } | |
207 | ||
d86c4d8e CH |
208 | return ret; |
209 | } | |
210 | ||
a686ed75 | 211 | static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl) |
c5017e85 | 212 | { |
77d0612d | 213 | dev_info(ctrl->device, |
e5ea42fa | 214 | "Removing ctrl: NQN \"%s\"\n", nvmf_ctrl_subsysnqn(ctrl)); |
77d0612d | 215 | |
4054637c | 216 | flush_work(&ctrl->reset_work); |
6cd53d14 CH |
217 | nvme_stop_ctrl(ctrl); |
218 | nvme_remove_namespaces(ctrl); | |
c5017e85 | 219 | ctrl->ops->delete_ctrl(ctrl); |
6cd53d14 | 220 | nvme_uninit_ctrl(ctrl); |
c5017e85 CH |
221 | } |
222 | ||
a686ed75 BVA |
223 | static void nvme_delete_ctrl_work(struct work_struct *work) |
224 | { | |
225 | struct nvme_ctrl *ctrl = | |
226 | container_of(work, struct nvme_ctrl, delete_work); | |
227 | ||
228 | nvme_do_delete_ctrl(ctrl); | |
229 | } | |
230 | ||
c5017e85 CH |
231 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl) |
232 | { | |
233 | if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING)) | |
234 | return -EBUSY; | |
b227c59b | 235 | if (!queue_work(nvme_delete_wq, &ctrl->delete_work)) |
c5017e85 CH |
236 | return -EBUSY; |
237 | return 0; | |
238 | } | |
239 | EXPORT_SYMBOL_GPL(nvme_delete_ctrl); | |
240 | ||
942e21c0 | 241 | void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl) |
c5017e85 | 242 | { |
c5017e85 | 243 | /* |
01fc08ff YY |
244 | * Keep a reference until nvme_do_delete_ctrl() complete, |
245 | * since ->delete_ctrl can free the controller. | |
c5017e85 CH |
246 | */ |
247 | nvme_get_ctrl(ctrl); | |
6721c18a | 248 | if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING)) |
b9c77583 | 249 | nvme_do_delete_ctrl(ctrl); |
c5017e85 | 250 | nvme_put_ctrl(ctrl); |
c5017e85 | 251 | } |
c5017e85 | 252 | |
2f9c1736 | 253 | static blk_status_t nvme_error_status(u16 status) |
27fa9bc5 | 254 | { |
2f9c1736 | 255 | switch (status & 0x7ff) { |
27fa9bc5 | 256 | case NVME_SC_SUCCESS: |
2a842aca | 257 | return BLK_STS_OK; |
27fa9bc5 | 258 | case NVME_SC_CAP_EXCEEDED: |
2a842aca | 259 | return BLK_STS_NOSPC; |
e96fef2c | 260 | case NVME_SC_LBA_RANGE: |
35038bff KB |
261 | case NVME_SC_CMD_INTERRUPTED: |
262 | case NVME_SC_NS_NOT_READY: | |
e96fef2c KB |
263 | return BLK_STS_TARGET; |
264 | case NVME_SC_BAD_ATTRIBUTES: | |
e02ab023 | 265 | case NVME_SC_ONCS_NOT_SUPPORTED: |
e96fef2c KB |
266 | case NVME_SC_INVALID_OPCODE: |
267 | case NVME_SC_INVALID_FIELD: | |
268 | case NVME_SC_INVALID_NS: | |
2a842aca | 269 | return BLK_STS_NOTSUPP; |
e02ab023 JG |
270 | case NVME_SC_WRITE_FAULT: |
271 | case NVME_SC_READ_ERROR: | |
272 | case NVME_SC_UNWRITTEN_BLOCK: | |
a751da33 CH |
273 | case NVME_SC_ACCESS_DENIED: |
274 | case NVME_SC_READ_ONLY: | |
e96fef2c | 275 | case NVME_SC_COMPARE_FAILED: |
2a842aca | 276 | return BLK_STS_MEDIUM; |
a751da33 CH |
277 | case NVME_SC_GUARD_CHECK: |
278 | case NVME_SC_APPTAG_CHECK: | |
279 | case NVME_SC_REFTAG_CHECK: | |
280 | case NVME_SC_INVALID_PI: | |
281 | return BLK_STS_PROTECTION; | |
282 | case NVME_SC_RESERVATION_CONFLICT: | |
7ba15083 | 283 | return BLK_STS_RESV_CONFLICT; |
1c0d12c0 SG |
284 | case NVME_SC_HOST_PATH_ERROR: |
285 | return BLK_STS_TRANSPORT; | |
afaf5c6c KB |
286 | case NVME_SC_ZONE_TOO_MANY_ACTIVE: |
287 | return BLK_STS_ZONE_ACTIVE_RESOURCE; | |
288 | case NVME_SC_ZONE_TOO_MANY_OPEN: | |
289 | return BLK_STS_ZONE_OPEN_RESOURCE; | |
2a842aca CH |
290 | default: |
291 | return BLK_STS_IOERR; | |
27fa9bc5 CH |
292 | } |
293 | } | |
27fa9bc5 | 294 | |
49cd84b6 KB |
295 | static void nvme_retry_req(struct request *req) |
296 | { | |
49cd84b6 KB |
297 | unsigned long delay = 0; |
298 | u16 crd; | |
299 | ||
300 | /* The mask and shift result must be <= 3 */ | |
301 | crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11; | |
f9063a53 MI |
302 | if (crd) |
303 | delay = nvme_req(req)->ctrl->crdt[crd - 1] * 100; | |
49cd84b6 KB |
304 | |
305 | nvme_req(req)->retries++; | |
306 | blk_mq_requeue_request(req, false); | |
307 | blk_mq_delay_kick_requeue_list(req->q, delay); | |
308 | } | |
309 | ||
bd83fe6f AA |
310 | static void nvme_log_error(struct request *req) |
311 | { | |
312 | struct nvme_ns *ns = req->q->queuedata; | |
313 | struct nvme_request *nr = nvme_req(req); | |
314 | ||
315 | if (ns) { | |
9419e71b | 316 | pr_err_ratelimited("%s: %s(0x%x) @ LBA %llu, %u blocks, %s (sct 0x%x / sc 0x%x) %s%s\n", |
bd83fe6f AA |
317 | ns->disk ? ns->disk->disk_name : "?", |
318 | nvme_get_opcode_str(nr->cmd->common.opcode), | |
319 | nr->cmd->common.opcode, | |
0372dd4e | 320 | nvme_sect_to_lba(ns->head, blk_rq_pos(req)), |
9419e71b | 321 | blk_rq_bytes(req) >> ns->head->lba_shift, |
bd83fe6f AA |
322 | nvme_get_error_status_str(nr->status), |
323 | nr->status >> 8 & 7, /* Status Code Type */ | |
324 | nr->status & 0xff, /* Status Code */ | |
325 | nr->status & NVME_SC_MORE ? "MORE " : "", | |
326 | nr->status & NVME_SC_DNR ? "DNR " : ""); | |
327 | return; | |
328 | } | |
329 | ||
330 | pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s\n", | |
331 | dev_name(nr->ctrl->device), | |
332 | nvme_get_admin_opcode_str(nr->cmd->common.opcode), | |
333 | nr->cmd->common.opcode, | |
334 | nvme_get_error_status_str(nr->status), | |
335 | nr->status >> 8 & 7, /* Status Code Type */ | |
336 | nr->status & 0xff, /* Status Code */ | |
337 | nr->status & NVME_SC_MORE ? "MORE " : "", | |
338 | nr->status & NVME_SC_DNR ? "DNR " : ""); | |
339 | } | |
340 | ||
9f079dda AA |
341 | static void nvme_log_err_passthru(struct request *req) |
342 | { | |
343 | struct nvme_ns *ns = req->q->queuedata; | |
344 | struct nvme_request *nr = nvme_req(req); | |
345 | ||
346 | pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s" | |
347 | "cdw10=0x%x cdw11=0x%x cdw12=0x%x cdw13=0x%x cdw14=0x%x cdw15=0x%x\n", | |
348 | ns ? ns->disk->disk_name : dev_name(nr->ctrl->device), | |
349 | ns ? nvme_get_opcode_str(nr->cmd->common.opcode) : | |
350 | nvme_get_admin_opcode_str(nr->cmd->common.opcode), | |
351 | nr->cmd->common.opcode, | |
352 | nvme_get_error_status_str(nr->status), | |
353 | nr->status >> 8 & 7, /* Status Code Type */ | |
354 | nr->status & 0xff, /* Status Code */ | |
355 | nr->status & NVME_SC_MORE ? "MORE " : "", | |
356 | nr->status & NVME_SC_DNR ? "DNR " : "", | |
357 | nr->cmd->common.cdw10, | |
358 | nr->cmd->common.cdw11, | |
359 | nr->cmd->common.cdw12, | |
360 | nr->cmd->common.cdw13, | |
361 | nr->cmd->common.cdw14, | |
362 | nr->cmd->common.cdw14); | |
363 | } | |
364 | ||
5ddaabe8 CH |
365 | enum nvme_disposition { |
366 | COMPLETE, | |
367 | RETRY, | |
368 | FAILOVER, | |
f50fff73 | 369 | AUTHENTICATE, |
5ddaabe8 CH |
370 | }; |
371 | ||
372 | static inline enum nvme_disposition nvme_decide_disposition(struct request *req) | |
77f02a7a | 373 | { |
5ddaabe8 CH |
374 | if (likely(nvme_req(req)->status == 0)) |
375 | return COMPLETE; | |
908e4564 | 376 | |
f50fff73 HR |
377 | if ((nvme_req(req)->status & 0x7ff) == NVME_SC_AUTH_REQUIRED) |
378 | return AUTHENTICATE; | |
379 | ||
5ddaabe8 CH |
380 | if (blk_noretry_request(req) || |
381 | (nvme_req(req)->status & NVME_SC_DNR) || | |
382 | nvme_req(req)->retries >= nvme_max_retries) | |
383 | return COMPLETE; | |
ca5554a6 | 384 | |
5ddaabe8 | 385 | if (req->cmd_flags & REQ_NVME_MPATH) { |
5eac5f33 CL |
386 | if (nvme_is_path_error(nvme_req(req)->status) || |
387 | blk_queue_dying(req->q)) | |
5ddaabe8 | 388 | return FAILOVER; |
5eac5f33 CL |
389 | } else { |
390 | if (blk_queue_dying(req->q)) | |
391 | return COMPLETE; | |
5ddaabe8 | 392 | } |
16686f3a | 393 | |
5ddaabe8 CH |
394 | return RETRY; |
395 | } | |
6e3ca03e | 396 | |
c234a653 | 397 | static inline void nvme_end_req_zoned(struct request *req) |
5ddaabe8 | 398 | { |
5ddaabe8 | 399 | if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) && |
0372dd4e DW |
400 | req_op(req) == REQ_OP_ZONE_APPEND) { |
401 | struct nvme_ns *ns = req->q->queuedata; | |
402 | ||
403 | req->__sector = nvme_lba_to_sect(ns->head, | |
240e6ee2 | 404 | le64_to_cpu(nvme_req(req)->result.u64)); |
0372dd4e | 405 | } |
c234a653 JA |
406 | } |
407 | ||
408 | static inline void nvme_end_req(struct request *req) | |
409 | { | |
410 | blk_status_t status = nvme_error_status(nvme_req(req)->status); | |
35fe0d12 | 411 | |
9f079dda AA |
412 | if (unlikely(nvme_req(req)->status && !(req->rq_flags & RQF_QUIET))) { |
413 | if (blk_rq_is_passthrough(req)) | |
414 | nvme_log_err_passthru(req); | |
415 | else | |
416 | nvme_log_error(req); | |
417 | } | |
c234a653 | 418 | nvme_end_req_zoned(req); |
2b59787a | 419 | nvme_trace_bio_complete(req); |
d4d957b5 SG |
420 | if (req->cmd_flags & REQ_NVME_MPATH) |
421 | nvme_mpath_end_request(req); | |
908e4564 | 422 | blk_mq_end_request(req, status); |
77f02a7a | 423 | } |
5ddaabe8 CH |
424 | |
425 | void nvme_complete_rq(struct request *req) | |
426 | { | |
f50fff73 HR |
427 | struct nvme_ctrl *ctrl = nvme_req(req)->ctrl; |
428 | ||
5ddaabe8 CH |
429 | trace_nvme_complete_rq(req); |
430 | nvme_cleanup_cmd(req); | |
431 | ||
774a9636 US |
432 | /* |
433 | * Completions of long-running commands should not be able to | |
434 | * defer sending of periodic keep alives, since the controller | |
435 | * may have completed processing such commands a long time ago | |
436 | * (arbitrarily close to command submission time). | |
437 | * req->deadline - req->timeout is the command submission time | |
438 | * in jiffies. | |
439 | */ | |
440 | if (ctrl->kas && | |
441 | req->deadline - req->timeout >= ctrl->ka_last_check_time) | |
f50fff73 | 442 | ctrl->comp_seen = true; |
5ddaabe8 CH |
443 | |
444 | switch (nvme_decide_disposition(req)) { | |
445 | case COMPLETE: | |
446 | nvme_end_req(req); | |
447 | return; | |
448 | case RETRY: | |
449 | nvme_retry_req(req); | |
450 | return; | |
451 | case FAILOVER: | |
452 | nvme_failover_req(req); | |
453 | return; | |
f50fff73 | 454 | case AUTHENTICATE: |
d6800634 | 455 | #ifdef CONFIG_NVME_HOST_AUTH |
f50fff73 HR |
456 | queue_work(nvme_wq, &ctrl->dhchap_auth_work); |
457 | nvme_retry_req(req); | |
458 | #else | |
459 | nvme_end_req(req); | |
460 | #endif | |
461 | return; | |
5ddaabe8 CH |
462 | } |
463 | } | |
77f02a7a CH |
464 | EXPORT_SYMBOL_GPL(nvme_complete_rq); |
465 | ||
c234a653 JA |
466 | void nvme_complete_batch_req(struct request *req) |
467 | { | |
00e757b6 | 468 | trace_nvme_complete_rq(req); |
c234a653 JA |
469 | nvme_cleanup_cmd(req); |
470 | nvme_end_req_zoned(req); | |
471 | } | |
472 | EXPORT_SYMBOL_GPL(nvme_complete_batch_req); | |
473 | ||
dda3248e CL |
474 | /* |
475 | * Called to unwind from ->queue_rq on a failed command submission so that the | |
476 | * multipathing code gets called to potentially failover to another path. | |
477 | * The caller needs to unwind all transport specific resource allocations and | |
478 | * must return propagate the return value. | |
479 | */ | |
480 | blk_status_t nvme_host_path_error(struct request *req) | |
481 | { | |
482 | nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR; | |
483 | blk_mq_set_request_complete(req); | |
484 | nvme_complete_rq(req); | |
485 | return BLK_STS_OK; | |
486 | } | |
487 | EXPORT_SYMBOL_GPL(nvme_host_path_error); | |
488 | ||
2dd6532e | 489 | bool nvme_cancel_request(struct request *req, void *data) |
c55a2fd4 | 490 | { |
c55a2fd4 ML |
491 | dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device, |
492 | "Cancelling I/O %d", req->tag); | |
493 | ||
d4f1d5f7 LY |
494 | /* don't abort one completed or idle request */ |
495 | if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) | |
78ca4072 ML |
496 | return true; |
497 | ||
2dc3947b | 498 | nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD; |
d3589381 | 499 | nvme_req(req)->flags |= NVME_REQ_CANCELLED; |
15f73f5b | 500 | blk_mq_complete_request(req); |
7baa8572 | 501 | return true; |
c55a2fd4 ML |
502 | } |
503 | EXPORT_SYMBOL_GPL(nvme_cancel_request); | |
504 | ||
25479069 CL |
505 | void nvme_cancel_tagset(struct nvme_ctrl *ctrl) |
506 | { | |
507 | if (ctrl->tagset) { | |
508 | blk_mq_tagset_busy_iter(ctrl->tagset, | |
509 | nvme_cancel_request, ctrl); | |
510 | blk_mq_tagset_wait_completed_request(ctrl->tagset); | |
511 | } | |
512 | } | |
513 | EXPORT_SYMBOL_GPL(nvme_cancel_tagset); | |
514 | ||
515 | void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl) | |
516 | { | |
517 | if (ctrl->admin_tagset) { | |
518 | blk_mq_tagset_busy_iter(ctrl->admin_tagset, | |
519 | nvme_cancel_request, ctrl); | |
520 | blk_mq_tagset_wait_completed_request(ctrl->admin_tagset); | |
521 | } | |
522 | } | |
523 | EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset); | |
524 | ||
bb8d261e CH |
525 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
526 | enum nvme_ctrl_state new_state) | |
527 | { | |
f6b6a28e | 528 | enum nvme_ctrl_state old_state; |
0a72bbba | 529 | unsigned long flags; |
bb8d261e CH |
530 | bool changed = false; |
531 | ||
0a72bbba | 532 | spin_lock_irqsave(&ctrl->lock, flags); |
f6b6a28e | 533 | |
e6e7f7ac | 534 | old_state = nvme_ctrl_state(ctrl); |
bb8d261e CH |
535 | switch (new_state) { |
536 | case NVME_CTRL_LIVE: | |
537 | switch (old_state) { | |
7d2e8008 | 538 | case NVME_CTRL_NEW: |
bb8d261e | 539 | case NVME_CTRL_RESETTING: |
ad6a0a52 | 540 | case NVME_CTRL_CONNECTING: |
bb8d261e | 541 | changed = true; |
df561f66 | 542 | fallthrough; |
bb8d261e CH |
543 | default: |
544 | break; | |
545 | } | |
546 | break; | |
547 | case NVME_CTRL_RESETTING: | |
548 | switch (old_state) { | |
549 | case NVME_CTRL_NEW: | |
def61eca | 550 | case NVME_CTRL_LIVE: |
def61eca | 551 | changed = true; |
df561f66 | 552 | fallthrough; |
def61eca CH |
553 | default: |
554 | break; | |
555 | } | |
556 | break; | |
ad6a0a52 | 557 | case NVME_CTRL_CONNECTING: |
def61eca | 558 | switch (old_state) { |
b754a32c | 559 | case NVME_CTRL_NEW: |
3cec7f9d | 560 | case NVME_CTRL_RESETTING: |
bb8d261e | 561 | changed = true; |
df561f66 | 562 | fallthrough; |
bb8d261e CH |
563 | default: |
564 | break; | |
565 | } | |
566 | break; | |
567 | case NVME_CTRL_DELETING: | |
568 | switch (old_state) { | |
569 | case NVME_CTRL_LIVE: | |
570 | case NVME_CTRL_RESETTING: | |
ad6a0a52 | 571 | case NVME_CTRL_CONNECTING: |
bb8d261e | 572 | changed = true; |
df561f66 | 573 | fallthrough; |
bb8d261e CH |
574 | default: |
575 | break; | |
576 | } | |
577 | break; | |
ecca390e SG |
578 | case NVME_CTRL_DELETING_NOIO: |
579 | switch (old_state) { | |
580 | case NVME_CTRL_DELETING: | |
581 | case NVME_CTRL_DEAD: | |
582 | changed = true; | |
df561f66 | 583 | fallthrough; |
ecca390e SG |
584 | default: |
585 | break; | |
586 | } | |
587 | break; | |
0ff9d4e1 KB |
588 | case NVME_CTRL_DEAD: |
589 | switch (old_state) { | |
590 | case NVME_CTRL_DELETING: | |
591 | changed = true; | |
df561f66 | 592 | fallthrough; |
0ff9d4e1 KB |
593 | default: |
594 | break; | |
595 | } | |
596 | break; | |
bb8d261e CH |
597 | default: |
598 | break; | |
599 | } | |
bb8d261e | 600 | |
c1ac9a4b | 601 | if (changed) { |
e6e7f7ac | 602 | WRITE_ONCE(ctrl->state, new_state); |
c1ac9a4b KB |
603 | wake_up_all(&ctrl->state_wq); |
604 | } | |
bb8d261e | 605 | |
0a72bbba | 606 | spin_unlock_irqrestore(&ctrl->lock, flags); |
8c4dfea9 VG |
607 | if (!changed) |
608 | return false; | |
609 | ||
e6e7f7ac | 610 | if (new_state == NVME_CTRL_LIVE) { |
8c4dfea9 VG |
611 | if (old_state == NVME_CTRL_CONNECTING) |
612 | nvme_stop_failfast_work(ctrl); | |
32acab31 | 613 | nvme_kick_requeue_lists(ctrl); |
e6e7f7ac | 614 | } else if (new_state == NVME_CTRL_CONNECTING && |
8c4dfea9 VG |
615 | old_state == NVME_CTRL_RESETTING) { |
616 | nvme_start_failfast_work(ctrl); | |
617 | } | |
bb8d261e CH |
618 | return changed; |
619 | } | |
620 | EXPORT_SYMBOL_GPL(nvme_change_ctrl_state); | |
621 | ||
c1ac9a4b KB |
622 | /* |
623 | * Returns true for sink states that can't ever transition back to live. | |
624 | */ | |
625 | static bool nvme_state_terminal(struct nvme_ctrl *ctrl) | |
626 | { | |
e6e7f7ac | 627 | switch (nvme_ctrl_state(ctrl)) { |
c1ac9a4b KB |
628 | case NVME_CTRL_NEW: |
629 | case NVME_CTRL_LIVE: | |
630 | case NVME_CTRL_RESETTING: | |
631 | case NVME_CTRL_CONNECTING: | |
632 | return false; | |
633 | case NVME_CTRL_DELETING: | |
ecca390e | 634 | case NVME_CTRL_DELETING_NOIO: |
c1ac9a4b KB |
635 | case NVME_CTRL_DEAD: |
636 | return true; | |
637 | default: | |
638 | WARN_ONCE(1, "Unhandled ctrl state:%d", ctrl->state); | |
639 | return true; | |
640 | } | |
641 | } | |
642 | ||
643 | /* | |
644 | * Waits for the controller state to be resetting, or returns false if it is | |
645 | * not possible to ever transition to that state. | |
646 | */ | |
647 | bool nvme_wait_reset(struct nvme_ctrl *ctrl) | |
648 | { | |
649 | wait_event(ctrl->state_wq, | |
650 | nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) || | |
651 | nvme_state_terminal(ctrl)); | |
e6e7f7ac | 652 | return nvme_ctrl_state(ctrl) == NVME_CTRL_RESETTING; |
c1ac9a4b KB |
653 | } |
654 | EXPORT_SYMBOL_GPL(nvme_wait_reset); | |
655 | ||
ed754e5d CH |
656 | static void nvme_free_ns_head(struct kref *ref) |
657 | { | |
658 | struct nvme_ns_head *head = | |
659 | container_of(ref, struct nvme_ns_head, ref); | |
660 | ||
32acab31 | 661 | nvme_mpath_remove_disk(head); |
8b850475 | 662 | ida_free(&head->subsys->ns_ida, head->instance); |
f5ad3991 | 663 | cleanup_srcu_struct(&head->srcu); |
12d9f070 | 664 | nvme_put_subsystem(head->subsys); |
ed754e5d CH |
665 | kfree(head); |
666 | } | |
667 | ||
1496bd49 | 668 | bool nvme_tryget_ns_head(struct nvme_ns_head *head) |
871ca3ef CH |
669 | { |
670 | return kref_get_unless_zero(&head->ref); | |
671 | } | |
672 | ||
1496bd49 | 673 | void nvme_put_ns_head(struct nvme_ns_head *head) |
ed754e5d CH |
674 | { |
675 | kref_put(&head->ref, nvme_free_ns_head); | |
676 | } | |
677 | ||
1673f1f0 CH |
678 | static void nvme_free_ns(struct kref *kref) |
679 | { | |
680 | struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref); | |
681 | ||
1673f1f0 | 682 | put_disk(ns->disk); |
ed754e5d | 683 | nvme_put_ns_head(ns->head); |
075790eb | 684 | nvme_put_ctrl(ns->ctrl); |
1673f1f0 CH |
685 | kfree(ns); |
686 | } | |
687 | ||
4c74d1f8 KJ |
688 | static inline bool nvme_get_ns(struct nvme_ns *ns) |
689 | { | |
690 | return kref_get_unless_zero(&ns->kref); | |
691 | } | |
692 | ||
24493b8b | 693 | void nvme_put_ns(struct nvme_ns *ns) |
1673f1f0 CH |
694 | { |
695 | kref_put(&ns->kref, nvme_free_ns); | |
696 | } | |
24493b8b | 697 | EXPORT_SYMBOL_NS_GPL(nvme_put_ns, NVME_TARGET_PASSTHRU); |
1673f1f0 | 698 | |
bb06ec31 JS |
699 | static inline void nvme_clear_nvme_request(struct request *req) |
700 | { | |
ae5e6886 | 701 | nvme_req(req)->status = 0; |
c03fd85d CK |
702 | nvme_req(req)->retries = 0; |
703 | nvme_req(req)->flags = 0; | |
704 | req->rq_flags |= RQF_DONTPREP; | |
bb06ec31 JS |
705 | } |
706 | ||
e559398f CH |
707 | /* initialize a passthrough request */ |
708 | void nvme_init_request(struct request *req, struct nvme_command *cmd) | |
39dfe844 | 709 | { |
9f079dda AA |
710 | struct nvme_request *nr = nvme_req(req); |
711 | bool logging_enabled; | |
712 | ||
713 | if (req->q->queuedata) { | |
714 | struct nvme_ns *ns = req->q->disk->private_data; | |
715 | ||
716 | logging_enabled = ns->passthru_err_log_enabled; | |
0d2e7c84 | 717 | req->timeout = NVME_IO_TIMEOUT; |
9f079dda AA |
718 | } else { /* no queuedata implies admin queue */ |
719 | logging_enabled = nr->ctrl->passthru_err_log_enabled; | |
dc96f938 | 720 | req->timeout = NVME_ADMIN_TIMEOUT; |
9f079dda AA |
721 | } |
722 | ||
723 | if (!logging_enabled) | |
724 | req->rq_flags |= RQF_QUIET; | |
21d34711 | 725 | |
f4b9e6c9 KB |
726 | /* passthru commands should let the driver set the SGL flags */ |
727 | cmd->common.flags &= ~NVME_CMD_SGL_ALL; | |
728 | ||
21d34711 | 729 | req->cmd_flags |= REQ_FAILFAST_DRIVER; |
be42a33b | 730 | if (req->mq_hctx->type == HCTX_TYPE_POLL) |
6ce913fe | 731 | req->cmd_flags |= REQ_POLLED; |
bb06ec31 | 732 | nvme_clear_nvme_request(req); |
9f079dda | 733 | memcpy(nr->cmd, cmd, sizeof(*cmd)); |
39dfe844 | 734 | } |
e559398f | 735 | EXPORT_SYMBOL_GPL(nvme_init_request); |
39dfe844 | 736 | |
a9715744 TC |
737 | /* |
738 | * For something we're not in a state to send to the device the default action | |
739 | * is to busy it and retry it after the controller state is recovered. However, | |
740 | * if the controller is deleting or if anything is marked for failfast or | |
741 | * nvme multipath it is immediately failed. | |
742 | * | |
743 | * Note: commands used to initialize the controller will be marked for failfast. | |
744 | * Note: nvme cli/ioctl commands are marked for failfast. | |
745 | */ | |
746 | blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl, | |
747 | struct request *rq) | |
748 | { | |
e6e7f7ac KB |
749 | enum nvme_ctrl_state state = nvme_ctrl_state(ctrl); |
750 | ||
751 | if (state != NVME_CTRL_DELETING_NOIO && | |
752 | state != NVME_CTRL_DELETING && | |
753 | state != NVME_CTRL_DEAD && | |
a9715744 TC |
754 | !test_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags) && |
755 | !blk_noretry_request(rq) && !(rq->cmd_flags & REQ_NVME_MPATH)) | |
756 | return BLK_STS_RESOURCE; | |
757 | return nvme_host_path_error(rq); | |
758 | } | |
759 | EXPORT_SYMBOL_GPL(nvme_fail_nonready_command); | |
760 | ||
761 | bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq, | |
6d3c7fb1 | 762 | bool queue_live, enum nvme_ctrl_state state) |
a9715744 TC |
763 | { |
764 | struct nvme_request *req = nvme_req(rq); | |
765 | ||
766 | /* | |
767 | * currently we have a problem sending passthru commands | |
768 | * on the admin_q if the controller is not LIVE because we can't | |
769 | * make sure that they are going out after the admin connect, | |
770 | * controller enable and/or other commands in the initialization | |
771 | * sequence. until the controller will be LIVE, fail with | |
772 | * BLK_STS_RESOURCE so that they will be rescheduled. | |
773 | */ | |
774 | if (rq->q == ctrl->admin_q && (req->flags & NVME_REQ_USERCMD)) | |
775 | return false; | |
776 | ||
777 | if (ctrl->ops->flags & NVME_F_FABRICS) { | |
778 | /* | |
779 | * Only allow commands on a live queue, except for the connect | |
780 | * command, which is require to set the queue live in the | |
781 | * appropinquate states. | |
782 | */ | |
6d3c7fb1 | 783 | switch (state) { |
a9715744 TC |
784 | case NVME_CTRL_CONNECTING: |
785 | if (blk_rq_is_passthrough(rq) && nvme_is_fabrics(req->cmd) && | |
f50fff73 HR |
786 | (req->cmd->fabrics.fctype == nvme_fabrics_type_connect || |
787 | req->cmd->fabrics.fctype == nvme_fabrics_type_auth_send || | |
788 | req->cmd->fabrics.fctype == nvme_fabrics_type_auth_receive)) | |
a9715744 TC |
789 | return true; |
790 | break; | |
791 | default: | |
792 | break; | |
793 | case NVME_CTRL_DEAD: | |
794 | return false; | |
795 | } | |
796 | } | |
797 | ||
798 | return queue_live; | |
799 | } | |
800 | EXPORT_SYMBOL_GPL(__nvme_check_ready); | |
801 | ||
8093f7ca ML |
802 | static inline void nvme_setup_flush(struct nvme_ns *ns, |
803 | struct nvme_command *cmnd) | |
804 | { | |
9c3d2929 | 805 | memset(cmnd, 0, sizeof(*cmnd)); |
8093f7ca | 806 | cmnd->common.opcode = nvme_cmd_flush; |
ed754e5d | 807 | cmnd->common.nsid = cpu_to_le32(ns->head->ns_id); |
8093f7ca ML |
808 | } |
809 | ||
fc17b653 | 810 | static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req, |
8093f7ca ML |
811 | struct nvme_command *cmnd) |
812 | { | |
b35ba01e | 813 | unsigned short segments = blk_rq_nr_discard_segments(req), n = 0; |
8093f7ca | 814 | struct nvme_dsm_range *range; |
b35ba01e | 815 | struct bio *bio; |
8093f7ca | 816 | |
530436c4 EH |
817 | /* |
818 | * Some devices do not consider the DSM 'Number of Ranges' field when | |
819 | * determining how much data to DMA. Always allocate memory for maximum | |
820 | * number of segments to prevent device reading beyond end of buffer. | |
821 | */ | |
822 | static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES; | |
823 | ||
824 | range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN); | |
cb5b7262 JA |
825 | if (!range) { |
826 | /* | |
827 | * If we fail allocation our range, fallback to the controller | |
828 | * discard page. If that's also busy, it's safe to return | |
829 | * busy, as we know we can make progress once that's freed. | |
830 | */ | |
831 | if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy)) | |
832 | return BLK_STS_RESOURCE; | |
833 | ||
834 | range = page_address(ns->ctrl->discard_page); | |
835 | } | |
8093f7ca | 836 | |
37f0dc2e | 837 | if (queue_max_discard_segments(req->q) == 1) { |
0372dd4e | 838 | u64 slba = nvme_sect_to_lba(ns->head, blk_rq_pos(req)); |
9419e71b | 839 | u32 nlb = blk_rq_sectors(req) >> (ns->head->lba_shift - 9); |
37f0dc2e ML |
840 | |
841 | range[0].cattr = cpu_to_le32(0); | |
842 | range[0].nlb = cpu_to_le32(nlb); | |
843 | range[0].slba = cpu_to_le64(slba); | |
844 | n = 1; | |
845 | } else { | |
846 | __rq_for_each_bio(bio, req) { | |
0372dd4e DW |
847 | u64 slba = nvme_sect_to_lba(ns->head, |
848 | bio->bi_iter.bi_sector); | |
9419e71b | 849 | u32 nlb = bio->bi_iter.bi_size >> ns->head->lba_shift; |
37f0dc2e ML |
850 | |
851 | if (n < segments) { | |
852 | range[n].cattr = cpu_to_le32(0); | |
853 | range[n].nlb = cpu_to_le32(nlb); | |
854 | range[n].slba = cpu_to_le64(slba); | |
855 | } | |
856 | n++; | |
8cb6af7b | 857 | } |
b35ba01e CH |
858 | } |
859 | ||
860 | if (WARN_ON_ONCE(n != segments)) { | |
cb5b7262 JA |
861 | if (virt_to_page(range) == ns->ctrl->discard_page) |
862 | clear_bit_unlock(0, &ns->ctrl->discard_page_busy); | |
863 | else | |
864 | kfree(range); | |
fc17b653 | 865 | return BLK_STS_IOERR; |
b35ba01e | 866 | } |
8093f7ca | 867 | |
9c3d2929 | 868 | memset(cmnd, 0, sizeof(*cmnd)); |
8093f7ca | 869 | cmnd->dsm.opcode = nvme_cmd_dsm; |
ed754e5d | 870 | cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id); |
f1dd03a8 | 871 | cmnd->dsm.nr = cpu_to_le32(segments - 1); |
8093f7ca ML |
872 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); |
873 | ||
4bee16da | 874 | bvec_set_virt(&req->special_vec, range, alloc_size); |
f9d03f96 | 875 | req->rq_flags |= RQF_SPECIAL_PAYLOAD; |
8093f7ca | 876 | |
fc17b653 | 877 | return BLK_STS_OK; |
8093f7ca | 878 | } |
8093f7ca | 879 | |
4020aad8 KB |
880 | static void nvme_set_ref_tag(struct nvme_ns *ns, struct nvme_command *cmnd, |
881 | struct request *req) | |
882 | { | |
883 | u32 upper, lower; | |
884 | u64 ref48; | |
885 | ||
886 | /* both rw and write zeroes share the same reftag format */ | |
9419e71b | 887 | switch (ns->head->guard_type) { |
4020aad8 KB |
888 | case NVME_NVM_NS_16B_GUARD: |
889 | cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req)); | |
890 | break; | |
891 | case NVME_NVM_NS_64B_GUARD: | |
892 | ref48 = ext_pi_ref_tag(req); | |
893 | lower = lower_32_bits(ref48); | |
894 | upper = upper_32_bits(ref48); | |
895 | ||
896 | cmnd->rw.reftag = cpu_to_le32(lower); | |
897 | cmnd->rw.cdw3 = cpu_to_le32(upper); | |
898 | break; | |
899 | default: | |
900 | break; | |
901 | } | |
902 | } | |
903 | ||
6e02318e CK |
904 | static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns, |
905 | struct request *req, struct nvme_command *cmnd) | |
906 | { | |
9c3d2929 JA |
907 | memset(cmnd, 0, sizeof(*cmnd)); |
908 | ||
6e02318e CK |
909 | if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES) |
910 | return nvme_setup_discard(ns, req, cmnd); | |
911 | ||
912 | cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes; | |
913 | cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id); | |
914 | cmnd->write_zeroes.slba = | |
0372dd4e | 915 | cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req))); |
6e02318e | 916 | cmnd->write_zeroes.length = |
9419e71b | 917 | cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1); |
00b33cf3 | 918 | |
9419e71b DW |
919 | if (!(req->cmd_flags & REQ_NOUNMAP) && |
920 | (ns->head->features & NVME_NS_DEAC)) | |
1b96f862 CH |
921 | cmnd->write_zeroes.control |= cpu_to_le16(NVME_WZ_DEAC); |
922 | ||
0372dd4e | 923 | if (nvme_ns_has_pi(ns->head)) { |
1b96f862 | 924 | cmnd->write_zeroes.control |= cpu_to_le16(NVME_RW_PRINFO_PRACT); |
00b33cf3 | 925 | |
9419e71b | 926 | switch (ns->head->pi_type) { |
00b33cf3 KJ |
927 | case NVME_NS_DPS_PI_TYPE1: |
928 | case NVME_NS_DPS_PI_TYPE2: | |
4020aad8 | 929 | nvme_set_ref_tag(ns, cmnd, req); |
00b33cf3 KJ |
930 | break; |
931 | } | |
932 | } | |
933 | ||
6e02318e CK |
934 | return BLK_STS_OK; |
935 | } | |
936 | ||
ebe6d874 | 937 | static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns, |
240e6ee2 KB |
938 | struct request *req, struct nvme_command *cmnd, |
939 | enum nvme_opcode op) | |
8093f7ca ML |
940 | { |
941 | u16 control = 0; | |
942 | u32 dsmgmt = 0; | |
943 | ||
944 | if (req->cmd_flags & REQ_FUA) | |
945 | control |= NVME_RW_FUA; | |
946 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
947 | control |= NVME_RW_LR; | |
948 | ||
949 | if (req->cmd_flags & REQ_RAHEAD) | |
950 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
951 | ||
240e6ee2 | 952 | cmnd->rw.opcode = op; |
a9a7e30f | 953 | cmnd->rw.flags = 0; |
ed754e5d | 954 | cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id); |
4020aad8 KB |
955 | cmnd->rw.cdw2 = 0; |
956 | cmnd->rw.cdw3 = 0; | |
a9a7e30f | 957 | cmnd->rw.metadata = 0; |
0372dd4e DW |
958 | cmnd->rw.slba = |
959 | cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req))); | |
9419e71b DW |
960 | cmnd->rw.length = |
961 | cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1); | |
a9a7e30f JA |
962 | cmnd->rw.reftag = 0; |
963 | cmnd->rw.apptag = 0; | |
964 | cmnd->rw.appmask = 0; | |
8093f7ca | 965 | |
9419e71b | 966 | if (ns->head->ms) { |
715ea9e0 CH |
967 | /* |
968 | * If formated with metadata, the block layer always provides a | |
969 | * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else | |
970 | * we enable the PRACT bit for protection information or set the | |
971 | * namespace capacity to zero to prevent any I/O. | |
972 | */ | |
973 | if (!blk_integrity_rq(req)) { | |
0372dd4e | 974 | if (WARN_ON_ONCE(!nvme_ns_has_pi(ns->head))) |
715ea9e0 CH |
975 | return BLK_STS_NOTSUPP; |
976 | control |= NVME_RW_PRINFO_PRACT; | |
977 | } | |
978 | ||
9419e71b | 979 | switch (ns->head->pi_type) { |
8093f7ca ML |
980 | case NVME_NS_DPS_PI_TYPE3: |
981 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
982 | break; | |
983 | case NVME_NS_DPS_PI_TYPE1: | |
984 | case NVME_NS_DPS_PI_TYPE2: | |
985 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
986 | NVME_RW_PRINFO_PRCHK_REF; | |
240e6ee2 KB |
987 | if (op == nvme_cmd_zone_append) |
988 | control |= NVME_RW_APPEND_PIREMAP; | |
4020aad8 | 989 | nvme_set_ref_tag(ns, cmnd, req); |
8093f7ca ML |
990 | break; |
991 | } | |
8093f7ca ML |
992 | } |
993 | ||
994 | cmnd->rw.control = cpu_to_le16(control); | |
995 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
ebe6d874 | 996 | return 0; |
8093f7ca ML |
997 | } |
998 | ||
f7f1fc36 MG |
999 | void nvme_cleanup_cmd(struct request *req) |
1000 | { | |
f7f1fc36 | 1001 | if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { |
fc97e942 | 1002 | struct nvme_ctrl *ctrl = nvme_req(req)->ctrl; |
cb5b7262 | 1003 | |
3973e15f | 1004 | if (req->special_vec.bv_page == ctrl->discard_page) |
fc97e942 | 1005 | clear_bit_unlock(0, &ctrl->discard_page_busy); |
cb5b7262 | 1006 | else |
3973e15f | 1007 | kfree(bvec_virt(&req->special_vec)); |
f7f1fc36 MG |
1008 | } |
1009 | } | |
1010 | EXPORT_SYMBOL_GPL(nvme_cleanup_cmd); | |
1011 | ||
f4b9e6c9 | 1012 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req) |
8093f7ca | 1013 | { |
f4b9e6c9 | 1014 | struct nvme_command *cmd = nvme_req(req)->cmd; |
fc17b653 | 1015 | blk_status_t ret = BLK_STS_OK; |
8093f7ca | 1016 | |
9c3d2929 | 1017 | if (!(req->rq_flags & RQF_DONTPREP)) |
c03fd85d | 1018 | nvme_clear_nvme_request(req); |
987f699a | 1019 | |
aebf526b CH |
1020 | switch (req_op(req)) { |
1021 | case REQ_OP_DRV_IN: | |
1022 | case REQ_OP_DRV_OUT: | |
f4b9e6c9 | 1023 | /* these are setup prior to execution in nvme_init_request() */ |
aebf526b CH |
1024 | break; |
1025 | case REQ_OP_FLUSH: | |
8093f7ca | 1026 | nvme_setup_flush(ns, cmd); |
aebf526b | 1027 | break; |
240e6ee2 KB |
1028 | case REQ_OP_ZONE_RESET_ALL: |
1029 | case REQ_OP_ZONE_RESET: | |
1030 | ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET); | |
1031 | break; | |
1032 | case REQ_OP_ZONE_OPEN: | |
1033 | ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN); | |
1034 | break; | |
1035 | case REQ_OP_ZONE_CLOSE: | |
1036 | ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE); | |
1037 | break; | |
1038 | case REQ_OP_ZONE_FINISH: | |
1039 | ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH); | |
1040 | break; | |
e850fd16 | 1041 | case REQ_OP_WRITE_ZEROES: |
6e02318e CK |
1042 | ret = nvme_setup_write_zeroes(ns, req, cmd); |
1043 | break; | |
aebf526b | 1044 | case REQ_OP_DISCARD: |
8093f7ca | 1045 | ret = nvme_setup_discard(ns, req, cmd); |
aebf526b CH |
1046 | break; |
1047 | case REQ_OP_READ: | |
240e6ee2 KB |
1048 | ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read); |
1049 | break; | |
aebf526b | 1050 | case REQ_OP_WRITE: |
240e6ee2 KB |
1051 | ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write); |
1052 | break; | |
1053 | case REQ_OP_ZONE_APPEND: | |
1054 | ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append); | |
aebf526b CH |
1055 | break; |
1056 | default: | |
1057 | WARN_ON_ONCE(1); | |
fc17b653 | 1058 | return BLK_STS_IOERR; |
aebf526b | 1059 | } |
8093f7ca | 1060 | |
e7006de6 | 1061 | cmd->common.command_id = nvme_cid(req); |
5d87eb94 | 1062 | trace_nvme_setup_cmd(req, cmd); |
8093f7ca ML |
1063 | return ret; |
1064 | } | |
1065 | EXPORT_SYMBOL_GPL(nvme_setup_cmd); | |
1066 | ||
ae5e6886 KB |
1067 | /* |
1068 | * Return values: | |
1069 | * 0: success | |
1070 | * >0: nvme controller's cqe status response | |
1071 | * <0: kernel error in lieu of controller response | |
1072 | */ | |
62281b9e | 1073 | int nvme_execute_rq(struct request *rq, bool at_head) |
ae5e6886 KB |
1074 | { |
1075 | blk_status_t status; | |
1076 | ||
b84ba30b | 1077 | status = blk_execute_rq(rq, at_head); |
ae5e6886 KB |
1078 | if (nvme_req(rq)->flags & NVME_REQ_CANCELLED) |
1079 | return -EINTR; | |
1080 | if (nvme_req(rq)->status) | |
1081 | return nvme_req(rq)->status; | |
1082 | return blk_status_to_errno(status); | |
1083 | } | |
62281b9e | 1084 | EXPORT_SYMBOL_NS_GPL(nvme_execute_rq, NVME_TARGET_PASSTHRU); |
ae5e6886 | 1085 | |
4160982e CH |
1086 | /* |
1087 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
1088 | * if the result is positive, it's an NVM Express status code | |
1089 | */ | |
1090 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
d49187e9 | 1091 | union nvme_result *result, void *buffer, unsigned bufflen, |
bd2687f2 | 1092 | int qid, nvme_submit_flags_t flags) |
4160982e CH |
1093 | { |
1094 | struct request *req; | |
1095 | int ret; | |
bd2687f2 | 1096 | blk_mq_req_flags_t blk_flags = 0; |
4160982e | 1097 | |
bd2687f2 HR |
1098 | if (flags & NVME_SUBMIT_NOWAIT) |
1099 | blk_flags |= BLK_MQ_REQ_NOWAIT; | |
1100 | if (flags & NVME_SUBMIT_RESERVED) | |
1101 | blk_flags |= BLK_MQ_REQ_RESERVED; | |
39dfe844 | 1102 | if (qid == NVME_QID_ANY) |
bd2687f2 | 1103 | req = blk_mq_alloc_request(q, nvme_req_op(cmd), blk_flags); |
39dfe844 | 1104 | else |
bd2687f2 | 1105 | req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), blk_flags, |
b10907b8 | 1106 | qid - 1); |
e559398f | 1107 | |
4160982e CH |
1108 | if (IS_ERR(req)) |
1109 | return PTR_ERR(req); | |
e559398f | 1110 | nvme_init_request(req, cmd); |
48dae466 HR |
1111 | if (flags & NVME_SUBMIT_RETRY) |
1112 | req->cmd_flags &= ~REQ_FAILFAST_DRIVER; | |
4160982e | 1113 | |
21d34711 CH |
1114 | if (buffer && bufflen) { |
1115 | ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL); | |
1116 | if (ret) | |
1117 | goto out; | |
4160982e CH |
1118 | } |
1119 | ||
bd2687f2 | 1120 | ret = nvme_execute_rq(req, flags & NVME_SUBMIT_AT_HEAD); |
ae5e6886 | 1121 | if (result && ret >= 0) |
d49187e9 | 1122 | *result = nvme_req(req)->result; |
4160982e CH |
1123 | out: |
1124 | blk_mq_free_request(req); | |
1125 | return ret; | |
1126 | } | |
eb71f435 | 1127 | EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd); |
4160982e CH |
1128 | |
1129 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, | |
1130 | void *buffer, unsigned bufflen) | |
1131 | { | |
6b46fa02 | 1132 | return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, |
bd2687f2 | 1133 | NVME_QID_ANY, 0); |
4160982e | 1134 | } |
576d55d6 | 1135 | EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd); |
4160982e | 1136 | |
df21b6b1 LG |
1137 | u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode) |
1138 | { | |
1139 | u32 effects = 0; | |
1140 | ||
1141 | if (ns) { | |
cc115cbe | 1142 | effects = le32_to_cpu(ns->head->effects->iocs[opcode]); |
df21b6b1 | 1143 | if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC)) |
ed4a854b | 1144 | dev_warn_once(ctrl->device, |
831ed60c | 1145 | "IO command:%02x has unusual effects:%08x\n", |
ed4a854b | 1146 | opcode, effects); |
df21b6b1 | 1147 | |
831ed60c CH |
1148 | /* |
1149 | * NVME_CMD_EFFECTS_CSE_MASK causes a freeze all I/O queues, | |
1150 | * which would deadlock when done on an I/O command. Note that | |
1151 | * We already warn about an unusual effect above. | |
1152 | */ | |
1153 | effects &= ~NVME_CMD_EFFECTS_CSE_MASK; | |
1154 | } else { | |
cc115cbe | 1155 | effects = le32_to_cpu(ctrl->effects->acs[opcode]); |
831ed60c | 1156 | } |
df21b6b1 LG |
1157 | |
1158 | return effects; | |
1159 | } | |
1160 | EXPORT_SYMBOL_NS_GPL(nvme_command_effects, NVME_TARGET_PASSTHRU); | |
1161 | ||
62281b9e | 1162 | u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode) |
df21b6b1 LG |
1163 | { |
1164 | u32 effects = nvme_command_effects(ctrl, ns, opcode); | |
1165 | ||
1166 | /* | |
1167 | * For simplicity, IO to all namespaces is quiesced even if the command | |
1168 | * effects say only one namespace is affected. | |
1169 | */ | |
af0f446d | 1170 | if (effects & NVME_CMD_EFFECTS_CSE_MASK) { |
df21b6b1 LG |
1171 | mutex_lock(&ctrl->scan_lock); |
1172 | mutex_lock(&ctrl->subsys->lock); | |
1173 | nvme_mpath_start_freeze(ctrl->subsys); | |
1174 | nvme_mpath_wait_freeze(ctrl->subsys); | |
1175 | nvme_start_freeze(ctrl); | |
1176 | nvme_wait_freeze(ctrl); | |
1177 | } | |
1178 | return effects; | |
1179 | } | |
62281b9e | 1180 | EXPORT_SYMBOL_NS_GPL(nvme_passthru_start, NVME_TARGET_PASSTHRU); |
df21b6b1 | 1181 | |
31a59782 | 1182 | void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects, |
bc8fb906 | 1183 | struct nvme_command *cmd, int status) |
df21b6b1 | 1184 | { |
af0f446d | 1185 | if (effects & NVME_CMD_EFFECTS_CSE_MASK) { |
df21b6b1 LG |
1186 | nvme_unfreeze(ctrl); |
1187 | nvme_mpath_unfreeze(ctrl->subsys); | |
1188 | mutex_unlock(&ctrl->subsys->lock); | |
df21b6b1 LG |
1189 | mutex_unlock(&ctrl->scan_lock); |
1190 | } | |
1e37a307 | 1191 | if (effects & NVME_CMD_EFFECTS_CCC) { |
d0dd594b BL |
1192 | if (!test_and_set_bit(NVME_CTRL_DIRTY_CAPABILITY, |
1193 | &ctrl->flags)) { | |
1194 | dev_info(ctrl->device, | |
1e37a307 | 1195 | "controller capabilities changed, reset may be required to take effect.\n"); |
d0dd594b | 1196 | } |
1e37a307 | 1197 | } |
df21b6b1 LG |
1198 | if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) { |
1199 | nvme_queue_scan(ctrl); | |
1200 | flush_work(&ctrl->scan_work); | |
1201 | } | |
31a59782 | 1202 | if (ns) |
1203 | return; | |
b58da2d2 TS |
1204 | |
1205 | switch (cmd->common.opcode) { | |
1206 | case nvme_admin_set_features: | |
1207 | switch (le32_to_cpu(cmd->common.cdw10) & 0xFF) { | |
1208 | case NVME_FEAT_KATO: | |
1209 | /* | |
1210 | * Keep alive commands interval on the host should be | |
1211 | * updated when KATO is modified by Set Features | |
1212 | * commands. | |
1213 | */ | |
1214 | if (!status) | |
1215 | nvme_update_keep_alive(ctrl, cmd); | |
1216 | break; | |
1217 | default: | |
1218 | break; | |
1219 | } | |
1220 | break; | |
1221 | default: | |
1222 | break; | |
1223 | } | |
df21b6b1 | 1224 | } |
bc8fb906 | 1225 | EXPORT_SYMBOL_NS_GPL(nvme_passthru_end, NVME_TARGET_PASSTHRU); |
df21b6b1 | 1226 | |
a70b81bd HR |
1227 | /* |
1228 | * Recommended frequency for KATO commands per NVMe 1.4 section 7.12.1: | |
1229 | * | |
1230 | * The host should send Keep Alive commands at half of the Keep Alive Timeout | |
1231 | * accounting for transport roundtrip times [..]. | |
1232 | */ | |
ea4d453b US |
1233 | static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl) |
1234 | { | |
1235 | unsigned long delay = ctrl->kato * HZ / 2; | |
1236 | ||
1237 | /* | |
1238 | * When using Traffic Based Keep Alive, we need to run | |
1239 | * nvme_keep_alive_work at twice the normal frequency, as one | |
1240 | * command completion can postpone sending a keep alive command | |
1241 | * by up to twice the delay between runs. | |
1242 | */ | |
1243 | if (ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) | |
1244 | delay /= 2; | |
1245 | return delay; | |
1246 | } | |
1247 | ||
a70b81bd | 1248 | static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl) |
4160982e | 1249 | { |
136cfcb8 MD |
1250 | unsigned long now = jiffies; |
1251 | unsigned long delay = nvme_keep_alive_work_period(ctrl); | |
1252 | unsigned long ka_next_check_tm = ctrl->ka_last_check_time + delay; | |
1253 | ||
1254 | if (time_after(now, ka_next_check_tm)) | |
1255 | delay = 0; | |
1256 | else | |
1257 | delay = ka_next_check_tm - now; | |
1258 | ||
1259 | queue_delayed_work(nvme_wq, &ctrl->ka_work, delay); | |
21d34711 CH |
1260 | } |
1261 | ||
de671d61 JA |
1262 | static enum rq_end_io_ret nvme_keep_alive_end_io(struct request *rq, |
1263 | blk_status_t status) | |
038bd4cb SG |
1264 | { |
1265 | struct nvme_ctrl *ctrl = rq->end_io_data; | |
86880d64 JS |
1266 | unsigned long flags; |
1267 | bool startka = false; | |
c7275ce6 US |
1268 | unsigned long rtt = jiffies - (rq->deadline - rq->timeout); |
1269 | unsigned long delay = nvme_keep_alive_work_period(ctrl); | |
1270 | ||
1271 | /* | |
1272 | * Subtract off the keepalive RTT so nvme_keep_alive_work runs | |
1273 | * at the desired frequency. | |
1274 | */ | |
1275 | if (rtt <= delay) { | |
1276 | delay -= rtt; | |
1277 | } else { | |
1278 | dev_warn(ctrl->device, "long keepalive RTT (%u ms)\n", | |
1279 | jiffies_to_msecs(rtt)); | |
1280 | delay = 0; | |
1281 | } | |
038bd4cb SG |
1282 | |
1283 | blk_mq_free_request(rq); | |
1284 | ||
2a842aca | 1285 | if (status) { |
038bd4cb | 1286 | dev_err(ctrl->device, |
2a842aca CH |
1287 | "failed nvme_keep_alive_end_io error=%d\n", |
1288 | status); | |
de671d61 | 1289 | return RQ_END_IO_NONE; |
038bd4cb SG |
1290 | } |
1291 | ||
774a9636 | 1292 | ctrl->ka_last_check_time = jiffies; |
6e3ca03e | 1293 | ctrl->comp_seen = false; |
86880d64 JS |
1294 | spin_lock_irqsave(&ctrl->lock, flags); |
1295 | if (ctrl->state == NVME_CTRL_LIVE || | |
1296 | ctrl->state == NVME_CTRL_CONNECTING) | |
1297 | startka = true; | |
1298 | spin_unlock_irqrestore(&ctrl->lock, flags); | |
1299 | if (startka) | |
c7275ce6 | 1300 | queue_delayed_work(nvme_wq, &ctrl->ka_work, delay); |
de671d61 | 1301 | return RQ_END_IO_NONE; |
038bd4cb SG |
1302 | } |
1303 | ||
038bd4cb SG |
1304 | static void nvme_keep_alive_work(struct work_struct *work) |
1305 | { | |
1306 | struct nvme_ctrl *ctrl = container_of(to_delayed_work(work), | |
1307 | struct nvme_ctrl, ka_work); | |
6e3ca03e | 1308 | bool comp_seen = ctrl->comp_seen; |
06c3c336 | 1309 | struct request *rq; |
6e3ca03e | 1310 | |
774a9636 US |
1311 | ctrl->ka_last_check_time = jiffies; |
1312 | ||
6e3ca03e SG |
1313 | if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) { |
1314 | dev_dbg(ctrl->device, | |
1315 | "reschedule traffic based keep-alive timer\n"); | |
1316 | ctrl->comp_seen = false; | |
a70b81bd | 1317 | nvme_queue_keep_alive_work(ctrl); |
6e3ca03e SG |
1318 | return; |
1319 | } | |
038bd4cb | 1320 | |
e559398f CH |
1321 | rq = blk_mq_alloc_request(ctrl->admin_q, nvme_req_op(&ctrl->ka_cmd), |
1322 | BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT); | |
06c3c336 | 1323 | if (IS_ERR(rq)) { |
038bd4cb | 1324 | /* allocation failure, reset the controller */ |
985c5a32 | 1325 | dev_err(ctrl->device, "keep-alive failed: %ld\n", PTR_ERR(rq)); |
39bdc590 | 1326 | nvme_reset_ctrl(ctrl); |
038bd4cb SG |
1327 | return; |
1328 | } | |
e559398f | 1329 | nvme_init_request(rq, &ctrl->ka_cmd); |
06c3c336 CH |
1330 | |
1331 | rq->timeout = ctrl->kato * HZ; | |
e2e53086 | 1332 | rq->end_io = nvme_keep_alive_end_io; |
06c3c336 | 1333 | rq->end_io_data = ctrl; |
e2e53086 | 1334 | blk_execute_rq_nowait(rq, false); |
038bd4cb SG |
1335 | } |
1336 | ||
00b683db | 1337 | static void nvme_start_keep_alive(struct nvme_ctrl *ctrl) |
038bd4cb SG |
1338 | { |
1339 | if (unlikely(ctrl->kato == 0)) | |
1340 | return; | |
1341 | ||
a70b81bd | 1342 | nvme_queue_keep_alive_work(ctrl); |
038bd4cb | 1343 | } |
038bd4cb SG |
1344 | |
1345 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl) | |
1346 | { | |
1347 | if (unlikely(ctrl->kato == 0)) | |
1348 | return; | |
1349 | ||
1350 | cancel_delayed_work_sync(&ctrl->ka_work); | |
1351 | } | |
1352 | EXPORT_SYMBOL_GPL(nvme_stop_keep_alive); | |
1353 | ||
b58da2d2 TS |
1354 | static void nvme_update_keep_alive(struct nvme_ctrl *ctrl, |
1355 | struct nvme_command *cmd) | |
1356 | { | |
1357 | unsigned int new_kato = | |
1358 | DIV_ROUND_UP(le32_to_cpu(cmd->common.cdw11), 1000); | |
1359 | ||
1360 | dev_info(ctrl->device, | |
1361 | "keep alive interval updated from %u ms to %u ms\n", | |
1362 | ctrl->kato * 1000 / 2, new_kato * 1000 / 2); | |
1363 | ||
1364 | nvme_stop_keep_alive(ctrl); | |
1365 | ctrl->kato = new_kato; | |
1366 | nvme_start_keep_alive(ctrl); | |
1367 | } | |
1368 | ||
b9a5c3d4 CH |
1369 | /* |
1370 | * In NVMe 1.0 the CNS field was just a binary controller or namespace | |
1371 | * flag, thus sending any new CNS opcodes has a big chance of not working. | |
1372 | * Qemu unfortunately had that bug after reporting a 1.1 version compliance | |
1373 | * (but not for any later version). | |
1374 | */ | |
1375 | static bool nvme_ctrl_limited_cns(struct nvme_ctrl *ctrl) | |
1376 | { | |
1377 | if (ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS) | |
1378 | return ctrl->vs < NVME_VS(1, 2, 0); | |
1379 | return ctrl->vs < NVME_VS(1, 1, 0); | |
1380 | } | |
1381 | ||
3f7f25a9 | 1382 | static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id) |
21d34711 CH |
1383 | { |
1384 | struct nvme_command c = { }; | |
1385 | int error; | |
1386 | ||
1387 | /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ | |
1388 | c.identify.opcode = nvme_admin_identify; | |
986994a2 | 1389 | c.identify.cns = NVME_ID_CNS_CTRL; |
21d34711 CH |
1390 | |
1391 | *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL); | |
1392 | if (!*id) | |
1393 | return -ENOMEM; | |
1394 | ||
1395 | error = nvme_submit_sync_cmd(dev->admin_q, &c, *id, | |
1396 | sizeof(struct nvme_id_ctrl)); | |
1397 | if (error) | |
1398 | kfree(*id); | |
1399 | return error; | |
1400 | } | |
1401 | ||
ad95a613 | 1402 | static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids, |
71010c30 | 1403 | struct nvme_ns_id_desc *cur, bool *csi_seen) |
ad95a613 CK |
1404 | { |
1405 | const char *warn_str = "ctrl returned bogus length:"; | |
1406 | void *data = cur; | |
1407 | ||
1408 | switch (cur->nidt) { | |
1409 | case NVME_NIDT_EUI64: | |
1410 | if (cur->nidl != NVME_NIDT_EUI64_LEN) { | |
1411 | dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n", | |
1412 | warn_str, cur->nidl); | |
1413 | return -1; | |
1414 | } | |
00ff400e CH |
1415 | if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) |
1416 | return NVME_NIDT_EUI64_LEN; | |
ad95a613 CK |
1417 | memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN); |
1418 | return NVME_NIDT_EUI64_LEN; | |
1419 | case NVME_NIDT_NGUID: | |
1420 | if (cur->nidl != NVME_NIDT_NGUID_LEN) { | |
1421 | dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n", | |
1422 | warn_str, cur->nidl); | |
1423 | return -1; | |
1424 | } | |
00ff400e CH |
1425 | if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) |
1426 | return NVME_NIDT_NGUID_LEN; | |
ad95a613 CK |
1427 | memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN); |
1428 | return NVME_NIDT_NGUID_LEN; | |
1429 | case NVME_NIDT_UUID: | |
1430 | if (cur->nidl != NVME_NIDT_UUID_LEN) { | |
1431 | dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n", | |
1432 | warn_str, cur->nidl); | |
1433 | return -1; | |
1434 | } | |
00ff400e CH |
1435 | if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) |
1436 | return NVME_NIDT_UUID_LEN; | |
ad95a613 CK |
1437 | uuid_copy(&ids->uuid, data + sizeof(*cur)); |
1438 | return NVME_NIDT_UUID_LEN; | |
71010c30 NC |
1439 | case NVME_NIDT_CSI: |
1440 | if (cur->nidl != NVME_NIDT_CSI_LEN) { | |
1441 | dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n", | |
1442 | warn_str, cur->nidl); | |
1443 | return -1; | |
1444 | } | |
1445 | memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN); | |
1446 | *csi_seen = true; | |
1447 | return NVME_NIDT_CSI_LEN; | |
ad95a613 CK |
1448 | default: |
1449 | /* Skip unknown types */ | |
1450 | return cur->nidl; | |
1451 | } | |
1452 | } | |
1453 | ||
1a893c2b CH |
1454 | static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, |
1455 | struct nvme_ns_info *info) | |
3b22ba26 JT |
1456 | { |
1457 | struct nvme_command c = { }; | |
71010c30 NC |
1458 | bool csi_seen = false; |
1459 | int status, pos, len; | |
3b22ba26 | 1460 | void *data; |
3b22ba26 | 1461 | |
8b7c0ff2 CH |
1462 | if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl)) |
1463 | return 0; | |
5bedd3af CH |
1464 | if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST) |
1465 | return 0; | |
1466 | ||
3b22ba26 | 1467 | c.identify.opcode = nvme_admin_identify; |
1a893c2b | 1468 | c.identify.nsid = cpu_to_le32(info->nsid); |
3b22ba26 JT |
1469 | c.identify.cns = NVME_ID_CNS_NS_DESC_LIST; |
1470 | ||
1471 | data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL); | |
1472 | if (!data) | |
1473 | return -ENOMEM; | |
1474 | ||
cdbff4f2 | 1475 | status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data, |
3b22ba26 | 1476 | NVME_IDENTIFY_DATA_SIZE); |
fb314eb0 CH |
1477 | if (status) { |
1478 | dev_warn(ctrl->device, | |
aa9d7295 | 1479 | "Identify Descriptors failed (nsid=%u, status=0x%x)\n", |
1a893c2b | 1480 | info->nsid, status); |
3b22ba26 | 1481 | goto free_data; |
fb314eb0 | 1482 | } |
3b22ba26 JT |
1483 | |
1484 | for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) { | |
1485 | struct nvme_ns_id_desc *cur = data + pos; | |
1486 | ||
1487 | if (cur->nidl == 0) | |
1488 | break; | |
1489 | ||
1a893c2b | 1490 | len = nvme_process_ns_desc(ctrl, &info->ids, cur, &csi_seen); |
ad95a613 | 1491 | if (len < 0) |
71010c30 | 1492 | break; |
3b22ba26 JT |
1493 | |
1494 | len += sizeof(*cur); | |
1495 | } | |
71010c30 NC |
1496 | |
1497 | if (nvme_multi_css(ctrl) && !csi_seen) { | |
1498 | dev_warn(ctrl->device, "Command set not reported for nsid:%d\n", | |
1a893c2b | 1499 | info->nsid); |
71010c30 NC |
1500 | status = -EINVAL; |
1501 | } | |
1502 | ||
3b22ba26 JT |
1503 | free_data: |
1504 | kfree(data); | |
1505 | return status; | |
1506 | } | |
1507 | ||
a1a825ab | 1508 | int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid, |
1a893c2b | 1509 | struct nvme_id_ns **id) |
21d34711 CH |
1510 | { |
1511 | struct nvme_command c = { }; | |
1512 | int error; | |
1513 | ||
1514 | /* gcc-4.4.4 (at least) has issues with initializers and anon unions */ | |
778f067c MG |
1515 | c.identify.opcode = nvme_admin_identify; |
1516 | c.identify.nsid = cpu_to_le32(nsid); | |
986994a2 | 1517 | c.identify.cns = NVME_ID_CNS_NS; |
21d34711 | 1518 | |
331813f6 SG |
1519 | *id = kmalloc(sizeof(**id), GFP_KERNEL); |
1520 | if (!*id) | |
1521 | return -ENOMEM; | |
21d34711 | 1522 | |
331813f6 | 1523 | error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id)); |
cdbff4f2 | 1524 | if (error) { |
d0de579c | 1525 | dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error); |
0dd6fff2 | 1526 | kfree(*id); |
cdbff4f2 | 1527 | } |
1a893c2b CH |
1528 | return error; |
1529 | } | |
00ff400e | 1530 | |
1a893c2b CH |
1531 | static int nvme_ns_info_from_identify(struct nvme_ctrl *ctrl, |
1532 | struct nvme_ns_info *info) | |
1533 | { | |
1534 | struct nvme_ns_ids *ids = &info->ids; | |
1535 | struct nvme_id_ns *id; | |
1536 | int ret; | |
1537 | ||
1538 | ret = nvme_identify_ns(ctrl, info->nsid, &id); | |
1539 | if (ret) | |
1540 | return ret; | |
0dd6fff2 CH |
1541 | |
1542 | if (id->ncap == 0) { | |
1543 | /* namespace not allocated or attached */ | |
1544 | info->is_removed = true; | |
e3139cef ML |
1545 | ret = -ENODEV; |
1546 | goto error; | |
0dd6fff2 CH |
1547 | } |
1548 | ||
1a893c2b CH |
1549 | info->anagrpid = id->anagrpid; |
1550 | info->is_shared = id->nmic & NVME_NS_NMIC_SHARED; | |
1e4ea66a | 1551 | info->is_readonly = id->nsattr & NVME_NS_ATTR_RO; |
1a893c2b | 1552 | info->is_ready = true; |
00ff400e CH |
1553 | if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) { |
1554 | dev_info(ctrl->device, | |
1555 | "Ignoring bogus Namespace Identifiers\n"); | |
1556 | } else { | |
1557 | if (ctrl->vs >= NVME_VS(1, 1, 0) && | |
1558 | !memchr_inv(ids->eui64, 0, sizeof(ids->eui64))) | |
1a893c2b | 1559 | memcpy(ids->eui64, id->eui64, sizeof(ids->eui64)); |
00ff400e CH |
1560 | if (ctrl->vs >= NVME_VS(1, 2, 0) && |
1561 | !memchr_inv(ids->nguid, 0, sizeof(ids->nguid))) | |
1a893c2b | 1562 | memcpy(ids->nguid, id->nguid, sizeof(ids->nguid)); |
00ff400e | 1563 | } |
e3139cef ML |
1564 | |
1565 | error: | |
1a893c2b | 1566 | kfree(id); |
e3139cef | 1567 | return ret; |
21d34711 CH |
1568 | } |
1569 | ||
1a893c2b CH |
1570 | static int nvme_ns_info_from_id_cs_indep(struct nvme_ctrl *ctrl, |
1571 | struct nvme_ns_info *info) | |
354201c5 | 1572 | { |
1a893c2b | 1573 | struct nvme_id_ns_cs_indep *id; |
354201c5 CH |
1574 | struct nvme_command c = { |
1575 | .identify.opcode = nvme_admin_identify, | |
1a893c2b | 1576 | .identify.nsid = cpu_to_le32(info->nsid), |
354201c5 CH |
1577 | .identify.cns = NVME_ID_CNS_NS_CS_INDEP, |
1578 | }; | |
1579 | int ret; | |
1580 | ||
1a893c2b CH |
1581 | id = kmalloc(sizeof(*id), GFP_KERNEL); |
1582 | if (!id) | |
354201c5 CH |
1583 | return -ENOMEM; |
1584 | ||
1a893c2b CH |
1585 | ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id)); |
1586 | if (!ret) { | |
1587 | info->anagrpid = id->anagrpid; | |
1588 | info->is_shared = id->nmic & NVME_NS_NMIC_SHARED; | |
1e4ea66a | 1589 | info->is_readonly = id->nsattr & NVME_NS_ATTR_RO; |
1a893c2b | 1590 | info->is_ready = id->nstat & NVME_NSTAT_NRDY; |
354201c5 | 1591 | } |
1a893c2b CH |
1592 | kfree(id); |
1593 | return ret; | |
354201c5 CH |
1594 | } |
1595 | ||
1a87ee65 KB |
1596 | static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid, |
1597 | unsigned int dword11, void *buffer, size_t buflen, u32 *result) | |
21d34711 | 1598 | { |
15755854 | 1599 | union nvme_result res = { 0 }; |
cc72c442 | 1600 | struct nvme_command c = { }; |
1cb3cce5 | 1601 | int ret; |
21d34711 | 1602 | |
1a87ee65 | 1603 | c.features.opcode = op; |
21d34711 CH |
1604 | c.features.fid = cpu_to_le32(fid); |
1605 | c.features.dword11 = cpu_to_le32(dword11); | |
1606 | ||
d49187e9 | 1607 | ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res, |
bd2687f2 | 1608 | buffer, buflen, NVME_QID_ANY, 0); |
9b47f77a | 1609 | if (ret >= 0 && result) |
d49187e9 | 1610 | *result = le32_to_cpu(res.u32); |
1cb3cce5 | 1611 | return ret; |
21d34711 CH |
1612 | } |
1613 | ||
1a87ee65 KB |
1614 | int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid, |
1615 | unsigned int dword11, void *buffer, size_t buflen, | |
1616 | u32 *result) | |
1617 | { | |
1618 | return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer, | |
1619 | buflen, result); | |
1620 | } | |
1621 | EXPORT_SYMBOL_GPL(nvme_set_features); | |
1622 | ||
1623 | int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid, | |
1624 | unsigned int dword11, void *buffer, size_t buflen, | |
1625 | u32 *result) | |
1626 | { | |
1627 | return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer, | |
1628 | buflen, result); | |
1629 | } | |
1630 | EXPORT_SYMBOL_GPL(nvme_get_features); | |
1631 | ||
9a0be7ab CH |
1632 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count) |
1633 | { | |
1634 | u32 q_count = (*count - 1) | ((*count - 1) << 16); | |
1635 | u32 result; | |
1636 | int status, nr_io_queues; | |
1637 | ||
1a6fe74d | 1638 | status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0, |
9a0be7ab | 1639 | &result); |
f5fa90dc | 1640 | if (status < 0) |
9a0be7ab CH |
1641 | return status; |
1642 | ||
f5fa90dc CH |
1643 | /* |
1644 | * Degraded controllers might return an error when setting the queue | |
1645 | * count. We still want to be able to bring them online and offer | |
1646 | * access to the admin queue, as that might be only way to fix them up. | |
1647 | */ | |
1648 | if (status > 0) { | |
f0425db0 | 1649 | dev_err(ctrl->device, "Could not set queue count (%d)\n", status); |
f5fa90dc CH |
1650 | *count = 0; |
1651 | } else { | |
1652 | nr_io_queues = min(result & 0xffff, result >> 16) + 1; | |
1653 | *count = min(*count, nr_io_queues); | |
1654 | } | |
1655 | ||
9a0be7ab CH |
1656 | return 0; |
1657 | } | |
576d55d6 | 1658 | EXPORT_SYMBOL_GPL(nvme_set_queue_count); |
9a0be7ab | 1659 | |
c0561f82 | 1660 | #define NVME_AEN_SUPPORTED \ |
85f8a435 SG |
1661 | (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \ |
1662 | NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE) | |
c0561f82 HR |
1663 | |
1664 | static void nvme_enable_aen(struct nvme_ctrl *ctrl) | |
1665 | { | |
fa441b71 | 1666 | u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED; |
c0561f82 HR |
1667 | int status; |
1668 | ||
fa441b71 WZ |
1669 | if (!supported_aens) |
1670 | return; | |
1671 | ||
1672 | status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens, | |
1673 | NULL, 0, &result); | |
c0561f82 HR |
1674 | if (status) |
1675 | dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n", | |
fa441b71 | 1676 | supported_aens); |
93da4023 SG |
1677 | |
1678 | queue_work(nvme_wq, &ctrl->async_event_work); | |
c0561f82 HR |
1679 | } |
1680 | ||
f5b9a51d | 1681 | static int nvme_ns_open(struct nvme_ns *ns) |
c225b610 | 1682 | { |
c225b610 | 1683 | |
32acab31 | 1684 | /* should never be called due to GENHD_FL_HIDDEN */ |
30897388 | 1685 | if (WARN_ON_ONCE(nvme_ns_head_multipath(ns->head))) |
85088c4a | 1686 | goto fail; |
4c74d1f8 | 1687 | if (!nvme_get_ns(ns)) |
85088c4a NC |
1688 | goto fail; |
1689 | if (!try_module_get(ns->ctrl->ops->module)) | |
1690 | goto fail_put_ns; | |
1691 | ||
c6424a90 | 1692 | return 0; |
85088c4a NC |
1693 | |
1694 | fail_put_ns: | |
1695 | nvme_put_ns(ns); | |
1696 | fail: | |
1697 | return -ENXIO; | |
1673f1f0 CH |
1698 | } |
1699 | ||
f5b9a51d | 1700 | static void nvme_ns_release(struct nvme_ns *ns) |
1673f1f0 | 1701 | { |
85088c4a NC |
1702 | |
1703 | module_put(ns->ctrl->ops->module); | |
1704 | nvme_put_ns(ns); | |
1673f1f0 CH |
1705 | } |
1706 | ||
05bdb996 | 1707 | static int nvme_open(struct gendisk *disk, blk_mode_t mode) |
f5b9a51d | 1708 | { |
d32e2bf8 | 1709 | return nvme_ns_open(disk->private_data); |
f5b9a51d CH |
1710 | } |
1711 | ||
ae220766 | 1712 | static void nvme_release(struct gendisk *disk) |
f5b9a51d CH |
1713 | { |
1714 | nvme_ns_release(disk->private_data); | |
1715 | } | |
1716 | ||
1496bd49 | 1717 | int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo) |
1673f1f0 CH |
1718 | { |
1719 | /* some standard values */ | |
1720 | geo->heads = 1 << 6; | |
1721 | geo->sectors = 1 << 5; | |
1722 | geo->cylinders = get_capacity(bdev->bd_disk) >> 11; | |
1723 | return 0; | |
1724 | } | |
1725 | ||
f467b48e | 1726 | static bool nvme_init_integrity(struct gendisk *disk, struct nvme_ns_head *head) |
1673f1f0 | 1727 | { |
cc72c442 | 1728 | struct blk_integrity integrity = { }; |
1673f1f0 | 1729 | |
414c62e2 CH |
1730 | blk_integrity_unregister(disk); |
1731 | ||
f467b48e CH |
1732 | if (!head->ms) |
1733 | return true; | |
1734 | ||
1735 | /* | |
1736 | * PI can always be supported as we can ask the controller to simply | |
1737 | * insert/strip it, which is not possible for other kinds of metadata. | |
1738 | */ | |
1739 | if (!IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) || | |
1740 | !(head->features & NVME_NS_METADATA_SUPPORTED)) | |
1741 | return nvme_ns_has_pi(head); | |
1742 | ||
d386aedc | 1743 | switch (head->pi_type) { |
1673f1f0 | 1744 | case NVME_NS_DPS_PI_TYPE3: |
d386aedc | 1745 | switch (head->guard_type) { |
4020aad8 KB |
1746 | case NVME_NVM_NS_16B_GUARD: |
1747 | integrity.profile = &t10_pi_type3_crc; | |
1748 | integrity.tag_size = sizeof(u16) + sizeof(u32); | |
1749 | integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE; | |
1750 | break; | |
1751 | case NVME_NVM_NS_64B_GUARD: | |
1752 | integrity.profile = &ext_pi_type3_crc64; | |
1753 | integrity.tag_size = sizeof(u16) + 6; | |
1754 | integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE; | |
1755 | break; | |
1756 | default: | |
1757 | integrity.profile = NULL; | |
1758 | break; | |
1759 | } | |
1673f1f0 CH |
1760 | break; |
1761 | case NVME_NS_DPS_PI_TYPE1: | |
1762 | case NVME_NS_DPS_PI_TYPE2: | |
d386aedc | 1763 | switch (head->guard_type) { |
4020aad8 KB |
1764 | case NVME_NVM_NS_16B_GUARD: |
1765 | integrity.profile = &t10_pi_type1_crc; | |
1766 | integrity.tag_size = sizeof(u16); | |
1767 | integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE; | |
1768 | break; | |
1769 | case NVME_NVM_NS_64B_GUARD: | |
1770 | integrity.profile = &ext_pi_type1_crc64; | |
1771 | integrity.tag_size = sizeof(u16); | |
1772 | integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE; | |
1773 | break; | |
1774 | default: | |
1775 | integrity.profile = NULL; | |
1776 | break; | |
1777 | } | |
1673f1f0 CH |
1778 | break; |
1779 | default: | |
1780 | integrity.profile = NULL; | |
1781 | break; | |
1782 | } | |
4020aad8 | 1783 | |
d386aedc | 1784 | integrity.tuple_size = head->ms; |
921e81db | 1785 | integrity.pi_offset = head->pi_offset; |
39b7baa4 | 1786 | blk_integrity_register(disk, &integrity); |
f467b48e | 1787 | return true; |
1673f1f0 | 1788 | } |
1673f1f0 | 1789 | |
d386aedc DW |
1790 | static void nvme_config_discard(struct nvme_ctrl *ctrl, struct gendisk *disk, |
1791 | struct nvme_ns_head *head) | |
1673f1f0 | 1792 | { |
26318571 | 1793 | struct request_queue *queue = disk->queue; |
f29886c2 | 1794 | u32 max_discard_sectors; |
30e5e929 | 1795 | |
f29886c2 CH |
1796 | if (ctrl->dmrsl && ctrl->dmrsl <= nvme_sect_to_lba(head, UINT_MAX)) { |
1797 | max_discard_sectors = nvme_lba_to_sect(head, ctrl->dmrsl); | |
1798 | } else if (ctrl->oncs & NVME_CTRL_ONCS_DSM) { | |
1799 | max_discard_sectors = UINT_MAX; | |
1800 | } else { | |
70200574 | 1801 | blk_queue_max_discard_sectors(queue, 0); |
3831761e JA |
1802 | return; |
1803 | } | |
1804 | ||
b35ba01e CH |
1805 | BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) < |
1806 | NVME_DSM_MAX_RANGES); | |
1807 | ||
d3074e9a CH |
1808 | /* |
1809 | * If discard is already enabled, don't reset queue limits. | |
1810 | * | |
1811 | * This works around the fact that the block layer can't cope well with | |
1812 | * updating the hardware limits when overridden through sysfs. This is | |
1813 | * harmless because discard limits in NVMe are purely advisory. | |
1814 | */ | |
70200574 | 1815 | if (queue->limits.max_discard_sectors) |
3831761e JA |
1816 | return; |
1817 | ||
f29886c2 | 1818 | blk_queue_max_discard_sectors(queue, max_discard_sectors); |
3b946fe1 CH |
1819 | if (ctrl->dmrl) |
1820 | blk_queue_max_discard_segments(queue, ctrl->dmrl); | |
1821 | else | |
1822 | blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES); | |
a4be9679 | 1823 | queue->limits.discard_granularity = queue_logical_block_size(queue); |
1673f1f0 CH |
1824 | } |
1825 | ||
002fab04 CH |
1826 | static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b) |
1827 | { | |
1828 | return uuid_equal(&a->uuid, &b->uuid) && | |
1829 | memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 && | |
71010c30 NC |
1830 | memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 && |
1831 | a->csi == b->csi; | |
002fab04 CH |
1832 | } |
1833 | ||
d386aedc DW |
1834 | static int nvme_init_ms(struct nvme_ctrl *ctrl, struct nvme_ns_head *head, |
1835 | struct nvme_id_ns *id) | |
d4609ea8 | 1836 | { |
4020aad8 KB |
1837 | bool first = id->dps & NVME_NS_DPS_PI_FIRST; |
1838 | unsigned lbaf = nvme_lbaf_index(id->flbas); | |
4020aad8 KB |
1839 | struct nvme_command c = { }; |
1840 | struct nvme_id_ns_nvm *nvm; | |
1841 | int ret = 0; | |
1842 | u32 elbaf; | |
1843 | ||
d386aedc DW |
1844 | head->pi_size = 0; |
1845 | head->ms = le16_to_cpu(id->lbaf[lbaf].ms); | |
4020aad8 | 1846 | if (!(ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)) { |
d386aedc DW |
1847 | head->pi_size = sizeof(struct t10_pi_tuple); |
1848 | head->guard_type = NVME_NVM_NS_16B_GUARD; | |
4020aad8 KB |
1849 | goto set_pi; |
1850 | } | |
d4609ea8 | 1851 | |
4020aad8 KB |
1852 | nvm = kzalloc(sizeof(*nvm), GFP_KERNEL); |
1853 | if (!nvm) | |
1854 | return -ENOMEM; | |
d4609ea8 | 1855 | |
4020aad8 | 1856 | c.identify.opcode = nvme_admin_identify; |
d386aedc | 1857 | c.identify.nsid = cpu_to_le32(head->ns_id); |
4020aad8 KB |
1858 | c.identify.cns = NVME_ID_CNS_CS_NS; |
1859 | c.identify.csi = NVME_CSI_NVM; | |
1860 | ||
d386aedc | 1861 | ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, nvm, sizeof(*nvm)); |
4020aad8 KB |
1862 | if (ret) |
1863 | goto free_data; | |
1864 | ||
1865 | elbaf = le32_to_cpu(nvm->elbaf[lbaf]); | |
1866 | ||
1867 | /* no support for storage tag formats right now */ | |
1868 | if (nvme_elbaf_sts(elbaf)) | |
1869 | goto free_data; | |
1870 | ||
d386aedc DW |
1871 | head->guard_type = nvme_elbaf_guard_type(elbaf); |
1872 | switch (head->guard_type) { | |
4020aad8 | 1873 | case NVME_NVM_NS_64B_GUARD: |
d386aedc | 1874 | head->pi_size = sizeof(struct crc64_pi_tuple); |
4020aad8 KB |
1875 | break; |
1876 | case NVME_NVM_NS_16B_GUARD: | |
d386aedc | 1877 | head->pi_size = sizeof(struct t10_pi_tuple); |
4020aad8 KB |
1878 | break; |
1879 | default: | |
1880 | break; | |
1881 | } | |
1882 | ||
1883 | free_data: | |
1884 | kfree(nvm); | |
1885 | set_pi: | |
921e81db | 1886 | if (head->pi_size && head->ms >= head->pi_size) |
d386aedc | 1887 | head->pi_type = id->dps & NVME_NS_DPS_PI_MASK; |
d4609ea8 | 1888 | else |
d386aedc | 1889 | head->pi_type = 0; |
d4609ea8 | 1890 | |
921e81db KJ |
1891 | if (first) |
1892 | head->pi_offset = 0; | |
1893 | else | |
1894 | head->pi_offset = head->ms - head->pi_size; | |
1895 | ||
4020aad8 KB |
1896 | return ret; |
1897 | } | |
1898 | ||
d386aedc DW |
1899 | static int nvme_configure_metadata(struct nvme_ctrl *ctrl, |
1900 | struct nvme_ns_head *head, struct nvme_id_ns *id) | |
4020aad8 | 1901 | { |
cd9aed60 | 1902 | int ret; |
4020aad8 | 1903 | |
d386aedc | 1904 | ret = nvme_init_ms(ctrl, head, id); |
cd9aed60 HR |
1905 | if (ret) |
1906 | return ret; | |
4020aad8 | 1907 | |
d386aedc DW |
1908 | head->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS); |
1909 | if (!head->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED)) | |
cd9aed60 | 1910 | return 0; |
363f6368 | 1911 | |
d4609ea8 CH |
1912 | if (ctrl->ops->flags & NVME_F_FABRICS) { |
1913 | /* | |
1914 | * The NVMe over Fabrics specification only supports metadata as | |
1915 | * part of the extended data LBA. We rely on HCA/HBA support to | |
1916 | * remap the separate metadata buffer from the block layer. | |
1917 | */ | |
1918 | if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT))) | |
cd9aed60 | 1919 | return 0; |
d39ad2a4 | 1920 | |
d386aedc | 1921 | head->features |= NVME_NS_EXT_LBAS; |
d39ad2a4 KB |
1922 | |
1923 | /* | |
1924 | * The current fabrics transport drivers support namespace | |
1925 | * metadata formats only if nvme_ns_has_pi() returns true. | |
1926 | * Suppress support for all other formats so the namespace will | |
1927 | * have a 0 capacity and not be usable through the block stack. | |
1928 | * | |
1929 | * Note, this check will need to be modified if any drivers | |
1930 | * gain the ability to use other metadata formats. | |
1931 | */ | |
d386aedc DW |
1932 | if (ctrl->max_integrity_segments && nvme_ns_has_pi(head)) |
1933 | head->features |= NVME_NS_METADATA_SUPPORTED; | |
d4609ea8 CH |
1934 | } else { |
1935 | /* | |
1936 | * For PCIe controllers, we can't easily remap the separate | |
1937 | * metadata buffer from the block layer and thus require a | |
1938 | * separate metadata buffer for block layer metadata/PI support. | |
1939 | * We allow extended LBAs for the passthrough interface, though. | |
1940 | */ | |
1941 | if (id->flbas & NVME_NS_FLBAS_META_EXT) | |
d386aedc | 1942 | head->features |= NVME_NS_EXT_LBAS; |
d4609ea8 | 1943 | else |
d386aedc | 1944 | head->features |= NVME_NS_METADATA_SUPPORTED; |
d4609ea8 | 1945 | } |
cd9aed60 | 1946 | return 0; |
d4609ea8 CH |
1947 | } |
1948 | ||
152694c8 CH |
1949 | static u32 nvme_max_drv_segments(struct nvme_ctrl *ctrl) |
1950 | { | |
1951 | return ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> SECTOR_SHIFT) + 1; | |
1952 | } | |
1953 | ||
658d9f7c CH |
1954 | static void nvme_set_queue_limits(struct nvme_ctrl *ctrl, |
1955 | struct request_queue *q) | |
1956 | { | |
c4485252 | 1957 | bool vwc = ctrl->vwc & NVME_CTRL_VWC_PRESENT; |
658d9f7c | 1958 | |
152694c8 CH |
1959 | blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors); |
1960 | blk_queue_max_segments(q, min_t(u32, USHRT_MAX, | |
1961 | min_not_zero(nvme_max_drv_segments(ctrl), ctrl->max_segments))); | |
f404dd92 | 1962 | blk_queue_max_integrity_segments(q, ctrl->max_integrity_segments); |
658d9f7c | 1963 | blk_queue_virt_boundary(q, NVME_CTRL_PAGE_SIZE - 1); |
52fde2c0 | 1964 | blk_queue_dma_alignment(q, 3); |
658d9f7c CH |
1965 | blk_queue_write_cache(q, vwc, vwc); |
1966 | } | |
1967 | ||
a5b1cd61 | 1968 | static bool nvme_update_disk_info(struct nvme_ns *ns, struct nvme_id_ns *id) |
24b0b58c | 1969 | { |
a5b1cd61 CH |
1970 | struct gendisk *disk = ns->disk; |
1971 | struct nvme_ns_head *head = ns->head; | |
d386aedc | 1972 | u32 bs = 1U << head->lba_shift; |
68ab60ca | 1973 | u32 atomic_bs, phys_bs, io_opt = 0; |
a5b1cd61 | 1974 | bool valid = true; |
24b0b58c | 1975 | |
13f0b26b CH |
1976 | /* |
1977 | * The block layer can't support LBA sizes larger than the page size | |
74fbc88e KB |
1978 | * or smaller than a sector size yet, so catch this early and don't |
1979 | * allow block I/O. | |
13f0b26b | 1980 | */ |
01d550f0 | 1981 | if (head->lba_shift > PAGE_SHIFT || head->lba_shift < SECTOR_SHIFT) { |
01fa0174 | 1982 | bs = (1 << 9); |
a5b1cd61 | 1983 | valid = false; |
01fa0174 | 1984 | } |
f9d5f457 | 1985 | |
68ab60ca | 1986 | atomic_bs = phys_bs = bs; |
81adb863 BVA |
1987 | if (id->nabo == 0) { |
1988 | /* | |
1989 | * Bit 1 indicates whether NAWUPF is defined for this namespace | |
1990 | * and whether it should be used instead of AWUPF. If NAWUPF == | |
1991 | * 0 then AWUPF must be used instead. | |
1992 | */ | |
92decf11 | 1993 | if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf) |
81adb863 BVA |
1994 | atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs; |
1995 | else | |
a5b1cd61 | 1996 | atomic_bs = (1 + ns->ctrl->subsys->awupf) * bs; |
81adb863 | 1997 | } |
31fdad7b | 1998 | |
92decf11 | 1999 | if (id->nsfeat & NVME_NS_FEAT_IO_OPT) { |
81adb863 | 2000 | /* NPWG = Namespace Preferred Write Granularity */ |
31fdad7b | 2001 | phys_bs = bs * (1 + le16_to_cpu(id->npwg)); |
81adb863 | 2002 | /* NOWS = Namespace Optimal Write Size */ |
31fdad7b | 2003 | io_opt = bs * (1 + le16_to_cpu(id->nows)); |
81adb863 BVA |
2004 | } |
2005 | ||
cee160fd | 2006 | blk_queue_logical_block_size(disk->queue, bs); |
81adb863 BVA |
2007 | /* |
2008 | * Linux filesystems assume writing a single physical block is | |
2009 | * an atomic operation. Hence limit the physical block size to the | |
2010 | * value of the Atomic Write Unit Power Fail parameter. | |
2011 | */ | |
2012 | blk_queue_physical_block_size(disk->queue, min(phys_bs, atomic_bs)); | |
2013 | blk_queue_io_min(disk->queue, phys_bs); | |
2014 | blk_queue_io_opt(disk->queue, io_opt); | |
cee160fd | 2015 | |
a5b1cd61 | 2016 | nvme_config_discard(ns->ctrl, disk, head); |
63dfa100 | 2017 | |
a5b1cd61 | 2018 | if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES) |
63dfa100 CH |
2019 | blk_queue_max_write_zeroes_sectors(disk->queue, UINT_MAX); |
2020 | else | |
2021 | blk_queue_max_write_zeroes_sectors(disk->queue, | |
a5b1cd61 CH |
2022 | ns->ctrl->max_zeroes_sectors); |
2023 | return valid; | |
24b0b58c CH |
2024 | } |
2025 | ||
1e4ea66a CH |
2026 | static bool nvme_ns_is_readonly(struct nvme_ns *ns, struct nvme_ns_info *info) |
2027 | { | |
2028 | return info->is_readonly || test_bit(NVME_NS_FORCE_RO, &ns->flags); | |
2029 | } | |
2030 | ||
e83d776f KB |
2031 | static inline bool nvme_first_scan(struct gendisk *disk) |
2032 | { | |
2033 | /* nvme_alloc_ns() scans the disk prior to adding it */ | |
50b4aecf | 2034 | return !disk_live(disk); |
e83d776f KB |
2035 | } |
2036 | ||
2037 | static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id) | |
2038 | { | |
2039 | struct nvme_ctrl *ctrl = ns->ctrl; | |
2040 | u32 iob; | |
2041 | ||
2042 | if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) && | |
2043 | is_power_of_2(ctrl->max_hw_sectors)) | |
2044 | iob = ctrl->max_hw_sectors; | |
2045 | else | |
0372dd4e | 2046 | iob = nvme_lba_to_sect(ns->head, le16_to_cpu(id->noiob)); |
e83d776f KB |
2047 | |
2048 | if (!iob) | |
2049 | return; | |
2050 | ||
2051 | if (!is_power_of_2(iob)) { | |
2052 | if (nvme_first_scan(ns->disk)) | |
2053 | pr_warn("%s: ignoring unaligned IO boundary:%u\n", | |
2054 | ns->disk->disk_name, iob); | |
2055 | return; | |
2056 | } | |
2057 | ||
2058 | if (blk_queue_is_zoned(ns->disk->queue)) { | |
2059 | if (nvme_first_scan(ns->disk)) | |
2060 | pr_warn("%s: ignoring zoned namespace IO boundary\n", | |
2061 | ns->disk->disk_name); | |
2062 | return; | |
2063 | } | |
2064 | ||
2065 | blk_queue_chunk_sectors(ns->queue, iob); | |
2066 | } | |
2067 | ||
eb867ee9 JG |
2068 | static int nvme_update_ns_info_generic(struct nvme_ns *ns, |
2069 | struct nvme_ns_info *info) | |
2070 | { | |
2071 | blk_mq_freeze_queue(ns->disk->queue); | |
2072 | nvme_set_queue_limits(ns->ctrl, ns->queue); | |
2073 | set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info)); | |
2074 | blk_mq_unfreeze_queue(ns->disk->queue); | |
2075 | ||
2076 | if (nvme_ns_head_multipath(ns->head)) { | |
2077 | blk_mq_freeze_queue(ns->head->disk->queue); | |
2078 | set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info)); | |
2079 | nvme_mpath_revalidate_paths(ns); | |
2080 | blk_stack_limits(&ns->head->disk->queue->limits, | |
2081 | &ns->queue->limits, 0); | |
2082 | ns->head->disk->flags |= GENHD_FL_HIDDEN; | |
2083 | blk_mq_unfreeze_queue(ns->head->disk->queue); | |
2084 | } | |
2085 | ||
2086 | /* Hide the block-interface for these devices */ | |
2087 | ns->disk->flags |= GENHD_FL_HIDDEN; | |
2088 | set_bit(NVME_NS_READY, &ns->flags); | |
2089 | ||
2090 | return 0; | |
2091 | } | |
2092 | ||
1a893c2b CH |
2093 | static int nvme_update_ns_info_block(struct nvme_ns *ns, |
2094 | struct nvme_ns_info *info) | |
ac81bfa9 | 2095 | { |
1a893c2b | 2096 | struct nvme_id_ns *id; |
a5b1cd61 | 2097 | sector_t capacity; |
1a893c2b | 2098 | unsigned lbaf; |
240e6ee2 | 2099 | int ret; |
1673f1f0 | 2100 | |
1a893c2b CH |
2101 | ret = nvme_identify_ns(ns->ctrl, info->nsid, &id); |
2102 | if (ret) | |
2103 | return ret; | |
2104 | ||
d8b90d60 EM |
2105 | if (id->ncap == 0) { |
2106 | /* namespace not allocated or attached */ | |
2107 | info->is_removed = true; | |
2108 | ret = -ENODEV; | |
2109 | goto error; | |
2110 | } | |
2111 | ||
f9d5f457 | 2112 | blk_mq_freeze_queue(ns->disk->queue); |
1a893c2b | 2113 | lbaf = nvme_lbaf_index(id->flbas); |
9419e71b | 2114 | ns->head->lba_shift = id->lbaf[lbaf].ds; |
a1a825ab | 2115 | ns->head->nuse = le64_to_cpu(id->nuse); |
a5b1cd61 CH |
2116 | capacity = nvme_lba_to_sect(ns->head, le64_to_cpu(id->nsze)); |
2117 | ||
8b7c0ff2 | 2118 | nvme_set_queue_limits(ns->ctrl, ns->queue); |
38adf94e | 2119 | |
d386aedc | 2120 | ret = nvme_configure_metadata(ns->ctrl, ns->head, id); |
cd9aed60 HR |
2121 | if (ret < 0) { |
2122 | blk_mq_unfreeze_queue(ns->disk->queue); | |
2123 | goto out; | |
2124 | } | |
73d90386 | 2125 | nvme_set_chunk_sectors(ns, id); |
a5b1cd61 CH |
2126 | if (!nvme_update_disk_info(ns, id)) |
2127 | capacity = 0; | |
2128 | ||
2129 | /* | |
2130 | * Register a metadata profile for PI, or the plain non-integrity NVMe | |
2131 | * metadata masquerading as Type 0 if supported, otherwise reject block | |
2132 | * I/O to namespaces with metadata except when the namespace supports | |
2133 | * PI, as it can strip/insert in that case. | |
2134 | */ | |
2135 | if (!nvme_init_integrity(ns->disk, ns->head)) | |
2136 | capacity = 0; | |
2137 | ||
2138 | set_capacity_and_notify(ns->disk, capacity); | |
73d90386 | 2139 | |
8b7c0ff2 | 2140 | if (ns->head->ids.csi == NVME_CSI_ZNS) { |
d525c3c0 | 2141 | ret = nvme_update_zone_info(ns, lbaf); |
e06b425b CH |
2142 | if (ret) { |
2143 | blk_mq_unfreeze_queue(ns->disk->queue); | |
2144 | goto out; | |
2145 | } | |
71010c30 NC |
2146 | } |
2147 | ||
1b96f862 CH |
2148 | /* |
2149 | * Only set the DEAC bit if the device guarantees that reads from | |
2150 | * deallocated data return zeroes. While the DEAC bit does not | |
2151 | * require that, it must be a no-op if reads from deallocated data | |
2152 | * do not return zeroes. | |
2153 | */ | |
2154 | if ((id->dlfeat & 0x7) == 0x1 && (id->dlfeat & (1 << 3))) | |
9419e71b | 2155 | ns->head->features |= NVME_NS_DEAC; |
1e4ea66a | 2156 | set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info)); |
e7d65803 | 2157 | set_bit(NVME_NS_READY, &ns->flags); |
f9d5f457 | 2158 | blk_mq_unfreeze_queue(ns->disk->queue); |
1673f1f0 | 2159 | |
3a9967ba | 2160 | if (blk_queue_is_zoned(ns->queue)) { |
1b2f5d5d | 2161 | ret = blk_revalidate_disk_zones(ns->disk, NULL); |
8685699c | 2162 | if (ret && !nvme_first_scan(ns->disk)) |
e06b425b | 2163 | goto out; |
b29f8485 MG |
2164 | } |
2165 | ||
30897388 | 2166 | if (nvme_ns_head_multipath(ns->head)) { |
f9d5f457 | 2167 | blk_mq_freeze_queue(ns->head->disk->queue); |
8f03cfa1 CH |
2168 | nvme_init_integrity(ns->head->disk, ns->head); |
2169 | set_capacity_and_notify(ns->head->disk, get_capacity(ns->disk)); | |
1e4ea66a | 2170 | set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info)); |
e7d65803 | 2171 | nvme_mpath_revalidate_paths(ns); |
b9b1a5d7 CH |
2172 | blk_stack_limits(&ns->head->disk->queue->limits, |
2173 | &ns->queue->limits, 0); | |
471aa704 | 2174 | disk_update_readahead(ns->head->disk); |
f9d5f457 | 2175 | blk_mq_unfreeze_queue(ns->head->disk->queue); |
8f676b85 | 2176 | } |
ac81bfa9 | 2177 | |
e06b425b CH |
2178 | ret = 0; |
2179 | out: | |
a9e0e6bc CH |
2180 | /* |
2181 | * If probing fails due an unsupported feature, hide the block device, | |
2182 | * but still allow other access. | |
2183 | */ | |
2184 | if (ret == -ENODEV) { | |
2185 | ns->disk->flags |= GENHD_FL_HIDDEN; | |
602e57c9 | 2186 | set_bit(NVME_NS_READY, &ns->flags); |
a9e0e6bc CH |
2187 | ret = 0; |
2188 | } | |
d8b90d60 EM |
2189 | |
2190 | error: | |
1a893c2b | 2191 | kfree(id); |
240e6ee2 KB |
2192 | return ret; |
2193 | } | |
2194 | ||
1a893c2b CH |
2195 | static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_ns_info *info) |
2196 | { | |
2197 | switch (info->ids.csi) { | |
2198 | case NVME_CSI_ZNS: | |
2199 | if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) { | |
eb867ee9 JG |
2200 | dev_info(ns->ctrl->device, |
2201 | "block device for nsid %u not supported without CONFIG_BLK_DEV_ZONED\n", | |
1a893c2b | 2202 | info->nsid); |
eb867ee9 | 2203 | return nvme_update_ns_info_generic(ns, info); |
1a893c2b CH |
2204 | } |
2205 | return nvme_update_ns_info_block(ns, info); | |
2206 | case NVME_CSI_NVM: | |
2207 | return nvme_update_ns_info_block(ns, info); | |
2208 | default: | |
eb867ee9 JG |
2209 | dev_info(ns->ctrl->device, |
2210 | "block device for nsid %u not supported (csi %u)\n", | |
2211 | info->nsid, info->ids.csi); | |
2212 | return nvme_update_ns_info_generic(ns, info); | |
1a893c2b CH |
2213 | } |
2214 | } | |
2215 | ||
a98e58e5 | 2216 | #ifdef CONFIG_BLK_SED_OPAL |
94cc781f | 2217 | static int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
4f1244c8 | 2218 | bool send) |
a98e58e5 | 2219 | { |
4f1244c8 | 2220 | struct nvme_ctrl *ctrl = data; |
cc72c442 | 2221 | struct nvme_command cmd = { }; |
a98e58e5 | 2222 | |
a98e58e5 SB |
2223 | if (send) |
2224 | cmd.common.opcode = nvme_admin_security_send; | |
2225 | else | |
2226 | cmd.common.opcode = nvme_admin_security_recv; | |
a98e58e5 | 2227 | cmd.common.nsid = 0; |
b7c8f366 CK |
2228 | cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8); |
2229 | cmd.common.cdw11 = cpu_to_le32(len); | |
a98e58e5 | 2230 | |
6b46fa02 | 2231 | return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len, |
bd2687f2 | 2232 | NVME_QID_ANY, NVME_SUBMIT_AT_HEAD); |
a98e58e5 | 2233 | } |
94cc781f CH |
2234 | |
2235 | static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended) | |
2236 | { | |
2237 | if (ctrl->oacs & NVME_CTRL_OACS_SEC_SUPP) { | |
2238 | if (!ctrl->opal_dev) | |
2239 | ctrl->opal_dev = init_opal_dev(ctrl, &nvme_sec_submit); | |
2240 | else if (was_suspended) | |
2241 | opal_unlock_from_suspend(ctrl->opal_dev); | |
2242 | } else { | |
2243 | free_opal_dev(ctrl->opal_dev); | |
2244 | ctrl->opal_dev = NULL; | |
2245 | } | |
2246 | } | |
2247 | #else | |
2248 | static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended) | |
2249 | { | |
2250 | } | |
a98e58e5 SB |
2251 | #endif /* CONFIG_BLK_SED_OPAL */ |
2252 | ||
8b4fb0f9 CH |
2253 | #ifdef CONFIG_BLK_DEV_ZONED |
2254 | static int nvme_report_zones(struct gendisk *disk, sector_t sector, | |
2255 | unsigned int nr_zones, report_zones_cb cb, void *data) | |
2256 | { | |
2257 | return nvme_ns_report_zones(disk->private_data, sector, nr_zones, cb, | |
2258 | data); | |
2259 | } | |
2260 | #else | |
2261 | #define nvme_report_zones NULL | |
2262 | #endif /* CONFIG_BLK_DEV_ZONED */ | |
2263 | ||
942e21c0 | 2264 | const struct block_device_operations nvme_bdev_ops = { |
1673f1f0 CH |
2265 | .owner = THIS_MODULE, |
2266 | .ioctl = nvme_ioctl, | |
a25d4261 | 2267 | .compat_ioctl = blkdev_compat_ptr_ioctl, |
1673f1f0 CH |
2268 | .open = nvme_open, |
2269 | .release = nvme_release, | |
2270 | .getgeo = nvme_getgeo, | |
240e6ee2 | 2271 | .report_zones = nvme_report_zones, |
1673f1f0 CH |
2272 | .pr_ops = &nvme_pr_ops, |
2273 | }; | |
2274 | ||
e6d275de CH |
2275 | static int nvme_wait_ready(struct nvme_ctrl *ctrl, u32 mask, u32 val, |
2276 | u32 timeout, const char *op) | |
5fd4ce1b | 2277 | { |
e6d275de CH |
2278 | unsigned long timeout_jiffies = jiffies + timeout * HZ; |
2279 | u32 csts; | |
5fd4ce1b CH |
2280 | int ret; |
2281 | ||
2282 | while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) { | |
0df1e4f5 KB |
2283 | if (csts == ~0) |
2284 | return -ENODEV; | |
e6d275de | 2285 | if ((csts & mask) == val) |
5fd4ce1b CH |
2286 | break; |
2287 | ||
3e98c244 | 2288 | usleep_range(1000, 2000); |
5fd4ce1b CH |
2289 | if (fatal_signal_pending(current)) |
2290 | return -EINTR; | |
354201c5 | 2291 | if (time_after(jiffies, timeout_jiffies)) { |
1b3c47c1 | 2292 | dev_err(ctrl->device, |
94d2e705 | 2293 | "Device not ready; aborting %s, CSTS=0x%x\n", |
e6d275de | 2294 | op, csts); |
5fd4ce1b CH |
2295 | return -ENODEV; |
2296 | } | |
2297 | } | |
2298 | ||
2299 | return ret; | |
2300 | } | |
2301 | ||
285b6e9b | 2302 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown) |
5fd4ce1b CH |
2303 | { |
2304 | int ret; | |
2305 | ||
2306 | ctrl->ctrl_config &= ~NVME_CC_SHN_MASK; | |
285b6e9b CH |
2307 | if (shutdown) |
2308 | ctrl->ctrl_config |= NVME_CC_SHN_NORMAL; | |
2309 | else | |
2310 | ctrl->ctrl_config &= ~NVME_CC_ENABLE; | |
5fd4ce1b CH |
2311 | |
2312 | ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); | |
2313 | if (ret) | |
2314 | return ret; | |
54adc010 | 2315 | |
285b6e9b CH |
2316 | if (shutdown) { |
2317 | return nvme_wait_ready(ctrl, NVME_CSTS_SHST_MASK, | |
2318 | NVME_CSTS_SHST_CMPLT, | |
2319 | ctrl->shutdown_timeout, "shutdown"); | |
2320 | } | |
b5a10c5f | 2321 | if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY) |
54adc010 | 2322 | msleep(NVME_QUIRK_DELAY_AMOUNT); |
e6d275de CH |
2323 | return nvme_wait_ready(ctrl, NVME_CSTS_RDY, 0, |
2324 | (NVME_CAP_TIMEOUT(ctrl->cap) + 1) / 2, "reset"); | |
5fd4ce1b | 2325 | } |
576d55d6 | 2326 | EXPORT_SYMBOL_GPL(nvme_disable_ctrl); |
5fd4ce1b | 2327 | |
c0f2f45b | 2328 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl) |
5fd4ce1b | 2329 | { |
6c3c05b0 | 2330 | unsigned dev_page_min; |
354201c5 | 2331 | u32 timeout; |
5fd4ce1b CH |
2332 | int ret; |
2333 | ||
c0f2f45b SG |
2334 | ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap); |
2335 | if (ret) { | |
2336 | dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret); | |
2337 | return ret; | |
2338 | } | |
2339 | dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12; | |
2340 | ||
6c3c05b0 | 2341 | if (NVME_CTRL_PAGE_SHIFT < dev_page_min) { |
1b3c47c1 | 2342 | dev_err(ctrl->device, |
5fd4ce1b | 2343 | "Minimum device page size %u too large for host (%u)\n", |
6c3c05b0 | 2344 | 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT); |
5fd4ce1b CH |
2345 | return -ENODEV; |
2346 | } | |
2347 | ||
71010c30 NC |
2348 | if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI) |
2349 | ctrl->ctrl_config = NVME_CC_CSS_CSI; | |
2350 | else | |
2351 | ctrl->ctrl_config = NVME_CC_CSS_NVM; | |
354201c5 | 2352 | |
6cc834ba KB |
2353 | if (ctrl->cap & NVME_CAP_CRMS_CRWMS && ctrl->cap & NVME_CAP_CRMS_CRIMS) |
2354 | ctrl->ctrl_config |= NVME_CC_CRIME; | |
354201c5 | 2355 | |
6c3c05b0 | 2356 | ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; |
60b43f62 | 2357 | ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE; |
5fd4ce1b | 2358 | ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
aa41d2fe NC |
2359 | ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); |
2360 | if (ret) | |
2361 | return ret; | |
5fd4ce1b | 2362 | |
aa41d2fe NC |
2363 | /* Flush write to device (required if transport is PCI) */ |
2364 | ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config); | |
2365 | if (ret) | |
2366 | return ret; | |
2367 | ||
6cc834ba KB |
2368 | /* CAP value may change after initial CC write */ |
2369 | ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap); | |
2370 | if (ret) | |
2371 | return ret; | |
2372 | ||
2373 | timeout = NVME_CAP_TIMEOUT(ctrl->cap); | |
2374 | if (ctrl->cap & NVME_CAP_CRMS_CRWMS) { | |
2375 | u32 crto, ready_timeout; | |
2376 | ||
2377 | ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CRTO, &crto); | |
2378 | if (ret) { | |
2379 | dev_err(ctrl->device, "Reading CRTO failed (%d)\n", | |
2380 | ret); | |
2381 | return ret; | |
2382 | } | |
2383 | ||
2384 | /* | |
2385 | * CRTO should always be greater or equal to CAP.TO, but some | |
2386 | * devices are known to get this wrong. Use the larger of the | |
2387 | * two values. | |
2388 | */ | |
2389 | if (ctrl->ctrl_config & NVME_CC_CRIME) | |
2390 | ready_timeout = NVME_CRTO_CRIMT(crto); | |
2391 | else | |
2392 | ready_timeout = NVME_CRTO_CRWMT(crto); | |
2393 | ||
2394 | if (ready_timeout < timeout) | |
2395 | dev_warn_once(ctrl->device, "bad crto:%x cap:%llx\n", | |
2396 | crto, ctrl->cap); | |
2397 | else | |
2398 | timeout = ready_timeout; | |
2399 | } | |
2400 | ||
aa41d2fe | 2401 | ctrl->ctrl_config |= NVME_CC_ENABLE; |
5fd4ce1b CH |
2402 | ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config); |
2403 | if (ret) | |
2404 | return ret; | |
e6d275de CH |
2405 | return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY, |
2406 | (timeout + 1) / 2, "initialisation"); | |
5fd4ce1b | 2407 | } |
576d55d6 | 2408 | EXPORT_SYMBOL_GPL(nvme_enable_ctrl); |
5fd4ce1b | 2409 | |
dbf86b39 JD |
2410 | static int nvme_configure_timestamp(struct nvme_ctrl *ctrl) |
2411 | { | |
2412 | __le64 ts; | |
2413 | int ret; | |
2414 | ||
2415 | if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP)) | |
2416 | return 0; | |
2417 | ||
2418 | ts = cpu_to_le64(ktime_to_ms(ktime_get_real())); | |
2419 | ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts), | |
2420 | NULL); | |
2421 | if (ret) | |
2422 | dev_warn_once(ctrl->device, | |
2423 | "could not set timestamp (%d)\n", ret); | |
2424 | return ret; | |
2425 | } | |
2426 | ||
4020aad8 | 2427 | static int nvme_configure_host_options(struct nvme_ctrl *ctrl) |
49cd84b6 KB |
2428 | { |
2429 | struct nvme_feat_host_behavior *host; | |
4020aad8 | 2430 | u8 acre = 0, lbafee = 0; |
49cd84b6 KB |
2431 | int ret; |
2432 | ||
2433 | /* Don't bother enabling the feature if retry delay is not reported */ | |
4020aad8 KB |
2434 | if (ctrl->crdt[0]) |
2435 | acre = NVME_ENABLE_ACRE; | |
2436 | if (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS) | |
2437 | lbafee = NVME_ENABLE_LBAFEE; | |
2438 | ||
2439 | if (!acre && !lbafee) | |
49cd84b6 KB |
2440 | return 0; |
2441 | ||
2442 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
2443 | if (!host) | |
2444 | return 0; | |
2445 | ||
4020aad8 KB |
2446 | host->acre = acre; |
2447 | host->lbafee = lbafee; | |
49cd84b6 KB |
2448 | ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0, |
2449 | host, sizeof(*host), NULL); | |
2450 | kfree(host); | |
2451 | return ret; | |
2452 | } | |
2453 | ||
ebd8a93a AB |
2454 | /* |
2455 | * The function checks whether the given total (exlat + enlat) latency of | |
2456 | * a power state allows the latter to be used as an APST transition target. | |
2457 | * It does so by comparing the latency to the primary and secondary latency | |
2458 | * tolerances defined by module params. If there's a match, the corresponding | |
2459 | * timeout value is returned and the matching tolerance index (1 or 2) is | |
2460 | * reported. | |
2461 | */ | |
2462 | static bool nvme_apst_get_transition_time(u64 total_latency, | |
2463 | u64 *transition_time, unsigned *last_index) | |
2464 | { | |
2465 | if (total_latency <= apst_primary_latency_tol_us) { | |
2466 | if (*last_index == 1) | |
2467 | return false; | |
2468 | *last_index = 1; | |
2469 | *transition_time = apst_primary_timeout_ms; | |
2470 | return true; | |
2471 | } | |
2472 | if (apst_secondary_timeout_ms && | |
2473 | total_latency <= apst_secondary_latency_tol_us) { | |
2474 | if (*last_index <= 2) | |
2475 | return false; | |
2476 | *last_index = 2; | |
2477 | *transition_time = apst_secondary_timeout_ms; | |
2478 | return true; | |
2479 | } | |
2480 | return false; | |
2481 | } | |
2482 | ||
60df5de9 CH |
2483 | /* |
2484 | * APST (Autonomous Power State Transition) lets us program a table of power | |
2485 | * state transitions that the controller will perform automatically. | |
ebd8a93a AB |
2486 | * |
2487 | * Depending on module params, one of the two supported techniques will be used: | |
2488 | * | |
2489 | * - If the parameters provide explicit timeouts and tolerances, they will be | |
2490 | * used to build a table with up to 2 non-operational states to transition to. | |
2491 | * The default parameter values were selected based on the values used by | |
2492 | * Microsoft's and Intel's NVMe drivers. Yet, since we don't implement dynamic | |
2493 | * regeneration of the APST table in the event of switching between external | |
2494 | * and battery power, the timeouts and tolerances reflect a compromise | |
2495 | * between values used by Microsoft for AC and battery scenarios. | |
2496 | * - If not, we'll configure the table with a simple heuristic: we are willing | |
2497 | * to spend at most 2% of the time transitioning between power states. | |
2498 | * Therefore, when running in any given state, we will enter the next | |
2499 | * lower-power non-operational state after waiting 50 * (enlat + exlat) | |
2500 | * microseconds, as long as that state's exit latency is under the requested | |
2501 | * maximum latency. | |
60df5de9 CH |
2502 | * |
2503 | * We will not autonomously enter any non-operational state for which the total | |
2504 | * latency exceeds ps_max_latency_us. | |
2505 | * | |
2506 | * Users can set ps_max_latency_us to zero to turn off APST. | |
2507 | */ | |
634b8325 | 2508 | static int nvme_configure_apst(struct nvme_ctrl *ctrl) |
c5552fde | 2509 | { |
c5552fde | 2510 | struct nvme_feat_auto_pst *table; |
60df5de9 | 2511 | unsigned apste = 0; |
fb0dc399 | 2512 | u64 max_lat_us = 0; |
60df5de9 | 2513 | __le64 target = 0; |
fb0dc399 | 2514 | int max_ps = -1; |
60df5de9 | 2515 | int state; |
c5552fde | 2516 | int ret; |
ebd8a93a | 2517 | unsigned last_lt_index = UINT_MAX; |
c5552fde AL |
2518 | |
2519 | /* | |
2520 | * If APST isn't supported or if we haven't been initialized yet, | |
2521 | * then don't do anything. | |
2522 | */ | |
2523 | if (!ctrl->apsta) | |
634b8325 | 2524 | return 0; |
c5552fde AL |
2525 | |
2526 | if (ctrl->npss > 31) { | |
2527 | dev_warn(ctrl->device, "NPSS is invalid; not using APST\n"); | |
634b8325 | 2528 | return 0; |
c5552fde AL |
2529 | } |
2530 | ||
2531 | table = kzalloc(sizeof(*table), GFP_KERNEL); | |
2532 | if (!table) | |
634b8325 | 2533 | return 0; |
c5552fde | 2534 | |
76a5af84 | 2535 | if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) { |
c5552fde | 2536 | /* Turn off APST. */ |
fb0dc399 | 2537 | dev_dbg(ctrl->device, "APST disabled\n"); |
60df5de9 CH |
2538 | goto done; |
2539 | } | |
c5552fde | 2540 | |
60df5de9 CH |
2541 | /* |
2542 | * Walk through all states from lowest- to highest-power. | |
2543 | * According to the spec, lower-numbered states use more power. NPSS, | |
2544 | * despite the name, is the index of the lowest-power state, not the | |
2545 | * number of states. | |
2546 | */ | |
2547 | for (state = (int)ctrl->npss; state >= 0; state--) { | |
2548 | u64 total_latency_us, exit_latency_us, transition_ms; | |
da87591b | 2549 | |
60df5de9 CH |
2550 | if (target) |
2551 | table->entries[state] = target; | |
c5552fde | 2552 | |
c5552fde | 2553 | /* |
60df5de9 CH |
2554 | * Don't allow transitions to the deepest state if it's quirked |
2555 | * off. | |
c5552fde | 2556 | */ |
60df5de9 CH |
2557 | if (state == ctrl->npss && |
2558 | (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) | |
2559 | continue; | |
fb0dc399 | 2560 | |
60df5de9 CH |
2561 | /* |
2562 | * Is this state a useful non-operational state for higher-power | |
2563 | * states to autonomously transition to? | |
2564 | */ | |
2565 | if (!(ctrl->psd[state].flags & NVME_PS_FLAGS_NON_OP_STATE)) | |
2566 | continue; | |
fb0dc399 | 2567 | |
60df5de9 CH |
2568 | exit_latency_us = (u64)le32_to_cpu(ctrl->psd[state].exit_lat); |
2569 | if (exit_latency_us > ctrl->ps_max_latency_us) | |
2570 | continue; | |
c5552fde | 2571 | |
60df5de9 CH |
2572 | total_latency_us = exit_latency_us + |
2573 | le32_to_cpu(ctrl->psd[state].entry_lat); | |
fb0dc399 | 2574 | |
60df5de9 | 2575 | /* |
ebd8a93a AB |
2576 | * This state is good. It can be used as the APST idle target |
2577 | * for higher power states. | |
60df5de9 | 2578 | */ |
ebd8a93a AB |
2579 | if (apst_primary_timeout_ms && apst_primary_latency_tol_us) { |
2580 | if (!nvme_apst_get_transition_time(total_latency_us, | |
2581 | &transition_ms, &last_lt_index)) | |
2582 | continue; | |
2583 | } else { | |
2584 | transition_ms = total_latency_us + 19; | |
2585 | do_div(transition_ms, 20); | |
2586 | if (transition_ms > (1 << 24) - 1) | |
2587 | transition_ms = (1 << 24) - 1; | |
2588 | } | |
60df5de9 CH |
2589 | |
2590 | target = cpu_to_le64((state << 3) | (transition_ms << 8)); | |
2591 | if (max_ps == -1) | |
2592 | max_ps = state; | |
2593 | if (total_latency_us > max_lat_us) | |
2594 | max_lat_us = total_latency_us; | |
c5552fde AL |
2595 | } |
2596 | ||
60df5de9 CH |
2597 | if (max_ps == -1) |
2598 | dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n"); | |
2599 | else | |
2600 | dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n", | |
2601 | max_ps, max_lat_us, (int)sizeof(*table), table); | |
2602 | apste = 1; | |
2603 | ||
2604 | done: | |
c5552fde AL |
2605 | ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste, |
2606 | table, sizeof(*table), NULL); | |
2607 | if (ret) | |
2608 | dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret); | |
c5552fde | 2609 | kfree(table); |
634b8325 | 2610 | return ret; |
c5552fde AL |
2611 | } |
2612 | ||
2613 | static void nvme_set_latency_tolerance(struct device *dev, s32 val) | |
2614 | { | |
2615 | struct nvme_ctrl *ctrl = dev_get_drvdata(dev); | |
2616 | u64 latency; | |
2617 | ||
2618 | switch (val) { | |
2619 | case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT: | |
2620 | case PM_QOS_LATENCY_ANY: | |
2621 | latency = U64_MAX; | |
2622 | break; | |
2623 | ||
2624 | default: | |
2625 | latency = val; | |
2626 | } | |
2627 | ||
2628 | if (ctrl->ps_max_latency_us != latency) { | |
2629 | ctrl->ps_max_latency_us = latency; | |
e6e7f7ac | 2630 | if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE) |
53fe2a30 | 2631 | nvme_configure_apst(ctrl); |
c5552fde AL |
2632 | } |
2633 | } | |
2634 | ||
bd4da3ab AL |
2635 | struct nvme_core_quirk_entry { |
2636 | /* | |
2637 | * NVMe model and firmware strings are padded with spaces. For | |
2638 | * simplicity, strings in the quirk table are padded with NULLs | |
2639 | * instead. | |
2640 | */ | |
2641 | u16 vid; | |
2642 | const char *mn; | |
2643 | const char *fr; | |
2644 | unsigned long quirks; | |
2645 | }; | |
2646 | ||
2647 | static const struct nvme_core_quirk_entry core_quirks[] = { | |
c5552fde | 2648 | { |
be56945c AL |
2649 | /* |
2650 | * This Toshiba device seems to die using any APST states. See: | |
2651 | * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11 | |
2652 | */ | |
2653 | .vid = 0x1179, | |
2654 | .mn = "THNSF5256GPUK TOSHIBA", | |
c5552fde | 2655 | .quirks = NVME_QUIRK_NO_APST, |
cb32de1b ML |
2656 | }, |
2657 | { | |
2658 | /* | |
2659 | * This LiteON CL1-3D*-Q11 firmware version has a race | |
2660 | * condition associated with actions related to suspend to idle | |
2661 | * LiteON has resolved the problem in future firmware | |
2662 | */ | |
2663 | .vid = 0x14a4, | |
2664 | .fr = "22301111", | |
2665 | .quirks = NVME_QUIRK_SIMPLE_SUSPEND, | |
5a6254d5 EM |
2666 | }, |
2667 | { | |
2668 | /* | |
2669 | * This Kioxia CD6-V Series / HPE PE8030 device times out and | |
2670 | * aborts I/O during any load, but more easily reproducible | |
2671 | * with discards (fstrim). | |
2672 | * | |
2673 | * The device is left in a state where it is also not possible | |
2674 | * to use "nvme set-feature" to disable APST, but booting with | |
2675 | * nvme_core.default_ps_max_latency=0 works. | |
2676 | */ | |
2677 | .vid = 0x1e0f, | |
2678 | .mn = "KCD6XVUL6T40", | |
2679 | .quirks = NVME_QUIRK_NO_APST, | |
e6487833 CH |
2680 | }, |
2681 | { | |
2682 | /* | |
2683 | * The external Samsung X5 SSD fails initialization without a | |
2684 | * delay before checking if it is ready and has a whole set of | |
2685 | * other problems. To make this even more interesting, it | |
2686 | * shares the PCI ID with internal Samsung 970 Evo Plus that | |
2687 | * does not need or want these quirks. | |
2688 | */ | |
2689 | .vid = 0x144d, | |
2690 | .mn = "Samsung Portable SSD X5", | |
2691 | .quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | | |
2692 | NVME_QUIRK_NO_DEEPEST_PS | | |
2693 | NVME_QUIRK_IGNORE_DEV_SUBNQN, | |
be56945c | 2694 | } |
bd4da3ab AL |
2695 | }; |
2696 | ||
2697 | /* match is null-terminated but idstr is space-padded. */ | |
2698 | static bool string_matches(const char *idstr, const char *match, size_t len) | |
2699 | { | |
2700 | size_t matchlen; | |
2701 | ||
2702 | if (!match) | |
2703 | return true; | |
2704 | ||
2705 | matchlen = strlen(match); | |
2706 | WARN_ON_ONCE(matchlen > len); | |
2707 | ||
2708 | if (memcmp(idstr, match, matchlen)) | |
2709 | return false; | |
2710 | ||
2711 | for (; matchlen < len; matchlen++) | |
2712 | if (idstr[matchlen] != ' ') | |
2713 | return false; | |
2714 | ||
2715 | return true; | |
2716 | } | |
2717 | ||
2718 | static bool quirk_matches(const struct nvme_id_ctrl *id, | |
2719 | const struct nvme_core_quirk_entry *q) | |
2720 | { | |
2721 | return q->vid == le16_to_cpu(id->vid) && | |
2722 | string_matches(id->mn, q->mn, sizeof(id->mn)) && | |
2723 | string_matches(id->fr, q->fr, sizeof(id->fr)); | |
2724 | } | |
2725 | ||
ab9e00cc CH |
2726 | static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl, |
2727 | struct nvme_id_ctrl *id) | |
180de007 CH |
2728 | { |
2729 | size_t nqnlen; | |
2730 | int off; | |
2731 | ||
6299358d JD |
2732 | if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) { |
2733 | nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE); | |
2734 | if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) { | |
a8817cc0 | 2735 | strscpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE); |
6299358d JD |
2736 | return; |
2737 | } | |
180de007 | 2738 | |
6299358d JD |
2739 | if (ctrl->vs >= NVME_VS(1, 2, 1)) |
2740 | dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n"); | |
2741 | } | |
180de007 | 2742 | |
1abc6961 LB |
2743 | /* |
2744 | * Generate a "fake" NQN similar to the one in Section 4.5 of the NVMe | |
2745 | * Base Specification 2.0. It is slightly different from the format | |
2746 | * specified there due to historic reasons, and we can't change it now. | |
2747 | */ | |
ab9e00cc | 2748 | off = snprintf(subsys->subnqn, NVMF_NQN_SIZE, |
3da584f5 | 2749 | "nqn.2014.08.org.nvmexpress:%04x%04x", |
180de007 | 2750 | le16_to_cpu(id->vid), le16_to_cpu(id->ssvid)); |
ab9e00cc | 2751 | memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn)); |
180de007 | 2752 | off += sizeof(id->sn); |
ab9e00cc | 2753 | memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn)); |
180de007 | 2754 | off += sizeof(id->mn); |
ab9e00cc CH |
2755 | memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off); |
2756 | } | |
2757 | ||
e654dfd3 | 2758 | static void nvme_release_subsystem(struct device *dev) |
ab9e00cc | 2759 | { |
e654dfd3 LG |
2760 | struct nvme_subsystem *subsys = |
2761 | container_of(dev, struct nvme_subsystem, dev); | |
2762 | ||
733e4b69 | 2763 | if (subsys->instance >= 0) |
8b850475 | 2764 | ida_free(&nvme_instance_ida, subsys->instance); |
ab9e00cc CH |
2765 | kfree(subsys); |
2766 | } | |
2767 | ||
ab9e00cc CH |
2768 | static void nvme_destroy_subsystem(struct kref *ref) |
2769 | { | |
2770 | struct nvme_subsystem *subsys = | |
2771 | container_of(ref, struct nvme_subsystem, ref); | |
2772 | ||
2773 | mutex_lock(&nvme_subsystems_lock); | |
2774 | list_del(&subsys->entry); | |
2775 | mutex_unlock(&nvme_subsystems_lock); | |
2776 | ||
ed754e5d | 2777 | ida_destroy(&subsys->ns_ida); |
ab9e00cc CH |
2778 | device_del(&subsys->dev); |
2779 | put_device(&subsys->dev); | |
2780 | } | |
2781 | ||
2782 | static void nvme_put_subsystem(struct nvme_subsystem *subsys) | |
2783 | { | |
2784 | kref_put(&subsys->ref, nvme_destroy_subsystem); | |
2785 | } | |
2786 | ||
2787 | static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn) | |
2788 | { | |
2789 | struct nvme_subsystem *subsys; | |
2790 | ||
2791 | lockdep_assert_held(&nvme_subsystems_lock); | |
2792 | ||
c26aa572 JS |
2793 | /* |
2794 | * Fail matches for discovery subsystems. This results | |
2795 | * in each discovery controller bound to a unique subsystem. | |
2796 | * This avoids issues with validating controller values | |
2797 | * that can only be true when there is a single unique subsystem. | |
2798 | * There may be multiple and completely independent entities | |
2799 | * that provide discovery controllers. | |
2800 | */ | |
2801 | if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME)) | |
2802 | return NULL; | |
2803 | ||
ab9e00cc CH |
2804 | list_for_each_entry(subsys, &nvme_subsystems, entry) { |
2805 | if (strcmp(subsys->subnqn, subsysnqn)) | |
2806 | continue; | |
2807 | if (!kref_get_unless_zero(&subsys->ref)) | |
2808 | continue; | |
2809 | return subsys; | |
2810 | } | |
2811 | ||
2812 | return NULL; | |
2813 | } | |
2814 | ||
5ab25a32 SG |
2815 | static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl) |
2816 | { | |
2817 | return ctrl->opts && ctrl->opts->discovery_nqn; | |
2818 | } | |
2819 | ||
1b1031ca CH |
2820 | static bool nvme_validate_cntlid(struct nvme_subsystem *subsys, |
2821 | struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) | |
b837b283 | 2822 | { |
1b1031ca | 2823 | struct nvme_ctrl *tmp; |
b837b283 | 2824 | |
32fd90c4 CH |
2825 | lockdep_assert_held(&nvme_subsystems_lock); |
2826 | ||
1b1031ca | 2827 | list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) { |
e7c43fea | 2828 | if (nvme_state_terminal(tmp)) |
1b1031ca CH |
2829 | continue; |
2830 | ||
2831 | if (tmp->cntlid == ctrl->cntlid) { | |
2832 | dev_err(ctrl->device, | |
16cc33b2 KB |
2833 | "Duplicate cntlid %u with %s, subsys %s, rejecting\n", |
2834 | ctrl->cntlid, dev_name(tmp->device), | |
2835 | subsys->subnqn); | |
1b1031ca CH |
2836 | return false; |
2837 | } | |
b837b283 | 2838 | |
92decf11 | 2839 | if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) || |
5ab25a32 | 2840 | nvme_discovery_ctrl(ctrl)) |
1b1031ca CH |
2841 | continue; |
2842 | ||
2843 | dev_err(ctrl->device, | |
2844 | "Subsystem does not support multiple controllers\n"); | |
2845 | return false; | |
b837b283 | 2846 | } |
b837b283 | 2847 | |
1b1031ca | 2848 | return true; |
b837b283 IR |
2849 | } |
2850 | ||
ab9e00cc CH |
2851 | static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) |
2852 | { | |
2853 | struct nvme_subsystem *subsys, *found; | |
2854 | int ret; | |
2855 | ||
2856 | subsys = kzalloc(sizeof(*subsys), GFP_KERNEL); | |
2857 | if (!subsys) | |
2858 | return -ENOMEM; | |
733e4b69 KB |
2859 | |
2860 | subsys->instance = -1; | |
ab9e00cc CH |
2861 | mutex_init(&subsys->lock); |
2862 | kref_init(&subsys->ref); | |
2863 | INIT_LIST_HEAD(&subsys->ctrls); | |
ed754e5d | 2864 | INIT_LIST_HEAD(&subsys->nsheads); |
ab9e00cc CH |
2865 | nvme_init_subnqn(subsys, ctrl, id); |
2866 | memcpy(subsys->serial, id->sn, sizeof(subsys->serial)); | |
2867 | memcpy(subsys->model, id->mn, sizeof(subsys->model)); | |
ab9e00cc CH |
2868 | subsys->vendor_id = le16_to_cpu(id->vid); |
2869 | subsys->cmic = id->cmic; | |
954ae166 HR |
2870 | |
2871 | /* Versions prior to 1.4 don't necessarily report a valid type */ | |
2872 | if (id->cntrltype == NVME_CTRL_DISC || | |
2873 | !strcmp(subsys->subnqn, NVME_DISC_SUBSYS_NAME)) | |
2874 | subsys->subtype = NVME_NQN_DISC; | |
2875 | else | |
2876 | subsys->subtype = NVME_NQN_NVME; | |
2877 | ||
20e8b689 HR |
2878 | if (nvme_discovery_ctrl(ctrl) && subsys->subtype != NVME_NQN_DISC) { |
2879 | dev_err(ctrl->device, | |
2880 | "Subsystem %s is not a discovery controller", | |
2881 | subsys->subnqn); | |
2882 | kfree(subsys); | |
2883 | return -EINVAL; | |
2884 | } | |
81adb863 | 2885 | subsys->awupf = le16_to_cpu(id->awupf); |
e3d34794 | 2886 | nvme_mpath_default_iopolicy(subsys); |
ab9e00cc CH |
2887 | |
2888 | subsys->dev.class = nvme_subsys_class; | |
2889 | subsys->dev.release = nvme_release_subsystem; | |
1e496938 | 2890 | subsys->dev.groups = nvme_subsys_attrs_groups; |
733e4b69 | 2891 | dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance); |
ab9e00cc CH |
2892 | device_initialize(&subsys->dev); |
2893 | ||
2894 | mutex_lock(&nvme_subsystems_lock); | |
2895 | found = __nvme_find_get_subsystem(subsys->subnqn); | |
2896 | if (found) { | |
e654dfd3 | 2897 | put_device(&subsys->dev); |
ab9e00cc | 2898 | subsys = found; |
32fd90c4 | 2899 | |
1b1031ca | 2900 | if (!nvme_validate_cntlid(subsys, ctrl, id)) { |
ab9e00cc | 2901 | ret = -EINVAL; |
32fd90c4 | 2902 | goto out_put_subsystem; |
ab9e00cc | 2903 | } |
ab9e00cc CH |
2904 | } else { |
2905 | ret = device_add(&subsys->dev); | |
2906 | if (ret) { | |
2907 | dev_err(ctrl->device, | |
2908 | "failed to register subsystem device.\n"); | |
8c36e66f | 2909 | put_device(&subsys->dev); |
ab9e00cc CH |
2910 | goto out_unlock; |
2911 | } | |
ed754e5d | 2912 | ida_init(&subsys->ns_ida); |
ab9e00cc CH |
2913 | list_add_tail(&subsys->entry, &nvme_subsystems); |
2914 | } | |
2915 | ||
bc4f6e06 DC |
2916 | ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj, |
2917 | dev_name(ctrl->device)); | |
2918 | if (ret) { | |
ab9e00cc CH |
2919 | dev_err(ctrl->device, |
2920 | "failed to create sysfs link from subsystem.\n"); | |
32fd90c4 | 2921 | goto out_put_subsystem; |
ab9e00cc CH |
2922 | } |
2923 | ||
733e4b69 KB |
2924 | if (!found) |
2925 | subsys->instance = ctrl->instance; | |
32fd90c4 | 2926 | ctrl->subsys = subsys; |
ab9e00cc | 2927 | list_add_tail(&ctrl->subsys_entry, &subsys->ctrls); |
32fd90c4 | 2928 | mutex_unlock(&nvme_subsystems_lock); |
ab9e00cc CH |
2929 | return 0; |
2930 | ||
32fd90c4 CH |
2931 | out_put_subsystem: |
2932 | nvme_put_subsystem(subsys); | |
ab9e00cc CH |
2933 | out_unlock: |
2934 | mutex_unlock(&nvme_subsystems_lock); | |
ab9e00cc | 2935 | return ret; |
180de007 CH |
2936 | } |
2937 | ||
be93e87e | 2938 | int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi, |
0e98719b | 2939 | void *log, size_t size, u64 offset) |
c627c487 KB |
2940 | { |
2941 | struct nvme_command c = { }; | |
71fb90eb | 2942 | u32 dwlen = nvme_bytes_to_numd(size); |
70da6094 MB |
2943 | |
2944 | c.get_log_page.opcode = nvme_admin_get_log_page; | |
0e98719b | 2945 | c.get_log_page.nsid = cpu_to_le32(nsid); |
70da6094 | 2946 | c.get_log_page.lid = log_page; |
0e98719b | 2947 | c.get_log_page.lsp = lsp; |
70da6094 MB |
2948 | c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1)); |
2949 | c.get_log_page.numdu = cpu_to_le16(dwlen >> 16); | |
7ec6074f MB |
2950 | c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset)); |
2951 | c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset)); | |
be93e87e | 2952 | c.get_log_page.csi = csi; |
c627c487 KB |
2953 | |
2954 | return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size); | |
2955 | } | |
2956 | ||
be93e87e KB |
2957 | static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi, |
2958 | struct nvme_effects_log **log) | |
84fef62d | 2959 | { |
f6224b86 | 2960 | struct nvme_effects_log *cel = xa_load(&ctrl->cels, csi); |
84fef62d KB |
2961 | int ret; |
2962 | ||
be93e87e KB |
2963 | if (cel) |
2964 | goto out; | |
84fef62d | 2965 | |
be93e87e KB |
2966 | cel = kzalloc(sizeof(*cel), GFP_KERNEL); |
2967 | if (!cel) | |
2968 | return -ENOMEM; | |
84fef62d | 2969 | |
46d2613e | 2970 | ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi, |
f6224b86 | 2971 | cel, sizeof(*cel), 0); |
84fef62d | 2972 | if (ret) { |
be93e87e KB |
2973 | kfree(cel); |
2974 | return ret; | |
84fef62d | 2975 | } |
be93e87e | 2976 | |
f6224b86 | 2977 | xa_store(&ctrl->cels, csi, cel, GFP_KERNEL); |
be93e87e | 2978 | out: |
f6224b86 | 2979 | *log = cel; |
be93e87e | 2980 | return 0; |
180de007 CH |
2981 | } |
2982 | ||
5befc7c2 | 2983 | static inline u32 nvme_mps_to_sectors(struct nvme_ctrl *ctrl, u32 units) |
7fd8930f | 2984 | { |
8609c63f | 2985 | u32 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12, val; |
7fd8930f | 2986 | |
8609c63f BVA |
2987 | if (check_shl_overflow(1U, units + page_shift - 9, &val)) |
2988 | return UINT_MAX; | |
2989 | return val; | |
5befc7c2 KB |
2990 | } |
2991 | ||
2992 | static int nvme_init_non_mdts_limits(struct nvme_ctrl *ctrl) | |
2993 | { | |
2994 | struct nvme_command c = { }; | |
2995 | struct nvme_id_ctrl_nvm *id; | |
2996 | int ret; | |
2997 | ||
5befc7c2 KB |
2998 | /* |
2999 | * Even though NVMe spec explicitly states that MDTS is not applicable | |
3000 | * to the write-zeroes, we are cautious and limit the size to the | |
3001 | * controllers max_hw_sectors value, which is based on the MDTS field | |
3002 | * and possibly other limiting factors. | |
3003 | */ | |
3004 | if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) && | |
3005 | !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES)) | |
3006 | ctrl->max_zeroes_sectors = ctrl->max_hw_sectors; | |
3007 | else | |
3008 | ctrl->max_zeroes_sectors = 0; | |
3009 | ||
def84ab6 | 3010 | if (ctrl->subsys->subtype != NVME_NQN_NVME || |
c917dd96 KB |
3011 | nvme_ctrl_limited_cns(ctrl) || |
3012 | test_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags)) | |
5befc7c2 KB |
3013 | return 0; |
3014 | ||
3015 | id = kzalloc(sizeof(*id), GFP_KERNEL); | |
3016 | if (!id) | |
bcaf434b | 3017 | return -ENOMEM; |
5befc7c2 KB |
3018 | |
3019 | c.identify.opcode = nvme_admin_identify; | |
3020 | c.identify.cns = NVME_ID_CNS_CS_CTRL; | |
3021 | c.identify.csi = NVME_CSI_NVM; | |
3022 | ||
3023 | ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id)); | |
3024 | if (ret) | |
3025 | goto free_data; | |
3026 | ||
3b946fe1 | 3027 | ctrl->dmrl = id->dmrl; |
1a86924e | 3028 | ctrl->dmrsl = le32_to_cpu(id->dmrsl); |
5befc7c2 KB |
3029 | if (id->wzsl) |
3030 | ctrl->max_zeroes_sectors = nvme_mps_to_sectors(ctrl, id->wzsl); | |
3031 | ||
3032 | free_data: | |
c917dd96 KB |
3033 | if (ret > 0) |
3034 | set_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags); | |
5befc7c2 KB |
3035 | kfree(id); |
3036 | return ret; | |
3037 | } | |
3038 | ||
cc115cbe KB |
3039 | static void nvme_init_known_nvm_effects(struct nvme_ctrl *ctrl) |
3040 | { | |
3041 | struct nvme_effects_log *log = ctrl->effects; | |
3042 | ||
3043 | log->acs[nvme_admin_format_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC | | |
3044 | NVME_CMD_EFFECTS_NCC | | |
3045 | NVME_CMD_EFFECTS_CSE_MASK); | |
3046 | log->acs[nvme_admin_sanitize_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC | | |
3047 | NVME_CMD_EFFECTS_CSE_MASK); | |
3048 | ||
baff6491 KB |
3049 | /* |
3050 | * The spec says the result of a security receive command depends on | |
3051 | * the previous security send command. As such, many vendors log this | |
3052 | * command as one to submitted only when no other commands to the same | |
3053 | * namespace are outstanding. The intention is to tell the host to | |
3054 | * prevent mixing security send and receive. | |
3055 | * | |
3056 | * This driver can only enforce such exclusive access against IO | |
3057 | * queues, though. We are not readily able to enforce such a rule for | |
3058 | * two commands to the admin queue, which is the only queue that | |
3059 | * matters for this command. | |
3060 | * | |
3061 | * Rather than blindly freezing the IO queues for this effect that | |
3062 | * doesn't even apply to IO, mask it off. | |
3063 | */ | |
c0c33b94 | 3064 | log->acs[nvme_admin_security_recv] &= cpu_to_le32(~NVME_CMD_EFFECTS_CSE_MASK); |
baff6491 | 3065 | |
cc115cbe KB |
3066 | log->iocs[nvme_cmd_write] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); |
3067 | log->iocs[nvme_cmd_write_zeroes] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); | |
3068 | log->iocs[nvme_cmd_write_uncor] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC); | |
3069 | } | |
3070 | ||
3071 | static int nvme_init_effects(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) | |
3072 | { | |
3073 | int ret = 0; | |
3074 | ||
3075 | if (ctrl->effects) | |
3076 | return 0; | |
3077 | ||
3078 | if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) { | |
3079 | ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects); | |
3080 | if (ret < 0) | |
3081 | return ret; | |
3082 | } | |
3083 | ||
3084 | if (!ctrl->effects) { | |
3085 | ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL); | |
3086 | if (!ctrl->effects) | |
3087 | return -ENOMEM; | |
3088 | xa_store(&ctrl->cels, NVME_CSI_NVM, ctrl->effects, GFP_KERNEL); | |
3089 | } | |
3090 | ||
3091 | nvme_init_known_nvm_effects(ctrl); | |
3092 | return 0; | |
3093 | } | |
3094 | ||
68999d1d GL |
3095 | static int nvme_check_ctrl_fabric_info(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id) |
3096 | { | |
3097 | /* | |
3098 | * In fabrics we need to verify the cntlid matches the | |
3099 | * admin connect | |
3100 | */ | |
3101 | if (ctrl->cntlid != le16_to_cpu(id->cntlid)) { | |
3102 | dev_err(ctrl->device, | |
3103 | "Mismatching cntlid: Connect %u vs Identify %u, rejecting\n", | |
3104 | ctrl->cntlid, le16_to_cpu(id->cntlid)); | |
3105 | return -EINVAL; | |
3106 | } | |
3107 | ||
3108 | if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) { | |
3109 | dev_err(ctrl->device, | |
3110 | "keep-alive support is mandatory for fabrics\n"); | |
3111 | return -EINVAL; | |
3112 | } | |
3113 | ||
7642138e | 3114 | if (!nvme_discovery_ctrl(ctrl) && ctrl->ioccsz < 4) { |
2fcd3ab3 GL |
3115 | dev_err(ctrl->device, |
3116 | "I/O queue command capsule supported size %d < 4\n", | |
3117 | ctrl->ioccsz); | |
3118 | return -EINVAL; | |
3119 | } | |
3120 | ||
7642138e | 3121 | if (!nvme_discovery_ctrl(ctrl) && ctrl->iorcsz < 1) { |
2fcd3ab3 GL |
3122 | dev_err(ctrl->device, |
3123 | "I/O queue response capsule supported size %d < 1\n", | |
3124 | ctrl->iorcsz); | |
3125 | return -EINVAL; | |
3126 | } | |
3127 | ||
49995681 GL |
3128 | if (!ctrl->maxcmd) { |
3129 | dev_err(ctrl->device, "Maximum outstanding commands is 0\n"); | |
3130 | return -EINVAL; | |
3131 | } | |
3132 | ||
68999d1d GL |
3133 | return 0; |
3134 | } | |
3135 | ||
44ef5611 | 3136 | static int nvme_init_identify(struct nvme_ctrl *ctrl) |
7fd8930f CH |
3137 | { |
3138 | struct nvme_id_ctrl *id; | |
a229dbf6 | 3139 | u32 max_hw_sectors; |
76a5af84 | 3140 | bool prev_apst_enabled; |
5befc7c2 | 3141 | int ret; |
f3ca80fc | 3142 | |
7fd8930f CH |
3143 | ret = nvme_identify_ctrl(ctrl, &id); |
3144 | if (ret) { | |
1b3c47c1 | 3145 | dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret); |
7fd8930f CH |
3146 | return -EIO; |
3147 | } | |
3148 | ||
a89fcca8 GP |
3149 | if (!(ctrl->ops->flags & NVME_F_FABRICS)) |
3150 | ctrl->cntlid = le16_to_cpu(id->cntlid); | |
3151 | ||
bd4da3ab | 3152 | if (!ctrl->identified) { |
44ef5611 | 3153 | unsigned int i; |
ab9e00cc | 3154 | |
bd4da3ab AL |
3155 | /* |
3156 | * Check for quirks. Quirk can depend on firmware version, | |
3157 | * so, in principle, the set of quirks present can change | |
3158 | * across a reset. As a possible future enhancement, we | |
3159 | * could re-scan for quirks every time we reinitialize | |
3160 | * the device, but we'd have to make sure that the driver | |
3161 | * behaves intelligently if the quirks change. | |
3162 | */ | |
bd4da3ab AL |
3163 | for (i = 0; i < ARRAY_SIZE(core_quirks); i++) { |
3164 | if (quirk_matches(id, &core_quirks[i])) | |
3165 | ctrl->quirks |= core_quirks[i].quirks; | |
3166 | } | |
6f2d7152 PR |
3167 | |
3168 | ret = nvme_init_subsystem(ctrl, id); | |
3169 | if (ret) | |
3170 | goto out_free; | |
cc115cbe KB |
3171 | |
3172 | ret = nvme_init_effects(ctrl, id); | |
3173 | if (ret) | |
3174 | goto out_free; | |
bd4da3ab | 3175 | } |
a8eb6c1b KB |
3176 | memcpy(ctrl->subsys->firmware_rev, id->fr, |
3177 | sizeof(ctrl->subsys->firmware_rev)); | |
bd4da3ab | 3178 | |
c35e30b4 | 3179 | if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) { |
f0425db0 | 3180 | dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n"); |
c35e30b4 AL |
3181 | ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS; |
3182 | } | |
3183 | ||
49cd84b6 KB |
3184 | ctrl->crdt[0] = le16_to_cpu(id->crdt1); |
3185 | ctrl->crdt[1] = le16_to_cpu(id->crdt2); | |
3186 | ctrl->crdt[2] = le16_to_cpu(id->crdt3); | |
3187 | ||
8a9ae523 | 3188 | ctrl->oacs = le16_to_cpu(id->oacs); |
43e2d08d | 3189 | ctrl->oncs = le16_to_cpu(id->oncs); |
2d466c7a | 3190 | ctrl->mtfa = le16_to_cpu(id->mtfa); |
c0561f82 | 3191 | ctrl->oaes = le32_to_cpu(id->oaes); |
400b6a7b GR |
3192 | ctrl->wctemp = le16_to_cpu(id->wctemp); |
3193 | ctrl->cctemp = le16_to_cpu(id->cctemp); | |
3194 | ||
6bf25d16 | 3195 | atomic_set(&ctrl->abort_limit, id->acl + 1); |
7fd8930f | 3196 | ctrl->vwc = id->vwc; |
7fd8930f | 3197 | if (id->mdts) |
5befc7c2 | 3198 | max_hw_sectors = nvme_mps_to_sectors(ctrl, id->mdts); |
7fd8930f | 3199 | else |
a229dbf6 CH |
3200 | max_hw_sectors = UINT_MAX; |
3201 | ctrl->max_hw_sectors = | |
3202 | min_not_zero(ctrl->max_hw_sectors, max_hw_sectors); | |
7fd8930f | 3203 | |
da35825d | 3204 | nvme_set_queue_limits(ctrl, ctrl->admin_q); |
07bfcd09 | 3205 | ctrl->sgls = le32_to_cpu(id->sgls); |
038bd4cb | 3206 | ctrl->kas = le16_to_cpu(id->kas); |
0d0b660f | 3207 | ctrl->max_namespaces = le32_to_cpu(id->mnan); |
3e53ba38 | 3208 | ctrl->ctratt = le32_to_cpu(id->ctratt); |
07bfcd09 | 3209 | |
86c2457a MB |
3210 | ctrl->cntrltype = id->cntrltype; |
3211 | ctrl->dctype = id->dctype; | |
3212 | ||
07fbd32a MP |
3213 | if (id->rtd3e) { |
3214 | /* us -> s */ | |
f5af577d | 3215 | u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC; |
07fbd32a MP |
3216 | |
3217 | ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time, | |
3218 | shutdown_timeout, 60); | |
3219 | ||
3220 | if (ctrl->shutdown_timeout != shutdown_timeout) | |
1a3838d7 | 3221 | dev_info(ctrl->device, |
07fbd32a MP |
3222 | "Shutdown timeout set to %u seconds\n", |
3223 | ctrl->shutdown_timeout); | |
3224 | } else | |
3225 | ctrl->shutdown_timeout = shutdown_timeout; | |
3226 | ||
c5552fde | 3227 | ctrl->npss = id->npss; |
76a5af84 KHF |
3228 | ctrl->apsta = id->apsta; |
3229 | prev_apst_enabled = ctrl->apst_enabled; | |
c35e30b4 AL |
3230 | if (ctrl->quirks & NVME_QUIRK_NO_APST) { |
3231 | if (force_apst && id->apsta) { | |
f0425db0 | 3232 | dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n"); |
76a5af84 | 3233 | ctrl->apst_enabled = true; |
c35e30b4 | 3234 | } else { |
76a5af84 | 3235 | ctrl->apst_enabled = false; |
c35e30b4 AL |
3236 | } |
3237 | } else { | |
76a5af84 | 3238 | ctrl->apst_enabled = id->apsta; |
c35e30b4 | 3239 | } |
c5552fde AL |
3240 | memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd)); |
3241 | ||
d3d5b87d | 3242 | if (ctrl->ops->flags & NVME_F_FABRICS) { |
07bfcd09 CH |
3243 | ctrl->icdoff = le16_to_cpu(id->icdoff); |
3244 | ctrl->ioccsz = le32_to_cpu(id->ioccsz); | |
3245 | ctrl->iorcsz = le32_to_cpu(id->iorcsz); | |
3246 | ctrl->maxcmd = le16_to_cpu(id->maxcmd); | |
3247 | ||
68999d1d GL |
3248 | ret = nvme_check_ctrl_fabric_info(ctrl, id); |
3249 | if (ret) | |
634b8325 | 3250 | goto out_free; |
07bfcd09 | 3251 | } else { |
fe6d53c9 CH |
3252 | ctrl->hmpre = le32_to_cpu(id->hmpre); |
3253 | ctrl->hmmin = le32_to_cpu(id->hmmin); | |
044a9df1 CH |
3254 | ctrl->hmminds = le32_to_cpu(id->hmminds); |
3255 | ctrl->hmmaxd = le16_to_cpu(id->hmmaxd); | |
07bfcd09 | 3256 | } |
da35825d | 3257 | |
5e1f6899 | 3258 | ret = nvme_mpath_init_identify(ctrl, id); |
0d0b660f | 3259 | if (ret < 0) |
44ef5611 | 3260 | goto out_free; |
0d0b660f | 3261 | |
76a5af84 | 3262 | if (ctrl->apst_enabled && !prev_apst_enabled) |
c5552fde | 3263 | dev_pm_qos_expose_latency_tolerance(ctrl->device); |
76a5af84 | 3264 | else if (!ctrl->apst_enabled && prev_apst_enabled) |
c5552fde AL |
3265 | dev_pm_qos_hide_latency_tolerance(ctrl->device); |
3266 | ||
44ef5611 CK |
3267 | out_free: |
3268 | kfree(id); | |
3269 | return ret; | |
3270 | } | |
3271 | ||
3272 | /* | |
3273 | * Initialize the cached copies of the Identify data and various controller | |
3274 | * register in our nvme_ctrl structure. This should be called as soon as | |
3275 | * the admin queue is fully up and running. | |
3276 | */ | |
94cc781f | 3277 | int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended) |
44ef5611 CK |
3278 | { |
3279 | int ret; | |
3280 | ||
3281 | ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs); | |
3282 | if (ret) { | |
3283 | dev_err(ctrl->device, "Reading VS failed (%d)\n", ret); | |
3284 | return ret; | |
3285 | } | |
3286 | ||
3287 | ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize); | |
3288 | ||
3289 | if (ctrl->vs >= NVME_VS(1, 1, 0)) | |
3290 | ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap); | |
3291 | ||
3292 | ret = nvme_init_identify(ctrl); | |
3293 | if (ret) | |
3294 | return ret; | |
3295 | ||
634b8325 KB |
3296 | ret = nvme_configure_apst(ctrl); |
3297 | if (ret < 0) | |
3298 | return ret; | |
95d54bd1 | 3299 | |
dbf86b39 JD |
3300 | ret = nvme_configure_timestamp(ctrl); |
3301 | if (ret < 0) | |
3302 | return ret; | |
634b8325 | 3303 | |
4020aad8 | 3304 | ret = nvme_configure_host_options(ctrl); |
49cd84b6 KB |
3305 | if (ret < 0) |
3306 | return ret; | |
3307 | ||
94cc781f CH |
3308 | nvme_configure_opal(ctrl, was_suspended); |
3309 | ||
5ab25a32 | 3310 | if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) { |
6b8cf940 CH |
3311 | /* |
3312 | * Do not return errors unless we are in a controller reset, | |
3313 | * the controller works perfectly fine without hwmon. | |
3314 | */ | |
59e330f8 | 3315 | ret = nvme_hwmon_init(ctrl); |
6b8cf940 | 3316 | if (ret == -EINTR) |
59e330f8 KB |
3317 | return ret; |
3318 | } | |
400b6a7b | 3319 | |
d0dd594b | 3320 | clear_bit(NVME_CTRL_DIRTY_CAPABILITY, &ctrl->flags); |
bd4da3ab | 3321 | ctrl->identified = true; |
c5552fde | 3322 | |
4733b65d HR |
3323 | nvme_start_keep_alive(ctrl); |
3324 | ||
634b8325 | 3325 | return 0; |
7fd8930f | 3326 | } |
f21c4769 | 3327 | EXPORT_SYMBOL_GPL(nvme_init_ctrl_finish); |
7fd8930f | 3328 | |
f3ca80fc | 3329 | static int nvme_dev_open(struct inode *inode, struct file *file) |
1673f1f0 | 3330 | { |
a6a5149b CH |
3331 | struct nvme_ctrl *ctrl = |
3332 | container_of(inode->i_cdev, struct nvme_ctrl, cdev); | |
1673f1f0 | 3333 | |
e6e7f7ac | 3334 | switch (nvme_ctrl_state(ctrl)) { |
2b1b7e78 | 3335 | case NVME_CTRL_LIVE: |
2b1b7e78 JW |
3336 | break; |
3337 | default: | |
a6a5149b | 3338 | return -EWOULDBLOCK; |
2b1b7e78 JW |
3339 | } |
3340 | ||
52a3974f | 3341 | nvme_get_ctrl(ctrl); |
4bab6909 CK |
3342 | if (!try_module_get(ctrl->ops->module)) { |
3343 | nvme_put_ctrl(ctrl); | |
52a3974f | 3344 | return -EINVAL; |
4bab6909 | 3345 | } |
52a3974f | 3346 | |
a6a5149b | 3347 | file->private_data = ctrl; |
f3ca80fc CH |
3348 | return 0; |
3349 | } | |
3350 | ||
52a3974f CK |
3351 | static int nvme_dev_release(struct inode *inode, struct file *file) |
3352 | { | |
3353 | struct nvme_ctrl *ctrl = | |
3354 | container_of(inode->i_cdev, struct nvme_ctrl, cdev); | |
3355 | ||
3356 | module_put(ctrl->ops->module); | |
3357 | nvme_put_ctrl(ctrl); | |
3358 | return 0; | |
3359 | } | |
3360 | ||
f3ca80fc CH |
3361 | static const struct file_operations nvme_dev_fops = { |
3362 | .owner = THIS_MODULE, | |
3363 | .open = nvme_dev_open, | |
52a3974f | 3364 | .release = nvme_dev_release, |
f3ca80fc | 3365 | .unlocked_ioctl = nvme_dev_ioctl, |
1832f2d8 | 3366 | .compat_ioctl = compat_ptr_ioctl, |
58e5bdeb | 3367 | .uring_cmd = nvme_dev_uring_cmd, |
f3ca80fc CH |
3368 | }; |
3369 | ||
5974ea7c | 3370 | static struct nvme_ns_head *nvme_find_ns_head(struct nvme_ctrl *ctrl, |
ed754e5d CH |
3371 | unsigned nsid) |
3372 | { | |
3373 | struct nvme_ns_head *h; | |
3374 | ||
5974ea7c | 3375 | lockdep_assert_held(&ctrl->subsys->lock); |
ed754e5d | 3376 | |
5974ea7c SM |
3377 | list_for_each_entry(h, &ctrl->subsys->nsheads, entry) { |
3378 | /* | |
3379 | * Private namespaces can share NSIDs under some conditions. | |
3380 | * In that case we can't use the same ns_head for namespaces | |
3381 | * with the same NSID. | |
3382 | */ | |
3383 | if (h->ns_id != nsid || !nvme_is_unique_nsid(ctrl, h)) | |
9edceaf4 DW |
3384 | continue; |
3385 | if (!list_empty(&h->list) && nvme_tryget_ns_head(h)) | |
ed754e5d CH |
3386 | return h; |
3387 | } | |
3388 | ||
3389 | return NULL; | |
3390 | } | |
3391 | ||
fd8099e7 CH |
3392 | static int nvme_subsys_check_duplicate_ids(struct nvme_subsystem *subsys, |
3393 | struct nvme_ns_ids *ids) | |
ed754e5d | 3394 | { |
e2724cb9 CH |
3395 | bool has_uuid = !uuid_is_null(&ids->uuid); |
3396 | bool has_nguid = memchr_inv(ids->nguid, 0, sizeof(ids->nguid)); | |
3397 | bool has_eui64 = memchr_inv(ids->eui64, 0, sizeof(ids->eui64)); | |
ed754e5d CH |
3398 | struct nvme_ns_head *h; |
3399 | ||
3400 | lockdep_assert_held(&subsys->lock); | |
3401 | ||
3402 | list_for_each_entry(h, &subsys->nsheads, entry) { | |
e2724cb9 CH |
3403 | if (has_uuid && uuid_equal(&ids->uuid, &h->ids.uuid)) |
3404 | return -EINVAL; | |
3405 | if (has_nguid && | |
3406 | memcmp(&ids->nguid, &h->ids.nguid, sizeof(ids->nguid)) == 0) | |
3407 | return -EINVAL; | |
3408 | if (has_eui64 && | |
3409 | memcmp(&ids->eui64, &h->ids.eui64, sizeof(ids->eui64)) == 0) | |
ed754e5d CH |
3410 | return -EINVAL; |
3411 | } | |
3412 | ||
3413 | return 0; | |
3414 | } | |
3415 | ||
be5eb933 AM |
3416 | static void nvme_cdev_rel(struct device *dev) |
3417 | { | |
8b850475 | 3418 | ida_free(&nvme_ns_chr_minor_ida, MINOR(dev->devt)); |
be5eb933 AM |
3419 | } |
3420 | ||
2637baed MI |
3421 | void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device) |
3422 | { | |
3423 | cdev_device_del(cdev, cdev_device); | |
be5eb933 | 3424 | put_device(cdev_device); |
2637baed MI |
3425 | } |
3426 | ||
3427 | int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device, | |
3428 | const struct file_operations *fops, struct module *owner) | |
3429 | { | |
3430 | int minor, ret; | |
3431 | ||
8b850475 | 3432 | minor = ida_alloc(&nvme_ns_chr_minor_ida, GFP_KERNEL); |
2637baed MI |
3433 | if (minor < 0) |
3434 | return minor; | |
3435 | cdev_device->devt = MKDEV(MAJOR(nvme_ns_chr_devt), minor); | |
3436 | cdev_device->class = nvme_ns_chr_class; | |
be5eb933 | 3437 | cdev_device->release = nvme_cdev_rel; |
2637baed MI |
3438 | device_initialize(cdev_device); |
3439 | cdev_init(cdev, fops); | |
3440 | cdev->owner = owner; | |
3441 | ret = cdev_device_add(cdev, cdev_device); | |
be5eb933 | 3442 | if (ret) |
3596a065 | 3443 | put_device(cdev_device); |
be5eb933 | 3444 | |
2637baed MI |
3445 | return ret; |
3446 | } | |
3447 | ||
3448 | static int nvme_ns_chr_open(struct inode *inode, struct file *file) | |
3449 | { | |
3450 | return nvme_ns_open(container_of(inode->i_cdev, struct nvme_ns, cdev)); | |
3451 | } | |
3452 | ||
3453 | static int nvme_ns_chr_release(struct inode *inode, struct file *file) | |
3454 | { | |
3455 | nvme_ns_release(container_of(inode->i_cdev, struct nvme_ns, cdev)); | |
3456 | return 0; | |
3457 | } | |
3458 | ||
3459 | static const struct file_operations nvme_ns_chr_fops = { | |
3460 | .owner = THIS_MODULE, | |
3461 | .open = nvme_ns_chr_open, | |
3462 | .release = nvme_ns_chr_release, | |
3463 | .unlocked_ioctl = nvme_ns_chr_ioctl, | |
3464 | .compat_ioctl = compat_ptr_ioctl, | |
456cba38 | 3465 | .uring_cmd = nvme_ns_chr_uring_cmd, |
585079b6 | 3466 | .uring_cmd_iopoll = nvme_ns_chr_uring_cmd_iopoll, |
2637baed MI |
3467 | }; |
3468 | ||
3469 | static int nvme_add_ns_cdev(struct nvme_ns *ns) | |
3470 | { | |
3471 | int ret; | |
3472 | ||
3473 | ns->cdev_device.parent = ns->ctrl->device; | |
3474 | ret = dev_set_name(&ns->cdev_device, "ng%dn%d", | |
3475 | ns->ctrl->instance, ns->head->instance); | |
3476 | if (ret) | |
3477 | return ret; | |
be5eb933 AM |
3478 | |
3479 | return nvme_cdev_add(&ns->cdev, &ns->cdev_device, &nvme_ns_chr_fops, | |
3480 | ns->ctrl->ops->module); | |
2637baed MI |
3481 | } |
3482 | ||
ed754e5d | 3483 | static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl, |
1a893c2b | 3484 | struct nvme_ns_info *info) |
ed754e5d CH |
3485 | { |
3486 | struct nvme_ns_head *head; | |
f3334447 | 3487 | size_t size = sizeof(*head); |
ed754e5d CH |
3488 | int ret = -ENOMEM; |
3489 | ||
f3334447 CH |
3490 | #ifdef CONFIG_NVME_MULTIPATH |
3491 | size += num_possible_nodes() * sizeof(struct nvme_ns *); | |
3492 | #endif | |
3493 | ||
3494 | head = kzalloc(size, GFP_KERNEL); | |
ed754e5d CH |
3495 | if (!head) |
3496 | goto out; | |
8b850475 | 3497 | ret = ida_alloc_min(&ctrl->subsys->ns_ida, 1, GFP_KERNEL); |
ed754e5d CH |
3498 | if (ret < 0) |
3499 | goto out_free_head; | |
3500 | head->instance = ret; | |
3501 | INIT_LIST_HEAD(&head->list); | |
fd92c77f MG |
3502 | ret = init_srcu_struct(&head->srcu); |
3503 | if (ret) | |
3504 | goto out_ida_remove; | |
ed754e5d | 3505 | head->subsys = ctrl->subsys; |
1a893c2b CH |
3506 | head->ns_id = info->nsid; |
3507 | head->ids = info->ids; | |
3508 | head->shared = info->is_shared; | |
a1a825ab DW |
3509 | ratelimit_state_init(&head->rs_nuse, 5 * HZ, 1); |
3510 | ratelimit_set_flags(&head->rs_nuse, RATELIMIT_MSG_ON_RELEASE); | |
ed754e5d CH |
3511 | kref_init(&head->ref); |
3512 | ||
be93e87e KB |
3513 | if (head->ids.csi) { |
3514 | ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects); | |
3515 | if (ret) | |
3516 | goto out_cleanup_srcu; | |
3517 | } else | |
3518 | head->effects = ctrl->effects; | |
3519 | ||
32acab31 CH |
3520 | ret = nvme_mpath_alloc_disk(ctrl, head); |
3521 | if (ret) | |
3522 | goto out_cleanup_srcu; | |
3523 | ||
ed754e5d | 3524 | list_add_tail(&head->entry, &ctrl->subsys->nsheads); |
12d9f070 JW |
3525 | |
3526 | kref_get(&ctrl->subsys->ref); | |
3527 | ||
ed754e5d CH |
3528 | return head; |
3529 | out_cleanup_srcu: | |
3530 | cleanup_srcu_struct(&head->srcu); | |
fd92c77f | 3531 | out_ida_remove: |
8b850475 | 3532 | ida_free(&ctrl->subsys->ns_ida, head->instance); |
ed754e5d CH |
3533 | out_free_head: |
3534 | kfree(head); | |
3535 | out: | |
538af88e SG |
3536 | if (ret > 0) |
3537 | ret = blk_status_to_errno(nvme_error_status(ret)); | |
ed754e5d CH |
3538 | return ERR_PTR(ret); |
3539 | } | |
3540 | ||
2079f41e CH |
3541 | static int nvme_global_check_duplicate_ids(struct nvme_subsystem *this, |
3542 | struct nvme_ns_ids *ids) | |
3543 | { | |
3544 | struct nvme_subsystem *s; | |
3545 | int ret = 0; | |
3546 | ||
3547 | /* | |
3548 | * Note that this check is racy as we try to avoid holding the global | |
3549 | * lock over the whole ns_head creation. But it is only intended as | |
3550 | * a sanity check anyway. | |
3551 | */ | |
3552 | mutex_lock(&nvme_subsystems_lock); | |
3553 | list_for_each_entry(s, &nvme_subsystems, entry) { | |
3554 | if (s == this) | |
3555 | continue; | |
3556 | mutex_lock(&s->lock); | |
3557 | ret = nvme_subsys_check_duplicate_ids(s, ids); | |
3558 | mutex_unlock(&s->lock); | |
3559 | if (ret) | |
3560 | break; | |
3561 | } | |
3562 | mutex_unlock(&nvme_subsystems_lock); | |
3563 | ||
3564 | return ret; | |
3565 | } | |
3566 | ||
1a893c2b | 3567 | static int nvme_init_ns_head(struct nvme_ns *ns, struct nvme_ns_info *info) |
ed754e5d CH |
3568 | { |
3569 | struct nvme_ctrl *ctrl = ns->ctrl; | |
ed754e5d | 3570 | struct nvme_ns_head *head = NULL; |
2079f41e CH |
3571 | int ret; |
3572 | ||
1a893c2b | 3573 | ret = nvme_global_check_duplicate_ids(ctrl->subsys, &info->ids); |
2079f41e | 3574 | if (ret) { |
ac522fc6 CH |
3575 | /* |
3576 | * We've found two different namespaces on two different | |
3577 | * subsystems that report the same ID. This is pretty nasty | |
3578 | * for anything that actually requires unique device | |
3579 | * identification. In the kernel we need this for multipathing, | |
3580 | * and in user space the /dev/disk/by-id/ links rely on it. | |
3581 | * | |
3582 | * If the device also claims to be multi-path capable back off | |
3583 | * here now and refuse the probe the second device as this is a | |
3584 | * recipe for data corruption. If not this is probably a | |
3585 | * cheap consumer device if on the PCIe bus, so let the user | |
3586 | * proceed and use the shiny toy, but warn that with changing | |
3587 | * probing order (which due to our async probing could just be | |
3588 | * device taking longer to startup) the other device could show | |
3589 | * up at any time. | |
3590 | */ | |
2f0dad17 | 3591 | nvme_print_device_info(ctrl); |
ac522fc6 CH |
3592 | if ((ns->ctrl->ops->flags & NVME_F_FABRICS) || /* !PCIe */ |
3593 | ((ns->ctrl->subsys->cmic & NVME_CTRL_CMIC_MULTI_CTRL) && | |
3594 | info->is_shared)) { | |
3595 | dev_err(ctrl->device, | |
3596 | "ignoring nsid %d because of duplicate IDs\n", | |
3597 | info->nsid); | |
3598 | return ret; | |
3599 | } | |
3600 | ||
3601 | dev_err(ctrl->device, | |
3602 | "clearing duplicate IDs for nsid %d\n", info->nsid); | |
3603 | dev_err(ctrl->device, | |
3604 | "use of /dev/disk/by-id/ may cause data corruption\n"); | |
3605 | memset(&info->ids.nguid, 0, sizeof(info->ids.nguid)); | |
3606 | memset(&info->ids.uuid, 0, sizeof(info->ids.uuid)); | |
3607 | memset(&info->ids.eui64, 0, sizeof(info->ids.eui64)); | |
3608 | ctrl->quirks |= NVME_QUIRK_BOGUS_NID; | |
2079f41e | 3609 | } |
ed754e5d CH |
3610 | |
3611 | mutex_lock(&ctrl->subsys->lock); | |
1a893c2b | 3612 | head = nvme_find_ns_head(ctrl, info->nsid); |
ed754e5d | 3613 | if (!head) { |
1a893c2b | 3614 | ret = nvme_subsys_check_duplicate_ids(ctrl->subsys, &info->ids); |
e2d77d2e CH |
3615 | if (ret) { |
3616 | dev_err(ctrl->device, | |
2079f41e | 3617 | "duplicate IDs in subsystem for nsid %d\n", |
1a893c2b | 3618 | info->nsid); |
e2d77d2e CH |
3619 | goto out_unlock; |
3620 | } | |
1a893c2b | 3621 | head = nvme_alloc_ns_head(ctrl, info); |
ed754e5d CH |
3622 | if (IS_ERR(head)) { |
3623 | ret = PTR_ERR(head); | |
3624 | goto out_unlock; | |
3625 | } | |
ed754e5d | 3626 | } else { |
6623c5b3 | 3627 | ret = -EINVAL; |
1a893c2b | 3628 | if (!info->is_shared || !head->shared) { |
9ad1927a | 3629 | dev_err(ctrl->device, |
1a893c2b CH |
3630 | "Duplicate unshared namespace %d\n", |
3631 | info->nsid); | |
6623c5b3 | 3632 | goto out_put_ns_head; |
9ad1927a | 3633 | } |
1a893c2b | 3634 | if (!nvme_ns_ids_equal(&head->ids, &info->ids)) { |
ed754e5d CH |
3635 | dev_err(ctrl->device, |
3636 | "IDs don't match for shared namespace %d\n", | |
1a893c2b | 3637 | info->nsid); |
6623c5b3 | 3638 | goto out_put_ns_head; |
ed754e5d | 3639 | } |
ce8d7861 | 3640 | |
2110a6bc | 3641 | if (!multipath) { |
ce8d7861 CH |
3642 | dev_warn(ctrl->device, |
3643 | "Found shared namespace %d, but multipathing not supported.\n", | |
1a893c2b | 3644 | info->nsid); |
ce8d7861 CH |
3645 | dev_warn_once(ctrl->device, |
3646 | "Support for shared namespaces without CONFIG_NVME_MULTIPATH is deprecated and will be removed in Linux 6.0\n."); | |
3647 | } | |
ed754e5d CH |
3648 | } |
3649 | ||
772ea326 | 3650 | list_add_tail_rcu(&ns->siblings, &head->list); |
ed754e5d | 3651 | ns->head = head; |
6623c5b3 CH |
3652 | mutex_unlock(&ctrl->subsys->lock); |
3653 | return 0; | |
ed754e5d | 3654 | |
6623c5b3 CH |
3655 | out_put_ns_head: |
3656 | nvme_put_ns_head(head); | |
ed754e5d CH |
3657 | out_unlock: |
3658 | mutex_unlock(&ctrl->subsys->lock); | |
3659 | return ret; | |
3660 | } | |
3661 | ||
24493b8b | 3662 | struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid) |
5bae7f73 | 3663 | { |
32f0c4af | 3664 | struct nvme_ns *ns, *ret = NULL; |
69d3b8ac | 3665 | |
765cc031 | 3666 | down_read(&ctrl->namespaces_rwsem); |
5bae7f73 | 3667 | list_for_each_entry(ns, &ctrl->namespaces, list) { |
ed754e5d | 3668 | if (ns->head->ns_id == nsid) { |
4c74d1f8 | 3669 | if (!nvme_get_ns(ns)) |
2dd41228 | 3670 | continue; |
32f0c4af KB |
3671 | ret = ns; |
3672 | break; | |
3673 | } | |
ed754e5d | 3674 | if (ns->head->ns_id > nsid) |
5bae7f73 CH |
3675 | break; |
3676 | } | |
765cc031 | 3677 | up_read(&ctrl->namespaces_rwsem); |
32f0c4af | 3678 | return ret; |
5bae7f73 | 3679 | } |
24493b8b | 3680 | EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU); |
5bae7f73 | 3681 | |
298ba0e3 CH |
3682 | /* |
3683 | * Add the namespace to the controller list while keeping the list ordered. | |
3684 | */ | |
3685 | static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns) | |
3686 | { | |
3687 | struct nvme_ns *tmp; | |
3688 | ||
3689 | list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) { | |
3690 | if (tmp->head->ns_id < ns->head->ns_id) { | |
3691 | list_add(&ns->list, &tmp->list); | |
3692 | return; | |
3693 | } | |
3694 | } | |
3695 | list_add(&ns->list, &ns->ctrl->namespaces); | |
3696 | } | |
3697 | ||
1a893c2b | 3698 | static void nvme_alloc_ns(struct nvme_ctrl *ctrl, struct nvme_ns_info *info) |
5bae7f73 CH |
3699 | { |
3700 | struct nvme_ns *ns; | |
3701 | struct gendisk *disk; | |
9953ab0c | 3702 | int node = ctrl->numa_node; |
5bae7f73 CH |
3703 | |
3704 | ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); | |
3705 | if (!ns) | |
1a893c2b | 3706 | return; |
5bae7f73 | 3707 | |
27e32cd2 | 3708 | disk = blk_mq_alloc_disk(ctrl->tagset, NULL, ns); |
5f432cce | 3709 | if (IS_ERR(disk)) |
ed754e5d | 3710 | goto out_free_ns; |
5f432cce CH |
3711 | disk->fops = &nvme_bdev_ops; |
3712 | disk->private_data = ns; | |
3713 | ||
3714 | ns->disk = disk; | |
3715 | ns->queue = disk->queue; | |
9f079dda | 3716 | ns->passthru_err_log_enabled = false; |
e0596ab2 | 3717 | |
7d30c81b | 3718 | if (ctrl->opts && ctrl->opts->data_digest) |
1cb039f3 | 3719 | blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, ns->queue); |
958f2a0f | 3720 | |
8b904b5b | 3721 | blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue); |
2f859441 LG |
3722 | if (ctrl->ops->supports_pci_p2pdma && |
3723 | ctrl->ops->supports_pci_p2pdma(ctrl)) | |
e0596ab2 LG |
3724 | blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue); |
3725 | ||
5bae7f73 | 3726 | ns->ctrl = ctrl; |
5bae7f73 | 3727 | kref_init(&ns->kref); |
5bae7f73 | 3728 | |
1a893c2b | 3729 | if (nvme_init_ns_head(ns, info)) |
5f432cce | 3730 | goto out_cleanup_disk; |
ac81bfa9 | 3731 | |
9953ab0c | 3732 | /* |
b739e137 CH |
3733 | * If multipathing is enabled, the device name for all disks and not |
3734 | * just those that represent shared namespaces needs to be based on the | |
3735 | * subsystem instance. Using the controller instance for private | |
3736 | * namespaces could lead to naming collisions between shared and private | |
3737 | * namespaces if they don't use a common numbering scheme. | |
3738 | * | |
3739 | * If multipathing is not enabled, disk names must use the controller | |
3740 | * instance as shared namespaces will show up as multiple block | |
3741 | * devices. | |
9953ab0c | 3742 | */ |
35e797b0 | 3743 | if (nvme_ns_head_multipath(ns->head)) { |
b739e137 CH |
3744 | sprintf(disk->disk_name, "nvme%dc%dn%d", ctrl->subsys->instance, |
3745 | ctrl->instance, ns->head->instance); | |
3746 | disk->flags |= GENHD_FL_HIDDEN; | |
3747 | } else if (multipath) { | |
3748 | sprintf(disk->disk_name, "nvme%dn%d", ctrl->subsys->instance, | |
3749 | ns->head->instance); | |
3750 | } else { | |
9953ab0c CH |
3751 | sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance, |
3752 | ns->head->instance); | |
b739e137 | 3753 | } |
3dc87dd0 | 3754 | |
1a893c2b | 3755 | if (nvme_update_ns_info(ns, info)) |
5f432cce | 3756 | goto out_unlink_ns; |
5bae7f73 | 3757 | |
765cc031 | 3758 | down_write(&ctrl->namespaces_rwsem); |
839a40d1 BH |
3759 | /* |
3760 | * Ensure that no namespaces are added to the ctrl list after the queues | |
3761 | * are frozen, thereby avoiding a deadlock between scan and reset. | |
3762 | */ | |
3763 | if (test_bit(NVME_CTRL_FROZEN, &ctrl->flags)) { | |
3764 | up_write(&ctrl->namespaces_rwsem); | |
3765 | goto out_unlink_ns; | |
3766 | } | |
298ba0e3 | 3767 | nvme_ns_add_to_ctrl_list(ns); |
765cc031 | 3768 | up_write(&ctrl->namespaces_rwsem); |
d22524a4 | 3769 | nvme_get_ctrl(ctrl); |
ac81bfa9 | 3770 | |
83ac678e | 3771 | if (device_add_disk(ctrl->device, ns->disk, nvme_ns_attr_groups)) |
ab3994f6 LC |
3772 | goto out_cleanup_ns_from_list; |
3773 | ||
2637baed MI |
3774 | if (!nvme_ns_head_multipath(ns->head)) |
3775 | nvme_add_ns_cdev(ns); | |
32acab31 | 3776 | |
1a893c2b | 3777 | nvme_mpath_add_disk(ns, info->anagrpid); |
a3646451 | 3778 | nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name); |
0d0b660f | 3779 | |
9f079dda AA |
3780 | /* |
3781 | * Set ns->disk->device->driver_data to ns so we can access | |
3782 | * ns->logging_enabled in nvme_passthru_err_log_enabled_store() and | |
3783 | * nvme_passthru_err_log_enabled_show(). | |
3784 | */ | |
3785 | dev_set_drvdata(disk_to_dev(ns->disk), ns); | |
3786 | ||
adce7e98 | 3787 | return; |
5f432cce | 3788 | |
ab3994f6 LC |
3789 | out_cleanup_ns_from_list: |
3790 | nvme_put_ctrl(ctrl); | |
3791 | down_write(&ctrl->namespaces_rwsem); | |
3792 | list_del_init(&ns->list); | |
3793 | up_write(&ctrl->namespaces_rwsem); | |
ed754e5d CH |
3794 | out_unlink_ns: |
3795 | mutex_lock(&ctrl->subsys->lock); | |
3796 | list_del_rcu(&ns->siblings); | |
d5675729 KB |
3797 | if (list_empty(&ns->head->list)) |
3798 | list_del_init(&ns->head->entry); | |
ed754e5d | 3799 | mutex_unlock(&ctrl->subsys->lock); |
a63b8370 | 3800 | nvme_put_ns_head(ns->head); |
5f432cce | 3801 | out_cleanup_disk: |
8b9ab626 | 3802 | put_disk(disk); |
5bae7f73 CH |
3803 | out_free_ns: |
3804 | kfree(ns); | |
3805 | } | |
3806 | ||
3807 | static void nvme_ns_remove(struct nvme_ns *ns) | |
3808 | { | |
5396fdac HR |
3809 | bool last_path = false; |
3810 | ||
646017a6 KB |
3811 | if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags)) |
3812 | return; | |
69d3b8ac | 3813 | |
e7d65803 | 3814 | clear_bit(NVME_NS_READY, &ns->flags); |
0a05226a | 3815 | set_capacity(ns->disk, 0); |
a3646451 | 3816 | nvme_fault_inject_fini(&ns->fault_inject); |
2181e455 | 3817 | |
d6d67427 CL |
3818 | /* |
3819 | * Ensure that !NVME_NS_READY is seen by other threads to prevent | |
3820 | * this ns going back into current_path. | |
3821 | */ | |
3822 | synchronize_srcu(&ns->head->srcu); | |
3823 | ||
3824 | /* wait for concurrent submissions */ | |
3825 | if (nvme_mpath_clear_current_path(ns)) | |
3826 | synchronize_srcu(&ns->head->srcu); | |
3827 | ||
2181e455 AE |
3828 | mutex_lock(&ns->ctrl->subsys->lock); |
3829 | list_del_rcu(&ns->siblings); | |
9edceaf4 DW |
3830 | if (list_empty(&ns->head->list)) { |
3831 | list_del_init(&ns->head->entry); | |
3832 | last_path = true; | |
3833 | } | |
2181e455 | 3834 | mutex_unlock(&ns->ctrl->subsys->lock); |
d5675729 | 3835 | |
041bd1a1 | 3836 | /* guarantee not available in head->list */ |
899d2a05 | 3837 | synchronize_srcu(&ns->head->srcu); |
041bd1a1 | 3838 | |
5eba2005 CH |
3839 | if (!nvme_ns_head_multipath(ns->head)) |
3840 | nvme_cdev_del(&ns->cdev, &ns->cdev_device); | |
3841 | del_gendisk(ns->disk); | |
32f0c4af | 3842 | |
765cc031 | 3843 | down_write(&ns->ctrl->namespaces_rwsem); |
5bae7f73 | 3844 | list_del_init(&ns->list); |
765cc031 | 3845 | up_write(&ns->ctrl->namespaces_rwsem); |
32f0c4af | 3846 | |
5396fdac HR |
3847 | if (last_path) |
3848 | nvme_mpath_shutdown_disk(ns->head); | |
5bae7f73 CH |
3849 | nvme_put_ns(ns); |
3850 | } | |
3851 | ||
4450ba3b CH |
3852 | static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid) |
3853 | { | |
3854 | struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid); | |
3855 | ||
3856 | if (ns) { | |
3857 | nvme_ns_remove(ns); | |
3858 | nvme_put_ns(ns); | |
3859 | } | |
3860 | } | |
3861 | ||
1a893c2b | 3862 | static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_info *info) |
b2dc748a | 3863 | { |
d95c1f41 | 3864 | int ret = NVME_SC_INVALID_NS | NVME_SC_DNR; |
b2dc748a | 3865 | |
1a893c2b | 3866 | if (!nvme_ns_ids_equal(&ns->head->ids, &info->ids)) { |
af5d6f7b | 3867 | dev_err(ns->ctrl->device, |
b2dc748a | 3868 | "identifiers changed for nsid %d\n", ns->head->ns_id); |
1a893c2b | 3869 | goto out; |
b2dc748a CH |
3870 | } |
3871 | ||
1a893c2b | 3872 | ret = nvme_update_ns_info(ns, info); |
b2dc748a CH |
3873 | out: |
3874 | /* | |
0a05226a | 3875 | * Only remove the namespace if we got a fatal error back from the |
b2dc748a | 3876 | * device, otherwise ignore the error and just move on. |
0a05226a CH |
3877 | * |
3878 | * TODO: we should probably schedule a delayed retry here. | |
b2dc748a | 3879 | */ |
d95c1f41 | 3880 | if (ret > 0 && (ret & NVME_SC_DNR)) |
0a05226a | 3881 | nvme_ns_remove(ns); |
b2dc748a CH |
3882 | } |
3883 | ||
04c170f6 | 3884 | static void nvme_scan_ns(struct nvme_ctrl *ctrl, unsigned nsid) |
540c801c | 3885 | { |
1a893c2b | 3886 | struct nvme_ns_info info = { .nsid = nsid }; |
540c801c | 3887 | struct nvme_ns *ns; |
0dd6fff2 | 3888 | int ret; |
540c801c | 3889 | |
1a893c2b | 3890 | if (nvme_identify_ns_descs(ctrl, &info)) |
8b7c0ff2 | 3891 | return; |
540c801c | 3892 | |
1a893c2b | 3893 | if (info.ids.csi != NVME_CSI_NVM && !nvme_multi_css(ctrl)) { |
71882e7d CH |
3894 | dev_warn(ctrl->device, |
3895 | "command set not reported for nsid: %d\n", nsid); | |
3896 | return; | |
3897 | } | |
3898 | ||
354201c5 | 3899 | /* |
1a893c2b CH |
3900 | * If available try to use the Command Set Idependent Identify Namespace |
3901 | * data structure to find all the generic information that is needed to | |
3902 | * set up a namespace. If not fall back to the legacy version. | |
354201c5 | 3903 | */ |
eb867ee9 | 3904 | if ((ctrl->cap & NVME_CAP_CRMS_CRIMS) || |
0dd6fff2 CH |
3905 | (info.ids.csi != NVME_CSI_NVM && info.ids.csi != NVME_CSI_ZNS)) |
3906 | ret = nvme_ns_info_from_id_cs_indep(ctrl, &info); | |
3907 | else | |
3908 | ret = nvme_ns_info_from_identify(ctrl, &info); | |
3909 | ||
3910 | if (info.is_removed) | |
3911 | nvme_ns_remove_by_nsid(ctrl, nsid); | |
354201c5 | 3912 | |
1a893c2b CH |
3913 | /* |
3914 | * Ignore the namespace if it is not ready. We will get an AEN once it | |
3915 | * becomes ready and restart the scan. | |
3916 | */ | |
0dd6fff2 | 3917 | if (ret || !info.is_ready) |
354201c5 CH |
3918 | return; |
3919 | ||
32f0c4af | 3920 | ns = nvme_find_get_ns(ctrl, nsid); |
8b7c0ff2 | 3921 | if (ns) { |
1a893c2b | 3922 | nvme_validate_ns(ns, &info); |
8b7c0ff2 | 3923 | nvme_put_ns(ns); |
1a893c2b CH |
3924 | } else { |
3925 | nvme_alloc_ns(ctrl, &info); | |
8b7c0ff2 | 3926 | } |
540c801c KB |
3927 | } |
3928 | ||
47b0e50a SB |
3929 | static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl, |
3930 | unsigned nsid) | |
3931 | { | |
3932 | struct nvme_ns *ns, *next; | |
6f8e0d78 | 3933 | LIST_HEAD(rm_list); |
47b0e50a | 3934 | |
765cc031 | 3935 | down_write(&ctrl->namespaces_rwsem); |
47b0e50a | 3936 | list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) { |
4f17344e | 3937 | if (ns->head->ns_id > nsid) |
6f8e0d78 | 3938 | list_move_tail(&ns->list, &rm_list); |
47b0e50a | 3939 | } |
765cc031 | 3940 | up_write(&ctrl->namespaces_rwsem); |
6f8e0d78 JW |
3941 | |
3942 | list_for_each_entry_safe(ns, next, &rm_list, list) | |
3943 | nvme_ns_remove(ns); | |
3944 | ||
47b0e50a SB |
3945 | } |
3946 | ||
4005f28d | 3947 | static int nvme_scan_ns_list(struct nvme_ctrl *ctrl) |
540c801c | 3948 | { |
aec459b4 | 3949 | const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32); |
540c801c | 3950 | __le32 *ns_list; |
4005f28d CH |
3951 | u32 prev = 0; |
3952 | int ret = 0, i; | |
540c801c | 3953 | |
42595eb7 | 3954 | ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL); |
540c801c KB |
3955 | if (!ns_list) |
3956 | return -ENOMEM; | |
3957 | ||
4005f28d | 3958 | for (;;) { |
7b153362 CH |
3959 | struct nvme_command cmd = { |
3960 | .identify.opcode = nvme_admin_identify, | |
3961 | .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST, | |
3962 | .identify.nsid = cpu_to_le32(prev), | |
3963 | }; | |
3964 | ||
3965 | ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list, | |
3966 | NVME_IDENTIFY_DATA_SIZE); | |
f781f3dd MI |
3967 | if (ret) { |
3968 | dev_warn(ctrl->device, | |
3969 | "Identify NS List failed (status=0x%x)\n", ret); | |
47b0e50a | 3970 | goto free; |
f781f3dd | 3971 | } |
540c801c | 3972 | |
aec459b4 | 3973 | for (i = 0; i < nr_entries; i++) { |
4005f28d | 3974 | u32 nsid = le32_to_cpu(ns_list[i]); |
540c801c | 3975 | |
4005f28d CH |
3976 | if (!nsid) /* end of the list? */ |
3977 | goto out; | |
04c170f6 | 3978 | nvme_scan_ns(ctrl, nsid); |
4450ba3b CH |
3979 | while (++prev < nsid) |
3980 | nvme_ns_remove_by_nsid(ctrl, prev); | |
540c801c | 3981 | } |
540c801c KB |
3982 | } |
3983 | out: | |
47b0e50a SB |
3984 | nvme_remove_invalid_namespaces(ctrl, prev); |
3985 | free: | |
540c801c KB |
3986 | kfree(ns_list); |
3987 | return ret; | |
3988 | } | |
3989 | ||
4005f28d | 3990 | static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl) |
5bae7f73 | 3991 | { |
4005f28d CH |
3992 | struct nvme_id_ctrl *id; |
3993 | u32 nn, i; | |
3994 | ||
3995 | if (nvme_identify_ctrl(ctrl, &id)) | |
3996 | return; | |
3997 | nn = le32_to_cpu(id->nn); | |
3998 | kfree(id); | |
5bae7f73 | 3999 | |
540c801c | 4000 | for (i = 1; i <= nn; i++) |
04c170f6 | 4001 | nvme_scan_ns(ctrl, i); |
540c801c | 4002 | |
47b0e50a | 4003 | nvme_remove_invalid_namespaces(ctrl, nn); |
5bae7f73 CH |
4004 | } |
4005 | ||
f493af37 | 4006 | static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl) |
30d90964 CH |
4007 | { |
4008 | size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32); | |
4009 | __le32 *log; | |
f493af37 | 4010 | int error; |
30d90964 CH |
4011 | |
4012 | log = kzalloc(log_size, GFP_KERNEL); | |
4013 | if (!log) | |
f493af37 | 4014 | return; |
30d90964 | 4015 | |
f493af37 CH |
4016 | /* |
4017 | * We need to read the log to clear the AEN, but we don't want to rely | |
4018 | * on it for the changed namespace information as userspace could have | |
4019 | * raced with us in reading the log page, which could cause us to miss | |
4020 | * updates. | |
4021 | */ | |
be93e87e KB |
4022 | error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0, |
4023 | NVME_CSI_NVM, log, log_size, 0); | |
f493af37 | 4024 | if (error) |
30d90964 CH |
4025 | dev_warn(ctrl->device, |
4026 | "reading changed ns log failed: %d\n", error); | |
30d90964 | 4027 | |
30d90964 | 4028 | kfree(log); |
30d90964 CH |
4029 | } |
4030 | ||
5955be21 | 4031 | static void nvme_scan_work(struct work_struct *work) |
5bae7f73 | 4032 | { |
5955be21 CH |
4033 | struct nvme_ctrl *ctrl = |
4034 | container_of(work, struct nvme_ctrl, scan_work); | |
78288665 | 4035 | int ret; |
5bae7f73 | 4036 | |
5d02a5c1 | 4037 | /* No tagset on a live ctrl means IO queues could not created */ |
e6e7f7ac | 4038 | if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE || !ctrl->tagset) |
5955be21 CH |
4039 | return; |
4040 | ||
78288665 CK |
4041 | /* |
4042 | * Identify controller limits can change at controller reset due to | |
4043 | * new firmware download, even though it is not common we cannot ignore | |
4044 | * such scenario. Controller's non-mdts limits are reported in the unit | |
4045 | * of logical blocks that is dependent on the format of attached | |
4046 | * namespace. Hence re-read the limits at the time of ns allocation. | |
4047 | */ | |
4048 | ret = nvme_init_non_mdts_limits(ctrl); | |
4049 | if (ret < 0) { | |
4050 | dev_warn(ctrl->device, | |
4051 | "reading non-mdts-limits failed: %d\n", ret); | |
4052 | return; | |
4053 | } | |
4054 | ||
77016199 | 4055 | if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) { |
30d90964 | 4056 | dev_info(ctrl->device, "rescanning namespaces.\n"); |
f493af37 | 4057 | nvme_clear_changed_ns_log(ctrl); |
30d90964 CH |
4058 | } |
4059 | ||
e7ad43c3 | 4060 | mutex_lock(&ctrl->scan_lock); |
811f4de0 | 4061 | if (nvme_ctrl_limited_cns(ctrl)) { |
4005f28d | 4062 | nvme_scan_ns_sequential(ctrl); |
811f4de0 US |
4063 | } else { |
4064 | /* | |
4065 | * Fall back to sequential scan if DNR is set to handle broken | |
4066 | * devices which should support Identify NS List (as per the VS | |
4067 | * they report) but don't actually support it. | |
4068 | */ | |
4069 | ret = nvme_scan_ns_list(ctrl); | |
4070 | if (ret > 0 && ret & NVME_SC_DNR) | |
4071 | nvme_scan_ns_sequential(ctrl); | |
4072 | } | |
e7ad43c3 | 4073 | mutex_unlock(&ctrl->scan_lock); |
5955be21 | 4074 | } |
5bae7f73 | 4075 | |
32f0c4af KB |
4076 | /* |
4077 | * This function iterates the namespace list unlocked to allow recovery from | |
4078 | * controller failure. It is up to the caller to ensure the namespace list is | |
4079 | * not modified by scan work while this function is executing. | |
4080 | */ | |
5bae7f73 CH |
4081 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl) |
4082 | { | |
4083 | struct nvme_ns *ns, *next; | |
6f8e0d78 | 4084 | LIST_HEAD(ns_list); |
5bae7f73 | 4085 | |
0157ec8d SG |
4086 | /* |
4087 | * make sure to requeue I/O to all namespaces as these | |
4088 | * might result from the scan itself and must complete | |
4089 | * for the scan_work to make progress | |
4090 | */ | |
4091 | nvme_mpath_clear_ctrl_paths(ctrl); | |
4092 | ||
1b95e817 ML |
4093 | /* |
4094 | * Unquiesce io queues so any pending IO won't hang, especially | |
4095 | * those submitted from scan work | |
4096 | */ | |
4097 | nvme_unquiesce_io_queues(ctrl); | |
4098 | ||
f6c8e432 SG |
4099 | /* prevent racing with ns scanning */ |
4100 | flush_work(&ctrl->scan_work); | |
4101 | ||
0ff9d4e1 KB |
4102 | /* |
4103 | * The dead states indicates the controller was not gracefully | |
4104 | * disconnected. In that case, we won't be able to flush any data while | |
4105 | * removing the namespaces' disks; fail all the queues now to avoid | |
4106 | * potentially having to clean up the failed sync later. | |
4107 | */ | |
e6e7f7ac | 4108 | if (nvme_ctrl_state(ctrl) == NVME_CTRL_DEAD) |
cd50f9b2 | 4109 | nvme_mark_namespaces_dead(ctrl); |
0ff9d4e1 | 4110 | |
ecca390e SG |
4111 | /* this is a no-op when called from the controller reset handler */ |
4112 | nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO); | |
4113 | ||
765cc031 | 4114 | down_write(&ctrl->namespaces_rwsem); |
6f8e0d78 | 4115 | list_splice_init(&ctrl->namespaces, &ns_list); |
765cc031 | 4116 | up_write(&ctrl->namespaces_rwsem); |
6f8e0d78 JW |
4117 | |
4118 | list_for_each_entry_safe(ns, next, &ns_list, list) | |
5bae7f73 CH |
4119 | nvme_ns_remove(ns); |
4120 | } | |
576d55d6 | 4121 | EXPORT_SYMBOL_GPL(nvme_remove_namespaces); |
5bae7f73 | 4122 | |
23680f0b | 4123 | static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env) |
a42f42e5 | 4124 | { |
23680f0b | 4125 | const struct nvme_ctrl *ctrl = |
a42f42e5 SG |
4126 | container_of(dev, struct nvme_ctrl, ctrl_device); |
4127 | struct nvmf_ctrl_options *opts = ctrl->opts; | |
4128 | int ret; | |
4129 | ||
4130 | ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name); | |
4131 | if (ret) | |
4132 | return ret; | |
4133 | ||
4134 | if (opts) { | |
4135 | ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr); | |
4136 | if (ret) | |
4137 | return ret; | |
4138 | ||
4139 | ret = add_uevent_var(env, "NVME_TRSVCID=%s", | |
4140 | opts->trsvcid ?: "none"); | |
4141 | if (ret) | |
4142 | return ret; | |
4143 | ||
4144 | ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s", | |
4145 | opts->host_traddr ?: "none"); | |
3ede8f72 MB |
4146 | if (ret) |
4147 | return ret; | |
4148 | ||
4149 | ret = add_uevent_var(env, "NVME_HOST_IFACE=%s", | |
4150 | opts->host_iface ?: "none"); | |
a42f42e5 SG |
4151 | } |
4152 | return ret; | |
4153 | } | |
4154 | ||
20d64911 MB |
4155 | static void nvme_change_uevent(struct nvme_ctrl *ctrl, char *envdata) |
4156 | { | |
4157 | char *envp[2] = { envdata, NULL }; | |
4158 | ||
4159 | kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp); | |
4160 | } | |
4161 | ||
e3d7874d KB |
4162 | static void nvme_aen_uevent(struct nvme_ctrl *ctrl) |
4163 | { | |
4164 | char *envp[2] = { NULL, NULL }; | |
4165 | u32 aen_result = ctrl->aen_result; | |
4166 | ||
4167 | ctrl->aen_result = 0; | |
4168 | if (!aen_result) | |
4169 | return; | |
4170 | ||
4171 | envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result); | |
4172 | if (!envp[0]) | |
4173 | return; | |
4174 | kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp); | |
4175 | kfree(envp[0]); | |
4176 | } | |
4177 | ||
f866fc42 CH |
4178 | static void nvme_async_event_work(struct work_struct *work) |
4179 | { | |
4180 | struct nvme_ctrl *ctrl = | |
4181 | container_of(work, struct nvme_ctrl, async_event_work); | |
4182 | ||
e3d7874d | 4183 | nvme_aen_uevent(ctrl); |
0fa0f99f SG |
4184 | |
4185 | /* | |
4186 | * The transport drivers must guarantee AER submission here is safe by | |
4187 | * flushing ctrl async_event_work after changing the controller state | |
4188 | * from LIVE and before freeing the admin queue. | |
4189 | */ | |
e6e7f7ac | 4190 | if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE) |
0fa0f99f | 4191 | ctrl->ops->submit_async_event(ctrl); |
f866fc42 CH |
4192 | } |
4193 | ||
b6dccf7f AD |
4194 | static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl) |
4195 | { | |
4196 | ||
4197 | u32 csts; | |
4198 | ||
4199 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) | |
4200 | return false; | |
4201 | ||
4202 | if (csts == ~0) | |
4203 | return false; | |
4204 | ||
4205 | return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP)); | |
4206 | } | |
4207 | ||
4208 | static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl) | |
4209 | { | |
b6dccf7f AD |
4210 | struct nvme_fw_slot_info_log *log; |
4211 | ||
4212 | log = kmalloc(sizeof(*log), GFP_KERNEL); | |
4213 | if (!log) | |
4214 | return; | |
4215 | ||
be93e87e | 4216 | if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM, |
983a338b | 4217 | log, sizeof(*log), 0)) { |
0e98719b | 4218 | dev_warn(ctrl->device, "Get FW SLOT INFO log error\n"); |
983a338b DW |
4219 | goto out_free_log; |
4220 | } | |
4221 | ||
4222 | if (log->afi & 0x70 || !(log->afi & 0x7)) { | |
4223 | dev_info(ctrl->device, | |
4224 | "Firmware is activated after next Controller Level Reset\n"); | |
4225 | goto out_free_log; | |
4226 | } | |
4227 | ||
4228 | memcpy(ctrl->subsys->firmware_rev, &log->frs[(log->afi & 0x7) - 1], | |
4229 | sizeof(ctrl->subsys->firmware_rev)); | |
4230 | ||
4231 | out_free_log: | |
b6dccf7f AD |
4232 | kfree(log); |
4233 | } | |
4234 | ||
4235 | static void nvme_fw_act_work(struct work_struct *work) | |
4236 | { | |
4237 | struct nvme_ctrl *ctrl = container_of(work, | |
4238 | struct nvme_ctrl, fw_act_work); | |
4239 | unsigned long fw_act_timeout; | |
4240 | ||
f6fe0b2d ML |
4241 | nvme_auth_stop(ctrl); |
4242 | ||
b6dccf7f AD |
4243 | if (ctrl->mtfa) |
4244 | fw_act_timeout = jiffies + | |
4245 | msecs_to_jiffies(ctrl->mtfa * 100); | |
4246 | else | |
4247 | fw_act_timeout = jiffies + | |
4248 | msecs_to_jiffies(admin_timeout * 1000); | |
4249 | ||
9f27bd70 | 4250 | nvme_quiesce_io_queues(ctrl); |
b6dccf7f AD |
4251 | while (nvme_ctrl_pp_status(ctrl)) { |
4252 | if (time_after(jiffies, fw_act_timeout)) { | |
4253 | dev_warn(ctrl->device, | |
4254 | "Fw activation timeout, reset controller\n"); | |
4c75f877 KB |
4255 | nvme_try_sched_reset(ctrl); |
4256 | return; | |
b6dccf7f AD |
4257 | } |
4258 | msleep(100); | |
4259 | } | |
4260 | ||
4c75f877 | 4261 | if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE)) |
b6dccf7f AD |
4262 | return; |
4263 | ||
9f27bd70 | 4264 | nvme_unquiesce_io_queues(ctrl); |
a806c6c8 | 4265 | /* read FW slot information to clear the AER */ |
b6dccf7f | 4266 | nvme_get_fw_slot_info(ctrl); |
371a982c KB |
4267 | |
4268 | queue_work(nvme_wq, &ctrl->async_event_work); | |
b6dccf7f AD |
4269 | } |
4270 | ||
2c61c97f MK |
4271 | static u32 nvme_aer_type(u32 result) |
4272 | { | |
4273 | return result & 0x7; | |
4274 | } | |
4275 | ||
4276 | static u32 nvme_aer_subtype(u32 result) | |
4277 | { | |
4278 | return (result & 0xff00) >> 8; | |
4279 | } | |
4280 | ||
371a982c | 4281 | static bool nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result) |
868c2392 | 4282 | { |
2c61c97f | 4283 | u32 aer_notice_type = nvme_aer_subtype(result); |
371a982c | 4284 | bool requeue = true; |
09bd1ff4 CK |
4285 | |
4286 | switch (aer_notice_type) { | |
868c2392 | 4287 | case NVME_AER_NOTICE_NS_CHANGED: |
77016199 | 4288 | set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events); |
868c2392 CH |
4289 | nvme_queue_scan(ctrl); |
4290 | break; | |
4291 | case NVME_AER_NOTICE_FW_ACT_STARTING: | |
4c75f877 KB |
4292 | /* |
4293 | * We are (ab)using the RESETTING state to prevent subsequent | |
4294 | * recovery actions from interfering with the controller's | |
4295 | * firmware activation. | |
4296 | */ | |
f50fff73 | 4297 | if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) { |
371a982c | 4298 | requeue = false; |
4c75f877 | 4299 | queue_work(nvme_wq, &ctrl->fw_act_work); |
f50fff73 | 4300 | } |
868c2392 | 4301 | break; |
0d0b660f CH |
4302 | #ifdef CONFIG_NVME_MULTIPATH |
4303 | case NVME_AER_NOTICE_ANA: | |
4304 | if (!ctrl->ana_log_buf) | |
4305 | break; | |
4306 | queue_work(nvme_wq, &ctrl->ana_work); | |
4307 | break; | |
4308 | #endif | |
85f8a435 SG |
4309 | case NVME_AER_NOTICE_DISC_CHANGED: |
4310 | ctrl->aen_result = result; | |
4311 | break; | |
868c2392 CH |
4312 | default: |
4313 | dev_warn(ctrl->device, "async event result %08x\n", result); | |
4314 | } | |
371a982c | 4315 | return requeue; |
868c2392 CH |
4316 | } |
4317 | ||
2c61c97f MK |
4318 | static void nvme_handle_aer_persistent_error(struct nvme_ctrl *ctrl) |
4319 | { | |
2c61c97f MK |
4320 | dev_warn(ctrl->device, "resetting controller due to AER\n"); |
4321 | nvme_reset_ctrl(ctrl); | |
4322 | } | |
4323 | ||
7bf58533 | 4324 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
287a63eb | 4325 | volatile union nvme_result *res) |
f866fc42 | 4326 | { |
7bf58533 | 4327 | u32 result = le32_to_cpu(res->u32); |
2c61c97f MK |
4328 | u32 aer_type = nvme_aer_type(result); |
4329 | u32 aer_subtype = nvme_aer_subtype(result); | |
371a982c | 4330 | bool requeue = true; |
f866fc42 | 4331 | |
ad22c355 | 4332 | if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS) |
f866fc42 CH |
4333 | return; |
4334 | ||
6622b76f | 4335 | trace_nvme_async_event(ctrl, result); |
09bd1ff4 | 4336 | switch (aer_type) { |
868c2392 | 4337 | case NVME_AER_NOTICE: |
371a982c | 4338 | requeue = nvme_handle_aen_notice(ctrl, result); |
868c2392 | 4339 | break; |
e3d7874d | 4340 | case NVME_AER_ERROR: |
2c61c97f MK |
4341 | /* |
4342 | * For a persistent internal error, don't run async_event_work | |
4343 | * to submit a new AER. The controller reset will do it. | |
4344 | */ | |
4345 | if (aer_subtype == NVME_AER_ERROR_PERSIST_INT_ERR) { | |
4346 | nvme_handle_aer_persistent_error(ctrl); | |
4347 | return; | |
4348 | } | |
4349 | fallthrough; | |
e3d7874d KB |
4350 | case NVME_AER_SMART: |
4351 | case NVME_AER_CSS: | |
4352 | case NVME_AER_VS: | |
4353 | ctrl->aen_result = result; | |
7bf58533 CH |
4354 | break; |
4355 | default: | |
4356 | break; | |
f866fc42 | 4357 | } |
371a982c KB |
4358 | |
4359 | if (requeue) | |
4360 | queue_work(nvme_wq, &ctrl->async_event_work); | |
f866fc42 | 4361 | } |
f866fc42 | 4362 | EXPORT_SYMBOL_GPL(nvme_complete_async_event); |
f3ca80fc | 4363 | |
fe60e8c5 | 4364 | int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, |
db45e1a5 | 4365 | const struct blk_mq_ops *ops, unsigned int cmd_size) |
fe60e8c5 CH |
4366 | { |
4367 | int ret; | |
4368 | ||
4369 | memset(set, 0, sizeof(*set)); | |
4370 | set->ops = ops; | |
4371 | set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; | |
4372 | if (ctrl->ops->flags & NVME_F_FABRICS) | |
4373 | set->reserved_tags = NVMF_RESERVED_TAGS; | |
4374 | set->numa_node = ctrl->numa_node; | |
db45e1a5 CH |
4375 | set->flags = BLK_MQ_F_NO_SCHED; |
4376 | if (ctrl->ops->flags & NVME_F_BLOCKING) | |
4377 | set->flags |= BLK_MQ_F_BLOCKING; | |
fe60e8c5 CH |
4378 | set->cmd_size = cmd_size; |
4379 | set->driver_data = ctrl; | |
4380 | set->nr_hw_queues = 1; | |
4381 | set->timeout = NVME_ADMIN_TIMEOUT; | |
4382 | ret = blk_mq_alloc_tag_set(set); | |
4383 | if (ret) | |
4384 | return ret; | |
4385 | ||
9ac4dd8c | 4386 | ctrl->admin_q = blk_mq_alloc_queue(set, NULL, NULL); |
fe60e8c5 CH |
4387 | if (IS_ERR(ctrl->admin_q)) { |
4388 | ret = PTR_ERR(ctrl->admin_q); | |
4389 | goto out_free_tagset; | |
4390 | } | |
4391 | ||
4392 | if (ctrl->ops->flags & NVME_F_FABRICS) { | |
9ac4dd8c | 4393 | ctrl->fabrics_q = blk_mq_alloc_queue(set, NULL, NULL); |
fe60e8c5 CH |
4394 | if (IS_ERR(ctrl->fabrics_q)) { |
4395 | ret = PTR_ERR(ctrl->fabrics_q); | |
4396 | goto out_cleanup_admin_q; | |
4397 | } | |
4398 | } | |
4399 | ||
4400 | ctrl->admin_tagset = set; | |
4401 | return 0; | |
4402 | ||
4403 | out_cleanup_admin_q: | |
4739824e | 4404 | blk_mq_destroy_queue(ctrl->admin_q); |
2b3f056f | 4405 | blk_put_queue(ctrl->admin_q); |
fe60e8c5 | 4406 | out_free_tagset: |
fd62678a ML |
4407 | blk_mq_free_tag_set(set); |
4408 | ctrl->admin_q = NULL; | |
4409 | ctrl->fabrics_q = NULL; | |
fe60e8c5 CH |
4410 | return ret; |
4411 | } | |
4412 | EXPORT_SYMBOL_GPL(nvme_alloc_admin_tag_set); | |
4413 | ||
4414 | void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl) | |
4415 | { | |
4416 | blk_mq_destroy_queue(ctrl->admin_q); | |
2b3f056f CH |
4417 | blk_put_queue(ctrl->admin_q); |
4418 | if (ctrl->ops->flags & NVME_F_FABRICS) { | |
fe60e8c5 | 4419 | blk_mq_destroy_queue(ctrl->fabrics_q); |
2b3f056f CH |
4420 | blk_put_queue(ctrl->fabrics_q); |
4421 | } | |
fe60e8c5 CH |
4422 | blk_mq_free_tag_set(ctrl->admin_tagset); |
4423 | } | |
4424 | EXPORT_SYMBOL_GPL(nvme_remove_admin_tag_set); | |
4425 | ||
4426 | int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set, | |
db45e1a5 | 4427 | const struct blk_mq_ops *ops, unsigned int nr_maps, |
fe60e8c5 CH |
4428 | unsigned int cmd_size) |
4429 | { | |
4430 | int ret; | |
4431 | ||
4432 | memset(set, 0, sizeof(*set)); | |
4433 | set->ops = ops; | |
33b93727 | 4434 | set->queue_depth = min_t(unsigned, ctrl->sqsize, BLK_MQ_MAX_DEPTH - 1); |
93b24f57 CH |
4435 | /* |
4436 | * Some Apple controllers requires tags to be unique across admin and | |
4437 | * the (only) I/O queue, so reserve the first 32 tags of the I/O queue. | |
4438 | */ | |
4439 | if (ctrl->quirks & NVME_QUIRK_SHARED_TAGS) | |
4440 | set->reserved_tags = NVME_AQ_DEPTH; | |
4441 | else if (ctrl->ops->flags & NVME_F_FABRICS) | |
b794d1c2 | 4442 | set->reserved_tags = NVMF_RESERVED_TAGS; |
fe60e8c5 | 4443 | set->numa_node = ctrl->numa_node; |
db45e1a5 CH |
4444 | set->flags = BLK_MQ_F_SHOULD_MERGE; |
4445 | if (ctrl->ops->flags & NVME_F_BLOCKING) | |
4446 | set->flags |= BLK_MQ_F_BLOCKING; | |
fe60e8c5 CH |
4447 | set->cmd_size = cmd_size, |
4448 | set->driver_data = ctrl; | |
4449 | set->nr_hw_queues = ctrl->queue_count - 1; | |
4450 | set->timeout = NVME_IO_TIMEOUT; | |
dcef7727 | 4451 | set->nr_maps = nr_maps; |
fe60e8c5 CH |
4452 | ret = blk_mq_alloc_tag_set(set); |
4453 | if (ret) | |
4454 | return ret; | |
4455 | ||
4456 | if (ctrl->ops->flags & NVME_F_FABRICS) { | |
9ac4dd8c | 4457 | ctrl->connect_q = blk_mq_alloc_queue(set, NULL, NULL); |
fe60e8c5 CH |
4458 | if (IS_ERR(ctrl->connect_q)) { |
4459 | ret = PTR_ERR(ctrl->connect_q); | |
4460 | goto out_free_tag_set; | |
4461 | } | |
98d81f0d CL |
4462 | blk_queue_flag_set(QUEUE_FLAG_SKIP_TAGSET_QUIESCE, |
4463 | ctrl->connect_q); | |
fe60e8c5 CH |
4464 | } |
4465 | ||
4466 | ctrl->tagset = set; | |
4467 | return 0; | |
4468 | ||
4469 | out_free_tag_set: | |
4470 | blk_mq_free_tag_set(set); | |
6fbf13c0 | 4471 | ctrl->connect_q = NULL; |
fe60e8c5 CH |
4472 | return ret; |
4473 | } | |
4474 | EXPORT_SYMBOL_GPL(nvme_alloc_io_tag_set); | |
4475 | ||
4476 | void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl) | |
4477 | { | |
2b3f056f | 4478 | if (ctrl->ops->flags & NVME_F_FABRICS) { |
fe60e8c5 | 4479 | blk_mq_destroy_queue(ctrl->connect_q); |
2b3f056f CH |
4480 | blk_put_queue(ctrl->connect_q); |
4481 | } | |
fe60e8c5 CH |
4482 | blk_mq_free_tag_set(ctrl->tagset); |
4483 | } | |
4484 | EXPORT_SYMBOL_GPL(nvme_remove_io_tag_set); | |
4485 | ||
d09f2b45 | 4486 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl) |
576d55d6 | 4487 | { |
0d0b660f | 4488 | nvme_mpath_stop(ctrl); |
f50fff73 | 4489 | nvme_auth_stop(ctrl); |
3af755a4 | 4490 | nvme_stop_keep_alive(ctrl); |
8c4dfea9 | 4491 | nvme_stop_failfast_work(ctrl); |
f866fc42 | 4492 | flush_work(&ctrl->async_event_work); |
b6dccf7f | 4493 | cancel_work_sync(&ctrl->fw_act_work); |
f7f70f4a RL |
4494 | if (ctrl->ops->stop_ctrl) |
4495 | ctrl->ops->stop_ctrl(ctrl); | |
d09f2b45 SG |
4496 | } |
4497 | EXPORT_SYMBOL_GPL(nvme_stop_ctrl); | |
4498 | ||
4499 | void nvme_start_ctrl(struct nvme_ctrl *ctrl) | |
4500 | { | |
93da4023 SG |
4501 | nvme_enable_aen(ctrl); |
4502 | ||
f46ef9e8 SG |
4503 | /* |
4504 | * persistent discovery controllers need to send indication to userspace | |
4505 | * to re-read the discovery log page to learn about possible changes | |
4506 | * that were missed. We identify persistent discovery controllers by | |
4507 | * checking that they started once before, hence are reconnecting back. | |
4508 | */ | |
2eb94dd5 | 4509 | if (test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) && |
f46ef9e8 SG |
4510 | nvme_discovery_ctrl(ctrl)) |
4511 | nvme_change_uevent(ctrl, "NVME_EVENT=rediscover"); | |
4512 | ||
d09f2b45 SG |
4513 | if (ctrl->queue_count > 1) { |
4514 | nvme_queue_scan(ctrl); | |
9f27bd70 | 4515 | nvme_unquiesce_io_queues(ctrl); |
a4a6f3c8 | 4516 | nvme_mpath_update(ctrl); |
d09f2b45 | 4517 | } |
20d64911 MB |
4518 | |
4519 | nvme_change_uevent(ctrl, "NVME_EVENT=connected"); | |
2eb94dd5 | 4520 | set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags); |
d09f2b45 SG |
4521 | } |
4522 | EXPORT_SYMBOL_GPL(nvme_start_ctrl); | |
5955be21 | 4523 | |
d09f2b45 SG |
4524 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl) |
4525 | { | |
ed7770f6 | 4526 | nvme_hwmon_exit(ctrl); |
f79d5fda | 4527 | nvme_fault_inject_fini(&ctrl->fault_inject); |
510a405d | 4528 | dev_pm_qos_hide_latency_tolerance(ctrl->device); |
a6a5149b | 4529 | cdev_device_del(&ctrl->cdev, ctrl->device); |
726612b6 | 4530 | nvme_put_ctrl(ctrl); |
53029b04 | 4531 | } |
576d55d6 | 4532 | EXPORT_SYMBOL_GPL(nvme_uninit_ctrl); |
53029b04 | 4533 | |
8168d23f KB |
4534 | static void nvme_free_cels(struct nvme_ctrl *ctrl) |
4535 | { | |
4536 | struct nvme_effects_log *cel; | |
4537 | unsigned long i; | |
4538 | ||
8f8ea928 | 4539 | xa_for_each(&ctrl->cels, i, cel) { |
8168d23f KB |
4540 | xa_erase(&ctrl->cels, i); |
4541 | kfree(cel); | |
4542 | } | |
4543 | ||
4544 | xa_destroy(&ctrl->cels); | |
4545 | } | |
4546 | ||
d22524a4 | 4547 | static void nvme_free_ctrl(struct device *dev) |
53029b04 | 4548 | { |
d22524a4 CH |
4549 | struct nvme_ctrl *ctrl = |
4550 | container_of(dev, struct nvme_ctrl, ctrl_device); | |
ab9e00cc | 4551 | struct nvme_subsystem *subsys = ctrl->subsys; |
f3ca80fc | 4552 | |
192f6c29 | 4553 | if (!subsys || ctrl->instance != subsys->instance) |
8b850475 | 4554 | ida_free(&nvme_instance_ida, ctrl->instance); |
be8e82ca | 4555 | key_put(ctrl->tls_key); |
8168d23f | 4556 | nvme_free_cels(ctrl); |
0d0b660f | 4557 | nvme_mpath_uninit(ctrl); |
f50fff73 HR |
4558 | nvme_auth_stop(ctrl); |
4559 | nvme_auth_free(ctrl); | |
092ff052 | 4560 | __free_page(ctrl->discard_page); |
94cc781f | 4561 | free_opal_dev(ctrl->opal_dev); |
f3ca80fc | 4562 | |
ab9e00cc | 4563 | if (subsys) { |
32fd90c4 | 4564 | mutex_lock(&nvme_subsystems_lock); |
ab9e00cc | 4565 | list_del(&ctrl->subsys_entry); |
ab9e00cc | 4566 | sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device)); |
32fd90c4 | 4567 | mutex_unlock(&nvme_subsystems_lock); |
ab9e00cc | 4568 | } |
f3ca80fc CH |
4569 | |
4570 | ctrl->ops->free_ctrl(ctrl); | |
f3ca80fc | 4571 | |
ab9e00cc CH |
4572 | if (subsys) |
4573 | nvme_put_subsystem(subsys); | |
f3ca80fc CH |
4574 | } |
4575 | ||
4576 | /* | |
4577 | * Initialize a NVMe controller structures. This needs to be called during | |
4578 | * earliest initialization so that we have the initialized structured around | |
4579 | * during probing. | |
4580 | */ | |
4581 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, | |
4582 | const struct nvme_ctrl_ops *ops, unsigned long quirks) | |
4583 | { | |
4584 | int ret; | |
4585 | ||
e6e7f7ac | 4586 | WRITE_ONCE(ctrl->state, NVME_CTRL_NEW); |
9f079dda | 4587 | ctrl->passthru_err_log_enabled = false; |
8c4dfea9 | 4588 | clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags); |
bb8d261e | 4589 | spin_lock_init(&ctrl->lock); |
e7ad43c3 | 4590 | mutex_init(&ctrl->scan_lock); |
f3ca80fc | 4591 | INIT_LIST_HEAD(&ctrl->namespaces); |
1cf7a12e | 4592 | xa_init(&ctrl->cels); |
765cc031 | 4593 | init_rwsem(&ctrl->namespaces_rwsem); |
f3ca80fc CH |
4594 | ctrl->dev = dev; |
4595 | ctrl->ops = ops; | |
4596 | ctrl->quirks = quirks; | |
4fea243e | 4597 | ctrl->numa_node = NUMA_NO_NODE; |
5955be21 | 4598 | INIT_WORK(&ctrl->scan_work, nvme_scan_work); |
f866fc42 | 4599 | INIT_WORK(&ctrl->async_event_work, nvme_async_event_work); |
b6dccf7f | 4600 | INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work); |
c5017e85 | 4601 | INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work); |
c1ac9a4b | 4602 | init_waitqueue_head(&ctrl->state_wq); |
f3ca80fc | 4603 | |
230f1f9e | 4604 | INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work); |
8c4dfea9 | 4605 | INIT_DELAYED_WORK(&ctrl->failfast_work, nvme_failfast_work); |
230f1f9e JS |
4606 | memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd)); |
4607 | ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive; | |
136cfcb8 | 4608 | ctrl->ka_last_check_time = jiffies; |
230f1f9e | 4609 | |
cb5b7262 JA |
4610 | BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) > |
4611 | PAGE_SIZE); | |
4612 | ctrl->discard_page = alloc_page(GFP_KERNEL); | |
4613 | if (!ctrl->discard_page) { | |
4614 | ret = -ENOMEM; | |
4615 | goto out; | |
4616 | } | |
4617 | ||
8b850475 | 4618 | ret = ida_alloc(&nvme_instance_ida, GFP_KERNEL); |
9843f685 | 4619 | if (ret < 0) |
f3ca80fc | 4620 | goto out; |
9843f685 | 4621 | ctrl->instance = ret; |
f3ca80fc | 4622 | |
d22524a4 CH |
4623 | device_initialize(&ctrl->ctrl_device); |
4624 | ctrl->device = &ctrl->ctrl_device; | |
f68abd9c JG |
4625 | ctrl->device->devt = MKDEV(MAJOR(nvme_ctrl_base_chr_devt), |
4626 | ctrl->instance); | |
d22524a4 CH |
4627 | ctrl->device->class = nvme_class; |
4628 | ctrl->device->parent = ctrl->dev; | |
86adbf0c CH |
4629 | if (ops->dev_attr_groups) |
4630 | ctrl->device->groups = ops->dev_attr_groups; | |
4631 | else | |
4632 | ctrl->device->groups = nvme_dev_attr_groups; | |
d22524a4 CH |
4633 | ctrl->device->release = nvme_free_ctrl; |
4634 | dev_set_drvdata(ctrl->device, ctrl); | |
4635 | ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance); | |
4636 | if (ret) | |
f3ca80fc | 4637 | goto out_release_instance; |
f3ca80fc | 4638 | |
b780d741 | 4639 | nvme_get_ctrl(ctrl); |
a6a5149b CH |
4640 | cdev_init(&ctrl->cdev, &nvme_dev_fops); |
4641 | ctrl->cdev.owner = ops->module; | |
4642 | ret = cdev_device_add(&ctrl->cdev, ctrl->device); | |
d22524a4 CH |
4643 | if (ret) |
4644 | goto out_free_name; | |
f3ca80fc | 4645 | |
c5552fde AL |
4646 | /* |
4647 | * Initialize latency tolerance controls. The sysfs files won't | |
4648 | * be visible to userspace unless the device actually supports APST. | |
4649 | */ | |
4650 | ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance; | |
4651 | dev_pm_qos_update_user_latency_tolerance(ctrl->device, | |
4652 | min(default_ps_max_latency_us, (unsigned long)S32_MAX)); | |
4653 | ||
f79d5fda | 4654 | nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device)); |
5e1f6899 | 4655 | nvme_mpath_init_ctrl(ctrl); |
193a8c7e SG |
4656 | ret = nvme_auth_init_ctrl(ctrl); |
4657 | if (ret) | |
4658 | goto out_free_cdev; | |
f79d5fda | 4659 | |
f3ca80fc | 4660 | return 0; |
193a8c7e | 4661 | out_free_cdev: |
3a12a0b8 | 4662 | nvme_fault_inject_fini(&ctrl->fault_inject); |
7ed5cf8e | 4663 | dev_pm_qos_hide_latency_tolerance(ctrl->device); |
193a8c7e | 4664 | cdev_device_del(&ctrl->cdev, ctrl->device); |
d22524a4 | 4665 | out_free_name: |
b780d741 | 4666 | nvme_put_ctrl(ctrl); |
d6a2b953 | 4667 | kfree_const(ctrl->device->kobj.name); |
f3ca80fc | 4668 | out_release_instance: |
8b850475 | 4669 | ida_free(&nvme_instance_ida, ctrl->instance); |
f3ca80fc | 4670 | out: |
cb5b7262 JA |
4671 | if (ctrl->discard_page) |
4672 | __free_page(ctrl->discard_page); | |
f3ca80fc CH |
4673 | return ret; |
4674 | } | |
576d55d6 | 4675 | EXPORT_SYMBOL_GPL(nvme_init_ctrl); |
f3ca80fc | 4676 | |
cd50f9b2 CH |
4677 | /* let I/O to all namespaces fail in preparation for surprise removal */ |
4678 | void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl) | |
69d9a99c KB |
4679 | { |
4680 | struct nvme_ns *ns; | |
4681 | ||
765cc031 | 4682 | down_read(&ctrl->namespaces_rwsem); |
cf39a6bc | 4683 | list_for_each_entry(ns, &ctrl->namespaces, list) |
cd50f9b2 | 4684 | blk_mark_disk_dead(ns->disk); |
765cc031 | 4685 | up_read(&ctrl->namespaces_rwsem); |
69d9a99c | 4686 | } |
cd50f9b2 | 4687 | EXPORT_SYMBOL_GPL(nvme_mark_namespaces_dead); |
69d9a99c | 4688 | |
302ad8cc KB |
4689 | void nvme_unfreeze(struct nvme_ctrl *ctrl) |
4690 | { | |
4691 | struct nvme_ns *ns; | |
4692 | ||
765cc031 | 4693 | down_read(&ctrl->namespaces_rwsem); |
302ad8cc KB |
4694 | list_for_each_entry(ns, &ctrl->namespaces, list) |
4695 | blk_mq_unfreeze_queue(ns->queue); | |
765cc031 | 4696 | up_read(&ctrl->namespaces_rwsem); |
839a40d1 | 4697 | clear_bit(NVME_CTRL_FROZEN, &ctrl->flags); |
302ad8cc KB |
4698 | } |
4699 | EXPORT_SYMBOL_GPL(nvme_unfreeze); | |
4700 | ||
7cf0d7c0 | 4701 | int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout) |
302ad8cc KB |
4702 | { |
4703 | struct nvme_ns *ns; | |
4704 | ||
765cc031 | 4705 | down_read(&ctrl->namespaces_rwsem); |
302ad8cc KB |
4706 | list_for_each_entry(ns, &ctrl->namespaces, list) { |
4707 | timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout); | |
4708 | if (timeout <= 0) | |
4709 | break; | |
4710 | } | |
765cc031 | 4711 | up_read(&ctrl->namespaces_rwsem); |
7cf0d7c0 | 4712 | return timeout; |
302ad8cc KB |
4713 | } |
4714 | EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout); | |
4715 | ||
4716 | void nvme_wait_freeze(struct nvme_ctrl *ctrl) | |
4717 | { | |
4718 | struct nvme_ns *ns; | |
4719 | ||
765cc031 | 4720 | down_read(&ctrl->namespaces_rwsem); |
302ad8cc KB |
4721 | list_for_each_entry(ns, &ctrl->namespaces, list) |
4722 | blk_mq_freeze_queue_wait(ns->queue); | |
765cc031 | 4723 | up_read(&ctrl->namespaces_rwsem); |
302ad8cc KB |
4724 | } |
4725 | EXPORT_SYMBOL_GPL(nvme_wait_freeze); | |
4726 | ||
4727 | void nvme_start_freeze(struct nvme_ctrl *ctrl) | |
4728 | { | |
4729 | struct nvme_ns *ns; | |
4730 | ||
839a40d1 | 4731 | set_bit(NVME_CTRL_FROZEN, &ctrl->flags); |
765cc031 | 4732 | down_read(&ctrl->namespaces_rwsem); |
302ad8cc | 4733 | list_for_each_entry(ns, &ctrl->namespaces, list) |
1671d522 | 4734 | blk_freeze_queue_start(ns->queue); |
765cc031 | 4735 | up_read(&ctrl->namespaces_rwsem); |
302ad8cc KB |
4736 | } |
4737 | EXPORT_SYMBOL_GPL(nvme_start_freeze); | |
4738 | ||
9f27bd70 | 4739 | void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl) |
363c9aac | 4740 | { |
ba0718a6 CH |
4741 | if (!ctrl->tagset) |
4742 | return; | |
98d81f0d CL |
4743 | if (!test_and_set_bit(NVME_CTRL_STOPPED, &ctrl->flags)) |
4744 | blk_mq_quiesce_tagset(ctrl->tagset); | |
4745 | else | |
4746 | blk_mq_wait_quiesce_done(ctrl->tagset); | |
363c9aac | 4747 | } |
9f27bd70 | 4748 | EXPORT_SYMBOL_GPL(nvme_quiesce_io_queues); |
363c9aac | 4749 | |
9f27bd70 | 4750 | void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl) |
363c9aac | 4751 | { |
ba0718a6 CH |
4752 | if (!ctrl->tagset) |
4753 | return; | |
98d81f0d CL |
4754 | if (test_and_clear_bit(NVME_CTRL_STOPPED, &ctrl->flags)) |
4755 | blk_mq_unquiesce_tagset(ctrl->tagset); | |
363c9aac | 4756 | } |
9f27bd70 | 4757 | EXPORT_SYMBOL_GPL(nvme_unquiesce_io_queues); |
363c9aac | 4758 | |
9f27bd70 | 4759 | void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl) |
a277654b | 4760 | { |
9e6a6b12 ML |
4761 | if (!test_and_set_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags)) |
4762 | blk_mq_quiesce_queue(ctrl->admin_q); | |
26af1cd0 | 4763 | else |
483239c7 | 4764 | blk_mq_wait_quiesce_done(ctrl->admin_q->tag_set); |
a277654b | 4765 | } |
9f27bd70 | 4766 | EXPORT_SYMBOL_GPL(nvme_quiesce_admin_queue); |
a277654b | 4767 | |
9f27bd70 | 4768 | void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl) |
a277654b | 4769 | { |
9e6a6b12 ML |
4770 | if (test_and_clear_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags)) |
4771 | blk_mq_unquiesce_queue(ctrl->admin_q); | |
a277654b | 4772 | } |
9f27bd70 | 4773 | EXPORT_SYMBOL_GPL(nvme_unquiesce_admin_queue); |
a277654b | 4774 | |
04800fbf | 4775 | void nvme_sync_io_queues(struct nvme_ctrl *ctrl) |
d6135c3a KB |
4776 | { |
4777 | struct nvme_ns *ns; | |
4778 | ||
4779 | down_read(&ctrl->namespaces_rwsem); | |
4780 | list_for_each_entry(ns, &ctrl->namespaces, list) | |
4781 | blk_sync_queue(ns->queue); | |
4782 | up_read(&ctrl->namespaces_rwsem); | |
04800fbf CL |
4783 | } |
4784 | EXPORT_SYMBOL_GPL(nvme_sync_io_queues); | |
03894b7a | 4785 | |
04800fbf CL |
4786 | void nvme_sync_queues(struct nvme_ctrl *ctrl) |
4787 | { | |
4788 | nvme_sync_io_queues(ctrl); | |
03894b7a EN |
4789 | if (ctrl->admin_q) |
4790 | blk_sync_queue(ctrl->admin_q); | |
d6135c3a KB |
4791 | } |
4792 | EXPORT_SYMBOL_GPL(nvme_sync_queues); | |
4793 | ||
b2702aaa | 4794 | struct nvme_ctrl *nvme_ctrl_from_file(struct file *file) |
f783f444 | 4795 | { |
b2702aaa CK |
4796 | if (file->f_op != &nvme_dev_fops) |
4797 | return NULL; | |
4798 | return file->private_data; | |
f783f444 | 4799 | } |
b2702aaa | 4800 | EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, NVME_TARGET_PASSTHRU); |
f783f444 | 4801 | |
81101540 CH |
4802 | /* |
4803 | * Check we didn't inadvertently grow the command structure sizes: | |
4804 | */ | |
4805 | static inline void _nvme_check_size(void) | |
4806 | { | |
4807 | BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64); | |
4808 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
4809 | BUILD_BUG_ON(sizeof(struct nvme_identify) != 64); | |
4810 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
4811 | BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64); | |
4812 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); | |
4813 | BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64); | |
4814 | BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64); | |
4815 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); | |
4816 | BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64); | |
4817 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
4818 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); | |
4819 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); | |
354201c5 CH |
4820 | BUILD_BUG_ON(sizeof(struct nvme_id_ns_cs_indep) != |
4821 | NVME_IDENTIFY_DATA_SIZE); | |
240e6ee2 | 4822 | BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE); |
4020aad8 | 4823 | BUILD_BUG_ON(sizeof(struct nvme_id_ns_nvm) != NVME_IDENTIFY_DATA_SIZE); |
240e6ee2 | 4824 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE); |
5befc7c2 | 4825 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_nvm) != NVME_IDENTIFY_DATA_SIZE); |
81101540 CH |
4826 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); |
4827 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); | |
4828 | BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); | |
4829 | BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64); | |
4020aad8 | 4830 | BUILD_BUG_ON(sizeof(struct nvme_feat_host_behavior) != 512); |
81101540 CH |
4831 | } |
4832 | ||
4833 | ||
893a74b7 | 4834 | static int __init nvme_core_init(void) |
5bae7f73 | 4835 | { |
b227c59b | 4836 | int result = -ENOMEM; |
5bae7f73 | 4837 | |
81101540 CH |
4838 | _nvme_check_size(); |
4839 | ||
9a6327d2 SG |
4840 | nvme_wq = alloc_workqueue("nvme-wq", |
4841 | WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0); | |
4842 | if (!nvme_wq) | |
b227c59b RS |
4843 | goto out; |
4844 | ||
4845 | nvme_reset_wq = alloc_workqueue("nvme-reset-wq", | |
4846 | WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0); | |
4847 | if (!nvme_reset_wq) | |
4848 | goto destroy_wq; | |
4849 | ||
4850 | nvme_delete_wq = alloc_workqueue("nvme-delete-wq", | |
4851 | WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0); | |
4852 | if (!nvme_delete_wq) | |
4853 | goto destroy_reset_wq; | |
9a6327d2 | 4854 | |
f68abd9c JG |
4855 | result = alloc_chrdev_region(&nvme_ctrl_base_chr_devt, 0, |
4856 | NVME_MINORS, "nvme"); | |
f3ca80fc | 4857 | if (result < 0) |
b227c59b | 4858 | goto destroy_delete_wq; |
f3ca80fc | 4859 | |
1aaba11d | 4860 | nvme_class = class_create("nvme"); |
f3ca80fc CH |
4861 | if (IS_ERR(nvme_class)) { |
4862 | result = PTR_ERR(nvme_class); | |
4863 | goto unregister_chrdev; | |
4864 | } | |
a42f42e5 | 4865 | nvme_class->dev_uevent = nvme_class_uevent; |
f3ca80fc | 4866 | |
1aaba11d | 4867 | nvme_subsys_class = class_create("nvme-subsystem"); |
ab9e00cc CH |
4868 | if (IS_ERR(nvme_subsys_class)) { |
4869 | result = PTR_ERR(nvme_subsys_class); | |
4870 | goto destroy_class; | |
4871 | } | |
2637baed MI |
4872 | |
4873 | result = alloc_chrdev_region(&nvme_ns_chr_devt, 0, NVME_MINORS, | |
4874 | "nvme-generic"); | |
4875 | if (result < 0) | |
4876 | goto destroy_subsys_class; | |
4877 | ||
1aaba11d | 4878 | nvme_ns_chr_class = class_create("nvme-generic"); |
2637baed MI |
4879 | if (IS_ERR(nvme_ns_chr_class)) { |
4880 | result = PTR_ERR(nvme_ns_chr_class); | |
4881 | goto unregister_generic_ns; | |
4882 | } | |
9d77eb52 HR |
4883 | result = nvme_init_auth(); |
4884 | if (result) | |
706add13 | 4885 | goto destroy_ns_chr; |
5bae7f73 | 4886 | return 0; |
f3ca80fc | 4887 | |
e481fc0a SG |
4888 | destroy_ns_chr: |
4889 | class_destroy(nvme_ns_chr_class); | |
2637baed MI |
4890 | unregister_generic_ns: |
4891 | unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS); | |
4892 | destroy_subsys_class: | |
4893 | class_destroy(nvme_subsys_class); | |
ab9e00cc CH |
4894 | destroy_class: |
4895 | class_destroy(nvme_class); | |
9a6327d2 | 4896 | unregister_chrdev: |
f68abd9c | 4897 | unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS); |
b227c59b RS |
4898 | destroy_delete_wq: |
4899 | destroy_workqueue(nvme_delete_wq); | |
4900 | destroy_reset_wq: | |
4901 | destroy_workqueue(nvme_reset_wq); | |
9a6327d2 SG |
4902 | destroy_wq: |
4903 | destroy_workqueue(nvme_wq); | |
b227c59b | 4904 | out: |
f3ca80fc | 4905 | return result; |
5bae7f73 CH |
4906 | } |
4907 | ||
893a74b7 | 4908 | static void __exit nvme_core_exit(void) |
5bae7f73 | 4909 | { |
e481fc0a | 4910 | nvme_exit_auth(); |
2637baed | 4911 | class_destroy(nvme_ns_chr_class); |
ab9e00cc | 4912 | class_destroy(nvme_subsys_class); |
f3ca80fc | 4913 | class_destroy(nvme_class); |
2637baed | 4914 | unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS); |
f68abd9c | 4915 | unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS); |
b227c59b RS |
4916 | destroy_workqueue(nvme_delete_wq); |
4917 | destroy_workqueue(nvme_reset_wq); | |
9a6327d2 | 4918 | destroy_workqueue(nvme_wq); |
2637baed | 4919 | ida_destroy(&nvme_ns_chr_minor_ida); |
f41cfd5d | 4920 | ida_destroy(&nvme_instance_ida); |
5bae7f73 | 4921 | } |
576d55d6 ML |
4922 | |
4923 | MODULE_LICENSE("GPL"); | |
4924 | MODULE_VERSION("1.0"); | |
92b0b0ff | 4925 | MODULE_DESCRIPTION("NVMe host core framework"); |
576d55d6 ML |
4926 | module_init(nvme_core_init); |
4927 | module_exit(nvme_core_exit); |