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nvme: cleanup double shift issue
[linux-2.6-block.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0 30#include <asm/unaligned.h>
21d34711 31
3d030e41
JT		 32#define CREATE_TRACE_POINTS
33#include "trace.h"
34
21d34711 35#include "nvme.h"
038bd4cb 36#include "fabrics.h"
21d34711 37
f3ca80fc
CH		 38#define NVME_MINORS (1U << MINORBITS)
39
8ae4e447
MO		 40unsigned int admin_timeout = 60;
41module_param(admin_timeout, uint, 0644);
ba0ba7d3 42MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 43EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 44
8ae4e447
MO		 45unsigned int nvme_io_timeout = 30;
46module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 47MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 48EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 49
b3b1b0b0 50static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 51module_param(shutdown_timeout, byte, 0644);
52MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
53
44e44b29
CH		 54static u8 nvme_max_retries = 5;
55module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 56MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 57
9947d6a0 58static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 59module_param(default_ps_max_latency_us, ulong, 0644);
60MODULE_PARM_DESC(default_ps_max_latency_us,
61 "max power saving latency for new devices; use PM QOS to change per device");
62
c35e30b4
AL		 63static bool force_apst;
64module_param(force_apst, bool, 0644);
65MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
66
f5d11840
JA		 67static bool streams;
68module_param(streams, bool, 0644);
69MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
70
b227c59b
RS		 71/*
72 * nvme_wq - hosts nvme related works that are not reset or delete
73 * nvme_reset_wq - hosts nvme reset works
74 * nvme_delete_wq - hosts nvme delete works
75 *
76 * nvme_wq will host works such are scan, aen handling, fw activation,
77 * keep-alive error recovery, periodic reconnects etc. nvme_reset_wq
78 * runs reset works which also flush works hosted on nvme_wq for
79 * serialization purposes. nvme_delete_wq host controller deletion
80 * works which flush reset works for serialization.
81 */
9a6327d2
SG		 82struct workqueue_struct *nvme_wq;
83EXPORT_SYMBOL_GPL(nvme_wq);
84
b227c59b
RS		 85struct workqueue_struct *nvme_reset_wq;
86EXPORT_SYMBOL_GPL(nvme_reset_wq);
87
88struct workqueue_struct *nvme_delete_wq;
89EXPORT_SYMBOL_GPL(nvme_delete_wq);
90
ab9e00cc
CH		 91static DEFINE_IDA(nvme_subsystems_ida);
92static LIST_HEAD(nvme_subsystems);
93static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 94
9843f685 95static DEFINE_IDA(nvme_instance_ida);
a6a5149b 96static dev_t nvme_chr_devt;
f3ca80fc 97static struct class *nvme_class;
ab9e00cc 98static struct class *nvme_subsys_class;
f3ca80fc 99
84fef62d
KB		 100static void nvme_ns_remove(struct nvme_ns *ns);
101static int nvme_revalidate_disk(struct gendisk *disk);
12d9f070 102static void nvme_put_subsystem(struct nvme_subsystem *subsys);
f3ca80fc 103
50e8d8ee
CH		 104static void nvme_queue_scan(struct nvme_ctrl *ctrl)
105{
106 /*
107 * Only new queue scan work when admin and IO queues are both alive
108 */
109 if (ctrl->state == NVME_CTRL_LIVE)
110 queue_work(nvme_wq, &ctrl->scan_work);
111}
112
d86c4d8e
CH		 113int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
114{
115 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
116 return -EBUSY;
b227c59b 117 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 118 return -EBUSY;
119 return 0;
120}
121EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
122
79c48ccf 123int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 124{
125 int ret;
126
127 ret = nvme_reset_ctrl(ctrl);
8000d1fd 128 if (!ret) {
d86c4d8e 129 flush_work(&ctrl->reset_work);
4e50d9eb
CM		 130 if (ctrl->state != NVME_CTRL_LIVE &&
131 ctrl->state != NVME_CTRL_ADMIN_ONLY)
8000d1fd
NC		 132 ret = -ENETRESET;
133 }
134
d86c4d8e
CH		 135 return ret;
136}
79c48ccf 137EXPORT_SYMBOL_GPL(nvme_reset_ctrl_sync);
d86c4d8e 138
c5017e85
CH		 139static void nvme_delete_ctrl_work(struct work_struct *work)
140{
141 struct nvme_ctrl *ctrl =
142 container_of(work, struct nvme_ctrl, delete_work);
143
77d0612d
MG		 144 dev_info(ctrl->device,
145 "Removing ctrl: NQN \"%s\"\n", ctrl->opts->subsysnqn);
146
4054637c 147 flush_work(&ctrl->reset_work);
6cd53d14
CH		 148 nvme_stop_ctrl(ctrl);
149 nvme_remove_namespaces(ctrl);
c5017e85 150 ctrl->ops->delete_ctrl(ctrl);
6cd53d14
CH		 151 nvme_uninit_ctrl(ctrl);
152 nvme_put_ctrl(ctrl);
c5017e85
CH		 153}
154
155int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
156{
157 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
158 return -EBUSY;
b227c59b 159 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 160 return -EBUSY;
161 return 0;
162}
163EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
164
165int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
166{
167 int ret = 0;
168
169 /*
170 * Keep a reference until the work is flushed since ->delete_ctrl
171 * can free the controller.
172 */
173 nvme_get_ctrl(ctrl);
174 ret = nvme_delete_ctrl(ctrl);
175 if (!ret)
176 flush_work(&ctrl->delete_work);
177 nvme_put_ctrl(ctrl);
178 return ret;
179}
180EXPORT_SYMBOL_GPL(nvme_delete_ctrl_sync);
181
715ea9e0
CH		 182static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
183{
184 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
185}
186
2a842aca 187static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 188{
189 switch (nvme_req(req)->status & 0x7ff) {
190 case NVME_SC_SUCCESS:
2a842aca 191 return BLK_STS_OK;
27fa9bc5 192 case NVME_SC_CAP_EXCEEDED:
2a842aca 193 return BLK_STS_NOSPC;
e96fef2c
KB		 194 case NVME_SC_LBA_RANGE:
195 return BLK_STS_TARGET;
196 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 197 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 198 case NVME_SC_INVALID_OPCODE:
199 case NVME_SC_INVALID_FIELD:
200 case NVME_SC_INVALID_NS:
2a842aca 201 return BLK_STS_NOTSUPP;
e02ab023
JG		 202 case NVME_SC_WRITE_FAULT:
203 case NVME_SC_READ_ERROR:
204 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 205 case NVME_SC_ACCESS_DENIED:
206 case NVME_SC_READ_ONLY:
e96fef2c 207 case NVME_SC_COMPARE_FAILED:
2a842aca 208 return BLK_STS_MEDIUM;
a751da33
CH		 209 case NVME_SC_GUARD_CHECK:
210 case NVME_SC_APPTAG_CHECK:
211 case NVME_SC_REFTAG_CHECK:
212 case NVME_SC_INVALID_PI:
213 return BLK_STS_PROTECTION;
214 case NVME_SC_RESERVATION_CONFLICT:
215 return BLK_STS_NEXUS;
2a842aca
CH		 216 default:
217 return BLK_STS_IOERR;
27fa9bc5
CH		 218 }
219}
27fa9bc5 220
f6324b1b 221static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 222{
f6324b1b
CH		 223 if (blk_noretry_request(req))
224 return false;
27fa9bc5 225 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b 226 return false;
44e44b29 227 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 228 return false;
229 return true;
77f02a7a
CH		 230}
231
232void nvme_complete_rq(struct request *req)
233{
908e4564
KB		 234 blk_status_t status = nvme_error_status(req);
235
ca5554a6
JT		 236 trace_nvme_complete_rq(req);
237
908e4564
KB		 238 if (unlikely(status != BLK_STS_OK && nvme_req_needs_retry(req))) {
239 if (nvme_req_needs_failover(req, status)) {
32acab31
CH		 240 nvme_failover_req(req);
241 return;
242 }
243
244 if (!blk_queue_dying(req->q)) {
245 nvme_req(req)->retries++;
246 blk_mq_requeue_request(req, true);
247 return;
248 }
77f02a7a 249 }
908e4564 250 blk_mq_end_request(req, status);
77f02a7a
CH		 251}
252EXPORT_SYMBOL_GPL(nvme_complete_rq);
253
c55a2fd4
ML		 254void nvme_cancel_request(struct request *req, void *data, bool reserved)
255{
c55a2fd4
ML		 256 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
257 "Cancelling I/O %d", req->tag);
258
e54b064c 259 nvme_req(req)->status = NVME_SC_ABORT_REQ;
08e0029a 260 blk_mq_complete_request(req);
27fa9bc5 261
c55a2fd4
ML		 262}
263EXPORT_SYMBOL_GPL(nvme_cancel_request);
264
bb8d261e
CH		 265bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
266 enum nvme_ctrl_state new_state)
267{
f6b6a28e 268 enum nvme_ctrl_state old_state;
0a72bbba 269 unsigned long flags;
bb8d261e
CH		 270 bool changed = false;
271
0a72bbba 272 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 273
274 old_state = ctrl->state;
bb8d261e 275 switch (new_state) {
2b1b7e78
JW		 276 case NVME_CTRL_ADMIN_ONLY:
277 switch (old_state) {
ad6a0a52 278 case NVME_CTRL_CONNECTING:
2b1b7e78
JW		 279 changed = true;
280 /* FALLTHRU */
281 default:
282 break;
283 }
284 break;
bb8d261e
CH		 285 case NVME_CTRL_LIVE:
286 switch (old_state) {
7d2e8008 287 case NVME_CTRL_NEW:
bb8d261e 288 case NVME_CTRL_RESETTING:
ad6a0a52 289 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 290 changed = true;
291 /* FALLTHRU */
292 default:
293 break;
294 }
295 break;
296 case NVME_CTRL_RESETTING:
297 switch (old_state) {
298 case NVME_CTRL_NEW:
def61eca 299 case NVME_CTRL_LIVE:
2b1b7e78 300 case NVME_CTRL_ADMIN_ONLY:
def61eca
CH		 301 changed = true;
302 /* FALLTHRU */
303 default:
304 break;
305 }
306 break;
ad6a0a52 307 case NVME_CTRL_CONNECTING:
def61eca 308 switch (old_state) {
b754a32c 309 case NVME_CTRL_NEW:
3cec7f9d 310 case NVME_CTRL_RESETTING:
bb8d261e
CH		 311 changed = true;
312 /* FALLTHRU */
313 default:
314 break;
315 }
316 break;
317 case NVME_CTRL_DELETING:
318 switch (old_state) {
319 case NVME_CTRL_LIVE:
2b1b7e78 320 case NVME_CTRL_ADMIN_ONLY:
bb8d261e 321 case NVME_CTRL_RESETTING:
ad6a0a52 322 case NVME_CTRL_CONNECTING:
bb8d261e
CH		 323 changed = true;
324 /* FALLTHRU */
325 default:
326 break;
327 }
328 break;
0ff9d4e1
KB		 329 case NVME_CTRL_DEAD:
330 switch (old_state) {
331 case NVME_CTRL_DELETING:
332 changed = true;
333 /* FALLTHRU */
334 default:
335 break;
336 }
337 break;
bb8d261e
CH		 338 default:
339 break;
340 }
bb8d261e
CH		 341
342 if (changed)
343 ctrl->state = new_state;
344
0a72bbba 345 spin_unlock_irqrestore(&ctrl->lock, flags);
32acab31
CH		 346 if (changed && ctrl->state == NVME_CTRL_LIVE)
347 nvme_kick_requeue_lists(ctrl);
bb8d261e
CH		 348 return changed;
349}
350EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
351
ed754e5d
CH		 352static void nvme_free_ns_head(struct kref *ref)
353{
354 struct nvme_ns_head *head =
355 container_of(ref, struct nvme_ns_head, ref);
356
32acab31 357 nvme_mpath_remove_disk(head);
ed754e5d
CH		 358 ida_simple_remove(&head->subsys->ns_ida, head->instance);
359 list_del_init(&head->entry);
360 cleanup_srcu_struct(&head->srcu);
12d9f070 361 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 362 kfree(head);
363}
364
365static void nvme_put_ns_head(struct nvme_ns_head *head)
366{
367 kref_put(&head->ref, nvme_free_ns_head);
368}
369
1673f1f0
CH		 370static void nvme_free_ns(struct kref *kref)
371{
372 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
373
b0b4e09c
MB		 374 if (ns->ndev)
375 nvme_nvm_unregister(ns);
1673f1f0 376
1673f1f0 377 put_disk(ns->disk);
ed754e5d 378 nvme_put_ns_head(ns->head);
075790eb 379 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 380 kfree(ns);
381}
382
5bae7f73 383static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 384{
385 kref_put(&ns->kref, nvme_free_ns);
386}
387
bb06ec31
JS		 388static inline void nvme_clear_nvme_request(struct request *req)
389{
390 if (!(req->rq_flags & RQF_DONTPREP)) {
391 nvme_req(req)->retries = 0;
392 nvme_req(req)->flags = 0;
393 req->rq_flags |= RQF_DONTPREP;
394 }
395}
396
4160982e 397struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 398 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
21d34711 399{
aebf526b 400 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 401 struct request *req;
21d34711 402
eb71f435 403 if (qid == NVME_QID_ANY) {
aebf526b 404 req = blk_mq_alloc_request(q, op, flags);
eb71f435 405 } else {
aebf526b 406 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 407 qid ? qid - 1 : 0);
408 }
21d34711 409 if (IS_ERR(req))
4160982e 410 return req;
21d34711 411
21d34711 412 req->cmd_flags |= REQ_FAILFAST_DRIVER;
bb06ec31 413 nvme_clear_nvme_request(req);
d49187e9 414 nvme_req(req)->cmd = cmd;
21d34711 415
4160982e
CH		 416 return req;
417}
576d55d6 418EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 419
f5d11840
JA		 420static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
421{
422 struct nvme_command c;
423
424 memset(&c, 0, sizeof(c));
425
426 c.directive.opcode = nvme_admin_directive_send;
62346eae 427 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 428 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
429 c.directive.dtype = NVME_DIR_IDENTIFY;
430 c.directive.tdtype = NVME_DIR_STREAMS;
431 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
432
433 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
434}
435
436static int nvme_disable_streams(struct nvme_ctrl *ctrl)
437{
438 return nvme_toggle_streams(ctrl, false);
439}
440
441static int nvme_enable_streams(struct nvme_ctrl *ctrl)
442{
443 return nvme_toggle_streams(ctrl, true);
444}
445
446static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
447 struct streams_directive_params *s, u32 nsid)
448{
449 struct nvme_command c;
450
451 memset(&c, 0, sizeof(c));
452 memset(s, 0, sizeof(*s));
453
454 c.directive.opcode = nvme_admin_directive_recv;
455 c.directive.nsid = cpu_to_le32(nsid);
a082b426 456 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 457 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
458 c.directive.dtype = NVME_DIR_STREAMS;
459
460 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
461}
462
463static int nvme_configure_directives(struct nvme_ctrl *ctrl)
464{
465 struct streams_directive_params s;
466 int ret;
467
468 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
469 return 0;
470 if (!streams)
471 return 0;
472
473 ret = nvme_enable_streams(ctrl);
474 if (ret)
475 return ret;
476
62346eae 477 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 478 if (ret)
479 return ret;
480
481 ctrl->nssa = le16_to_cpu(s.nssa);
482 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
483 dev_info(ctrl->device, "too few streams (%u) available\n",
484 ctrl->nssa);
485 nvme_disable_streams(ctrl);
486 return 0;
487 }
488
489 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
490 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
491 return 0;
492}
493
494/*
495 * Check if 'req' has a write hint associated with it. If it does, assign
496 * a valid namespace stream to the write.
497 */
498static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
499 struct request *req, u16 *control,
500 u32 *dsmgmt)
501{
502 enum rw_hint streamid = req->write_hint;
503
504 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
505 streamid = 0;
506 else {
507 streamid--;
508 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
509 return;
510
511 *control |= NVME_RW_DTYPE_STREAMS;
512 *dsmgmt |= streamid << 16;
513 }
514
515 if (streamid < ARRAY_SIZE(req->q->write_hints))
516 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
517}
518
8093f7ca
ML		 519static inline void nvme_setup_flush(struct nvme_ns *ns,
520 struct nvme_command *cmnd)
521{
522 memset(cmnd, 0, sizeof(*cmnd));
523 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 524 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 525}
526
fc17b653 527static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 528 struct nvme_command *cmnd)
529{
b35ba01e 530 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 531 struct nvme_dsm_range *range;
b35ba01e 532 struct bio *bio;
8093f7ca 533
b35ba01e 534 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca 535 if (!range)
fc17b653 536 return BLK_STS_RESOURCE;
8093f7ca 537
b35ba01e
CH		 538 __rq_for_each_bio(bio, req) {
539 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
540 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
541
8cb6af7b
KB		 542 if (n < segments) {
543 range[n].cattr = cpu_to_le32(0);
544 range[n].nlb = cpu_to_le32(nlb);
545 range[n].slba = cpu_to_le64(slba);
546 }
b35ba01e
CH		 547 n++;
548 }
549
550 if (WARN_ON_ONCE(n != segments)) {
551 kfree(range);
fc17b653 552 return BLK_STS_IOERR;
b35ba01e 553 }
8093f7ca
ML		 554
555 memset(cmnd, 0, sizeof(*cmnd));
556 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 557 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 558 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 559 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
560
f9d03f96
CH		 561 req->special_vec.bv_page = virt_to_page(range);
562 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 563 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 564 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 565
fc17b653 566 return BLK_STS_OK;
8093f7ca 567}
8093f7ca 568
ebe6d874
CH		 569static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
570 struct request *req, struct nvme_command *cmnd)
8093f7ca 571{
f5d11840 572 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 573 u16 control = 0;
574 u32 dsmgmt = 0;
575
576 if (req->cmd_flags & REQ_FUA)
577 control |= NVME_RW_FUA;
578 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
579 control |= NVME_RW_LR;
580
581 if (req->cmd_flags & REQ_RAHEAD)
582 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
583
584 memset(cmnd, 0, sizeof(*cmnd));
585 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
ed754e5d 586 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 587 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
588 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
589
f5d11840
JA		 590 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
591 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
592
8093f7ca 593 if (ns->ms) {
715ea9e0
CH		 594 /*
595 * If formated with metadata, the block layer always provides a
596 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
597 * we enable the PRACT bit for protection information or set the
598 * namespace capacity to zero to prevent any I/O.
599 */
600 if (!blk_integrity_rq(req)) {
601 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
602 return BLK_STS_NOTSUPP;
603 control |= NVME_RW_PRINFO_PRACT;
604 }
605
8093f7ca
ML		 606 switch (ns->pi_type) {
607 case NVME_NS_DPS_PI_TYPE3:
608 control |= NVME_RW_PRINFO_PRCHK_GUARD;
609 break;
610 case NVME_NS_DPS_PI_TYPE1:
611 case NVME_NS_DPS_PI_TYPE2:
612 control |= NVME_RW_PRINFO_PRCHK_GUARD |
613 NVME_RW_PRINFO_PRCHK_REF;
614 cmnd->rw.reftag = cpu_to_le32(
615 nvme_block_nr(ns, blk_rq_pos(req)));
616 break;
617 }
8093f7ca
ML		 618 }
619
620 cmnd->rw.control = cpu_to_le16(control);
621 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 622 return 0;
8093f7ca
ML		 623}
624
fc17b653 625blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 626 struct nvme_command *cmd)
627{
fc17b653 628 blk_status_t ret = BLK_STS_OK;
8093f7ca 629
bb06ec31 630 nvme_clear_nvme_request(req);
987f699a 631
aebf526b
CH		 632 switch (req_op(req)) {
633 case REQ_OP_DRV_IN:
634 case REQ_OP_DRV_OUT:
d49187e9 635 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 636 break;
637 case REQ_OP_FLUSH:
8093f7ca 638 nvme_setup_flush(ns, cmd);
aebf526b 639 break;
e850fd16
CH		 640 case REQ_OP_WRITE_ZEROES:
641 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 642 case REQ_OP_DISCARD:
8093f7ca 643 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 644 break;
645 case REQ_OP_READ:
646 case REQ_OP_WRITE:
ebe6d874 647 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 648 break;
649 default:
650 WARN_ON_ONCE(1);
fc17b653 651 return BLK_STS_IOERR;
aebf526b 652 }
8093f7ca 653
721b3917 654 cmd->common.command_id = req->tag;
3d030e41
JT		 655 if (ns)
656 trace_nvme_setup_nvm_cmd(req->q->id, cmd);
657 else
658 trace_nvme_setup_admin_cmd(cmd);
8093f7ca
ML		 659 return ret;
660}
661EXPORT_SYMBOL_GPL(nvme_setup_cmd);
662
4160982e
CH		 663/*
664 * Returns 0 on success. If the result is negative, it's a Linux error code;
665 * if the result is positive, it's an NVM Express status code
666 */
667int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 668 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef
BVA		 669 unsigned timeout, int qid, int at_head,
670 blk_mq_req_flags_t flags)
4160982e
CH		 671{
672 struct request *req;
673 int ret;
674
eb71f435 675 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 676 if (IS_ERR(req))
677 return PTR_ERR(req);
678
679 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
680
21d34711
CH		 681 if (buffer && bufflen) {
682 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
683 if (ret)
684 goto out;
4160982e
CH		 685 }
686
eb71f435 687 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 688 if (result)
689 *result = nvme_req(req)->result;
27fa9bc5
CH		 690 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
691 ret = -EINTR;
692 else
693 ret = nvme_req(req)->status;
4160982e
CH		 694 out:
695 blk_mq_free_request(req);
696 return ret;
697}
eb71f435 698EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 699
700int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
701 void *buffer, unsigned bufflen)
702{
eb71f435
CH		 703 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
704 NVME_QID_ANY, 0, 0);
4160982e 705}
576d55d6 706EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 707
1cad6562
CH		 708static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
709 unsigned len, u32 seed, bool write)
710{
711 struct bio_integrity_payload *bip;
712 int ret = -ENOMEM;
713 void *buf;
714
715 buf = kmalloc(len, GFP_KERNEL);
716 if (!buf)
717 goto out;
718
719 ret = -EFAULT;
720 if (write && copy_from_user(buf, ubuf, len))
721 goto out_free_meta;
722
723 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
724 if (IS_ERR(bip)) {
725 ret = PTR_ERR(bip);
726 goto out_free_meta;
727 }
728
729 bip->bip_iter.bi_size = len;
730 bip->bip_iter.bi_sector = seed;
731 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
732 offset_in_page(buf));
733 if (ret == len)
734 return buf;
735 ret = -ENOMEM;
736out_free_meta:
737 kfree(buf);
738out:
739 return ERR_PTR(ret);
740}
741
63263d60 742static int nvme_submit_user_cmd(struct request_queue *q,
485783ca
KB		 743 struct nvme_command *cmd, void __user *ubuffer,
744 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
745 u32 meta_seed, u32 *result, unsigned timeout)
4160982e 746{
7a5abb4b 747 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 748 struct nvme_ns *ns = q->queuedata;
749 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 750 struct request *req;
0b7f1f26
KB		 751 struct bio *bio = NULL;
752 void *meta = NULL;
4160982e
CH		 753 int ret;
754
eb71f435 755 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 756 if (IS_ERR(req))
757 return PTR_ERR(req);
758
759 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
bb06ec31 760 nvme_req(req)->flags |= NVME_REQ_USERCMD;
4160982e
CH		 761
762 if (ubuffer && bufflen) {
21d34711
CH		 763 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
764 GFP_KERNEL);
765 if (ret)
766 goto out;
767 bio = req->bio;
74d46992 768 bio->bi_disk = disk;
1cad6562
CH		 769 if (disk && meta_buffer && meta_len) {
770 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
771 meta_seed, write);
772 if (IS_ERR(meta)) {
773 ret = PTR_ERR(meta);
0b7f1f26
KB		 774 goto out_unmap;
775 }
f31a2110 776 req->cmd_flags |= REQ_INTEGRITY;
0b7f1f26
KB		 777 }
778 }
1cad6562 779
0b7f1f26 780 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 781 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
782 ret = -EINTR;
783 else
784 ret = nvme_req(req)->status;
21d34711 785 if (result)
d49187e9 786 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 787 if (meta && !ret && !write) {
788 if (copy_to_user(meta_buffer, meta, meta_len))
789 ret = -EFAULT;
790 }
0b7f1f26
KB		 791 kfree(meta);
792 out_unmap:
74d46992 793 if (bio)
0b7f1f26 794 blk_rq_unmap_user(bio);
21d34711
CH		 795 out:
796 blk_mq_free_request(req);
797 return ret;
798}
799
2a842aca 800static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 801{
802 struct nvme_ctrl *ctrl = rq->end_io_data;
803
804 blk_mq_free_request(rq);
805
2a842aca 806 if (status) {
038bd4cb 807 dev_err(ctrl->device,
2a842aca
CH		 808 "failed nvme_keep_alive_end_io error=%d\n",
809 status);
038bd4cb
SG		 810 return;
811 }
812
813 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
814}
815
816static int nvme_keep_alive(struct nvme_ctrl *ctrl)
817{
038bd4cb
SG		 818 struct request *rq;
819
0a34e466 820 rq = nvme_alloc_request(ctrl->admin_q, &ctrl->ka_cmd, BLK_MQ_REQ_RESERVED,
038bd4cb
SG		 821 NVME_QID_ANY);
822 if (IS_ERR(rq))
823 return PTR_ERR(rq);
824
825 rq->timeout = ctrl->kato * HZ;
826 rq->end_io_data = ctrl;
827
828 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
829
830 return 0;
831}
832
833static void nvme_keep_alive_work(struct work_struct *work)
834{
835 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
836 struct nvme_ctrl, ka_work);
837
838 if (nvme_keep_alive(ctrl)) {
839 /* allocation failure, reset the controller */
840 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 841 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 842 return;
843 }
844}
845
00b683db 846static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 847{
848 if (unlikely(ctrl->kato == 0))
849 return;
850
851 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
0a34e466
RD		 852 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
853 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
038bd4cb
SG		 854 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
855}
038bd4cb
SG		 856
857void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
858{
859 if (unlikely(ctrl->kato == 0))
860 return;
861
862 cancel_delayed_work_sync(&ctrl->ka_work);
863}
864EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
865
3f7f25a9 866static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 867{
868 struct nvme_command c = { };
869 int error;
870
871 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
872 c.identify.opcode = nvme_admin_identify;
986994a2 873 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 874
875 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
876 if (!*id)
877 return -ENOMEM;
878
879 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
880 sizeof(struct nvme_id_ctrl));
881 if (error)
882 kfree(*id);
883 return error;
884}
885
cdbff4f2 886static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 887 struct nvme_ns_ids *ids)
3b22ba26
JT		 888{
889 struct nvme_command c = { };
890 int status;
891 void *data;
892 int pos;
893 int len;
894
895 c.identify.opcode = nvme_admin_identify;
896 c.identify.nsid = cpu_to_le32(nsid);
897 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
898
899 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
900 if (!data)
901 return -ENOMEM;
902
cdbff4f2 903 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 904 NVME_IDENTIFY_DATA_SIZE);
905 if (status)
906 goto free_data;
907
908 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
909 struct nvme_ns_id_desc *cur = data + pos;
910
911 if (cur->nidl == 0)
912 break;
913
914 switch (cur->nidt) {
915 case NVME_NIDT_EUI64:
916 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 917 dev_warn(ctrl->device,
3b22ba26
JT		 918 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
919 cur->nidl);
920 goto free_data;
921 }
922 len = NVME_NIDT_EUI64_LEN;
002fab04 923 memcpy(ids->eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 924 break;
925 case NVME_NIDT_NGUID:
926 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 927 dev_warn(ctrl->device,
3b22ba26
JT		 928 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
929 cur->nidl);
930 goto free_data;
931 }
932 len = NVME_NIDT_NGUID_LEN;
002fab04 933 memcpy(ids->nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 934 break;
935 case NVME_NIDT_UUID:
936 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 937 dev_warn(ctrl->device,
3b22ba26
JT		 938 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
939 cur->nidl);
940 goto free_data;
941 }
942 len = NVME_NIDT_UUID_LEN;
002fab04 943 uuid_copy(&ids->uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 944 break;
945 default:
946 /* Skip unnkown types */
947 len = cur->nidl;
948 break;
949 }
950
951 len += sizeof(*cur);
952 }
953free_data:
954 kfree(data);
955 return status;
956}
957
540c801c
KB		 958static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
959{
960 struct nvme_command c = { };
961
962 c.identify.opcode = nvme_admin_identify;
986994a2 963 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c 964 c.identify.nsid = cpu_to_le32(nsid);
42595eb7
MI		 965 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list,
966 NVME_IDENTIFY_DATA_SIZE);
540c801c
KB		 967}
968
cdbff4f2
CH		 969static struct nvme_id_ns *nvme_identify_ns(struct nvme_ctrl *ctrl,
970 unsigned nsid)
21d34711 971{
cdbff4f2 972 struct nvme_id_ns *id;
21d34711
CH		 973 struct nvme_command c = { };
974 int error;
975
976 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 977 c.identify.opcode = nvme_admin_identify;
978 c.identify.nsid = cpu_to_le32(nsid);
986994a2 979 c.identify.cns = NVME_ID_CNS_NS;
21d34711 980
cdbff4f2
CH		 981 id = kmalloc(sizeof(*id), GFP_KERNEL);
982 if (!id)
983 return NULL;
21d34711 984
cdbff4f2
CH		 985 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
986 if (error) {
987 dev_warn(ctrl->device, "Identify namespace failed\n");
988 kfree(id);
989 return NULL;
990 }
991
992 return id;
21d34711
CH		 993}
994
3f7f25a9 995static int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
1a6fe74d 996 void *buffer, size_t buflen, u32 *result)
21d34711
CH		 997{
998 struct nvme_command c;
d49187e9 999 union nvme_result res;
1cb3cce5 1000 int ret;
21d34711
CH		 1001
1002 memset(&c, 0, sizeof(c));
1003 c.features.opcode = nvme_admin_set_features;
21d34711
CH		 1004 c.features.fid = cpu_to_le32(fid);
1005 c.features.dword11 = cpu_to_le32(dword11);
1006
d49187e9 1007 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 1008 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 1009 if (ret >= 0 && result)
d49187e9 1010 *result = le32_to_cpu(res.u32);
1cb3cce5 1011 return ret;
21d34711
CH		 1012}
1013
9a0be7ab
CH		 1014int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1015{
1016 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1017 u32 result;
1018 int status, nr_io_queues;
1019
1a6fe74d 1020 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1021 &result);
f5fa90dc 1022 if (status < 0)
9a0be7ab
CH		 1023 return status;
1024
f5fa90dc
CH		 1025 /*
1026 * Degraded controllers might return an error when setting the queue
1027 * count. We still want to be able to bring them online and offer
1028 * access to the admin queue, as that might be only way to fix them up.
1029 */
1030 if (status > 0) {
f0425db0 1031 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1032 *count = 0;
1033 } else {
1034 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1035 *count = min(*count, nr_io_queues);
1036 }
1037
9a0be7ab
CH		 1038 return 0;
1039}
576d55d6 1040EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1041
c0561f82
HR		 1042#define NVME_AEN_SUPPORTED \
1043 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT)
1044
1045static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1046{
1047 u32 result;
1048 int status;
1049
1050 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT,
1051 ctrl->oaes & NVME_AEN_SUPPORTED, NULL, 0, &result);
1052 if (status)
1053 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
1054 ctrl->oaes & NVME_AEN_SUPPORTED);
1055}
1056
1673f1f0
CH		 1057static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1058{
1059 struct nvme_user_io io;
1060 struct nvme_command c;
1061 unsigned length, meta_len;
1062 void __user *metadata;
1063
1064 if (copy_from_user(&io, uio, sizeof(io)))
1065 return -EFAULT;
63088ec7
KB		 1066 if (io.flags)
1067 return -EINVAL;
1673f1f0
CH		 1068
1069 switch (io.opcode) {
1070 case nvme_cmd_write:
1071 case nvme_cmd_read:
1072 case nvme_cmd_compare:
1073 break;
1074 default:
1075 return -EINVAL;
1076 }
1077
1078 length = (io.nblocks + 1) << ns->lba_shift;
1079 meta_len = (io.nblocks + 1) * ns->ms;
1080 metadata = (void __user *)(uintptr_t)io.metadata;
1081
1082 if (ns->ext) {
1083 length += meta_len;
1084 meta_len = 0;
1085 } else if (meta_len) {
1086 if ((io.metadata & 3) || !io.metadata)
1087 return -EINVAL;
1088 }
1089
1090 memset(&c, 0, sizeof(c));
1091 c.rw.opcode = io.opcode;
1092 c.rw.flags = io.flags;
ed754e5d 1093 c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1094 c.rw.slba = cpu_to_le64(io.slba);
1095 c.rw.length = cpu_to_le16(io.nblocks);
1096 c.rw.control = cpu_to_le16(io.control);
1097 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1098 c.rw.reftag = cpu_to_le32(io.reftag);
1099 c.rw.apptag = cpu_to_le16(io.apptag);
1100 c.rw.appmask = cpu_to_le16(io.appmask);
1101
63263d60 1102 return nvme_submit_user_cmd(ns->queue, &c,
1673f1f0
CH		 1103 (void __user *)(uintptr_t)io.addr, length,
1104 metadata, meta_len, io.slba, NULL, 0);
1105}
1106
84fef62d
KB		 1107static u32 nvme_known_admin_effects(u8 opcode)
1108{
1109 switch (opcode) {
1110 case nvme_admin_format_nvm:
1111 return NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
1112 NVME_CMD_EFFECTS_CSE_MASK;
1113 case nvme_admin_sanitize_nvm:
1114 return NVME_CMD_EFFECTS_CSE_MASK;
1115 default:
1116 break;
1117 }
1118 return 0;
1119}
1120
1121static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1122 u8 opcode)
1123{
1124 u32 effects = 0;
1125
1126 if (ns) {
1127 if (ctrl->effects)
1128 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
1129 if (effects & ~NVME_CMD_EFFECTS_CSUPP)
1130 dev_warn(ctrl->device,
1131 "IO command:%02x has unhandled effects:%08x\n",
1132 opcode, effects);
1133 return 0;
1134 }
1135
1136 if (ctrl->effects)
62843c2e 1137 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
84fef62d
KB		 1138 else
1139 effects = nvme_known_admin_effects(opcode);
1140
1141 /*
1142 * For simplicity, IO to all namespaces is quiesced even if the command
1143 * effects say only one namespace is affected.
1144 */
1145 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
1146 nvme_start_freeze(ctrl);
1147 nvme_wait_freeze(ctrl);
1148 }
1149 return effects;
1150}
1151
1152static void nvme_update_formats(struct nvme_ctrl *ctrl)
1153{
3fd176b7
JW		 1154 struct nvme_ns *ns, *next;
1155 LIST_HEAD(rm_list);
84fef62d 1156
765cc031 1157 down_write(&ctrl->namespaces_rwsem);
84fef62d 1158 list_for_each_entry(ns, &ctrl->namespaces, list) {
3fd176b7
JW		 1159 if (ns->disk && nvme_revalidate_disk(ns->disk)) {
1160 list_move_tail(&ns->list, &rm_list);
1161 }
84fef62d 1162 }
765cc031 1163 up_write(&ctrl->namespaces_rwsem);
3fd176b7
JW		 1164
1165 list_for_each_entry_safe(ns, next, &rm_list, list)
1166 nvme_ns_remove(ns);
84fef62d
KB		 1167}
1168
1169static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1170{
1171 /*
1172 * Revalidate LBA changes prior to unfreezing. This is necessary to
1173 * prevent memory corruption if a logical block size was changed by
1174 * this command.
1175 */
1176 if (effects & NVME_CMD_EFFECTS_LBCC)
1177 nvme_update_formats(ctrl);
1178 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK))
1179 nvme_unfreeze(ctrl);
1180 if (effects & NVME_CMD_EFFECTS_CCC)
1181 nvme_init_identify(ctrl);
1182 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC))
1183 nvme_queue_scan(ctrl);
1184}
1185
f3ca80fc 1186static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 1187 struct nvme_passthru_cmd __user *ucmd)
1188{
1189 struct nvme_passthru_cmd cmd;
1190 struct nvme_command c;
1191 unsigned timeout = 0;
84fef62d 1192 u32 effects;
1673f1f0
CH		 1193 int status;
1194
1195 if (!capable(CAP_SYS_ADMIN))
1196 return -EACCES;
1197 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1198 return -EFAULT;
63088ec7
KB		 1199 if (cmd.flags)
1200 return -EINVAL;
1673f1f0
CH		 1201
1202 memset(&c, 0, sizeof(c));
1203 c.common.opcode = cmd.opcode;
1204 c.common.flags = cmd.flags;
1205 c.common.nsid = cpu_to_le32(cmd.nsid);
1206 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1207 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1208 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1209 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1210 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1211 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1212 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1213 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1214
1215 if (cmd.timeout_ms)
1216 timeout = msecs_to_jiffies(cmd.timeout_ms);
1217
84fef62d 1218 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1673f1f0 1219 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1220 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
63263d60
KB		 1221 (void __user *)(uintptr_t)cmd.metadata, cmd.metadata,
1222 0, &cmd.result, timeout);
84fef62d
KB		 1223 nvme_passthru_end(ctrl, effects);
1224
1673f1f0
CH		 1225 if (status >= 0) {
1226 if (put_user(cmd.result, &ucmd->result))
1227 return -EFAULT;
1228 }
1229
1230 return status;
1231}
1232
32acab31
CH		 1233/*
1234 * Issue ioctl requests on the first available path. Note that unlike normal
1235 * block layer requests we will not retry failed request on another controller.
1236 */
1237static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1238 struct nvme_ns_head **head, int *srcu_idx)
1673f1f0 1239{
32acab31
CH		 1240#ifdef CONFIG_NVME_MULTIPATH
1241 if (disk->fops == &nvme_ns_head_ops) {
1242 *head = disk->private_data;
1243 *srcu_idx = srcu_read_lock(&(*head)->srcu);
1244 return nvme_find_path(*head);
1245 }
1246#endif
1247 *head = NULL;
1248 *srcu_idx = -1;
1249 return disk->private_data;
1250}
1673f1f0 1251
32acab31
CH		 1252static void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1253{
1254 if (head)
1255 srcu_read_unlock(&head->srcu, idx);
1256}
1673f1f0 1257
32acab31
CH		 1258static int nvme_ns_ioctl(struct nvme_ns *ns, unsigned cmd, unsigned long arg)
1259{
1673f1f0
CH		 1260 switch (cmd) {
1261 case NVME_IOCTL_ID:
1262 force_successful_syscall_return();
ed754e5d 1263 return ns->head->ns_id;
1673f1f0
CH		 1264 case NVME_IOCTL_ADMIN_CMD:
1265 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1266 case NVME_IOCTL_IO_CMD:
1267 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1268 case NVME_IOCTL_SUBMIT_IO:
1269 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1270 default:
84d4add7
MB		 1271#ifdef CONFIG_NVM
1272 if (ns->ndev)
1273 return nvme_nvm_ioctl(ns, cmd, arg);
1274#endif
a98e58e5 1275 if (is_sed_ioctl(cmd))
4f1244c8 1276 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1277 (void __user *) arg);
1673f1f0
CH		 1278 return -ENOTTY;
1279 }
1280}
1281
32acab31
CH		 1282static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1283 unsigned int cmd, unsigned long arg)
1673f1f0 1284{
32acab31
CH		 1285 struct nvme_ns_head *head = NULL;
1286 struct nvme_ns *ns;
1287 int srcu_idx, ret;
1288
1289 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1290 if (unlikely(!ns))
1291 ret = -EWOULDBLOCK;
1292 else
1293 ret = nvme_ns_ioctl(ns, cmd, arg);
1294 nvme_put_ns_from_disk(head, srcu_idx);
1295 return ret;
1673f1f0 1296}
1673f1f0
CH		 1297
1298static int nvme_open(struct block_device *bdev, fmode_t mode)
1299{
c6424a90
CH		 1300 struct nvme_ns *ns = bdev->bd_disk->private_data;
1301
32acab31
CH		 1302#ifdef CONFIG_NVME_MULTIPATH
1303 /* should never be called due to GENHD_FL_HIDDEN */
1304 if (WARN_ON_ONCE(ns->head->disk))
85088c4a 1305 goto fail;
32acab31 1306#endif
c6424a90 1307 if (!kref_get_unless_zero(&ns->kref))
85088c4a
NC		 1308 goto fail;
1309 if (!try_module_get(ns->ctrl->ops->module))
1310 goto fail_put_ns;
1311
c6424a90 1312 return 0;
85088c4a
NC		 1313
1314fail_put_ns:
1315 nvme_put_ns(ns);
1316fail:
1317 return -ENXIO;
1673f1f0
CH		 1318}
1319
1320static void nvme_release(struct gendisk *disk, fmode_t mode)
1321{
85088c4a
NC		 1322 struct nvme_ns *ns = disk->private_data;
1323
1324 module_put(ns->ctrl->ops->module);
1325 nvme_put_ns(ns);
1673f1f0
CH		 1326}
1327
1328static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1329{
1330 /* some standard values */
1331 geo->heads = 1 << 6;
1332 geo->sectors = 1 << 5;
1333 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1334 return 0;
1335}
1336
1337#ifdef CONFIG_BLK_DEV_INTEGRITY
39b7baa4 1338static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1339{
1340 struct blk_integrity integrity;
1341
fa9a89fc 1342 memset(&integrity, 0, sizeof(integrity));
39b7baa4 1343 switch (pi_type) {
1673f1f0
CH		 1344 case NVME_NS_DPS_PI_TYPE3:
1345 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1346 integrity.tag_size = sizeof(u16) + sizeof(u32);
1347 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1348 break;
1349 case NVME_NS_DPS_PI_TYPE1:
1350 case NVME_NS_DPS_PI_TYPE2:
1351 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1352 integrity.tag_size = sizeof(u16);
1353 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1354 break;
1355 default:
1356 integrity.profile = NULL;
1357 break;
1358 }
39b7baa4
CH		 1359 integrity.tuple_size = ms;
1360 blk_integrity_register(disk, &integrity);
1361 blk_queue_max_integrity_segments(disk->queue, 1);
1673f1f0
CH		 1362}
1363#else
39b7baa4 1364static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1365{
1366}
1367#endif /* CONFIG_BLK_DEV_INTEGRITY */
1368
6b8190d6
SB		 1369static void nvme_set_chunk_size(struct nvme_ns *ns)
1370{
1371 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1372 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1373}
1374
3831761e 1375static void nvme_config_discard(struct nvme_ns *ns)
1673f1f0 1376{
3831761e
JA		 1377 struct nvme_ctrl *ctrl = ns->ctrl;
1378 struct request_queue *queue = ns->queue;
30e5e929
CH		 1379 u32 size = queue_logical_block_size(queue);
1380
3831761e
JA		 1381 if (!(ctrl->oncs & NVME_CTRL_ONCS_DSM)) {
1382 blk_queue_flag_clear(QUEUE_FLAG_DISCARD, queue);
1383 return;
1384 }
1385
1386 if (ctrl->nr_streams && ns->sws && ns->sgs)
1387 size *= ns->sws * ns->sgs;
08095e70 1388
b35ba01e
CH		 1389 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1390 NVME_DSM_MAX_RANGES);
1391
b224f613 1392 queue->limits.discard_alignment = 0;
30e5e929 1393 queue->limits.discard_granularity = size;
f5d11840 1394
3831761e
JA		 1395 /* If discard is already enabled, don't reset queue limits */
1396 if (blk_queue_flag_test_and_set(QUEUE_FLAG_DISCARD, queue))
1397 return;
1398
30e5e929
CH		 1399 blk_queue_max_discard_sectors(queue, UINT_MAX);
1400 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
e850fd16
CH		 1401
1402 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1403 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1404}
1405
cdbff4f2 1406static void nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
002fab04 1407 struct nvme_id_ns *id, struct nvme_ns_ids *ids)
1673f1f0 1408{
002fab04
CH		 1409 memset(ids, 0, sizeof(*ids));
1410
cdbff4f2 1411 if (ctrl->vs >= NVME_VS(1, 1, 0))
002fab04 1412 memcpy(ids->eui64, id->eui64, sizeof(id->eui64));
cdbff4f2 1413 if (ctrl->vs >= NVME_VS(1, 2, 0))
002fab04 1414 memcpy(ids->nguid, id->nguid, sizeof(id->nguid));
cdbff4f2 1415 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1416 /* Don't treat error as fatal we potentially
1417 * already have a NGUID or EUI-64
1418 */
002fab04 1419 if (nvme_identify_ns_descs(ctrl, nsid, ids))
cdbff4f2 1420 dev_warn(ctrl->device,
3b22ba26
JT		 1421 "%s: Identify Descriptors failed\n", __func__);
1422 }
ac81bfa9
MB		 1423}
1424
ed754e5d
CH		 1425static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1426{
1427 return !uuid_is_null(&ids->uuid) ||
1428 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1429 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1430}
1431
002fab04
CH		 1432static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1433{
1434 return uuid_equal(&a->uuid, &b->uuid) &&
1435 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1436 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0;
1437}
1438
24b0b58c
CH		 1439static void nvme_update_disk_info(struct gendisk *disk,
1440 struct nvme_ns *ns, struct nvme_id_ns *id)
1441{
1442 sector_t capacity = le64_to_cpup(&id->nsze) << (ns->lba_shift - 9);
cee160fd 1443 unsigned short bs = 1 << ns->lba_shift;
24b0b58c
CH		 1444
1445 blk_mq_freeze_queue(disk->queue);
1446 blk_integrity_unregister(disk);
1447
cee160fd
JL		 1448 blk_queue_logical_block_size(disk->queue, bs);
1449 blk_queue_physical_block_size(disk->queue, bs);
1450 blk_queue_io_min(disk->queue, bs);
1451
24b0b58c
CH		 1452 if (ns->ms && !ns->ext &&
1453 (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1454 nvme_init_integrity(disk, ns->ms, ns->pi_type);
715ea9e0 1455 if (ns->ms && !nvme_ns_has_pi(ns) && !blk_get_integrity(disk))
24b0b58c 1456 capacity = 0;
24b0b58c 1457
3831761e
JA		 1458 set_capacity(disk, capacity);
1459 nvme_config_discard(ns);
24b0b58c
CH		 1460 blk_mq_unfreeze_queue(disk->queue);
1461}
1462
ac81bfa9
MB		 1463static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1464{
1465 struct nvme_ns *ns = disk->private_data;
1673f1f0
CH		 1466
1467 /*
1468 * If identify namespace failed, use default 512 byte block size so
1469 * block layer can use before failing read/write for 0 capacity.
1470 */
c81bfba9 1471 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1472 if (ns->lba_shift == 0)
1473 ns->lba_shift = 9;
6b8190d6 1474 ns->noiob = le16_to_cpu(id->noiob);
b5be3b39 1475 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
c97f414c 1476 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
b5be3b39
CH		 1477 /* the PI implementation requires metadata equal t10 pi tuple size */
1478 if (ns->ms == sizeof(struct t10_pi_tuple))
1479 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1480 else
1481 ns->pi_type = 0;
1673f1f0 1482
6b8190d6
SB		 1483 if (ns->noiob)
1484 nvme_set_chunk_size(ns);
24b0b58c 1485 nvme_update_disk_info(disk, ns, id);
96257a8a
MB		 1486 if (ns->ndev)
1487 nvme_nvm_update_nvm_info(ns);
32acab31
CH		 1488#ifdef CONFIG_NVME_MULTIPATH
1489 if (ns->head->disk)
1490 nvme_update_disk_info(ns->head->disk, ns, id);
1491#endif
ac81bfa9 1492}
1673f1f0 1493
ac81bfa9
MB		 1494static int nvme_revalidate_disk(struct gendisk *disk)
1495{
1496 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1497 struct nvme_ctrl *ctrl = ns->ctrl;
1498 struct nvme_id_ns *id;
002fab04 1499 struct nvme_ns_ids ids;
cdbff4f2 1500 int ret = 0;
ac81bfa9
MB		 1501
1502 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1503 set_capacity(disk, 0);
1504 return -ENODEV;
1505 }
1506
ed754e5d 1507 id = nvme_identify_ns(ctrl, ns->head->ns_id);
cdbff4f2
CH		 1508 if (!id)
1509 return -ENODEV;
ac81bfa9 1510
cdbff4f2
CH		 1511 if (id->ncap == 0) {
1512 ret = -ENODEV;
1513 goto out;
1514 }
ac81bfa9 1515
5e0fab57 1516 __nvme_revalidate_disk(disk, id);
ed754e5d
CH		 1517 nvme_report_ns_ids(ctrl, ns->head->ns_id, id, &ids);
1518 if (!nvme_ns_ids_equal(&ns->head->ids, &ids)) {
1d5df6af 1519 dev_err(ctrl->device,
ed754e5d 1520 "identifiers changed for nsid %d\n", ns->head->ns_id);
1d5df6af
CH		 1521 ret = -ENODEV;
1522 }
1523
cdbff4f2
CH		 1524out:
1525 kfree(id);
1526 return ret;
1673f1f0
CH		 1527}
1528
1529static char nvme_pr_type(enum pr_type type)
1530{
1531 switch (type) {
1532 case PR_WRITE_EXCLUSIVE:
1533 return 1;
1534 case PR_EXCLUSIVE_ACCESS:
1535 return 2;
1536 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1537 return 3;
1538 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1539 return 4;
1540 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1541 return 5;
1542 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1543 return 6;
1544 default:
1545 return 0;
1546 }
1547};
1548
1549static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1550 u64 key, u64 sa_key, u8 op)
1551{
32acab31
CH		 1552 struct nvme_ns_head *head = NULL;
1553 struct nvme_ns *ns;
1673f1f0 1554 struct nvme_command c;
32acab31 1555 int srcu_idx, ret;
1673f1f0
CH		 1556 u8 data[16] = { 0, };
1557
b0d61d58
KB		 1558 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1559 if (unlikely(!ns))
1560 return -EWOULDBLOCK;
1561
1673f1f0
CH		 1562 put_unaligned_le64(key, &data[0]);
1563 put_unaligned_le64(sa_key, &data[8]);
1564
1565 memset(&c, 0, sizeof(c));
1566 c.common.opcode = op;
b0d61d58 1567 c.common.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1568 c.common.cdw10[0] = cpu_to_le32(cdw10);
1569
b0d61d58 1570 ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
32acab31
CH		 1571 nvme_put_ns_from_disk(head, srcu_idx);
1572 return ret;
1673f1f0
CH		 1573}
1574
1575static int nvme_pr_register(struct block_device *bdev, u64 old,
1576 u64 new, unsigned flags)
1577{
1578 u32 cdw10;
1579
1580 if (flags & ~PR_FL_IGNORE_KEY)
1581 return -EOPNOTSUPP;
1582
1583 cdw10 = old ? 2 : 0;
1584 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1585 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1586 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1587}
1588
1589static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1590 enum pr_type type, unsigned flags)
1591{
1592 u32 cdw10;
1593
1594 if (flags & ~PR_FL_IGNORE_KEY)
1595 return -EOPNOTSUPP;
1596
1597 cdw10 = nvme_pr_type(type) << 8;
1598 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1599 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1600}
1601
1602static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1603 enum pr_type type, bool abort)
1604{
e9a9853c 1605 u32 cdw10 = nvme_pr_type(type) << 8 | (abort ? 2 : 1);
1673f1f0
CH		 1606 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1607}
1608
1609static int nvme_pr_clear(struct block_device *bdev, u64 key)
1610{
8c0b3915 1611 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1612 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1613}
1614
1615static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1616{
e9a9853c 1617 u32 cdw10 = nvme_pr_type(type) << 8 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1618 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1619}
1620
1621static const struct pr_ops nvme_pr_ops = {
1622 .pr_register = nvme_pr_register,
1623 .pr_reserve = nvme_pr_reserve,
1624 .pr_release = nvme_pr_release,
1625 .pr_preempt = nvme_pr_preempt,
1626 .pr_clear = nvme_pr_clear,
1627};
1628
a98e58e5 1629#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1630int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1631 bool send)
a98e58e5 1632{
4f1244c8 1633 struct nvme_ctrl *ctrl = data;
a98e58e5 1634 struct nvme_command cmd;
a98e58e5
SB		 1635
1636 memset(&cmd, 0, sizeof(cmd));
1637 if (send)
1638 cmd.common.opcode = nvme_admin_security_send;
1639 else
1640 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1641 cmd.common.nsid = 0;
1642 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1643 cmd.common.cdw10[1] = cpu_to_le32(len);
1644
1645 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1646 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1647}
1648EXPORT_SYMBOL_GPL(nvme_sec_submit);
1649#endif /* CONFIG_BLK_SED_OPAL */
1650
5bae7f73 1651static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1652 .owner = THIS_MODULE,
1653 .ioctl = nvme_ioctl,
761f2e1e 1654 .compat_ioctl = nvme_ioctl,
1673f1f0
CH		 1655 .open = nvme_open,
1656 .release = nvme_release,
1657 .getgeo = nvme_getgeo,
1658 .revalidate_disk= nvme_revalidate_disk,
1659 .pr_ops = &nvme_pr_ops,
1660};
1661
32acab31
CH		 1662#ifdef CONFIG_NVME_MULTIPATH
1663static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
1664{
1665 struct nvme_ns_head *head = bdev->bd_disk->private_data;
1666
1667 if (!kref_get_unless_zero(&head->ref))
1668 return -ENXIO;
1669 return 0;
1670}
1671
1672static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
1673{
1674 nvme_put_ns_head(disk->private_data);
1675}
1676
1677const struct block_device_operations nvme_ns_head_ops = {
1678 .owner = THIS_MODULE,
1679 .open = nvme_ns_head_open,
1680 .release = nvme_ns_head_release,
1681 .ioctl = nvme_ioctl,
1682 .compat_ioctl = nvme_ioctl,
1683 .getgeo = nvme_getgeo,
1684 .pr_ops = &nvme_pr_ops,
1685};
1686#endif /* CONFIG_NVME_MULTIPATH */
1687
5fd4ce1b
CH		 1688static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1689{
1690 unsigned long timeout =
1691 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1692 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1693 int ret;
1694
1695 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1696 if (csts == ~0)
1697 return -ENODEV;
5fd4ce1b
CH		 1698 if ((csts & NVME_CSTS_RDY) == bit)
1699 break;
1700
1701 msleep(100);
1702 if (fatal_signal_pending(current))
1703 return -EINTR;
1704 if (time_after(jiffies, timeout)) {
1b3c47c1 1705 dev_err(ctrl->device,
5fd4ce1b
CH		 1706 "Device not ready; aborting %s\n", enabled ?
1707 "initialisation" : "reset");
1708 return -ENODEV;
1709 }
1710 }
1711
1712 return ret;
1713}
1714
1715/*
1716 * If the device has been passed off to us in an enabled state, just clear
1717 * the enabled bit. The spec says we should set the 'shutdown notification
1718 * bits', but doing so may cause the device to complete commands to the
1719 * admin queue ... and we don't know what memory that might be pointing at!
1720 */
1721int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1722{
1723 int ret;
1724
1725 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1726 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1727
1728 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1729 if (ret)
1730 return ret;
54adc010 1731
b5a10c5f 1732 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1733 msleep(NVME_QUIRK_DELAY_AMOUNT);
1734
5fd4ce1b
CH		 1735 return nvme_wait_ready(ctrl, cap, false);
1736}
576d55d6 1737EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1738
1739int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1740{
1741 /*
1742 * Default to a 4K page size, with the intention to update this
1743 * path in the future to accomodate architectures with differing
1744 * kernel and IO page sizes.
1745 */
1746 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1747 int ret;
1748
1749 if (page_shift < dev_page_min) {
1b3c47c1 1750 dev_err(ctrl->device,
5fd4ce1b
CH		 1751 "Minimum device page size %u too large for host (%u)\n",
1752 1 << dev_page_min, 1 << page_shift);
1753 return -ENODEV;
1754 }
1755
1756 ctrl->page_size = 1 << page_shift;
1757
1758 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1759 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 1760 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 1761 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1762 ctrl->ctrl_config |= NVME_CC_ENABLE;
1763
1764 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1765 if (ret)
1766 return ret;
1767 return nvme_wait_ready(ctrl, cap, true);
1768}
576d55d6 1769EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1770
1771int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1772{
07fbd32a 1773 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 1774 u32 csts;
1775 int ret;
1776
1777 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1778 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1779
1780 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1781 if (ret)
1782 return ret;
1783
1784 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1785 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1786 break;
1787
1788 msleep(100);
1789 if (fatal_signal_pending(current))
1790 return -EINTR;
1791 if (time_after(jiffies, timeout)) {
1b3c47c1 1792 dev_err(ctrl->device,
5fd4ce1b
CH		 1793 "Device shutdown incomplete; abort shutdown\n");
1794 return -ENODEV;
1795 }
1796 }
1797
1798 return ret;
1799}
576d55d6 1800EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1801
da35825d
CH		 1802static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1803 struct request_queue *q)
1804{
7c88cb00
JA		 1805 bool vwc = false;
1806
da35825d 1807 if (ctrl->max_hw_sectors) {
45686b61
CH		 1808 u32 max_segments =
1809 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1810
da35825d 1811 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1812 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1813 }
249159c5
KB		 1814 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
1815 is_power_of_2(ctrl->max_hw_sectors))
e6282aef 1816 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1817 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1818 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1819 vwc = true;
1820 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1821}
1822
dbf86b39
JD		 1823static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1824{
1825 __le64 ts;
1826 int ret;
1827
1828 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1829 return 0;
1830
1831 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1832 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
1833 NULL);
1834 if (ret)
1835 dev_warn_once(ctrl->device,
1836 "could not set timestamp (%d)\n", ret);
1837 return ret;
1838}
1839
634b8325 1840static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 1841{
1842 /*
1843 * APST (Autonomous Power State Transition) lets us program a
1844 * table of power state transitions that the controller will
1845 * perform automatically. We configure it with a simple
1846 * heuristic: we are willing to spend at most 2% of the time
1847 * transitioning between power states. Therefore, when running
1848 * in any given state, we will enter the next lower-power
76e4ad09 1849 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 1850 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 1851 * the requested maximum latency.
1852 *
1853 * We will not autonomously enter any non-operational state for
1854 * which the total latency exceeds ps_max_latency_us. Users
1855 * can set ps_max_latency_us to zero to turn off APST.
1856 */
1857
1858 unsigned apste;
1859 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1860 u64 max_lat_us = 0;
1861 int max_ps = -1;
c5552fde
AL		 1862 int ret;
1863
1864 /*
1865 * If APST isn't supported or if we haven't been initialized yet,
1866 * then don't do anything.
1867 */
1868 if (!ctrl->apsta)
634b8325 1869 return 0;
c5552fde
AL		 1870
1871 if (ctrl->npss > 31) {
1872 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 1873 return 0;
c5552fde
AL		 1874 }
1875
1876 table = kzalloc(sizeof(*table), GFP_KERNEL);
1877 if (!table)
634b8325 1878 return 0;
c5552fde 1879
76a5af84 1880 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 1881 /* Turn off APST. */
1882 apste = 0;
fb0dc399 1883 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 1884 } else {
1885 __le64 target = cpu_to_le64(0);
1886 int state;
1887
1888 /*
1889 * Walk through all states from lowest- to highest-power.
1890 * According to the spec, lower-numbered states use more
1891 * power. NPSS, despite the name, is the index of the
1892 * lowest-power state, not the number of states.
1893 */
1894 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 1895 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 1896
1897 if (target)
1898 table->entries[state] = target;
1899
ff5350a8
AL		 1900 /*
1901 * Don't allow transitions to the deepest state
1902 * if it's quirked off.
1903 */
1904 if (state == ctrl->npss &&
1905 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1906 continue;
1907
c5552fde
AL		 1908 /*
1909 * Is this state a useful non-operational state for
1910 * higher-power states to autonomously transition to?
1911 */
1912 if (!(ctrl->psd[state].flags &
1913 NVME_PS_FLAGS_NON_OP_STATE))
1914 continue;
1915
da87591b
KHF		 1916 exit_latency_us =
1917 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
1918 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 1919 continue;
1920
da87591b
KHF		 1921 total_latency_us =
1922 exit_latency_us +
1923 le32_to_cpu(ctrl->psd[state].entry_lat);
1924
c5552fde
AL		 1925 /*
1926 * This state is good. Use it as the APST idle
1927 * target for higher power states.
1928 */
1929 transition_ms = total_latency_us + 19;
1930 do_div(transition_ms, 20);
1931 if (transition_ms > (1 << 24) - 1)
1932 transition_ms = (1 << 24) - 1;
1933
1934 target = cpu_to_le64((state << 3) |
1935 (transition_ms << 8));
fb0dc399
AL		 1936
1937 if (max_ps == -1)
1938 max_ps = state;
1939
1940 if (total_latency_us > max_lat_us)
1941 max_lat_us = total_latency_us;
c5552fde
AL		 1942 }
1943
1944 apste = 1;
fb0dc399
AL		 1945
1946 if (max_ps == -1) {
1947 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1948 } else {
1949 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1950 max_ps, max_lat_us, (int)sizeof(*table), table);
1951 }
c5552fde
AL		 1952 }
1953
1954 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1955 table, sizeof(*table), NULL);
1956 if (ret)
1957 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1958
1959 kfree(table);
634b8325 1960 return ret;
c5552fde
AL		 1961}
1962
1963static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1964{
1965 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1966 u64 latency;
1967
1968 switch (val) {
1969 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1970 case PM_QOS_LATENCY_ANY:
1971 latency = U64_MAX;
1972 break;
1973
1974 default:
1975 latency = val;
1976 }
1977
1978 if (ctrl->ps_max_latency_us != latency) {
1979 ctrl->ps_max_latency_us = latency;
1980 nvme_configure_apst(ctrl);
1981 }
1982}
1983
bd4da3ab
AL		 1984struct nvme_core_quirk_entry {
1985 /*
1986 * NVMe model and firmware strings are padded with spaces. For
1987 * simplicity, strings in the quirk table are padded with NULLs
1988 * instead.
1989 */
1990 u16 vid;
1991 const char *mn;
1992 const char *fr;
1993 unsigned long quirks;
1994};
1995
1996static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1997 {
be56945c
AL		 1998 /*
1999 * This Toshiba device seems to die using any APST states. See:
2000 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2001 */
2002 .vid = 0x1179,
2003 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2004 .quirks = NVME_QUIRK_NO_APST,
be56945c 2005 }
bd4da3ab
AL		 2006};
2007
2008/* match is null-terminated but idstr is space-padded. */
2009static bool string_matches(const char *idstr, const char *match, size_t len)
2010{
2011 size_t matchlen;
2012
2013 if (!match)
2014 return true;
2015
2016 matchlen = strlen(match);
2017 WARN_ON_ONCE(matchlen > len);
2018
2019 if (memcmp(idstr, match, matchlen))
2020 return false;
2021
2022 for (; matchlen < len; matchlen++)
2023 if (idstr[matchlen] != ' ')
2024 return false;
2025
2026 return true;
2027}
2028
2029static bool quirk_matches(const struct nvme_id_ctrl *id,
2030 const struct nvme_core_quirk_entry *q)
2031{
2032 return q->vid == le16_to_cpu(id->vid) &&
2033 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2034 string_matches(id->fr, q->fr, sizeof(id->fr));
2035}
2036
ab9e00cc
CH		 2037static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2038 struct nvme_id_ctrl *id)
180de007
CH		 2039{
2040 size_t nqnlen;
2041 int off;
2042
2043 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2044 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
ab9e00cc 2045 strncpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
180de007
CH		 2046 return;
2047 }
2048
2049 if (ctrl->vs >= NVME_VS(1, 2, 1))
2050 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2051
2052 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 2053 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
180de007
CH		 2054 "nqn.2014.08.org.nvmexpress:%4x%4x",
2055 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2056 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2057 off += sizeof(id->sn);
ab9e00cc 2058 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2059 off += sizeof(id->mn);
ab9e00cc
CH		 2060 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2061}
2062
2063static void __nvme_release_subsystem(struct nvme_subsystem *subsys)
2064{
2065 ida_simple_remove(&nvme_subsystems_ida, subsys->instance);
2066 kfree(subsys);
2067}
2068
2069static void nvme_release_subsystem(struct device *dev)
2070{
2071 __nvme_release_subsystem(container_of(dev, struct nvme_subsystem, dev));
2072}
2073
2074static void nvme_destroy_subsystem(struct kref *ref)
2075{
2076 struct nvme_subsystem *subsys =
2077 container_of(ref, struct nvme_subsystem, ref);
2078
2079 mutex_lock(&nvme_subsystems_lock);
2080 list_del(&subsys->entry);
2081 mutex_unlock(&nvme_subsystems_lock);
2082
ed754e5d 2083 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2084 device_del(&subsys->dev);
2085 put_device(&subsys->dev);
2086}
2087
2088static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2089{
2090 kref_put(&subsys->ref, nvme_destroy_subsystem);
2091}
2092
2093static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2094{
2095 struct nvme_subsystem *subsys;
2096
2097 lockdep_assert_held(&nvme_subsystems_lock);
2098
2099 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2100 if (strcmp(subsys->subnqn, subsysnqn))
2101 continue;
2102 if (!kref_get_unless_zero(&subsys->ref))
2103 continue;
2104 return subsys;
2105 }
2106
2107 return NULL;
2108}
2109
1e496938
HR		 2110#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2111 struct device_attribute subsys_attr_##_name = \
2112 __ATTR(_name, _mode, _show, NULL)
2113
2114static ssize_t nvme_subsys_show_nqn(struct device *dev,
2115 struct device_attribute *attr,
2116 char *buf)
2117{
2118 struct nvme_subsystem *subsys =
2119 container_of(dev, struct nvme_subsystem, dev);
2120
2121 return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2122}
2123static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2124
2125#define nvme_subsys_show_str_function(field) \
2126static ssize_t subsys_##field##_show(struct device *dev, \
2127 struct device_attribute *attr, char *buf) \
2128{ \
2129 struct nvme_subsystem *subsys = \
2130 container_of(dev, struct nvme_subsystem, dev); \
2131 return sprintf(buf, "%.*s\n", \
2132 (int)sizeof(subsys->field), subsys->field); \
2133} \
2134static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2135
2136nvme_subsys_show_str_function(model);
2137nvme_subsys_show_str_function(serial);
2138nvme_subsys_show_str_function(firmware_rev);
2139
2140static struct attribute *nvme_subsys_attrs[] = {
2141 &subsys_attr_model.attr,
2142 &subsys_attr_serial.attr,
2143 &subsys_attr_firmware_rev.attr,
2144 &subsys_attr_subsysnqn.attr,
2145 NULL,
2146};
2147
2148static struct attribute_group nvme_subsys_attrs_group = {
2149 .attrs = nvme_subsys_attrs,
2150};
2151
2152static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2153 &nvme_subsys_attrs_group,
2154 NULL,
2155};
2156
b837b283
IR		 2157static int nvme_active_ctrls(struct nvme_subsystem *subsys)
2158{
2159 int count = 0;
2160 struct nvme_ctrl *ctrl;
2161
2162 mutex_lock(&subsys->lock);
2163 list_for_each_entry(ctrl, &subsys->ctrls, subsys_entry) {
2164 if (ctrl->state != NVME_CTRL_DELETING &&
2165 ctrl->state != NVME_CTRL_DEAD)
2166 count++;
2167 }
2168 mutex_unlock(&subsys->lock);
2169
2170 return count;
2171}
2172
ab9e00cc
CH		 2173static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2174{
2175 struct nvme_subsystem *subsys, *found;
2176 int ret;
2177
2178 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2179 if (!subsys)
2180 return -ENOMEM;
2181 ret = ida_simple_get(&nvme_subsystems_ida, 0, 0, GFP_KERNEL);
2182 if (ret < 0) {
2183 kfree(subsys);
2184 return ret;
2185 }
2186 subsys->instance = ret;
2187 mutex_init(&subsys->lock);
2188 kref_init(&subsys->ref);
2189 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2190 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2191 nvme_init_subnqn(subsys, ctrl, id);
2192 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2193 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2194 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2195 subsys->vendor_id = le16_to_cpu(id->vid);
2196 subsys->cmic = id->cmic;
2197
2198 subsys->dev.class = nvme_subsys_class;
2199 subsys->dev.release = nvme_release_subsystem;
1e496938 2200 subsys->dev.groups = nvme_subsys_attrs_groups;
ab9e00cc
CH		 2201 dev_set_name(&subsys->dev, "nvme-subsys%d", subsys->instance);
2202 device_initialize(&subsys->dev);
2203
2204 mutex_lock(&nvme_subsystems_lock);
2205 found = __nvme_find_get_subsystem(subsys->subnqn);
2206 if (found) {
2207 /*
2208 * Verify that the subsystem actually supports multiple
2209 * controllers, else bail out.
2210 */
181303d0
HR		 2211 if (!ctrl->opts->discovery_nqn &&
2212 nvme_active_ctrls(found) && !(id->cmic & (1 << 1))) {
ab9e00cc
CH		 2213 dev_err(ctrl->device,
2214 "ignoring ctrl due to duplicate subnqn (%s).\n",
2215 found->subnqn);
2216 nvme_put_subsystem(found);
2217 ret = -EINVAL;
2218 goto out_unlock;
2219 }
2220
2221 __nvme_release_subsystem(subsys);
2222 subsys = found;
2223 } else {
2224 ret = device_add(&subsys->dev);
2225 if (ret) {
2226 dev_err(ctrl->device,
2227 "failed to register subsystem device.\n");
2228 goto out_unlock;
2229 }
ed754e5d 2230 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2231 list_add_tail(&subsys->entry, &nvme_subsystems);
2232 }
2233
2234 ctrl->subsys = subsys;
2235 mutex_unlock(&nvme_subsystems_lock);
2236
2237 if (sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2238 dev_name(ctrl->device))) {
2239 dev_err(ctrl->device,
2240 "failed to create sysfs link from subsystem.\n");
2241 /* the transport driver will eventually put the subsystem */
2242 return -EINVAL;
2243 }
2244
2245 mutex_lock(&subsys->lock);
2246 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
2247 mutex_unlock(&subsys->lock);
2248
2249 return 0;
2250
2251out_unlock:
2252 mutex_unlock(&nvme_subsystems_lock);
2253 put_device(&subsys->dev);
2254 return ret;
180de007
CH		 2255}
2256
d558fb51 2257int nvme_get_log_ext(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
a294c199 2258 u8 log_page, void *log,
7ec6074f 2259 size_t size, u64 offset)
c627c487
KB		 2260{
2261 struct nvme_command c = { };
70da6094
MB		 2262 unsigned long dwlen = size / 4 - 1;
2263
2264 c.get_log_page.opcode = nvme_admin_get_log_page;
2265
2266 if (ns)
2267 c.get_log_page.nsid = cpu_to_le32(ns->head->ns_id);
2268 else
2269 c.get_log_page.nsid = cpu_to_le32(NVME_NSID_ALL);
c627c487 2270
70da6094
MB		 2271 c.get_log_page.lid = log_page;
2272 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2273 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2274 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2275 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
c627c487
KB		 2276
2277 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2278}
2279
70da6094
MB		 2280static int nvme_get_log(struct nvme_ctrl *ctrl, u8 log_page, void *log,
2281 size_t size)
2282{
2283 return nvme_get_log_ext(ctrl, NULL, log_page, log, size, 0);
2284}
2285
84fef62d
KB		 2286static int nvme_get_effects_log(struct nvme_ctrl *ctrl)
2287{
2288 int ret;
2289
2290 if (!ctrl->effects)
2291 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
2292
2293 if (!ctrl->effects)
2294 return 0;
2295
2296 ret = nvme_get_log(ctrl, NVME_LOG_CMD_EFFECTS, ctrl->effects,
2297 sizeof(*ctrl->effects));
2298 if (ret) {
2299 kfree(ctrl->effects);
2300 ctrl->effects = NULL;
2301 }
2302 return ret;
180de007
CH		 2303}
2304
7fd8930f
CH		 2305/*
2306 * Initialize the cached copies of the Identify data and various controller
2307 * register in our nvme_ctrl structure. This should be called as soon as
2308 * the admin queue is fully up and running.
2309 */
2310int nvme_init_identify(struct nvme_ctrl *ctrl)
2311{
2312 struct nvme_id_ctrl *id;
2313 u64 cap;
2314 int ret, page_shift;
a229dbf6 2315 u32 max_hw_sectors;
76a5af84 2316 bool prev_apst_enabled;
7fd8930f 2317
f3ca80fc
CH		 2318 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2319 if (ret) {
1b3c47c1 2320 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 2321 return ret;
2322 }
2323
7fd8930f
CH		 2324 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
2325 if (ret) {
1b3c47c1 2326 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 2327 return ret;
2328 }
2329 page_shift = NVME_CAP_MPSMIN(cap) + 12;
2330
8ef2074d 2331 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 2332 ctrl->subsystem = NVME_CAP_NSSRC(cap);
2333
7fd8930f
CH		 2334 ret = nvme_identify_ctrl(ctrl, &id);
2335 if (ret) {
1b3c47c1 2336 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 2337 return -EIO;
2338 }
2339
84fef62d
KB		 2340 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
2341 ret = nvme_get_effects_log(ctrl);
2342 if (ret < 0)
75c8b19a 2343 goto out_free;
84fef62d 2344 }
180de007 2345
bd4da3ab 2346 if (!ctrl->identified) {
ab9e00cc
CH		 2347 int i;
2348
2349 ret = nvme_init_subsystem(ctrl, id);
2350 if (ret)
2351 goto out_free;
2352
bd4da3ab
AL		 2353 /*
2354 * Check for quirks. Quirk can depend on firmware version,
2355 * so, in principle, the set of quirks present can change
2356 * across a reset. As a possible future enhancement, we
2357 * could re-scan for quirks every time we reinitialize
2358 * the device, but we'd have to make sure that the driver
2359 * behaves intelligently if the quirks change.
2360 */
bd4da3ab
AL		 2361 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2362 if (quirk_matches(id, &core_quirks[i]))
2363 ctrl->quirks |= core_quirks[i].quirks;
2364 }
2365 }
2366
c35e30b4 2367 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2368 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 2369 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2370 }
2371
8a9ae523 2372 ctrl->oacs = le16_to_cpu(id->oacs);
7fd8930f 2373 ctrl->oncs = le16_to_cpup(&id->oncs);
c0561f82 2374 ctrl->oaes = le32_to_cpu(id->oaes);
6bf25d16 2375 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2376 ctrl->vwc = id->vwc;
931e1c22 2377 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f 2378 if (id->mdts)
a229dbf6 2379 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 2380 else
a229dbf6
CH		 2381 max_hw_sectors = UINT_MAX;
2382 ctrl->max_hw_sectors =
2383 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2384
da35825d 2385 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2386 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2387 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 2388
07fbd32a
MP		 2389 if (id->rtd3e) {
2390 /* us -> s */
2391 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
2392
2393 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2394 shutdown_timeout, 60);
2395
2396 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 2397 dev_info(ctrl->device,
07fbd32a
MP		 2398 "Shutdown timeout set to %u seconds\n",
2399 ctrl->shutdown_timeout);
2400 } else
2401 ctrl->shutdown_timeout = shutdown_timeout;
2402
c5552fde 2403 ctrl->npss = id->npss;
76a5af84
KHF		 2404 ctrl->apsta = id->apsta;
2405 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 2406 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2407 if (force_apst && id->apsta) {
f0425db0 2408 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2409 ctrl->apst_enabled = true;
c35e30b4 2410 } else {
76a5af84 2411 ctrl->apst_enabled = false;
c35e30b4
AL		 2412 }
2413 } else {
76a5af84 2414 ctrl->apst_enabled = id->apsta;
c35e30b4 2415 }
c5552fde
AL		 2416 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2417
d3d5b87d 2418 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 2419 ctrl->icdoff = le16_to_cpu(id->icdoff);
2420 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2421 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2422 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2423
2424 /*
2425 * In fabrics we need to verify the cntlid matches the
2426 * admin connect
2427 */
634b8325 2428 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 2429 ret = -EINVAL;
634b8325
KB		 2430 goto out_free;
2431 }
038bd4cb
SG		 2432
2433 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 2434 dev_err(ctrl->device,
038bd4cb
SG		 2435 "keep-alive support is mandatory for fabrics\n");
2436 ret = -EINVAL;
634b8325 2437 goto out_free;
038bd4cb 2438 }
07bfcd09
CH		 2439 } else {
2440 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 2441 ctrl->hmpre = le32_to_cpu(id->hmpre);
2442 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 2443 ctrl->hmminds = le32_to_cpu(id->hmminds);
2444 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2445 }
da35825d 2446
7fd8930f 2447 kfree(id);
bd4da3ab 2448
76a5af84 2449 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2450 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2451 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 2452 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2453
634b8325
KB		 2454 ret = nvme_configure_apst(ctrl);
2455 if (ret < 0)
2456 return ret;
dbf86b39
JD		 2457
2458 ret = nvme_configure_timestamp(ctrl);
2459 if (ret < 0)
2460 return ret;
634b8325
KB		 2461
2462 ret = nvme_configure_directives(ctrl);
2463 if (ret < 0)
2464 return ret;
c5552fde 2465
bd4da3ab 2466 ctrl->identified = true;
c5552fde 2467
634b8325
KB		 2468 return 0;
2469
2470out_free:
2471 kfree(id);
07bfcd09 2472 return ret;
7fd8930f 2473}
576d55d6 2474EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 2475
f3ca80fc 2476static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 2477{
a6a5149b
CH		 2478 struct nvme_ctrl *ctrl =
2479 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 2480
2b1b7e78
JW		 2481 switch (ctrl->state) {
2482 case NVME_CTRL_LIVE:
2483 case NVME_CTRL_ADMIN_ONLY:
2484 break;
2485 default:
a6a5149b 2486 return -EWOULDBLOCK;
2b1b7e78
JW		 2487 }
2488
a6a5149b 2489 file->private_data = ctrl;
f3ca80fc
CH		 2490 return 0;
2491}
2492
bfd89471
CH		 2493static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
2494{
2495 struct nvme_ns *ns;
2496 int ret;
2497
765cc031 2498 down_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2499 if (list_empty(&ctrl->namespaces)) {
2500 ret = -ENOTTY;
2501 goto out_unlock;
2502 }
2503
2504 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
2505 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 2506 dev_warn(ctrl->device,
bfd89471
CH		 2507 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
2508 ret = -EINVAL;
2509 goto out_unlock;
2510 }
2511
1b3c47c1 2512 dev_warn(ctrl->device,
bfd89471
CH		 2513 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
2514 kref_get(&ns->kref);
765cc031 2515 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2516
2517 ret = nvme_user_cmd(ctrl, ns, argp);
2518 nvme_put_ns(ns);
2519 return ret;
2520
2521out_unlock:
765cc031 2522 up_read(&ctrl->namespaces_rwsem);
bfd89471
CH		 2523 return ret;
2524}
2525
f3ca80fc
CH		 2526static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2527 unsigned long arg)
2528{
2529 struct nvme_ctrl *ctrl = file->private_data;
2530 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2531
2532 switch (cmd) {
2533 case NVME_IOCTL_ADMIN_CMD:
2534 return nvme_user_cmd(ctrl, NULL, argp);
2535 case NVME_IOCTL_IO_CMD:
bfd89471 2536 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2537 case NVME_IOCTL_RESET:
1b3c47c1 2538 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2539 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2540 case NVME_IOCTL_SUBSYS_RESET:
2541 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2542 case NVME_IOCTL_RESCAN:
2543 nvme_queue_scan(ctrl);
2544 return 0;
f3ca80fc
CH		 2545 default:
2546 return -ENOTTY;
2547 }
2548}
2549
2550static const struct file_operations nvme_dev_fops = {
2551 .owner = THIS_MODULE,
2552 .open = nvme_dev_open,
f3ca80fc
CH		 2553 .unlocked_ioctl = nvme_dev_ioctl,
2554 .compat_ioctl = nvme_dev_ioctl,
2555};
2556
2557static ssize_t nvme_sysfs_reset(struct device *dev,
2558 struct device_attribute *attr, const char *buf,
2559 size_t count)
2560{
2561 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2562 int ret;
2563
d86c4d8e 2564 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2565 if (ret < 0)
2566 return ret;
2567 return count;
1673f1f0 2568}
f3ca80fc 2569static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2570
9ec3bb2f
KB		 2571static ssize_t nvme_sysfs_rescan(struct device *dev,
2572 struct device_attribute *attr, const char *buf,
2573 size_t count)
2574{
2575 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2576
2577 nvme_queue_scan(ctrl);
2578 return count;
2579}
2580static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2581
5b85b826
CH		 2582static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
2583{
2584 struct gendisk *disk = dev_to_disk(dev);
2585
2586 if (disk->fops == &nvme_fops)
2587 return nvme_get_ns_from_dev(dev)->head;
2588 else
2589 return disk->private_data;
2590}
2591
118472ab 2592static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2593 char *buf)
118472ab 2594{
5b85b826
CH		 2595 struct nvme_ns_head *head = dev_to_ns_head(dev);
2596 struct nvme_ns_ids *ids = &head->ids;
2597 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH		 2598 int serial_len = sizeof(subsys->serial);
2599 int model_len = sizeof(subsys->model);
118472ab 2600
002fab04
CH		 2601 if (!uuid_is_null(&ids->uuid))
2602 return sprintf(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 2603
002fab04
CH		 2604 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2605 return sprintf(buf, "eui.%16phN\n", ids->nguid);
118472ab 2606
002fab04
CH		 2607 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2608 return sprintf(buf, "eui.%8phN\n", ids->eui64);
118472ab 2609
ab9e00cc
CH		 2610 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
2611 subsys->serial[serial_len - 1] == '\0'))
118472ab 2612 serial_len--;
ab9e00cc
CH		 2613 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
2614 subsys->model[model_len - 1] == '\0'))
118472ab
KB		 2615 model_len--;
2616
ab9e00cc
CH		 2617 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
2618 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 2619 head->ns_id);
118472ab 2620}
c828a892 2621static DEVICE_ATTR_RO(wwid);
118472ab 2622
d934f984 2623static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2624 char *buf)
d934f984 2625{
5b85b826 2626 return sprintf(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 2627}
c828a892 2628static DEVICE_ATTR_RO(nguid);
d934f984 2629
2b9b6e86 2630static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2631 char *buf)
2b9b6e86 2632{
5b85b826 2633 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT		 2634
2635 /* For backward compatibility expose the NGUID to userspace if
2636 * we have no UUID set
2637 */
002fab04 2638 if (uuid_is_null(&ids->uuid)) {
d934f984
JT		 2639 printk_ratelimited(KERN_WARNING
2640 "No UUID available providing old NGUID\n");
002fab04 2641 return sprintf(buf, "%pU\n", ids->nguid);
d934f984 2642 }
002fab04 2643 return sprintf(buf, "%pU\n", &ids->uuid);
2b9b6e86 2644}
c828a892 2645static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB		 2646
2647static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 2648 char *buf)
2b9b6e86 2649{
5b85b826 2650 return sprintf(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 2651}
c828a892 2652static DEVICE_ATTR_RO(eui);
2b9b6e86
KB		 2653
2654static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2655 char *buf)
2b9b6e86 2656{
5b85b826 2657 return sprintf(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 2658}
c828a892 2659static DEVICE_ATTR_RO(nsid);
2b9b6e86 2660
5b85b826 2661static struct attribute *nvme_ns_id_attrs[] = {
118472ab 2662 &dev_attr_wwid.attr,
2b9b6e86 2663 &dev_attr_uuid.attr,
d934f984 2664 &dev_attr_nguid.attr,
2b9b6e86
KB		 2665 &dev_attr_eui.attr,
2666 &dev_attr_nsid.attr,
2667 NULL,
2668};
2669
5b85b826 2670static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2671 struct attribute *a, int n)
2672{
2673 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 2674 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB		 2675
2676 if (a == &dev_attr_uuid.attr) {
a04b5de5 2677 if (uuid_is_null(&ids->uuid) &&
002fab04 2678 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT		 2679 return 0;
2680 }
2681 if (a == &dev_attr_nguid.attr) {
002fab04 2682 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB		 2683 return 0;
2684 }
2685 if (a == &dev_attr_eui.attr) {
002fab04 2686 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB		 2687 return 0;
2688 }
2689 return a->mode;
2690}
2691
5b85b826
CH		 2692const struct attribute_group nvme_ns_id_attr_group = {
2693 .attrs = nvme_ns_id_attrs,
2694 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB		 2695};
2696
931e1c22 2697#define nvme_show_str_function(field) \
779ff756
KB		 2698static ssize_t field##_show(struct device *dev, \
2699 struct device_attribute *attr, char *buf) \
2700{ \
2701 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
ab9e00cc
CH		 2702 return sprintf(buf, "%.*s\n", \
2703 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB		 2704} \
2705static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2706
ab9e00cc
CH		 2707nvme_show_str_function(model);
2708nvme_show_str_function(serial);
2709nvme_show_str_function(firmware_rev);
2710
931e1c22
ML		 2711#define nvme_show_int_function(field) \
2712static ssize_t field##_show(struct device *dev, \
2713 struct device_attribute *attr, char *buf) \
2714{ \
2715 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2716 return sprintf(buf, "%d\n", ctrl->field); \
2717} \
2718static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2719
931e1c22 2720nvme_show_int_function(cntlid);
779ff756 2721
1a353d85
ML		 2722static ssize_t nvme_sysfs_delete(struct device *dev,
2723 struct device_attribute *attr, const char *buf,
2724 size_t count)
2725{
2726 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2727
2728 if (device_remove_file_self(dev, attr))
c5017e85 2729 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML		 2730 return count;
2731}
2732static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2733
2734static ssize_t nvme_sysfs_show_transport(struct device *dev,
2735 struct device_attribute *attr,
2736 char *buf)
2737{
2738 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2739
2740 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2741}
2742static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2743
8432bdb2
SG		 2744static ssize_t nvme_sysfs_show_state(struct device *dev,
2745 struct device_attribute *attr,
2746 char *buf)
2747{
2748 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2749 static const char *const state_name[] = {
2750 [NVME_CTRL_NEW] = "new",
2751 [NVME_CTRL_LIVE] = "live",
2b1b7e78 2752 [NVME_CTRL_ADMIN_ONLY] = "only-admin",
8432bdb2 2753 [NVME_CTRL_RESETTING] = "resetting",
ad6a0a52 2754 [NVME_CTRL_CONNECTING] = "connecting",
8432bdb2
SG		 2755 [NVME_CTRL_DELETING] = "deleting",
2756 [NVME_CTRL_DEAD] = "dead",
2757 };
2758
2759 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2760 state_name[ctrl->state])
2761 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2762
2763 return sprintf(buf, "unknown state\n");
2764}
2765
2766static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2767
1a353d85
ML		 2768static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2769 struct device_attribute *attr,
2770 char *buf)
2771{
2772 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2773
ab9e00cc 2774 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML		 2775}
2776static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2777
2778static ssize_t nvme_sysfs_show_address(struct device *dev,
2779 struct device_attribute *attr,
2780 char *buf)
2781{
2782 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2783
2784 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2785}
2786static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2787
779ff756
KB		 2788static struct attribute *nvme_dev_attrs[] = {
2789 &dev_attr_reset_controller.attr,
9ec3bb2f 2790 &dev_attr_rescan_controller.attr,
779ff756
KB		 2791 &dev_attr_model.attr,
2792 &dev_attr_serial.attr,
2793 &dev_attr_firmware_rev.attr,
931e1c22 2794 &dev_attr_cntlid.attr,
1a353d85
ML		 2795 &dev_attr_delete_controller.attr,
2796 &dev_attr_transport.attr,
2797 &dev_attr_subsysnqn.attr,
2798 &dev_attr_address.attr,
8432bdb2 2799 &dev_attr_state.attr,
779ff756
KB		 2800 NULL
2801};
2802
1a353d85
ML		 2803static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
2804 struct attribute *a, int n)
2805{
2806 struct device *dev = container_of(kobj, struct device, kobj);
2807 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2808
49d3d50b
CH		 2809 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
2810 return 0;
2811 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
2812 return 0;
1a353d85
ML		 2813
2814 return a->mode;
2815}
2816
779ff756 2817static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 2818 .attrs = nvme_dev_attrs,
2819 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 2820};
2821
2822static const struct attribute_group *nvme_dev_attr_groups[] = {
2823 &nvme_dev_attrs_group,
2824 NULL,
2825};
2826
ed754e5d
CH		 2827static struct nvme_ns_head *__nvme_find_ns_head(struct nvme_subsystem *subsys,
2828 unsigned nsid)
2829{
2830 struct nvme_ns_head *h;
2831
2832 lockdep_assert_held(&subsys->lock);
2833
2834 list_for_each_entry(h, &subsys->nsheads, entry) {
2835 if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
2836 return h;
2837 }
2838
2839 return NULL;
2840}
2841
2842static int __nvme_check_ids(struct nvme_subsystem *subsys,
2843 struct nvme_ns_head *new)
2844{
2845 struct nvme_ns_head *h;
2846
2847 lockdep_assert_held(&subsys->lock);
2848
2849 list_for_each_entry(h, &subsys->nsheads, entry) {
2850 if (nvme_ns_ids_valid(&new->ids) &&
2079699c 2851 !list_empty(&h->list) &&
ed754e5d
CH		 2852 nvme_ns_ids_equal(&new->ids, &h->ids))
2853 return -EINVAL;
2854 }
2855
2856 return 0;
2857}
2858
2859static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
2860 unsigned nsid, struct nvme_id_ns *id)
2861{
2862 struct nvme_ns_head *head;
2863 int ret = -ENOMEM;
2864
2865 head = kzalloc(sizeof(*head), GFP_KERNEL);
2866 if (!head)
2867 goto out;
2868 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
2869 if (ret < 0)
2870 goto out_free_head;
2871 head->instance = ret;
2872 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 2873 ret = init_srcu_struct(&head->srcu);
2874 if (ret)
2875 goto out_ida_remove;
ed754e5d
CH		 2876 head->subsys = ctrl->subsys;
2877 head->ns_id = nsid;
2878 kref_init(&head->ref);
2879
2880 nvme_report_ns_ids(ctrl, nsid, id, &head->ids);
2881
2882 ret = __nvme_check_ids(ctrl->subsys, head);
2883 if (ret) {
2884 dev_err(ctrl->device,
2885 "duplicate IDs for nsid %d\n", nsid);
2886 goto out_cleanup_srcu;
2887 }
2888
32acab31
CH		 2889 ret = nvme_mpath_alloc_disk(ctrl, head);
2890 if (ret)
2891 goto out_cleanup_srcu;
2892
ed754e5d 2893 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 2894
2895 kref_get(&ctrl->subsys->ref);
2896
ed754e5d
CH		 2897 return head;
2898out_cleanup_srcu:
2899 cleanup_srcu_struct(&head->srcu);
fd92c77f 2900out_ida_remove:
ed754e5d
CH		 2901 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
2902out_free_head:
2903 kfree(head);
2904out:
2905 return ERR_PTR(ret);
2906}
2907
2908static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
9bd82b1a 2909 struct nvme_id_ns *id)
ed754e5d
CH		 2910{
2911 struct nvme_ctrl *ctrl = ns->ctrl;
2912 bool is_shared = id->nmic & (1 << 0);
2913 struct nvme_ns_head *head = NULL;
2914 int ret = 0;
2915
2916 mutex_lock(&ctrl->subsys->lock);
2917 if (is_shared)
2918 head = __nvme_find_ns_head(ctrl->subsys, nsid);
2919 if (!head) {
2920 head = nvme_alloc_ns_head(ctrl, nsid, id);
2921 if (IS_ERR(head)) {
2922 ret = PTR_ERR(head);
2923 goto out_unlock;
2924 }
ed754e5d
CH		 2925 } else {
2926 struct nvme_ns_ids ids;
2927
2928 nvme_report_ns_ids(ctrl, nsid, id, &ids);
2929 if (!nvme_ns_ids_equal(&head->ids, &ids)) {
2930 dev_err(ctrl->device,
2931 "IDs don't match for shared namespace %d\n",
2932 nsid);
2933 ret = -EINVAL;
2934 goto out_unlock;
2935 }
ed754e5d
CH		 2936 }
2937
2938 list_add_tail(&ns->siblings, &head->list);
2939 ns->head = head;
2940
2941out_unlock:
2942 mutex_unlock(&ctrl->subsys->lock);
2943 return ret;
2944}
2945
5bae7f73
CH		 2946static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2947{
2948 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2949 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2950
ed754e5d 2951 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH		 2952}
2953
32f0c4af 2954static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 2955{
32f0c4af 2956 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 2957
765cc031 2958 down_read(&ctrl->namespaces_rwsem);
5bae7f73 2959 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 2960 if (ns->head->ns_id == nsid) {
2dd41228
CH		 2961 if (!kref_get_unless_zero(&ns->kref))
2962 continue;
32f0c4af
KB		 2963 ret = ns;
2964 break;
2965 }
ed754e5d 2966 if (ns->head->ns_id > nsid)
5bae7f73
CH		 2967 break;
2968 }
765cc031 2969 up_read(&ctrl->namespaces_rwsem);
32f0c4af 2970 return ret;
5bae7f73
CH		 2971}
2972
f5d11840
JA		 2973static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
2974{
2975 struct streams_directive_params s;
2976 int ret;
2977
2978 if (!ctrl->nr_streams)
2979 return 0;
2980
ed754e5d 2981 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
f5d11840
JA		 2982 if (ret)
2983 return ret;
2984
2985 ns->sws = le32_to_cpu(s.sws);
2986 ns->sgs = le16_to_cpu(s.sgs);
2987
2988 if (ns->sws) {
2989 unsigned int bs = 1 << ns->lba_shift;
2990
2991 blk_queue_io_min(ns->queue, bs * ns->sws);
2992 if (ns->sgs)
2993 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
2994 }
2995
2996 return 0;
2997}
2998
5bae7f73
CH		 2999static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3000{
3001 struct nvme_ns *ns;
3002 struct gendisk *disk;
ac81bfa9
MB		 3003 struct nvme_id_ns *id;
3004 char disk_name[DISK_NAME_LEN];
32acab31 3005 int node = dev_to_node(ctrl->dev), flags = GENHD_FL_EXT_DEVT;
5bae7f73
CH		 3006
3007 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3008 if (!ns)
3009 return;
3010
3011 ns->queue = blk_mq_init_queue(ctrl->tagset);
3012 if (IS_ERR(ns->queue))
ed754e5d 3013 goto out_free_ns;
8b904b5b 3014 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
5bae7f73
CH		 3015 ns->queue->queuedata = ns;
3016 ns->ctrl = ctrl;
3017
5bae7f73 3018 kref_init(&ns->kref);
5bae7f73 3019 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 3020
3021 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 3022 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 3023
cdbff4f2
CH		 3024 id = nvme_identify_ns(ctrl, nsid);
3025 if (!id)
ac81bfa9
MB		 3026 goto out_free_queue;
3027
cdbff4f2
CH		 3028 if (id->ncap == 0)
3029 goto out_free_id;
3030
9bd82b1a 3031 if (nvme_init_ns_head(ns, nsid, id))
ed754e5d 3032 goto out_free_id;
654b4a4a 3033 nvme_setup_streams_ns(ctrl, ns);
a785dbcc 3034 nvme_set_disk_name(disk_name, ns, ctrl, &flags);
cdbff4f2 3035
608cc4b1
CH		 3036 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
3037 if (nvme_nvm_register(ns, disk_name, node)) {
3038 dev_warn(ctrl->device, "LightNVM init failure\n");
ed754e5d 3039 goto out_unlink_ns;
608cc4b1 3040 }
3dc87dd0 3041 }
ac81bfa9 3042
3dc87dd0
MB		 3043 disk = alloc_disk_node(0, node);
3044 if (!disk)
ed754e5d 3045 goto out_unlink_ns;
ac81bfa9 3046
3dc87dd0
MB		 3047 disk->fops = &nvme_fops;
3048 disk->private_data = ns;
3049 disk->queue = ns->queue;
32acab31 3050 disk->flags = flags;
3dc87dd0
MB		 3051 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
3052 ns->disk = disk;
3053
3054 __nvme_revalidate_disk(disk, id);
5bae7f73 3055
765cc031 3056 down_write(&ctrl->namespaces_rwsem);
32f0c4af 3057 list_add_tail(&ns->list, &ctrl->namespaces);
765cc031 3058 up_write(&ctrl->namespaces_rwsem);
32f0c4af 3059
d22524a4 3060 nvme_get_ctrl(ctrl);
ac81bfa9
MB		 3061
3062 kfree(id);
3063
0d52c756 3064 device_add_disk(ctrl->device, ns->disk);
2b9b6e86 3065 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
5b85b826 3066 &nvme_ns_id_attr_group))
2b9b6e86
KB		 3067 pr_warn("%s: failed to create sysfs group for identification\n",
3068 ns->disk->disk_name);
3dc87dd0
MB		 3069 if (ns->ndev && nvme_nvm_register_sysfs(ns))
3070 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
3071 ns->disk->disk_name);
32acab31 3072
9bd82b1a 3073 nvme_mpath_add_disk(ns->head);
b9e03857 3074 nvme_fault_inject_init(ns);
5bae7f73 3075 return;
ed754e5d
CH		 3076 out_unlink_ns:
3077 mutex_lock(&ctrl->subsys->lock);
3078 list_del_rcu(&ns->siblings);
3079 mutex_unlock(&ctrl->subsys->lock);
ac81bfa9
MB		 3080 out_free_id:
3081 kfree(id);
5bae7f73
CH		 3082 out_free_queue:
3083 blk_cleanup_queue(ns->queue);
3084 out_free_ns:
3085 kfree(ns);
3086}
3087
3088static void nvme_ns_remove(struct nvme_ns *ns)
3089{
646017a6
KB		 3090 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3091 return;
69d3b8ac 3092
b9e03857 3093 nvme_fault_inject_fini(ns);
b0b4e09c 3094 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
2b9b6e86 3095 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
5b85b826 3096 &nvme_ns_id_attr_group);
3dc87dd0
MB		 3097 if (ns->ndev)
3098 nvme_nvm_unregister_sysfs(ns);
5bae7f73 3099 del_gendisk(ns->disk);
5bae7f73 3100 blk_cleanup_queue(ns->queue);
bd9f5d65
ML		 3101 if (blk_get_integrity(ns->disk))
3102 blk_integrity_unregister(ns->disk);
5bae7f73 3103 }
32f0c4af 3104
ed754e5d 3105 mutex_lock(&ns->ctrl->subsys->lock);
32acab31 3106 nvme_mpath_clear_current_path(ns);
9941a862 3107 list_del_rcu(&ns->siblings);
ed754e5d
CH		 3108 mutex_unlock(&ns->ctrl->subsys->lock);
3109
765cc031 3110 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3111 list_del_init(&ns->list);
765cc031 3112 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3113
9941a862 3114 synchronize_srcu(&ns->head->srcu);
479a322f 3115 nvme_mpath_check_last_path(ns);
5bae7f73
CH		 3116 nvme_put_ns(ns);
3117}
3118
540c801c
KB		 3119static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3120{
3121 struct nvme_ns *ns;
3122
32f0c4af 3123 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 3124 if (ns) {
b0b4e09c 3125 if (ns->disk && revalidate_disk(ns->disk))
540c801c 3126 nvme_ns_remove(ns);
32f0c4af 3127 nvme_put_ns(ns);
540c801c
KB		 3128 } else
3129 nvme_alloc_ns(ctrl, nsid);
3130}
3131
47b0e50a
SB		 3132static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3133 unsigned nsid)
3134{
3135 struct nvme_ns *ns, *next;
6f8e0d78 3136 LIST_HEAD(rm_list);
47b0e50a 3137
765cc031 3138 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3139 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
ed754e5d 3140 if (ns->head->ns_id > nsid)
6f8e0d78 3141 list_move_tail(&ns->list, &rm_list);
47b0e50a 3142 }
765cc031 3143 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3144
3145 list_for_each_entry_safe(ns, next, &rm_list, list)
3146 nvme_ns_remove(ns);
3147
47b0e50a
SB		 3148}
3149
540c801c
KB		 3150static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
3151{
3152 struct nvme_ns *ns;
3153 __le32 *ns_list;
3154 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
3155 int ret = 0;
3156
42595eb7 3157 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3158 if (!ns_list)
3159 return -ENOMEM;
3160
3161 for (i = 0; i < num_lists; i++) {
3162 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
3163 if (ret)
47b0e50a 3164 goto free;
540c801c
KB		 3165
3166 for (j = 0; j < min(nn, 1024U); j++) {
3167 nsid = le32_to_cpu(ns_list[j]);
3168 if (!nsid)
3169 goto out;
3170
3171 nvme_validate_ns(ctrl, nsid);
3172
3173 while (++prev < nsid) {
32f0c4af
KB		 3174 ns = nvme_find_get_ns(ctrl, prev);
3175 if (ns) {
540c801c 3176 nvme_ns_remove(ns);
32f0c4af
KB		 3177 nvme_put_ns(ns);
3178 }
540c801c
KB		 3179 }
3180 }
3181 nn -= j;
3182 }
3183 out:
47b0e50a
SB		 3184 nvme_remove_invalid_namespaces(ctrl, prev);
3185 free:
540c801c
KB		 3186 kfree(ns_list);
3187 return ret;
3188}
3189
5955be21 3190static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 3191{
5bae7f73
CH		 3192 unsigned i;
3193
540c801c
KB		 3194 for (i = 1; i <= nn; i++)
3195 nvme_validate_ns(ctrl, i);
3196
47b0e50a 3197 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3198}
3199
30d90964
CH		 3200static bool nvme_scan_changed_ns_log(struct nvme_ctrl *ctrl)
3201{
3202 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
3203 __le32 *log;
3204 int error, i;
3205 bool ret = false;
3206
3207 log = kzalloc(log_size, GFP_KERNEL);
3208 if (!log)
3209 return false;
3210
3211 error = nvme_get_log(ctrl, NVME_LOG_CHANGED_NS, log, log_size);
3212 if (error) {
3213 dev_warn(ctrl->device,
3214 "reading changed ns log failed: %d\n", error);
3215 goto out_free_log;
3216 }
3217
3218 if (log[0] == cpu_to_le32(0xffffffff))
3219 goto out_free_log;
3220
3221 for (i = 0; i < NVME_MAX_CHANGED_NAMESPACES; i++) {
3222 u32 nsid = le32_to_cpu(log[i]);
3223
3224 if (nsid == 0)
3225 break;
3226 dev_info(ctrl->device, "rescanning namespace %d.\n", nsid);
3227 nvme_validate_ns(ctrl, nsid);
3228 }
3229 ret = true;
3230
3231out_free_log:
3232 kfree(log);
3233 return ret;
3234}
3235
5955be21 3236static void nvme_scan_work(struct work_struct *work)
5bae7f73 3237{
5955be21
CH		 3238 struct nvme_ctrl *ctrl =
3239 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 3240 struct nvme_id_ctrl *id;
540c801c 3241 unsigned nn;
5bae7f73 3242
5955be21
CH		 3243 if (ctrl->state != NVME_CTRL_LIVE)
3244 return;
3245
2b1b7e78
JW		 3246 WARN_ON_ONCE(!ctrl->tagset);
3247
77016199 3248 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964
CH		 3249 if (nvme_scan_changed_ns_log(ctrl))
3250 goto out_sort_namespaces;
3251 dev_info(ctrl->device, "rescanning namespaces.\n");
3252 }
3253
5bae7f73
CH		 3254 if (nvme_identify_ctrl(ctrl, &id))
3255 return;
540c801c
KB		 3256
3257 nn = le32_to_cpu(id->nn);
8ef2074d 3258 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 3259 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
3260 if (!nvme_scan_ns_list(ctrl, nn))
30d90964 3261 goto out_free_id;
540c801c 3262 }
5955be21 3263 nvme_scan_ns_sequential(ctrl, nn);
30d90964
CH		 3264out_free_id:
3265 kfree(id);
3266out_sort_namespaces:
765cc031 3267 down_write(&ctrl->namespaces_rwsem);
540c801c 3268 list_sort(NULL, &ctrl->namespaces, ns_cmp);
765cc031 3269 up_write(&ctrl->namespaces_rwsem);
5955be21 3270}
5bae7f73 3271
32f0c4af
KB		 3272/*
3273 * This function iterates the namespace list unlocked to allow recovery from
3274 * controller failure. It is up to the caller to ensure the namespace list is
3275 * not modified by scan work while this function is executing.
3276 */
5bae7f73
CH		 3277void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
3278{
3279 struct nvme_ns *ns, *next;
6f8e0d78 3280 LIST_HEAD(ns_list);
5bae7f73 3281
0ff9d4e1
KB		 3282 /*
3283 * The dead states indicates the controller was not gracefully
3284 * disconnected. In that case, we won't be able to flush any data while
3285 * removing the namespaces' disks; fail all the queues now to avoid
3286 * potentially having to clean up the failed sync later.
3287 */
3288 if (ctrl->state == NVME_CTRL_DEAD)
3289 nvme_kill_queues(ctrl);
3290
765cc031 3291 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 3292 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 3293 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3294
3295 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 3296 nvme_ns_remove(ns);
3297}
576d55d6 3298EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 3299
e3d7874d
KB		 3300static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
3301{
3302 char *envp[2] = { NULL, NULL };
3303 u32 aen_result = ctrl->aen_result;
3304
3305 ctrl->aen_result = 0;
3306 if (!aen_result)
3307 return;
3308
3309 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
3310 if (!envp[0])
3311 return;
3312 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
3313 kfree(envp[0]);
3314}
3315
f866fc42
CH		 3316static void nvme_async_event_work(struct work_struct *work)
3317{
3318 struct nvme_ctrl *ctrl =
3319 container_of(work, struct nvme_ctrl, async_event_work);
3320
e3d7874d 3321 nvme_aen_uevent(ctrl);
ad22c355 3322 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 3323}
3324
b6dccf7f
AD		 3325static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
3326{
3327
3328 u32 csts;
3329
3330 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
3331 return false;
3332
3333 if (csts == ~0)
3334 return false;
3335
3336 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
3337}
3338
3339static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
3340{
b6dccf7f
AD		 3341 struct nvme_fw_slot_info_log *log;
3342
3343 log = kmalloc(sizeof(*log), GFP_KERNEL);
3344 if (!log)
3345 return;
3346
c627c487 3347 if (nvme_get_log(ctrl, NVME_LOG_FW_SLOT, log, sizeof(*log)))
b6dccf7f
AD		 3348 dev_warn(ctrl->device,
3349 "Get FW SLOT INFO log error\n");
3350 kfree(log);
3351}
3352
3353static void nvme_fw_act_work(struct work_struct *work)
3354{
3355 struct nvme_ctrl *ctrl = container_of(work,
3356 struct nvme_ctrl, fw_act_work);
3357 unsigned long fw_act_timeout;
3358
3359 if (ctrl->mtfa)
3360 fw_act_timeout = jiffies +
3361 msecs_to_jiffies(ctrl->mtfa * 100);
3362 else
3363 fw_act_timeout = jiffies +
3364 msecs_to_jiffies(admin_timeout * 1000);
3365
3366 nvme_stop_queues(ctrl);
3367 while (nvme_ctrl_pp_status(ctrl)) {
3368 if (time_after(jiffies, fw_act_timeout)) {
3369 dev_warn(ctrl->device,
3370 "Fw activation timeout, reset controller\n");
3371 nvme_reset_ctrl(ctrl);
3372 break;
3373 }
3374 msleep(100);
3375 }
3376
3377 if (ctrl->state != NVME_CTRL_LIVE)
3378 return;
3379
3380 nvme_start_queues(ctrl);
a806c6c8 3381 /* read FW slot information to clear the AER */
b6dccf7f
AD		 3382 nvme_get_fw_slot_info(ctrl);
3383}
3384
868c2392
CH		 3385static void nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
3386{
3387 switch ((result & 0xff00) >> 8) {
3388 case NVME_AER_NOTICE_NS_CHANGED:
77016199 3389 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 3390 nvme_queue_scan(ctrl);
3391 break;
3392 case NVME_AER_NOTICE_FW_ACT_STARTING:
3393 queue_work(nvme_wq, &ctrl->fw_act_work);
3394 break;
3395 default:
3396 dev_warn(ctrl->device, "async event result %08x\n", result);
3397 }
3398}
3399
7bf58533 3400void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 3401 volatile union nvme_result *res)
f866fc42 3402{
7bf58533 3403 u32 result = le32_to_cpu(res->u32);
f866fc42 3404
ad22c355 3405 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 3406 return;
3407
e3d7874d 3408 switch (result & 0x7) {
868c2392
CH		 3409 case NVME_AER_NOTICE:
3410 nvme_handle_aen_notice(ctrl, result);
3411 break;
e3d7874d
KB		 3412 case NVME_AER_ERROR:
3413 case NVME_AER_SMART:
3414 case NVME_AER_CSS:
3415 case NVME_AER_VS:
3416 ctrl->aen_result = result;
7bf58533
CH		 3417 break;
3418 default:
3419 break;
f866fc42 3420 }
c669ccdc 3421 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 3422}
f866fc42 3423EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 3424
d09f2b45 3425void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 3426{
d09f2b45 3427 nvme_stop_keep_alive(ctrl);
f866fc42 3428 flush_work(&ctrl->async_event_work);
5955be21 3429 flush_work(&ctrl->scan_work);
b6dccf7f 3430 cancel_work_sync(&ctrl->fw_act_work);
b435ecea
NC		 3431 if (ctrl->ops->stop_ctrl)
3432 ctrl->ops->stop_ctrl(ctrl);
d09f2b45
SG		 3433}
3434EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
3435
3436void nvme_start_ctrl(struct nvme_ctrl *ctrl)
3437{
3438 if (ctrl->kato)
3439 nvme_start_keep_alive(ctrl);
3440
3441 if (ctrl->queue_count > 1) {
3442 nvme_queue_scan(ctrl);
c0561f82 3443 nvme_enable_aen(ctrl);
d99ca609 3444 queue_work(nvme_wq, &ctrl->async_event_work);
d09f2b45
SG		 3445 nvme_start_queues(ctrl);
3446 }
3447}
3448EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 3449
d09f2b45
SG		 3450void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
3451{
a6a5149b 3452 cdev_device_del(&ctrl->cdev, ctrl->device);
53029b04 3453}
576d55d6 3454EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 3455
d22524a4 3456static void nvme_free_ctrl(struct device *dev)
53029b04 3457{
d22524a4
CH		 3458 struct nvme_ctrl *ctrl =
3459 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 3460 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 3461
9843f685 3462 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
84fef62d 3463 kfree(ctrl->effects);
f3ca80fc 3464
ab9e00cc
CH		 3465 if (subsys) {
3466 mutex_lock(&subsys->lock);
3467 list_del(&ctrl->subsys_entry);
3468 mutex_unlock(&subsys->lock);
3469 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
3470 }
f3ca80fc
CH		 3471
3472 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 3473
ab9e00cc
CH		 3474 if (subsys)
3475 nvme_put_subsystem(subsys);
f3ca80fc
CH		 3476}
3477
3478/*
3479 * Initialize a NVMe controller structures. This needs to be called during
3480 * earliest initialization so that we have the initialized structured around
3481 * during probing.
3482 */
3483int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
3484 const struct nvme_ctrl_ops *ops, unsigned long quirks)
3485{
3486 int ret;
3487
bb8d261e
CH		 3488 ctrl->state = NVME_CTRL_NEW;
3489 spin_lock_init(&ctrl->lock);
f3ca80fc 3490 INIT_LIST_HEAD(&ctrl->namespaces);
765cc031 3491 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 3492 ctrl->dev = dev;
3493 ctrl->ops = ops;
3494 ctrl->quirks = quirks;
5955be21 3495 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 3496 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 3497 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 3498 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
f3ca80fc 3499
9843f685
CH		 3500 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
3501 if (ret < 0)
f3ca80fc 3502 goto out;
9843f685 3503 ctrl->instance = ret;
f3ca80fc 3504
d22524a4
CH		 3505 device_initialize(&ctrl->ctrl_device);
3506 ctrl->device = &ctrl->ctrl_device;
a6a5149b 3507 ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
d22524a4
CH		 3508 ctrl->device->class = nvme_class;
3509 ctrl->device->parent = ctrl->dev;
3510 ctrl->device->groups = nvme_dev_attr_groups;
3511 ctrl->device->release = nvme_free_ctrl;
3512 dev_set_drvdata(ctrl->device, ctrl);
3513 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
3514 if (ret)
f3ca80fc 3515 goto out_release_instance;
f3ca80fc 3516
a6a5149b
CH		 3517 cdev_init(&ctrl->cdev, &nvme_dev_fops);
3518 ctrl->cdev.owner = ops->module;
3519 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 3520 if (ret)
3521 goto out_free_name;
f3ca80fc 3522
c5552fde
AL		 3523 /*
3524 * Initialize latency tolerance controls. The sysfs files won't
3525 * be visible to userspace unless the device actually supports APST.
3526 */
3527 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
3528 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
3529 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
3530
f3ca80fc 3531 return 0;
d22524a4
CH		 3532out_free_name:
3533 kfree_const(dev->kobj.name);
f3ca80fc 3534out_release_instance:
9843f685 3535 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc
CH		 3536out:
3537 return ret;
3538}
576d55d6 3539EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 3540
69d9a99c
KB		 3541/**
3542 * nvme_kill_queues(): Ends all namespace queues
3543 * @ctrl: the dead controller that needs to end
3544 *
3545 * Call this function when the driver determines it is unable to get the
3546 * controller in a state capable of servicing IO.
3547 */
3548void nvme_kill_queues(struct nvme_ctrl *ctrl)
3549{
3550 struct nvme_ns *ns;
3551
765cc031 3552 down_read(&ctrl->namespaces_rwsem);
82654b6b 3553
443bd90f 3554 /* Forcibly unquiesce queues to avoid blocking dispatch */
7dd1ab16
SB		 3555 if (ctrl->admin_q)
3556 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 3557
32f0c4af 3558 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 3559 /*
3560 * Revalidating a dead namespace sets capacity to 0. This will
3561 * end buffered writers dirtying pages that can't be synced.
3562 */
f33447b9
KB		 3563 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
3564 continue;
3565 revalidate_disk(ns->disk);
69d9a99c 3566 blk_set_queue_dying(ns->queue);
806f026f 3567
443bd90f
ML		 3568 /* Forcibly unquiesce queues to avoid blocking dispatch */
3569 blk_mq_unquiesce_queue(ns->queue);
69d9a99c 3570 }
765cc031 3571 up_read(&ctrl->namespaces_rwsem);
69d9a99c 3572}
237045fc 3573EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 3574
302ad8cc
KB		 3575void nvme_unfreeze(struct nvme_ctrl *ctrl)
3576{
3577 struct nvme_ns *ns;
3578
765cc031 3579 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3580 list_for_each_entry(ns, &ctrl->namespaces, list)
3581 blk_mq_unfreeze_queue(ns->queue);
765cc031 3582 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3583}
3584EXPORT_SYMBOL_GPL(nvme_unfreeze);
3585
3586void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
3587{
3588 struct nvme_ns *ns;
3589
765cc031 3590 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3591 list_for_each_entry(ns, &ctrl->namespaces, list) {
3592 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
3593 if (timeout <= 0)
3594 break;
3595 }
765cc031 3596 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3597}
3598EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
3599
3600void nvme_wait_freeze(struct nvme_ctrl *ctrl)
3601{
3602 struct nvme_ns *ns;
3603
765cc031 3604 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3605 list_for_each_entry(ns, &ctrl->namespaces, list)
3606 blk_mq_freeze_queue_wait(ns->queue);
765cc031 3607 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3608}
3609EXPORT_SYMBOL_GPL(nvme_wait_freeze);
3610
3611void nvme_start_freeze(struct nvme_ctrl *ctrl)
3612{
3613 struct nvme_ns *ns;
3614
765cc031 3615 down_read(&ctrl->namespaces_rwsem);
302ad8cc 3616 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 3617 blk_freeze_queue_start(ns->queue);
765cc031 3618 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 3619}
3620EXPORT_SYMBOL_GPL(nvme_start_freeze);
3621
25646264 3622void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3623{
3624 struct nvme_ns *ns;
3625
765cc031 3626 down_read(&ctrl->namespaces_rwsem);
a6eaa884 3627 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 3628 blk_mq_quiesce_queue(ns->queue);
765cc031 3629 up_read(&ctrl->namespaces_rwsem);
363c9aac 3630}
576d55d6 3631EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 3632
25646264 3633void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3634{
3635 struct nvme_ns *ns;
3636
765cc031 3637 down_read(&ctrl->namespaces_rwsem);
8d7b8faf 3638 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 3639 blk_mq_unquiesce_queue(ns->queue);
765cc031 3640 up_read(&ctrl->namespaces_rwsem);
363c9aac 3641}
576d55d6 3642EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 3643
31b84460
SG		 3644int nvme_reinit_tagset(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set)
3645{
3646 if (!ctrl->ops->reinit_request)
3647 return 0;
3648
3649 return blk_mq_tagset_iter(set, set->driver_data,
3650 ctrl->ops->reinit_request);
3651}
3652EXPORT_SYMBOL_GPL(nvme_reinit_tagset);
3653
5bae7f73
CH		 3654int __init nvme_core_init(void)
3655{
b227c59b 3656 int result = -ENOMEM;
5bae7f73 3657
9a6327d2
SG		 3658 nvme_wq = alloc_workqueue("nvme-wq",
3659 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3660 if (!nvme_wq)
b227c59b
RS		 3661 goto out;
3662
3663 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
3664 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3665 if (!nvme_reset_wq)
3666 goto destroy_wq;
3667
3668 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
3669 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3670 if (!nvme_delete_wq)
3671 goto destroy_reset_wq;
9a6327d2 3672
a6a5149b 3673 result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
f3ca80fc 3674 if (result < 0)
b227c59b 3675 goto destroy_delete_wq;
f3ca80fc
CH		 3676
3677 nvme_class = class_create(THIS_MODULE, "nvme");
3678 if (IS_ERR(nvme_class)) {
3679 result = PTR_ERR(nvme_class);
3680 goto unregister_chrdev;
3681 }
3682
ab9e00cc
CH		 3683 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
3684 if (IS_ERR(nvme_subsys_class)) {
3685 result = PTR_ERR(nvme_subsys_class);
3686 goto destroy_class;
3687 }
5bae7f73 3688 return 0;
f3ca80fc 3689
ab9e00cc
CH		 3690destroy_class:
3691 class_destroy(nvme_class);
9a6327d2 3692unregister_chrdev:
a6a5149b 3693 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3694destroy_delete_wq:
3695 destroy_workqueue(nvme_delete_wq);
3696destroy_reset_wq:
3697 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 3698destroy_wq:
3699 destroy_workqueue(nvme_wq);
b227c59b 3700out:
f3ca80fc 3701 return result;
5bae7f73
CH		 3702}
3703
3704void nvme_core_exit(void)
3705{
ab9e00cc
CH		 3706 ida_destroy(&nvme_subsystems_ida);
3707 class_destroy(nvme_subsys_class);
f3ca80fc 3708 class_destroy(nvme_class);
a6a5149b 3709 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
b227c59b
RS		 3710 destroy_workqueue(nvme_delete_wq);
3711 destroy_workqueue(nvme_reset_wq);
9a6327d2 3712 destroy_workqueue(nvme_wq);
5bae7f73 3713}
576d55d6
ML		 3714
3715MODULE_LICENSE("GPL");
3716MODULE_VERSION("1.0");
3717module_init(nvme_core_init);
3718module_exit(nvme_core_exit);
Linux 6.x block layer and io_uring tree(s)