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nvme: cleanup nvme_configure_metadata
[linux-2.6-block.git] / drivers / nvme / host / core.c
CommitLineData
bc50ad75 1// SPDX-License-Identifier: GPL-2.0
21d34711
CH		 2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
21d34711
CH		 5 */
6
7#include <linux/blkdev.h>
8#include <linux/blk-mq.h>
fe45e630 9#include <linux/blk-integrity.h>
c95b708d 10#include <linux/compat.h>
5fd4ce1b 11#include <linux/delay.h>
21d34711 12#include <linux/errno.h>
1673f1f0 13#include <linux/hdreg.h>
21d34711 14#include <linux/kernel.h>
5bae7f73 15#include <linux/module.h>
958f2a0f 16#include <linux/backing-dev.h>
21d34711
CH		 17#include <linux/slab.h>
18#include <linux/types.h>
1673f1f0
CH		 19#include <linux/pr.h>
20#include <linux/ptrace.h>
21#include <linux/nvme_ioctl.h>
c5552fde 22#include <linux/pm_qos.h>
a1a825ab 23#include <linux/ratelimit.h>
1673f1f0 24#include <asm/unaligned.h>
21d34711
CH		 25
26#include "nvme.h"
038bd4cb 27#include "fabrics.h"
f50fff73 28#include <linux/nvme-auth.h>
21d34711 29
35fe0d12
HR		 30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
f3ca80fc
CH		 33#define NVME_MINORS (1U << MINORBITS)
34
1a893c2b
CH		 35struct nvme_ns_info {
36 struct nvme_ns_ids ids;
37 u32 nsid;
38 __le32 anagrpid;
39 bool is_shared;
1e4ea66a 40 bool is_readonly;
1a893c2b 41 bool is_ready;
0dd6fff2 42 bool is_removed;
1a893c2b
CH		 43};
44
8ae4e447
MO		 45unsigned int admin_timeout = 60;
46module_param(admin_timeout, uint, 0644);
ba0ba7d3 47MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 48EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 49
8ae4e447
MO		 50unsigned int nvme_io_timeout = 30;
51module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 52MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 53EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 54
b3b1b0b0 55static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 56module_param(shutdown_timeout, byte, 0644);
57MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
58
44e44b29
CH		 59static u8 nvme_max_retries = 5;
60module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 61MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 62
9947d6a0 63static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 64module_param(default_ps_max_latency_us, ulong, 0644);
65MODULE_PARM_DESC(default_ps_max_latency_us,
66 "max power saving latency for new devices; use PM QOS to change per device");
67
c35e30b4
AL		 68static bool force_apst;
69module_param(force_apst, bool, 0644);
70MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
71
ebd8a93a
AB		 72static unsigned long apst_primary_timeout_ms = 100;
73module_param(apst_primary_timeout_ms, ulong, 0644);
74MODULE_PARM_DESC(apst_primary_timeout_ms,
75 "primary APST timeout in ms");
76
77static unsigned long apst_secondary_timeout_ms = 2000;
78module_param(apst_secondary_timeout_ms, ulong, 0644);
79MODULE_PARM_DESC(apst_secondary_timeout_ms,
80 "secondary APST timeout in ms");
81
82static unsigned long apst_primary_latency_tol_us = 15000;
83module_param(apst_primary_latency_tol_us, ulong, 0644);
84MODULE_PARM_DESC(apst_primary_latency_tol_us,
85 "primary APST latency tolerance in us");
86
87static unsigned long apst_secondary_latency_tol_us = 100000;
88module_param(apst_secondary_latency_tol_us, ulong, 0644);
89MODULE_PARM_DESC(apst_secondary_latency_tol_us,
90 "secondary APST latency tolerance in us");
91
b227c59b
RS		 92/*
93 * nvme_wq - hosts nvme related works that are not reset or delete
94 * nvme_reset_wq - hosts nvme reset works
95 * nvme_delete_wq - hosts nvme delete works
96 *
97b2512a
NK		 97 * nvme_wq will host works such as scan, aen handling, fw activation,
98 * keep-alive, periodic reconnects etc. nvme_reset_wq
b227c59b
RS		 99 * runs reset works which also flush works hosted on nvme_wq for
100 * serialization purposes. nvme_delete_wq host controller deletion
101 * works which flush reset works for serialization.
102 */
9a6327d2
SG		 103struct workqueue_struct *nvme_wq;
104EXPORT_SYMBOL_GPL(nvme_wq);
105
b227c59b
RS		 106struct workqueue_struct *nvme_reset_wq;
107EXPORT_SYMBOL_GPL(nvme_reset_wq);
108
109struct workqueue_struct *nvme_delete_wq;
110EXPORT_SYMBOL_GPL(nvme_delete_wq);
111
ab9e00cc
CH		 112static LIST_HEAD(nvme_subsystems);
113static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 114
9843f685 115static DEFINE_IDA(nvme_instance_ida);
f68abd9c 116static dev_t nvme_ctrl_base_chr_devt;
f3ca80fc 117static struct class *nvme_class;
ab9e00cc 118static struct class *nvme_subsys_class;
f3ca80fc 119
2637baed
MI		 120static DEFINE_IDA(nvme_ns_chr_minor_ida);
121static dev_t nvme_ns_chr_devt;
122static struct class *nvme_ns_chr_class;
123
12d9f070 124static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB		 125static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
126 unsigned nsid);
b58da2d2
TS		 127static void nvme_update_keep_alive(struct nvme_ctrl *ctrl,
128 struct nvme_command *cmd);
cf39a6bc 129
2405252a 130void nvme_queue_scan(struct nvme_ctrl *ctrl)
50e8d8ee
CH		 131{
132 /*
133 * Only new queue scan work when admin and IO queues are both alive
134 */
e6e7f7ac 135 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE && ctrl->tagset)
50e8d8ee
CH		 136 queue_work(nvme_wq, &ctrl->scan_work);
137}
138
4c75f877
KB		 139/*
140 * Use this function to proceed with scheduling reset_work for a controller
141 * that had previously been set to the resetting state. This is intended for
142 * code paths that can't be interrupted by other reset attempts. A hot removal
143 * may prevent this from succeeding.
144 */
c1ac9a4b 145int nvme_try_sched_reset(struct nvme_ctrl *ctrl)
4c75f877 146{
e6e7f7ac 147 if (nvme_ctrl_state(ctrl) != NVME_CTRL_RESETTING)
4c75f877
KB		 148 return -EBUSY;
149 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
150 return -EBUSY;
151 return 0;
152}
c1ac9a4b 153EXPORT_SYMBOL_GPL(nvme_try_sched_reset);
4c75f877 154
8c4dfea9
VG		 155static void nvme_failfast_work(struct work_struct *work)
156{
157 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
158 struct nvme_ctrl, failfast_work);
159
e6e7f7ac 160 if (nvme_ctrl_state(ctrl) != NVME_CTRL_CONNECTING)
8c4dfea9
VG		 161 return;
162
163 set_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
164 dev_info(ctrl->device, "failfast expired\n");
165 nvme_kick_requeue_lists(ctrl);
166}
167
168static inline void nvme_start_failfast_work(struct nvme_ctrl *ctrl)
169{
170 if (!ctrl->opts || ctrl->opts->fast_io_fail_tmo == -1)
171 return;
172
173 schedule_delayed_work(&ctrl->failfast_work,
174 ctrl->opts->fast_io_fail_tmo * HZ);
175}
176
177static inline void nvme_stop_failfast_work(struct nvme_ctrl *ctrl)
178{
179 if (!ctrl->opts)
180 return;
181
182 cancel_delayed_work_sync(&ctrl->failfast_work);
183 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
184}
185
186
d86c4d8e
CH		 187int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
188{
189 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
190 return -EBUSY;
b227c59b 191 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 192 return -EBUSY;
193 return 0;
194}
195EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
196
2405252a 197int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 198{
199 int ret;
200
201 ret = nvme_reset_ctrl(ctrl);
8000d1fd 202 if (!ret) {
d86c4d8e 203 flush_work(&ctrl->reset_work);
e6e7f7ac 204 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
8000d1fd
NC		 205 ret = -ENETRESET;
206 }
207
d86c4d8e
CH		 208 return ret;
209}
210
a686ed75 211static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
c5017e85 212{
77d0612d 213 dev_info(ctrl->device,
e5ea42fa 214 "Removing ctrl: NQN \"%s\"\n", nvmf_ctrl_subsysnqn(ctrl));
77d0612d 215
4054637c 216 flush_work(&ctrl->reset_work);
6cd53d14
CH		 217 nvme_stop_ctrl(ctrl);
218 nvme_remove_namespaces(ctrl);
c5017e85 219 ctrl->ops->delete_ctrl(ctrl);
6cd53d14 220 nvme_uninit_ctrl(ctrl);
c5017e85
CH		 221}
222
a686ed75
BVA		 223static void nvme_delete_ctrl_work(struct work_struct *work)
224{
225 struct nvme_ctrl *ctrl =
226 container_of(work, struct nvme_ctrl, delete_work);
227
228 nvme_do_delete_ctrl(ctrl);
229}
230
c5017e85
CH		 231int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
232{
233 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
234 return -EBUSY;
b227c59b 235 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 236 return -EBUSY;
237 return 0;
238}
239EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
240
942e21c0 241void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
c5017e85 242{
c5017e85 243 /*
01fc08ff
YY		 244 * Keep a reference until nvme_do_delete_ctrl() complete,
245 * since ->delete_ctrl can free the controller.
c5017e85
CH		 246 */
247 nvme_get_ctrl(ctrl);
6721c18a 248 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
b9c77583 249 nvme_do_delete_ctrl(ctrl);
c5017e85 250 nvme_put_ctrl(ctrl);
c5017e85 251}
c5017e85 252
2f9c1736 253static blk_status_t nvme_error_status(u16 status)
27fa9bc5 254{
2f9c1736 255 switch (status & 0x7ff) {
27fa9bc5 256 case NVME_SC_SUCCESS:
2a842aca 257 return BLK_STS_OK;
27fa9bc5 258 case NVME_SC_CAP_EXCEEDED:
2a842aca 259 return BLK_STS_NOSPC;
e96fef2c 260 case NVME_SC_LBA_RANGE:
35038bff
KB		 261 case NVME_SC_CMD_INTERRUPTED:
262 case NVME_SC_NS_NOT_READY:
e96fef2c
KB		 263 return BLK_STS_TARGET;
264 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 265 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 266 case NVME_SC_INVALID_OPCODE:
267 case NVME_SC_INVALID_FIELD:
268 case NVME_SC_INVALID_NS:
2a842aca 269 return BLK_STS_NOTSUPP;
e02ab023
JG		 270 case NVME_SC_WRITE_FAULT:
271 case NVME_SC_READ_ERROR:
272 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 273 case NVME_SC_ACCESS_DENIED:
274 case NVME_SC_READ_ONLY:
e96fef2c 275 case NVME_SC_COMPARE_FAILED:
2a842aca 276 return BLK_STS_MEDIUM;
a751da33
CH		 277 case NVME_SC_GUARD_CHECK:
278 case NVME_SC_APPTAG_CHECK:
279 case NVME_SC_REFTAG_CHECK:
280 case NVME_SC_INVALID_PI:
281 return BLK_STS_PROTECTION;
282 case NVME_SC_RESERVATION_CONFLICT:
7ba15083 283 return BLK_STS_RESV_CONFLICT;
1c0d12c0
SG		 284 case NVME_SC_HOST_PATH_ERROR:
285 return BLK_STS_TRANSPORT;
afaf5c6c
KB		 286 case NVME_SC_ZONE_TOO_MANY_ACTIVE:
287 return BLK_STS_ZONE_ACTIVE_RESOURCE;
288 case NVME_SC_ZONE_TOO_MANY_OPEN:
289 return BLK_STS_ZONE_OPEN_RESOURCE;
2a842aca
CH		 290 default:
291 return BLK_STS_IOERR;
27fa9bc5
CH		 292 }
293}
27fa9bc5 294
49cd84b6
KB		 295static void nvme_retry_req(struct request *req)
296{
49cd84b6
KB		 297 unsigned long delay = 0;
298 u16 crd;
299
300 /* The mask and shift result must be <= 3 */
301 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
f9063a53
MI		 302 if (crd)
303 delay = nvme_req(req)->ctrl->crdt[crd - 1] * 100;
49cd84b6
KB		 304
305 nvme_req(req)->retries++;
306 blk_mq_requeue_request(req, false);
307 blk_mq_delay_kick_requeue_list(req->q, delay);
308}
309
bd83fe6f
AA		 310static void nvme_log_error(struct request *req)
311{
312 struct nvme_ns *ns = req->q->queuedata;
313 struct nvme_request *nr = nvme_req(req);
314
315 if (ns) {
9419e71b 316 pr_err_ratelimited("%s: %s(0x%x) @ LBA %llu, %u blocks, %s (sct 0x%x / sc 0x%x) %s%s\n",
bd83fe6f
AA		 317 ns->disk ? ns->disk->disk_name : "?",
318 nvme_get_opcode_str(nr->cmd->common.opcode),
319 nr->cmd->common.opcode,
0372dd4e 320 nvme_sect_to_lba(ns->head, blk_rq_pos(req)),
9419e71b 321 blk_rq_bytes(req) >> ns->head->lba_shift,
bd83fe6f
AA		 322 nvme_get_error_status_str(nr->status),
323 nr->status >> 8 & 7, /* Status Code Type */
324 nr->status & 0xff, /* Status Code */
325 nr->status & NVME_SC_MORE ? "MORE " : "",
326 nr->status & NVME_SC_DNR ? "DNR " : "");
327 return;
328 }
329
330 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s\n",
331 dev_name(nr->ctrl->device),
332 nvme_get_admin_opcode_str(nr->cmd->common.opcode),
333 nr->cmd->common.opcode,
334 nvme_get_error_status_str(nr->status),
335 nr->status >> 8 & 7, /* Status Code Type */
336 nr->status & 0xff, /* Status Code */
337 nr->status & NVME_SC_MORE ? "MORE " : "",
338 nr->status & NVME_SC_DNR ? "DNR " : "");
339}
340
9f079dda
AA		 341static void nvme_log_err_passthru(struct request *req)
342{
343 struct nvme_ns *ns = req->q->queuedata;
344 struct nvme_request *nr = nvme_req(req);
345
346 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s"
347 "cdw10=0x%x cdw11=0x%x cdw12=0x%x cdw13=0x%x cdw14=0x%x cdw15=0x%x\n",
348 ns ? ns->disk->disk_name : dev_name(nr->ctrl->device),
349 ns ? nvme_get_opcode_str(nr->cmd->common.opcode) :
350 nvme_get_admin_opcode_str(nr->cmd->common.opcode),
351 nr->cmd->common.opcode,
352 nvme_get_error_status_str(nr->status),
353 nr->status >> 8 & 7, /* Status Code Type */
354 nr->status & 0xff, /* Status Code */
355 nr->status & NVME_SC_MORE ? "MORE " : "",
356 nr->status & NVME_SC_DNR ? "DNR " : "",
357 nr->cmd->common.cdw10,
358 nr->cmd->common.cdw11,
359 nr->cmd->common.cdw12,
360 nr->cmd->common.cdw13,
361 nr->cmd->common.cdw14,
362 nr->cmd->common.cdw14);
363}
364
5ddaabe8
CH		 365enum nvme_disposition {
366 COMPLETE,
367 RETRY,
368 FAILOVER,
f50fff73 369 AUTHENTICATE,
5ddaabe8
CH		 370};
371
372static inline enum nvme_disposition nvme_decide_disposition(struct request *req)
77f02a7a 373{
5ddaabe8
CH		 374 if (likely(nvme_req(req)->status == 0))
375 return COMPLETE;
908e4564 376
f50fff73
HR		 377 if ((nvme_req(req)->status & 0x7ff) == NVME_SC_AUTH_REQUIRED)
378 return AUTHENTICATE;
379
5ddaabe8
CH		 380 if (blk_noretry_request(req) ||
381 (nvme_req(req)->status & NVME_SC_DNR) ||
382 nvme_req(req)->retries >= nvme_max_retries)
383 return COMPLETE;
ca5554a6 384
5ddaabe8 385 if (req->cmd_flags & REQ_NVME_MPATH) {
5eac5f33
CL		 386 if (nvme_is_path_error(nvme_req(req)->status) ||
387 blk_queue_dying(req->q))
5ddaabe8 388 return FAILOVER;
5eac5f33
CL		 389 } else {
390 if (blk_queue_dying(req->q))
391 return COMPLETE;
5ddaabe8 392 }
16686f3a 393
5ddaabe8
CH		 394 return RETRY;
395}
6e3ca03e 396
c234a653 397static inline void nvme_end_req_zoned(struct request *req)
5ddaabe8 398{
5ddaabe8 399 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
0372dd4e
DW		 400 req_op(req) == REQ_OP_ZONE_APPEND) {
401 struct nvme_ns *ns = req->q->queuedata;
402
403 req->__sector = nvme_lba_to_sect(ns->head,
240e6ee2 404 le64_to_cpu(nvme_req(req)->result.u64));
0372dd4e 405 }
c234a653
JA		 406}
407
408static inline void nvme_end_req(struct request *req)
409{
410 blk_status_t status = nvme_error_status(nvme_req(req)->status);
35fe0d12 411
9f079dda
AA		 412 if (unlikely(nvme_req(req)->status && !(req->rq_flags & RQF_QUIET))) {
413 if (blk_rq_is_passthrough(req))
414 nvme_log_err_passthru(req);
415 else
416 nvme_log_error(req);
417 }
c234a653 418 nvme_end_req_zoned(req);
2b59787a 419 nvme_trace_bio_complete(req);
d4d957b5
SG		 420 if (req->cmd_flags & REQ_NVME_MPATH)
421 nvme_mpath_end_request(req);
908e4564 422 blk_mq_end_request(req, status);
77f02a7a 423}
5ddaabe8
CH		 424
425void nvme_complete_rq(struct request *req)
426{
f50fff73
HR		 427 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
428
5ddaabe8
CH		 429 trace_nvme_complete_rq(req);
430 nvme_cleanup_cmd(req);
431
774a9636
US		 432 /*
433 * Completions of long-running commands should not be able to
434 * defer sending of periodic keep alives, since the controller
435 * may have completed processing such commands a long time ago
436 * (arbitrarily close to command submission time).
437 * req->deadline - req->timeout is the command submission time
438 * in jiffies.
439 */
440 if (ctrl->kas &&
441 req->deadline - req->timeout >= ctrl->ka_last_check_time)
f50fff73 442 ctrl->comp_seen = true;
5ddaabe8
CH		 443
444 switch (nvme_decide_disposition(req)) {
445 case COMPLETE:
446 nvme_end_req(req);
447 return;
448 case RETRY:
449 nvme_retry_req(req);
450 return;
451 case FAILOVER:
452 nvme_failover_req(req);
453 return;
f50fff73 454 case AUTHENTICATE:
d6800634 455#ifdef CONFIG_NVME_HOST_AUTH
f50fff73
HR		 456 queue_work(nvme_wq, &ctrl->dhchap_auth_work);
457 nvme_retry_req(req);
458#else
459 nvme_end_req(req);
460#endif
461 return;
5ddaabe8
CH		 462 }
463}
77f02a7a
CH		 464EXPORT_SYMBOL_GPL(nvme_complete_rq);
465
c234a653
JA		 466void nvme_complete_batch_req(struct request *req)
467{
00e757b6 468 trace_nvme_complete_rq(req);
c234a653
JA		 469 nvme_cleanup_cmd(req);
470 nvme_end_req_zoned(req);
471}
472EXPORT_SYMBOL_GPL(nvme_complete_batch_req);
473
dda3248e
CL		 474/*
475 * Called to unwind from ->queue_rq on a failed command submission so that the
476 * multipathing code gets called to potentially failover to another path.
477 * The caller needs to unwind all transport specific resource allocations and
478 * must return propagate the return value.
479 */
480blk_status_t nvme_host_path_error(struct request *req)
481{
482 nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR;
483 blk_mq_set_request_complete(req);
484 nvme_complete_rq(req);
485 return BLK_STS_OK;
486}
487EXPORT_SYMBOL_GPL(nvme_host_path_error);
488
2dd6532e 489bool nvme_cancel_request(struct request *req, void *data)
c55a2fd4 490{
c55a2fd4
ML		 491 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
492 "Cancelling I/O %d", req->tag);
493
d4f1d5f7
LY		 494 /* don't abort one completed or idle request */
495 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT)
78ca4072
ML		 496 return true;
497
2dc3947b 498 nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD;
d3589381 499 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
15f73f5b 500 blk_mq_complete_request(req);
7baa8572 501 return true;
c55a2fd4
ML		 502}
503EXPORT_SYMBOL_GPL(nvme_cancel_request);
504
25479069
CL		 505void nvme_cancel_tagset(struct nvme_ctrl *ctrl)
506{
507 if (ctrl->tagset) {
508 blk_mq_tagset_busy_iter(ctrl->tagset,
509 nvme_cancel_request, ctrl);
510 blk_mq_tagset_wait_completed_request(ctrl->tagset);
511 }
512}
513EXPORT_SYMBOL_GPL(nvme_cancel_tagset);
514
515void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl)
516{
517 if (ctrl->admin_tagset) {
518 blk_mq_tagset_busy_iter(ctrl->admin_tagset,
519 nvme_cancel_request, ctrl);
520 blk_mq_tagset_wait_completed_request(ctrl->admin_tagset);
521 }
522}
523EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset);
524
bb8d261e
CH		 525bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
526 enum nvme_ctrl_state new_state)
527{
f6b6a28e 528 enum nvme_ctrl_state old_state;
0a72bbba 529 unsigned long flags;
bb8d261e
CH		 530 bool changed = false;
531
0a72bbba 532 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e 533
e6e7f7ac 534 old_state = nvme_ctrl_state(ctrl);
bb8d261e
CH		 535 switch (new_state) {
536 case NVME_CTRL_LIVE:
537 switch (old_state) {
7d2e8008 538 case NVME_CTRL_NEW:
bb8d261e 539 case NVME_CTRL_RESETTING:
ad6a0a52 540 case NVME_CTRL_CONNECTING:
bb8d261e 541 changed = true;
df561f66 542 fallthrough;
bb8d261e
CH		 543 default:
544 break;
545 }
546 break;
547 case NVME_CTRL_RESETTING:
548 switch (old_state) {
549 case NVME_CTRL_NEW:
def61eca 550 case NVME_CTRL_LIVE:
def61eca 551 changed = true;
df561f66 552 fallthrough;
def61eca
CH		 553 default:
554 break;
555 }
556 break;
ad6a0a52 557 case NVME_CTRL_CONNECTING:
def61eca 558 switch (old_state) {
b754a32c 559 case NVME_CTRL_NEW:
3cec7f9d 560 case NVME_CTRL_RESETTING:
bb8d261e 561 changed = true;
df561f66 562 fallthrough;
bb8d261e
CH		 563 default:
564 break;
565 }
566 break;
567 case NVME_CTRL_DELETING:
568 switch (old_state) {
569 case NVME_CTRL_LIVE:
570 case NVME_CTRL_RESETTING:
ad6a0a52 571 case NVME_CTRL_CONNECTING:
bb8d261e 572 changed = true;
df561f66 573 fallthrough;
bb8d261e
CH		 574 default:
575 break;
576 }
577 break;
ecca390e
SG		 578 case NVME_CTRL_DELETING_NOIO:
579 switch (old_state) {
580 case NVME_CTRL_DELETING:
581 case NVME_CTRL_DEAD:
582 changed = true;
df561f66 583 fallthrough;
ecca390e
SG		 584 default:
585 break;
586 }
587 break;
0ff9d4e1
KB		 588 case NVME_CTRL_DEAD:
589 switch (old_state) {
590 case NVME_CTRL_DELETING:
591 changed = true;
df561f66 592 fallthrough;
0ff9d4e1
KB		 593 default:
594 break;
595 }
596 break;
bb8d261e
CH		 597 default:
598 break;
599 }
bb8d261e 600
c1ac9a4b 601 if (changed) {
e6e7f7ac 602 WRITE_ONCE(ctrl->state, new_state);
c1ac9a4b
KB		 603 wake_up_all(&ctrl->state_wq);
604 }
bb8d261e 605
0a72bbba 606 spin_unlock_irqrestore(&ctrl->lock, flags);
8c4dfea9
VG		 607 if (!changed)
608 return false;
609
e6e7f7ac 610 if (new_state == NVME_CTRL_LIVE) {
8c4dfea9
VG		 611 if (old_state == NVME_CTRL_CONNECTING)
612 nvme_stop_failfast_work(ctrl);
32acab31 613 nvme_kick_requeue_lists(ctrl);
e6e7f7ac 614 } else if (new_state == NVME_CTRL_CONNECTING &&
8c4dfea9
VG		 615 old_state == NVME_CTRL_RESETTING) {
616 nvme_start_failfast_work(ctrl);
617 }
bb8d261e
CH		 618 return changed;
619}
620EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
621
c1ac9a4b
KB		 622/*
623 * Returns true for sink states that can't ever transition back to live.
624 */
625static bool nvme_state_terminal(struct nvme_ctrl *ctrl)
626{
e6e7f7ac 627 switch (nvme_ctrl_state(ctrl)) {
c1ac9a4b
KB		 628 case NVME_CTRL_NEW:
629 case NVME_CTRL_LIVE:
630 case NVME_CTRL_RESETTING:
631 case NVME_CTRL_CONNECTING:
632 return false;
633 case NVME_CTRL_DELETING:
ecca390e 634 case NVME_CTRL_DELETING_NOIO:
c1ac9a4b
KB		 635 case NVME_CTRL_DEAD:
636 return true;
637 default:
638 WARN_ONCE(1, "Unhandled ctrl state:%d", ctrl->state);
639 return true;
640 }
641}
642
643/*
644 * Waits for the controller state to be resetting, or returns false if it is
645 * not possible to ever transition to that state.
646 */
647bool nvme_wait_reset(struct nvme_ctrl *ctrl)
648{
649 wait_event(ctrl->state_wq,
650 nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) ||
651 nvme_state_terminal(ctrl));
e6e7f7ac 652 return nvme_ctrl_state(ctrl) == NVME_CTRL_RESETTING;
c1ac9a4b
KB		 653}
654EXPORT_SYMBOL_GPL(nvme_wait_reset);
655
ed754e5d
CH		 656static void nvme_free_ns_head(struct kref *ref)
657{
658 struct nvme_ns_head *head =
659 container_of(ref, struct nvme_ns_head, ref);
660
32acab31 661 nvme_mpath_remove_disk(head);
8b850475 662 ida_free(&head->subsys->ns_ida, head->instance);
f5ad3991 663 cleanup_srcu_struct(&head->srcu);
12d9f070 664 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 665 kfree(head);
666}
667
1496bd49 668bool nvme_tryget_ns_head(struct nvme_ns_head *head)
871ca3ef
CH		 669{
670 return kref_get_unless_zero(&head->ref);
671}
672
1496bd49 673void nvme_put_ns_head(struct nvme_ns_head *head)
ed754e5d
CH		 674{
675 kref_put(&head->ref, nvme_free_ns_head);
676}
677
1673f1f0
CH		 678static void nvme_free_ns(struct kref *kref)
679{
680 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
681
1673f1f0 682 put_disk(ns->disk);
ed754e5d 683 nvme_put_ns_head(ns->head);
075790eb 684 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 685 kfree(ns);
686}
687
4c74d1f8
KJ		 688static inline bool nvme_get_ns(struct nvme_ns *ns)
689{
690 return kref_get_unless_zero(&ns->kref);
691}
692
24493b8b 693void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 694{
695 kref_put(&ns->kref, nvme_free_ns);
696}
24493b8b 697EXPORT_SYMBOL_NS_GPL(nvme_put_ns, NVME_TARGET_PASSTHRU);
1673f1f0 698
bb06ec31
JS		 699static inline void nvme_clear_nvme_request(struct request *req)
700{
ae5e6886 701 nvme_req(req)->status = 0;
c03fd85d
CK		 702 nvme_req(req)->retries = 0;
703 nvme_req(req)->flags = 0;
704 req->rq_flags |= RQF_DONTPREP;
bb06ec31
JS		 705}
706
e559398f
CH		 707/* initialize a passthrough request */
708void nvme_init_request(struct request *req, struct nvme_command *cmd)
39dfe844 709{
9f079dda
AA		 710 struct nvme_request *nr = nvme_req(req);
711 bool logging_enabled;
712
713 if (req->q->queuedata) {
714 struct nvme_ns *ns = req->q->disk->private_data;
715
716 logging_enabled = ns->passthru_err_log_enabled;
0d2e7c84 717 req->timeout = NVME_IO_TIMEOUT;
9f079dda
AA		 718 } else { /* no queuedata implies admin queue */
719 logging_enabled = nr->ctrl->passthru_err_log_enabled;
dc96f938 720 req->timeout = NVME_ADMIN_TIMEOUT;
9f079dda
AA		 721 }
722
723 if (!logging_enabled)
724 req->rq_flags |= RQF_QUIET;
21d34711 725
f4b9e6c9
KB		 726 /* passthru commands should let the driver set the SGL flags */
727 cmd->common.flags &= ~NVME_CMD_SGL_ALL;
728
21d34711 729 req->cmd_flags |= REQ_FAILFAST_DRIVER;
be42a33b 730 if (req->mq_hctx->type == HCTX_TYPE_POLL)
6ce913fe 731 req->cmd_flags |= REQ_POLLED;
bb06ec31 732 nvme_clear_nvme_request(req);
9f079dda 733 memcpy(nr->cmd, cmd, sizeof(*cmd));
39dfe844 734}
e559398f 735EXPORT_SYMBOL_GPL(nvme_init_request);
39dfe844 736
a9715744
TC		 737/*
738 * For something we're not in a state to send to the device the default action
739 * is to busy it and retry it after the controller state is recovered. However,
740 * if the controller is deleting or if anything is marked for failfast or
741 * nvme multipath it is immediately failed.
742 *
743 * Note: commands used to initialize the controller will be marked for failfast.
744 * Note: nvme cli/ioctl commands are marked for failfast.
745 */
746blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl,
747 struct request *rq)
748{
e6e7f7ac
KB		 749 enum nvme_ctrl_state state = nvme_ctrl_state(ctrl);
750
751 if (state != NVME_CTRL_DELETING_NOIO &&
752 state != NVME_CTRL_DELETING &&
753 state != NVME_CTRL_DEAD &&
a9715744
TC		 754 !test_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags) &&
755 !blk_noretry_request(rq) && !(rq->cmd_flags & REQ_NVME_MPATH))
756 return BLK_STS_RESOURCE;
757 return nvme_host_path_error(rq);
758}
759EXPORT_SYMBOL_GPL(nvme_fail_nonready_command);
760
761bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq,
6d3c7fb1 762 bool queue_live, enum nvme_ctrl_state state)
a9715744
TC		 763{
764 struct nvme_request *req = nvme_req(rq);
765
766 /*
767 * currently we have a problem sending passthru commands
768 * on the admin_q if the controller is not LIVE because we can't
769 * make sure that they are going out after the admin connect,
770 * controller enable and/or other commands in the initialization
771 * sequence. until the controller will be LIVE, fail with
772 * BLK_STS_RESOURCE so that they will be rescheduled.
773 */
774 if (rq->q == ctrl->admin_q && (req->flags & NVME_REQ_USERCMD))
775 return false;
776
777 if (ctrl->ops->flags & NVME_F_FABRICS) {
778 /*
779 * Only allow commands on a live queue, except for the connect
780 * command, which is require to set the queue live in the
781 * appropinquate states.
782 */
6d3c7fb1 783 switch (state) {
a9715744
TC		 784 case NVME_CTRL_CONNECTING:
785 if (blk_rq_is_passthrough(rq) && nvme_is_fabrics(req->cmd) &&
f50fff73
HR		 786 (req->cmd->fabrics.fctype == nvme_fabrics_type_connect ||
787 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_send ||
788 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_receive))
a9715744
TC		 789 return true;
790 break;
791 default:
792 break;
793 case NVME_CTRL_DEAD:
794 return false;
795 }
796 }
797
798 return queue_live;
799}
800EXPORT_SYMBOL_GPL(__nvme_check_ready);
801
8093f7ca
ML		 802static inline void nvme_setup_flush(struct nvme_ns *ns,
803 struct nvme_command *cmnd)
804{
9c3d2929 805 memset(cmnd, 0, sizeof(*cmnd));
8093f7ca 806 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 807 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 808}
809
fc17b653 810static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 811 struct nvme_command *cmnd)
812{
b35ba01e 813 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 814 struct nvme_dsm_range *range;
b35ba01e 815 struct bio *bio;
8093f7ca 816
530436c4
EH		 817 /*
818 * Some devices do not consider the DSM 'Number of Ranges' field when
819 * determining how much data to DMA. Always allocate memory for maximum
820 * number of segments to prevent device reading beyond end of buffer.
821 */
822 static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES;
823
824 range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN);
cb5b7262
JA		 825 if (!range) {
826 /*
827 * If we fail allocation our range, fallback to the controller
828 * discard page. If that's also busy, it's safe to return
829 * busy, as we know we can make progress once that's freed.
830 */
831 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
832 return BLK_STS_RESOURCE;
833
834 range = page_address(ns->ctrl->discard_page);
835 }
8093f7ca 836
37f0dc2e 837 if (queue_max_discard_segments(req->q) == 1) {
0372dd4e 838 u64 slba = nvme_sect_to_lba(ns->head, blk_rq_pos(req));
9419e71b 839 u32 nlb = blk_rq_sectors(req) >> (ns->head->lba_shift - 9);
37f0dc2e
ML		 840
841 range[0].cattr = cpu_to_le32(0);
842 range[0].nlb = cpu_to_le32(nlb);
843 range[0].slba = cpu_to_le64(slba);
844 n = 1;
845 } else {
846 __rq_for_each_bio(bio, req) {
0372dd4e
DW		 847 u64 slba = nvme_sect_to_lba(ns->head,
848 bio->bi_iter.bi_sector);
9419e71b 849 u32 nlb = bio->bi_iter.bi_size >> ns->head->lba_shift;
37f0dc2e
ML		 850
851 if (n < segments) {
852 range[n].cattr = cpu_to_le32(0);
853 range[n].nlb = cpu_to_le32(nlb);
854 range[n].slba = cpu_to_le64(slba);
855 }
856 n++;
8cb6af7b 857 }
b35ba01e
CH		 858 }
859
860 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA		 861 if (virt_to_page(range) == ns->ctrl->discard_page)
862 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
863 else
864 kfree(range);
fc17b653 865 return BLK_STS_IOERR;
b35ba01e 866 }
8093f7ca 867
9c3d2929 868 memset(cmnd, 0, sizeof(*cmnd));
8093f7ca 869 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 870 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 871 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 872 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
873
4bee16da 874 bvec_set_virt(&req->special_vec, range, alloc_size);
f9d03f96 875 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 876
fc17b653 877 return BLK_STS_OK;
8093f7ca 878}
8093f7ca 879
4020aad8
KB		 880static void nvme_set_ref_tag(struct nvme_ns *ns, struct nvme_command *cmnd,
881 struct request *req)
882{
883 u32 upper, lower;
884 u64 ref48;
885
886 /* both rw and write zeroes share the same reftag format */
9419e71b 887 switch (ns->head->guard_type) {
4020aad8
KB		 888 case NVME_NVM_NS_16B_GUARD:
889 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
890 break;
891 case NVME_NVM_NS_64B_GUARD:
892 ref48 = ext_pi_ref_tag(req);
893 lower = lower_32_bits(ref48);
894 upper = upper_32_bits(ref48);
895
896 cmnd->rw.reftag = cpu_to_le32(lower);
897 cmnd->rw.cdw3 = cpu_to_le32(upper);
898 break;
899 default:
900 break;
901 }
902}
903
6e02318e
CK		 904static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
905 struct request *req, struct nvme_command *cmnd)
906{
9c3d2929
JA		 907 memset(cmnd, 0, sizeof(*cmnd));
908
6e02318e
CK		 909 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
910 return nvme_setup_discard(ns, req, cmnd);
911
912 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
913 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
914 cmnd->write_zeroes.slba =
0372dd4e 915 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req)));
6e02318e 916 cmnd->write_zeroes.length =
9419e71b 917 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1);
00b33cf3 918
9419e71b
DW		 919 if (!(req->cmd_flags & REQ_NOUNMAP) &&
920 (ns->head->features & NVME_NS_DEAC))
1b96f862
CH		 921 cmnd->write_zeroes.control |= cpu_to_le16(NVME_WZ_DEAC);
922
0372dd4e 923 if (nvme_ns_has_pi(ns->head)) {
1b96f862 924 cmnd->write_zeroes.control |= cpu_to_le16(NVME_RW_PRINFO_PRACT);
00b33cf3 925
9419e71b 926 switch (ns->head->pi_type) {
00b33cf3
KJ		 927 case NVME_NS_DPS_PI_TYPE1:
928 case NVME_NS_DPS_PI_TYPE2:
4020aad8 929 nvme_set_ref_tag(ns, cmnd, req);
00b33cf3
KJ		 930 break;
931 }
932 }
933
6e02318e
CK		 934 return BLK_STS_OK;
935}
936
ebe6d874 937static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
240e6ee2
KB		 938 struct request *req, struct nvme_command *cmnd,
939 enum nvme_opcode op)
8093f7ca
ML		 940{
941 u16 control = 0;
942 u32 dsmgmt = 0;
943
944 if (req->cmd_flags & REQ_FUA)
945 control |= NVME_RW_FUA;
946 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
947 control |= NVME_RW_LR;
948
949 if (req->cmd_flags & REQ_RAHEAD)
950 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
951
240e6ee2 952 cmnd->rw.opcode = op;
a9a7e30f 953 cmnd->rw.flags = 0;
ed754e5d 954 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
4020aad8
KB		 955 cmnd->rw.cdw2 = 0;
956 cmnd->rw.cdw3 = 0;
a9a7e30f 957 cmnd->rw.metadata = 0;
0372dd4e
DW		 958 cmnd->rw.slba =
959 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req)));
9419e71b
DW		 960 cmnd->rw.length =
961 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1);
a9a7e30f
JA		 962 cmnd->rw.reftag = 0;
963 cmnd->rw.apptag = 0;
964 cmnd->rw.appmask = 0;
8093f7ca 965
9419e71b 966 if (ns->head->ms) {
715ea9e0
CH		 967 /*
968 * If formated with metadata, the block layer always provides a
969 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
970 * we enable the PRACT bit for protection information or set the
971 * namespace capacity to zero to prevent any I/O.
972 */
973 if (!blk_integrity_rq(req)) {
0372dd4e 974 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns->head)))
715ea9e0
CH		 975 return BLK_STS_NOTSUPP;
976 control |= NVME_RW_PRINFO_PRACT;
977 }
978
9419e71b 979 switch (ns->head->pi_type) {
8093f7ca
ML		 980 case NVME_NS_DPS_PI_TYPE3:
981 control |= NVME_RW_PRINFO_PRCHK_GUARD;
982 break;
983 case NVME_NS_DPS_PI_TYPE1:
984 case NVME_NS_DPS_PI_TYPE2:
985 control |= NVME_RW_PRINFO_PRCHK_GUARD |
986 NVME_RW_PRINFO_PRCHK_REF;
240e6ee2
KB		 987 if (op == nvme_cmd_zone_append)
988 control |= NVME_RW_APPEND_PIREMAP;
4020aad8 989 nvme_set_ref_tag(ns, cmnd, req);
8093f7ca
ML		 990 break;
991 }
8093f7ca
ML		 992 }
993
994 cmnd->rw.control = cpu_to_le16(control);
995 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 996 return 0;
8093f7ca
ML		 997}
998
f7f1fc36
MG		 999void nvme_cleanup_cmd(struct request *req)
1000{
f7f1fc36 1001 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
fc97e942 1002 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
cb5b7262 1003
3973e15f 1004 if (req->special_vec.bv_page == ctrl->discard_page)
fc97e942 1005 clear_bit_unlock(0, &ctrl->discard_page_busy);
cb5b7262 1006 else
3973e15f 1007 kfree(bvec_virt(&req->special_vec));
f7f1fc36
MG		 1008 }
1009}
1010EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
1011
f4b9e6c9 1012blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req)
8093f7ca 1013{
f4b9e6c9 1014 struct nvme_command *cmd = nvme_req(req)->cmd;
fc17b653 1015 blk_status_t ret = BLK_STS_OK;
8093f7ca 1016
9c3d2929 1017 if (!(req->rq_flags & RQF_DONTPREP))
c03fd85d 1018 nvme_clear_nvme_request(req);
987f699a 1019
aebf526b
CH		 1020 switch (req_op(req)) {
1021 case REQ_OP_DRV_IN:
1022 case REQ_OP_DRV_OUT:
f4b9e6c9 1023 /* these are setup prior to execution in nvme_init_request() */
aebf526b
CH		 1024 break;
1025 case REQ_OP_FLUSH:
8093f7ca 1026 nvme_setup_flush(ns, cmd);
aebf526b 1027 break;
240e6ee2
KB		 1028 case REQ_OP_ZONE_RESET_ALL:
1029 case REQ_OP_ZONE_RESET:
1030 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET);
1031 break;
1032 case REQ_OP_ZONE_OPEN:
1033 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN);
1034 break;
1035 case REQ_OP_ZONE_CLOSE:
1036 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE);
1037 break;
1038 case REQ_OP_ZONE_FINISH:
1039 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH);
1040 break;
e850fd16 1041 case REQ_OP_WRITE_ZEROES:
6e02318e
CK		 1042 ret = nvme_setup_write_zeroes(ns, req, cmd);
1043 break;
aebf526b 1044 case REQ_OP_DISCARD:
8093f7ca 1045 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 1046 break;
1047 case REQ_OP_READ:
240e6ee2
KB		 1048 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read);
1049 break;
aebf526b 1050 case REQ_OP_WRITE:
240e6ee2
KB		 1051 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write);
1052 break;
1053 case REQ_OP_ZONE_APPEND:
1054 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append);
aebf526b
CH		 1055 break;
1056 default:
1057 WARN_ON_ONCE(1);
fc17b653 1058 return BLK_STS_IOERR;
aebf526b 1059 }
8093f7ca 1060
e7006de6 1061 cmd->common.command_id = nvme_cid(req);
5d87eb94 1062 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 1063 return ret;
1064}
1065EXPORT_SYMBOL_GPL(nvme_setup_cmd);
1066
ae5e6886
KB		 1067/*
1068 * Return values:
1069 * 0: success
1070 * >0: nvme controller's cqe status response
1071 * <0: kernel error in lieu of controller response
1072 */
62281b9e 1073int nvme_execute_rq(struct request *rq, bool at_head)
ae5e6886
KB		 1074{
1075 blk_status_t status;
1076
b84ba30b 1077 status = blk_execute_rq(rq, at_head);
ae5e6886
KB		 1078 if (nvme_req(rq)->flags & NVME_REQ_CANCELLED)
1079 return -EINTR;
1080 if (nvme_req(rq)->status)
1081 return nvme_req(rq)->status;
1082 return blk_status_to_errno(status);
1083}
62281b9e 1084EXPORT_SYMBOL_NS_GPL(nvme_execute_rq, NVME_TARGET_PASSTHRU);
ae5e6886 1085
4160982e
CH		 1086/*
1087 * Returns 0 on success. If the result is negative, it's a Linux error code;
1088 * if the result is positive, it's an NVM Express status code
1089 */
1090int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 1091 union nvme_result *result, void *buffer, unsigned bufflen,
bd2687f2 1092 int qid, nvme_submit_flags_t flags)
4160982e
CH		 1093{
1094 struct request *req;
1095 int ret;
bd2687f2 1096 blk_mq_req_flags_t blk_flags = 0;
4160982e 1097
bd2687f2
HR		 1098 if (flags & NVME_SUBMIT_NOWAIT)
1099 blk_flags |= BLK_MQ_REQ_NOWAIT;
1100 if (flags & NVME_SUBMIT_RESERVED)
1101 blk_flags |= BLK_MQ_REQ_RESERVED;
39dfe844 1102 if (qid == NVME_QID_ANY)
bd2687f2 1103 req = blk_mq_alloc_request(q, nvme_req_op(cmd), blk_flags);
39dfe844 1104 else
bd2687f2 1105 req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), blk_flags,
b10907b8 1106 qid - 1);
e559398f 1107
4160982e
CH		 1108 if (IS_ERR(req))
1109 return PTR_ERR(req);
e559398f 1110 nvme_init_request(req, cmd);
48dae466
HR		 1111 if (flags & NVME_SUBMIT_RETRY)
1112 req->cmd_flags &= ~REQ_FAILFAST_DRIVER;
4160982e 1113
21d34711
CH		 1114 if (buffer && bufflen) {
1115 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
1116 if (ret)
1117 goto out;
4160982e
CH		 1118 }
1119
bd2687f2 1120 ret = nvme_execute_rq(req, flags & NVME_SUBMIT_AT_HEAD);
ae5e6886 1121 if (result && ret >= 0)
d49187e9 1122 *result = nvme_req(req)->result;
4160982e
CH		 1123 out:
1124 blk_mq_free_request(req);
1125 return ret;
1126}
eb71f435 1127EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 1128
1129int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1130 void *buffer, unsigned bufflen)
1131{
6b46fa02 1132 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen,
bd2687f2 1133 NVME_QID_ANY, 0);
4160982e 1134}
576d55d6 1135EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 1136
df21b6b1
LG		 1137u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
1138{
1139 u32 effects = 0;
1140
1141 if (ns) {
cc115cbe 1142 effects = le32_to_cpu(ns->head->effects->iocs[opcode]);
df21b6b1 1143 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
ed4a854b 1144 dev_warn_once(ctrl->device,
831ed60c 1145 "IO command:%02x has unusual effects:%08x\n",
ed4a854b 1146 opcode, effects);
df21b6b1 1147
831ed60c
CH		 1148 /*
1149 * NVME_CMD_EFFECTS_CSE_MASK causes a freeze all I/O queues,
1150 * which would deadlock when done on an I/O command. Note that
1151 * We already warn about an unusual effect above.
1152 */
1153 effects &= ~NVME_CMD_EFFECTS_CSE_MASK;
1154 } else {
cc115cbe 1155 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
831ed60c 1156 }
df21b6b1
LG		 1157
1158 return effects;
1159}
1160EXPORT_SYMBOL_NS_GPL(nvme_command_effects, NVME_TARGET_PASSTHRU);
1161
62281b9e 1162u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
df21b6b1
LG		 1163{
1164 u32 effects = nvme_command_effects(ctrl, ns, opcode);
1165
1166 /*
1167 * For simplicity, IO to all namespaces is quiesced even if the command
1168 * effects say only one namespace is affected.
1169 */
af0f446d 1170 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG		 1171 mutex_lock(&ctrl->scan_lock);
1172 mutex_lock(&ctrl->subsys->lock);
1173 nvme_mpath_start_freeze(ctrl->subsys);
1174 nvme_mpath_wait_freeze(ctrl->subsys);
1175 nvme_start_freeze(ctrl);
1176 nvme_wait_freeze(ctrl);
1177 }
1178 return effects;
1179}
62281b9e 1180EXPORT_SYMBOL_NS_GPL(nvme_passthru_start, NVME_TARGET_PASSTHRU);
df21b6b1 1181
31a59782 1182void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects,
bc8fb906 1183 struct nvme_command *cmd, int status)
df21b6b1 1184{
af0f446d 1185 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG		 1186 nvme_unfreeze(ctrl);
1187 nvme_mpath_unfreeze(ctrl->subsys);
1188 mutex_unlock(&ctrl->subsys->lock);
df21b6b1
LG		 1189 mutex_unlock(&ctrl->scan_lock);
1190 }
1e37a307 1191 if (effects & NVME_CMD_EFFECTS_CCC) {
d0dd594b
BL		 1192 if (!test_and_set_bit(NVME_CTRL_DIRTY_CAPABILITY,
1193 &ctrl->flags)) {
1194 dev_info(ctrl->device,
1e37a307 1195"controller capabilities changed, reset may be required to take effect.\n");
d0dd594b 1196 }
1e37a307 1197 }
df21b6b1
LG		 1198 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) {
1199 nvme_queue_scan(ctrl);
1200 flush_work(&ctrl->scan_work);
1201 }
31a59782 1202 if (ns)
1203 return;
b58da2d2
TS		 1204
1205 switch (cmd->common.opcode) {
1206 case nvme_admin_set_features:
1207 switch (le32_to_cpu(cmd->common.cdw10) & 0xFF) {
1208 case NVME_FEAT_KATO:
1209 /*
1210 * Keep alive commands interval on the host should be
1211 * updated when KATO is modified by Set Features
1212 * commands.
1213 */
1214 if (!status)
1215 nvme_update_keep_alive(ctrl, cmd);
1216 break;
1217 default:
1218 break;
1219 }
1220 break;
1221 default:
1222 break;
1223 }
df21b6b1 1224}
bc8fb906 1225EXPORT_SYMBOL_NS_GPL(nvme_passthru_end, NVME_TARGET_PASSTHRU);
df21b6b1 1226
a70b81bd
HR		 1227/*
1228 * Recommended frequency for KATO commands per NVMe 1.4 section 7.12.1:
1229 *
1230 * The host should send Keep Alive commands at half of the Keep Alive Timeout
1231 * accounting for transport roundtrip times [..].
1232 */
ea4d453b
US		 1233static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl)
1234{
1235 unsigned long delay = ctrl->kato * HZ / 2;
1236
1237 /*
1238 * When using Traffic Based Keep Alive, we need to run
1239 * nvme_keep_alive_work at twice the normal frequency, as one
1240 * command completion can postpone sending a keep alive command
1241 * by up to twice the delay between runs.
1242 */
1243 if (ctrl->ctratt & NVME_CTRL_ATTR_TBKAS)
1244 delay /= 2;
1245 return delay;
1246}
1247
a70b81bd 1248static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl)
4160982e 1249{
136cfcb8
MD		 1250 unsigned long now = jiffies;
1251 unsigned long delay = nvme_keep_alive_work_period(ctrl);
1252 unsigned long ka_next_check_tm = ctrl->ka_last_check_time + delay;
1253
1254 if (time_after(now, ka_next_check_tm))
1255 delay = 0;
1256 else
1257 delay = ka_next_check_tm - now;
1258
1259 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay);
21d34711
CH		 1260}
1261
de671d61
JA		 1262static enum rq_end_io_ret nvme_keep_alive_end_io(struct request *rq,
1263 blk_status_t status)
038bd4cb
SG		 1264{
1265 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS		 1266 unsigned long flags;
1267 bool startka = false;
c7275ce6
US		 1268 unsigned long rtt = jiffies - (rq->deadline - rq->timeout);
1269 unsigned long delay = nvme_keep_alive_work_period(ctrl);
1270
1271 /*
1272 * Subtract off the keepalive RTT so nvme_keep_alive_work runs
1273 * at the desired frequency.
1274 */
1275 if (rtt <= delay) {
1276 delay -= rtt;
1277 } else {
1278 dev_warn(ctrl->device, "long keepalive RTT (%u ms)\n",
1279 jiffies_to_msecs(rtt));
1280 delay = 0;
1281 }
038bd4cb
SG		 1282
1283 blk_mq_free_request(rq);
1284
2a842aca 1285 if (status) {
038bd4cb 1286 dev_err(ctrl->device,
2a842aca
CH		 1287 "failed nvme_keep_alive_end_io error=%d\n",
1288 status);
de671d61 1289 return RQ_END_IO_NONE;
038bd4cb
SG		 1290 }
1291
774a9636 1292 ctrl->ka_last_check_time = jiffies;
6e3ca03e 1293 ctrl->comp_seen = false;
86880d64
JS		 1294 spin_lock_irqsave(&ctrl->lock, flags);
1295 if (ctrl->state == NVME_CTRL_LIVE ||
1296 ctrl->state == NVME_CTRL_CONNECTING)
1297 startka = true;
1298 spin_unlock_irqrestore(&ctrl->lock, flags);
1299 if (startka)
c7275ce6 1300 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay);
de671d61 1301 return RQ_END_IO_NONE;
038bd4cb
SG		 1302}
1303
038bd4cb
SG		 1304static void nvme_keep_alive_work(struct work_struct *work)
1305{
1306 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
1307 struct nvme_ctrl, ka_work);
6e3ca03e 1308 bool comp_seen = ctrl->comp_seen;
06c3c336 1309 struct request *rq;
6e3ca03e 1310
774a9636
US		 1311 ctrl->ka_last_check_time = jiffies;
1312
6e3ca03e
SG		 1313 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
1314 dev_dbg(ctrl->device,
1315 "reschedule traffic based keep-alive timer\n");
1316 ctrl->comp_seen = false;
a70b81bd 1317 nvme_queue_keep_alive_work(ctrl);
6e3ca03e
SG		 1318 return;
1319 }
038bd4cb 1320
e559398f
CH		 1321 rq = blk_mq_alloc_request(ctrl->admin_q, nvme_req_op(&ctrl->ka_cmd),
1322 BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT);
06c3c336 1323 if (IS_ERR(rq)) {
038bd4cb 1324 /* allocation failure, reset the controller */
985c5a32 1325 dev_err(ctrl->device, "keep-alive failed: %ld\n", PTR_ERR(rq));
39bdc590 1326 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 1327 return;
1328 }
e559398f 1329 nvme_init_request(rq, &ctrl->ka_cmd);
06c3c336
CH		 1330
1331 rq->timeout = ctrl->kato * HZ;
e2e53086 1332 rq->end_io = nvme_keep_alive_end_io;
06c3c336 1333 rq->end_io_data = ctrl;
e2e53086 1334 blk_execute_rq_nowait(rq, false);
038bd4cb
SG		 1335}
1336
00b683db 1337static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 1338{
1339 if (unlikely(ctrl->kato == 0))
1340 return;
1341
a70b81bd 1342 nvme_queue_keep_alive_work(ctrl);
038bd4cb 1343}
038bd4cb
SG		 1344
1345void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
1346{
1347 if (unlikely(ctrl->kato == 0))
1348 return;
1349
1350 cancel_delayed_work_sync(&ctrl->ka_work);
1351}
1352EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
1353
b58da2d2
TS		 1354static void nvme_update_keep_alive(struct nvme_ctrl *ctrl,
1355 struct nvme_command *cmd)
1356{
1357 unsigned int new_kato =
1358 DIV_ROUND_UP(le32_to_cpu(cmd->common.cdw11), 1000);
1359
1360 dev_info(ctrl->device,
1361 "keep alive interval updated from %u ms to %u ms\n",
1362 ctrl->kato * 1000 / 2, new_kato * 1000 / 2);
1363
1364 nvme_stop_keep_alive(ctrl);
1365 ctrl->kato = new_kato;
1366 nvme_start_keep_alive(ctrl);
1367}
1368
b9a5c3d4
CH		 1369/*
1370 * In NVMe 1.0 the CNS field was just a binary controller or namespace
1371 * flag, thus sending any new CNS opcodes has a big chance of not working.
1372 * Qemu unfortunately had that bug after reporting a 1.1 version compliance
1373 * (but not for any later version).
1374 */
1375static bool nvme_ctrl_limited_cns(struct nvme_ctrl *ctrl)
1376{
1377 if (ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)
1378 return ctrl->vs < NVME_VS(1, 2, 0);
1379 return ctrl->vs < NVME_VS(1, 1, 0);
1380}
1381
3f7f25a9 1382static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 1383{
1384 struct nvme_command c = { };
1385 int error;
1386
1387 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1388 c.identify.opcode = nvme_admin_identify;
986994a2 1389 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 1390
1391 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1392 if (!*id)
1393 return -ENOMEM;
1394
1395 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1396 sizeof(struct nvme_id_ctrl));
1397 if (error)
1398 kfree(*id);
1399 return error;
1400}
1401
ad95a613 1402static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids,
71010c30 1403 struct nvme_ns_id_desc *cur, bool *csi_seen)
ad95a613
CK		 1404{
1405 const char *warn_str = "ctrl returned bogus length:";
1406 void *data = cur;
1407
1408 switch (cur->nidt) {
1409 case NVME_NIDT_EUI64:
1410 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
1411 dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n",
1412 warn_str, cur->nidl);
1413 return -1;
1414 }
00ff400e
CH		 1415 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1416 return NVME_NIDT_EUI64_LEN;
ad95a613
CK		 1417 memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN);
1418 return NVME_NIDT_EUI64_LEN;
1419 case NVME_NIDT_NGUID:
1420 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
1421 dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n",
1422 warn_str, cur->nidl);
1423 return -1;
1424 }
00ff400e
CH		 1425 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1426 return NVME_NIDT_NGUID_LEN;
ad95a613
CK		 1427 memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN);
1428 return NVME_NIDT_NGUID_LEN;
1429 case NVME_NIDT_UUID:
1430 if (cur->nidl != NVME_NIDT_UUID_LEN) {
1431 dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n",
1432 warn_str, cur->nidl);
1433 return -1;
1434 }
00ff400e
CH		 1435 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1436 return NVME_NIDT_UUID_LEN;
ad95a613
CK		 1437 uuid_copy(&ids->uuid, data + sizeof(*cur));
1438 return NVME_NIDT_UUID_LEN;
71010c30
NC		 1439 case NVME_NIDT_CSI:
1440 if (cur->nidl != NVME_NIDT_CSI_LEN) {
1441 dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n",
1442 warn_str, cur->nidl);
1443 return -1;
1444 }
1445 memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN);
1446 *csi_seen = true;
1447 return NVME_NIDT_CSI_LEN;
ad95a613
CK		 1448 default:
1449 /* Skip unknown types */
1450 return cur->nidl;
1451 }
1452}
1453
1a893c2b
CH		 1454static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl,
1455 struct nvme_ns_info *info)
3b22ba26
JT		 1456{
1457 struct nvme_command c = { };
71010c30
NC		 1458 bool csi_seen = false;
1459 int status, pos, len;
3b22ba26 1460 void *data;
3b22ba26 1461
8b7c0ff2
CH		 1462 if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl))
1463 return 0;
5bedd3af
CH		 1464 if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST)
1465 return 0;
1466
3b22ba26 1467 c.identify.opcode = nvme_admin_identify;
1a893c2b 1468 c.identify.nsid = cpu_to_le32(info->nsid);
3b22ba26
JT		 1469 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1470
1471 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1472 if (!data)
1473 return -ENOMEM;
1474
cdbff4f2 1475 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26 1476 NVME_IDENTIFY_DATA_SIZE);
fb314eb0
CH		 1477 if (status) {
1478 dev_warn(ctrl->device,
aa9d7295 1479 "Identify Descriptors failed (nsid=%u, status=0x%x)\n",
1a893c2b 1480 info->nsid, status);
3b22ba26 1481 goto free_data;
fb314eb0 1482 }
3b22ba26
JT		 1483
1484 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1485 struct nvme_ns_id_desc *cur = data + pos;
1486
1487 if (cur->nidl == 0)
1488 break;
1489
1a893c2b 1490 len = nvme_process_ns_desc(ctrl, &info->ids, cur, &csi_seen);
ad95a613 1491 if (len < 0)
71010c30 1492 break;
3b22ba26
JT		 1493
1494 len += sizeof(*cur);
1495 }
71010c30
NC		 1496
1497 if (nvme_multi_css(ctrl) && !csi_seen) {
1498 dev_warn(ctrl->device, "Command set not reported for nsid:%d\n",
1a893c2b 1499 info->nsid);
71010c30
NC		 1500 status = -EINVAL;
1501 }
1502
3b22ba26
JT		 1503free_data:
1504 kfree(data);
1505 return status;
1506}
1507
a1a825ab 1508int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid,
1a893c2b 1509 struct nvme_id_ns **id)
21d34711
CH		 1510{
1511 struct nvme_command c = { };
1512 int error;
1513
1514 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 1515 c.identify.opcode = nvme_admin_identify;
1516 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1517 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1518
331813f6
SG		 1519 *id = kmalloc(sizeof(**id), GFP_KERNEL);
1520 if (!*id)
1521 return -ENOMEM;
21d34711 1522
331813f6 1523 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id));
cdbff4f2 1524 if (error) {
d0de579c 1525 dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error);
0dd6fff2 1526 kfree(*id);
cdbff4f2 1527 }
1a893c2b
CH		 1528 return error;
1529}
00ff400e 1530
1a893c2b
CH		 1531static int nvme_ns_info_from_identify(struct nvme_ctrl *ctrl,
1532 struct nvme_ns_info *info)
1533{
1534 struct nvme_ns_ids *ids = &info->ids;
1535 struct nvme_id_ns *id;
1536 int ret;
1537
1538 ret = nvme_identify_ns(ctrl, info->nsid, &id);
1539 if (ret)
1540 return ret;
0dd6fff2
CH		 1541
1542 if (id->ncap == 0) {
1543 /* namespace not allocated or attached */
1544 info->is_removed = true;
e3139cef
ML		 1545 ret = -ENODEV;
1546 goto error;
0dd6fff2
CH		 1547 }
1548
1a893c2b
CH		 1549 info->anagrpid = id->anagrpid;
1550 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED;
1e4ea66a 1551 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO;
1a893c2b 1552 info->is_ready = true;
00ff400e
CH		 1553 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) {
1554 dev_info(ctrl->device,
1555 "Ignoring bogus Namespace Identifiers\n");
1556 } else {
1557 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
1558 !memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
1a893c2b 1559 memcpy(ids->eui64, id->eui64, sizeof(ids->eui64));
00ff400e
CH		 1560 if (ctrl->vs >= NVME_VS(1, 2, 0) &&
1561 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
1a893c2b 1562 memcpy(ids->nguid, id->nguid, sizeof(ids->nguid));
00ff400e 1563 }
e3139cef
ML		 1564
1565error:
1a893c2b 1566 kfree(id);
e3139cef 1567 return ret;
21d34711
CH		 1568}
1569
1a893c2b
CH		 1570static int nvme_ns_info_from_id_cs_indep(struct nvme_ctrl *ctrl,
1571 struct nvme_ns_info *info)
354201c5 1572{
1a893c2b 1573 struct nvme_id_ns_cs_indep *id;
354201c5
CH		 1574 struct nvme_command c = {
1575 .identify.opcode = nvme_admin_identify,
1a893c2b 1576 .identify.nsid = cpu_to_le32(info->nsid),
354201c5
CH		 1577 .identify.cns = NVME_ID_CNS_NS_CS_INDEP,
1578 };
1579 int ret;
1580
1a893c2b
CH		 1581 id = kmalloc(sizeof(*id), GFP_KERNEL);
1582 if (!id)
354201c5
CH		 1583 return -ENOMEM;
1584
1a893c2b
CH		 1585 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
1586 if (!ret) {
1587 info->anagrpid = id->anagrpid;
1588 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED;
1e4ea66a 1589 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO;
1a893c2b 1590 info->is_ready = id->nstat & NVME_NSTAT_NRDY;
354201c5 1591 }
1a893c2b
CH		 1592 kfree(id);
1593 return ret;
354201c5
CH		 1594}
1595
1a87ee65
KB		 1596static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
1597 unsigned int dword11, void *buffer, size_t buflen, u32 *result)
21d34711 1598{
15755854 1599 union nvme_result res = { 0 };
cc72c442 1600 struct nvme_command c = { };
1cb3cce5 1601 int ret;
21d34711 1602
1a87ee65 1603 c.features.opcode = op;
21d34711
CH		 1604 c.features.fid = cpu_to_le32(fid);
1605 c.features.dword11 = cpu_to_le32(dword11);
1606
d49187e9 1607 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
bd2687f2 1608 buffer, buflen, NVME_QID_ANY, 0);
9b47f77a 1609 if (ret >= 0 && result)
d49187e9 1610 *result = le32_to_cpu(res.u32);
1cb3cce5 1611 return ret;
21d34711
CH		 1612}
1613
1a87ee65
KB		 1614int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
1615 unsigned int dword11, void *buffer, size_t buflen,
1616 u32 *result)
1617{
1618 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer,
1619 buflen, result);
1620}
1621EXPORT_SYMBOL_GPL(nvme_set_features);
1622
1623int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
1624 unsigned int dword11, void *buffer, size_t buflen,
1625 u32 *result)
1626{
1627 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer,
1628 buflen, result);
1629}
1630EXPORT_SYMBOL_GPL(nvme_get_features);
1631
9a0be7ab
CH		 1632int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1633{
1634 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1635 u32 result;
1636 int status, nr_io_queues;
1637
1a6fe74d 1638 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1639 &result);
f5fa90dc 1640 if (status < 0)
9a0be7ab
CH		 1641 return status;
1642
f5fa90dc
CH		 1643 /*
1644 * Degraded controllers might return an error when setting the queue
1645 * count. We still want to be able to bring them online and offer
1646 * access to the admin queue, as that might be only way to fix them up.
1647 */
1648 if (status > 0) {
f0425db0 1649 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1650 *count = 0;
1651 } else {
1652 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1653 *count = min(*count, nr_io_queues);
1654 }
1655
9a0be7ab
CH		 1656 return 0;
1657}
576d55d6 1658EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1659
c0561f82 1660#define NVME_AEN_SUPPORTED \
85f8a435
SG		 1661 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \
1662 NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE)
c0561f82
HR		 1663
1664static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1665{
fa441b71 1666 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR		 1667 int status;
1668
fa441b71
WZ		 1669 if (!supported_aens)
1670 return;
1671
1672 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1673 NULL, 0, &result);
c0561f82
HR		 1674 if (status)
1675 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1676 supported_aens);
93da4023
SG		 1677
1678 queue_work(nvme_wq, &ctrl->async_event_work);
c0561f82
HR		 1679}
1680
f5b9a51d 1681static int nvme_ns_open(struct nvme_ns *ns)
c225b610 1682{
c225b610 1683
32acab31 1684 /* should never be called due to GENHD_FL_HIDDEN */
30897388 1685 if (WARN_ON_ONCE(nvme_ns_head_multipath(ns->head)))
85088c4a 1686 goto fail;
4c74d1f8 1687 if (!nvme_get_ns(ns))
85088c4a
NC		 1688 goto fail;
1689 if (!try_module_get(ns->ctrl->ops->module))
1690 goto fail_put_ns;
1691
c6424a90 1692 return 0;
85088c4a
NC		 1693
1694fail_put_ns:
1695 nvme_put_ns(ns);
1696fail:
1697 return -ENXIO;
1673f1f0
CH		 1698}
1699
f5b9a51d 1700static void nvme_ns_release(struct nvme_ns *ns)
1673f1f0 1701{
85088c4a
NC		 1702
1703 module_put(ns->ctrl->ops->module);
1704 nvme_put_ns(ns);
1673f1f0
CH		 1705}
1706
05bdb996 1707static int nvme_open(struct gendisk *disk, blk_mode_t mode)
f5b9a51d 1708{
d32e2bf8 1709 return nvme_ns_open(disk->private_data);
f5b9a51d
CH		 1710}
1711
ae220766 1712static void nvme_release(struct gendisk *disk)
f5b9a51d
CH		 1713{
1714 nvme_ns_release(disk->private_data);
1715}
1716
1496bd49 1717int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1673f1f0
CH		 1718{
1719 /* some standard values */
1720 geo->heads = 1 << 6;
1721 geo->sectors = 1 << 5;
1722 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1723 return 0;
1724}
1725
f467b48e 1726static bool nvme_init_integrity(struct gendisk *disk, struct nvme_ns_head *head)
1673f1f0 1727{
cc72c442 1728 struct blk_integrity integrity = { };
1673f1f0 1729
414c62e2
CH		 1730 blk_integrity_unregister(disk);
1731
f467b48e
CH		 1732 if (!head->ms)
1733 return true;
1734
1735 /*
1736 * PI can always be supported as we can ask the controller to simply
1737 * insert/strip it, which is not possible for other kinds of metadata.
1738 */
1739 if (!IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) ||
1740 !(head->features & NVME_NS_METADATA_SUPPORTED))
1741 return nvme_ns_has_pi(head);
1742
d386aedc 1743 switch (head->pi_type) {
1673f1f0 1744 case NVME_NS_DPS_PI_TYPE3:
d386aedc 1745 switch (head->guard_type) {
4020aad8
KB		 1746 case NVME_NVM_NS_16B_GUARD:
1747 integrity.profile = &t10_pi_type3_crc;
1748 integrity.tag_size = sizeof(u16) + sizeof(u32);
1749 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1750 break;
1751 case NVME_NVM_NS_64B_GUARD:
1752 integrity.profile = &ext_pi_type3_crc64;
1753 integrity.tag_size = sizeof(u16) + 6;
1754 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1755 break;
1756 default:
1757 integrity.profile = NULL;
1758 break;
1759 }
1673f1f0
CH		 1760 break;
1761 case NVME_NS_DPS_PI_TYPE1:
1762 case NVME_NS_DPS_PI_TYPE2:
d386aedc 1763 switch (head->guard_type) {
4020aad8
KB		 1764 case NVME_NVM_NS_16B_GUARD:
1765 integrity.profile = &t10_pi_type1_crc;
1766 integrity.tag_size = sizeof(u16);
1767 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1768 break;
1769 case NVME_NVM_NS_64B_GUARD:
1770 integrity.profile = &ext_pi_type1_crc64;
1771 integrity.tag_size = sizeof(u16);
1772 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1773 break;
1774 default:
1775 integrity.profile = NULL;
1776 break;
1777 }
1673f1f0
CH		 1778 break;
1779 default:
1780 integrity.profile = NULL;
1781 break;
1782 }
4020aad8 1783
d386aedc 1784 integrity.tuple_size = head->ms;
921e81db 1785 integrity.pi_offset = head->pi_offset;
39b7baa4 1786 blk_integrity_register(disk, &integrity);
f467b48e 1787 return true;
1673f1f0 1788}
1673f1f0 1789
d386aedc
DW		 1790static void nvme_config_discard(struct nvme_ctrl *ctrl, struct gendisk *disk,
1791 struct nvme_ns_head *head)
1673f1f0 1792{
26318571 1793 struct request_queue *queue = disk->queue;
f29886c2 1794 u32 max_discard_sectors;
30e5e929 1795
f29886c2
CH		 1796 if (ctrl->dmrsl && ctrl->dmrsl <= nvme_sect_to_lba(head, UINT_MAX)) {
1797 max_discard_sectors = nvme_lba_to_sect(head, ctrl->dmrsl);
1798 } else if (ctrl->oncs & NVME_CTRL_ONCS_DSM) {
1799 max_discard_sectors = UINT_MAX;
1800 } else {
70200574 1801 blk_queue_max_discard_sectors(queue, 0);
3831761e
JA		 1802 return;
1803 }
1804
b35ba01e
CH		 1805 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1806 NVME_DSM_MAX_RANGES);
1807
d3074e9a
CH		 1808 /*
1809 * If discard is already enabled, don't reset queue limits.
1810 *
1811 * This works around the fact that the block layer can't cope well with
1812 * updating the hardware limits when overridden through sysfs. This is
1813 * harmless because discard limits in NVMe are purely advisory.
1814 */
70200574 1815 if (queue->limits.max_discard_sectors)
3831761e
JA		 1816 return;
1817
f29886c2 1818 blk_queue_max_discard_sectors(queue, max_discard_sectors);
3b946fe1
CH		 1819 if (ctrl->dmrl)
1820 blk_queue_max_discard_segments(queue, ctrl->dmrl);
1821 else
1822 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
a4be9679 1823 queue->limits.discard_granularity = queue_logical_block_size(queue);
1673f1f0
CH		 1824}
1825
002fab04
CH		 1826static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1827{
1828 return uuid_equal(&a->uuid, &b->uuid) &&
1829 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
71010c30
NC		 1830 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 &&
1831 a->csi == b->csi;
002fab04
CH		 1832}
1833
c6fce9f1
CH		 1834static int nvme_identify_ns_nvm(struct nvme_ctrl *ctrl, unsigned int nsid,
1835 struct nvme_id_ns_nvm **nvmp)
1836{
1837 struct nvme_command c = {
1838 .identify.opcode = nvme_admin_identify,
1839 .identify.nsid = cpu_to_le32(nsid),
1840 .identify.cns = NVME_ID_CNS_CS_NS,
1841 .identify.csi = NVME_CSI_NVM,
1842 };
1843 struct nvme_id_ns_nvm *nvm;
1844 int ret;
1845
1846 nvm = kzalloc(sizeof(*nvm), GFP_KERNEL);
1847 if (!nvm)
1848 return -ENOMEM;
1849
1850 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, nvm, sizeof(*nvm));
1851 if (ret)
1852 kfree(nvm);
1853 else
1854 *nvmp = nvm;
1855 return ret;
1856}
1857
27cb91a3 1858static void nvme_configure_pi_elbas(struct nvme_ns_head *head,
e5ea00a5 1859 struct nvme_id_ns *id, struct nvme_id_ns_nvm *nvm)
d4609ea8 1860{
27cb91a3 1861 u32 elbaf = le32_to_cpu(nvm->elbaf[nvme_lbaf_index(id->flbas)]);
4020aad8
KB		 1862
1863 /* no support for storage tag formats right now */
1864 if (nvme_elbaf_sts(elbaf))
27cb91a3 1865 return;
4020aad8 1866
d386aedc
DW		 1867 head->guard_type = nvme_elbaf_guard_type(elbaf);
1868 switch (head->guard_type) {
4020aad8 1869 case NVME_NVM_NS_64B_GUARD:
d386aedc 1870 head->pi_size = sizeof(struct crc64_pi_tuple);
4020aad8
KB		 1871 break;
1872 case NVME_NVM_NS_16B_GUARD:
d386aedc 1873 head->pi_size = sizeof(struct t10_pi_tuple);
4020aad8
KB		 1874 break;
1875 default:
1876 break;
1877 }
4020aad8
KB		 1878}
1879
e5ea00a5
CH		 1880static void nvme_configure_metadata(struct nvme_ctrl *ctrl,
1881 struct nvme_ns_head *head, struct nvme_id_ns *id,
1882 struct nvme_id_ns_nvm *nvm)
4020aad8 1883{
d386aedc 1884 head->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS);
27cb91a3
CH		 1885 head->pi_type = 0;
1886 head->pi_size = 0;
1887 head->pi_offset = 0;
1888 head->ms = le16_to_cpu(id->lbaf[nvme_lbaf_index(id->flbas)].ms);
d386aedc 1889 if (!head->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
e5ea00a5 1890 return;
363f6368 1891
27cb91a3
CH		 1892 if (nvm && (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)) {
1893 nvme_configure_pi_elbas(head, id, nvm);
1894 } else {
1895 head->pi_size = sizeof(struct t10_pi_tuple);
1896 head->guard_type = NVME_NVM_NS_16B_GUARD;
1897 }
1898
1899 if (head->pi_size && head->ms >= head->pi_size)
1900 head->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1901 if (!(id->dps & NVME_NS_DPS_PI_FIRST))
1902 head->pi_offset = head->ms - head->pi_size;
1903
d4609ea8
CH		 1904 if (ctrl->ops->flags & NVME_F_FABRICS) {
1905 /*
1906 * The NVMe over Fabrics specification only supports metadata as
1907 * part of the extended data LBA. We rely on HCA/HBA support to
1908 * remap the separate metadata buffer from the block layer.
1909 */
1910 if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT)))
e5ea00a5 1911 return;
d39ad2a4 1912
d386aedc 1913 head->features |= NVME_NS_EXT_LBAS;
d39ad2a4
KB		 1914
1915 /*
1916 * The current fabrics transport drivers support namespace
1917 * metadata formats only if nvme_ns_has_pi() returns true.
1918 * Suppress support for all other formats so the namespace will
1919 * have a 0 capacity and not be usable through the block stack.
1920 *
1921 * Note, this check will need to be modified if any drivers
1922 * gain the ability to use other metadata formats.
1923 */
d386aedc
DW		 1924 if (ctrl->max_integrity_segments && nvme_ns_has_pi(head))
1925 head->features |= NVME_NS_METADATA_SUPPORTED;
d4609ea8
CH		 1926 } else {
1927 /*
1928 * For PCIe controllers, we can't easily remap the separate
1929 * metadata buffer from the block layer and thus require a
1930 * separate metadata buffer for block layer metadata/PI support.
1931 * We allow extended LBAs for the passthrough interface, though.
1932 */
1933 if (id->flbas & NVME_NS_FLBAS_META_EXT)
d386aedc 1934 head->features |= NVME_NS_EXT_LBAS;
d4609ea8 1935 else
d386aedc 1936 head->features |= NVME_NS_METADATA_SUPPORTED;
d4609ea8 1937 }
d4609ea8
CH		 1938}
1939
152694c8
CH		 1940static u32 nvme_max_drv_segments(struct nvme_ctrl *ctrl)
1941{
1942 return ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> SECTOR_SHIFT) + 1;
1943}
1944
658d9f7c
CH		 1945static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1946 struct request_queue *q)
1947{
152694c8
CH		 1948 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
1949 blk_queue_max_segments(q, min_t(u32, USHRT_MAX,
1950 min_not_zero(nvme_max_drv_segments(ctrl), ctrl->max_segments)));
f404dd92 1951 blk_queue_max_integrity_segments(q, ctrl->max_integrity_segments);
658d9f7c 1952 blk_queue_virt_boundary(q, NVME_CTRL_PAGE_SIZE - 1);
52fde2c0 1953 blk_queue_dma_alignment(q, 3);
658d9f7c
CH		 1954}
1955
a5b1cd61 1956static bool nvme_update_disk_info(struct nvme_ns *ns, struct nvme_id_ns *id)
24b0b58c 1957{
a5b1cd61
CH		 1958 struct gendisk *disk = ns->disk;
1959 struct nvme_ns_head *head = ns->head;
d386aedc 1960 u32 bs = 1U << head->lba_shift;
68ab60ca 1961 u32 atomic_bs, phys_bs, io_opt = 0;
a5b1cd61 1962 bool valid = true;
24b0b58c 1963
13f0b26b
CH		 1964 /*
1965 * The block layer can't support LBA sizes larger than the page size
74fbc88e
KB		 1966 * or smaller than a sector size yet, so catch this early and don't
1967 * allow block I/O.
13f0b26b 1968 */
01d550f0 1969 if (head->lba_shift > PAGE_SHIFT || head->lba_shift < SECTOR_SHIFT) {
01fa0174 1970 bs = (1 << 9);
a5b1cd61 1971 valid = false;
01fa0174 1972 }
f9d5f457 1973
68ab60ca 1974 atomic_bs = phys_bs = bs;
81adb863
BVA		 1975 if (id->nabo == 0) {
1976 /*
1977 * Bit 1 indicates whether NAWUPF is defined for this namespace
1978 * and whether it should be used instead of AWUPF. If NAWUPF ==
1979 * 0 then AWUPF must be used instead.
1980 */
92decf11 1981 if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf)
81adb863
BVA		 1982 atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs;
1983 else
a5b1cd61 1984 atomic_bs = (1 + ns->ctrl->subsys->awupf) * bs;
81adb863 1985 }
31fdad7b 1986
92decf11 1987 if (id->nsfeat & NVME_NS_FEAT_IO_OPT) {
81adb863 1988 /* NPWG = Namespace Preferred Write Granularity */
31fdad7b 1989 phys_bs = bs * (1 + le16_to_cpu(id->npwg));
81adb863 1990 /* NOWS = Namespace Optimal Write Size */
31fdad7b 1991 io_opt = bs * (1 + le16_to_cpu(id->nows));
81adb863
BVA		 1992 }
1993
cee160fd 1994 blk_queue_logical_block_size(disk->queue, bs);
81adb863
BVA		 1995 /*
1996 * Linux filesystems assume writing a single physical block is
1997 * an atomic operation. Hence limit the physical block size to the
1998 * value of the Atomic Write Unit Power Fail parameter.
1999 */
2000 blk_queue_physical_block_size(disk->queue, min(phys_bs, atomic_bs));
2001 blk_queue_io_min(disk->queue, phys_bs);
2002 blk_queue_io_opt(disk->queue, io_opt);
cee160fd 2003
a5b1cd61 2004 nvme_config_discard(ns->ctrl, disk, head);
63dfa100 2005
a5b1cd61 2006 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
63dfa100
CH		 2007 blk_queue_max_write_zeroes_sectors(disk->queue, UINT_MAX);
2008 else
2009 blk_queue_max_write_zeroes_sectors(disk->queue,
a5b1cd61
CH		 2010 ns->ctrl->max_zeroes_sectors);
2011 return valid;
24b0b58c
CH		 2012}
2013
1e4ea66a
CH		 2014static bool nvme_ns_is_readonly(struct nvme_ns *ns, struct nvme_ns_info *info)
2015{
2016 return info->is_readonly || test_bit(NVME_NS_FORCE_RO, &ns->flags);
2017}
2018
e83d776f
KB		 2019static inline bool nvme_first_scan(struct gendisk *disk)
2020{
2021 /* nvme_alloc_ns() scans the disk prior to adding it */
50b4aecf 2022 return !disk_live(disk);
e83d776f
KB		 2023}
2024
2025static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id)
2026{
2027 struct nvme_ctrl *ctrl = ns->ctrl;
2028 u32 iob;
2029
2030 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
2031 is_power_of_2(ctrl->max_hw_sectors))
2032 iob = ctrl->max_hw_sectors;
2033 else
0372dd4e 2034 iob = nvme_lba_to_sect(ns->head, le16_to_cpu(id->noiob));
e83d776f
KB		 2035
2036 if (!iob)
2037 return;
2038
2039 if (!is_power_of_2(iob)) {
2040 if (nvme_first_scan(ns->disk))
2041 pr_warn("%s: ignoring unaligned IO boundary:%u\n",
2042 ns->disk->disk_name, iob);
2043 return;
2044 }
2045
2046 if (blk_queue_is_zoned(ns->disk->queue)) {
2047 if (nvme_first_scan(ns->disk))
2048 pr_warn("%s: ignoring zoned namespace IO boundary\n",
2049 ns->disk->disk_name);
2050 return;
2051 }
2052
2053 blk_queue_chunk_sectors(ns->queue, iob);
2054}
2055
eb867ee9
JG		 2056static int nvme_update_ns_info_generic(struct nvme_ns *ns,
2057 struct nvme_ns_info *info)
2058{
2059 blk_mq_freeze_queue(ns->disk->queue);
2060 nvme_set_queue_limits(ns->ctrl, ns->queue);
2061 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info));
2062 blk_mq_unfreeze_queue(ns->disk->queue);
2063
eb867ee9 2064 /* Hide the block-interface for these devices */
46e7422c 2065 return -ENODEV;
eb867ee9
JG		 2066}
2067
1a893c2b
CH		 2068static int nvme_update_ns_info_block(struct nvme_ns *ns,
2069 struct nvme_ns_info *info)
ac81bfa9 2070{
d60c23e4 2071 bool vwc = ns->ctrl->vwc & NVME_CTRL_VWC_PRESENT;
e5ea00a5 2072 struct nvme_id_ns_nvm *nvm = NULL;
1a893c2b 2073 struct nvme_id_ns *id;
a5b1cd61 2074 sector_t capacity;
1a893c2b 2075 unsigned lbaf;
240e6ee2 2076 int ret;
1673f1f0 2077
1a893c2b
CH		 2078 ret = nvme_identify_ns(ns->ctrl, info->nsid, &id);
2079 if (ret)
2080 return ret;
2081
d8b90d60
EM		 2082 if (id->ncap == 0) {
2083 /* namespace not allocated or attached */
2084 info->is_removed = true;
2085 ret = -ENODEV;
46e7422c 2086 goto out;
d8b90d60
EM		 2087 }
2088
e5ea00a5
CH		 2089 if (ns->ctrl->ctratt & NVME_CTRL_ATTR_ELBAS) {
2090 ret = nvme_identify_ns_nvm(ns->ctrl, info->nsid, &nvm);
2091 if (ret < 0)
2092 goto out;
2093 }
2094
f9d5f457 2095 blk_mq_freeze_queue(ns->disk->queue);
1a893c2b 2096 lbaf = nvme_lbaf_index(id->flbas);
9419e71b 2097 ns->head->lba_shift = id->lbaf[lbaf].ds;
a1a825ab 2098 ns->head->nuse = le64_to_cpu(id->nuse);
a5b1cd61
CH		 2099 capacity = nvme_lba_to_sect(ns->head, le64_to_cpu(id->nsze));
2100
8b7c0ff2 2101 nvme_set_queue_limits(ns->ctrl, ns->queue);
e5ea00a5 2102 nvme_configure_metadata(ns->ctrl, ns->head, id, nvm);
73d90386 2103 nvme_set_chunk_sectors(ns, id);
a5b1cd61
CH		 2104 if (!nvme_update_disk_info(ns, id))
2105 capacity = 0;
2106
2107 /*
2108 * Register a metadata profile for PI, or the plain non-integrity NVMe
2109 * metadata masquerading as Type 0 if supported, otherwise reject block
2110 * I/O to namespaces with metadata except when the namespace supports
2111 * PI, as it can strip/insert in that case.
2112 */
2113 if (!nvme_init_integrity(ns->disk, ns->head))
2114 capacity = 0;
2115
2116 set_capacity_and_notify(ns->disk, capacity);
73d90386 2117
8b7c0ff2 2118 if (ns->head->ids.csi == NVME_CSI_ZNS) {
d525c3c0 2119 ret = nvme_update_zone_info(ns, lbaf);
e06b425b
CH		 2120 if (ret) {
2121 blk_mq_unfreeze_queue(ns->disk->queue);
2122 goto out;
2123 }
71010c30
NC		 2124 }
2125
1b96f862
CH		 2126 /*
2127 * Only set the DEAC bit if the device guarantees that reads from
2128 * deallocated data return zeroes. While the DEAC bit does not
2129 * require that, it must be a no-op if reads from deallocated data
2130 * do not return zeroes.
2131 */
2132 if ((id->dlfeat & 0x7) == 0x1 && (id->dlfeat & (1 << 3)))
9419e71b 2133 ns->head->features |= NVME_NS_DEAC;
1e4ea66a 2134 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info));
d60c23e4 2135 blk_queue_write_cache(ns->disk->queue, vwc, vwc);
e7d65803 2136 set_bit(NVME_NS_READY, &ns->flags);
f9d5f457 2137 blk_mq_unfreeze_queue(ns->disk->queue);
1673f1f0 2138
3a9967ba 2139 if (blk_queue_is_zoned(ns->queue)) {
1b2f5d5d 2140 ret = blk_revalidate_disk_zones(ns->disk, NULL);
8685699c 2141 if (ret && !nvme_first_scan(ns->disk))
e06b425b 2142 goto out;
b29f8485
MG		 2143 }
2144
e06b425b
CH		 2145 ret = 0;
2146out:
e5ea00a5 2147 kfree(nvm);
1a893c2b 2148 kfree(id);
240e6ee2
KB		 2149 return ret;
2150}
2151
1a893c2b
CH		 2152static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_ns_info *info)
2153{
46e7422c
CH		 2154 bool unsupported = false;
2155 int ret;
2156
1a893c2b
CH		 2157 switch (info->ids.csi) {
2158 case NVME_CSI_ZNS:
2159 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
eb867ee9
JG		 2160 dev_info(ns->ctrl->device,
2161 "block device for nsid %u not supported without CONFIG_BLK_DEV_ZONED\n",
1a893c2b 2162 info->nsid);
46e7422c
CH		 2163 ret = nvme_update_ns_info_generic(ns, info);
2164 break;
1a893c2b 2165 }
46e7422c
CH		 2166 ret = nvme_update_ns_info_block(ns, info);
2167 break;
1a893c2b 2168 case NVME_CSI_NVM:
46e7422c
CH		 2169 ret = nvme_update_ns_info_block(ns, info);
2170 break;
1a893c2b 2171 default:
eb867ee9
JG		 2172 dev_info(ns->ctrl->device,
2173 "block device for nsid %u not supported (csi %u)\n",
2174 info->nsid, info->ids.csi);
46e7422c
CH		 2175 ret = nvme_update_ns_info_generic(ns, info);
2176 break;
2177 }
2178
2179 /*
2180 * If probing fails due an unsupported feature, hide the block device,
2181 * but still allow other access.
2182 */
2183 if (ret == -ENODEV) {
2184 ns->disk->flags |= GENHD_FL_HIDDEN;
2185 set_bit(NVME_NS_READY, &ns->flags);
2186 unsupported = true;
2187 ret = 0;
2188 }
2189
2190 if (!ret && nvme_ns_head_multipath(ns->head)) {
2191 blk_mq_freeze_queue(ns->head->disk->queue);
2192 if (unsupported)
2193 ns->head->disk->flags |= GENHD_FL_HIDDEN;
2194 else
2195 nvme_init_integrity(ns->head->disk, ns->head);
2196 set_capacity_and_notify(ns->head->disk, get_capacity(ns->disk));
2197 set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info));
2198 nvme_mpath_revalidate_paths(ns);
2199 blk_stack_limits(&ns->head->disk->queue->limits,
2200 &ns->queue->limits, 0);
2201
2202 disk_update_readahead(ns->head->disk);
2203 blk_mq_unfreeze_queue(ns->head->disk->queue);
1a893c2b 2204 }
46e7422c
CH		 2205
2206 return ret;
1a893c2b
CH		 2207}
2208
a98e58e5 2209#ifdef CONFIG_BLK_SED_OPAL
94cc781f 2210static int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
4f1244c8 2211 bool send)
a98e58e5 2212{
4f1244c8 2213 struct nvme_ctrl *ctrl = data;
cc72c442 2214 struct nvme_command cmd = { };
a98e58e5 2215
a98e58e5
SB		 2216 if (send)
2217 cmd.common.opcode = nvme_admin_security_send;
2218 else
2219 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 2220 cmd.common.nsid = 0;
b7c8f366
CK		 2221 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
2222 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5 2223
6b46fa02 2224 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
bd2687f2 2225 NVME_QID_ANY, NVME_SUBMIT_AT_HEAD);
a98e58e5 2226}
94cc781f
CH		 2227
2228static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended)
2229{
2230 if (ctrl->oacs & NVME_CTRL_OACS_SEC_SUPP) {
2231 if (!ctrl->opal_dev)
2232 ctrl->opal_dev = init_opal_dev(ctrl, &nvme_sec_submit);
2233 else if (was_suspended)
2234 opal_unlock_from_suspend(ctrl->opal_dev);
2235 } else {
2236 free_opal_dev(ctrl->opal_dev);
2237 ctrl->opal_dev = NULL;
2238 }
2239}
2240#else
2241static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended)
2242{
2243}
a98e58e5
SB		 2244#endif /* CONFIG_BLK_SED_OPAL */
2245
8b4fb0f9
CH		 2246#ifdef CONFIG_BLK_DEV_ZONED
2247static int nvme_report_zones(struct gendisk *disk, sector_t sector,
2248 unsigned int nr_zones, report_zones_cb cb, void *data)
2249{
2250 return nvme_ns_report_zones(disk->private_data, sector, nr_zones, cb,
2251 data);
2252}
2253#else
2254#define nvme_report_zones NULL
2255#endif /* CONFIG_BLK_DEV_ZONED */
2256
942e21c0 2257const struct block_device_operations nvme_bdev_ops = {
1673f1f0
CH		 2258 .owner = THIS_MODULE,
2259 .ioctl = nvme_ioctl,
a25d4261 2260 .compat_ioctl = blkdev_compat_ptr_ioctl,
1673f1f0
CH		 2261 .open = nvme_open,
2262 .release = nvme_release,
2263 .getgeo = nvme_getgeo,
240e6ee2 2264 .report_zones = nvme_report_zones,
1673f1f0
CH		 2265 .pr_ops = &nvme_pr_ops,
2266};
2267
e6d275de
CH		 2268static int nvme_wait_ready(struct nvme_ctrl *ctrl, u32 mask, u32 val,
2269 u32 timeout, const char *op)
5fd4ce1b 2270{
e6d275de
CH		 2271 unsigned long timeout_jiffies = jiffies + timeout * HZ;
2272 u32 csts;
5fd4ce1b
CH		 2273 int ret;
2274
2275 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 2276 if (csts == ~0)
2277 return -ENODEV;
e6d275de 2278 if ((csts & mask) == val)
5fd4ce1b
CH		 2279 break;
2280
3e98c244 2281 usleep_range(1000, 2000);
5fd4ce1b
CH		 2282 if (fatal_signal_pending(current))
2283 return -EINTR;
354201c5 2284 if (time_after(jiffies, timeout_jiffies)) {
1b3c47c1 2285 dev_err(ctrl->device,
94d2e705 2286 "Device not ready; aborting %s, CSTS=0x%x\n",
e6d275de 2287 op, csts);
5fd4ce1b
CH		 2288 return -ENODEV;
2289 }
2290 }
2291
2292 return ret;
2293}
2294
285b6e9b 2295int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown)
5fd4ce1b
CH		 2296{
2297 int ret;
2298
2299 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
285b6e9b
CH		 2300 if (shutdown)
2301 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
2302 else
2303 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
5fd4ce1b
CH		 2304
2305 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2306 if (ret)
2307 return ret;
54adc010 2308
285b6e9b
CH		 2309 if (shutdown) {
2310 return nvme_wait_ready(ctrl, NVME_CSTS_SHST_MASK,
2311 NVME_CSTS_SHST_CMPLT,
2312 ctrl->shutdown_timeout, "shutdown");
2313 }
b5a10c5f 2314 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010 2315 msleep(NVME_QUIRK_DELAY_AMOUNT);
e6d275de
CH		 2316 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, 0,
2317 (NVME_CAP_TIMEOUT(ctrl->cap) + 1) / 2, "reset");
5fd4ce1b 2318}
576d55d6 2319EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b 2320
c0f2f45b 2321int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
5fd4ce1b 2322{
6c3c05b0 2323 unsigned dev_page_min;
354201c5 2324 u32 timeout;
5fd4ce1b
CH		 2325 int ret;
2326
c0f2f45b
SG		 2327 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2328 if (ret) {
2329 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
2330 return ret;
2331 }
2332 dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12;
2333
6c3c05b0 2334 if (NVME_CTRL_PAGE_SHIFT < dev_page_min) {
1b3c47c1 2335 dev_err(ctrl->device,
5fd4ce1b 2336 "Minimum device page size %u too large for host (%u)\n",
6c3c05b0 2337 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT);
5fd4ce1b
CH		 2338 return -ENODEV;
2339 }
2340
71010c30
NC		 2341 if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI)
2342 ctrl->ctrl_config = NVME_CC_CSS_CSI;
2343 else
2344 ctrl->ctrl_config = NVME_CC_CSS_NVM;
354201c5 2345
6cc834ba
KB		 2346 if (ctrl->cap & NVME_CAP_CRMS_CRWMS && ctrl->cap & NVME_CAP_CRMS_CRIMS)
2347 ctrl->ctrl_config |= NVME_CC_CRIME;
354201c5 2348
6c3c05b0 2349 ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
60b43f62 2350 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b 2351 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
aa41d2fe
NC		 2352 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2353 if (ret)
2354 return ret;
5fd4ce1b 2355
aa41d2fe
NC		 2356 /* Flush write to device (required if transport is PCI) */
2357 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);
2358 if (ret)
2359 return ret;
2360
6cc834ba
KB		 2361 /* CAP value may change after initial CC write */
2362 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2363 if (ret)
2364 return ret;
2365
2366 timeout = NVME_CAP_TIMEOUT(ctrl->cap);
2367 if (ctrl->cap & NVME_CAP_CRMS_CRWMS) {
2368 u32 crto, ready_timeout;
2369
2370 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CRTO, &crto);
2371 if (ret) {
2372 dev_err(ctrl->device, "Reading CRTO failed (%d)\n",
2373 ret);
2374 return ret;
2375 }
2376
2377 /*
2378 * CRTO should always be greater or equal to CAP.TO, but some
2379 * devices are known to get this wrong. Use the larger of the
2380 * two values.
2381 */
2382 if (ctrl->ctrl_config & NVME_CC_CRIME)
2383 ready_timeout = NVME_CRTO_CRIMT(crto);
2384 else
2385 ready_timeout = NVME_CRTO_CRWMT(crto);
2386
2387 if (ready_timeout < timeout)
2388 dev_warn_once(ctrl->device, "bad crto:%x cap:%llx\n",
2389 crto, ctrl->cap);
2390 else
2391 timeout = ready_timeout;
2392 }
2393
aa41d2fe 2394 ctrl->ctrl_config |= NVME_CC_ENABLE;
5fd4ce1b
CH		 2395 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2396 if (ret)
2397 return ret;
e6d275de
CH		 2398 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY,
2399 (timeout + 1) / 2, "initialisation");
5fd4ce1b 2400}
576d55d6 2401EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b 2402
dbf86b39
JD		 2403static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
2404{
2405 __le64 ts;
2406 int ret;
2407
2408 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
2409 return 0;
2410
2411 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
2412 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
2413 NULL);
2414 if (ret)
2415 dev_warn_once(ctrl->device,
2416 "could not set timestamp (%d)\n", ret);
2417 return ret;
2418}
2419
4020aad8 2420static int nvme_configure_host_options(struct nvme_ctrl *ctrl)
49cd84b6
KB		 2421{
2422 struct nvme_feat_host_behavior *host;
4020aad8 2423 u8 acre = 0, lbafee = 0;
49cd84b6
KB		 2424 int ret;
2425
2426 /* Don't bother enabling the feature if retry delay is not reported */
4020aad8
KB		 2427 if (ctrl->crdt[0])
2428 acre = NVME_ENABLE_ACRE;
2429 if (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)
2430 lbafee = NVME_ENABLE_LBAFEE;
2431
2432 if (!acre && !lbafee)
49cd84b6
KB		 2433 return 0;
2434
2435 host = kzalloc(sizeof(*host), GFP_KERNEL);
2436 if (!host)
2437 return 0;
2438
4020aad8
KB		 2439 host->acre = acre;
2440 host->lbafee = lbafee;
49cd84b6
KB		 2441 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2442 host, sizeof(*host), NULL);
2443 kfree(host);
2444 return ret;
2445}
2446
ebd8a93a
AB		 2447/*
2448 * The function checks whether the given total (exlat + enlat) latency of
2449 * a power state allows the latter to be used as an APST transition target.
2450 * It does so by comparing the latency to the primary and secondary latency
2451 * tolerances defined by module params. If there's a match, the corresponding
2452 * timeout value is returned and the matching tolerance index (1 or 2) is
2453 * reported.
2454 */
2455static bool nvme_apst_get_transition_time(u64 total_latency,
2456 u64 *transition_time, unsigned *last_index)
2457{
2458 if (total_latency <= apst_primary_latency_tol_us) {
2459 if (*last_index == 1)
2460 return false;
2461 *last_index = 1;
2462 *transition_time = apst_primary_timeout_ms;
2463 return true;
2464 }
2465 if (apst_secondary_timeout_ms &&
2466 total_latency <= apst_secondary_latency_tol_us) {
2467 if (*last_index <= 2)
2468 return false;
2469 *last_index = 2;
2470 *transition_time = apst_secondary_timeout_ms;
2471 return true;
2472 }
2473 return false;
2474}
2475
60df5de9
CH		 2476/*
2477 * APST (Autonomous Power State Transition) lets us program a table of power
2478 * state transitions that the controller will perform automatically.
ebd8a93a
AB		 2479 *
2480 * Depending on module params, one of the two supported techniques will be used:
2481 *
2482 * - If the parameters provide explicit timeouts and tolerances, they will be
2483 * used to build a table with up to 2 non-operational states to transition to.
2484 * The default parameter values were selected based on the values used by
2485 * Microsoft's and Intel's NVMe drivers. Yet, since we don't implement dynamic
2486 * regeneration of the APST table in the event of switching between external
2487 * and battery power, the timeouts and tolerances reflect a compromise
2488 * between values used by Microsoft for AC and battery scenarios.
2489 * - If not, we'll configure the table with a simple heuristic: we are willing
2490 * to spend at most 2% of the time transitioning between power states.
2491 * Therefore, when running in any given state, we will enter the next
2492 * lower-power non-operational state after waiting 50 * (enlat + exlat)
2493 * microseconds, as long as that state's exit latency is under the requested
2494 * maximum latency.
60df5de9
CH		 2495 *
2496 * We will not autonomously enter any non-operational state for which the total
2497 * latency exceeds ps_max_latency_us.
2498 *
2499 * Users can set ps_max_latency_us to zero to turn off APST.
2500 */
634b8325 2501static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde 2502{
c5552fde 2503 struct nvme_feat_auto_pst *table;
60df5de9 2504 unsigned apste = 0;
fb0dc399 2505 u64 max_lat_us = 0;
60df5de9 2506 __le64 target = 0;
fb0dc399 2507 int max_ps = -1;
60df5de9 2508 int state;
c5552fde 2509 int ret;
ebd8a93a 2510 unsigned last_lt_index = UINT_MAX;
c5552fde
AL		 2511
2512 /*
2513 * If APST isn't supported or if we haven't been initialized yet,
2514 * then don't do anything.
2515 */
2516 if (!ctrl->apsta)
634b8325 2517 return 0;
c5552fde
AL		 2518
2519 if (ctrl->npss > 31) {
2520 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2521 return 0;
c5552fde
AL		 2522 }
2523
2524 table = kzalloc(sizeof(*table), GFP_KERNEL);
2525 if (!table)
634b8325 2526 return 0;
c5552fde 2527
76a5af84 2528 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde 2529 /* Turn off APST. */
fb0dc399 2530 dev_dbg(ctrl->device, "APST disabled\n");
60df5de9
CH		 2531 goto done;
2532 }
c5552fde 2533
60df5de9
CH		 2534 /*
2535 * Walk through all states from lowest- to highest-power.
2536 * According to the spec, lower-numbered states use more power. NPSS,
2537 * despite the name, is the index of the lowest-power state, not the
2538 * number of states.
2539 */
2540 for (state = (int)ctrl->npss; state >= 0; state--) {
2541 u64 total_latency_us, exit_latency_us, transition_ms;
da87591b 2542
60df5de9
CH		 2543 if (target)
2544 table->entries[state] = target;
c5552fde 2545
c5552fde 2546 /*
60df5de9
CH		 2547 * Don't allow transitions to the deepest state if it's quirked
2548 * off.
c5552fde 2549 */
60df5de9
CH		 2550 if (state == ctrl->npss &&
2551 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2552 continue;
fb0dc399 2553
60df5de9
CH		 2554 /*
2555 * Is this state a useful non-operational state for higher-power
2556 * states to autonomously transition to?
2557 */
2558 if (!(ctrl->psd[state].flags & NVME_PS_FLAGS_NON_OP_STATE))
2559 continue;
fb0dc399 2560
60df5de9
CH		 2561 exit_latency_us = (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2562 if (exit_latency_us > ctrl->ps_max_latency_us)
2563 continue;
c5552fde 2564
60df5de9
CH		 2565 total_latency_us = exit_latency_us +
2566 le32_to_cpu(ctrl->psd[state].entry_lat);
fb0dc399 2567
60df5de9 2568 /*
ebd8a93a
AB		 2569 * This state is good. It can be used as the APST idle target
2570 * for higher power states.
60df5de9 2571 */
ebd8a93a
AB		 2572 if (apst_primary_timeout_ms && apst_primary_latency_tol_us) {
2573 if (!nvme_apst_get_transition_time(total_latency_us,
2574 &transition_ms, &last_lt_index))
2575 continue;
2576 } else {
2577 transition_ms = total_latency_us + 19;
2578 do_div(transition_ms, 20);
2579 if (transition_ms > (1 << 24) - 1)
2580 transition_ms = (1 << 24) - 1;
2581 }
60df5de9
CH		 2582
2583 target = cpu_to_le64((state << 3) | (transition_ms << 8));
2584 if (max_ps == -1)
2585 max_ps = state;
2586 if (total_latency_us > max_lat_us)
2587 max_lat_us = total_latency_us;
c5552fde
AL		 2588 }
2589
60df5de9
CH		 2590 if (max_ps == -1)
2591 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2592 else
2593 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2594 max_ps, max_lat_us, (int)sizeof(*table), table);
2595 apste = 1;
2596
2597done:
c5552fde
AL		 2598 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2599 table, sizeof(*table), NULL);
2600 if (ret)
2601 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
c5552fde 2602 kfree(table);
634b8325 2603 return ret;
c5552fde
AL		 2604}
2605
2606static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2607{
2608 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2609 u64 latency;
2610
2611 switch (val) {
2612 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2613 case PM_QOS_LATENCY_ANY:
2614 latency = U64_MAX;
2615 break;
2616
2617 default:
2618 latency = val;
2619 }
2620
2621 if (ctrl->ps_max_latency_us != latency) {
2622 ctrl->ps_max_latency_us = latency;
e6e7f7ac 2623 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE)
53fe2a30 2624 nvme_configure_apst(ctrl);
c5552fde
AL		 2625 }
2626}
2627
bd4da3ab
AL		 2628struct nvme_core_quirk_entry {
2629 /*
2630 * NVMe model and firmware strings are padded with spaces. For
2631 * simplicity, strings in the quirk table are padded with NULLs
2632 * instead.
2633 */
2634 u16 vid;
2635 const char *mn;
2636 const char *fr;
2637 unsigned long quirks;
2638};
2639
2640static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2641 {
be56945c
AL		 2642 /*
2643 * This Toshiba device seems to die using any APST states. See:
2644 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2645 */
2646 .vid = 0x1179,
2647 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2648 .quirks = NVME_QUIRK_NO_APST,
cb32de1b
ML		 2649 },
2650 {
2651 /*
2652 * This LiteON CL1-3D*-Q11 firmware version has a race
2653 * condition associated with actions related to suspend to idle
2654 * LiteON has resolved the problem in future firmware
2655 */
2656 .vid = 0x14a4,
2657 .fr = "22301111",
2658 .quirks = NVME_QUIRK_SIMPLE_SUSPEND,
5a6254d5
EM		 2659 },
2660 {
2661 /*
2662 * This Kioxia CD6-V Series / HPE PE8030 device times out and
2663 * aborts I/O during any load, but more easily reproducible
2664 * with discards (fstrim).
2665 *
2666 * The device is left in a state where it is also not possible
2667 * to use "nvme set-feature" to disable APST, but booting with
2668 * nvme_core.default_ps_max_latency=0 works.
2669 */
2670 .vid = 0x1e0f,
2671 .mn = "KCD6XVUL6T40",
2672 .quirks = NVME_QUIRK_NO_APST,
e6487833
CH		 2673 },
2674 {
2675 /*
2676 * The external Samsung X5 SSD fails initialization without a
2677 * delay before checking if it is ready and has a whole set of
2678 * other problems. To make this even more interesting, it
2679 * shares the PCI ID with internal Samsung 970 Evo Plus that
2680 * does not need or want these quirks.
2681 */
2682 .vid = 0x144d,
2683 .mn = "Samsung Portable SSD X5",
2684 .quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
2685 NVME_QUIRK_NO_DEEPEST_PS |
2686 NVME_QUIRK_IGNORE_DEV_SUBNQN,
be56945c 2687 }
bd4da3ab
AL		 2688};
2689
2690/* match is null-terminated but idstr is space-padded. */
2691static bool string_matches(const char *idstr, const char *match, size_t len)
2692{
2693 size_t matchlen;
2694
2695 if (!match)
2696 return true;
2697
2698 matchlen = strlen(match);
2699 WARN_ON_ONCE(matchlen > len);
2700
2701 if (memcmp(idstr, match, matchlen))
2702 return false;
2703
2704 for (; matchlen < len; matchlen++)
2705 if (idstr[matchlen] != ' ')
2706 return false;
2707
2708 return true;
2709}
2710
2711static bool quirk_matches(const struct nvme_id_ctrl *id,
2712 const struct nvme_core_quirk_entry *q)
2713{
2714 return q->vid == le16_to_cpu(id->vid) &&
2715 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2716 string_matches(id->fr, q->fr, sizeof(id->fr));
2717}
2718
ab9e00cc
CH		 2719static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2720 struct nvme_id_ctrl *id)
180de007
CH		 2721{
2722 size_t nqnlen;
2723 int off;
2724
6299358d
JD		 2725 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2726 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2727 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
a8817cc0 2728 strscpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
6299358d
JD		 2729 return;
2730 }
180de007 2731
6299358d
JD		 2732 if (ctrl->vs >= NVME_VS(1, 2, 1))
2733 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2734 }
180de007 2735
1abc6961
LB		 2736 /*
2737 * Generate a "fake" NQN similar to the one in Section 4.5 of the NVMe
2738 * Base Specification 2.0. It is slightly different from the format
2739 * specified there due to historic reasons, and we can't change it now.
2740 */
ab9e00cc 2741 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2742 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2743 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2744 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2745 off += sizeof(id->sn);
ab9e00cc 2746 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2747 off += sizeof(id->mn);
ab9e00cc
CH		 2748 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2749}
2750
e654dfd3 2751static void nvme_release_subsystem(struct device *dev)
ab9e00cc 2752{
e654dfd3
LG		 2753 struct nvme_subsystem *subsys =
2754 container_of(dev, struct nvme_subsystem, dev);
2755
733e4b69 2756 if (subsys->instance >= 0)
8b850475 2757 ida_free(&nvme_instance_ida, subsys->instance);
ab9e00cc
CH		 2758 kfree(subsys);
2759}
2760
ab9e00cc
CH		 2761static void nvme_destroy_subsystem(struct kref *ref)
2762{
2763 struct nvme_subsystem *subsys =
2764 container_of(ref, struct nvme_subsystem, ref);
2765
2766 mutex_lock(&nvme_subsystems_lock);
2767 list_del(&subsys->entry);
2768 mutex_unlock(&nvme_subsystems_lock);
2769
ed754e5d 2770 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2771 device_del(&subsys->dev);
2772 put_device(&subsys->dev);
2773}
2774
2775static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2776{
2777 kref_put(&subsys->ref, nvme_destroy_subsystem);
2778}
2779
2780static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2781{
2782 struct nvme_subsystem *subsys;
2783
2784 lockdep_assert_held(&nvme_subsystems_lock);
2785
c26aa572
JS		 2786 /*
2787 * Fail matches for discovery subsystems. This results
2788 * in each discovery controller bound to a unique subsystem.
2789 * This avoids issues with validating controller values
2790 * that can only be true when there is a single unique subsystem.
2791 * There may be multiple and completely independent entities
2792 * that provide discovery controllers.
2793 */
2794 if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME))
2795 return NULL;
2796
ab9e00cc
CH		 2797 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2798 if (strcmp(subsys->subnqn, subsysnqn))
2799 continue;
2800 if (!kref_get_unless_zero(&subsys->ref))
2801 continue;
2802 return subsys;
2803 }
2804
2805 return NULL;
2806}
2807
5ab25a32
SG		 2808static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl)
2809{
2810 return ctrl->opts && ctrl->opts->discovery_nqn;
2811}
2812
1b1031ca
CH		 2813static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
2814 struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
b837b283 2815{
1b1031ca 2816 struct nvme_ctrl *tmp;
b837b283 2817
32fd90c4
CH		 2818 lockdep_assert_held(&nvme_subsystems_lock);
2819
1b1031ca 2820 list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) {
e7c43fea 2821 if (nvme_state_terminal(tmp))
1b1031ca
CH		 2822 continue;
2823
2824 if (tmp->cntlid == ctrl->cntlid) {
2825 dev_err(ctrl->device,
16cc33b2
KB		 2826 "Duplicate cntlid %u with %s, subsys %s, rejecting\n",
2827 ctrl->cntlid, dev_name(tmp->device),
2828 subsys->subnqn);
1b1031ca
CH		 2829 return false;
2830 }
b837b283 2831
92decf11 2832 if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) ||
5ab25a32 2833 nvme_discovery_ctrl(ctrl))
1b1031ca
CH		 2834 continue;
2835
2836 dev_err(ctrl->device,
2837 "Subsystem does not support multiple controllers\n");
2838 return false;
b837b283 2839 }
b837b283 2840
1b1031ca 2841 return true;
b837b283
IR		 2842}
2843
ab9e00cc
CH		 2844static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2845{
2846 struct nvme_subsystem *subsys, *found;
2847 int ret;
2848
2849 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2850 if (!subsys)
2851 return -ENOMEM;
733e4b69
KB		 2852
2853 subsys->instance = -1;
ab9e00cc
CH		 2854 mutex_init(&subsys->lock);
2855 kref_init(&subsys->ref);
2856 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2857 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2858 nvme_init_subnqn(subsys, ctrl, id);
2859 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2860 memcpy(subsys->model, id->mn, sizeof(subsys->model));
ab9e00cc
CH		 2861 subsys->vendor_id = le16_to_cpu(id->vid);
2862 subsys->cmic = id->cmic;
954ae166
HR		 2863
2864 /* Versions prior to 1.4 don't necessarily report a valid type */
2865 if (id->cntrltype == NVME_CTRL_DISC ||
2866 !strcmp(subsys->subnqn, NVME_DISC_SUBSYS_NAME))
2867 subsys->subtype = NVME_NQN_DISC;
2868 else
2869 subsys->subtype = NVME_NQN_NVME;
2870
20e8b689
HR		 2871 if (nvme_discovery_ctrl(ctrl) && subsys->subtype != NVME_NQN_DISC) {
2872 dev_err(ctrl->device,
2873 "Subsystem %s is not a discovery controller",
2874 subsys->subnqn);
2875 kfree(subsys);
2876 return -EINVAL;
2877 }
81adb863 2878 subsys->awupf = le16_to_cpu(id->awupf);
e3d34794 2879 nvme_mpath_default_iopolicy(subsys);
ab9e00cc
CH		 2880
2881 subsys->dev.class = nvme_subsys_class;
2882 subsys->dev.release = nvme_release_subsystem;
1e496938 2883 subsys->dev.groups = nvme_subsys_attrs_groups;
733e4b69 2884 dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance);
ab9e00cc
CH		 2885 device_initialize(&subsys->dev);
2886
2887 mutex_lock(&nvme_subsystems_lock);
2888 found = __nvme_find_get_subsystem(subsys->subnqn);
2889 if (found) {
e654dfd3 2890 put_device(&subsys->dev);
ab9e00cc 2891 subsys = found;
32fd90c4 2892
1b1031ca 2893 if (!nvme_validate_cntlid(subsys, ctrl, id)) {
ab9e00cc 2894 ret = -EINVAL;
32fd90c4 2895 goto out_put_subsystem;
ab9e00cc 2896 }
ab9e00cc
CH		 2897 } else {
2898 ret = device_add(&subsys->dev);
2899 if (ret) {
2900 dev_err(ctrl->device,
2901 "failed to register subsystem device.\n");
8c36e66f 2902 put_device(&subsys->dev);
ab9e00cc
CH		 2903 goto out_unlock;
2904 }
ed754e5d 2905 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2906 list_add_tail(&subsys->entry, &nvme_subsystems);
2907 }
2908
bc4f6e06
DC		 2909 ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2910 dev_name(ctrl->device));
2911 if (ret) {
ab9e00cc
CH		 2912 dev_err(ctrl->device,
2913 "failed to create sysfs link from subsystem.\n");
32fd90c4 2914 goto out_put_subsystem;
ab9e00cc
CH		 2915 }
2916
733e4b69
KB		 2917 if (!found)
2918 subsys->instance = ctrl->instance;
32fd90c4 2919 ctrl->subsys = subsys;
ab9e00cc 2920 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
32fd90c4 2921 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc
CH		 2922 return 0;
2923
32fd90c4
CH		 2924out_put_subsystem:
2925 nvme_put_subsystem(subsys);
ab9e00cc
CH		 2926out_unlock:
2927 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 2928 return ret;
180de007
CH		 2929}
2930
be93e87e 2931int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
0e98719b 2932 void *log, size_t size, u64 offset)
c627c487
KB		 2933{
2934 struct nvme_command c = { };
71fb90eb 2935 u32 dwlen = nvme_bytes_to_numd(size);
70da6094
MB		 2936
2937 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2938 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2939 c.get_log_page.lid = log_page;
0e98719b 2940 c.get_log_page.lsp = lsp;
70da6094
MB		 2941 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2942 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2943 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2944 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
be93e87e 2945 c.get_log_page.csi = csi;
c627c487
KB		 2946
2947 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2948}
2949
be93e87e
KB		 2950static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi,
2951 struct nvme_effects_log **log)
84fef62d 2952{
f6224b86 2953 struct nvme_effects_log *cel = xa_load(&ctrl->cels, csi);
84fef62d
KB		 2954 int ret;
2955
be93e87e
KB		 2956 if (cel)
2957 goto out;
84fef62d 2958
be93e87e
KB		 2959 cel = kzalloc(sizeof(*cel), GFP_KERNEL);
2960 if (!cel)
2961 return -ENOMEM;
84fef62d 2962
46d2613e 2963 ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi,
f6224b86 2964 cel, sizeof(*cel), 0);
84fef62d 2965 if (ret) {
be93e87e
KB		 2966 kfree(cel);
2967 return ret;
84fef62d 2968 }
be93e87e 2969
f6224b86 2970 xa_store(&ctrl->cels, csi, cel, GFP_KERNEL);
be93e87e 2971out:
f6224b86 2972 *log = cel;
be93e87e 2973 return 0;
180de007
CH		 2974}
2975
5befc7c2 2976static inline u32 nvme_mps_to_sectors(struct nvme_ctrl *ctrl, u32 units)
7fd8930f 2977{
8609c63f 2978 u32 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12, val;
7fd8930f 2979
8609c63f
BVA		 2980 if (check_shl_overflow(1U, units + page_shift - 9, &val))
2981 return UINT_MAX;
2982 return val;
5befc7c2
KB		 2983}
2984
2985static int nvme_init_non_mdts_limits(struct nvme_ctrl *ctrl)
2986{
2987 struct nvme_command c = { };
2988 struct nvme_id_ctrl_nvm *id;
2989 int ret;
2990
5befc7c2
KB		 2991 /*
2992 * Even though NVMe spec explicitly states that MDTS is not applicable
2993 * to the write-zeroes, we are cautious and limit the size to the
2994 * controllers max_hw_sectors value, which is based on the MDTS field
2995 * and possibly other limiting factors.
2996 */
2997 if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) &&
2998 !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES))
2999 ctrl->max_zeroes_sectors = ctrl->max_hw_sectors;
3000 else
3001 ctrl->max_zeroes_sectors = 0;
3002
def84ab6 3003 if (ctrl->subsys->subtype != NVME_NQN_NVME ||
c917dd96
KB		 3004 nvme_ctrl_limited_cns(ctrl) ||
3005 test_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags))
5befc7c2
KB		 3006 return 0;
3007
3008 id = kzalloc(sizeof(*id), GFP_KERNEL);
3009 if (!id)
bcaf434b 3010 return -ENOMEM;
5befc7c2
KB		 3011
3012 c.identify.opcode = nvme_admin_identify;
3013 c.identify.cns = NVME_ID_CNS_CS_CTRL;
3014 c.identify.csi = NVME_CSI_NVM;
3015
3016 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
3017 if (ret)
3018 goto free_data;
3019
3b946fe1 3020 ctrl->dmrl = id->dmrl;
1a86924e 3021 ctrl->dmrsl = le32_to_cpu(id->dmrsl);
5befc7c2
KB		 3022 if (id->wzsl)
3023 ctrl->max_zeroes_sectors = nvme_mps_to_sectors(ctrl, id->wzsl);
3024
3025free_data:
c917dd96
KB		 3026 if (ret > 0)
3027 set_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags);
5befc7c2
KB		 3028 kfree(id);
3029 return ret;
3030}
3031
cc115cbe
KB		 3032static void nvme_init_known_nvm_effects(struct nvme_ctrl *ctrl)
3033{
3034 struct nvme_effects_log *log = ctrl->effects;
3035
3036 log->acs[nvme_admin_format_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC |
3037 NVME_CMD_EFFECTS_NCC |
3038 NVME_CMD_EFFECTS_CSE_MASK);
3039 log->acs[nvme_admin_sanitize_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC |
3040 NVME_CMD_EFFECTS_CSE_MASK);
3041
baff6491
KB		 3042 /*
3043 * The spec says the result of a security receive command depends on
3044 * the previous security send command. As such, many vendors log this
3045 * command as one to submitted only when no other commands to the same
3046 * namespace are outstanding. The intention is to tell the host to
3047 * prevent mixing security send and receive.
3048 *
3049 * This driver can only enforce such exclusive access against IO
3050 * queues, though. We are not readily able to enforce such a rule for
3051 * two commands to the admin queue, which is the only queue that
3052 * matters for this command.
3053 *
3054 * Rather than blindly freezing the IO queues for this effect that
3055 * doesn't even apply to IO, mask it off.
3056 */
c0c33b94 3057 log->acs[nvme_admin_security_recv] &= cpu_to_le32(~NVME_CMD_EFFECTS_CSE_MASK);
baff6491 3058
cc115cbe
KB		 3059 log->iocs[nvme_cmd_write] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3060 log->iocs[nvme_cmd_write_zeroes] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3061 log->iocs[nvme_cmd_write_uncor] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3062}
3063
3064static int nvme_init_effects(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
3065{
3066 int ret = 0;
3067
3068 if (ctrl->effects)
3069 return 0;
3070
3071 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
3072 ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects);
3073 if (ret < 0)
3074 return ret;
3075 }
3076
3077 if (!ctrl->effects) {
3078 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
3079 if (!ctrl->effects)
3080 return -ENOMEM;
3081 xa_store(&ctrl->cels, NVME_CSI_NVM, ctrl->effects, GFP_KERNEL);
3082 }
3083
3084 nvme_init_known_nvm_effects(ctrl);
3085 return 0;
3086}
3087
68999d1d
GL		 3088static int nvme_check_ctrl_fabric_info(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
3089{
3090 /*
3091 * In fabrics we need to verify the cntlid matches the
3092 * admin connect
3093 */
3094 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
3095 dev_err(ctrl->device,
3096 "Mismatching cntlid: Connect %u vs Identify %u, rejecting\n",
3097 ctrl->cntlid, le16_to_cpu(id->cntlid));
3098 return -EINVAL;
3099 }
3100
3101 if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) {
3102 dev_err(ctrl->device,
3103 "keep-alive support is mandatory for fabrics\n");
3104 return -EINVAL;
3105 }
3106
7642138e 3107 if (!nvme_discovery_ctrl(ctrl) && ctrl->ioccsz < 4) {
2fcd3ab3
GL		 3108 dev_err(ctrl->device,
3109 "I/O queue command capsule supported size %d < 4\n",
3110 ctrl->ioccsz);
3111 return -EINVAL;
3112 }
3113
7642138e 3114 if (!nvme_discovery_ctrl(ctrl) && ctrl->iorcsz < 1) {
2fcd3ab3
GL		 3115 dev_err(ctrl->device,
3116 "I/O queue response capsule supported size %d < 1\n",
3117 ctrl->iorcsz);
3118 return -EINVAL;
3119 }
3120
49995681
GL		 3121 if (!ctrl->maxcmd) {
3122 dev_err(ctrl->device, "Maximum outstanding commands is 0\n");
3123 return -EINVAL;
3124 }
3125
68999d1d
GL		 3126 return 0;
3127}
3128
44ef5611 3129static int nvme_init_identify(struct nvme_ctrl *ctrl)
7fd8930f
CH		 3130{
3131 struct nvme_id_ctrl *id;
a229dbf6 3132 u32 max_hw_sectors;
76a5af84 3133 bool prev_apst_enabled;
5befc7c2 3134 int ret;
f3ca80fc 3135
7fd8930f
CH		 3136 ret = nvme_identify_ctrl(ctrl, &id);
3137 if (ret) {
1b3c47c1 3138 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 3139 return -EIO;
3140 }
3141
a89fcca8
GP		 3142 if (!(ctrl->ops->flags & NVME_F_FABRICS))
3143 ctrl->cntlid = le16_to_cpu(id->cntlid);
3144
bd4da3ab 3145 if (!ctrl->identified) {
44ef5611 3146 unsigned int i;
ab9e00cc 3147
bd4da3ab
AL		 3148 /*
3149 * Check for quirks. Quirk can depend on firmware version,
3150 * so, in principle, the set of quirks present can change
3151 * across a reset. As a possible future enhancement, we
3152 * could re-scan for quirks every time we reinitialize
3153 * the device, but we'd have to make sure that the driver
3154 * behaves intelligently if the quirks change.
3155 */
bd4da3ab
AL		 3156 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
3157 if (quirk_matches(id, &core_quirks[i]))
3158 ctrl->quirks |= core_quirks[i].quirks;
3159 }
6f2d7152
PR		 3160
3161 ret = nvme_init_subsystem(ctrl, id);
3162 if (ret)
3163 goto out_free;
cc115cbe
KB		 3164
3165 ret = nvme_init_effects(ctrl, id);
3166 if (ret)
3167 goto out_free;
bd4da3ab 3168 }
a8eb6c1b
KB		 3169 memcpy(ctrl->subsys->firmware_rev, id->fr,
3170 sizeof(ctrl->subsys->firmware_rev));
bd4da3ab 3171
c35e30b4 3172 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 3173 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 3174 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
3175 }
3176
49cd84b6
KB		 3177 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
3178 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
3179 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
3180
8a9ae523 3181 ctrl->oacs = le16_to_cpu(id->oacs);
43e2d08d 3182 ctrl->oncs = le16_to_cpu(id->oncs);
2d466c7a 3183 ctrl->mtfa = le16_to_cpu(id->mtfa);
c0561f82 3184 ctrl->oaes = le32_to_cpu(id->oaes);
400b6a7b
GR		 3185 ctrl->wctemp = le16_to_cpu(id->wctemp);
3186 ctrl->cctemp = le16_to_cpu(id->cctemp);
3187
6bf25d16 3188 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 3189 ctrl->vwc = id->vwc;
7fd8930f 3190 if (id->mdts)
5befc7c2 3191 max_hw_sectors = nvme_mps_to_sectors(ctrl, id->mdts);
7fd8930f 3192 else
a229dbf6
CH		 3193 max_hw_sectors = UINT_MAX;
3194 ctrl->max_hw_sectors =
3195 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 3196
da35825d 3197 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 3198 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 3199 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 3200 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 3201 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 3202
86c2457a
MB		 3203 ctrl->cntrltype = id->cntrltype;
3204 ctrl->dctype = id->dctype;
3205
07fbd32a
MP		 3206 if (id->rtd3e) {
3207 /* us -> s */
f5af577d 3208 u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC;
07fbd32a
MP		 3209
3210 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
3211 shutdown_timeout, 60);
3212
3213 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 3214 dev_info(ctrl->device,
07fbd32a
MP		 3215 "Shutdown timeout set to %u seconds\n",
3216 ctrl->shutdown_timeout);
3217 } else
3218 ctrl->shutdown_timeout = shutdown_timeout;
3219
c5552fde 3220 ctrl->npss = id->npss;
76a5af84
KHF		 3221 ctrl->apsta = id->apsta;
3222 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 3223 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
3224 if (force_apst && id->apsta) {
f0425db0 3225 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 3226 ctrl->apst_enabled = true;
c35e30b4 3227 } else {
76a5af84 3228 ctrl->apst_enabled = false;
c35e30b4
AL		 3229 }
3230 } else {
76a5af84 3231 ctrl->apst_enabled = id->apsta;
c35e30b4 3232 }
c5552fde
AL		 3233 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
3234
d3d5b87d 3235 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 3236 ctrl->icdoff = le16_to_cpu(id->icdoff);
3237 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
3238 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
3239 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
3240
68999d1d
GL		 3241 ret = nvme_check_ctrl_fabric_info(ctrl, id);
3242 if (ret)
634b8325 3243 goto out_free;
07bfcd09 3244 } else {
fe6d53c9
CH		 3245 ctrl->hmpre = le32_to_cpu(id->hmpre);
3246 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 3247 ctrl->hmminds = le32_to_cpu(id->hmminds);
3248 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 3249 }
da35825d 3250
5e1f6899 3251 ret = nvme_mpath_init_identify(ctrl, id);
0d0b660f 3252 if (ret < 0)
44ef5611 3253 goto out_free;
0d0b660f 3254
76a5af84 3255 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 3256 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 3257 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 3258 dev_pm_qos_hide_latency_tolerance(ctrl->device);
3259
44ef5611
CK		 3260out_free:
3261 kfree(id);
3262 return ret;
3263}
3264
3265/*
3266 * Initialize the cached copies of the Identify data and various controller
3267 * register in our nvme_ctrl structure. This should be called as soon as
3268 * the admin queue is fully up and running.
3269 */
94cc781f 3270int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended)
44ef5611
CK		 3271{
3272 int ret;
3273
3274 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
3275 if (ret) {
3276 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
3277 return ret;
3278 }
3279
3280 ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize);
3281
3282 if (ctrl->vs >= NVME_VS(1, 1, 0))
3283 ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap);
3284
3285 ret = nvme_init_identify(ctrl);
3286 if (ret)
3287 return ret;
3288
634b8325
KB		 3289 ret = nvme_configure_apst(ctrl);
3290 if (ret < 0)
3291 return ret;
95d54bd1 3292
dbf86b39
JD		 3293 ret = nvme_configure_timestamp(ctrl);
3294 if (ret < 0)
3295 return ret;
634b8325 3296
4020aad8 3297 ret = nvme_configure_host_options(ctrl);
49cd84b6
KB		 3298 if (ret < 0)
3299 return ret;
3300
94cc781f
CH		 3301 nvme_configure_opal(ctrl, was_suspended);
3302
5ab25a32 3303 if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) {
6b8cf940
CH		 3304 /*
3305 * Do not return errors unless we are in a controller reset,
3306 * the controller works perfectly fine without hwmon.
3307 */
59e330f8 3308 ret = nvme_hwmon_init(ctrl);
6b8cf940 3309 if (ret == -EINTR)
59e330f8
KB		 3310 return ret;
3311 }
400b6a7b 3312
d0dd594b 3313 clear_bit(NVME_CTRL_DIRTY_CAPABILITY, &ctrl->flags);
bd4da3ab 3314 ctrl->identified = true;
c5552fde 3315
4733b65d
HR		 3316 nvme_start_keep_alive(ctrl);
3317
634b8325 3318 return 0;
7fd8930f 3319}
f21c4769 3320EXPORT_SYMBOL_GPL(nvme_init_ctrl_finish);
7fd8930f 3321
f3ca80fc 3322static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 3323{
a6a5149b
CH		 3324 struct nvme_ctrl *ctrl =
3325 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 3326
e6e7f7ac 3327 switch (nvme_ctrl_state(ctrl)) {
2b1b7e78 3328 case NVME_CTRL_LIVE:
2b1b7e78
JW		 3329 break;
3330 default:
a6a5149b 3331 return -EWOULDBLOCK;
2b1b7e78
JW		 3332 }
3333
52a3974f 3334 nvme_get_ctrl(ctrl);
4bab6909
CK		 3335 if (!try_module_get(ctrl->ops->module)) {
3336 nvme_put_ctrl(ctrl);
52a3974f 3337 return -EINVAL;
4bab6909 3338 }
52a3974f 3339
a6a5149b 3340 file->private_data = ctrl;
f3ca80fc
CH		 3341 return 0;
3342}
3343
52a3974f
CK		 3344static int nvme_dev_release(struct inode *inode, struct file *file)
3345{
3346 struct nvme_ctrl *ctrl =
3347 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
3348
3349 module_put(ctrl->ops->module);
3350 nvme_put_ctrl(ctrl);
3351 return 0;
3352}
3353
f3ca80fc
CH		 3354static const struct file_operations nvme_dev_fops = {
3355 .owner = THIS_MODULE,
3356 .open = nvme_dev_open,
52a3974f 3357 .release = nvme_dev_release,
f3ca80fc 3358 .unlocked_ioctl = nvme_dev_ioctl,
1832f2d8 3359 .compat_ioctl = compat_ptr_ioctl,
58e5bdeb 3360 .uring_cmd = nvme_dev_uring_cmd,
f3ca80fc
CH		 3361};
3362
5974ea7c 3363static struct nvme_ns_head *nvme_find_ns_head(struct nvme_ctrl *ctrl,
ed754e5d
CH		 3364 unsigned nsid)
3365{
3366 struct nvme_ns_head *h;
3367
5974ea7c 3368 lockdep_assert_held(&ctrl->subsys->lock);
ed754e5d 3369
5974ea7c
SM		 3370 list_for_each_entry(h, &ctrl->subsys->nsheads, entry) {
3371 /*
3372 * Private namespaces can share NSIDs under some conditions.
3373 * In that case we can't use the same ns_head for namespaces
3374 * with the same NSID.
3375 */
3376 if (h->ns_id != nsid || !nvme_is_unique_nsid(ctrl, h))
9edceaf4
DW		 3377 continue;
3378 if (!list_empty(&h->list) && nvme_tryget_ns_head(h))
ed754e5d
CH		 3379 return h;
3380 }
3381
3382 return NULL;
3383}
3384
fd8099e7
CH		 3385static int nvme_subsys_check_duplicate_ids(struct nvme_subsystem *subsys,
3386 struct nvme_ns_ids *ids)
ed754e5d 3387{
e2724cb9
CH		 3388 bool has_uuid = !uuid_is_null(&ids->uuid);
3389 bool has_nguid = memchr_inv(ids->nguid, 0, sizeof(ids->nguid));
3390 bool has_eui64 = memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
ed754e5d
CH		 3391 struct nvme_ns_head *h;
3392
3393 lockdep_assert_held(&subsys->lock);
3394
3395 list_for_each_entry(h, &subsys->nsheads, entry) {
e2724cb9
CH		 3396 if (has_uuid && uuid_equal(&ids->uuid, &h->ids.uuid))
3397 return -EINVAL;
3398 if (has_nguid &&
3399 memcmp(&ids->nguid, &h->ids.nguid, sizeof(ids->nguid)) == 0)
3400 return -EINVAL;
3401 if (has_eui64 &&
3402 memcmp(&ids->eui64, &h->ids.eui64, sizeof(ids->eui64)) == 0)
ed754e5d
CH		 3403 return -EINVAL;
3404 }
3405
3406 return 0;
3407}
3408
be5eb933
AM		 3409static void nvme_cdev_rel(struct device *dev)
3410{
8b850475 3411 ida_free(&nvme_ns_chr_minor_ida, MINOR(dev->devt));
be5eb933
AM		 3412}
3413
2637baed
MI		 3414void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device)
3415{
3416 cdev_device_del(cdev, cdev_device);
be5eb933 3417 put_device(cdev_device);
2637baed
MI		 3418}
3419
3420int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device,
3421 const struct file_operations *fops, struct module *owner)
3422{
3423 int minor, ret;
3424
8b850475 3425 minor = ida_alloc(&nvme_ns_chr_minor_ida, GFP_KERNEL);
2637baed
MI		 3426 if (minor < 0)
3427 return minor;
3428 cdev_device->devt = MKDEV(MAJOR(nvme_ns_chr_devt), minor);
3429 cdev_device->class = nvme_ns_chr_class;
be5eb933 3430 cdev_device->release = nvme_cdev_rel;
2637baed
MI		 3431 device_initialize(cdev_device);
3432 cdev_init(cdev, fops);
3433 cdev->owner = owner;
3434 ret = cdev_device_add(cdev, cdev_device);
be5eb933 3435 if (ret)
3596a065 3436 put_device(cdev_device);
be5eb933 3437
2637baed
MI		 3438 return ret;
3439}
3440
3441static int nvme_ns_chr_open(struct inode *inode, struct file *file)
3442{
3443 return nvme_ns_open(container_of(inode->i_cdev, struct nvme_ns, cdev));
3444}
3445
3446static int nvme_ns_chr_release(struct inode *inode, struct file *file)
3447{
3448 nvme_ns_release(container_of(inode->i_cdev, struct nvme_ns, cdev));
3449 return 0;
3450}
3451
3452static const struct file_operations nvme_ns_chr_fops = {
3453 .owner = THIS_MODULE,
3454 .open = nvme_ns_chr_open,
3455 .release = nvme_ns_chr_release,
3456 .unlocked_ioctl = nvme_ns_chr_ioctl,
3457 .compat_ioctl = compat_ptr_ioctl,
456cba38 3458 .uring_cmd = nvme_ns_chr_uring_cmd,
585079b6 3459 .uring_cmd_iopoll = nvme_ns_chr_uring_cmd_iopoll,
2637baed
MI		 3460};
3461
3462static int nvme_add_ns_cdev(struct nvme_ns *ns)
3463{
3464 int ret;
3465
3466 ns->cdev_device.parent = ns->ctrl->device;
3467 ret = dev_set_name(&ns->cdev_device, "ng%dn%d",
3468 ns->ctrl->instance, ns->head->instance);
3469 if (ret)
3470 return ret;
be5eb933
AM		 3471
3472 return nvme_cdev_add(&ns->cdev, &ns->cdev_device, &nvme_ns_chr_fops,
3473 ns->ctrl->ops->module);
2637baed
MI		 3474}
3475
ed754e5d 3476static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
1a893c2b 3477 struct nvme_ns_info *info)
ed754e5d
CH		 3478{
3479 struct nvme_ns_head *head;
f3334447 3480 size_t size = sizeof(*head);
ed754e5d
CH		 3481 int ret = -ENOMEM;
3482
f3334447
CH		 3483#ifdef CONFIG_NVME_MULTIPATH
3484 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3485#endif
3486
3487 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH		 3488 if (!head)
3489 goto out;
8b850475 3490 ret = ida_alloc_min(&ctrl->subsys->ns_ida, 1, GFP_KERNEL);
ed754e5d
CH		 3491 if (ret < 0)
3492 goto out_free_head;
3493 head->instance = ret;
3494 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 3495 ret = init_srcu_struct(&head->srcu);
3496 if (ret)
3497 goto out_ida_remove;
ed754e5d 3498 head->subsys = ctrl->subsys;
1a893c2b
CH		 3499 head->ns_id = info->nsid;
3500 head->ids = info->ids;
3501 head->shared = info->is_shared;
a1a825ab
DW		 3502 ratelimit_state_init(&head->rs_nuse, 5 * HZ, 1);
3503 ratelimit_set_flags(&head->rs_nuse, RATELIMIT_MSG_ON_RELEASE);
ed754e5d
CH		 3504 kref_init(&head->ref);
3505
be93e87e
KB		 3506 if (head->ids.csi) {
3507 ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects);
3508 if (ret)
3509 goto out_cleanup_srcu;
3510 } else
3511 head->effects = ctrl->effects;
3512
32acab31
CH		 3513 ret = nvme_mpath_alloc_disk(ctrl, head);
3514 if (ret)
3515 goto out_cleanup_srcu;
3516
ed754e5d 3517 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 3518
3519 kref_get(&ctrl->subsys->ref);
3520
ed754e5d
CH		 3521 return head;
3522out_cleanup_srcu:
3523 cleanup_srcu_struct(&head->srcu);
fd92c77f 3524out_ida_remove:
8b850475 3525 ida_free(&ctrl->subsys->ns_ida, head->instance);
ed754e5d
CH		 3526out_free_head:
3527 kfree(head);
3528out:
538af88e
SG		 3529 if (ret > 0)
3530 ret = blk_status_to_errno(nvme_error_status(ret));
ed754e5d
CH		 3531 return ERR_PTR(ret);
3532}
3533
2079f41e
CH		 3534static int nvme_global_check_duplicate_ids(struct nvme_subsystem *this,
3535 struct nvme_ns_ids *ids)
3536{
3537 struct nvme_subsystem *s;
3538 int ret = 0;
3539
3540 /*
3541 * Note that this check is racy as we try to avoid holding the global
3542 * lock over the whole ns_head creation. But it is only intended as
3543 * a sanity check anyway.
3544 */
3545 mutex_lock(&nvme_subsystems_lock);
3546 list_for_each_entry(s, &nvme_subsystems, entry) {
3547 if (s == this)
3548 continue;
3549 mutex_lock(&s->lock);
3550 ret = nvme_subsys_check_duplicate_ids(s, ids);
3551 mutex_unlock(&s->lock);
3552 if (ret)
3553 break;
3554 }
3555 mutex_unlock(&nvme_subsystems_lock);
3556
3557 return ret;
3558}
3559
1a893c2b 3560static int nvme_init_ns_head(struct nvme_ns *ns, struct nvme_ns_info *info)
ed754e5d
CH		 3561{
3562 struct nvme_ctrl *ctrl = ns->ctrl;
ed754e5d 3563 struct nvme_ns_head *head = NULL;
2079f41e
CH		 3564 int ret;
3565
1a893c2b 3566 ret = nvme_global_check_duplicate_ids(ctrl->subsys, &info->ids);
2079f41e 3567 if (ret) {
ac522fc6
CH		 3568 /*
3569 * We've found two different namespaces on two different
3570 * subsystems that report the same ID. This is pretty nasty
3571 * for anything that actually requires unique device
3572 * identification. In the kernel we need this for multipathing,
3573 * and in user space the /dev/disk/by-id/ links rely on it.
3574 *
3575 * If the device also claims to be multi-path capable back off
3576 * here now and refuse the probe the second device as this is a
3577 * recipe for data corruption. If not this is probably a
3578 * cheap consumer device if on the PCIe bus, so let the user
3579 * proceed and use the shiny toy, but warn that with changing
3580 * probing order (which due to our async probing could just be
3581 * device taking longer to startup) the other device could show
3582 * up at any time.
3583 */
2f0dad17 3584 nvme_print_device_info(ctrl);
ac522fc6
CH		 3585 if ((ns->ctrl->ops->flags & NVME_F_FABRICS) || /* !PCIe */
3586 ((ns->ctrl->subsys->cmic & NVME_CTRL_CMIC_MULTI_CTRL) &&
3587 info->is_shared)) {
3588 dev_err(ctrl->device,
3589 "ignoring nsid %d because of duplicate IDs\n",
3590 info->nsid);
3591 return ret;
3592 }
3593
3594 dev_err(ctrl->device,
3595 "clearing duplicate IDs for nsid %d\n", info->nsid);
3596 dev_err(ctrl->device,
3597 "use of /dev/disk/by-id/ may cause data corruption\n");
3598 memset(&info->ids.nguid, 0, sizeof(info->ids.nguid));
3599 memset(&info->ids.uuid, 0, sizeof(info->ids.uuid));
3600 memset(&info->ids.eui64, 0, sizeof(info->ids.eui64));
3601 ctrl->quirks |= NVME_QUIRK_BOGUS_NID;
2079f41e 3602 }
ed754e5d
CH		 3603
3604 mutex_lock(&ctrl->subsys->lock);
1a893c2b 3605 head = nvme_find_ns_head(ctrl, info->nsid);
ed754e5d 3606 if (!head) {
1a893c2b 3607 ret = nvme_subsys_check_duplicate_ids(ctrl->subsys, &info->ids);
e2d77d2e
CH		 3608 if (ret) {
3609 dev_err(ctrl->device,
2079f41e 3610 "duplicate IDs in subsystem for nsid %d\n",
1a893c2b 3611 info->nsid);
e2d77d2e
CH		 3612 goto out_unlock;
3613 }
1a893c2b 3614 head = nvme_alloc_ns_head(ctrl, info);
ed754e5d
CH		 3615 if (IS_ERR(head)) {
3616 ret = PTR_ERR(head);
3617 goto out_unlock;
3618 }
ed754e5d 3619 } else {
6623c5b3 3620 ret = -EINVAL;
1a893c2b 3621 if (!info->is_shared || !head->shared) {
9ad1927a 3622 dev_err(ctrl->device,
1a893c2b
CH		 3623 "Duplicate unshared namespace %d\n",
3624 info->nsid);
6623c5b3 3625 goto out_put_ns_head;
9ad1927a 3626 }
1a893c2b 3627 if (!nvme_ns_ids_equal(&head->ids, &info->ids)) {
ed754e5d
CH		 3628 dev_err(ctrl->device,
3629 "IDs don't match for shared namespace %d\n",
1a893c2b 3630 info->nsid);
6623c5b3 3631 goto out_put_ns_head;
ed754e5d 3632 }
ce8d7861 3633
2110a6bc 3634 if (!multipath) {
ce8d7861
CH		 3635 dev_warn(ctrl->device,
3636 "Found shared namespace %d, but multipathing not supported.\n",
1a893c2b 3637 info->nsid);
ce8d7861
CH		 3638 dev_warn_once(ctrl->device,
3639 "Support for shared namespaces without CONFIG_NVME_MULTIPATH is deprecated and will be removed in Linux 6.0\n.");
3640 }
ed754e5d
CH		 3641 }
3642
772ea326 3643 list_add_tail_rcu(&ns->siblings, &head->list);
ed754e5d 3644 ns->head = head;
6623c5b3
CH		 3645 mutex_unlock(&ctrl->subsys->lock);
3646 return 0;
ed754e5d 3647
6623c5b3
CH		 3648out_put_ns_head:
3649 nvme_put_ns_head(head);
ed754e5d
CH		 3650out_unlock:
3651 mutex_unlock(&ctrl->subsys->lock);
3652 return ret;
3653}
3654
24493b8b 3655struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3656{
32f0c4af 3657 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 3658
765cc031 3659 down_read(&ctrl->namespaces_rwsem);
5bae7f73 3660 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 3661 if (ns->head->ns_id == nsid) {
4c74d1f8 3662 if (!nvme_get_ns(ns))
2dd41228 3663 continue;
32f0c4af
KB		 3664 ret = ns;
3665 break;
3666 }
ed754e5d 3667 if (ns->head->ns_id > nsid)
5bae7f73
CH		 3668 break;
3669 }
765cc031 3670 up_read(&ctrl->namespaces_rwsem);
32f0c4af 3671 return ret;
5bae7f73 3672}
24493b8b 3673EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU);
5bae7f73 3674
298ba0e3
CH		 3675/*
3676 * Add the namespace to the controller list while keeping the list ordered.
3677 */
3678static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns)
3679{
3680 struct nvme_ns *tmp;
3681
3682 list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) {
3683 if (tmp->head->ns_id < ns->head->ns_id) {
3684 list_add(&ns->list, &tmp->list);
3685 return;
3686 }
3687 }
3688 list_add(&ns->list, &ns->ctrl->namespaces);
3689}
3690
1a893c2b 3691static void nvme_alloc_ns(struct nvme_ctrl *ctrl, struct nvme_ns_info *info)
5bae7f73
CH		 3692{
3693 struct nvme_ns *ns;
3694 struct gendisk *disk;
9953ab0c 3695 int node = ctrl->numa_node;
5bae7f73
CH		 3696
3697 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3698 if (!ns)
1a893c2b 3699 return;
5bae7f73 3700
27e32cd2 3701 disk = blk_mq_alloc_disk(ctrl->tagset, NULL, ns);
5f432cce 3702 if (IS_ERR(disk))
ed754e5d 3703 goto out_free_ns;
5f432cce
CH		 3704 disk->fops = &nvme_bdev_ops;
3705 disk->private_data = ns;
3706
3707 ns->disk = disk;
3708 ns->queue = disk->queue;
9f079dda 3709 ns->passthru_err_log_enabled = false;
e0596ab2 3710
7d30c81b 3711 if (ctrl->opts && ctrl->opts->data_digest)
1cb039f3 3712 blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, ns->queue);
958f2a0f 3713
8b904b5b 3714 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
2f859441
LG		 3715 if (ctrl->ops->supports_pci_p2pdma &&
3716 ctrl->ops->supports_pci_p2pdma(ctrl))
e0596ab2
LG		 3717 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3718
5bae7f73 3719 ns->ctrl = ctrl;
5bae7f73 3720 kref_init(&ns->kref);
5bae7f73 3721
1a893c2b 3722 if (nvme_init_ns_head(ns, info))
5f432cce 3723 goto out_cleanup_disk;
ac81bfa9 3724
9953ab0c 3725 /*
b739e137
CH		 3726 * If multipathing is enabled, the device name for all disks and not
3727 * just those that represent shared namespaces needs to be based on the
3728 * subsystem instance. Using the controller instance for private
3729 * namespaces could lead to naming collisions between shared and private
3730 * namespaces if they don't use a common numbering scheme.
3731 *
3732 * If multipathing is not enabled, disk names must use the controller
3733 * instance as shared namespaces will show up as multiple block
3734 * devices.
9953ab0c 3735 */
35e797b0 3736 if (nvme_ns_head_multipath(ns->head)) {
b739e137
CH		 3737 sprintf(disk->disk_name, "nvme%dc%dn%d", ctrl->subsys->instance,
3738 ctrl->instance, ns->head->instance);
3739 disk->flags |= GENHD_FL_HIDDEN;
3740 } else if (multipath) {
3741 sprintf(disk->disk_name, "nvme%dn%d", ctrl->subsys->instance,
3742 ns->head->instance);
3743 } else {
9953ab0c
CH		 3744 sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance,
3745 ns->head->instance);
b739e137 3746 }
3dc87dd0 3747
1a893c2b 3748 if (nvme_update_ns_info(ns, info))
5f432cce 3749 goto out_unlink_ns;
5bae7f73 3750
765cc031 3751 down_write(&ctrl->namespaces_rwsem);
839a40d1
BH		 3752 /*
3753 * Ensure that no namespaces are added to the ctrl list after the queues
3754 * are frozen, thereby avoiding a deadlock between scan and reset.
3755 */
3756 if (test_bit(NVME_CTRL_FROZEN, &ctrl->flags)) {
3757 up_write(&ctrl->namespaces_rwsem);
3758 goto out_unlink_ns;
3759 }
298ba0e3 3760 nvme_ns_add_to_ctrl_list(ns);
765cc031 3761 up_write(&ctrl->namespaces_rwsem);
d22524a4 3762 nvme_get_ctrl(ctrl);
ac81bfa9 3763
83ac678e 3764 if (device_add_disk(ctrl->device, ns->disk, nvme_ns_attr_groups))
ab3994f6
LC		 3765 goto out_cleanup_ns_from_list;
3766
2637baed
MI		 3767 if (!nvme_ns_head_multipath(ns->head))
3768 nvme_add_ns_cdev(ns);
32acab31 3769
1a893c2b 3770 nvme_mpath_add_disk(ns, info->anagrpid);
a3646451 3771 nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name);
0d0b660f 3772
9f079dda
AA		 3773 /*
3774 * Set ns->disk->device->driver_data to ns so we can access
3775 * ns->logging_enabled in nvme_passthru_err_log_enabled_store() and
3776 * nvme_passthru_err_log_enabled_show().
3777 */
3778 dev_set_drvdata(disk_to_dev(ns->disk), ns);
3779
adce7e98 3780 return;
5f432cce 3781
ab3994f6
LC		 3782 out_cleanup_ns_from_list:
3783 nvme_put_ctrl(ctrl);
3784 down_write(&ctrl->namespaces_rwsem);
3785 list_del_init(&ns->list);
3786 up_write(&ctrl->namespaces_rwsem);
ed754e5d
CH		 3787 out_unlink_ns:
3788 mutex_lock(&ctrl->subsys->lock);
3789 list_del_rcu(&ns->siblings);
d5675729
KB		 3790 if (list_empty(&ns->head->list))
3791 list_del_init(&ns->head->entry);
ed754e5d 3792 mutex_unlock(&ctrl->subsys->lock);
a63b8370 3793 nvme_put_ns_head(ns->head);
5f432cce 3794 out_cleanup_disk:
8b9ab626 3795 put_disk(disk);
5bae7f73
CH		 3796 out_free_ns:
3797 kfree(ns);
3798}
3799
3800static void nvme_ns_remove(struct nvme_ns *ns)
3801{
5396fdac
HR		 3802 bool last_path = false;
3803
646017a6
KB		 3804 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3805 return;
69d3b8ac 3806
e7d65803 3807 clear_bit(NVME_NS_READY, &ns->flags);
0a05226a 3808 set_capacity(ns->disk, 0);
a3646451 3809 nvme_fault_inject_fini(&ns->fault_inject);
2181e455 3810
d6d67427
CL		 3811 /*
3812 * Ensure that !NVME_NS_READY is seen by other threads to prevent
3813 * this ns going back into current_path.
3814 */
3815 synchronize_srcu(&ns->head->srcu);
3816
3817 /* wait for concurrent submissions */
3818 if (nvme_mpath_clear_current_path(ns))
3819 synchronize_srcu(&ns->head->srcu);
3820
2181e455
AE		 3821 mutex_lock(&ns->ctrl->subsys->lock);
3822 list_del_rcu(&ns->siblings);
9edceaf4
DW		 3823 if (list_empty(&ns->head->list)) {
3824 list_del_init(&ns->head->entry);
3825 last_path = true;
3826 }
2181e455 3827 mutex_unlock(&ns->ctrl->subsys->lock);
d5675729 3828
041bd1a1 3829 /* guarantee not available in head->list */
899d2a05 3830 synchronize_srcu(&ns->head->srcu);
041bd1a1 3831
5eba2005
CH		 3832 if (!nvme_ns_head_multipath(ns->head))
3833 nvme_cdev_del(&ns->cdev, &ns->cdev_device);
3834 del_gendisk(ns->disk);
32f0c4af 3835
765cc031 3836 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3837 list_del_init(&ns->list);
765cc031 3838 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3839
5396fdac
HR		 3840 if (last_path)
3841 nvme_mpath_shutdown_disk(ns->head);
5bae7f73
CH		 3842 nvme_put_ns(ns);
3843}
3844
4450ba3b
CH		 3845static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid)
3846{
3847 struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid);
3848
3849 if (ns) {
3850 nvme_ns_remove(ns);
3851 nvme_put_ns(ns);
3852 }
3853}
3854
1a893c2b 3855static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_info *info)
b2dc748a 3856{
d95c1f41 3857 int ret = NVME_SC_INVALID_NS | NVME_SC_DNR;
b2dc748a 3858
1a893c2b 3859 if (!nvme_ns_ids_equal(&ns->head->ids, &info->ids)) {
af5d6f7b 3860 dev_err(ns->ctrl->device,
b2dc748a 3861 "identifiers changed for nsid %d\n", ns->head->ns_id);
1a893c2b 3862 goto out;
b2dc748a
CH		 3863 }
3864
1a893c2b 3865 ret = nvme_update_ns_info(ns, info);
b2dc748a
CH		 3866out:
3867 /*
0a05226a 3868 * Only remove the namespace if we got a fatal error back from the
b2dc748a 3869 * device, otherwise ignore the error and just move on.
0a05226a
CH		 3870 *
3871 * TODO: we should probably schedule a delayed retry here.
b2dc748a 3872 */
d95c1f41 3873 if (ret > 0 && (ret & NVME_SC_DNR))
0a05226a 3874 nvme_ns_remove(ns);
b2dc748a
CH		 3875}
3876
04c170f6 3877static void nvme_scan_ns(struct nvme_ctrl *ctrl, unsigned nsid)
540c801c 3878{
1a893c2b 3879 struct nvme_ns_info info = { .nsid = nsid };
540c801c 3880 struct nvme_ns *ns;
0dd6fff2 3881 int ret;
540c801c 3882
1a893c2b 3883 if (nvme_identify_ns_descs(ctrl, &info))
8b7c0ff2 3884 return;
540c801c 3885
1a893c2b 3886 if (info.ids.csi != NVME_CSI_NVM && !nvme_multi_css(ctrl)) {
71882e7d
CH		 3887 dev_warn(ctrl->device,
3888 "command set not reported for nsid: %d\n", nsid);
3889 return;
3890 }
3891
354201c5 3892 /*
1a893c2b
CH		 3893 * If available try to use the Command Set Idependent Identify Namespace
3894 * data structure to find all the generic information that is needed to
3895 * set up a namespace. If not fall back to the legacy version.
354201c5 3896 */
eb867ee9 3897 if ((ctrl->cap & NVME_CAP_CRMS_CRIMS) ||
0dd6fff2
CH		 3898 (info.ids.csi != NVME_CSI_NVM && info.ids.csi != NVME_CSI_ZNS))
3899 ret = nvme_ns_info_from_id_cs_indep(ctrl, &info);
3900 else
3901 ret = nvme_ns_info_from_identify(ctrl, &info);
3902
3903 if (info.is_removed)
3904 nvme_ns_remove_by_nsid(ctrl, nsid);
354201c5 3905
1a893c2b
CH		 3906 /*
3907 * Ignore the namespace if it is not ready. We will get an AEN once it
3908 * becomes ready and restart the scan.
3909 */
0dd6fff2 3910 if (ret || !info.is_ready)
354201c5
CH		 3911 return;
3912
32f0c4af 3913 ns = nvme_find_get_ns(ctrl, nsid);
8b7c0ff2 3914 if (ns) {
1a893c2b 3915 nvme_validate_ns(ns, &info);
8b7c0ff2 3916 nvme_put_ns(ns);
1a893c2b
CH		 3917 } else {
3918 nvme_alloc_ns(ctrl, &info);
8b7c0ff2 3919 }
540c801c
KB		 3920}
3921
47b0e50a
SB		 3922static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3923 unsigned nsid)
3924{
3925 struct nvme_ns *ns, *next;
6f8e0d78 3926 LIST_HEAD(rm_list);
47b0e50a 3927
765cc031 3928 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3929 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
4f17344e 3930 if (ns->head->ns_id > nsid)
6f8e0d78 3931 list_move_tail(&ns->list, &rm_list);
47b0e50a 3932 }
765cc031 3933 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3934
3935 list_for_each_entry_safe(ns, next, &rm_list, list)
3936 nvme_ns_remove(ns);
3937
47b0e50a
SB		 3938}
3939
4005f28d 3940static int nvme_scan_ns_list(struct nvme_ctrl *ctrl)
540c801c 3941{
aec459b4 3942 const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32);
540c801c 3943 __le32 *ns_list;
4005f28d
CH		 3944 u32 prev = 0;
3945 int ret = 0, i;
540c801c 3946
42595eb7 3947 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3948 if (!ns_list)
3949 return -ENOMEM;
3950
4005f28d 3951 for (;;) {
7b153362
CH		 3952 struct nvme_command cmd = {
3953 .identify.opcode = nvme_admin_identify,
3954 .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST,
3955 .identify.nsid = cpu_to_le32(prev),
3956 };
3957
3958 ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list,
3959 NVME_IDENTIFY_DATA_SIZE);
f781f3dd
MI		 3960 if (ret) {
3961 dev_warn(ctrl->device,
3962 "Identify NS List failed (status=0x%x)\n", ret);
47b0e50a 3963 goto free;
f781f3dd 3964 }
540c801c 3965
aec459b4 3966 for (i = 0; i < nr_entries; i++) {
4005f28d 3967 u32 nsid = le32_to_cpu(ns_list[i]);
540c801c 3968
4005f28d
CH		 3969 if (!nsid) /* end of the list? */
3970 goto out;
04c170f6 3971 nvme_scan_ns(ctrl, nsid);
4450ba3b
CH		 3972 while (++prev < nsid)
3973 nvme_ns_remove_by_nsid(ctrl, prev);
540c801c 3974 }
540c801c
KB		 3975 }
3976 out:
47b0e50a
SB		 3977 nvme_remove_invalid_namespaces(ctrl, prev);
3978 free:
540c801c
KB		 3979 kfree(ns_list);
3980 return ret;
3981}
3982
4005f28d 3983static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl)
5bae7f73 3984{
4005f28d
CH		 3985 struct nvme_id_ctrl *id;
3986 u32 nn, i;
3987
3988 if (nvme_identify_ctrl(ctrl, &id))
3989 return;
3990 nn = le32_to_cpu(id->nn);
3991 kfree(id);
5bae7f73 3992
540c801c 3993 for (i = 1; i <= nn; i++)
04c170f6 3994 nvme_scan_ns(ctrl, i);
540c801c 3995
47b0e50a 3996 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3997}
3998
f493af37 3999static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 4000{
4001 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
4002 __le32 *log;
f493af37 4003 int error;
30d90964
CH		 4004
4005 log = kzalloc(log_size, GFP_KERNEL);
4006 if (!log)
f493af37 4007 return;
30d90964 4008
f493af37
CH		 4009 /*
4010 * We need to read the log to clear the AEN, but we don't want to rely
4011 * on it for the changed namespace information as userspace could have
4012 * raced with us in reading the log page, which could cause us to miss
4013 * updates.
4014 */
be93e87e
KB		 4015 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0,
4016 NVME_CSI_NVM, log, log_size, 0);
f493af37 4017 if (error)
30d90964
CH		 4018 dev_warn(ctrl->device,
4019 "reading changed ns log failed: %d\n", error);
30d90964 4020
30d90964 4021 kfree(log);
30d90964
CH		 4022}
4023
5955be21 4024static void nvme_scan_work(struct work_struct *work)
5bae7f73 4025{
5955be21
CH		 4026 struct nvme_ctrl *ctrl =
4027 container_of(work, struct nvme_ctrl, scan_work);
78288665 4028 int ret;
5bae7f73 4029
5d02a5c1 4030 /* No tagset on a live ctrl means IO queues could not created */
e6e7f7ac 4031 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE || !ctrl->tagset)
5955be21
CH		 4032 return;
4033
78288665
CK		 4034 /*
4035 * Identify controller limits can change at controller reset due to
4036 * new firmware download, even though it is not common we cannot ignore
4037 * such scenario. Controller's non-mdts limits are reported in the unit
4038 * of logical blocks that is dependent on the format of attached
4039 * namespace. Hence re-read the limits at the time of ns allocation.
4040 */
4041 ret = nvme_init_non_mdts_limits(ctrl);
4042 if (ret < 0) {
4043 dev_warn(ctrl->device,
4044 "reading non-mdts-limits failed: %d\n", ret);
4045 return;
4046 }
4047
77016199 4048 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 4049 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 4050 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 4051 }
4052
e7ad43c3 4053 mutex_lock(&ctrl->scan_lock);
811f4de0 4054 if (nvme_ctrl_limited_cns(ctrl)) {
4005f28d 4055 nvme_scan_ns_sequential(ctrl);
811f4de0
US		 4056 } else {
4057 /*
4058 * Fall back to sequential scan if DNR is set to handle broken
4059 * devices which should support Identify NS List (as per the VS
4060 * they report) but don't actually support it.
4061 */
4062 ret = nvme_scan_ns_list(ctrl);
4063 if (ret > 0 && ret & NVME_SC_DNR)
4064 nvme_scan_ns_sequential(ctrl);
4065 }
e7ad43c3 4066 mutex_unlock(&ctrl->scan_lock);
5955be21 4067}
5bae7f73 4068
32f0c4af
KB		 4069/*
4070 * This function iterates the namespace list unlocked to allow recovery from
4071 * controller failure. It is up to the caller to ensure the namespace list is
4072 * not modified by scan work while this function is executing.
4073 */
5bae7f73
CH		 4074void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
4075{
4076 struct nvme_ns *ns, *next;
6f8e0d78 4077 LIST_HEAD(ns_list);
5bae7f73 4078
0157ec8d
SG		 4079 /*
4080 * make sure to requeue I/O to all namespaces as these
4081 * might result from the scan itself and must complete
4082 * for the scan_work to make progress
4083 */
4084 nvme_mpath_clear_ctrl_paths(ctrl);
4085
1b95e817
ML		 4086 /*
4087 * Unquiesce io queues so any pending IO won't hang, especially
4088 * those submitted from scan work
4089 */
4090 nvme_unquiesce_io_queues(ctrl);
4091
f6c8e432
SG		 4092 /* prevent racing with ns scanning */
4093 flush_work(&ctrl->scan_work);
4094
0ff9d4e1
KB		 4095 /*
4096 * The dead states indicates the controller was not gracefully
4097 * disconnected. In that case, we won't be able to flush any data while
4098 * removing the namespaces' disks; fail all the queues now to avoid
4099 * potentially having to clean up the failed sync later.
4100 */
e6e7f7ac 4101 if (nvme_ctrl_state(ctrl) == NVME_CTRL_DEAD)
cd50f9b2 4102 nvme_mark_namespaces_dead(ctrl);
0ff9d4e1 4103
ecca390e
SG		 4104 /* this is a no-op when called from the controller reset handler */
4105 nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO);
4106
765cc031 4107 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 4108 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 4109 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 4110
4111 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 4112 nvme_ns_remove(ns);
4113}
576d55d6 4114EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 4115
23680f0b 4116static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env)
a42f42e5 4117{
23680f0b 4118 const struct nvme_ctrl *ctrl =
a42f42e5
SG		 4119 container_of(dev, struct nvme_ctrl, ctrl_device);
4120 struct nvmf_ctrl_options *opts = ctrl->opts;
4121 int ret;
4122
4123 ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name);
4124 if (ret)
4125 return ret;
4126
4127 if (opts) {
4128 ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr);
4129 if (ret)
4130 return ret;
4131
4132 ret = add_uevent_var(env, "NVME_TRSVCID=%s",
4133 opts->trsvcid ?: "none");
4134 if (ret)
4135 return ret;
4136
4137 ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s",
4138 opts->host_traddr ?: "none");
3ede8f72
MB		 4139 if (ret)
4140 return ret;
4141
4142 ret = add_uevent_var(env, "NVME_HOST_IFACE=%s",
4143 opts->host_iface ?: "none");
a42f42e5
SG		 4144 }
4145 return ret;
4146}
4147
20d64911
MB		 4148static void nvme_change_uevent(struct nvme_ctrl *ctrl, char *envdata)
4149{
4150 char *envp[2] = { envdata, NULL };
4151
4152 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4153}
4154
e3d7874d
KB		 4155static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
4156{
4157 char *envp[2] = { NULL, NULL };
4158 u32 aen_result = ctrl->aen_result;
4159
4160 ctrl->aen_result = 0;
4161 if (!aen_result)
4162 return;
4163
4164 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
4165 if (!envp[0])
4166 return;
4167 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4168 kfree(envp[0]);
4169}
4170
f866fc42
CH		 4171static void nvme_async_event_work(struct work_struct *work)
4172{
4173 struct nvme_ctrl *ctrl =
4174 container_of(work, struct nvme_ctrl, async_event_work);
4175
e3d7874d 4176 nvme_aen_uevent(ctrl);
0fa0f99f
SG		 4177
4178 /*
4179 * The transport drivers must guarantee AER submission here is safe by
4180 * flushing ctrl async_event_work after changing the controller state
4181 * from LIVE and before freeing the admin queue.
4182 */
e6e7f7ac 4183 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE)
0fa0f99f 4184 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 4185}
4186
b6dccf7f
AD		 4187static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
4188{
4189
4190 u32 csts;
4191
4192 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
4193 return false;
4194
4195 if (csts == ~0)
4196 return false;
4197
4198 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
4199}
4200
4201static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
4202{
b6dccf7f
AD		 4203 struct nvme_fw_slot_info_log *log;
4204
4205 log = kmalloc(sizeof(*log), GFP_KERNEL);
4206 if (!log)
4207 return;
4208
be93e87e 4209 if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM,
983a338b 4210 log, sizeof(*log), 0)) {
0e98719b 4211 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
983a338b
DW		 4212 goto out_free_log;
4213 }
4214
4215 if (log->afi & 0x70 || !(log->afi & 0x7)) {
4216 dev_info(ctrl->device,
4217 "Firmware is activated after next Controller Level Reset\n");
4218 goto out_free_log;
4219 }
4220
4221 memcpy(ctrl->subsys->firmware_rev, &log->frs[(log->afi & 0x7) - 1],
4222 sizeof(ctrl->subsys->firmware_rev));
4223
4224out_free_log:
b6dccf7f
AD		 4225 kfree(log);
4226}
4227
4228static void nvme_fw_act_work(struct work_struct *work)
4229{
4230 struct nvme_ctrl *ctrl = container_of(work,
4231 struct nvme_ctrl, fw_act_work);
4232 unsigned long fw_act_timeout;
4233
f6fe0b2d
ML		 4234 nvme_auth_stop(ctrl);
4235
b6dccf7f
AD		 4236 if (ctrl->mtfa)
4237 fw_act_timeout = jiffies +
4238 msecs_to_jiffies(ctrl->mtfa * 100);
4239 else
4240 fw_act_timeout = jiffies +
4241 msecs_to_jiffies(admin_timeout * 1000);
4242
9f27bd70 4243 nvme_quiesce_io_queues(ctrl);
b6dccf7f
AD		 4244 while (nvme_ctrl_pp_status(ctrl)) {
4245 if (time_after(jiffies, fw_act_timeout)) {
4246 dev_warn(ctrl->device,
4247 "Fw activation timeout, reset controller\n");
4c75f877
KB		 4248 nvme_try_sched_reset(ctrl);
4249 return;
b6dccf7f
AD		 4250 }
4251 msleep(100);
4252 }
4253
4c75f877 4254 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE))
b6dccf7f
AD		 4255 return;
4256
9f27bd70 4257 nvme_unquiesce_io_queues(ctrl);
a806c6c8 4258 /* read FW slot information to clear the AER */
b6dccf7f 4259 nvme_get_fw_slot_info(ctrl);
371a982c
KB		 4260
4261 queue_work(nvme_wq, &ctrl->async_event_work);
b6dccf7f
AD		 4262}
4263
2c61c97f
MK		 4264static u32 nvme_aer_type(u32 result)
4265{
4266 return result & 0x7;
4267}
4268
4269static u32 nvme_aer_subtype(u32 result)
4270{
4271 return (result & 0xff00) >> 8;
4272}
4273
371a982c 4274static bool nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
868c2392 4275{
2c61c97f 4276 u32 aer_notice_type = nvme_aer_subtype(result);
371a982c 4277 bool requeue = true;
09bd1ff4
CK		 4278
4279 switch (aer_notice_type) {
868c2392 4280 case NVME_AER_NOTICE_NS_CHANGED:
77016199 4281 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 4282 nvme_queue_scan(ctrl);
4283 break;
4284 case NVME_AER_NOTICE_FW_ACT_STARTING:
4c75f877
KB		 4285 /*
4286 * We are (ab)using the RESETTING state to prevent subsequent
4287 * recovery actions from interfering with the controller's
4288 * firmware activation.
4289 */
f50fff73 4290 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) {
371a982c 4291 requeue = false;
4c75f877 4292 queue_work(nvme_wq, &ctrl->fw_act_work);
f50fff73 4293 }
868c2392 4294 break;
0d0b660f
CH		 4295#ifdef CONFIG_NVME_MULTIPATH
4296 case NVME_AER_NOTICE_ANA:
4297 if (!ctrl->ana_log_buf)
4298 break;
4299 queue_work(nvme_wq, &ctrl->ana_work);
4300 break;
4301#endif
85f8a435
SG		 4302 case NVME_AER_NOTICE_DISC_CHANGED:
4303 ctrl->aen_result = result;
4304 break;
868c2392
CH		 4305 default:
4306 dev_warn(ctrl->device, "async event result %08x\n", result);
4307 }
371a982c 4308 return requeue;
868c2392
CH		 4309}
4310
2c61c97f
MK		 4311static void nvme_handle_aer_persistent_error(struct nvme_ctrl *ctrl)
4312{
2c61c97f
MK		 4313 dev_warn(ctrl->device, "resetting controller due to AER\n");
4314 nvme_reset_ctrl(ctrl);
4315}
4316
7bf58533 4317void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 4318 volatile union nvme_result *res)
f866fc42 4319{
7bf58533 4320 u32 result = le32_to_cpu(res->u32);
2c61c97f
MK		 4321 u32 aer_type = nvme_aer_type(result);
4322 u32 aer_subtype = nvme_aer_subtype(result);
371a982c 4323 bool requeue = true;
f866fc42 4324
ad22c355 4325 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 4326 return;
4327
6622b76f 4328 trace_nvme_async_event(ctrl, result);
09bd1ff4 4329 switch (aer_type) {
868c2392 4330 case NVME_AER_NOTICE:
371a982c 4331 requeue = nvme_handle_aen_notice(ctrl, result);
868c2392 4332 break;
e3d7874d 4333 case NVME_AER_ERROR:
2c61c97f
MK		 4334 /*
4335 * For a persistent internal error, don't run async_event_work
4336 * to submit a new AER. The controller reset will do it.
4337 */
4338 if (aer_subtype == NVME_AER_ERROR_PERSIST_INT_ERR) {
4339 nvme_handle_aer_persistent_error(ctrl);
4340 return;
4341 }
4342 fallthrough;
e3d7874d
KB		 4343 case NVME_AER_SMART:
4344 case NVME_AER_CSS:
4345 case NVME_AER_VS:
4346 ctrl->aen_result = result;
7bf58533
CH		 4347 break;
4348 default:
4349 break;
f866fc42 4350 }
371a982c
KB		 4351
4352 if (requeue)
4353 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 4354}
f866fc42 4355EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 4356
fe60e8c5 4357int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
db45e1a5 4358 const struct blk_mq_ops *ops, unsigned int cmd_size)
fe60e8c5
CH		 4359{
4360 int ret;
4361
4362 memset(set, 0, sizeof(*set));
4363 set->ops = ops;
4364 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
4365 if (ctrl->ops->flags & NVME_F_FABRICS)
4366 set->reserved_tags = NVMF_RESERVED_TAGS;
4367 set->numa_node = ctrl->numa_node;
db45e1a5
CH		 4368 set->flags = BLK_MQ_F_NO_SCHED;
4369 if (ctrl->ops->flags & NVME_F_BLOCKING)
4370 set->flags |= BLK_MQ_F_BLOCKING;
fe60e8c5
CH		 4371 set->cmd_size = cmd_size;
4372 set->driver_data = ctrl;
4373 set->nr_hw_queues = 1;
4374 set->timeout = NVME_ADMIN_TIMEOUT;
4375 ret = blk_mq_alloc_tag_set(set);
4376 if (ret)
4377 return ret;
4378
9ac4dd8c 4379 ctrl->admin_q = blk_mq_alloc_queue(set, NULL, NULL);
fe60e8c5
CH		 4380 if (IS_ERR(ctrl->admin_q)) {
4381 ret = PTR_ERR(ctrl->admin_q);
4382 goto out_free_tagset;
4383 }
4384
4385 if (ctrl->ops->flags & NVME_F_FABRICS) {
9ac4dd8c 4386 ctrl->fabrics_q = blk_mq_alloc_queue(set, NULL, NULL);
fe60e8c5
CH		 4387 if (IS_ERR(ctrl->fabrics_q)) {
4388 ret = PTR_ERR(ctrl->fabrics_q);
4389 goto out_cleanup_admin_q;
4390 }
4391 }
4392
4393 ctrl->admin_tagset = set;
4394 return 0;
4395
4396out_cleanup_admin_q:
4739824e 4397 blk_mq_destroy_queue(ctrl->admin_q);
2b3f056f 4398 blk_put_queue(ctrl->admin_q);
fe60e8c5 4399out_free_tagset:
fd62678a
ML		 4400 blk_mq_free_tag_set(set);
4401 ctrl->admin_q = NULL;
4402 ctrl->fabrics_q = NULL;
fe60e8c5
CH		 4403 return ret;
4404}
4405EXPORT_SYMBOL_GPL(nvme_alloc_admin_tag_set);
4406
4407void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl)
4408{
4409 blk_mq_destroy_queue(ctrl->admin_q);
2b3f056f
CH		 4410 blk_put_queue(ctrl->admin_q);
4411 if (ctrl->ops->flags & NVME_F_FABRICS) {
fe60e8c5 4412 blk_mq_destroy_queue(ctrl->fabrics_q);
2b3f056f
CH		 4413 blk_put_queue(ctrl->fabrics_q);
4414 }
fe60e8c5
CH		 4415 blk_mq_free_tag_set(ctrl->admin_tagset);
4416}
4417EXPORT_SYMBOL_GPL(nvme_remove_admin_tag_set);
4418
4419int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
db45e1a5 4420 const struct blk_mq_ops *ops, unsigned int nr_maps,
fe60e8c5
CH		 4421 unsigned int cmd_size)
4422{
4423 int ret;
4424
4425 memset(set, 0, sizeof(*set));
4426 set->ops = ops;
33b93727 4427 set->queue_depth = min_t(unsigned, ctrl->sqsize, BLK_MQ_MAX_DEPTH - 1);
93b24f57
CH		 4428 /*
4429 * Some Apple controllers requires tags to be unique across admin and
4430 * the (only) I/O queue, so reserve the first 32 tags of the I/O queue.
4431 */
4432 if (ctrl->quirks & NVME_QUIRK_SHARED_TAGS)
4433 set->reserved_tags = NVME_AQ_DEPTH;
4434 else if (ctrl->ops->flags & NVME_F_FABRICS)
b794d1c2 4435 set->reserved_tags = NVMF_RESERVED_TAGS;
fe60e8c5 4436 set->numa_node = ctrl->numa_node;
db45e1a5
CH		 4437 set->flags = BLK_MQ_F_SHOULD_MERGE;
4438 if (ctrl->ops->flags & NVME_F_BLOCKING)
4439 set->flags |= BLK_MQ_F_BLOCKING;
fe60e8c5
CH		 4440 set->cmd_size = cmd_size,
4441 set->driver_data = ctrl;
4442 set->nr_hw_queues = ctrl->queue_count - 1;
4443 set->timeout = NVME_IO_TIMEOUT;
dcef7727 4444 set->nr_maps = nr_maps;
fe60e8c5
CH		 4445 ret = blk_mq_alloc_tag_set(set);
4446 if (ret)
4447 return ret;
4448
4449 if (ctrl->ops->flags & NVME_F_FABRICS) {
9ac4dd8c 4450 ctrl->connect_q = blk_mq_alloc_queue(set, NULL, NULL);
fe60e8c5
CH		 4451 if (IS_ERR(ctrl->connect_q)) {
4452 ret = PTR_ERR(ctrl->connect_q);
4453 goto out_free_tag_set;
4454 }
98d81f0d
CL		 4455 blk_queue_flag_set(QUEUE_FLAG_SKIP_TAGSET_QUIESCE,
4456 ctrl->connect_q);
fe60e8c5
CH		 4457 }
4458
4459 ctrl->tagset = set;
4460 return 0;
4461
4462out_free_tag_set:
4463 blk_mq_free_tag_set(set);
6fbf13c0 4464 ctrl->connect_q = NULL;
fe60e8c5
CH		 4465 return ret;
4466}
4467EXPORT_SYMBOL_GPL(nvme_alloc_io_tag_set);
4468
4469void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl)
4470{
2b3f056f 4471 if (ctrl->ops->flags & NVME_F_FABRICS) {
fe60e8c5 4472 blk_mq_destroy_queue(ctrl->connect_q);
2b3f056f
CH		 4473 blk_put_queue(ctrl->connect_q);
4474 }
fe60e8c5
CH		 4475 blk_mq_free_tag_set(ctrl->tagset);
4476}
4477EXPORT_SYMBOL_GPL(nvme_remove_io_tag_set);
4478
d09f2b45 4479void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 4480{
0d0b660f 4481 nvme_mpath_stop(ctrl);
f50fff73 4482 nvme_auth_stop(ctrl);
3af755a4 4483 nvme_stop_keep_alive(ctrl);
8c4dfea9 4484 nvme_stop_failfast_work(ctrl);
f866fc42 4485 flush_work(&ctrl->async_event_work);
b6dccf7f 4486 cancel_work_sync(&ctrl->fw_act_work);
f7f70f4a
RL		 4487 if (ctrl->ops->stop_ctrl)
4488 ctrl->ops->stop_ctrl(ctrl);
d09f2b45
SG		 4489}
4490EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
4491
4492void nvme_start_ctrl(struct nvme_ctrl *ctrl)
4493{
93da4023
SG		 4494 nvme_enable_aen(ctrl);
4495
f46ef9e8
SG		 4496 /*
4497 * persistent discovery controllers need to send indication to userspace
4498 * to re-read the discovery log page to learn about possible changes
4499 * that were missed. We identify persistent discovery controllers by
4500 * checking that they started once before, hence are reconnecting back.
4501 */
2eb94dd5 4502 if (test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) &&
f46ef9e8
SG		 4503 nvme_discovery_ctrl(ctrl))
4504 nvme_change_uevent(ctrl, "NVME_EVENT=rediscover");
4505
d09f2b45
SG		 4506 if (ctrl->queue_count > 1) {
4507 nvme_queue_scan(ctrl);
9f27bd70 4508 nvme_unquiesce_io_queues(ctrl);
a4a6f3c8 4509 nvme_mpath_update(ctrl);
d09f2b45 4510 }
20d64911
MB		 4511
4512 nvme_change_uevent(ctrl, "NVME_EVENT=connected");
2eb94dd5 4513 set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags);
d09f2b45
SG		 4514}
4515EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 4516
d09f2b45
SG		 4517void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
4518{
ed7770f6 4519 nvme_hwmon_exit(ctrl);
f79d5fda 4520 nvme_fault_inject_fini(&ctrl->fault_inject);
510a405d 4521 dev_pm_qos_hide_latency_tolerance(ctrl->device);
a6a5149b 4522 cdev_device_del(&ctrl->cdev, ctrl->device);
726612b6 4523 nvme_put_ctrl(ctrl);
53029b04 4524}
576d55d6 4525EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 4526
8168d23f
KB		 4527static void nvme_free_cels(struct nvme_ctrl *ctrl)
4528{
4529 struct nvme_effects_log *cel;
4530 unsigned long i;
4531
8f8ea928 4532 xa_for_each(&ctrl->cels, i, cel) {
8168d23f
KB		 4533 xa_erase(&ctrl->cels, i);
4534 kfree(cel);
4535 }
4536
4537 xa_destroy(&ctrl->cels);
4538}
4539
d22524a4 4540static void nvme_free_ctrl(struct device *dev)
53029b04 4541{
d22524a4
CH		 4542 struct nvme_ctrl *ctrl =
4543 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 4544 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 4545
192f6c29 4546 if (!subsys || ctrl->instance != subsys->instance)
8b850475 4547 ida_free(&nvme_instance_ida, ctrl->instance);
be8e82ca 4548 key_put(ctrl->tls_key);
8168d23f 4549 nvme_free_cels(ctrl);
0d0b660f 4550 nvme_mpath_uninit(ctrl);
f50fff73
HR		 4551 nvme_auth_stop(ctrl);
4552 nvme_auth_free(ctrl);
092ff052 4553 __free_page(ctrl->discard_page);
94cc781f 4554 free_opal_dev(ctrl->opal_dev);
f3ca80fc 4555
ab9e00cc 4556 if (subsys) {
32fd90c4 4557 mutex_lock(&nvme_subsystems_lock);
ab9e00cc 4558 list_del(&ctrl->subsys_entry);
ab9e00cc 4559 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
32fd90c4 4560 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 4561 }
f3ca80fc
CH		 4562
4563 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 4564
ab9e00cc
CH		 4565 if (subsys)
4566 nvme_put_subsystem(subsys);
f3ca80fc
CH		 4567}
4568
4569/*
4570 * Initialize a NVMe controller structures. This needs to be called during
4571 * earliest initialization so that we have the initialized structured around
4572 * during probing.
4573 */
4574int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
4575 const struct nvme_ctrl_ops *ops, unsigned long quirks)
4576{
4577 int ret;
4578
e6e7f7ac 4579 WRITE_ONCE(ctrl->state, NVME_CTRL_NEW);
9f079dda 4580 ctrl->passthru_err_log_enabled = false;
8c4dfea9 4581 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
bb8d261e 4582 spin_lock_init(&ctrl->lock);
e7ad43c3 4583 mutex_init(&ctrl->scan_lock);
f3ca80fc 4584 INIT_LIST_HEAD(&ctrl->namespaces);
1cf7a12e 4585 xa_init(&ctrl->cels);
765cc031 4586 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 4587 ctrl->dev = dev;
4588 ctrl->ops = ops;
4589 ctrl->quirks = quirks;
4fea243e 4590 ctrl->numa_node = NUMA_NO_NODE;
5955be21 4591 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 4592 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 4593 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 4594 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
c1ac9a4b 4595 init_waitqueue_head(&ctrl->state_wq);
f3ca80fc 4596
230f1f9e 4597 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
8c4dfea9 4598 INIT_DELAYED_WORK(&ctrl->failfast_work, nvme_failfast_work);
230f1f9e
JS		 4599 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
4600 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
136cfcb8 4601 ctrl->ka_last_check_time = jiffies;
230f1f9e 4602
cb5b7262
JA		 4603 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
4604 PAGE_SIZE);
4605 ctrl->discard_page = alloc_page(GFP_KERNEL);
4606 if (!ctrl->discard_page) {
4607 ret = -ENOMEM;
4608 goto out;
4609 }
4610
8b850475 4611 ret = ida_alloc(&nvme_instance_ida, GFP_KERNEL);
9843f685 4612 if (ret < 0)
f3ca80fc 4613 goto out;
9843f685 4614 ctrl->instance = ret;
f3ca80fc 4615
d22524a4
CH		 4616 device_initialize(&ctrl->ctrl_device);
4617 ctrl->device = &ctrl->ctrl_device;
f68abd9c
JG		 4618 ctrl->device->devt = MKDEV(MAJOR(nvme_ctrl_base_chr_devt),
4619 ctrl->instance);
d22524a4
CH		 4620 ctrl->device->class = nvme_class;
4621 ctrl->device->parent = ctrl->dev;
86adbf0c
CH		 4622 if (ops->dev_attr_groups)
4623 ctrl->device->groups = ops->dev_attr_groups;
4624 else
4625 ctrl->device->groups = nvme_dev_attr_groups;
d22524a4
CH		 4626 ctrl->device->release = nvme_free_ctrl;
4627 dev_set_drvdata(ctrl->device, ctrl);
4628 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
4629 if (ret)
f3ca80fc 4630 goto out_release_instance;
f3ca80fc 4631
b780d741 4632 nvme_get_ctrl(ctrl);
a6a5149b
CH		 4633 cdev_init(&ctrl->cdev, &nvme_dev_fops);
4634 ctrl->cdev.owner = ops->module;
4635 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 4636 if (ret)
4637 goto out_free_name;
f3ca80fc 4638
c5552fde
AL		 4639 /*
4640 * Initialize latency tolerance controls. The sysfs files won't
4641 * be visible to userspace unless the device actually supports APST.
4642 */
4643 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
4644 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
4645 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
4646
f79d5fda 4647 nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device));
5e1f6899 4648 nvme_mpath_init_ctrl(ctrl);
193a8c7e
SG		 4649 ret = nvme_auth_init_ctrl(ctrl);
4650 if (ret)
4651 goto out_free_cdev;
f79d5fda 4652
f3ca80fc 4653 return 0;
193a8c7e 4654out_free_cdev:
3a12a0b8 4655 nvme_fault_inject_fini(&ctrl->fault_inject);
7ed5cf8e 4656 dev_pm_qos_hide_latency_tolerance(ctrl->device);
193a8c7e 4657 cdev_device_del(&ctrl->cdev, ctrl->device);
d22524a4 4658out_free_name:
b780d741 4659 nvme_put_ctrl(ctrl);
d6a2b953 4660 kfree_const(ctrl->device->kobj.name);
f3ca80fc 4661out_release_instance:
8b850475 4662 ida_free(&nvme_instance_ida, ctrl->instance);
f3ca80fc 4663out:
cb5b7262
JA		 4664 if (ctrl->discard_page)
4665 __free_page(ctrl->discard_page);
f3ca80fc
CH		 4666 return ret;
4667}
576d55d6 4668EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 4669
cd50f9b2
CH		 4670/* let I/O to all namespaces fail in preparation for surprise removal */
4671void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl)
69d9a99c
KB		 4672{
4673 struct nvme_ns *ns;
4674
765cc031 4675 down_read(&ctrl->namespaces_rwsem);
cf39a6bc 4676 list_for_each_entry(ns, &ctrl->namespaces, list)
cd50f9b2 4677 blk_mark_disk_dead(ns->disk);
765cc031 4678 up_read(&ctrl->namespaces_rwsem);
69d9a99c 4679}
cd50f9b2 4680EXPORT_SYMBOL_GPL(nvme_mark_namespaces_dead);
69d9a99c 4681
302ad8cc
KB		 4682void nvme_unfreeze(struct nvme_ctrl *ctrl)
4683{
4684 struct nvme_ns *ns;
4685
765cc031 4686 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4687 list_for_each_entry(ns, &ctrl->namespaces, list)
4688 blk_mq_unfreeze_queue(ns->queue);
765cc031 4689 up_read(&ctrl->namespaces_rwsem);
839a40d1 4690 clear_bit(NVME_CTRL_FROZEN, &ctrl->flags);
302ad8cc
KB		 4691}
4692EXPORT_SYMBOL_GPL(nvme_unfreeze);
4693
7cf0d7c0 4694int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
302ad8cc
KB		 4695{
4696 struct nvme_ns *ns;
4697
765cc031 4698 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4699 list_for_each_entry(ns, &ctrl->namespaces, list) {
4700 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
4701 if (timeout <= 0)
4702 break;
4703 }
765cc031 4704 up_read(&ctrl->namespaces_rwsem);
7cf0d7c0 4705 return timeout;
302ad8cc
KB		 4706}
4707EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
4708
4709void nvme_wait_freeze(struct nvme_ctrl *ctrl)
4710{
4711 struct nvme_ns *ns;
4712
765cc031 4713 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4714 list_for_each_entry(ns, &ctrl->namespaces, list)
4715 blk_mq_freeze_queue_wait(ns->queue);
765cc031 4716 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4717}
4718EXPORT_SYMBOL_GPL(nvme_wait_freeze);
4719
4720void nvme_start_freeze(struct nvme_ctrl *ctrl)
4721{
4722 struct nvme_ns *ns;
4723
839a40d1 4724 set_bit(NVME_CTRL_FROZEN, &ctrl->flags);
765cc031 4725 down_read(&ctrl->namespaces_rwsem);
302ad8cc 4726 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 4727 blk_freeze_queue_start(ns->queue);
765cc031 4728 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4729}
4730EXPORT_SYMBOL_GPL(nvme_start_freeze);
4731
9f27bd70 4732void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl)
363c9aac 4733{
ba0718a6
CH		 4734 if (!ctrl->tagset)
4735 return;
98d81f0d
CL		 4736 if (!test_and_set_bit(NVME_CTRL_STOPPED, &ctrl->flags))
4737 blk_mq_quiesce_tagset(ctrl->tagset);
4738 else
4739 blk_mq_wait_quiesce_done(ctrl->tagset);
363c9aac 4740}
9f27bd70 4741EXPORT_SYMBOL_GPL(nvme_quiesce_io_queues);
363c9aac 4742
9f27bd70 4743void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl)
363c9aac 4744{
ba0718a6
CH		 4745 if (!ctrl->tagset)
4746 return;
98d81f0d
CL		 4747 if (test_and_clear_bit(NVME_CTRL_STOPPED, &ctrl->flags))
4748 blk_mq_unquiesce_tagset(ctrl->tagset);
363c9aac 4749}
9f27bd70 4750EXPORT_SYMBOL_GPL(nvme_unquiesce_io_queues);
363c9aac 4751
9f27bd70 4752void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl)
a277654b 4753{
9e6a6b12
ML		 4754 if (!test_and_set_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags))
4755 blk_mq_quiesce_queue(ctrl->admin_q);
26af1cd0 4756 else
483239c7 4757 blk_mq_wait_quiesce_done(ctrl->admin_q->tag_set);
a277654b 4758}
9f27bd70 4759EXPORT_SYMBOL_GPL(nvme_quiesce_admin_queue);
a277654b 4760
9f27bd70 4761void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl)
a277654b 4762{
9e6a6b12
ML		 4763 if (test_and_clear_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags))
4764 blk_mq_unquiesce_queue(ctrl->admin_q);
a277654b 4765}
9f27bd70 4766EXPORT_SYMBOL_GPL(nvme_unquiesce_admin_queue);
a277654b 4767
04800fbf 4768void nvme_sync_io_queues(struct nvme_ctrl *ctrl)
d6135c3a
KB		 4769{
4770 struct nvme_ns *ns;
4771
4772 down_read(&ctrl->namespaces_rwsem);
4773 list_for_each_entry(ns, &ctrl->namespaces, list)
4774 blk_sync_queue(ns->queue);
4775 up_read(&ctrl->namespaces_rwsem);
04800fbf
CL		 4776}
4777EXPORT_SYMBOL_GPL(nvme_sync_io_queues);
03894b7a 4778
04800fbf
CL		 4779void nvme_sync_queues(struct nvme_ctrl *ctrl)
4780{
4781 nvme_sync_io_queues(ctrl);
03894b7a
EN		 4782 if (ctrl->admin_q)
4783 blk_sync_queue(ctrl->admin_q);
d6135c3a
KB		 4784}
4785EXPORT_SYMBOL_GPL(nvme_sync_queues);
4786
b2702aaa 4787struct nvme_ctrl *nvme_ctrl_from_file(struct file *file)
f783f444 4788{
b2702aaa
CK		 4789 if (file->f_op != &nvme_dev_fops)
4790 return NULL;
4791 return file->private_data;
f783f444 4792}
b2702aaa 4793EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, NVME_TARGET_PASSTHRU);
f783f444 4794
81101540
CH		 4795/*
4796 * Check we didn't inadvertently grow the command structure sizes:
4797 */
4798static inline void _nvme_check_size(void)
4799{
4800 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64);
4801 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
4802 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64);
4803 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
4804 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64);
4805 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
4806 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64);
4807 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64);
4808 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
4809 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64);
4810 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
4811 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
4812 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
354201c5
CH		 4813 BUILD_BUG_ON(sizeof(struct nvme_id_ns_cs_indep) !=
4814 NVME_IDENTIFY_DATA_SIZE);
240e6ee2 4815 BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE);
4020aad8 4816 BUILD_BUG_ON(sizeof(struct nvme_id_ns_nvm) != NVME_IDENTIFY_DATA_SIZE);
240e6ee2 4817 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE);
5befc7c2 4818 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_nvm) != NVME_IDENTIFY_DATA_SIZE);
81101540
CH		 4819 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
4820 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
4821 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
4822 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64);
4020aad8 4823 BUILD_BUG_ON(sizeof(struct nvme_feat_host_behavior) != 512);
81101540
CH		 4824}
4825
4826
893a74b7 4827static int __init nvme_core_init(void)
5bae7f73 4828{
b227c59b 4829 int result = -ENOMEM;
5bae7f73 4830
81101540
CH		 4831 _nvme_check_size();
4832
9a6327d2
SG		 4833 nvme_wq = alloc_workqueue("nvme-wq",
4834 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4835 if (!nvme_wq)
b227c59b
RS		 4836 goto out;
4837
4838 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
4839 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4840 if (!nvme_reset_wq)
4841 goto destroy_wq;
4842
4843 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
4844 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4845 if (!nvme_delete_wq)
4846 goto destroy_reset_wq;
9a6327d2 4847
f68abd9c
JG		 4848 result = alloc_chrdev_region(&nvme_ctrl_base_chr_devt, 0,
4849 NVME_MINORS, "nvme");
f3ca80fc 4850 if (result < 0)
b227c59b 4851 goto destroy_delete_wq;
f3ca80fc 4852
1aaba11d 4853 nvme_class = class_create("nvme");
f3ca80fc
CH		 4854 if (IS_ERR(nvme_class)) {
4855 result = PTR_ERR(nvme_class);
4856 goto unregister_chrdev;
4857 }
a42f42e5 4858 nvme_class->dev_uevent = nvme_class_uevent;
f3ca80fc 4859
1aaba11d 4860 nvme_subsys_class = class_create("nvme-subsystem");
ab9e00cc
CH		 4861 if (IS_ERR(nvme_subsys_class)) {
4862 result = PTR_ERR(nvme_subsys_class);
4863 goto destroy_class;
4864 }
2637baed
MI		 4865
4866 result = alloc_chrdev_region(&nvme_ns_chr_devt, 0, NVME_MINORS,
4867 "nvme-generic");
4868 if (result < 0)
4869 goto destroy_subsys_class;
4870
1aaba11d 4871 nvme_ns_chr_class = class_create("nvme-generic");
2637baed
MI		 4872 if (IS_ERR(nvme_ns_chr_class)) {
4873 result = PTR_ERR(nvme_ns_chr_class);
4874 goto unregister_generic_ns;
4875 }
9d77eb52
HR		 4876 result = nvme_init_auth();
4877 if (result)
706add13 4878 goto destroy_ns_chr;
5bae7f73 4879 return 0;
f3ca80fc 4880
e481fc0a
SG		 4881destroy_ns_chr:
4882 class_destroy(nvme_ns_chr_class);
2637baed
MI		 4883unregister_generic_ns:
4884 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
4885destroy_subsys_class:
4886 class_destroy(nvme_subsys_class);
ab9e00cc
CH		 4887destroy_class:
4888 class_destroy(nvme_class);
9a6327d2 4889unregister_chrdev:
f68abd9c 4890 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS		 4891destroy_delete_wq:
4892 destroy_workqueue(nvme_delete_wq);
4893destroy_reset_wq:
4894 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 4895destroy_wq:
4896 destroy_workqueue(nvme_wq);
b227c59b 4897out:
f3ca80fc 4898 return result;
5bae7f73
CH		 4899}
4900
893a74b7 4901static void __exit nvme_core_exit(void)
5bae7f73 4902{
e481fc0a 4903 nvme_exit_auth();
2637baed 4904 class_destroy(nvme_ns_chr_class);
ab9e00cc 4905 class_destroy(nvme_subsys_class);
f3ca80fc 4906 class_destroy(nvme_class);
2637baed 4907 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
f68abd9c 4908 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS		 4909 destroy_workqueue(nvme_delete_wq);
4910 destroy_workqueue(nvme_reset_wq);
9a6327d2 4911 destroy_workqueue(nvme_wq);
2637baed 4912 ida_destroy(&nvme_ns_chr_minor_ida);
f41cfd5d 4913 ida_destroy(&nvme_instance_ida);
5bae7f73 4914}
576d55d6
ML		 4915
4916MODULE_LICENSE("GPL");
4917MODULE_VERSION("1.0");
92b0b0ff 4918MODULE_DESCRIPTION("NVMe host core framework");
576d55d6
ML		 4919module_init(nvme_core_init);
4920module_exit(nvme_core_exit);
Linux 6.x block layer and io_uring tree(s)