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Merge tag 'for-6.10/block-20240511' of git://git.kernel.dk/linux
[linux-2.6-block.git] / drivers / nvme / host / core.c
CommitLineData
bc50ad75 1// SPDX-License-Identifier: GPL-2.0
21d34711
CH		 2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
21d34711
CH		 5 */
6
7#include <linux/blkdev.h>
8#include <linux/blk-mq.h>
fe45e630 9#include <linux/blk-integrity.h>
c95b708d 10#include <linux/compat.h>
5fd4ce1b 11#include <linux/delay.h>
21d34711 12#include <linux/errno.h>
1673f1f0 13#include <linux/hdreg.h>
21d34711 14#include <linux/kernel.h>
5bae7f73 15#include <linux/module.h>
958f2a0f 16#include <linux/backing-dev.h>
21d34711
CH		 17#include <linux/slab.h>
18#include <linux/types.h>
1673f1f0
CH		 19#include <linux/pr.h>
20#include <linux/ptrace.h>
21#include <linux/nvme_ioctl.h>
c5552fde 22#include <linux/pm_qos.h>
a1a825ab 23#include <linux/ratelimit.h>
1673f1f0 24#include <asm/unaligned.h>
21d34711
CH		 25
26#include "nvme.h"
038bd4cb 27#include "fabrics.h"
f50fff73 28#include <linux/nvme-auth.h>
21d34711 29
35fe0d12
HR		 30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
f3ca80fc
CH		 33#define NVME_MINORS (1U << MINORBITS)
34
1a893c2b
CH		 35struct nvme_ns_info {
36 struct nvme_ns_ids ids;
37 u32 nsid;
38 __le32 anagrpid;
39 bool is_shared;
1e4ea66a 40 bool is_readonly;
1a893c2b 41 bool is_ready;
0dd6fff2 42 bool is_removed;
1a893c2b
CH		 43};
44
8ae4e447
MO		 45unsigned int admin_timeout = 60;
46module_param(admin_timeout, uint, 0644);
ba0ba7d3 47MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 48EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 49
8ae4e447
MO		 50unsigned int nvme_io_timeout = 30;
51module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 52MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 53EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 54
b3b1b0b0 55static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 56module_param(shutdown_timeout, byte, 0644);
57MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
58
44e44b29
CH		 59static u8 nvme_max_retries = 5;
60module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 61MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 62
9947d6a0 63static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 64module_param(default_ps_max_latency_us, ulong, 0644);
65MODULE_PARM_DESC(default_ps_max_latency_us,
66 "max power saving latency for new devices; use PM QOS to change per device");
67
c35e30b4
AL		 68static bool force_apst;
69module_param(force_apst, bool, 0644);
70MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
71
ebd8a93a
AB		 72static unsigned long apst_primary_timeout_ms = 100;
73module_param(apst_primary_timeout_ms, ulong, 0644);
74MODULE_PARM_DESC(apst_primary_timeout_ms,
75 "primary APST timeout in ms");
76
77static unsigned long apst_secondary_timeout_ms = 2000;
78module_param(apst_secondary_timeout_ms, ulong, 0644);
79MODULE_PARM_DESC(apst_secondary_timeout_ms,
80 "secondary APST timeout in ms");
81
82static unsigned long apst_primary_latency_tol_us = 15000;
83module_param(apst_primary_latency_tol_us, ulong, 0644);
84MODULE_PARM_DESC(apst_primary_latency_tol_us,
85 "primary APST latency tolerance in us");
86
87static unsigned long apst_secondary_latency_tol_us = 100000;
88module_param(apst_secondary_latency_tol_us, ulong, 0644);
89MODULE_PARM_DESC(apst_secondary_latency_tol_us,
90 "secondary APST latency tolerance in us");
91
b227c59b
RS		 92/*
93 * nvme_wq - hosts nvme related works that are not reset or delete
94 * nvme_reset_wq - hosts nvme reset works
95 * nvme_delete_wq - hosts nvme delete works
96 *
97b2512a
NK		 97 * nvme_wq will host works such as scan, aen handling, fw activation,
98 * keep-alive, periodic reconnects etc. nvme_reset_wq
b227c59b
RS		 99 * runs reset works which also flush works hosted on nvme_wq for
100 * serialization purposes. nvme_delete_wq host controller deletion
101 * works which flush reset works for serialization.
102 */
9a6327d2
SG		 103struct workqueue_struct *nvme_wq;
104EXPORT_SYMBOL_GPL(nvme_wq);
105
b227c59b
RS		 106struct workqueue_struct *nvme_reset_wq;
107EXPORT_SYMBOL_GPL(nvme_reset_wq);
108
109struct workqueue_struct *nvme_delete_wq;
110EXPORT_SYMBOL_GPL(nvme_delete_wq);
111
ab9e00cc
CH		 112static LIST_HEAD(nvme_subsystems);
113static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 114
9843f685 115static DEFINE_IDA(nvme_instance_ida);
f68abd9c 116static dev_t nvme_ctrl_base_chr_devt;
ab21f3d9
RM		 117static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env);
118static const struct class nvme_class = {
119 .name = "nvme",
120 .dev_uevent = nvme_class_uevent,
121};
122
123static const struct class nvme_subsys_class = {
124 .name = "nvme-subsystem",
125};
f3ca80fc 126
2637baed
MI		 127static DEFINE_IDA(nvme_ns_chr_minor_ida);
128static dev_t nvme_ns_chr_devt;
ab21f3d9
RM		 129static const struct class nvme_ns_chr_class = {
130 .name = "nvme-generic",
131};
2637baed 132
12d9f070 133static void nvme_put_subsystem(struct nvme_subsystem *subsys);
cf39a6bc
SB		 134static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
135 unsigned nsid);
b58da2d2
TS		 136static void nvme_update_keep_alive(struct nvme_ctrl *ctrl,
137 struct nvme_command *cmd);
cf39a6bc 138
2405252a 139void nvme_queue_scan(struct nvme_ctrl *ctrl)
50e8d8ee
CH		 140{
141 /*
142 * Only new queue scan work when admin and IO queues are both alive
143 */
e6e7f7ac 144 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE && ctrl->tagset)
50e8d8ee
CH		 145 queue_work(nvme_wq, &ctrl->scan_work);
146}
147
4c75f877
KB		 148/*
149 * Use this function to proceed with scheduling reset_work for a controller
150 * that had previously been set to the resetting state. This is intended for
151 * code paths that can't be interrupted by other reset attempts. A hot removal
152 * may prevent this from succeeding.
153 */
c1ac9a4b 154int nvme_try_sched_reset(struct nvme_ctrl *ctrl)
4c75f877 155{
e6e7f7ac 156 if (nvme_ctrl_state(ctrl) != NVME_CTRL_RESETTING)
4c75f877
KB		 157 return -EBUSY;
158 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
159 return -EBUSY;
160 return 0;
161}
c1ac9a4b 162EXPORT_SYMBOL_GPL(nvme_try_sched_reset);
4c75f877 163
8c4dfea9
VG		 164static void nvme_failfast_work(struct work_struct *work)
165{
166 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
167 struct nvme_ctrl, failfast_work);
168
e6e7f7ac 169 if (nvme_ctrl_state(ctrl) != NVME_CTRL_CONNECTING)
8c4dfea9
VG		 170 return;
171
172 set_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
173 dev_info(ctrl->device, "failfast expired\n");
174 nvme_kick_requeue_lists(ctrl);
175}
176
177static inline void nvme_start_failfast_work(struct nvme_ctrl *ctrl)
178{
179 if (!ctrl->opts || ctrl->opts->fast_io_fail_tmo == -1)
180 return;
181
182 schedule_delayed_work(&ctrl->failfast_work,
183 ctrl->opts->fast_io_fail_tmo * HZ);
184}
185
186static inline void nvme_stop_failfast_work(struct nvme_ctrl *ctrl)
187{
188 if (!ctrl->opts)
189 return;
190
191 cancel_delayed_work_sync(&ctrl->failfast_work);
192 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
193}
194
195
d86c4d8e
CH		 196int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
197{
198 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
199 return -EBUSY;
b227c59b 200 if (!queue_work(nvme_reset_wq, &ctrl->reset_work))
d86c4d8e
CH		 201 return -EBUSY;
202 return 0;
203}
204EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
205
2405252a 206int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
d86c4d8e
CH		 207{
208 int ret;
209
210 ret = nvme_reset_ctrl(ctrl);
8000d1fd 211 if (!ret) {
d86c4d8e 212 flush_work(&ctrl->reset_work);
e6e7f7ac 213 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
8000d1fd
NC		 214 ret = -ENETRESET;
215 }
216
d86c4d8e
CH		 217 return ret;
218}
219
a686ed75 220static void nvme_do_delete_ctrl(struct nvme_ctrl *ctrl)
c5017e85 221{
77d0612d 222 dev_info(ctrl->device,
e5ea42fa 223 "Removing ctrl: NQN \"%s\"\n", nvmf_ctrl_subsysnqn(ctrl));
77d0612d 224
4054637c 225 flush_work(&ctrl->reset_work);
6cd53d14
CH		 226 nvme_stop_ctrl(ctrl);
227 nvme_remove_namespaces(ctrl);
c5017e85 228 ctrl->ops->delete_ctrl(ctrl);
6cd53d14 229 nvme_uninit_ctrl(ctrl);
c5017e85
CH		 230}
231
a686ed75
BVA		 232static void nvme_delete_ctrl_work(struct work_struct *work)
233{
234 struct nvme_ctrl *ctrl =
235 container_of(work, struct nvme_ctrl, delete_work);
236
237 nvme_do_delete_ctrl(ctrl);
238}
239
c5017e85
CH		 240int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
241{
242 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
243 return -EBUSY;
b227c59b 244 if (!queue_work(nvme_delete_wq, &ctrl->delete_work))
c5017e85
CH		 245 return -EBUSY;
246 return 0;
247}
248EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
249
942e21c0 250void nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
c5017e85 251{
c5017e85 252 /*
01fc08ff
YY		 253 * Keep a reference until nvme_do_delete_ctrl() complete,
254 * since ->delete_ctrl can free the controller.
c5017e85
CH		 255 */
256 nvme_get_ctrl(ctrl);
6721c18a 257 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
b9c77583 258 nvme_do_delete_ctrl(ctrl);
c5017e85 259 nvme_put_ctrl(ctrl);
c5017e85 260}
c5017e85 261
2f9c1736 262static blk_status_t nvme_error_status(u16 status)
27fa9bc5 263{
2f9c1736 264 switch (status & 0x7ff) {
27fa9bc5 265 case NVME_SC_SUCCESS:
2a842aca 266 return BLK_STS_OK;
27fa9bc5 267 case NVME_SC_CAP_EXCEEDED:
2a842aca 268 return BLK_STS_NOSPC;
e96fef2c 269 case NVME_SC_LBA_RANGE:
35038bff
KB		 270 case NVME_SC_CMD_INTERRUPTED:
271 case NVME_SC_NS_NOT_READY:
e96fef2c
KB		 272 return BLK_STS_TARGET;
273 case NVME_SC_BAD_ATTRIBUTES:
e02ab023 274 case NVME_SC_ONCS_NOT_SUPPORTED:
e96fef2c
KB		 275 case NVME_SC_INVALID_OPCODE:
276 case NVME_SC_INVALID_FIELD:
277 case NVME_SC_INVALID_NS:
2a842aca 278 return BLK_STS_NOTSUPP;
e02ab023
JG		 279 case NVME_SC_WRITE_FAULT:
280 case NVME_SC_READ_ERROR:
281 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 282 case NVME_SC_ACCESS_DENIED:
283 case NVME_SC_READ_ONLY:
e96fef2c 284 case NVME_SC_COMPARE_FAILED:
2a842aca 285 return BLK_STS_MEDIUM;
a751da33
CH		 286 case NVME_SC_GUARD_CHECK:
287 case NVME_SC_APPTAG_CHECK:
288 case NVME_SC_REFTAG_CHECK:
289 case NVME_SC_INVALID_PI:
290 return BLK_STS_PROTECTION;
291 case NVME_SC_RESERVATION_CONFLICT:
7ba15083 292 return BLK_STS_RESV_CONFLICT;
1c0d12c0
SG		 293 case NVME_SC_HOST_PATH_ERROR:
294 return BLK_STS_TRANSPORT;
afaf5c6c
KB		 295 case NVME_SC_ZONE_TOO_MANY_ACTIVE:
296 return BLK_STS_ZONE_ACTIVE_RESOURCE;
297 case NVME_SC_ZONE_TOO_MANY_OPEN:
298 return BLK_STS_ZONE_OPEN_RESOURCE;
2a842aca
CH		 299 default:
300 return BLK_STS_IOERR;
27fa9bc5
CH		 301 }
302}
27fa9bc5 303
49cd84b6
KB		 304static void nvme_retry_req(struct request *req)
305{
49cd84b6
KB		 306 unsigned long delay = 0;
307 u16 crd;
308
309 /* The mask and shift result must be <= 3 */
310 crd = (nvme_req(req)->status & NVME_SC_CRD) >> 11;
f9063a53
MI		 311 if (crd)
312 delay = nvme_req(req)->ctrl->crdt[crd - 1] * 100;
49cd84b6
KB		 313
314 nvme_req(req)->retries++;
315 blk_mq_requeue_request(req, false);
316 blk_mq_delay_kick_requeue_list(req->q, delay);
317}
318
bd83fe6f
AA		 319static void nvme_log_error(struct request *req)
320{
321 struct nvme_ns *ns = req->q->queuedata;
322 struct nvme_request *nr = nvme_req(req);
323
324 if (ns) {
9419e71b 325 pr_err_ratelimited("%s: %s(0x%x) @ LBA %llu, %u blocks, %s (sct 0x%x / sc 0x%x) %s%s\n",
bd83fe6f
AA		 326 ns->disk ? ns->disk->disk_name : "?",
327 nvme_get_opcode_str(nr->cmd->common.opcode),
328 nr->cmd->common.opcode,
0372dd4e 329 nvme_sect_to_lba(ns->head, blk_rq_pos(req)),
9419e71b 330 blk_rq_bytes(req) >> ns->head->lba_shift,
bd83fe6f
AA		 331 nvme_get_error_status_str(nr->status),
332 nr->status >> 8 & 7, /* Status Code Type */
333 nr->status & 0xff, /* Status Code */
334 nr->status & NVME_SC_MORE ? "MORE " : "",
335 nr->status & NVME_SC_DNR ? "DNR " : "");
336 return;
337 }
338
339 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s\n",
340 dev_name(nr->ctrl->device),
341 nvme_get_admin_opcode_str(nr->cmd->common.opcode),
342 nr->cmd->common.opcode,
343 nvme_get_error_status_str(nr->status),
344 nr->status >> 8 & 7, /* Status Code Type */
345 nr->status & 0xff, /* Status Code */
346 nr->status & NVME_SC_MORE ? "MORE " : "",
347 nr->status & NVME_SC_DNR ? "DNR " : "");
348}
349
9f079dda
AA		 350static void nvme_log_err_passthru(struct request *req)
351{
352 struct nvme_ns *ns = req->q->queuedata;
353 struct nvme_request *nr = nvme_req(req);
354
355 pr_err_ratelimited("%s: %s(0x%x), %s (sct 0x%x / sc 0x%x) %s%s"
356 "cdw10=0x%x cdw11=0x%x cdw12=0x%x cdw13=0x%x cdw14=0x%x cdw15=0x%x\n",
357 ns ? ns->disk->disk_name : dev_name(nr->ctrl->device),
358 ns ? nvme_get_opcode_str(nr->cmd->common.opcode) :
359 nvme_get_admin_opcode_str(nr->cmd->common.opcode),
360 nr->cmd->common.opcode,
361 nvme_get_error_status_str(nr->status),
362 nr->status >> 8 & 7, /* Status Code Type */
363 nr->status & 0xff, /* Status Code */
364 nr->status & NVME_SC_MORE ? "MORE " : "",
365 nr->status & NVME_SC_DNR ? "DNR " : "",
366 nr->cmd->common.cdw10,
367 nr->cmd->common.cdw11,
368 nr->cmd->common.cdw12,
369 nr->cmd->common.cdw13,
370 nr->cmd->common.cdw14,
371 nr->cmd->common.cdw14);
372}
373
5ddaabe8
CH		 374enum nvme_disposition {
375 COMPLETE,
376 RETRY,
377 FAILOVER,
f50fff73 378 AUTHENTICATE,
5ddaabe8
CH		 379};
380
381static inline enum nvme_disposition nvme_decide_disposition(struct request *req)
77f02a7a 382{
5ddaabe8
CH		 383 if (likely(nvme_req(req)->status == 0))
384 return COMPLETE;
908e4564 385
f50fff73
HR		 386 if ((nvme_req(req)->status & 0x7ff) == NVME_SC_AUTH_REQUIRED)
387 return AUTHENTICATE;
388
5ddaabe8
CH		 389 if (blk_noretry_request(req) ||
390 (nvme_req(req)->status & NVME_SC_DNR) ||
391 nvme_req(req)->retries >= nvme_max_retries)
392 return COMPLETE;
ca5554a6 393
5ddaabe8 394 if (req->cmd_flags & REQ_NVME_MPATH) {
5eac5f33
CL		 395 if (nvme_is_path_error(nvme_req(req)->status) ||
396 blk_queue_dying(req->q))
5ddaabe8 397 return FAILOVER;
5eac5f33
CL		 398 } else {
399 if (blk_queue_dying(req->q))
400 return COMPLETE;
5ddaabe8 401 }
16686f3a 402
5ddaabe8
CH		 403 return RETRY;
404}
6e3ca03e 405
c234a653 406static inline void nvme_end_req_zoned(struct request *req)
5ddaabe8 407{
5ddaabe8 408 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
0372dd4e
DW		 409 req_op(req) == REQ_OP_ZONE_APPEND) {
410 struct nvme_ns *ns = req->q->queuedata;
411
412 req->__sector = nvme_lba_to_sect(ns->head,
240e6ee2 413 le64_to_cpu(nvme_req(req)->result.u64));
0372dd4e 414 }
c234a653
JA		 415}
416
417static inline void nvme_end_req(struct request *req)
418{
419 blk_status_t status = nvme_error_status(nvme_req(req)->status);
35fe0d12 420
9f079dda
AA		 421 if (unlikely(nvme_req(req)->status && !(req->rq_flags & RQF_QUIET))) {
422 if (blk_rq_is_passthrough(req))
423 nvme_log_err_passthru(req);
424 else
425 nvme_log_error(req);
426 }
c234a653 427 nvme_end_req_zoned(req);
2b59787a 428 nvme_trace_bio_complete(req);
d4d957b5
SG		 429 if (req->cmd_flags & REQ_NVME_MPATH)
430 nvme_mpath_end_request(req);
908e4564 431 blk_mq_end_request(req, status);
77f02a7a 432}
5ddaabe8
CH		 433
434void nvme_complete_rq(struct request *req)
435{
f50fff73
HR		 436 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
437
5ddaabe8
CH		 438 trace_nvme_complete_rq(req);
439 nvme_cleanup_cmd(req);
440
774a9636
US		 441 /*
442 * Completions of long-running commands should not be able to
443 * defer sending of periodic keep alives, since the controller
444 * may have completed processing such commands a long time ago
445 * (arbitrarily close to command submission time).
446 * req->deadline - req->timeout is the command submission time
447 * in jiffies.
448 */
449 if (ctrl->kas &&
450 req->deadline - req->timeout >= ctrl->ka_last_check_time)
f50fff73 451 ctrl->comp_seen = true;
5ddaabe8
CH		 452
453 switch (nvme_decide_disposition(req)) {
454 case COMPLETE:
455 nvme_end_req(req);
456 return;
457 case RETRY:
458 nvme_retry_req(req);
459 return;
460 case FAILOVER:
461 nvme_failover_req(req);
462 return;
f50fff73 463 case AUTHENTICATE:
d6800634 464#ifdef CONFIG_NVME_HOST_AUTH
f50fff73
HR		 465 queue_work(nvme_wq, &ctrl->dhchap_auth_work);
466 nvme_retry_req(req);
467#else
468 nvme_end_req(req);
469#endif
470 return;
5ddaabe8
CH		 471 }
472}
77f02a7a
CH		 473EXPORT_SYMBOL_GPL(nvme_complete_rq);
474
c234a653
JA		 475void nvme_complete_batch_req(struct request *req)
476{
00e757b6 477 trace_nvme_complete_rq(req);
c234a653
JA		 478 nvme_cleanup_cmd(req);
479 nvme_end_req_zoned(req);
480}
481EXPORT_SYMBOL_GPL(nvme_complete_batch_req);
482
dda3248e
CL		 483/*
484 * Called to unwind from ->queue_rq on a failed command submission so that the
485 * multipathing code gets called to potentially failover to another path.
486 * The caller needs to unwind all transport specific resource allocations and
487 * must return propagate the return value.
488 */
489blk_status_t nvme_host_path_error(struct request *req)
490{
491 nvme_req(req)->status = NVME_SC_HOST_PATH_ERROR;
492 blk_mq_set_request_complete(req);
493 nvme_complete_rq(req);
494 return BLK_STS_OK;
495}
496EXPORT_SYMBOL_GPL(nvme_host_path_error);
497
2dd6532e 498bool nvme_cancel_request(struct request *req, void *data)
c55a2fd4 499{
c55a2fd4
ML		 500 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
501 "Cancelling I/O %d", req->tag);
502
d4f1d5f7
LY		 503 /* don't abort one completed or idle request */
504 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT)
78ca4072
ML		 505 return true;
506
2dc3947b 507 nvme_req(req)->status = NVME_SC_HOST_ABORTED_CMD;
d3589381 508 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
15f73f5b 509 blk_mq_complete_request(req);
7baa8572 510 return true;
c55a2fd4
ML		 511}
512EXPORT_SYMBOL_GPL(nvme_cancel_request);
513
25479069
CL		 514void nvme_cancel_tagset(struct nvme_ctrl *ctrl)
515{
516 if (ctrl->tagset) {
517 blk_mq_tagset_busy_iter(ctrl->tagset,
518 nvme_cancel_request, ctrl);
519 blk_mq_tagset_wait_completed_request(ctrl->tagset);
520 }
521}
522EXPORT_SYMBOL_GPL(nvme_cancel_tagset);
523
524void nvme_cancel_admin_tagset(struct nvme_ctrl *ctrl)
525{
526 if (ctrl->admin_tagset) {
527 blk_mq_tagset_busy_iter(ctrl->admin_tagset,
528 nvme_cancel_request, ctrl);
529 blk_mq_tagset_wait_completed_request(ctrl->admin_tagset);
530 }
531}
532EXPORT_SYMBOL_GPL(nvme_cancel_admin_tagset);
533
bb8d261e
CH		 534bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
535 enum nvme_ctrl_state new_state)
536{
f6b6a28e 537 enum nvme_ctrl_state old_state;
0a72bbba 538 unsigned long flags;
bb8d261e
CH		 539 bool changed = false;
540
0a72bbba 541 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e 542
e6e7f7ac 543 old_state = nvme_ctrl_state(ctrl);
bb8d261e
CH		 544 switch (new_state) {
545 case NVME_CTRL_LIVE:
546 switch (old_state) {
7d2e8008 547 case NVME_CTRL_NEW:
bb8d261e 548 case NVME_CTRL_RESETTING:
ad6a0a52 549 case NVME_CTRL_CONNECTING:
bb8d261e 550 changed = true;
df561f66 551 fallthrough;
bb8d261e
CH		 552 default:
553 break;
554 }
555 break;
556 case NVME_CTRL_RESETTING:
557 switch (old_state) {
558 case NVME_CTRL_NEW:
def61eca 559 case NVME_CTRL_LIVE:
def61eca 560 changed = true;
df561f66 561 fallthrough;
def61eca
CH		 562 default:
563 break;
564 }
565 break;
ad6a0a52 566 case NVME_CTRL_CONNECTING:
def61eca 567 switch (old_state) {
b754a32c 568 case NVME_CTRL_NEW:
3cec7f9d 569 case NVME_CTRL_RESETTING:
bb8d261e 570 changed = true;
df561f66 571 fallthrough;
bb8d261e
CH		 572 default:
573 break;
574 }
575 break;
576 case NVME_CTRL_DELETING:
577 switch (old_state) {
578 case NVME_CTRL_LIVE:
579 case NVME_CTRL_RESETTING:
ad6a0a52 580 case NVME_CTRL_CONNECTING:
bb8d261e 581 changed = true;
df561f66 582 fallthrough;
bb8d261e
CH		 583 default:
584 break;
585 }
586 break;
ecca390e
SG		 587 case NVME_CTRL_DELETING_NOIO:
588 switch (old_state) {
589 case NVME_CTRL_DELETING:
590 case NVME_CTRL_DEAD:
591 changed = true;
df561f66 592 fallthrough;
ecca390e
SG		 593 default:
594 break;
595 }
596 break;
0ff9d4e1
KB		 597 case NVME_CTRL_DEAD:
598 switch (old_state) {
599 case NVME_CTRL_DELETING:
600 changed = true;
df561f66 601 fallthrough;
0ff9d4e1
KB		 602 default:
603 break;
604 }
605 break;
bb8d261e
CH		 606 default:
607 break;
608 }
bb8d261e 609
c1ac9a4b 610 if (changed) {
e6e7f7ac 611 WRITE_ONCE(ctrl->state, new_state);
c1ac9a4b
KB		 612 wake_up_all(&ctrl->state_wq);
613 }
bb8d261e 614
0a72bbba 615 spin_unlock_irqrestore(&ctrl->lock, flags);
8c4dfea9
VG		 616 if (!changed)
617 return false;
618
e6e7f7ac 619 if (new_state == NVME_CTRL_LIVE) {
8c4dfea9
VG		 620 if (old_state == NVME_CTRL_CONNECTING)
621 nvme_stop_failfast_work(ctrl);
32acab31 622 nvme_kick_requeue_lists(ctrl);
e6e7f7ac 623 } else if (new_state == NVME_CTRL_CONNECTING &&
8c4dfea9
VG		 624 old_state == NVME_CTRL_RESETTING) {
625 nvme_start_failfast_work(ctrl);
626 }
bb8d261e
CH		 627 return changed;
628}
629EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
630
c1ac9a4b
KB		 631/*
632 * Waits for the controller state to be resetting, or returns false if it is
633 * not possible to ever transition to that state.
634 */
635bool nvme_wait_reset(struct nvme_ctrl *ctrl)
636{
637 wait_event(ctrl->state_wq,
638 nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING) ||
639 nvme_state_terminal(ctrl));
e6e7f7ac 640 return nvme_ctrl_state(ctrl) == NVME_CTRL_RESETTING;
c1ac9a4b
KB		 641}
642EXPORT_SYMBOL_GPL(nvme_wait_reset);
643
ed754e5d
CH		 644static void nvme_free_ns_head(struct kref *ref)
645{
646 struct nvme_ns_head *head =
647 container_of(ref, struct nvme_ns_head, ref);
648
32acab31 649 nvme_mpath_remove_disk(head);
8b850475 650 ida_free(&head->subsys->ns_ida, head->instance);
f5ad3991 651 cleanup_srcu_struct(&head->srcu);
12d9f070 652 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 653 kfree(head);
654}
655
1496bd49 656bool nvme_tryget_ns_head(struct nvme_ns_head *head)
871ca3ef
CH		 657{
658 return kref_get_unless_zero(&head->ref);
659}
660
1496bd49 661void nvme_put_ns_head(struct nvme_ns_head *head)
ed754e5d
CH		 662{
663 kref_put(&head->ref, nvme_free_ns_head);
664}
665
1673f1f0
CH		 666static void nvme_free_ns(struct kref *kref)
667{
668 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
669
1673f1f0 670 put_disk(ns->disk);
ed754e5d 671 nvme_put_ns_head(ns->head);
075790eb 672 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 673 kfree(ns);
674}
675
4c74d1f8
KJ		 676static inline bool nvme_get_ns(struct nvme_ns *ns)
677{
678 return kref_get_unless_zero(&ns->kref);
679}
680
24493b8b 681void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 682{
683 kref_put(&ns->kref, nvme_free_ns);
684}
24493b8b 685EXPORT_SYMBOL_NS_GPL(nvme_put_ns, NVME_TARGET_PASSTHRU);
1673f1f0 686
bb06ec31
JS		 687static inline void nvme_clear_nvme_request(struct request *req)
688{
ae5e6886 689 nvme_req(req)->status = 0;
c03fd85d
CK		 690 nvme_req(req)->retries = 0;
691 nvme_req(req)->flags = 0;
692 req->rq_flags |= RQF_DONTPREP;
bb06ec31
JS		 693}
694
e559398f
CH		 695/* initialize a passthrough request */
696void nvme_init_request(struct request *req, struct nvme_command *cmd)
39dfe844 697{
9f079dda
AA		 698 struct nvme_request *nr = nvme_req(req);
699 bool logging_enabled;
700
701 if (req->q->queuedata) {
702 struct nvme_ns *ns = req->q->disk->private_data;
703
1f4137e8 704 logging_enabled = ns->head->passthru_err_log_enabled;
0d2e7c84 705 req->timeout = NVME_IO_TIMEOUT;
9f079dda
AA		 706 } else { /* no queuedata implies admin queue */
707 logging_enabled = nr->ctrl->passthru_err_log_enabled;
dc96f938 708 req->timeout = NVME_ADMIN_TIMEOUT;
9f079dda
AA		 709 }
710
711 if (!logging_enabled)
712 req->rq_flags |= RQF_QUIET;
21d34711 713
f4b9e6c9
KB		 714 /* passthru commands should let the driver set the SGL flags */
715 cmd->common.flags &= ~NVME_CMD_SGL_ALL;
716
21d34711 717 req->cmd_flags |= REQ_FAILFAST_DRIVER;
be42a33b 718 if (req->mq_hctx->type == HCTX_TYPE_POLL)
6ce913fe 719 req->cmd_flags |= REQ_POLLED;
bb06ec31 720 nvme_clear_nvme_request(req);
9f079dda 721 memcpy(nr->cmd, cmd, sizeof(*cmd));
39dfe844 722}
e559398f 723EXPORT_SYMBOL_GPL(nvme_init_request);
39dfe844 724
a9715744
TC		 725/*
726 * For something we're not in a state to send to the device the default action
727 * is to busy it and retry it after the controller state is recovered. However,
728 * if the controller is deleting or if anything is marked for failfast or
729 * nvme multipath it is immediately failed.
730 *
731 * Note: commands used to initialize the controller will be marked for failfast.
732 * Note: nvme cli/ioctl commands are marked for failfast.
733 */
734blk_status_t nvme_fail_nonready_command(struct nvme_ctrl *ctrl,
735 struct request *rq)
736{
e6e7f7ac
KB		 737 enum nvme_ctrl_state state = nvme_ctrl_state(ctrl);
738
739 if (state != NVME_CTRL_DELETING_NOIO &&
740 state != NVME_CTRL_DELETING &&
741 state != NVME_CTRL_DEAD &&
a9715744
TC		 742 !test_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags) &&
743 !blk_noretry_request(rq) && !(rq->cmd_flags & REQ_NVME_MPATH))
744 return BLK_STS_RESOURCE;
745 return nvme_host_path_error(rq);
746}
747EXPORT_SYMBOL_GPL(nvme_fail_nonready_command);
748
749bool __nvme_check_ready(struct nvme_ctrl *ctrl, struct request *rq,
6d3c7fb1 750 bool queue_live, enum nvme_ctrl_state state)
a9715744
TC		 751{
752 struct nvme_request *req = nvme_req(rq);
753
754 /*
755 * currently we have a problem sending passthru commands
756 * on the admin_q if the controller is not LIVE because we can't
757 * make sure that they are going out after the admin connect,
758 * controller enable and/or other commands in the initialization
759 * sequence. until the controller will be LIVE, fail with
760 * BLK_STS_RESOURCE so that they will be rescheduled.
761 */
762 if (rq->q == ctrl->admin_q && (req->flags & NVME_REQ_USERCMD))
763 return false;
764
765 if (ctrl->ops->flags & NVME_F_FABRICS) {
766 /*
767 * Only allow commands on a live queue, except for the connect
768 * command, which is require to set the queue live in the
769 * appropinquate states.
770 */
6d3c7fb1 771 switch (state) {
a9715744
TC		 772 case NVME_CTRL_CONNECTING:
773 if (blk_rq_is_passthrough(rq) && nvme_is_fabrics(req->cmd) &&
f50fff73
HR		 774 (req->cmd->fabrics.fctype == nvme_fabrics_type_connect ||
775 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_send ||
776 req->cmd->fabrics.fctype == nvme_fabrics_type_auth_receive))
a9715744
TC		 777 return true;
778 break;
779 default:
780 break;
781 case NVME_CTRL_DEAD:
782 return false;
783 }
784 }
785
786 return queue_live;
787}
788EXPORT_SYMBOL_GPL(__nvme_check_ready);
789
8093f7ca
ML		 790static inline void nvme_setup_flush(struct nvme_ns *ns,
791 struct nvme_command *cmnd)
792{
9c3d2929 793 memset(cmnd, 0, sizeof(*cmnd));
8093f7ca 794 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 795 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 796}
797
fc17b653 798static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 799 struct nvme_command *cmnd)
800{
b35ba01e 801 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 802 struct nvme_dsm_range *range;
b35ba01e 803 struct bio *bio;
8093f7ca 804
530436c4
EH		 805 /*
806 * Some devices do not consider the DSM 'Number of Ranges' field when
807 * determining how much data to DMA. Always allocate memory for maximum
808 * number of segments to prevent device reading beyond end of buffer.
809 */
810 static const size_t alloc_size = sizeof(*range) * NVME_DSM_MAX_RANGES;
811
812 range = kzalloc(alloc_size, GFP_ATOMIC | __GFP_NOWARN);
cb5b7262
JA		 813 if (!range) {
814 /*
815 * If we fail allocation our range, fallback to the controller
816 * discard page. If that's also busy, it's safe to return
817 * busy, as we know we can make progress once that's freed.
818 */
819 if (test_and_set_bit_lock(0, &ns->ctrl->discard_page_busy))
820 return BLK_STS_RESOURCE;
821
822 range = page_address(ns->ctrl->discard_page);
823 }
8093f7ca 824
37f0dc2e 825 if (queue_max_discard_segments(req->q) == 1) {
0372dd4e 826 u64 slba = nvme_sect_to_lba(ns->head, blk_rq_pos(req));
9419e71b 827 u32 nlb = blk_rq_sectors(req) >> (ns->head->lba_shift - 9);
37f0dc2e
ML		 828
829 range[0].cattr = cpu_to_le32(0);
830 range[0].nlb = cpu_to_le32(nlb);
831 range[0].slba = cpu_to_le64(slba);
832 n = 1;
833 } else {
834 __rq_for_each_bio(bio, req) {
0372dd4e
DW		 835 u64 slba = nvme_sect_to_lba(ns->head,
836 bio->bi_iter.bi_sector);
9419e71b 837 u32 nlb = bio->bi_iter.bi_size >> ns->head->lba_shift;
37f0dc2e
ML		 838
839 if (n < segments) {
840 range[n].cattr = cpu_to_le32(0);
841 range[n].nlb = cpu_to_le32(nlb);
842 range[n].slba = cpu_to_le64(slba);
843 }
844 n++;
8cb6af7b 845 }
b35ba01e
CH		 846 }
847
848 if (WARN_ON_ONCE(n != segments)) {
cb5b7262
JA		 849 if (virt_to_page(range) == ns->ctrl->discard_page)
850 clear_bit_unlock(0, &ns->ctrl->discard_page_busy);
851 else
852 kfree(range);
fc17b653 853 return BLK_STS_IOERR;
b35ba01e 854 }
8093f7ca 855
9c3d2929 856 memset(cmnd, 0, sizeof(*cmnd));
8093f7ca 857 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 858 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 859 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 860 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
861
4bee16da 862 bvec_set_virt(&req->special_vec, range, alloc_size);
f9d03f96 863 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 864
fc17b653 865 return BLK_STS_OK;
8093f7ca 866}
8093f7ca 867
4020aad8
KB		 868static void nvme_set_ref_tag(struct nvme_ns *ns, struct nvme_command *cmnd,
869 struct request *req)
870{
871 u32 upper, lower;
872 u64 ref48;
873
874 /* both rw and write zeroes share the same reftag format */
9419e71b 875 switch (ns->head->guard_type) {
4020aad8
KB		 876 case NVME_NVM_NS_16B_GUARD:
877 cmnd->rw.reftag = cpu_to_le32(t10_pi_ref_tag(req));
878 break;
879 case NVME_NVM_NS_64B_GUARD:
880 ref48 = ext_pi_ref_tag(req);
881 lower = lower_32_bits(ref48);
882 upper = upper_32_bits(ref48);
883
884 cmnd->rw.reftag = cpu_to_le32(lower);
885 cmnd->rw.cdw3 = cpu_to_le32(upper);
886 break;
887 default:
888 break;
889 }
890}
891
6e02318e
CK		 892static inline blk_status_t nvme_setup_write_zeroes(struct nvme_ns *ns,
893 struct request *req, struct nvme_command *cmnd)
894{
9c3d2929
JA		 895 memset(cmnd, 0, sizeof(*cmnd));
896
6e02318e
CK		 897 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
898 return nvme_setup_discard(ns, req, cmnd);
899
900 cmnd->write_zeroes.opcode = nvme_cmd_write_zeroes;
901 cmnd->write_zeroes.nsid = cpu_to_le32(ns->head->ns_id);
902 cmnd->write_zeroes.slba =
0372dd4e 903 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req)));
6e02318e 904 cmnd->write_zeroes.length =
9419e71b 905 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1);
00b33cf3 906
9419e71b
DW		 907 if (!(req->cmd_flags & REQ_NOUNMAP) &&
908 (ns->head->features & NVME_NS_DEAC))
1b96f862
CH		 909 cmnd->write_zeroes.control |= cpu_to_le16(NVME_WZ_DEAC);
910
0372dd4e 911 if (nvme_ns_has_pi(ns->head)) {
1b96f862 912 cmnd->write_zeroes.control |= cpu_to_le16(NVME_RW_PRINFO_PRACT);
00b33cf3 913
9419e71b 914 switch (ns->head->pi_type) {
00b33cf3
KJ		 915 case NVME_NS_DPS_PI_TYPE1:
916 case NVME_NS_DPS_PI_TYPE2:
4020aad8 917 nvme_set_ref_tag(ns, cmnd, req);
00b33cf3
KJ		 918 break;
919 }
920 }
921
6e02318e
CK		 922 return BLK_STS_OK;
923}
924
ebe6d874 925static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
240e6ee2
KB		 926 struct request *req, struct nvme_command *cmnd,
927 enum nvme_opcode op)
8093f7ca
ML		 928{
929 u16 control = 0;
930 u32 dsmgmt = 0;
931
932 if (req->cmd_flags & REQ_FUA)
933 control |= NVME_RW_FUA;
934 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
935 control |= NVME_RW_LR;
936
937 if (req->cmd_flags & REQ_RAHEAD)
938 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
939
240e6ee2 940 cmnd->rw.opcode = op;
a9a7e30f 941 cmnd->rw.flags = 0;
ed754e5d 942 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
4020aad8
KB		 943 cmnd->rw.cdw2 = 0;
944 cmnd->rw.cdw3 = 0;
a9a7e30f 945 cmnd->rw.metadata = 0;
0372dd4e
DW		 946 cmnd->rw.slba =
947 cpu_to_le64(nvme_sect_to_lba(ns->head, blk_rq_pos(req)));
9419e71b
DW		 948 cmnd->rw.length =
949 cpu_to_le16((blk_rq_bytes(req) >> ns->head->lba_shift) - 1);
a9a7e30f
JA		 950 cmnd->rw.reftag = 0;
951 cmnd->rw.apptag = 0;
952 cmnd->rw.appmask = 0;
8093f7ca 953
9419e71b 954 if (ns->head->ms) {
715ea9e0
CH		 955 /*
956 * If formated with metadata, the block layer always provides a
957 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
958 * we enable the PRACT bit for protection information or set the
959 * namespace capacity to zero to prevent any I/O.
960 */
961 if (!blk_integrity_rq(req)) {
0372dd4e 962 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns->head)))
715ea9e0
CH		 963 return BLK_STS_NOTSUPP;
964 control |= NVME_RW_PRINFO_PRACT;
965 }
966
9419e71b 967 switch (ns->head->pi_type) {
8093f7ca
ML		 968 case NVME_NS_DPS_PI_TYPE3:
969 control |= NVME_RW_PRINFO_PRCHK_GUARD;
970 break;
971 case NVME_NS_DPS_PI_TYPE1:
972 case NVME_NS_DPS_PI_TYPE2:
973 control |= NVME_RW_PRINFO_PRCHK_GUARD |
974 NVME_RW_PRINFO_PRCHK_REF;
240e6ee2
KB		 975 if (op == nvme_cmd_zone_append)
976 control |= NVME_RW_APPEND_PIREMAP;
4020aad8 977 nvme_set_ref_tag(ns, cmnd, req);
8093f7ca
ML		 978 break;
979 }
8093f7ca
ML		 980 }
981
982 cmnd->rw.control = cpu_to_le16(control);
983 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 984 return 0;
8093f7ca
ML		 985}
986
f7f1fc36
MG		 987void nvme_cleanup_cmd(struct request *req)
988{
f7f1fc36 989 if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
fc97e942 990 struct nvme_ctrl *ctrl = nvme_req(req)->ctrl;
cb5b7262 991
3973e15f 992 if (req->special_vec.bv_page == ctrl->discard_page)
fc97e942 993 clear_bit_unlock(0, &ctrl->discard_page_busy);
cb5b7262 994 else
3973e15f 995 kfree(bvec_virt(&req->special_vec));
f7f1fc36
MG		 996 }
997}
998EXPORT_SYMBOL_GPL(nvme_cleanup_cmd);
999
f4b9e6c9 1000blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req)
8093f7ca 1001{
f4b9e6c9 1002 struct nvme_command *cmd = nvme_req(req)->cmd;
fc17b653 1003 blk_status_t ret = BLK_STS_OK;
8093f7ca 1004
9c3d2929 1005 if (!(req->rq_flags & RQF_DONTPREP))
c03fd85d 1006 nvme_clear_nvme_request(req);
987f699a 1007
aebf526b
CH		 1008 switch (req_op(req)) {
1009 case REQ_OP_DRV_IN:
1010 case REQ_OP_DRV_OUT:
f4b9e6c9 1011 /* these are setup prior to execution in nvme_init_request() */
aebf526b
CH		 1012 break;
1013 case REQ_OP_FLUSH:
8093f7ca 1014 nvme_setup_flush(ns, cmd);
aebf526b 1015 break;
240e6ee2
KB		 1016 case REQ_OP_ZONE_RESET_ALL:
1017 case REQ_OP_ZONE_RESET:
1018 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_RESET);
1019 break;
1020 case REQ_OP_ZONE_OPEN:
1021 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_OPEN);
1022 break;
1023 case REQ_OP_ZONE_CLOSE:
1024 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_CLOSE);
1025 break;
1026 case REQ_OP_ZONE_FINISH:
1027 ret = nvme_setup_zone_mgmt_send(ns, req, cmd, NVME_ZONE_FINISH);
1028 break;
e850fd16 1029 case REQ_OP_WRITE_ZEROES:
6e02318e
CK		 1030 ret = nvme_setup_write_zeroes(ns, req, cmd);
1031 break;
aebf526b 1032 case REQ_OP_DISCARD:
8093f7ca 1033 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 1034 break;
1035 case REQ_OP_READ:
240e6ee2
KB		 1036 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_read);
1037 break;
aebf526b 1038 case REQ_OP_WRITE:
240e6ee2
KB		 1039 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_write);
1040 break;
1041 case REQ_OP_ZONE_APPEND:
1042 ret = nvme_setup_rw(ns, req, cmd, nvme_cmd_zone_append);
aebf526b
CH		 1043 break;
1044 default:
1045 WARN_ON_ONCE(1);
fc17b653 1046 return BLK_STS_IOERR;
aebf526b 1047 }
8093f7ca 1048
e7006de6 1049 cmd->common.command_id = nvme_cid(req);
5d87eb94 1050 trace_nvme_setup_cmd(req, cmd);
8093f7ca
ML		 1051 return ret;
1052}
1053EXPORT_SYMBOL_GPL(nvme_setup_cmd);
1054
ae5e6886
KB		 1055/*
1056 * Return values:
1057 * 0: success
1058 * >0: nvme controller's cqe status response
1059 * <0: kernel error in lieu of controller response
1060 */
62281b9e 1061int nvme_execute_rq(struct request *rq, bool at_head)
ae5e6886
KB		 1062{
1063 blk_status_t status;
1064
b84ba30b 1065 status = blk_execute_rq(rq, at_head);
ae5e6886
KB		 1066 if (nvme_req(rq)->flags & NVME_REQ_CANCELLED)
1067 return -EINTR;
1068 if (nvme_req(rq)->status)
1069 return nvme_req(rq)->status;
1070 return blk_status_to_errno(status);
1071}
62281b9e 1072EXPORT_SYMBOL_NS_GPL(nvme_execute_rq, NVME_TARGET_PASSTHRU);
ae5e6886 1073
4160982e
CH		 1074/*
1075 * Returns 0 on success. If the result is negative, it's a Linux error code;
1076 * if the result is positive, it's an NVM Express status code
1077 */
1078int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 1079 union nvme_result *result, void *buffer, unsigned bufflen,
bd2687f2 1080 int qid, nvme_submit_flags_t flags)
4160982e
CH		 1081{
1082 struct request *req;
1083 int ret;
bd2687f2 1084 blk_mq_req_flags_t blk_flags = 0;
4160982e 1085
bd2687f2
HR		 1086 if (flags & NVME_SUBMIT_NOWAIT)
1087 blk_flags |= BLK_MQ_REQ_NOWAIT;
1088 if (flags & NVME_SUBMIT_RESERVED)
1089 blk_flags |= BLK_MQ_REQ_RESERVED;
39dfe844 1090 if (qid == NVME_QID_ANY)
bd2687f2 1091 req = blk_mq_alloc_request(q, nvme_req_op(cmd), blk_flags);
39dfe844 1092 else
bd2687f2 1093 req = blk_mq_alloc_request_hctx(q, nvme_req_op(cmd), blk_flags,
b10907b8 1094 qid - 1);
e559398f 1095
4160982e
CH		 1096 if (IS_ERR(req))
1097 return PTR_ERR(req);
e559398f 1098 nvme_init_request(req, cmd);
48dae466
HR		 1099 if (flags & NVME_SUBMIT_RETRY)
1100 req->cmd_flags &= ~REQ_FAILFAST_DRIVER;
4160982e 1101
21d34711
CH		 1102 if (buffer && bufflen) {
1103 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
1104 if (ret)
1105 goto out;
4160982e
CH		 1106 }
1107
bd2687f2 1108 ret = nvme_execute_rq(req, flags & NVME_SUBMIT_AT_HEAD);
ae5e6886 1109 if (result && ret >= 0)
d49187e9 1110 *result = nvme_req(req)->result;
4160982e
CH		 1111 out:
1112 blk_mq_free_request(req);
1113 return ret;
1114}
eb71f435 1115EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 1116
1117int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1118 void *buffer, unsigned bufflen)
1119{
6b46fa02 1120 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen,
bd2687f2 1121 NVME_QID_ANY, 0);
4160982e 1122}
576d55d6 1123EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 1124
df21b6b1
LG		 1125u32 nvme_command_effects(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
1126{
1127 u32 effects = 0;
1128
1129 if (ns) {
cc115cbe 1130 effects = le32_to_cpu(ns->head->effects->iocs[opcode]);
df21b6b1 1131 if (effects & ~(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC))
ed4a854b 1132 dev_warn_once(ctrl->device,
831ed60c 1133 "IO command:%02x has unusual effects:%08x\n",
ed4a854b 1134 opcode, effects);
df21b6b1 1135
831ed60c
CH		 1136 /*
1137 * NVME_CMD_EFFECTS_CSE_MASK causes a freeze all I/O queues,
1138 * which would deadlock when done on an I/O command. Note that
1139 * We already warn about an unusual effect above.
1140 */
1141 effects &= ~NVME_CMD_EFFECTS_CSE_MASK;
1142 } else {
cc115cbe 1143 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
29f69753
KB		 1144
1145 /* Ignore execution restrictions if any relaxation bits are set */
1146 if (effects & NVME_CMD_EFFECTS_CSER_MASK)
1147 effects &= ~NVME_CMD_EFFECTS_CSE_MASK;
831ed60c 1148 }
df21b6b1
LG		 1149
1150 return effects;
1151}
1152EXPORT_SYMBOL_NS_GPL(nvme_command_effects, NVME_TARGET_PASSTHRU);
1153
62281b9e 1154u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u8 opcode)
df21b6b1
LG		 1155{
1156 u32 effects = nvme_command_effects(ctrl, ns, opcode);
1157
1158 /*
1159 * For simplicity, IO to all namespaces is quiesced even if the command
1160 * effects say only one namespace is affected.
1161 */
af0f446d 1162 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG		 1163 mutex_lock(&ctrl->scan_lock);
1164 mutex_lock(&ctrl->subsys->lock);
1165 nvme_mpath_start_freeze(ctrl->subsys);
1166 nvme_mpath_wait_freeze(ctrl->subsys);
1167 nvme_start_freeze(ctrl);
1168 nvme_wait_freeze(ctrl);
1169 }
1170 return effects;
1171}
62281b9e 1172EXPORT_SYMBOL_NS_GPL(nvme_passthru_start, NVME_TARGET_PASSTHRU);
df21b6b1 1173
31a59782 1174void nvme_passthru_end(struct nvme_ctrl *ctrl, struct nvme_ns *ns, u32 effects,
bc8fb906 1175 struct nvme_command *cmd, int status)
df21b6b1 1176{
af0f446d 1177 if (effects & NVME_CMD_EFFECTS_CSE_MASK) {
df21b6b1
LG		 1178 nvme_unfreeze(ctrl);
1179 nvme_mpath_unfreeze(ctrl->subsys);
1180 mutex_unlock(&ctrl->subsys->lock);
df21b6b1
LG		 1181 mutex_unlock(&ctrl->scan_lock);
1182 }
1e37a307 1183 if (effects & NVME_CMD_EFFECTS_CCC) {
d0dd594b
BL		 1184 if (!test_and_set_bit(NVME_CTRL_DIRTY_CAPABILITY,
1185 &ctrl->flags)) {
1186 dev_info(ctrl->device,
1e37a307 1187"controller capabilities changed, reset may be required to take effect.\n");
d0dd594b 1188 }
1e37a307 1189 }
df21b6b1
LG		 1190 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC)) {
1191 nvme_queue_scan(ctrl);
1192 flush_work(&ctrl->scan_work);
1193 }
31a59782 1194 if (ns)
1195 return;
b58da2d2
TS		 1196
1197 switch (cmd->common.opcode) {
1198 case nvme_admin_set_features:
1199 switch (le32_to_cpu(cmd->common.cdw10) & 0xFF) {
1200 case NVME_FEAT_KATO:
1201 /*
1202 * Keep alive commands interval on the host should be
1203 * updated when KATO is modified by Set Features
1204 * commands.
1205 */
1206 if (!status)
1207 nvme_update_keep_alive(ctrl, cmd);
1208 break;
1209 default:
1210 break;
1211 }
1212 break;
1213 default:
1214 break;
1215 }
df21b6b1 1216}
bc8fb906 1217EXPORT_SYMBOL_NS_GPL(nvme_passthru_end, NVME_TARGET_PASSTHRU);
df21b6b1 1218
a70b81bd
HR		 1219/*
1220 * Recommended frequency for KATO commands per NVMe 1.4 section 7.12.1:
1221 *
1222 * The host should send Keep Alive commands at half of the Keep Alive Timeout
1223 * accounting for transport roundtrip times [..].
1224 */
ea4d453b
US		 1225static unsigned long nvme_keep_alive_work_period(struct nvme_ctrl *ctrl)
1226{
1227 unsigned long delay = ctrl->kato * HZ / 2;
1228
1229 /*
1230 * When using Traffic Based Keep Alive, we need to run
1231 * nvme_keep_alive_work at twice the normal frequency, as one
1232 * command completion can postpone sending a keep alive command
1233 * by up to twice the delay between runs.
1234 */
1235 if (ctrl->ctratt & NVME_CTRL_ATTR_TBKAS)
1236 delay /= 2;
1237 return delay;
1238}
1239
a70b81bd 1240static void nvme_queue_keep_alive_work(struct nvme_ctrl *ctrl)
4160982e 1241{
136cfcb8
MD		 1242 unsigned long now = jiffies;
1243 unsigned long delay = nvme_keep_alive_work_period(ctrl);
1244 unsigned long ka_next_check_tm = ctrl->ka_last_check_time + delay;
1245
1246 if (time_after(now, ka_next_check_tm))
1247 delay = 0;
1248 else
1249 delay = ka_next_check_tm - now;
1250
1251 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay);
21d34711
CH		 1252}
1253
de671d61
JA		 1254static enum rq_end_io_ret nvme_keep_alive_end_io(struct request *rq,
1255 blk_status_t status)
038bd4cb
SG		 1256{
1257 struct nvme_ctrl *ctrl = rq->end_io_data;
86880d64
JS		 1258 unsigned long flags;
1259 bool startka = false;
c7275ce6
US		 1260 unsigned long rtt = jiffies - (rq->deadline - rq->timeout);
1261 unsigned long delay = nvme_keep_alive_work_period(ctrl);
1262
1263 /*
1264 * Subtract off the keepalive RTT so nvme_keep_alive_work runs
1265 * at the desired frequency.
1266 */
1267 if (rtt <= delay) {
1268 delay -= rtt;
1269 } else {
1270 dev_warn(ctrl->device, "long keepalive RTT (%u ms)\n",
1271 jiffies_to_msecs(rtt));
1272 delay = 0;
1273 }
038bd4cb
SG		 1274
1275 blk_mq_free_request(rq);
1276
2a842aca 1277 if (status) {
038bd4cb 1278 dev_err(ctrl->device,
2a842aca
CH		 1279 "failed nvme_keep_alive_end_io error=%d\n",
1280 status);
de671d61 1281 return RQ_END_IO_NONE;
038bd4cb
SG		 1282 }
1283
774a9636 1284 ctrl->ka_last_check_time = jiffies;
6e3ca03e 1285 ctrl->comp_seen = false;
86880d64
JS		 1286 spin_lock_irqsave(&ctrl->lock, flags);
1287 if (ctrl->state == NVME_CTRL_LIVE ||
1288 ctrl->state == NVME_CTRL_CONNECTING)
1289 startka = true;
1290 spin_unlock_irqrestore(&ctrl->lock, flags);
1291 if (startka)
c7275ce6 1292 queue_delayed_work(nvme_wq, &ctrl->ka_work, delay);
de671d61 1293 return RQ_END_IO_NONE;
038bd4cb
SG		 1294}
1295
038bd4cb
SG		 1296static void nvme_keep_alive_work(struct work_struct *work)
1297{
1298 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
1299 struct nvme_ctrl, ka_work);
6e3ca03e 1300 bool comp_seen = ctrl->comp_seen;
06c3c336 1301 struct request *rq;
6e3ca03e 1302
774a9636
US		 1303 ctrl->ka_last_check_time = jiffies;
1304
6e3ca03e
SG		 1305 if ((ctrl->ctratt & NVME_CTRL_ATTR_TBKAS) && comp_seen) {
1306 dev_dbg(ctrl->device,
1307 "reschedule traffic based keep-alive timer\n");
1308 ctrl->comp_seen = false;
a70b81bd 1309 nvme_queue_keep_alive_work(ctrl);
6e3ca03e
SG		 1310 return;
1311 }
038bd4cb 1312
e559398f
CH		 1313 rq = blk_mq_alloc_request(ctrl->admin_q, nvme_req_op(&ctrl->ka_cmd),
1314 BLK_MQ_REQ_RESERVED | BLK_MQ_REQ_NOWAIT);
06c3c336 1315 if (IS_ERR(rq)) {
038bd4cb 1316 /* allocation failure, reset the controller */
985c5a32 1317 dev_err(ctrl->device, "keep-alive failed: %ld\n", PTR_ERR(rq));
39bdc590 1318 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 1319 return;
1320 }
e559398f 1321 nvme_init_request(rq, &ctrl->ka_cmd);
06c3c336
CH		 1322
1323 rq->timeout = ctrl->kato * HZ;
e2e53086 1324 rq->end_io = nvme_keep_alive_end_io;
06c3c336 1325 rq->end_io_data = ctrl;
e2e53086 1326 blk_execute_rq_nowait(rq, false);
038bd4cb
SG		 1327}
1328
00b683db 1329static void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
038bd4cb
SG		 1330{
1331 if (unlikely(ctrl->kato == 0))
1332 return;
1333
a70b81bd 1334 nvme_queue_keep_alive_work(ctrl);
038bd4cb 1335}
038bd4cb
SG		 1336
1337void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
1338{
1339 if (unlikely(ctrl->kato == 0))
1340 return;
1341
1342 cancel_delayed_work_sync(&ctrl->ka_work);
1343}
1344EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
1345
b58da2d2
TS		 1346static void nvme_update_keep_alive(struct nvme_ctrl *ctrl,
1347 struct nvme_command *cmd)
1348{
1349 unsigned int new_kato =
1350 DIV_ROUND_UP(le32_to_cpu(cmd->common.cdw11), 1000);
1351
1352 dev_info(ctrl->device,
1353 "keep alive interval updated from %u ms to %u ms\n",
1354 ctrl->kato * 1000 / 2, new_kato * 1000 / 2);
1355
1356 nvme_stop_keep_alive(ctrl);
1357 ctrl->kato = new_kato;
1358 nvme_start_keep_alive(ctrl);
1359}
1360
b9a5c3d4
CH		 1361/*
1362 * In NVMe 1.0 the CNS field was just a binary controller or namespace
1363 * flag, thus sending any new CNS opcodes has a big chance of not working.
1364 * Qemu unfortunately had that bug after reporting a 1.1 version compliance
1365 * (but not for any later version).
1366 */
1367static bool nvme_ctrl_limited_cns(struct nvme_ctrl *ctrl)
1368{
1369 if (ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)
1370 return ctrl->vs < NVME_VS(1, 2, 0);
1371 return ctrl->vs < NVME_VS(1, 1, 0);
1372}
1373
3f7f25a9 1374static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 1375{
1376 struct nvme_command c = { };
1377 int error;
1378
1379 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1380 c.identify.opcode = nvme_admin_identify;
986994a2 1381 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 1382
1383 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1384 if (!*id)
1385 return -ENOMEM;
1386
1387 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1388 sizeof(struct nvme_id_ctrl));
7e80eb79 1389 if (error) {
21d34711 1390 kfree(*id);
7e80eb79
KB		 1391 *id = NULL;
1392 }
21d34711
CH		 1393 return error;
1394}
1395
ad95a613 1396static int nvme_process_ns_desc(struct nvme_ctrl *ctrl, struct nvme_ns_ids *ids,
71010c30 1397 struct nvme_ns_id_desc *cur, bool *csi_seen)
ad95a613
CK		 1398{
1399 const char *warn_str = "ctrl returned bogus length:";
1400 void *data = cur;
1401
1402 switch (cur->nidt) {
1403 case NVME_NIDT_EUI64:
1404 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
1405 dev_warn(ctrl->device, "%s %d for NVME_NIDT_EUI64\n",
1406 warn_str, cur->nidl);
1407 return -1;
1408 }
00ff400e
CH		 1409 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1410 return NVME_NIDT_EUI64_LEN;
ad95a613
CK		 1411 memcpy(ids->eui64, data + sizeof(*cur), NVME_NIDT_EUI64_LEN);
1412 return NVME_NIDT_EUI64_LEN;
1413 case NVME_NIDT_NGUID:
1414 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
1415 dev_warn(ctrl->device, "%s %d for NVME_NIDT_NGUID\n",
1416 warn_str, cur->nidl);
1417 return -1;
1418 }
00ff400e
CH		 1419 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1420 return NVME_NIDT_NGUID_LEN;
ad95a613
CK		 1421 memcpy(ids->nguid, data + sizeof(*cur), NVME_NIDT_NGUID_LEN);
1422 return NVME_NIDT_NGUID_LEN;
1423 case NVME_NIDT_UUID:
1424 if (cur->nidl != NVME_NIDT_UUID_LEN) {
1425 dev_warn(ctrl->device, "%s %d for NVME_NIDT_UUID\n",
1426 warn_str, cur->nidl);
1427 return -1;
1428 }
00ff400e
CH		 1429 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID)
1430 return NVME_NIDT_UUID_LEN;
ad95a613
CK		 1431 uuid_copy(&ids->uuid, data + sizeof(*cur));
1432 return NVME_NIDT_UUID_LEN;
71010c30
NC		 1433 case NVME_NIDT_CSI:
1434 if (cur->nidl != NVME_NIDT_CSI_LEN) {
1435 dev_warn(ctrl->device, "%s %d for NVME_NIDT_CSI\n",
1436 warn_str, cur->nidl);
1437 return -1;
1438 }
1439 memcpy(&ids->csi, data + sizeof(*cur), NVME_NIDT_CSI_LEN);
1440 *csi_seen = true;
1441 return NVME_NIDT_CSI_LEN;
ad95a613
CK		 1442 default:
1443 /* Skip unknown types */
1444 return cur->nidl;
1445 }
1446}
1447
1a893c2b
CH		 1448static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl,
1449 struct nvme_ns_info *info)
3b22ba26
JT		 1450{
1451 struct nvme_command c = { };
71010c30
NC		 1452 bool csi_seen = false;
1453 int status, pos, len;
3b22ba26 1454 void *data;
3b22ba26 1455
8b7c0ff2
CH		 1456 if (ctrl->vs < NVME_VS(1, 3, 0) && !nvme_multi_css(ctrl))
1457 return 0;
5bedd3af
CH		 1458 if (ctrl->quirks & NVME_QUIRK_NO_NS_DESC_LIST)
1459 return 0;
1460
3b22ba26 1461 c.identify.opcode = nvme_admin_identify;
1a893c2b 1462 c.identify.nsid = cpu_to_le32(info->nsid);
3b22ba26
JT		 1463 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
1464
1465 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
1466 if (!data)
1467 return -ENOMEM;
1468
cdbff4f2 1469 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26 1470 NVME_IDENTIFY_DATA_SIZE);
fb314eb0
CH		 1471 if (status) {
1472 dev_warn(ctrl->device,
aa9d7295 1473 "Identify Descriptors failed (nsid=%u, status=0x%x)\n",
1a893c2b 1474 info->nsid, status);
3b22ba26 1475 goto free_data;
fb314eb0 1476 }
3b22ba26
JT		 1477
1478 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
1479 struct nvme_ns_id_desc *cur = data + pos;
1480
1481 if (cur->nidl == 0)
1482 break;
1483
1a893c2b 1484 len = nvme_process_ns_desc(ctrl, &info->ids, cur, &csi_seen);
ad95a613 1485 if (len < 0)
71010c30 1486 break;
3b22ba26
JT		 1487
1488 len += sizeof(*cur);
1489 }
71010c30
NC		 1490
1491 if (nvme_multi_css(ctrl) && !csi_seen) {
1492 dev_warn(ctrl->device, "Command set not reported for nsid:%d\n",
1a893c2b 1493 info->nsid);
71010c30
NC		 1494 status = -EINVAL;
1495 }
1496
3b22ba26
JT		 1497free_data:
1498 kfree(data);
1499 return status;
1500}
1501
a1a825ab 1502int nvme_identify_ns(struct nvme_ctrl *ctrl, unsigned nsid,
1a893c2b 1503 struct nvme_id_ns **id)
21d34711
CH		 1504{
1505 struct nvme_command c = { };
1506 int error;
1507
1508 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 1509 c.identify.opcode = nvme_admin_identify;
1510 c.identify.nsid = cpu_to_le32(nsid);
986994a2 1511 c.identify.cns = NVME_ID_CNS_NS;
21d34711 1512
331813f6
SG		 1513 *id = kmalloc(sizeof(**id), GFP_KERNEL);
1514 if (!*id)
1515 return -ENOMEM;
21d34711 1516
331813f6 1517 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, *id, sizeof(**id));
cdbff4f2 1518 if (error) {
d0de579c 1519 dev_warn(ctrl->device, "Identify namespace failed (%d)\n", error);
0dd6fff2 1520 kfree(*id);
7e80eb79 1521 *id = NULL;
cdbff4f2 1522 }
1a893c2b
CH		 1523 return error;
1524}
00ff400e 1525
1a893c2b
CH		 1526static int nvme_ns_info_from_identify(struct nvme_ctrl *ctrl,
1527 struct nvme_ns_info *info)
1528{
1529 struct nvme_ns_ids *ids = &info->ids;
1530 struct nvme_id_ns *id;
1531 int ret;
1532
1533 ret = nvme_identify_ns(ctrl, info->nsid, &id);
1534 if (ret)
1535 return ret;
0dd6fff2
CH		 1536
1537 if (id->ncap == 0) {
1538 /* namespace not allocated or attached */
1539 info->is_removed = true;
e3139cef
ML		 1540 ret = -ENODEV;
1541 goto error;
0dd6fff2
CH		 1542 }
1543
1a893c2b
CH		 1544 info->anagrpid = id->anagrpid;
1545 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED;
1e4ea66a 1546 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO;
1a893c2b 1547 info->is_ready = true;
00ff400e
CH		 1548 if (ctrl->quirks & NVME_QUIRK_BOGUS_NID) {
1549 dev_info(ctrl->device,
1550 "Ignoring bogus Namespace Identifiers\n");
1551 } else {
1552 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
1553 !memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
1a893c2b 1554 memcpy(ids->eui64, id->eui64, sizeof(ids->eui64));
00ff400e
CH		 1555 if (ctrl->vs >= NVME_VS(1, 2, 0) &&
1556 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
1a893c2b 1557 memcpy(ids->nguid, id->nguid, sizeof(ids->nguid));
00ff400e 1558 }
e3139cef
ML		 1559
1560error:
1a893c2b 1561 kfree(id);
e3139cef 1562 return ret;
21d34711
CH		 1563}
1564
1a893c2b
CH		 1565static int nvme_ns_info_from_id_cs_indep(struct nvme_ctrl *ctrl,
1566 struct nvme_ns_info *info)
354201c5 1567{
1a893c2b 1568 struct nvme_id_ns_cs_indep *id;
354201c5
CH		 1569 struct nvme_command c = {
1570 .identify.opcode = nvme_admin_identify,
1a893c2b 1571 .identify.nsid = cpu_to_le32(info->nsid),
354201c5
CH		 1572 .identify.cns = NVME_ID_CNS_NS_CS_INDEP,
1573 };
1574 int ret;
1575
1a893c2b
CH		 1576 id = kmalloc(sizeof(*id), GFP_KERNEL);
1577 if (!id)
354201c5
CH		 1578 return -ENOMEM;
1579
1a893c2b
CH		 1580 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
1581 if (!ret) {
1582 info->anagrpid = id->anagrpid;
1583 info->is_shared = id->nmic & NVME_NS_NMIC_SHARED;
1e4ea66a 1584 info->is_readonly = id->nsattr & NVME_NS_ATTR_RO;
1a893c2b 1585 info->is_ready = id->nstat & NVME_NSTAT_NRDY;
354201c5 1586 }
1a893c2b
CH		 1587 kfree(id);
1588 return ret;
354201c5
CH		 1589}
1590
1a87ee65
KB		 1591static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
1592 unsigned int dword11, void *buffer, size_t buflen, u32 *result)
21d34711 1593{
15755854 1594 union nvme_result res = { 0 };
cc72c442 1595 struct nvme_command c = { };
1cb3cce5 1596 int ret;
21d34711 1597
1a87ee65 1598 c.features.opcode = op;
21d34711
CH		 1599 c.features.fid = cpu_to_le32(fid);
1600 c.features.dword11 = cpu_to_le32(dword11);
1601
d49187e9 1602 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
bd2687f2 1603 buffer, buflen, NVME_QID_ANY, 0);
9b47f77a 1604 if (ret >= 0 && result)
d49187e9 1605 *result = le32_to_cpu(res.u32);
1cb3cce5 1606 return ret;
21d34711
CH		 1607}
1608
1a87ee65
KB		 1609int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
1610 unsigned int dword11, void *buffer, size_t buflen,
1611 u32 *result)
1612{
1613 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer,
1614 buflen, result);
1615}
1616EXPORT_SYMBOL_GPL(nvme_set_features);
1617
1618int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
1619 unsigned int dword11, void *buffer, size_t buflen,
1620 u32 *result)
1621{
1622 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer,
1623 buflen, result);
1624}
1625EXPORT_SYMBOL_GPL(nvme_get_features);
1626
9a0be7ab
CH		 1627int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
1628{
1629 u32 q_count = (*count - 1) | ((*count - 1) << 16);
1630 u32 result;
1631 int status, nr_io_queues;
1632
1a6fe74d 1633 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 1634 &result);
f5fa90dc 1635 if (status < 0)
9a0be7ab
CH		 1636 return status;
1637
f5fa90dc
CH		 1638 /*
1639 * Degraded controllers might return an error when setting the queue
1640 * count. We still want to be able to bring them online and offer
1641 * access to the admin queue, as that might be only way to fix them up.
1642 */
1643 if (status > 0) {
f0425db0 1644 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 1645 *count = 0;
1646 } else {
1647 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
1648 *count = min(*count, nr_io_queues);
1649 }
1650
9a0be7ab
CH		 1651 return 0;
1652}
576d55d6 1653EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 1654
c0561f82 1655#define NVME_AEN_SUPPORTED \
85f8a435
SG		 1656 (NVME_AEN_CFG_NS_ATTR | NVME_AEN_CFG_FW_ACT | \
1657 NVME_AEN_CFG_ANA_CHANGE | NVME_AEN_CFG_DISC_CHANGE)
c0561f82
HR		 1658
1659static void nvme_enable_aen(struct nvme_ctrl *ctrl)
1660{
fa441b71 1661 u32 result, supported_aens = ctrl->oaes & NVME_AEN_SUPPORTED;
c0561f82
HR		 1662 int status;
1663
fa441b71
WZ		 1664 if (!supported_aens)
1665 return;
1666
1667 status = nvme_set_features(ctrl, NVME_FEAT_ASYNC_EVENT, supported_aens,
1668 NULL, 0, &result);
c0561f82
HR		 1669 if (status)
1670 dev_warn(ctrl->device, "Failed to configure AEN (cfg %x)\n",
fa441b71 1671 supported_aens);
93da4023
SG		 1672
1673 queue_work(nvme_wq, &ctrl->async_event_work);
c0561f82
HR		 1674}
1675
f5b9a51d 1676static int nvme_ns_open(struct nvme_ns *ns)
c225b610 1677{
c225b610 1678
32acab31 1679 /* should never be called due to GENHD_FL_HIDDEN */
30897388 1680 if (WARN_ON_ONCE(nvme_ns_head_multipath(ns->head)))
85088c4a 1681 goto fail;
4c74d1f8 1682 if (!nvme_get_ns(ns))
85088c4a
NC		 1683 goto fail;
1684 if (!try_module_get(ns->ctrl->ops->module))
1685 goto fail_put_ns;
1686
c6424a90 1687 return 0;
85088c4a
NC		 1688
1689fail_put_ns:
1690 nvme_put_ns(ns);
1691fail:
1692 return -ENXIO;
1673f1f0
CH		 1693}
1694
f5b9a51d 1695static void nvme_ns_release(struct nvme_ns *ns)
1673f1f0 1696{
85088c4a
NC		 1697
1698 module_put(ns->ctrl->ops->module);
1699 nvme_put_ns(ns);
1673f1f0
CH		 1700}
1701
05bdb996 1702static int nvme_open(struct gendisk *disk, blk_mode_t mode)
f5b9a51d 1703{
d32e2bf8 1704 return nvme_ns_open(disk->private_data);
f5b9a51d
CH		 1705}
1706
ae220766 1707static void nvme_release(struct gendisk *disk)
f5b9a51d
CH		 1708{
1709 nvme_ns_release(disk->private_data);
1710}
1711
1496bd49 1712int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1673f1f0
CH		 1713{
1714 /* some standard values */
1715 geo->heads = 1 << 6;
1716 geo->sectors = 1 << 5;
1717 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1718 return 0;
1719}
1720
f467b48e 1721static bool nvme_init_integrity(struct gendisk *disk, struct nvme_ns_head *head)
1673f1f0 1722{
cc72c442 1723 struct blk_integrity integrity = { };
1673f1f0 1724
414c62e2
CH		 1725 blk_integrity_unregister(disk);
1726
f467b48e
CH		 1727 if (!head->ms)
1728 return true;
1729
1730 /*
1731 * PI can always be supported as we can ask the controller to simply
1732 * insert/strip it, which is not possible for other kinds of metadata.
1733 */
1734 if (!IS_ENABLED(CONFIG_BLK_DEV_INTEGRITY) ||
1735 !(head->features & NVME_NS_METADATA_SUPPORTED))
1736 return nvme_ns_has_pi(head);
1737
d386aedc 1738 switch (head->pi_type) {
1673f1f0 1739 case NVME_NS_DPS_PI_TYPE3:
d386aedc 1740 switch (head->guard_type) {
4020aad8
KB		 1741 case NVME_NVM_NS_16B_GUARD:
1742 integrity.profile = &t10_pi_type3_crc;
1743 integrity.tag_size = sizeof(u16) + sizeof(u32);
1744 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1745 break;
1746 case NVME_NVM_NS_64B_GUARD:
1747 integrity.profile = &ext_pi_type3_crc64;
1748 integrity.tag_size = sizeof(u16) + 6;
1749 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1750 break;
1751 default:
1752 integrity.profile = NULL;
1753 break;
1754 }
1673f1f0
CH		 1755 break;
1756 case NVME_NS_DPS_PI_TYPE1:
1757 case NVME_NS_DPS_PI_TYPE2:
d386aedc 1758 switch (head->guard_type) {
4020aad8
KB		 1759 case NVME_NVM_NS_16B_GUARD:
1760 integrity.profile = &t10_pi_type1_crc;
1761 integrity.tag_size = sizeof(u16);
1762 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1763 break;
1764 case NVME_NVM_NS_64B_GUARD:
1765 integrity.profile = &ext_pi_type1_crc64;
1766 integrity.tag_size = sizeof(u16);
1767 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1768 break;
1769 default:
1770 integrity.profile = NULL;
1771 break;
1772 }
1673f1f0
CH		 1773 break;
1774 default:
1775 integrity.profile = NULL;
1776 break;
1777 }
4020aad8 1778
d386aedc 1779 integrity.tuple_size = head->ms;
921e81db 1780 integrity.pi_offset = head->pi_offset;
39b7baa4 1781 blk_integrity_register(disk, &integrity);
f467b48e 1782 return true;
1673f1f0 1783}
1673f1f0 1784
e6c9b130 1785static void nvme_config_discard(struct nvme_ns *ns, struct queue_limits *lim)
1673f1f0 1786{
e6c9b130 1787 struct nvme_ctrl *ctrl = ns->ctrl;
3831761e 1788
e6c9b130
CH		 1789 if (ctrl->dmrsl && ctrl->dmrsl <= nvme_sect_to_lba(ns->head, UINT_MAX))
1790 lim->max_hw_discard_sectors =
1791 nvme_lba_to_sect(ns->head, ctrl->dmrsl);
1792 else if (ctrl->oncs & NVME_CTRL_ONCS_DSM)
1793 lim->max_hw_discard_sectors = UINT_MAX;
1794 else
1795 lim->max_hw_discard_sectors = 0;
1796
1797 lim->discard_granularity = lim->logical_block_size;
3831761e 1798
3b946fe1 1799 if (ctrl->dmrl)
e6c9b130 1800 lim->max_discard_segments = ctrl->dmrl;
3b946fe1 1801 else
e6c9b130 1802 lim->max_discard_segments = NVME_DSM_MAX_RANGES;
1673f1f0
CH		 1803}
1804
002fab04
CH		 1805static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1806{
1807 return uuid_equal(&a->uuid, &b->uuid) &&
1808 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
71010c30
NC		 1809 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0 &&
1810 a->csi == b->csi;
002fab04
CH		 1811}
1812
c6fce9f1
CH		 1813static int nvme_identify_ns_nvm(struct nvme_ctrl *ctrl, unsigned int nsid,
1814 struct nvme_id_ns_nvm **nvmp)
d4609ea8 1815{
c6fce9f1
CH		 1816 struct nvme_command c = {
1817 .identify.opcode = nvme_admin_identify,
1818 .identify.nsid = cpu_to_le32(nsid),
1819 .identify.cns = NVME_ID_CNS_CS_NS,
1820 .identify.csi = NVME_CSI_NVM,
1821 };
4020aad8 1822 struct nvme_id_ns_nvm *nvm;
c6fce9f1 1823 int ret;
d4609ea8 1824
4020aad8
KB		 1825 nvm = kzalloc(sizeof(*nvm), GFP_KERNEL);
1826 if (!nvm)
1827 return -ENOMEM;
d4609ea8 1828
d386aedc 1829 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, nvm, sizeof(*nvm));
4020aad8 1830 if (ret)
c6fce9f1
CH		 1831 kfree(nvm);
1832 else
1833 *nvmp = nvm;
1834 return ret;
1835}
4020aad8 1836
27cb91a3 1837static void nvme_configure_pi_elbas(struct nvme_ns_head *head,
e5ea00a5 1838 struct nvme_id_ns *id, struct nvme_id_ns_nvm *nvm)
d4609ea8 1839{
27cb91a3 1840 u32 elbaf = le32_to_cpu(nvm->elbaf[nvme_lbaf_index(id->flbas)]);
4020aad8
KB		 1841
1842 /* no support for storage tag formats right now */
1843 if (nvme_elbaf_sts(elbaf))
27cb91a3 1844 return;
4020aad8 1845
d386aedc
DW		 1846 head->guard_type = nvme_elbaf_guard_type(elbaf);
1847 switch (head->guard_type) {
4020aad8 1848 case NVME_NVM_NS_64B_GUARD:
d386aedc 1849 head->pi_size = sizeof(struct crc64_pi_tuple);
4020aad8
KB		 1850 break;
1851 case NVME_NVM_NS_16B_GUARD:
d386aedc 1852 head->pi_size = sizeof(struct t10_pi_tuple);
4020aad8
KB		 1853 break;
1854 default:
1855 break;
1856 }
4020aad8
KB		 1857}
1858
e5ea00a5
CH		 1859static void nvme_configure_metadata(struct nvme_ctrl *ctrl,
1860 struct nvme_ns_head *head, struct nvme_id_ns *id,
1861 struct nvme_id_ns_nvm *nvm)
4020aad8 1862{
d386aedc 1863 head->features &= ~(NVME_NS_METADATA_SUPPORTED | NVME_NS_EXT_LBAS);
27cb91a3
CH		 1864 head->pi_type = 0;
1865 head->pi_size = 0;
1866 head->pi_offset = 0;
1867 head->ms = le16_to_cpu(id->lbaf[nvme_lbaf_index(id->flbas)].ms);
d386aedc 1868 if (!head->ms || !(ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
e5ea00a5 1869 return;
363f6368 1870
27cb91a3
CH		 1871 if (nvm && (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)) {
1872 nvme_configure_pi_elbas(head, id, nvm);
1873 } else {
1874 head->pi_size = sizeof(struct t10_pi_tuple);
1875 head->guard_type = NVME_NVM_NS_16B_GUARD;
1876 }
1877
1878 if (head->pi_size && head->ms >= head->pi_size)
1879 head->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1880 if (!(id->dps & NVME_NS_DPS_PI_FIRST))
1881 head->pi_offset = head->ms - head->pi_size;
363f6368 1882
d4609ea8
CH		 1883 if (ctrl->ops->flags & NVME_F_FABRICS) {
1884 /*
1885 * The NVMe over Fabrics specification only supports metadata as
1886 * part of the extended data LBA. We rely on HCA/HBA support to
1887 * remap the separate metadata buffer from the block layer.
1888 */
1889 if (WARN_ON_ONCE(!(id->flbas & NVME_NS_FLBAS_META_EXT)))
e5ea00a5 1890 return;
d39ad2a4 1891
d386aedc 1892 head->features |= NVME_NS_EXT_LBAS;
d39ad2a4
KB		 1893
1894 /*
1895 * The current fabrics transport drivers support namespace
1896 * metadata formats only if nvme_ns_has_pi() returns true.
1897 * Suppress support for all other formats so the namespace will
1898 * have a 0 capacity and not be usable through the block stack.
1899 *
1900 * Note, this check will need to be modified if any drivers
1901 * gain the ability to use other metadata formats.
1902 */
d386aedc
DW		 1903 if (ctrl->max_integrity_segments && nvme_ns_has_pi(head))
1904 head->features |= NVME_NS_METADATA_SUPPORTED;
d4609ea8
CH		 1905 } else {
1906 /*
1907 * For PCIe controllers, we can't easily remap the separate
1908 * metadata buffer from the block layer and thus require a
1909 * separate metadata buffer for block layer metadata/PI support.
1910 * We allow extended LBAs for the passthrough interface, though.
1911 */
1912 if (id->flbas & NVME_NS_FLBAS_META_EXT)
d386aedc 1913 head->features |= NVME_NS_EXT_LBAS;
d4609ea8 1914 else
d386aedc 1915 head->features |= NVME_NS_METADATA_SUPPORTED;
d4609ea8 1916 }
d4609ea8
CH		 1917}
1918
152694c8 1919static u32 nvme_max_drv_segments(struct nvme_ctrl *ctrl)
658d9f7c 1920{
152694c8
CH		 1921 return ctrl->max_hw_sectors / (NVME_CTRL_PAGE_SIZE >> SECTOR_SHIFT) + 1;
1922}
658d9f7c 1923
e6c9b130
CH		 1924static void nvme_set_ctrl_limits(struct nvme_ctrl *ctrl,
1925 struct queue_limits *lim)
658d9f7c 1926{
e6c9b130
CH		 1927 lim->max_hw_sectors = ctrl->max_hw_sectors;
1928 lim->max_segments = min_t(u32, USHRT_MAX,
1929 min_not_zero(nvme_max_drv_segments(ctrl), ctrl->max_segments));
1930 lim->max_integrity_segments = ctrl->max_integrity_segments;
1931 lim->virt_boundary_mask = NVME_CTRL_PAGE_SIZE - 1;
1932 lim->max_segment_size = UINT_MAX;
1933 lim->dma_alignment = 3;
658d9f7c
CH		 1934}
1935
e6c9b130
CH		 1936static bool nvme_update_disk_info(struct nvme_ns *ns, struct nvme_id_ns *id,
1937 struct queue_limits *lim)
24b0b58c 1938{
a5b1cd61 1939 struct nvme_ns_head *head = ns->head;
d386aedc 1940 u32 bs = 1U << head->lba_shift;
68ab60ca 1941 u32 atomic_bs, phys_bs, io_opt = 0;
a5b1cd61 1942 bool valid = true;
24b0b58c 1943
13f0b26b
CH		 1944 /*
1945 * The block layer can't support LBA sizes larger than the page size
74fbc88e
KB		 1946 * or smaller than a sector size yet, so catch this early and don't
1947 * allow block I/O.
13f0b26b 1948 */
01d550f0 1949 if (head->lba_shift > PAGE_SHIFT || head->lba_shift < SECTOR_SHIFT) {
01fa0174 1950 bs = (1 << 9);
a5b1cd61 1951 valid = false;
01fa0174 1952 }
f9d5f457 1953
68ab60ca 1954 atomic_bs = phys_bs = bs;
81adb863
BVA		 1955 if (id->nabo == 0) {
1956 /*
1957 * Bit 1 indicates whether NAWUPF is defined for this namespace
1958 * and whether it should be used instead of AWUPF. If NAWUPF ==
1959 * 0 then AWUPF must be used instead.
1960 */
92decf11 1961 if (id->nsfeat & NVME_NS_FEAT_ATOMICS && id->nawupf)
81adb863
BVA		 1962 atomic_bs = (1 + le16_to_cpu(id->nawupf)) * bs;
1963 else
a5b1cd61 1964 atomic_bs = (1 + ns->ctrl->subsys->awupf) * bs;
81adb863 1965 }
31fdad7b 1966
92decf11 1967 if (id->nsfeat & NVME_NS_FEAT_IO_OPT) {
81adb863 1968 /* NPWG = Namespace Preferred Write Granularity */
31fdad7b 1969 phys_bs = bs * (1 + le16_to_cpu(id->npwg));
81adb863 1970 /* NOWS = Namespace Optimal Write Size */
31fdad7b 1971 io_opt = bs * (1 + le16_to_cpu(id->nows));
81adb863
BVA		 1972 }
1973
81adb863
BVA		 1974 /*
1975 * Linux filesystems assume writing a single physical block is
1976 * an atomic operation. Hence limit the physical block size to the
1977 * value of the Atomic Write Unit Power Fail parameter.
1978 */
e6c9b130
CH		 1979 lim->logical_block_size = bs;
1980 lim->physical_block_size = min(phys_bs, atomic_bs);
1981 lim->io_min = phys_bs;
1982 lim->io_opt = io_opt;
a5b1cd61 1983 if (ns->ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
e6c9b130 1984 lim->max_write_zeroes_sectors = UINT_MAX;
63dfa100 1985 else
e6c9b130 1986 lim->max_write_zeroes_sectors = ns->ctrl->max_zeroes_sectors;
a5b1cd61 1987 return valid;
24b0b58c
CH		 1988}
1989
1e4ea66a
CH		 1990static bool nvme_ns_is_readonly(struct nvme_ns *ns, struct nvme_ns_info *info)
1991{
1992 return info->is_readonly || test_bit(NVME_NS_FORCE_RO, &ns->flags);
1993}
1994
e83d776f
KB		 1995static inline bool nvme_first_scan(struct gendisk *disk)
1996{
1997 /* nvme_alloc_ns() scans the disk prior to adding it */
50b4aecf 1998 return !disk_live(disk);
e83d776f
KB		 1999}
2000
e6c9b130
CH		 2001static void nvme_set_chunk_sectors(struct nvme_ns *ns, struct nvme_id_ns *id,
2002 struct queue_limits *lim)
e83d776f
KB		 2003{
2004 struct nvme_ctrl *ctrl = ns->ctrl;
2005 u32 iob;
2006
2007 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
2008 is_power_of_2(ctrl->max_hw_sectors))
2009 iob = ctrl->max_hw_sectors;
2010 else
0372dd4e 2011 iob = nvme_lba_to_sect(ns->head, le16_to_cpu(id->noiob));
e83d776f
KB		 2012
2013 if (!iob)
2014 return;
2015
2016 if (!is_power_of_2(iob)) {
2017 if (nvme_first_scan(ns->disk))
2018 pr_warn("%s: ignoring unaligned IO boundary:%u\n",
2019 ns->disk->disk_name, iob);
2020 return;
2021 }
2022
2023 if (blk_queue_is_zoned(ns->disk->queue)) {
2024 if (nvme_first_scan(ns->disk))
2025 pr_warn("%s: ignoring zoned namespace IO boundary\n",
2026 ns->disk->disk_name);
2027 return;
2028 }
2029
e6c9b130 2030 lim->chunk_sectors = iob;
e83d776f
KB		 2031}
2032
eb867ee9
JG		 2033static int nvme_update_ns_info_generic(struct nvme_ns *ns,
2034 struct nvme_ns_info *info)
2035{
e6c9b130
CH		 2036 struct queue_limits lim;
2037 int ret;
2038
eb867ee9 2039 blk_mq_freeze_queue(ns->disk->queue);
e6c9b130
CH		 2040 lim = queue_limits_start_update(ns->disk->queue);
2041 nvme_set_ctrl_limits(ns->ctrl, &lim);
2042 ret = queue_limits_commit_update(ns->disk->queue, &lim);
eb867ee9
JG		 2043 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info));
2044 blk_mq_unfreeze_queue(ns->disk->queue);
2045
eb867ee9 2046 /* Hide the block-interface for these devices */
e6c9b130
CH		 2047 if (!ret)
2048 ret = -ENODEV;
2049 return ret;
eb867ee9
JG		 2050}
2051
1a893c2b
CH		 2052static int nvme_update_ns_info_block(struct nvme_ns *ns,
2053 struct nvme_ns_info *info)
ac81bfa9 2054{
d60c23e4 2055 bool vwc = ns->ctrl->vwc & NVME_CTRL_VWC_PRESENT;
e6c9b130 2056 struct queue_limits lim;
e5ea00a5 2057 struct nvme_id_ns_nvm *nvm = NULL;
c85c9ab9 2058 struct nvme_zone_info zi = {};
1a893c2b 2059 struct nvme_id_ns *id;
a5b1cd61 2060 sector_t capacity;
1a893c2b 2061 unsigned lbaf;
240e6ee2 2062 int ret;
1673f1f0 2063
1a893c2b
CH		 2064 ret = nvme_identify_ns(ns->ctrl, info->nsid, &id);
2065 if (ret)
2066 return ret;
2067
d8b90d60
EM		 2068 if (id->ncap == 0) {
2069 /* namespace not allocated or attached */
2070 info->is_removed = true;
0551ec93 2071 ret = -ENXIO;
46e7422c 2072 goto out;
d8b90d60 2073 }
c85c9ab9 2074 lbaf = nvme_lbaf_index(id->flbas);
d8b90d60 2075
e5ea00a5
CH		 2076 if (ns->ctrl->ctratt & NVME_CTRL_ATTR_ELBAS) {
2077 ret = nvme_identify_ns_nvm(ns->ctrl, info->nsid, &nvm);
2078 if (ret < 0)
2079 goto out;
d8b90d60
EM		 2080 }
2081
c85c9ab9
CH		 2082 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
2083 ns->head->ids.csi == NVME_CSI_ZNS) {
2084 ret = nvme_query_zone_info(ns, lbaf, &zi);
2085 if (ret < 0)
2086 goto out;
2087 }
2088
f9d5f457 2089 blk_mq_freeze_queue(ns->disk->queue);
9419e71b 2090 ns->head->lba_shift = id->lbaf[lbaf].ds;
a1a825ab 2091 ns->head->nuse = le64_to_cpu(id->nuse);
a5b1cd61 2092 capacity = nvme_lba_to_sect(ns->head, le64_to_cpu(id->nsze));
73d90386 2093
e6c9b130
CH		 2094 lim = queue_limits_start_update(ns->disk->queue);
2095 nvme_set_ctrl_limits(ns->ctrl, &lim);
e5ea00a5 2096 nvme_configure_metadata(ns->ctrl, ns->head, id, nvm);
e6c9b130
CH		 2097 nvme_set_chunk_sectors(ns, id, &lim);
2098 if (!nvme_update_disk_info(ns, id, &lim))
a5b1cd61 2099 capacity = 0;
e6c9b130
CH		 2100 nvme_config_discard(ns, &lim);
2101 if (IS_ENABLED(CONFIG_BLK_DEV_ZONED) &&
c85c9ab9
CH		 2102 ns->head->ids.csi == NVME_CSI_ZNS)
2103 nvme_update_zone_info(ns, &lim, &zi);
e6c9b130
CH		 2104 ret = queue_limits_commit_update(ns->disk->queue, &lim);
2105 if (ret) {
2106 blk_mq_unfreeze_queue(ns->disk->queue);
2107 goto out;
2108 }
a5b1cd61
CH		 2109
2110 /*
2111 * Register a metadata profile for PI, or the plain non-integrity NVMe
2112 * metadata masquerading as Type 0 if supported, otherwise reject block
2113 * I/O to namespaces with metadata except when the namespace supports
2114 * PI, as it can strip/insert in that case.
2115 */
2116 if (!nvme_init_integrity(ns->disk, ns->head))
2117 capacity = 0;
2118
2119 set_capacity_and_notify(ns->disk, capacity);
71010c30 2120
1b96f862
CH		 2121 /*
2122 * Only set the DEAC bit if the device guarantees that reads from
2123 * deallocated data return zeroes. While the DEAC bit does not
2124 * require that, it must be a no-op if reads from deallocated data
2125 * do not return zeroes.
2126 */
2127 if ((id->dlfeat & 0x7) == 0x1 && (id->dlfeat & (1 << 3)))
9419e71b 2128 ns->head->features |= NVME_NS_DEAC;
1e4ea66a 2129 set_disk_ro(ns->disk, nvme_ns_is_readonly(ns, info));
d60c23e4 2130 blk_queue_write_cache(ns->disk->queue, vwc, vwc);
e7d65803 2131 set_bit(NVME_NS_READY, &ns->flags);
f9d5f457 2132 blk_mq_unfreeze_queue(ns->disk->queue);
1673f1f0 2133
3a9967ba 2134 if (blk_queue_is_zoned(ns->queue)) {
9b3c08b9 2135 ret = blk_revalidate_disk_zones(ns->disk);
8685699c 2136 if (ret && !nvme_first_scan(ns->disk))
e06b425b 2137 goto out;
b29f8485
MG		 2138 }
2139
e06b425b
CH		 2140 ret = 0;
2141out:
e5ea00a5 2142 kfree(nvm);
1a893c2b 2143 kfree(id);
240e6ee2
KB		 2144 return ret;
2145}
2146
1a893c2b
CH		 2147static int nvme_update_ns_info(struct nvme_ns *ns, struct nvme_ns_info *info)
2148{
46e7422c
CH		 2149 bool unsupported = false;
2150 int ret;
2151
1a893c2b
CH		 2152 switch (info->ids.csi) {
2153 case NVME_CSI_ZNS:
2154 if (!IS_ENABLED(CONFIG_BLK_DEV_ZONED)) {
eb867ee9
JG		 2155 dev_info(ns->ctrl->device,
2156 "block device for nsid %u not supported without CONFIG_BLK_DEV_ZONED\n",
1a893c2b 2157 info->nsid);
46e7422c
CH		 2158 ret = nvme_update_ns_info_generic(ns, info);
2159 break;
1a893c2b 2160 }
46e7422c
CH		 2161 ret = nvme_update_ns_info_block(ns, info);
2162 break;
1a893c2b 2163 case NVME_CSI_NVM:
46e7422c
CH		 2164 ret = nvme_update_ns_info_block(ns, info);
2165 break;
1a893c2b 2166 default:
eb867ee9
JG		 2167 dev_info(ns->ctrl->device,
2168 "block device for nsid %u not supported (csi %u)\n",
2169 info->nsid, info->ids.csi);
46e7422c
CH		 2170 ret = nvme_update_ns_info_generic(ns, info);
2171 break;
2172 }
2173
2174 /*
2175 * If probing fails due an unsupported feature, hide the block device,
2176 * but still allow other access.
2177 */
2178 if (ret == -ENODEV) {
2179 ns->disk->flags |= GENHD_FL_HIDDEN;
2180 set_bit(NVME_NS_READY, &ns->flags);
2181 unsupported = true;
2182 ret = 0;
1a893c2b 2183 }
46e7422c
CH		 2184
2185 if (!ret && nvme_ns_head_multipath(ns->head)) {
ac229a2d 2186 struct queue_limits *ns_lim = &ns->disk->queue->limits;
f7e0a545
CH		 2187 struct queue_limits lim;
2188
46e7422c
CH		 2189 blk_mq_freeze_queue(ns->head->disk->queue);
2190 if (unsupported)
2191 ns->head->disk->flags |= GENHD_FL_HIDDEN;
2192 else
2193 nvme_init_integrity(ns->head->disk, ns->head);
2194 set_capacity_and_notify(ns->head->disk, get_capacity(ns->disk));
2195 set_disk_ro(ns->head->disk, nvme_ns_is_readonly(ns, info));
2196 nvme_mpath_revalidate_paths(ns);
46e7422c 2197
ac229a2d
CH		 2198 /*
2199 * queue_limits mixes values that are the hardware limitations
2200 * for bio splitting with what is the device configuration.
2201 *
2202 * For NVMe the device configuration can change after e.g. a
2203 * Format command, and we really want to pick up the new format
2204 * value here. But we must still stack the queue limits to the
2205 * least common denominator for multipathing to split the bios
2206 * properly.
2207 *
2208 * To work around this, we explicitly set the device
2209 * configuration to those that we just queried, but only stack
2210 * the splitting limits in to make sure we still obey possibly
2211 * lower limitations of other controllers.
2212 */
f7e0a545 2213 lim = queue_limits_start_update(ns->head->disk->queue);
ac229a2d
CH		 2214 lim.logical_block_size = ns_lim->logical_block_size;
2215 lim.physical_block_size = ns_lim->physical_block_size;
2216 lim.io_min = ns_lim->io_min;
2217 lim.io_opt = ns_lim->io_opt;
f7e0a545
CH		 2218 queue_limits_stack_bdev(&lim, ns->disk->part0, 0,
2219 ns->head->disk->disk_name);
2220 ret = queue_limits_commit_update(ns->head->disk->queue, &lim);
46e7422c 2221 blk_mq_unfreeze_queue(ns->head->disk->queue);
1a893c2b 2222 }
46e7422c
CH		 2223
2224 return ret;
1a893c2b
CH		 2225}
2226
a98e58e5 2227#ifdef CONFIG_BLK_SED_OPAL
94cc781f 2228static int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
4f1244c8 2229 bool send)
a98e58e5 2230{
4f1244c8 2231 struct nvme_ctrl *ctrl = data;
cc72c442 2232 struct nvme_command cmd = { };
a98e58e5 2233
a98e58e5
SB		 2234 if (send)
2235 cmd.common.opcode = nvme_admin_security_send;
2236 else
2237 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5 2238 cmd.common.nsid = 0;
b7c8f366
CK		 2239 cmd.common.cdw10 = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
2240 cmd.common.cdw11 = cpu_to_le32(len);
a98e58e5 2241
6b46fa02 2242 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
bd2687f2 2243 NVME_QID_ANY, NVME_SUBMIT_AT_HEAD);
a98e58e5 2244}
94cc781f
CH		 2245
2246static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended)
2247{
2248 if (ctrl->oacs & NVME_CTRL_OACS_SEC_SUPP) {
2249 if (!ctrl->opal_dev)
2250 ctrl->opal_dev = init_opal_dev(ctrl, &nvme_sec_submit);
2251 else if (was_suspended)
2252 opal_unlock_from_suspend(ctrl->opal_dev);
2253 } else {
2254 free_opal_dev(ctrl->opal_dev);
2255 ctrl->opal_dev = NULL;
2256 }
2257}
2258#else
2259static void nvme_configure_opal(struct nvme_ctrl *ctrl, bool was_suspended)
2260{
2261}
a98e58e5
SB		 2262#endif /* CONFIG_BLK_SED_OPAL */
2263
8b4fb0f9
CH		 2264#ifdef CONFIG_BLK_DEV_ZONED
2265static int nvme_report_zones(struct gendisk *disk, sector_t sector,
2266 unsigned int nr_zones, report_zones_cb cb, void *data)
2267{
2268 return nvme_ns_report_zones(disk->private_data, sector, nr_zones, cb,
2269 data);
2270}
2271#else
2272#define nvme_report_zones NULL
2273#endif /* CONFIG_BLK_DEV_ZONED */
2274
942e21c0 2275const struct block_device_operations nvme_bdev_ops = {
1673f1f0
CH		 2276 .owner = THIS_MODULE,
2277 .ioctl = nvme_ioctl,
a25d4261 2278 .compat_ioctl = blkdev_compat_ptr_ioctl,
1673f1f0
CH		 2279 .open = nvme_open,
2280 .release = nvme_release,
2281 .getgeo = nvme_getgeo,
240e6ee2 2282 .report_zones = nvme_report_zones,
1673f1f0
CH		 2283 .pr_ops = &nvme_pr_ops,
2284};
2285
e6d275de
CH		 2286static int nvme_wait_ready(struct nvme_ctrl *ctrl, u32 mask, u32 val,
2287 u32 timeout, const char *op)
5fd4ce1b 2288{
e6d275de
CH		 2289 unsigned long timeout_jiffies = jiffies + timeout * HZ;
2290 u32 csts;
5fd4ce1b
CH		 2291 int ret;
2292
2293 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 2294 if (csts == ~0)
2295 return -ENODEV;
e6d275de 2296 if ((csts & mask) == val)
5fd4ce1b
CH		 2297 break;
2298
3e98c244 2299 usleep_range(1000, 2000);
5fd4ce1b
CH		 2300 if (fatal_signal_pending(current))
2301 return -EINTR;
354201c5 2302 if (time_after(jiffies, timeout_jiffies)) {
1b3c47c1 2303 dev_err(ctrl->device,
94d2e705 2304 "Device not ready; aborting %s, CSTS=0x%x\n",
e6d275de 2305 op, csts);
5fd4ce1b
CH		 2306 return -ENODEV;
2307 }
2308 }
2309
2310 return ret;
2311}
2312
285b6e9b 2313int nvme_disable_ctrl(struct nvme_ctrl *ctrl, bool shutdown)
5fd4ce1b
CH		 2314{
2315 int ret;
2316
2317 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
285b6e9b
CH		 2318 if (shutdown)
2319 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
2320 else
2321 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
5fd4ce1b
CH		 2322
2323 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2324 if (ret)
2325 return ret;
54adc010 2326
285b6e9b
CH		 2327 if (shutdown) {
2328 return nvme_wait_ready(ctrl, NVME_CSTS_SHST_MASK,
2329 NVME_CSTS_SHST_CMPLT,
2330 ctrl->shutdown_timeout, "shutdown");
2331 }
b5a10c5f 2332 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010 2333 msleep(NVME_QUIRK_DELAY_AMOUNT);
e6d275de
CH		 2334 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, 0,
2335 (NVME_CAP_TIMEOUT(ctrl->cap) + 1) / 2, "reset");
5fd4ce1b 2336}
576d55d6 2337EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b 2338
c0f2f45b 2339int nvme_enable_ctrl(struct nvme_ctrl *ctrl)
5fd4ce1b 2340{
6c3c05b0 2341 unsigned dev_page_min;
354201c5 2342 u32 timeout;
5fd4ce1b
CH		 2343 int ret;
2344
c0f2f45b
SG		 2345 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2346 if (ret) {
2347 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
2348 return ret;
2349 }
2350 dev_page_min = NVME_CAP_MPSMIN(ctrl->cap) + 12;
2351
6c3c05b0 2352 if (NVME_CTRL_PAGE_SHIFT < dev_page_min) {
1b3c47c1 2353 dev_err(ctrl->device,
5fd4ce1b 2354 "Minimum device page size %u too large for host (%u)\n",
6c3c05b0 2355 1 << dev_page_min, 1 << NVME_CTRL_PAGE_SHIFT);
5fd4ce1b
CH		 2356 return -ENODEV;
2357 }
2358
71010c30
NC		 2359 if (NVME_CAP_CSS(ctrl->cap) & NVME_CAP_CSS_CSI)
2360 ctrl->ctrl_config = NVME_CC_CSS_CSI;
2361 else
2362 ctrl->ctrl_config = NVME_CC_CSS_NVM;
354201c5 2363
6cc834ba
KB		 2364 if (ctrl->cap & NVME_CAP_CRMS_CRWMS && ctrl->cap & NVME_CAP_CRMS_CRIMS)
2365 ctrl->ctrl_config |= NVME_CC_CRIME;
354201c5 2366
6c3c05b0 2367 ctrl->ctrl_config |= (NVME_CTRL_PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
60b43f62 2368 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b 2369 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
aa41d2fe
NC		 2370 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2371 if (ret)
2372 return ret;
5fd4ce1b 2373
aa41d2fe
NC		 2374 /* Flush write to device (required if transport is PCI) */
2375 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CC, &ctrl->ctrl_config);
2376 if (ret)
2377 return ret;
2378
6cc834ba
KB		 2379 /* CAP value may change after initial CC write */
2380 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &ctrl->cap);
2381 if (ret)
2382 return ret;
2383
2384 timeout = NVME_CAP_TIMEOUT(ctrl->cap);
2385 if (ctrl->cap & NVME_CAP_CRMS_CRWMS) {
2386 u32 crto, ready_timeout;
2387
2388 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CRTO, &crto);
2389 if (ret) {
2390 dev_err(ctrl->device, "Reading CRTO failed (%d)\n",
2391 ret);
2392 return ret;
2393 }
2394
2395 /*
2396 * CRTO should always be greater or equal to CAP.TO, but some
2397 * devices are known to get this wrong. Use the larger of the
2398 * two values.
2399 */
2400 if (ctrl->ctrl_config & NVME_CC_CRIME)
2401 ready_timeout = NVME_CRTO_CRIMT(crto);
2402 else
2403 ready_timeout = NVME_CRTO_CRWMT(crto);
2404
2405 if (ready_timeout < timeout)
2406 dev_warn_once(ctrl->device, "bad crto:%x cap:%llx\n",
2407 crto, ctrl->cap);
2408 else
2409 timeout = ready_timeout;
2410 }
2411
aa41d2fe 2412 ctrl->ctrl_config |= NVME_CC_ENABLE;
5fd4ce1b
CH		 2413 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
2414 if (ret)
2415 return ret;
e6d275de
CH		 2416 return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY,
2417 (timeout + 1) / 2, "initialisation");
5fd4ce1b 2418}
576d55d6 2419EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b 2420
dbf86b39
JD		 2421static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
2422{
2423 __le64 ts;
2424 int ret;
2425
2426 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
2427 return 0;
2428
2429 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
2430 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
2431 NULL);
2432 if (ret)
2433 dev_warn_once(ctrl->device,
2434 "could not set timestamp (%d)\n", ret);
2435 return ret;
2436}
2437
4020aad8 2438static int nvme_configure_host_options(struct nvme_ctrl *ctrl)
49cd84b6
KB		 2439{
2440 struct nvme_feat_host_behavior *host;
4020aad8 2441 u8 acre = 0, lbafee = 0;
49cd84b6
KB		 2442 int ret;
2443
2444 /* Don't bother enabling the feature if retry delay is not reported */
4020aad8
KB		 2445 if (ctrl->crdt[0])
2446 acre = NVME_ENABLE_ACRE;
2447 if (ctrl->ctratt & NVME_CTRL_ATTR_ELBAS)
2448 lbafee = NVME_ENABLE_LBAFEE;
2449
2450 if (!acre && !lbafee)
49cd84b6
KB		 2451 return 0;
2452
2453 host = kzalloc(sizeof(*host), GFP_KERNEL);
2454 if (!host)
2455 return 0;
2456
4020aad8
KB		 2457 host->acre = acre;
2458 host->lbafee = lbafee;
49cd84b6
KB		 2459 ret = nvme_set_features(ctrl, NVME_FEAT_HOST_BEHAVIOR, 0,
2460 host, sizeof(*host), NULL);
2461 kfree(host);
2462 return ret;
2463}
2464
ebd8a93a
AB		 2465/*
2466 * The function checks whether the given total (exlat + enlat) latency of
2467 * a power state allows the latter to be used as an APST transition target.
2468 * It does so by comparing the latency to the primary and secondary latency
2469 * tolerances defined by module params. If there's a match, the corresponding
2470 * timeout value is returned and the matching tolerance index (1 or 2) is
2471 * reported.
2472 */
2473static bool nvme_apst_get_transition_time(u64 total_latency,
2474 u64 *transition_time, unsigned *last_index)
2475{
2476 if (total_latency <= apst_primary_latency_tol_us) {
2477 if (*last_index == 1)
2478 return false;
2479 *last_index = 1;
2480 *transition_time = apst_primary_timeout_ms;
2481 return true;
2482 }
2483 if (apst_secondary_timeout_ms &&
2484 total_latency <= apst_secondary_latency_tol_us) {
2485 if (*last_index <= 2)
2486 return false;
2487 *last_index = 2;
2488 *transition_time = apst_secondary_timeout_ms;
2489 return true;
2490 }
2491 return false;
2492}
2493
60df5de9
CH		 2494/*
2495 * APST (Autonomous Power State Transition) lets us program a table of power
2496 * state transitions that the controller will perform automatically.
ebd8a93a
AB		 2497 *
2498 * Depending on module params, one of the two supported techniques will be used:
2499 *
2500 * - If the parameters provide explicit timeouts and tolerances, they will be
2501 * used to build a table with up to 2 non-operational states to transition to.
2502 * The default parameter values were selected based on the values used by
2503 * Microsoft's and Intel's NVMe drivers. Yet, since we don't implement dynamic
2504 * regeneration of the APST table in the event of switching between external
2505 * and battery power, the timeouts and tolerances reflect a compromise
2506 * between values used by Microsoft for AC and battery scenarios.
2507 * - If not, we'll configure the table with a simple heuristic: we are willing
2508 * to spend at most 2% of the time transitioning between power states.
2509 * Therefore, when running in any given state, we will enter the next
2510 * lower-power non-operational state after waiting 50 * (enlat + exlat)
2511 * microseconds, as long as that state's exit latency is under the requested
2512 * maximum latency.
60df5de9
CH		 2513 *
2514 * We will not autonomously enter any non-operational state for which the total
2515 * latency exceeds ps_max_latency_us.
2516 *
2517 * Users can set ps_max_latency_us to zero to turn off APST.
2518 */
634b8325 2519static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde 2520{
c5552fde 2521 struct nvme_feat_auto_pst *table;
60df5de9 2522 unsigned apste = 0;
fb0dc399 2523 u64 max_lat_us = 0;
60df5de9 2524 __le64 target = 0;
fb0dc399 2525 int max_ps = -1;
60df5de9 2526 int state;
c5552fde 2527 int ret;
ebd8a93a 2528 unsigned last_lt_index = UINT_MAX;
c5552fde
AL		 2529
2530 /*
2531 * If APST isn't supported or if we haven't been initialized yet,
2532 * then don't do anything.
2533 */
2534 if (!ctrl->apsta)
634b8325 2535 return 0;
c5552fde
AL		 2536
2537 if (ctrl->npss > 31) {
2538 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 2539 return 0;
c5552fde
AL		 2540 }
2541
2542 table = kzalloc(sizeof(*table), GFP_KERNEL);
2543 if (!table)
634b8325 2544 return 0;
c5552fde 2545
76a5af84 2546 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde 2547 /* Turn off APST. */
fb0dc399 2548 dev_dbg(ctrl->device, "APST disabled\n");
60df5de9
CH		 2549 goto done;
2550 }
c5552fde 2551
60df5de9
CH		 2552 /*
2553 * Walk through all states from lowest- to highest-power.
2554 * According to the spec, lower-numbered states use more power. NPSS,
2555 * despite the name, is the index of the lowest-power state, not the
2556 * number of states.
2557 */
2558 for (state = (int)ctrl->npss; state >= 0; state--) {
2559 u64 total_latency_us, exit_latency_us, transition_ms;
da87591b 2560
60df5de9
CH		 2561 if (target)
2562 table->entries[state] = target;
c5552fde 2563
c5552fde 2564 /*
60df5de9
CH		 2565 * Don't allow transitions to the deepest state if it's quirked
2566 * off.
c5552fde 2567 */
60df5de9
CH		 2568 if (state == ctrl->npss &&
2569 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
2570 continue;
fb0dc399 2571
60df5de9
CH		 2572 /*
2573 * Is this state a useful non-operational state for higher-power
2574 * states to autonomously transition to?
2575 */
2576 if (!(ctrl->psd[state].flags & NVME_PS_FLAGS_NON_OP_STATE))
2577 continue;
fb0dc399 2578
60df5de9
CH		 2579 exit_latency_us = (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
2580 if (exit_latency_us > ctrl->ps_max_latency_us)
2581 continue;
c5552fde 2582
60df5de9
CH		 2583 total_latency_us = exit_latency_us +
2584 le32_to_cpu(ctrl->psd[state].entry_lat);
fb0dc399 2585
60df5de9 2586 /*
ebd8a93a
AB		 2587 * This state is good. It can be used as the APST idle target
2588 * for higher power states.
60df5de9 2589 */
ebd8a93a
AB		 2590 if (apst_primary_timeout_ms && apst_primary_latency_tol_us) {
2591 if (!nvme_apst_get_transition_time(total_latency_us,
2592 &transition_ms, &last_lt_index))
2593 continue;
2594 } else {
2595 transition_ms = total_latency_us + 19;
2596 do_div(transition_ms, 20);
2597 if (transition_ms > (1 << 24) - 1)
2598 transition_ms = (1 << 24) - 1;
2599 }
60df5de9
CH		 2600
2601 target = cpu_to_le64((state << 3) | (transition_ms << 8));
2602 if (max_ps == -1)
2603 max_ps = state;
2604 if (total_latency_us > max_lat_us)
2605 max_lat_us = total_latency_us;
c5552fde
AL		 2606 }
2607
60df5de9
CH		 2608 if (max_ps == -1)
2609 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
2610 else
2611 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
2612 max_ps, max_lat_us, (int)sizeof(*table), table);
2613 apste = 1;
2614
2615done:
c5552fde
AL		 2616 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
2617 table, sizeof(*table), NULL);
2618 if (ret)
2619 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
c5552fde 2620 kfree(table);
634b8325 2621 return ret;
c5552fde
AL		 2622}
2623
2624static void nvme_set_latency_tolerance(struct device *dev, s32 val)
2625{
2626 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2627 u64 latency;
2628
2629 switch (val) {
2630 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
2631 case PM_QOS_LATENCY_ANY:
2632 latency = U64_MAX;
2633 break;
2634
2635 default:
2636 latency = val;
2637 }
2638
2639 if (ctrl->ps_max_latency_us != latency) {
2640 ctrl->ps_max_latency_us = latency;
e6e7f7ac 2641 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE)
53fe2a30 2642 nvme_configure_apst(ctrl);
c5552fde
AL		 2643 }
2644}
2645
bd4da3ab
AL		 2646struct nvme_core_quirk_entry {
2647 /*
2648 * NVMe model and firmware strings are padded with spaces. For
2649 * simplicity, strings in the quirk table are padded with NULLs
2650 * instead.
2651 */
2652 u16 vid;
2653 const char *mn;
2654 const char *fr;
2655 unsigned long quirks;
2656};
2657
2658static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 2659 {
be56945c
AL		 2660 /*
2661 * This Toshiba device seems to die using any APST states. See:
2662 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
2663 */
2664 .vid = 0x1179,
2665 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 2666 .quirks = NVME_QUIRK_NO_APST,
cb32de1b
ML		 2667 },
2668 {
2669 /*
2670 * This LiteON CL1-3D*-Q11 firmware version has a race
2671 * condition associated with actions related to suspend to idle
2672 * LiteON has resolved the problem in future firmware
2673 */
2674 .vid = 0x14a4,
2675 .fr = "22301111",
2676 .quirks = NVME_QUIRK_SIMPLE_SUSPEND,
5a6254d5
EM		 2677 },
2678 {
2679 /*
2680 * This Kioxia CD6-V Series / HPE PE8030 device times out and
2681 * aborts I/O during any load, but more easily reproducible
2682 * with discards (fstrim).
2683 *
2684 * The device is left in a state where it is also not possible
2685 * to use "nvme set-feature" to disable APST, but booting with
2686 * nvme_core.default_ps_max_latency=0 works.
2687 */
2688 .vid = 0x1e0f,
2689 .mn = "KCD6XVUL6T40",
2690 .quirks = NVME_QUIRK_NO_APST,
e6487833
CH		 2691 },
2692 {
2693 /*
2694 * The external Samsung X5 SSD fails initialization without a
2695 * delay before checking if it is ready and has a whole set of
2696 * other problems. To make this even more interesting, it
2697 * shares the PCI ID with internal Samsung 970 Evo Plus that
2698 * does not need or want these quirks.
2699 */
2700 .vid = 0x144d,
2701 .mn = "Samsung Portable SSD X5",
2702 .quirks = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
2703 NVME_QUIRK_NO_DEEPEST_PS |
2704 NVME_QUIRK_IGNORE_DEV_SUBNQN,
be56945c 2705 }
bd4da3ab
AL		 2706};
2707
2708/* match is null-terminated but idstr is space-padded. */
2709static bool string_matches(const char *idstr, const char *match, size_t len)
2710{
2711 size_t matchlen;
2712
2713 if (!match)
2714 return true;
2715
2716 matchlen = strlen(match);
2717 WARN_ON_ONCE(matchlen > len);
2718
2719 if (memcmp(idstr, match, matchlen))
2720 return false;
2721
2722 for (; matchlen < len; matchlen++)
2723 if (idstr[matchlen] != ' ')
2724 return false;
2725
2726 return true;
2727}
2728
2729static bool quirk_matches(const struct nvme_id_ctrl *id,
2730 const struct nvme_core_quirk_entry *q)
2731{
2732 return q->vid == le16_to_cpu(id->vid) &&
2733 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
2734 string_matches(id->fr, q->fr, sizeof(id->fr));
2735}
2736
ab9e00cc
CH		 2737static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
2738 struct nvme_id_ctrl *id)
180de007
CH		 2739{
2740 size_t nqnlen;
2741 int off;
2742
6299358d
JD		 2743 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
2744 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
2745 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
a8817cc0 2746 strscpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
6299358d
JD		 2747 return;
2748 }
180de007 2749
6299358d
JD		 2750 if (ctrl->vs >= NVME_VS(1, 2, 1))
2751 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
2752 }
180de007 2753
1abc6961
LB		 2754 /*
2755 * Generate a "fake" NQN similar to the one in Section 4.5 of the NVMe
2756 * Base Specification 2.0. It is slightly different from the format
2757 * specified there due to historic reasons, and we can't change it now.
2758 */
ab9e00cc 2759 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
3da584f5 2760 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 2761 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 2762 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 2763 off += sizeof(id->sn);
ab9e00cc 2764 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 2765 off += sizeof(id->mn);
ab9e00cc
CH		 2766 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
2767}
2768
e654dfd3 2769static void nvme_release_subsystem(struct device *dev)
ab9e00cc 2770{
e654dfd3
LG		 2771 struct nvme_subsystem *subsys =
2772 container_of(dev, struct nvme_subsystem, dev);
2773
733e4b69 2774 if (subsys->instance >= 0)
8b850475 2775 ida_free(&nvme_instance_ida, subsys->instance);
ab9e00cc
CH		 2776 kfree(subsys);
2777}
2778
ab9e00cc
CH		 2779static void nvme_destroy_subsystem(struct kref *ref)
2780{
2781 struct nvme_subsystem *subsys =
2782 container_of(ref, struct nvme_subsystem, ref);
2783
2784 mutex_lock(&nvme_subsystems_lock);
2785 list_del(&subsys->entry);
2786 mutex_unlock(&nvme_subsystems_lock);
2787
ed754e5d 2788 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2789 device_del(&subsys->dev);
2790 put_device(&subsys->dev);
2791}
2792
2793static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2794{
2795 kref_put(&subsys->ref, nvme_destroy_subsystem);
2796}
2797
2798static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2799{
2800 struct nvme_subsystem *subsys;
2801
2802 lockdep_assert_held(&nvme_subsystems_lock);
2803
c26aa572
JS		 2804 /*
2805 * Fail matches for discovery subsystems. This results
2806 * in each discovery controller bound to a unique subsystem.
2807 * This avoids issues with validating controller values
2808 * that can only be true when there is a single unique subsystem.
2809 * There may be multiple and completely independent entities
2810 * that provide discovery controllers.
2811 */
2812 if (!strcmp(subsysnqn, NVME_DISC_SUBSYS_NAME))
2813 return NULL;
2814
ab9e00cc
CH		 2815 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2816 if (strcmp(subsys->subnqn, subsysnqn))
2817 continue;
2818 if (!kref_get_unless_zero(&subsys->ref))
2819 continue;
2820 return subsys;
2821 }
2822
2823 return NULL;
2824}
2825
5ab25a32
SG		 2826static inline bool nvme_discovery_ctrl(struct nvme_ctrl *ctrl)
2827{
2828 return ctrl->opts && ctrl->opts->discovery_nqn;
2829}
2830
1b1031ca
CH		 2831static bool nvme_validate_cntlid(struct nvme_subsystem *subsys,
2832 struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
b837b283 2833{
1b1031ca 2834 struct nvme_ctrl *tmp;
b837b283 2835
32fd90c4
CH		 2836 lockdep_assert_held(&nvme_subsystems_lock);
2837
1b1031ca 2838 list_for_each_entry(tmp, &subsys->ctrls, subsys_entry) {
e7c43fea 2839 if (nvme_state_terminal(tmp))
1b1031ca
CH		 2840 continue;
2841
2842 if (tmp->cntlid == ctrl->cntlid) {
2843 dev_err(ctrl->device,
16cc33b2
KB		 2844 "Duplicate cntlid %u with %s, subsys %s, rejecting\n",
2845 ctrl->cntlid, dev_name(tmp->device),
2846 subsys->subnqn);
1b1031ca
CH		 2847 return false;
2848 }
b837b283 2849
92decf11 2850 if ((id->cmic & NVME_CTRL_CMIC_MULTI_CTRL) ||
5ab25a32 2851 nvme_discovery_ctrl(ctrl))
1b1031ca
CH		 2852 continue;
2853
2854 dev_err(ctrl->device,
2855 "Subsystem does not support multiple controllers\n");
2856 return false;
b837b283 2857 }
b837b283 2858
1b1031ca 2859 return true;
b837b283
IR		 2860}
2861
ab9e00cc
CH		 2862static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2863{
2864 struct nvme_subsystem *subsys, *found;
2865 int ret;
2866
2867 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2868 if (!subsys)
2869 return -ENOMEM;
733e4b69
KB		 2870
2871 subsys->instance = -1;
ab9e00cc
CH		 2872 mutex_init(&subsys->lock);
2873 kref_init(&subsys->ref);
2874 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2875 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2876 nvme_init_subnqn(subsys, ctrl, id);
2877 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2878 memcpy(subsys->model, id->mn, sizeof(subsys->model));
ab9e00cc
CH		 2879 subsys->vendor_id = le16_to_cpu(id->vid);
2880 subsys->cmic = id->cmic;
954ae166
HR		 2881
2882 /* Versions prior to 1.4 don't necessarily report a valid type */
2883 if (id->cntrltype == NVME_CTRL_DISC ||
2884 !strcmp(subsys->subnqn, NVME_DISC_SUBSYS_NAME))
2885 subsys->subtype = NVME_NQN_DISC;
2886 else
2887 subsys->subtype = NVME_NQN_NVME;
2888
20e8b689
HR		 2889 if (nvme_discovery_ctrl(ctrl) && subsys->subtype != NVME_NQN_DISC) {
2890 dev_err(ctrl->device,
2891 "Subsystem %s is not a discovery controller",
2892 subsys->subnqn);
2893 kfree(subsys);
2894 return -EINVAL;
2895 }
81adb863 2896 subsys->awupf = le16_to_cpu(id->awupf);
e3d34794 2897 nvme_mpath_default_iopolicy(subsys);
ab9e00cc 2898
ab21f3d9 2899 subsys->dev.class = &nvme_subsys_class;
ab9e00cc 2900 subsys->dev.release = nvme_release_subsystem;
1e496938 2901 subsys->dev.groups = nvme_subsys_attrs_groups;
733e4b69 2902 dev_set_name(&subsys->dev, "nvme-subsys%d", ctrl->instance);
ab9e00cc
CH		 2903 device_initialize(&subsys->dev);
2904
2905 mutex_lock(&nvme_subsystems_lock);
2906 found = __nvme_find_get_subsystem(subsys->subnqn);
2907 if (found) {
e654dfd3 2908 put_device(&subsys->dev);
ab9e00cc 2909 subsys = found;
32fd90c4 2910
1b1031ca 2911 if (!nvme_validate_cntlid(subsys, ctrl, id)) {
ab9e00cc 2912 ret = -EINVAL;
32fd90c4 2913 goto out_put_subsystem;
ab9e00cc 2914 }
ab9e00cc
CH		 2915 } else {
2916 ret = device_add(&subsys->dev);
2917 if (ret) {
2918 dev_err(ctrl->device,
2919 "failed to register subsystem device.\n");
8c36e66f 2920 put_device(&subsys->dev);
ab9e00cc
CH		 2921 goto out_unlock;
2922 }
ed754e5d 2923 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2924 list_add_tail(&subsys->entry, &nvme_subsystems);
2925 }
2926
bc4f6e06
DC		 2927 ret = sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2928 dev_name(ctrl->device));
2929 if (ret) {
ab9e00cc
CH		 2930 dev_err(ctrl->device,
2931 "failed to create sysfs link from subsystem.\n");
32fd90c4 2932 goto out_put_subsystem;
ab9e00cc
CH		 2933 }
2934
733e4b69
KB		 2935 if (!found)
2936 subsys->instance = ctrl->instance;
32fd90c4 2937 ctrl->subsys = subsys;
ab9e00cc 2938 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
32fd90c4 2939 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc
CH		 2940 return 0;
2941
32fd90c4
CH		 2942out_put_subsystem:
2943 nvme_put_subsystem(subsys);
ab9e00cc
CH		 2944out_unlock:
2945 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 2946 return ret;
180de007
CH		 2947}
2948
be93e87e 2949int nvme_get_log(struct nvme_ctrl *ctrl, u32 nsid, u8 log_page, u8 lsp, u8 csi,
0e98719b 2950 void *log, size_t size, u64 offset)
c627c487
KB		 2951{
2952 struct nvme_command c = { };
71fb90eb 2953 u32 dwlen = nvme_bytes_to_numd(size);
70da6094
MB		 2954
2955 c.get_log_page.opcode = nvme_admin_get_log_page;
0e98719b 2956 c.get_log_page.nsid = cpu_to_le32(nsid);
70da6094 2957 c.get_log_page.lid = log_page;
0e98719b 2958 c.get_log_page.lsp = lsp;
70da6094
MB		 2959 c.get_log_page.numdl = cpu_to_le16(dwlen & ((1 << 16) - 1));
2960 c.get_log_page.numdu = cpu_to_le16(dwlen >> 16);
7ec6074f
MB		 2961 c.get_log_page.lpol = cpu_to_le32(lower_32_bits(offset));
2962 c.get_log_page.lpou = cpu_to_le32(upper_32_bits(offset));
be93e87e 2963 c.get_log_page.csi = csi;
c627c487
KB		 2964
2965 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2966}
2967
be93e87e
KB		 2968static int nvme_get_effects_log(struct nvme_ctrl *ctrl, u8 csi,
2969 struct nvme_effects_log **log)
84fef62d 2970{
f6224b86 2971 struct nvme_effects_log *cel = xa_load(&ctrl->cels, csi);
84fef62d
KB		 2972 int ret;
2973
be93e87e
KB		 2974 if (cel)
2975 goto out;
84fef62d 2976
be93e87e
KB		 2977 cel = kzalloc(sizeof(*cel), GFP_KERNEL);
2978 if (!cel)
2979 return -ENOMEM;
84fef62d 2980
46d2613e 2981 ret = nvme_get_log(ctrl, 0x00, NVME_LOG_CMD_EFFECTS, 0, csi,
f6224b86 2982 cel, sizeof(*cel), 0);
84fef62d 2983 if (ret) {
be93e87e
KB		 2984 kfree(cel);
2985 return ret;
84fef62d 2986 }
be93e87e 2987
f6224b86 2988 xa_store(&ctrl->cels, csi, cel, GFP_KERNEL);
be93e87e 2989out:
f6224b86 2990 *log = cel;
be93e87e 2991 return 0;
180de007
CH		 2992}
2993
5befc7c2 2994static inline u32 nvme_mps_to_sectors(struct nvme_ctrl *ctrl, u32 units)
7fd8930f 2995{
8609c63f 2996 u32 page_shift = NVME_CAP_MPSMIN(ctrl->cap) + 12, val;
7fd8930f 2997
8609c63f
BVA		 2998 if (check_shl_overflow(1U, units + page_shift - 9, &val))
2999 return UINT_MAX;
3000 return val;
5befc7c2
KB		 3001}
3002
3003static int nvme_init_non_mdts_limits(struct nvme_ctrl *ctrl)
3004{
3005 struct nvme_command c = { };
3006 struct nvme_id_ctrl_nvm *id;
3007 int ret;
3008
5befc7c2
KB		 3009 /*
3010 * Even though NVMe spec explicitly states that MDTS is not applicable
3011 * to the write-zeroes, we are cautious and limit the size to the
3012 * controllers max_hw_sectors value, which is based on the MDTS field
3013 * and possibly other limiting factors.
3014 */
3015 if ((ctrl->oncs & NVME_CTRL_ONCS_WRITE_ZEROES) &&
3016 !(ctrl->quirks & NVME_QUIRK_DISABLE_WRITE_ZEROES))
3017 ctrl->max_zeroes_sectors = ctrl->max_hw_sectors;
3018 else
3019 ctrl->max_zeroes_sectors = 0;
3020
def84ab6 3021 if (ctrl->subsys->subtype != NVME_NQN_NVME ||
c917dd96
KB		 3022 nvme_ctrl_limited_cns(ctrl) ||
3023 test_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags))
5befc7c2
KB		 3024 return 0;
3025
3026 id = kzalloc(sizeof(*id), GFP_KERNEL);
3027 if (!id)
bcaf434b 3028 return -ENOMEM;
5befc7c2
KB		 3029
3030 c.identify.opcode = nvme_admin_identify;
3031 c.identify.cns = NVME_ID_CNS_CS_CTRL;
3032 c.identify.csi = NVME_CSI_NVM;
3033
3034 ret = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
3035 if (ret)
3036 goto free_data;
3037
3b946fe1 3038 ctrl->dmrl = id->dmrl;
1a86924e 3039 ctrl->dmrsl = le32_to_cpu(id->dmrsl);
5befc7c2
KB		 3040 if (id->wzsl)
3041 ctrl->max_zeroes_sectors = nvme_mps_to_sectors(ctrl, id->wzsl);
3042
3043free_data:
c917dd96
KB		 3044 if (ret > 0)
3045 set_bit(NVME_CTRL_SKIP_ID_CNS_CS, &ctrl->flags);
5befc7c2
KB		 3046 kfree(id);
3047 return ret;
3048}
3049
cc115cbe
KB		 3050static void nvme_init_known_nvm_effects(struct nvme_ctrl *ctrl)
3051{
3052 struct nvme_effects_log *log = ctrl->effects;
3053
3054 log->acs[nvme_admin_format_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC |
3055 NVME_CMD_EFFECTS_NCC |
3056 NVME_CMD_EFFECTS_CSE_MASK);
3057 log->acs[nvme_admin_sanitize_nvm] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC |
3058 NVME_CMD_EFFECTS_CSE_MASK);
3059
baff6491
KB		 3060 /*
3061 * The spec says the result of a security receive command depends on
3062 * the previous security send command. As such, many vendors log this
3063 * command as one to submitted only when no other commands to the same
3064 * namespace are outstanding. The intention is to tell the host to
3065 * prevent mixing security send and receive.
3066 *
3067 * This driver can only enforce such exclusive access against IO
3068 * queues, though. We are not readily able to enforce such a rule for
3069 * two commands to the admin queue, which is the only queue that
3070 * matters for this command.
3071 *
3072 * Rather than blindly freezing the IO queues for this effect that
3073 * doesn't even apply to IO, mask it off.
3074 */
c0c33b94 3075 log->acs[nvme_admin_security_recv] &= cpu_to_le32(~NVME_CMD_EFFECTS_CSE_MASK);
baff6491 3076
cc115cbe
KB		 3077 log->iocs[nvme_cmd_write] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3078 log->iocs[nvme_cmd_write_zeroes] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3079 log->iocs[nvme_cmd_write_uncor] |= cpu_to_le32(NVME_CMD_EFFECTS_LBCC);
3080}
3081
3082static int nvme_init_effects(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
3083{
3084 int ret = 0;
3085
3086 if (ctrl->effects)
3087 return 0;
3088
3089 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
3090 ret = nvme_get_effects_log(ctrl, NVME_CSI_NVM, &ctrl->effects);
3091 if (ret < 0)
3092 return ret;
3093 }
3094
3095 if (!ctrl->effects) {
3096 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
3097 if (!ctrl->effects)
3098 return -ENOMEM;
3099 xa_store(&ctrl->cels, NVME_CSI_NVM, ctrl->effects, GFP_KERNEL);
3100 }
3101
3102 nvme_init_known_nvm_effects(ctrl);
3103 return 0;
3104}
3105
68999d1d
GL		 3106static int nvme_check_ctrl_fabric_info(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
3107{
3108 /*
3109 * In fabrics we need to verify the cntlid matches the
3110 * admin connect
3111 */
3112 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
3113 dev_err(ctrl->device,
3114 "Mismatching cntlid: Connect %u vs Identify %u, rejecting\n",
3115 ctrl->cntlid, le16_to_cpu(id->cntlid));
3116 return -EINVAL;
3117 }
3118
3119 if (!nvme_discovery_ctrl(ctrl) && !ctrl->kas) {
3120 dev_err(ctrl->device,
3121 "keep-alive support is mandatory for fabrics\n");
3122 return -EINVAL;
3123 }
3124
7642138e 3125 if (!nvme_discovery_ctrl(ctrl) && ctrl->ioccsz < 4) {
2fcd3ab3
GL		 3126 dev_err(ctrl->device,
3127 "I/O queue command capsule supported size %d < 4\n",
3128 ctrl->ioccsz);
3129 return -EINVAL;
3130 }
3131
7642138e 3132 if (!nvme_discovery_ctrl(ctrl) && ctrl->iorcsz < 1) {
2fcd3ab3
GL		 3133 dev_err(ctrl->device,
3134 "I/O queue response capsule supported size %d < 1\n",
3135 ctrl->iorcsz);
3136 return -EINVAL;
3137 }
3138
49995681
GL		 3139 if (!ctrl->maxcmd) {
3140 dev_err(ctrl->device, "Maximum outstanding commands is 0\n");
3141 return -EINVAL;
3142 }
3143
68999d1d
GL		 3144 return 0;
3145}
3146
44ef5611 3147static int nvme_init_identify(struct nvme_ctrl *ctrl)
7fd8930f 3148{
e6c9b130 3149 struct queue_limits lim;
7fd8930f 3150 struct nvme_id_ctrl *id;
a229dbf6 3151 u32 max_hw_sectors;
76a5af84 3152 bool prev_apst_enabled;
5befc7c2 3153 int ret;
f3ca80fc 3154
7fd8930f
CH		 3155 ret = nvme_identify_ctrl(ctrl, &id);
3156 if (ret) {
1b3c47c1 3157 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 3158 return -EIO;
3159 }
3160
a89fcca8
GP		 3161 if (!(ctrl->ops->flags & NVME_F_FABRICS))
3162 ctrl->cntlid = le16_to_cpu(id->cntlid);
3163
bd4da3ab 3164 if (!ctrl->identified) {
44ef5611 3165 unsigned int i;
ab9e00cc 3166
bd4da3ab
AL		 3167 /*
3168 * Check for quirks. Quirk can depend on firmware version,
3169 * so, in principle, the set of quirks present can change
3170 * across a reset. As a possible future enhancement, we
3171 * could re-scan for quirks every time we reinitialize
3172 * the device, but we'd have to make sure that the driver
3173 * behaves intelligently if the quirks change.
3174 */
bd4da3ab
AL		 3175 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
3176 if (quirk_matches(id, &core_quirks[i]))
3177 ctrl->quirks |= core_quirks[i].quirks;
3178 }
6f2d7152
PR		 3179
3180 ret = nvme_init_subsystem(ctrl, id);
3181 if (ret)
3182 goto out_free;
cc115cbe
KB		 3183
3184 ret = nvme_init_effects(ctrl, id);
3185 if (ret)
3186 goto out_free;
bd4da3ab 3187 }
a8eb6c1b
KB		 3188 memcpy(ctrl->subsys->firmware_rev, id->fr,
3189 sizeof(ctrl->subsys->firmware_rev));
bd4da3ab 3190
c35e30b4 3191 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 3192 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 3193 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
3194 }
3195
49cd84b6
KB		 3196 ctrl->crdt[0] = le16_to_cpu(id->crdt1);
3197 ctrl->crdt[1] = le16_to_cpu(id->crdt2);
3198 ctrl->crdt[2] = le16_to_cpu(id->crdt3);
3199
8a9ae523 3200 ctrl->oacs = le16_to_cpu(id->oacs);
43e2d08d 3201 ctrl->oncs = le16_to_cpu(id->oncs);
2d466c7a 3202 ctrl->mtfa = le16_to_cpu(id->mtfa);
c0561f82 3203 ctrl->oaes = le32_to_cpu(id->oaes);
400b6a7b
GR		 3204 ctrl->wctemp = le16_to_cpu(id->wctemp);
3205 ctrl->cctemp = le16_to_cpu(id->cctemp);
3206
6bf25d16 3207 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 3208 ctrl->vwc = id->vwc;
7fd8930f 3209 if (id->mdts)
5befc7c2 3210 max_hw_sectors = nvme_mps_to_sectors(ctrl, id->mdts);
7fd8930f 3211 else
a229dbf6
CH		 3212 max_hw_sectors = UINT_MAX;
3213 ctrl->max_hw_sectors =
3214 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 3215
e6c9b130
CH		 3216 lim = queue_limits_start_update(ctrl->admin_q);
3217 nvme_set_ctrl_limits(ctrl, &lim);
3218 ret = queue_limits_commit_update(ctrl->admin_q, &lim);
3219 if (ret)
3220 goto out_free;
3221
07bfcd09 3222 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 3223 ctrl->kas = le16_to_cpu(id->kas);
0d0b660f 3224 ctrl->max_namespaces = le32_to_cpu(id->mnan);
3e53ba38 3225 ctrl->ctratt = le32_to_cpu(id->ctratt);
07bfcd09 3226
86c2457a
MB		 3227 ctrl->cntrltype = id->cntrltype;
3228 ctrl->dctype = id->dctype;
3229
07fbd32a
MP		 3230 if (id->rtd3e) {
3231 /* us -> s */
f5af577d 3232 u32 transition_time = le32_to_cpu(id->rtd3e) / USEC_PER_SEC;
07fbd32a
MP		 3233
3234 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
3235 shutdown_timeout, 60);
3236
3237 if (ctrl->shutdown_timeout != shutdown_timeout)
1a3838d7 3238 dev_info(ctrl->device,
34485c37 3239 "D3 entry latency set to %u seconds\n",
07fbd32a
MP		 3240 ctrl->shutdown_timeout);
3241 } else
3242 ctrl->shutdown_timeout = shutdown_timeout;
3243
c5552fde 3244 ctrl->npss = id->npss;
76a5af84
KHF		 3245 ctrl->apsta = id->apsta;
3246 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 3247 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
3248 if (force_apst && id->apsta) {
f0425db0 3249 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 3250 ctrl->apst_enabled = true;
c35e30b4 3251 } else {
76a5af84 3252 ctrl->apst_enabled = false;
c35e30b4
AL		 3253 }
3254 } else {
76a5af84 3255 ctrl->apst_enabled = id->apsta;
c35e30b4 3256 }
c5552fde
AL		 3257 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
3258
d3d5b87d 3259 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 3260 ctrl->icdoff = le16_to_cpu(id->icdoff);
3261 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
3262 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
3263 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
3264
68999d1d
GL		 3265 ret = nvme_check_ctrl_fabric_info(ctrl, id);
3266 if (ret)
634b8325 3267 goto out_free;
07bfcd09 3268 } else {
fe6d53c9
CH		 3269 ctrl->hmpre = le32_to_cpu(id->hmpre);
3270 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 3271 ctrl->hmminds = le32_to_cpu(id->hmminds);
3272 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 3273 }
da35825d 3274
5e1f6899 3275 ret = nvme_mpath_init_identify(ctrl, id);
0d0b660f 3276 if (ret < 0)
44ef5611 3277 goto out_free;
0d0b660f 3278
76a5af84 3279 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 3280 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 3281 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 3282 dev_pm_qos_hide_latency_tolerance(ctrl->device);
3283
44ef5611
CK		 3284out_free:
3285 kfree(id);
3286 return ret;
3287}
3288
3289/*
3290 * Initialize the cached copies of the Identify data and various controller
3291 * register in our nvme_ctrl structure. This should be called as soon as
3292 * the admin queue is fully up and running.
3293 */
94cc781f 3294int nvme_init_ctrl_finish(struct nvme_ctrl *ctrl, bool was_suspended)
44ef5611
CK		 3295{
3296 int ret;
3297
3298 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
3299 if (ret) {
3300 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
3301 return ret;
3302 }
3303
3304 ctrl->sqsize = min_t(u16, NVME_CAP_MQES(ctrl->cap), ctrl->sqsize);
3305
3306 if (ctrl->vs >= NVME_VS(1, 1, 0))
3307 ctrl->subsystem = NVME_CAP_NSSRC(ctrl->cap);
3308
3309 ret = nvme_init_identify(ctrl);
3310 if (ret)
3311 return ret;
3312
634b8325
KB		 3313 ret = nvme_configure_apst(ctrl);
3314 if (ret < 0)
3315 return ret;
95d54bd1 3316
dbf86b39
JD		 3317 ret = nvme_configure_timestamp(ctrl);
3318 if (ret < 0)
3319 return ret;
634b8325 3320
4020aad8 3321 ret = nvme_configure_host_options(ctrl);
49cd84b6
KB		 3322 if (ret < 0)
3323 return ret;
3324
94cc781f
CH		 3325 nvme_configure_opal(ctrl, was_suspended);
3326
5ab25a32 3327 if (!ctrl->identified && !nvme_discovery_ctrl(ctrl)) {
6b8cf940
CH		 3328 /*
3329 * Do not return errors unless we are in a controller reset,
3330 * the controller works perfectly fine without hwmon.
3331 */
59e330f8 3332 ret = nvme_hwmon_init(ctrl);
6b8cf940 3333 if (ret == -EINTR)
59e330f8
KB		 3334 return ret;
3335 }
400b6a7b 3336
d0dd594b 3337 clear_bit(NVME_CTRL_DIRTY_CAPABILITY, &ctrl->flags);
bd4da3ab 3338 ctrl->identified = true;
c5552fde 3339
4733b65d
HR		 3340 nvme_start_keep_alive(ctrl);
3341
634b8325 3342 return 0;
7fd8930f 3343}
f21c4769 3344EXPORT_SYMBOL_GPL(nvme_init_ctrl_finish);
7fd8930f 3345
f3ca80fc 3346static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 3347{
a6a5149b
CH		 3348 struct nvme_ctrl *ctrl =
3349 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 3350
e6e7f7ac 3351 switch (nvme_ctrl_state(ctrl)) {
2b1b7e78 3352 case NVME_CTRL_LIVE:
2b1b7e78
JW		 3353 break;
3354 default:
a6a5149b 3355 return -EWOULDBLOCK;
2b1b7e78
JW		 3356 }
3357
52a3974f 3358 nvme_get_ctrl(ctrl);
4bab6909
CK		 3359 if (!try_module_get(ctrl->ops->module)) {
3360 nvme_put_ctrl(ctrl);
52a3974f 3361 return -EINVAL;
4bab6909 3362 }
52a3974f 3363
a6a5149b 3364 file->private_data = ctrl;
f3ca80fc
CH		 3365 return 0;
3366}
3367
52a3974f
CK		 3368static int nvme_dev_release(struct inode *inode, struct file *file)
3369{
3370 struct nvme_ctrl *ctrl =
3371 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
3372
3373 module_put(ctrl->ops->module);
3374 nvme_put_ctrl(ctrl);
3375 return 0;
3376}
3377
f3ca80fc
CH		 3378static const struct file_operations nvme_dev_fops = {
3379 .owner = THIS_MODULE,
3380 .open = nvme_dev_open,
52a3974f 3381 .release = nvme_dev_release,
f3ca80fc 3382 .unlocked_ioctl = nvme_dev_ioctl,
1832f2d8 3383 .compat_ioctl = compat_ptr_ioctl,
58e5bdeb 3384 .uring_cmd = nvme_dev_uring_cmd,
f3ca80fc
CH		 3385};
3386
5974ea7c 3387static struct nvme_ns_head *nvme_find_ns_head(struct nvme_ctrl *ctrl,
ed754e5d
CH		 3388 unsigned nsid)
3389{
3390 struct nvme_ns_head *h;
3391
5974ea7c 3392 lockdep_assert_held(&ctrl->subsys->lock);
ed754e5d 3393
5974ea7c
SM		 3394 list_for_each_entry(h, &ctrl->subsys->nsheads, entry) {
3395 /*
3396 * Private namespaces can share NSIDs under some conditions.
3397 * In that case we can't use the same ns_head for namespaces
3398 * with the same NSID.
3399 */
3400 if (h->ns_id != nsid || !nvme_is_unique_nsid(ctrl, h))
9edceaf4
DW		 3401 continue;
3402 if (!list_empty(&h->list) && nvme_tryget_ns_head(h))
ed754e5d
CH		 3403 return h;
3404 }
3405
3406 return NULL;
3407}
3408
fd8099e7
CH		 3409static int nvme_subsys_check_duplicate_ids(struct nvme_subsystem *subsys,
3410 struct nvme_ns_ids *ids)
ed754e5d 3411{
e2724cb9
CH		 3412 bool has_uuid = !uuid_is_null(&ids->uuid);
3413 bool has_nguid = memchr_inv(ids->nguid, 0, sizeof(ids->nguid));
3414 bool has_eui64 = memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
ed754e5d
CH		 3415 struct nvme_ns_head *h;
3416
3417 lockdep_assert_held(&subsys->lock);
3418
3419 list_for_each_entry(h, &subsys->nsheads, entry) {
e2724cb9
CH		 3420 if (has_uuid && uuid_equal(&ids->uuid, &h->ids.uuid))
3421 return -EINVAL;
3422 if (has_nguid &&
3423 memcmp(&ids->nguid, &h->ids.nguid, sizeof(ids->nguid)) == 0)
3424 return -EINVAL;
3425 if (has_eui64 &&
3426 memcmp(&ids->eui64, &h->ids.eui64, sizeof(ids->eui64)) == 0)
ed754e5d
CH		 3427 return -EINVAL;
3428 }
3429
3430 return 0;
3431}
3432
be5eb933
AM		 3433static void nvme_cdev_rel(struct device *dev)
3434{
8b850475 3435 ida_free(&nvme_ns_chr_minor_ida, MINOR(dev->devt));
be5eb933
AM		 3436}
3437
2637baed
MI		 3438void nvme_cdev_del(struct cdev *cdev, struct device *cdev_device)
3439{
3440 cdev_device_del(cdev, cdev_device);
be5eb933 3441 put_device(cdev_device);
2637baed
MI		 3442}
3443
3444int nvme_cdev_add(struct cdev *cdev, struct device *cdev_device,
3445 const struct file_operations *fops, struct module *owner)
3446{
3447 int minor, ret;
3448
8b850475 3449 minor = ida_alloc(&nvme_ns_chr_minor_ida, GFP_KERNEL);
2637baed
MI		 3450 if (minor < 0)
3451 return minor;
3452 cdev_device->devt = MKDEV(MAJOR(nvme_ns_chr_devt), minor);
ab21f3d9 3453 cdev_device->class = &nvme_ns_chr_class;
be5eb933 3454 cdev_device->release = nvme_cdev_rel;
2637baed
MI		 3455 device_initialize(cdev_device);
3456 cdev_init(cdev, fops);
3457 cdev->owner = owner;
3458 ret = cdev_device_add(cdev, cdev_device);
be5eb933 3459 if (ret)
3596a065 3460 put_device(cdev_device);
be5eb933 3461
2637baed
MI		 3462 return ret;
3463}
3464
3465static int nvme_ns_chr_open(struct inode *inode, struct file *file)
3466{
3467 return nvme_ns_open(container_of(inode->i_cdev, struct nvme_ns, cdev));
3468}
3469
3470static int nvme_ns_chr_release(struct inode *inode, struct file *file)
3471{
3472 nvme_ns_release(container_of(inode->i_cdev, struct nvme_ns, cdev));
3473 return 0;
3474}
3475
3476static const struct file_operations nvme_ns_chr_fops = {
3477 .owner = THIS_MODULE,
3478 .open = nvme_ns_chr_open,
3479 .release = nvme_ns_chr_release,
3480 .unlocked_ioctl = nvme_ns_chr_ioctl,
3481 .compat_ioctl = compat_ptr_ioctl,
456cba38 3482 .uring_cmd = nvme_ns_chr_uring_cmd,
585079b6 3483 .uring_cmd_iopoll = nvme_ns_chr_uring_cmd_iopoll,
2637baed
MI		 3484};
3485
3486static int nvme_add_ns_cdev(struct nvme_ns *ns)
3487{
3488 int ret;
3489
3490 ns->cdev_device.parent = ns->ctrl->device;
3491 ret = dev_set_name(&ns->cdev_device, "ng%dn%d",
3492 ns->ctrl->instance, ns->head->instance);
3493 if (ret)
3494 return ret;
be5eb933
AM		 3495
3496 return nvme_cdev_add(&ns->cdev, &ns->cdev_device, &nvme_ns_chr_fops,
3497 ns->ctrl->ops->module);
2637baed
MI		 3498}
3499
ed754e5d 3500static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
1a893c2b 3501 struct nvme_ns_info *info)
ed754e5d
CH		 3502{
3503 struct nvme_ns_head *head;
f3334447 3504 size_t size = sizeof(*head);
ed754e5d
CH		 3505 int ret = -ENOMEM;
3506
f3334447
CH		 3507#ifdef CONFIG_NVME_MULTIPATH
3508 size += num_possible_nodes() * sizeof(struct nvme_ns *);
3509#endif
3510
3511 head = kzalloc(size, GFP_KERNEL);
ed754e5d
CH		 3512 if (!head)
3513 goto out;
8b850475 3514 ret = ida_alloc_min(&ctrl->subsys->ns_ida, 1, GFP_KERNEL);
ed754e5d
CH		 3515 if (ret < 0)
3516 goto out_free_head;
3517 head->instance = ret;
3518 INIT_LIST_HEAD(&head->list);
fd92c77f
MG		 3519 ret = init_srcu_struct(&head->srcu);
3520 if (ret)
3521 goto out_ida_remove;
ed754e5d 3522 head->subsys = ctrl->subsys;
1a893c2b
CH		 3523 head->ns_id = info->nsid;
3524 head->ids = info->ids;
3525 head->shared = info->is_shared;
a1a825ab
DW		 3526 ratelimit_state_init(&head->rs_nuse, 5 * HZ, 1);
3527 ratelimit_set_flags(&head->rs_nuse, RATELIMIT_MSG_ON_RELEASE);
ed754e5d
CH		 3528 kref_init(&head->ref);
3529
be93e87e
KB		 3530 if (head->ids.csi) {
3531 ret = nvme_get_effects_log(ctrl, head->ids.csi, &head->effects);
3532 if (ret)
3533 goto out_cleanup_srcu;
3534 } else
3535 head->effects = ctrl->effects;
3536
32acab31
CH		 3537 ret = nvme_mpath_alloc_disk(ctrl, head);
3538 if (ret)
3539 goto out_cleanup_srcu;
3540
ed754e5d 3541 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
12d9f070
JW		 3542
3543 kref_get(&ctrl->subsys->ref);
3544
ed754e5d
CH		 3545 return head;
3546out_cleanup_srcu:
3547 cleanup_srcu_struct(&head->srcu);
fd92c77f 3548out_ida_remove:
8b850475 3549 ida_free(&ctrl->subsys->ns_ida, head->instance);
ed754e5d
CH		 3550out_free_head:
3551 kfree(head);
3552out:
538af88e
SG		 3553 if (ret > 0)
3554 ret = blk_status_to_errno(nvme_error_status(ret));
ed754e5d
CH		 3555 return ERR_PTR(ret);
3556}
3557
2079f41e
CH		 3558static int nvme_global_check_duplicate_ids(struct nvme_subsystem *this,
3559 struct nvme_ns_ids *ids)
3560{
3561 struct nvme_subsystem *s;
3562 int ret = 0;
3563
3564 /*
3565 * Note that this check is racy as we try to avoid holding the global
3566 * lock over the whole ns_head creation. But it is only intended as
3567 * a sanity check anyway.
3568 */
3569 mutex_lock(&nvme_subsystems_lock);
3570 list_for_each_entry(s, &nvme_subsystems, entry) {
3571 if (s == this)
3572 continue;
3573 mutex_lock(&s->lock);
3574 ret = nvme_subsys_check_duplicate_ids(s, ids);
3575 mutex_unlock(&s->lock);
3576 if (ret)
3577 break;
3578 }
3579 mutex_unlock(&nvme_subsystems_lock);
3580
3581 return ret;
3582}
3583
1a893c2b 3584static int nvme_init_ns_head(struct nvme_ns *ns, struct nvme_ns_info *info)
ed754e5d
CH		 3585{
3586 struct nvme_ctrl *ctrl = ns->ctrl;
ed754e5d 3587 struct nvme_ns_head *head = NULL;
2079f41e
CH		 3588 int ret;
3589
1a893c2b 3590 ret = nvme_global_check_duplicate_ids(ctrl->subsys, &info->ids);
2079f41e 3591 if (ret) {
ac522fc6
CH		 3592 /*
3593 * We've found two different namespaces on two different
3594 * subsystems that report the same ID. This is pretty nasty
3595 * for anything that actually requires unique device
3596 * identification. In the kernel we need this for multipathing,
3597 * and in user space the /dev/disk/by-id/ links rely on it.
3598 *
3599 * If the device also claims to be multi-path capable back off
3600 * here now and refuse the probe the second device as this is a
3601 * recipe for data corruption. If not this is probably a
3602 * cheap consumer device if on the PCIe bus, so let the user
3603 * proceed and use the shiny toy, but warn that with changing
3604 * probing order (which due to our async probing could just be
3605 * device taking longer to startup) the other device could show
3606 * up at any time.
3607 */
2f0dad17 3608 nvme_print_device_info(ctrl);
ac522fc6
CH		 3609 if ((ns->ctrl->ops->flags & NVME_F_FABRICS) || /* !PCIe */
3610 ((ns->ctrl->subsys->cmic & NVME_CTRL_CMIC_MULTI_CTRL) &&
3611 info->is_shared)) {
3612 dev_err(ctrl->device,
3613 "ignoring nsid %d because of duplicate IDs\n",
3614 info->nsid);
3615 return ret;
3616 }
3617
3618 dev_err(ctrl->device,
3619 "clearing duplicate IDs for nsid %d\n", info->nsid);
3620 dev_err(ctrl->device,
3621 "use of /dev/disk/by-id/ may cause data corruption\n");
3622 memset(&info->ids.nguid, 0, sizeof(info->ids.nguid));
3623 memset(&info->ids.uuid, 0, sizeof(info->ids.uuid));
3624 memset(&info->ids.eui64, 0, sizeof(info->ids.eui64));
3625 ctrl->quirks |= NVME_QUIRK_BOGUS_NID;
2079f41e 3626 }
ed754e5d
CH		 3627
3628 mutex_lock(&ctrl->subsys->lock);
1a893c2b 3629 head = nvme_find_ns_head(ctrl, info->nsid);
ed754e5d 3630 if (!head) {
1a893c2b 3631 ret = nvme_subsys_check_duplicate_ids(ctrl->subsys, &info->ids);
e2d77d2e
CH		 3632 if (ret) {
3633 dev_err(ctrl->device,
2079f41e 3634 "duplicate IDs in subsystem for nsid %d\n",
1a893c2b 3635 info->nsid);
e2d77d2e
CH		 3636 goto out_unlock;
3637 }
1a893c2b 3638 head = nvme_alloc_ns_head(ctrl, info);
ed754e5d
CH		 3639 if (IS_ERR(head)) {
3640 ret = PTR_ERR(head);
3641 goto out_unlock;
3642 }
ed754e5d 3643 } else {
6623c5b3 3644 ret = -EINVAL;
1a893c2b 3645 if (!info->is_shared || !head->shared) {
9ad1927a 3646 dev_err(ctrl->device,
1a893c2b
CH		 3647 "Duplicate unshared namespace %d\n",
3648 info->nsid);
6623c5b3 3649 goto out_put_ns_head;
9ad1927a 3650 }
1a893c2b 3651 if (!nvme_ns_ids_equal(&head->ids, &info->ids)) {
ed754e5d
CH		 3652 dev_err(ctrl->device,
3653 "IDs don't match for shared namespace %d\n",
1a893c2b 3654 info->nsid);
6623c5b3 3655 goto out_put_ns_head;
ed754e5d 3656 }
ce8d7861 3657
2110a6bc 3658 if (!multipath) {
ce8d7861
CH		 3659 dev_warn(ctrl->device,
3660 "Found shared namespace %d, but multipathing not supported.\n",
1a893c2b 3661 info->nsid);
ce8d7861 3662 dev_warn_once(ctrl->device,
0bc2e80b 3663 "Support for shared namespaces without CONFIG_NVME_MULTIPATH is deprecated and will be removed in Linux 6.0.\n");
ce8d7861 3664 }
ed754e5d
CH		 3665 }
3666
772ea326 3667 list_add_tail_rcu(&ns->siblings, &head->list);
ed754e5d 3668 ns->head = head;
6623c5b3
CH		 3669 mutex_unlock(&ctrl->subsys->lock);
3670 return 0;
ed754e5d 3671
6623c5b3
CH		 3672out_put_ns_head:
3673 nvme_put_ns_head(head);
ed754e5d
CH		 3674out_unlock:
3675 mutex_unlock(&ctrl->subsys->lock);
3676 return ret;
3677}
3678
24493b8b 3679struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 3680{
32f0c4af 3681 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 3682
765cc031 3683 down_read(&ctrl->namespaces_rwsem);
5bae7f73 3684 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 3685 if (ns->head->ns_id == nsid) {
4c74d1f8 3686 if (!nvme_get_ns(ns))
2dd41228 3687 continue;
32f0c4af
KB		 3688 ret = ns;
3689 break;
3690 }
ed754e5d 3691 if (ns->head->ns_id > nsid)
5bae7f73
CH		 3692 break;
3693 }
765cc031 3694 up_read(&ctrl->namespaces_rwsem);
32f0c4af 3695 return ret;
5bae7f73 3696}
24493b8b 3697EXPORT_SYMBOL_NS_GPL(nvme_find_get_ns, NVME_TARGET_PASSTHRU);
5bae7f73 3698
298ba0e3
CH		 3699/*
3700 * Add the namespace to the controller list while keeping the list ordered.
3701 */
3702static void nvme_ns_add_to_ctrl_list(struct nvme_ns *ns)
3703{
3704 struct nvme_ns *tmp;
3705
3706 list_for_each_entry_reverse(tmp, &ns->ctrl->namespaces, list) {
3707 if (tmp->head->ns_id < ns->head->ns_id) {
3708 list_add(&ns->list, &tmp->list);
3709 return;
3710 }
3711 }
3712 list_add(&ns->list, &ns->ctrl->namespaces);
3713}
3714
1a893c2b 3715static void nvme_alloc_ns(struct nvme_ctrl *ctrl, struct nvme_ns_info *info)
5bae7f73
CH		 3716{
3717 struct nvme_ns *ns;
3718 struct gendisk *disk;
9953ab0c 3719 int node = ctrl->numa_node;
5bae7f73
CH		 3720
3721 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
3722 if (!ns)
1a893c2b 3723 return;
5bae7f73 3724
27e32cd2 3725 disk = blk_mq_alloc_disk(ctrl->tagset, NULL, ns);
5f432cce 3726 if (IS_ERR(disk))
ed754e5d 3727 goto out_free_ns;
5f432cce
CH		 3728 disk->fops = &nvme_bdev_ops;
3729 disk->private_data = ns;
3730
3731 ns->disk = disk;
3732 ns->queue = disk->queue;
e0596ab2 3733
7d30c81b 3734 if (ctrl->opts && ctrl->opts->data_digest)
1cb039f3 3735 blk_queue_flag_set(QUEUE_FLAG_STABLE_WRITES, ns->queue);
958f2a0f 3736
8b904b5b 3737 blk_queue_flag_set(QUEUE_FLAG_NONROT, ns->queue);
2f859441
LG		 3738 if (ctrl->ops->supports_pci_p2pdma &&
3739 ctrl->ops->supports_pci_p2pdma(ctrl))
e0596ab2
LG		 3740 blk_queue_flag_set(QUEUE_FLAG_PCI_P2PDMA, ns->queue);
3741
5bae7f73 3742 ns->ctrl = ctrl;
5bae7f73 3743 kref_init(&ns->kref);
5bae7f73 3744
1a893c2b 3745 if (nvme_init_ns_head(ns, info))
5f432cce 3746 goto out_cleanup_disk;
ac81bfa9 3747
9953ab0c 3748 /*
b739e137
CH		 3749 * If multipathing is enabled, the device name for all disks and not
3750 * just those that represent shared namespaces needs to be based on the
3751 * subsystem instance. Using the controller instance for private
3752 * namespaces could lead to naming collisions between shared and private
3753 * namespaces if they don't use a common numbering scheme.
3754 *
3755 * If multipathing is not enabled, disk names must use the controller
3756 * instance as shared namespaces will show up as multiple block
3757 * devices.
9953ab0c 3758 */
35e797b0 3759 if (nvme_ns_head_multipath(ns->head)) {
b739e137
CH		 3760 sprintf(disk->disk_name, "nvme%dc%dn%d", ctrl->subsys->instance,
3761 ctrl->instance, ns->head->instance);
3762 disk->flags |= GENHD_FL_HIDDEN;
3763 } else if (multipath) {
3764 sprintf(disk->disk_name, "nvme%dn%d", ctrl->subsys->instance,
3765 ns->head->instance);
3766 } else {
9953ab0c
CH		 3767 sprintf(disk->disk_name, "nvme%dn%d", ctrl->instance,
3768 ns->head->instance);
b739e137 3769 }
3dc87dd0 3770
1a893c2b 3771 if (nvme_update_ns_info(ns, info))
5f432cce 3772 goto out_unlink_ns;
5bae7f73 3773
765cc031 3774 down_write(&ctrl->namespaces_rwsem);
839a40d1
BH		 3775 /*
3776 * Ensure that no namespaces are added to the ctrl list after the queues
3777 * are frozen, thereby avoiding a deadlock between scan and reset.
3778 */
3779 if (test_bit(NVME_CTRL_FROZEN, &ctrl->flags)) {
3780 up_write(&ctrl->namespaces_rwsem);
3781 goto out_unlink_ns;
3782 }
298ba0e3 3783 nvme_ns_add_to_ctrl_list(ns);
765cc031 3784 up_write(&ctrl->namespaces_rwsem);
d22524a4 3785 nvme_get_ctrl(ctrl);
ac81bfa9 3786
83ac678e 3787 if (device_add_disk(ctrl->device, ns->disk, nvme_ns_attr_groups))
ab3994f6
LC		 3788 goto out_cleanup_ns_from_list;
3789
2637baed
MI		 3790 if (!nvme_ns_head_multipath(ns->head))
3791 nvme_add_ns_cdev(ns);
32acab31 3792
1a893c2b 3793 nvme_mpath_add_disk(ns, info->anagrpid);
a3646451 3794 nvme_fault_inject_init(&ns->fault_inject, ns->disk->disk_name);
0d0b660f 3795
9f079dda
AA		 3796 /*
3797 * Set ns->disk->device->driver_data to ns so we can access
e8c263ed
CK		 3798 * ns->head->passthru_err_log_enabled in
3799 * nvme_io_passthru_err_log_enabled_[store | show]().
9f079dda
AA		 3800 */
3801 dev_set_drvdata(disk_to_dev(ns->disk), ns);
3802
adce7e98 3803 return;
5f432cce 3804
ab3994f6
LC		 3805 out_cleanup_ns_from_list:
3806 nvme_put_ctrl(ctrl);
3807 down_write(&ctrl->namespaces_rwsem);
3808 list_del_init(&ns->list);
3809 up_write(&ctrl->namespaces_rwsem);
ed754e5d
CH		 3810 out_unlink_ns:
3811 mutex_lock(&ctrl->subsys->lock);
3812 list_del_rcu(&ns->siblings);
d5675729
KB		 3813 if (list_empty(&ns->head->list))
3814 list_del_init(&ns->head->entry);
ed754e5d 3815 mutex_unlock(&ctrl->subsys->lock);
a63b8370 3816 nvme_put_ns_head(ns->head);
5f432cce 3817 out_cleanup_disk:
8b9ab626 3818 put_disk(disk);
5bae7f73
CH		 3819 out_free_ns:
3820 kfree(ns);
3821}
3822
3823static void nvme_ns_remove(struct nvme_ns *ns)
3824{
5396fdac
HR		 3825 bool last_path = false;
3826
646017a6
KB		 3827 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
3828 return;
69d3b8ac 3829
e7d65803 3830 clear_bit(NVME_NS_READY, &ns->flags);
0a05226a 3831 set_capacity(ns->disk, 0);
a3646451 3832 nvme_fault_inject_fini(&ns->fault_inject);
2181e455 3833
d6d67427
CL		 3834 /*
3835 * Ensure that !NVME_NS_READY is seen by other threads to prevent
3836 * this ns going back into current_path.
3837 */
3838 synchronize_srcu(&ns->head->srcu);
3839
3840 /* wait for concurrent submissions */
3841 if (nvme_mpath_clear_current_path(ns))
3842 synchronize_srcu(&ns->head->srcu);
3843
2181e455
AE		 3844 mutex_lock(&ns->ctrl->subsys->lock);
3845 list_del_rcu(&ns->siblings);
9edceaf4
DW		 3846 if (list_empty(&ns->head->list)) {
3847 list_del_init(&ns->head->entry);
3848 last_path = true;
3849 }
2181e455 3850 mutex_unlock(&ns->ctrl->subsys->lock);
d5675729 3851
041bd1a1 3852 /* guarantee not available in head->list */
899d2a05 3853 synchronize_srcu(&ns->head->srcu);
041bd1a1 3854
5eba2005
CH		 3855 if (!nvme_ns_head_multipath(ns->head))
3856 nvme_cdev_del(&ns->cdev, &ns->cdev_device);
3857 del_gendisk(ns->disk);
32f0c4af 3858
765cc031 3859 down_write(&ns->ctrl->namespaces_rwsem);
5bae7f73 3860 list_del_init(&ns->list);
765cc031 3861 up_write(&ns->ctrl->namespaces_rwsem);
32f0c4af 3862
5396fdac
HR		 3863 if (last_path)
3864 nvme_mpath_shutdown_disk(ns->head);
5bae7f73
CH		 3865 nvme_put_ns(ns);
3866}
3867
4450ba3b
CH		 3868static void nvme_ns_remove_by_nsid(struct nvme_ctrl *ctrl, u32 nsid)
3869{
3870 struct nvme_ns *ns = nvme_find_get_ns(ctrl, nsid);
3871
3872 if (ns) {
3873 nvme_ns_remove(ns);
3874 nvme_put_ns(ns);
3875 }
3876}
3877
1a893c2b 3878static void nvme_validate_ns(struct nvme_ns *ns, struct nvme_ns_info *info)
b2dc748a 3879{
d95c1f41 3880 int ret = NVME_SC_INVALID_NS | NVME_SC_DNR;
b2dc748a 3881
1a893c2b 3882 if (!nvme_ns_ids_equal(&ns->head->ids, &info->ids)) {
af5d6f7b 3883 dev_err(ns->ctrl->device,
b2dc748a 3884 "identifiers changed for nsid %d\n", ns->head->ns_id);
1a893c2b 3885 goto out;
b2dc748a
CH		 3886 }
3887
1a893c2b 3888 ret = nvme_update_ns_info(ns, info);
b2dc748a
CH		 3889out:
3890 /*
0a05226a 3891 * Only remove the namespace if we got a fatal error back from the
b2dc748a 3892 * device, otherwise ignore the error and just move on.
0a05226a
CH		 3893 *
3894 * TODO: we should probably schedule a delayed retry here.
b2dc748a 3895 */
d95c1f41 3896 if (ret > 0 && (ret & NVME_SC_DNR))
0a05226a 3897 nvme_ns_remove(ns);
b2dc748a
CH		 3898}
3899
04c170f6 3900static void nvme_scan_ns(struct nvme_ctrl *ctrl, unsigned nsid)
540c801c 3901{
1a893c2b 3902 struct nvme_ns_info info = { .nsid = nsid };
540c801c 3903 struct nvme_ns *ns;
0dd6fff2 3904 int ret;
540c801c 3905
1a893c2b 3906 if (nvme_identify_ns_descs(ctrl, &info))
8b7c0ff2 3907 return;
540c801c 3908
1a893c2b 3909 if (info.ids.csi != NVME_CSI_NVM && !nvme_multi_css(ctrl)) {
71882e7d
CH		 3910 dev_warn(ctrl->device,
3911 "command set not reported for nsid: %d\n", nsid);
3912 return;
3913 }
3914
354201c5 3915 /*
1a893c2b
CH		 3916 * If available try to use the Command Set Idependent Identify Namespace
3917 * data structure to find all the generic information that is needed to
3918 * set up a namespace. If not fall back to the legacy version.
354201c5 3919 */
eb867ee9 3920 if ((ctrl->cap & NVME_CAP_CRMS_CRIMS) ||
0dd6fff2
CH		 3921 (info.ids.csi != NVME_CSI_NVM && info.ids.csi != NVME_CSI_ZNS))
3922 ret = nvme_ns_info_from_id_cs_indep(ctrl, &info);
3923 else
3924 ret = nvme_ns_info_from_identify(ctrl, &info);
3925
3926 if (info.is_removed)
3927 nvme_ns_remove_by_nsid(ctrl, nsid);
354201c5 3928
1a893c2b
CH		 3929 /*
3930 * Ignore the namespace if it is not ready. We will get an AEN once it
3931 * becomes ready and restart the scan.
3932 */
0dd6fff2 3933 if (ret || !info.is_ready)
354201c5
CH		 3934 return;
3935
32f0c4af 3936 ns = nvme_find_get_ns(ctrl, nsid);
8b7c0ff2 3937 if (ns) {
1a893c2b 3938 nvme_validate_ns(ns, &info);
8b7c0ff2 3939 nvme_put_ns(ns);
1a893c2b
CH		 3940 } else {
3941 nvme_alloc_ns(ctrl, &info);
8b7c0ff2 3942 }
540c801c
KB		 3943}
3944
47b0e50a
SB		 3945static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3946 unsigned nsid)
3947{
3948 struct nvme_ns *ns, *next;
6f8e0d78 3949 LIST_HEAD(rm_list);
47b0e50a 3950
765cc031 3951 down_write(&ctrl->namespaces_rwsem);
47b0e50a 3952 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
4f17344e 3953 if (ns->head->ns_id > nsid)
6f8e0d78 3954 list_move_tail(&ns->list, &rm_list);
47b0e50a 3955 }
765cc031 3956 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 3957
3958 list_for_each_entry_safe(ns, next, &rm_list, list)
3959 nvme_ns_remove(ns);
3960
47b0e50a
SB		 3961}
3962
4005f28d 3963static int nvme_scan_ns_list(struct nvme_ctrl *ctrl)
540c801c 3964{
aec459b4 3965 const int nr_entries = NVME_IDENTIFY_DATA_SIZE / sizeof(__le32);
540c801c 3966 __le32 *ns_list;
4005f28d
CH		 3967 u32 prev = 0;
3968 int ret = 0, i;
540c801c 3969
42595eb7 3970 ns_list = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
540c801c
KB		 3971 if (!ns_list)
3972 return -ENOMEM;
3973
4005f28d 3974 for (;;) {
7b153362
CH		 3975 struct nvme_command cmd = {
3976 .identify.opcode = nvme_admin_identify,
3977 .identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST,
3978 .identify.nsid = cpu_to_le32(prev),
3979 };
3980
3981 ret = nvme_submit_sync_cmd(ctrl->admin_q, &cmd, ns_list,
3982 NVME_IDENTIFY_DATA_SIZE);
f781f3dd
MI		 3983 if (ret) {
3984 dev_warn(ctrl->device,
3985 "Identify NS List failed (status=0x%x)\n", ret);
47b0e50a 3986 goto free;
f781f3dd 3987 }
540c801c 3988
aec459b4 3989 for (i = 0; i < nr_entries; i++) {
4005f28d 3990 u32 nsid = le32_to_cpu(ns_list[i]);
540c801c 3991
4005f28d
CH		 3992 if (!nsid) /* end of the list? */
3993 goto out;
04c170f6 3994 nvme_scan_ns(ctrl, nsid);
4450ba3b
CH		 3995 while (++prev < nsid)
3996 nvme_ns_remove_by_nsid(ctrl, prev);
540c801c 3997 }
540c801c
KB		 3998 }
3999 out:
47b0e50a
SB		 4000 nvme_remove_invalid_namespaces(ctrl, prev);
4001 free:
540c801c
KB		 4002 kfree(ns_list);
4003 return ret;
4004}
4005
4005f28d 4006static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl)
5bae7f73 4007{
4005f28d
CH		 4008 struct nvme_id_ctrl *id;
4009 u32 nn, i;
4010
4011 if (nvme_identify_ctrl(ctrl, &id))
4012 return;
4013 nn = le32_to_cpu(id->nn);
4014 kfree(id);
5bae7f73 4015
540c801c 4016 for (i = 1; i <= nn; i++)
04c170f6 4017 nvme_scan_ns(ctrl, i);
540c801c 4018
47b0e50a 4019 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 4020}
4021
f493af37 4022static void nvme_clear_changed_ns_log(struct nvme_ctrl *ctrl)
30d90964
CH		 4023{
4024 size_t log_size = NVME_MAX_CHANGED_NAMESPACES * sizeof(__le32);
4025 __le32 *log;
f493af37 4026 int error;
30d90964
CH		 4027
4028 log = kzalloc(log_size, GFP_KERNEL);
4029 if (!log)
f493af37 4030 return;
30d90964 4031
f493af37
CH		 4032 /*
4033 * We need to read the log to clear the AEN, but we don't want to rely
4034 * on it for the changed namespace information as userspace could have
4035 * raced with us in reading the log page, which could cause us to miss
4036 * updates.
4037 */
be93e87e
KB		 4038 error = nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_CHANGED_NS, 0,
4039 NVME_CSI_NVM, log, log_size, 0);
f493af37 4040 if (error)
30d90964
CH		 4041 dev_warn(ctrl->device,
4042 "reading changed ns log failed: %d\n", error);
30d90964 4043
30d90964 4044 kfree(log);
30d90964
CH		 4045}
4046
5955be21 4047static void nvme_scan_work(struct work_struct *work)
5bae7f73 4048{
5955be21
CH		 4049 struct nvme_ctrl *ctrl =
4050 container_of(work, struct nvme_ctrl, scan_work);
78288665 4051 int ret;
5bae7f73 4052
5d02a5c1 4053 /* No tagset on a live ctrl means IO queues could not created */
e6e7f7ac 4054 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE || !ctrl->tagset)
5955be21
CH		 4055 return;
4056
78288665
CK		 4057 /*
4058 * Identify controller limits can change at controller reset due to
4059 * new firmware download, even though it is not common we cannot ignore
4060 * such scenario. Controller's non-mdts limits are reported in the unit
4061 * of logical blocks that is dependent on the format of attached
4062 * namespace. Hence re-read the limits at the time of ns allocation.
4063 */
4064 ret = nvme_init_non_mdts_limits(ctrl);
4065 if (ret < 0) {
4066 dev_warn(ctrl->device,
4067 "reading non-mdts-limits failed: %d\n", ret);
4068 return;
4069 }
4070
77016199 4071 if (test_and_clear_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events)) {
30d90964 4072 dev_info(ctrl->device, "rescanning namespaces.\n");
f493af37 4073 nvme_clear_changed_ns_log(ctrl);
30d90964
CH		 4074 }
4075
e7ad43c3 4076 mutex_lock(&ctrl->scan_lock);
811f4de0 4077 if (nvme_ctrl_limited_cns(ctrl)) {
4005f28d 4078 nvme_scan_ns_sequential(ctrl);
811f4de0
US		 4079 } else {
4080 /*
4081 * Fall back to sequential scan if DNR is set to handle broken
4082 * devices which should support Identify NS List (as per the VS
4083 * they report) but don't actually support it.
4084 */
4085 ret = nvme_scan_ns_list(ctrl);
4086 if (ret > 0 && ret & NVME_SC_DNR)
4087 nvme_scan_ns_sequential(ctrl);
4088 }
e7ad43c3 4089 mutex_unlock(&ctrl->scan_lock);
5955be21 4090}
5bae7f73 4091
32f0c4af
KB		 4092/*
4093 * This function iterates the namespace list unlocked to allow recovery from
4094 * controller failure. It is up to the caller to ensure the namespace list is
4095 * not modified by scan work while this function is executing.
4096 */
5bae7f73
CH		 4097void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
4098{
4099 struct nvme_ns *ns, *next;
6f8e0d78 4100 LIST_HEAD(ns_list);
5bae7f73 4101
0157ec8d
SG		 4102 /*
4103 * make sure to requeue I/O to all namespaces as these
4104 * might result from the scan itself and must complete
4105 * for the scan_work to make progress
4106 */
4107 nvme_mpath_clear_ctrl_paths(ctrl);
4108
1b95e817
ML		 4109 /*
4110 * Unquiesce io queues so any pending IO won't hang, especially
4111 * those submitted from scan work
4112 */
4113 nvme_unquiesce_io_queues(ctrl);
4114
f6c8e432
SG		 4115 /* prevent racing with ns scanning */
4116 flush_work(&ctrl->scan_work);
4117
0ff9d4e1
KB		 4118 /*
4119 * The dead states indicates the controller was not gracefully
4120 * disconnected. In that case, we won't be able to flush any data while
4121 * removing the namespaces' disks; fail all the queues now to avoid
4122 * potentially having to clean up the failed sync later.
4123 */
e6e7f7ac 4124 if (nvme_ctrl_state(ctrl) == NVME_CTRL_DEAD)
cd50f9b2 4125 nvme_mark_namespaces_dead(ctrl);
0ff9d4e1 4126
ecca390e
SG		 4127 /* this is a no-op when called from the controller reset handler */
4128 nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING_NOIO);
4129
765cc031 4130 down_write(&ctrl->namespaces_rwsem);
6f8e0d78 4131 list_splice_init(&ctrl->namespaces, &ns_list);
765cc031 4132 up_write(&ctrl->namespaces_rwsem);
6f8e0d78
JW		 4133
4134 list_for_each_entry_safe(ns, next, &ns_list, list)
5bae7f73
CH		 4135 nvme_ns_remove(ns);
4136}
576d55d6 4137EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 4138
23680f0b 4139static int nvme_class_uevent(const struct device *dev, struct kobj_uevent_env *env)
a42f42e5 4140{
23680f0b 4141 const struct nvme_ctrl *ctrl =
a42f42e5
SG		 4142 container_of(dev, struct nvme_ctrl, ctrl_device);
4143 struct nvmf_ctrl_options *opts = ctrl->opts;
4144 int ret;
4145
4146 ret = add_uevent_var(env, "NVME_TRTYPE=%s", ctrl->ops->name);
4147 if (ret)
4148 return ret;
4149
4150 if (opts) {
4151 ret = add_uevent_var(env, "NVME_TRADDR=%s", opts->traddr);
4152 if (ret)
4153 return ret;
4154
4155 ret = add_uevent_var(env, "NVME_TRSVCID=%s",
4156 opts->trsvcid ?: "none");
4157 if (ret)
4158 return ret;
4159
4160 ret = add_uevent_var(env, "NVME_HOST_TRADDR=%s",
4161 opts->host_traddr ?: "none");
3ede8f72
MB		 4162 if (ret)
4163 return ret;
4164
4165 ret = add_uevent_var(env, "NVME_HOST_IFACE=%s",
4166 opts->host_iface ?: "none");
a42f42e5
SG		 4167 }
4168 return ret;
4169}
4170
20d64911
MB		 4171static void nvme_change_uevent(struct nvme_ctrl *ctrl, char *envdata)
4172{
4173 char *envp[2] = { envdata, NULL };
4174
4175 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4176}
4177
e3d7874d
KB		 4178static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
4179{
4180 char *envp[2] = { NULL, NULL };
4181 u32 aen_result = ctrl->aen_result;
4182
4183 ctrl->aen_result = 0;
4184 if (!aen_result)
4185 return;
4186
4187 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
4188 if (!envp[0])
4189 return;
4190 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
4191 kfree(envp[0]);
4192}
4193
f866fc42
CH		 4194static void nvme_async_event_work(struct work_struct *work)
4195{
4196 struct nvme_ctrl *ctrl =
4197 container_of(work, struct nvme_ctrl, async_event_work);
4198
e3d7874d 4199 nvme_aen_uevent(ctrl);
0fa0f99f
SG		 4200
4201 /*
4202 * The transport drivers must guarantee AER submission here is safe by
4203 * flushing ctrl async_event_work after changing the controller state
4204 * from LIVE and before freeing the admin queue.
4205 */
e6e7f7ac 4206 if (nvme_ctrl_state(ctrl) == NVME_CTRL_LIVE)
0fa0f99f 4207 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 4208}
4209
b6dccf7f
AD		 4210static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
4211{
4212
4213 u32 csts;
4214
4215 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
4216 return false;
4217
4218 if (csts == ~0)
4219 return false;
4220
4221 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
4222}
4223
4224static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
4225{
b6dccf7f 4226 struct nvme_fw_slot_info_log *log;
f0377ff9 4227 u8 next_fw_slot, cur_fw_slot;
b6dccf7f
AD		 4228
4229 log = kmalloc(sizeof(*log), GFP_KERNEL);
4230 if (!log)
4231 return;
4232
be93e87e 4233 if (nvme_get_log(ctrl, NVME_NSID_ALL, NVME_LOG_FW_SLOT, 0, NVME_CSI_NVM,
983a338b 4234 log, sizeof(*log), 0)) {
0e98719b 4235 dev_warn(ctrl->device, "Get FW SLOT INFO log error\n");
983a338b
DW		 4236 goto out_free_log;
4237 }
4238
f0377ff9
ML		 4239 cur_fw_slot = log->afi & 0x7;
4240 next_fw_slot = (log->afi & 0x70) >> 4;
4241 if (!cur_fw_slot || (next_fw_slot && (cur_fw_slot != next_fw_slot))) {
983a338b
DW		 4242 dev_info(ctrl->device,
4243 "Firmware is activated after next Controller Level Reset\n");
4244 goto out_free_log;
4245 }
4246
f0377ff9 4247 memcpy(ctrl->subsys->firmware_rev, &log->frs[cur_fw_slot - 1],
983a338b
DW		 4248 sizeof(ctrl->subsys->firmware_rev));
4249
4250out_free_log:
b6dccf7f
AD		 4251 kfree(log);
4252}
4253
4254static void nvme_fw_act_work(struct work_struct *work)
4255{
4256 struct nvme_ctrl *ctrl = container_of(work,
4257 struct nvme_ctrl, fw_act_work);
4258 unsigned long fw_act_timeout;
4259
f6fe0b2d
ML		 4260 nvme_auth_stop(ctrl);
4261
b6dccf7f
AD		 4262 if (ctrl->mtfa)
4263 fw_act_timeout = jiffies +
4264 msecs_to_jiffies(ctrl->mtfa * 100);
4265 else
4266 fw_act_timeout = jiffies +
4267 msecs_to_jiffies(admin_timeout * 1000);
4268
9f27bd70 4269 nvme_quiesce_io_queues(ctrl);
b6dccf7f
AD		 4270 while (nvme_ctrl_pp_status(ctrl)) {
4271 if (time_after(jiffies, fw_act_timeout)) {
4272 dev_warn(ctrl->device,
4273 "Fw activation timeout, reset controller\n");
4c75f877
KB		 4274 nvme_try_sched_reset(ctrl);
4275 return;
b6dccf7f
AD		 4276 }
4277 msleep(100);
4278 }
4279
4c75f877 4280 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE))
b6dccf7f
AD		 4281 return;
4282
9f27bd70 4283 nvme_unquiesce_io_queues(ctrl);
a806c6c8 4284 /* read FW slot information to clear the AER */
b6dccf7f 4285 nvme_get_fw_slot_info(ctrl);
371a982c
KB		 4286
4287 queue_work(nvme_wq, &ctrl->async_event_work);
b6dccf7f
AD		 4288}
4289
2c61c97f
MK		 4290static u32 nvme_aer_type(u32 result)
4291{
4292 return result & 0x7;
4293}
4294
4295static u32 nvme_aer_subtype(u32 result)
4296{
4297 return (result & 0xff00) >> 8;
4298}
4299
371a982c 4300static bool nvme_handle_aen_notice(struct nvme_ctrl *ctrl, u32 result)
868c2392 4301{
2c61c97f 4302 u32 aer_notice_type = nvme_aer_subtype(result);
371a982c 4303 bool requeue = true;
09bd1ff4
CK		 4304
4305 switch (aer_notice_type) {
868c2392 4306 case NVME_AER_NOTICE_NS_CHANGED:
77016199 4307 set_bit(NVME_AER_NOTICE_NS_CHANGED, &ctrl->events);
868c2392
CH		 4308 nvme_queue_scan(ctrl);
4309 break;
4310 case NVME_AER_NOTICE_FW_ACT_STARTING:
4c75f877
KB		 4311 /*
4312 * We are (ab)using the RESETTING state to prevent subsequent
4313 * recovery actions from interfering with the controller's
4314 * firmware activation.
4315 */
f50fff73 4316 if (nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) {
371a982c 4317 requeue = false;
4c75f877 4318 queue_work(nvme_wq, &ctrl->fw_act_work);
f50fff73 4319 }
868c2392 4320 break;
0d0b660f
CH		 4321#ifdef CONFIG_NVME_MULTIPATH
4322 case NVME_AER_NOTICE_ANA:
4323 if (!ctrl->ana_log_buf)
4324 break;
4325 queue_work(nvme_wq, &ctrl->ana_work);
4326 break;
4327#endif
85f8a435
SG		 4328 case NVME_AER_NOTICE_DISC_CHANGED:
4329 ctrl->aen_result = result;
4330 break;
868c2392
CH		 4331 default:
4332 dev_warn(ctrl->device, "async event result %08x\n", result);
4333 }
371a982c 4334 return requeue;
868c2392
CH		 4335}
4336
2c61c97f
MK		 4337static void nvme_handle_aer_persistent_error(struct nvme_ctrl *ctrl)
4338{
2c61c97f
MK		 4339 dev_warn(ctrl->device, "resetting controller due to AER\n");
4340 nvme_reset_ctrl(ctrl);
4341}
4342
7bf58533 4343void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
287a63eb 4344 volatile union nvme_result *res)
f866fc42 4345{
7bf58533 4346 u32 result = le32_to_cpu(res->u32);
2c61c97f
MK		 4347 u32 aer_type = nvme_aer_type(result);
4348 u32 aer_subtype = nvme_aer_subtype(result);
371a982c 4349 bool requeue = true;
f866fc42 4350
ad22c355 4351 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 4352 return;
4353
6622b76f 4354 trace_nvme_async_event(ctrl, result);
09bd1ff4 4355 switch (aer_type) {
868c2392 4356 case NVME_AER_NOTICE:
371a982c 4357 requeue = nvme_handle_aen_notice(ctrl, result);
868c2392 4358 break;
e3d7874d 4359 case NVME_AER_ERROR:
2c61c97f
MK		 4360 /*
4361 * For a persistent internal error, don't run async_event_work
4362 * to submit a new AER. The controller reset will do it.
4363 */
4364 if (aer_subtype == NVME_AER_ERROR_PERSIST_INT_ERR) {
4365 nvme_handle_aer_persistent_error(ctrl);
4366 return;
4367 }
4368 fallthrough;
e3d7874d
KB		 4369 case NVME_AER_SMART:
4370 case NVME_AER_CSS:
4371 case NVME_AER_VS:
4372 ctrl->aen_result = result;
7bf58533
CH		 4373 break;
4374 default:
4375 break;
f866fc42 4376 }
371a982c
KB		 4377
4378 if (requeue)
4379 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 4380}
f866fc42 4381EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 4382
fe60e8c5 4383int nvme_alloc_admin_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
db45e1a5 4384 const struct blk_mq_ops *ops, unsigned int cmd_size)
fe60e8c5 4385{
e6c9b130 4386 struct queue_limits lim = {};
fe60e8c5
CH		 4387 int ret;
4388
4389 memset(set, 0, sizeof(*set));
4390 set->ops = ops;
4391 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH;
4392 if (ctrl->ops->flags & NVME_F_FABRICS)
de105068
CX		 4393 /* Reserved for fabric connect and keep alive */
4394 set->reserved_tags = 2;
fe60e8c5 4395 set->numa_node = ctrl->numa_node;
db45e1a5
CH		 4396 set->flags = BLK_MQ_F_NO_SCHED;
4397 if (ctrl->ops->flags & NVME_F_BLOCKING)
4398 set->flags |= BLK_MQ_F_BLOCKING;
fe60e8c5
CH		 4399 set->cmd_size = cmd_size;
4400 set->driver_data = ctrl;
4401 set->nr_hw_queues = 1;
4402 set->timeout = NVME_ADMIN_TIMEOUT;
4403 ret = blk_mq_alloc_tag_set(set);
4404 if (ret)
4405 return ret;
4406
e6c9b130 4407 ctrl->admin_q = blk_mq_alloc_queue(set, &lim, NULL);
fe60e8c5
CH		 4408 if (IS_ERR(ctrl->admin_q)) {
4409 ret = PTR_ERR(ctrl->admin_q);
4410 goto out_free_tagset;
4411 }
4412
4413 if (ctrl->ops->flags & NVME_F_FABRICS) {
9ac4dd8c 4414 ctrl->fabrics_q = blk_mq_alloc_queue(set, NULL, NULL);
fe60e8c5
CH		 4415 if (IS_ERR(ctrl->fabrics_q)) {
4416 ret = PTR_ERR(ctrl->fabrics_q);
4417 goto out_cleanup_admin_q;
4418 }
4419 }
4420
4421 ctrl->admin_tagset = set;
4422 return 0;
4423
4424out_cleanup_admin_q:
4739824e 4425 blk_mq_destroy_queue(ctrl->admin_q);
2b3f056f 4426 blk_put_queue(ctrl->admin_q);
fe60e8c5 4427out_free_tagset:
fd62678a
ML		 4428 blk_mq_free_tag_set(set);
4429 ctrl->admin_q = NULL;
4430 ctrl->fabrics_q = NULL;
fe60e8c5
CH		 4431 return ret;
4432}
4433EXPORT_SYMBOL_GPL(nvme_alloc_admin_tag_set);
4434
4435void nvme_remove_admin_tag_set(struct nvme_ctrl *ctrl)
4436{
4437 blk_mq_destroy_queue(ctrl->admin_q);
2b3f056f
CH		 4438 blk_put_queue(ctrl->admin_q);
4439 if (ctrl->ops->flags & NVME_F_FABRICS) {
fe60e8c5 4440 blk_mq_destroy_queue(ctrl->fabrics_q);
2b3f056f
CH		 4441 blk_put_queue(ctrl->fabrics_q);
4442 }
fe60e8c5
CH		 4443 blk_mq_free_tag_set(ctrl->admin_tagset);
4444}
4445EXPORT_SYMBOL_GPL(nvme_remove_admin_tag_set);
4446
4447int nvme_alloc_io_tag_set(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set,
db45e1a5 4448 const struct blk_mq_ops *ops, unsigned int nr_maps,
fe60e8c5
CH		 4449 unsigned int cmd_size)
4450{
4451 int ret;
4452
4453 memset(set, 0, sizeof(*set));
4454 set->ops = ops;
33b93727 4455 set->queue_depth = min_t(unsigned, ctrl->sqsize, BLK_MQ_MAX_DEPTH - 1);
93b24f57
CH		 4456 /*
4457 * Some Apple controllers requires tags to be unique across admin and
4458 * the (only) I/O queue, so reserve the first 32 tags of the I/O queue.
4459 */
4460 if (ctrl->quirks & NVME_QUIRK_SHARED_TAGS)
4461 set->reserved_tags = NVME_AQ_DEPTH;
4462 else if (ctrl->ops->flags & NVME_F_FABRICS)
de105068
CX		 4463 /* Reserved for fabric connect */
4464 set->reserved_tags = 1;
fe60e8c5 4465 set->numa_node = ctrl->numa_node;
db45e1a5
CH		 4466 set->flags = BLK_MQ_F_SHOULD_MERGE;
4467 if (ctrl->ops->flags & NVME_F_BLOCKING)
4468 set->flags |= BLK_MQ_F_BLOCKING;
fe60e8c5
CH		 4469 set->cmd_size = cmd_size,
4470 set->driver_data = ctrl;
4471 set->nr_hw_queues = ctrl->queue_count - 1;
4472 set->timeout = NVME_IO_TIMEOUT;
dcef7727 4473 set->nr_maps = nr_maps;
fe60e8c5
CH		 4474 ret = blk_mq_alloc_tag_set(set);
4475 if (ret)
4476 return ret;
4477
4478 if (ctrl->ops->flags & NVME_F_FABRICS) {
9ac4dd8c 4479 ctrl->connect_q = blk_mq_alloc_queue(set, NULL, NULL);
fe60e8c5
CH		 4480 if (IS_ERR(ctrl->connect_q)) {
4481 ret = PTR_ERR(ctrl->connect_q);
4482 goto out_free_tag_set;
4483 }
98d81f0d
CL		 4484 blk_queue_flag_set(QUEUE_FLAG_SKIP_TAGSET_QUIESCE,
4485 ctrl->connect_q);
fe60e8c5
CH		 4486 }
4487
4488 ctrl->tagset = set;
4489 return 0;
4490
4491out_free_tag_set:
4492 blk_mq_free_tag_set(set);
6fbf13c0 4493 ctrl->connect_q = NULL;
fe60e8c5
CH		 4494 return ret;
4495}
4496EXPORT_SYMBOL_GPL(nvme_alloc_io_tag_set);
4497
4498void nvme_remove_io_tag_set(struct nvme_ctrl *ctrl)
4499{
2b3f056f 4500 if (ctrl->ops->flags & NVME_F_FABRICS) {
fe60e8c5 4501 blk_mq_destroy_queue(ctrl->connect_q);
2b3f056f
CH		 4502 blk_put_queue(ctrl->connect_q);
4503 }
fe60e8c5
CH		 4504 blk_mq_free_tag_set(ctrl->tagset);
4505}
4506EXPORT_SYMBOL_GPL(nvme_remove_io_tag_set);
4507
d09f2b45 4508void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 4509{
0d0b660f 4510 nvme_mpath_stop(ctrl);
f50fff73 4511 nvme_auth_stop(ctrl);
3af755a4 4512 nvme_stop_keep_alive(ctrl);
8c4dfea9 4513 nvme_stop_failfast_work(ctrl);
f866fc42 4514 flush_work(&ctrl->async_event_work);
b6dccf7f 4515 cancel_work_sync(&ctrl->fw_act_work);
f7f70f4a
RL		 4516 if (ctrl->ops->stop_ctrl)
4517 ctrl->ops->stop_ctrl(ctrl);
d09f2b45
SG		 4518}
4519EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
4520
4521void nvme_start_ctrl(struct nvme_ctrl *ctrl)
4522{
93da4023
SG		 4523 nvme_enable_aen(ctrl);
4524
f46ef9e8
SG		 4525 /*
4526 * persistent discovery controllers need to send indication to userspace
4527 * to re-read the discovery log page to learn about possible changes
4528 * that were missed. We identify persistent discovery controllers by
4529 * checking that they started once before, hence are reconnecting back.
4530 */
2eb94dd5 4531 if (test_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags) &&
f46ef9e8
SG		 4532 nvme_discovery_ctrl(ctrl))
4533 nvme_change_uevent(ctrl, "NVME_EVENT=rediscover");
4534
d09f2b45
SG		 4535 if (ctrl->queue_count > 1) {
4536 nvme_queue_scan(ctrl);
9f27bd70 4537 nvme_unquiesce_io_queues(ctrl);
a4a6f3c8 4538 nvme_mpath_update(ctrl);
d09f2b45 4539 }
20d64911
MB		 4540
4541 nvme_change_uevent(ctrl, "NVME_EVENT=connected");
2eb94dd5 4542 set_bit(NVME_CTRL_STARTED_ONCE, &ctrl->flags);
d09f2b45
SG		 4543}
4544EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 4545
d09f2b45
SG		 4546void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
4547{
ed7770f6 4548 nvme_hwmon_exit(ctrl);
f79d5fda 4549 nvme_fault_inject_fini(&ctrl->fault_inject);
510a405d 4550 dev_pm_qos_hide_latency_tolerance(ctrl->device);
a6a5149b 4551 cdev_device_del(&ctrl->cdev, ctrl->device);
726612b6 4552 nvme_put_ctrl(ctrl);
53029b04 4553}
576d55d6 4554EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 4555
8168d23f
KB		 4556static void nvme_free_cels(struct nvme_ctrl *ctrl)
4557{
4558 struct nvme_effects_log *cel;
4559 unsigned long i;
4560
8f8ea928 4561 xa_for_each(&ctrl->cels, i, cel) {
8168d23f
KB		 4562 xa_erase(&ctrl->cels, i);
4563 kfree(cel);
4564 }
4565
4566 xa_destroy(&ctrl->cels);
4567}
4568
d22524a4 4569static void nvme_free_ctrl(struct device *dev)
53029b04 4570{
d22524a4
CH		 4571 struct nvme_ctrl *ctrl =
4572 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 4573 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 4574
192f6c29 4575 if (!subsys || ctrl->instance != subsys->instance)
8b850475 4576 ida_free(&nvme_instance_ida, ctrl->instance);
be8e82ca 4577 key_put(ctrl->tls_key);
8168d23f 4578 nvme_free_cels(ctrl);
0d0b660f 4579 nvme_mpath_uninit(ctrl);
f50fff73
HR		 4580 nvme_auth_stop(ctrl);
4581 nvme_auth_free(ctrl);
092ff052 4582 __free_page(ctrl->discard_page);
94cc781f 4583 free_opal_dev(ctrl->opal_dev);
f3ca80fc 4584
ab9e00cc 4585 if (subsys) {
32fd90c4 4586 mutex_lock(&nvme_subsystems_lock);
ab9e00cc 4587 list_del(&ctrl->subsys_entry);
ab9e00cc 4588 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
32fd90c4 4589 mutex_unlock(&nvme_subsystems_lock);
ab9e00cc 4590 }
f3ca80fc
CH		 4591
4592 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 4593
ab9e00cc
CH		 4594 if (subsys)
4595 nvme_put_subsystem(subsys);
f3ca80fc
CH		 4596}
4597
4598/*
4599 * Initialize a NVMe controller structures. This needs to be called during
4600 * earliest initialization so that we have the initialized structured around
4601 * during probing.
4602 */
4603int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
4604 const struct nvme_ctrl_ops *ops, unsigned long quirks)
4605{
4606 int ret;
4607
e6e7f7ac 4608 WRITE_ONCE(ctrl->state, NVME_CTRL_NEW);
9f079dda 4609 ctrl->passthru_err_log_enabled = false;
8c4dfea9 4610 clear_bit(NVME_CTRL_FAILFAST_EXPIRED, &ctrl->flags);
bb8d261e 4611 spin_lock_init(&ctrl->lock);
e7ad43c3 4612 mutex_init(&ctrl->scan_lock);
f3ca80fc 4613 INIT_LIST_HEAD(&ctrl->namespaces);
1cf7a12e 4614 xa_init(&ctrl->cels);
765cc031 4615 init_rwsem(&ctrl->namespaces_rwsem);
f3ca80fc
CH		 4616 ctrl->dev = dev;
4617 ctrl->ops = ops;
4618 ctrl->quirks = quirks;
4fea243e 4619 ctrl->numa_node = NUMA_NO_NODE;
5955be21 4620 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 4621 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 4622 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 4623 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
c1ac9a4b 4624 init_waitqueue_head(&ctrl->state_wq);
f3ca80fc 4625
230f1f9e 4626 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
8c4dfea9 4627 INIT_DELAYED_WORK(&ctrl->failfast_work, nvme_failfast_work);
230f1f9e
JS		 4628 memset(&ctrl->ka_cmd, 0, sizeof(ctrl->ka_cmd));
4629 ctrl->ka_cmd.common.opcode = nvme_admin_keep_alive;
136cfcb8 4630 ctrl->ka_last_check_time = jiffies;
230f1f9e 4631
cb5b7262
JA		 4632 BUILD_BUG_ON(NVME_DSM_MAX_RANGES * sizeof(struct nvme_dsm_range) >
4633 PAGE_SIZE);
4634 ctrl->discard_page = alloc_page(GFP_KERNEL);
4635 if (!ctrl->discard_page) {
4636 ret = -ENOMEM;
4637 goto out;
4638 }
4639
8b850475 4640 ret = ida_alloc(&nvme_instance_ida, GFP_KERNEL);
9843f685 4641 if (ret < 0)
f3ca80fc 4642 goto out;
9843f685 4643 ctrl->instance = ret;
f3ca80fc 4644
d22524a4
CH		 4645 device_initialize(&ctrl->ctrl_device);
4646 ctrl->device = &ctrl->ctrl_device;
f68abd9c
JG		 4647 ctrl->device->devt = MKDEV(MAJOR(nvme_ctrl_base_chr_devt),
4648 ctrl->instance);
ab21f3d9 4649 ctrl->device->class = &nvme_class;
d22524a4 4650 ctrl->device->parent = ctrl->dev;
86adbf0c
CH		 4651 if (ops->dev_attr_groups)
4652 ctrl->device->groups = ops->dev_attr_groups;
4653 else
4654 ctrl->device->groups = nvme_dev_attr_groups;
d22524a4
CH		 4655 ctrl->device->release = nvme_free_ctrl;
4656 dev_set_drvdata(ctrl->device, ctrl);
4657 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
4658 if (ret)
f3ca80fc 4659 goto out_release_instance;
f3ca80fc 4660
b780d741 4661 nvme_get_ctrl(ctrl);
a6a5149b
CH		 4662 cdev_init(&ctrl->cdev, &nvme_dev_fops);
4663 ctrl->cdev.owner = ops->module;
4664 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 4665 if (ret)
4666 goto out_free_name;
f3ca80fc 4667
c5552fde
AL		 4668 /*
4669 * Initialize latency tolerance controls. The sysfs files won't
4670 * be visible to userspace unless the device actually supports APST.
4671 */
4672 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
4673 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
4674 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
4675
f79d5fda 4676 nvme_fault_inject_init(&ctrl->fault_inject, dev_name(ctrl->device));
5e1f6899 4677 nvme_mpath_init_ctrl(ctrl);
193a8c7e
SG		 4678 ret = nvme_auth_init_ctrl(ctrl);
4679 if (ret)
4680 goto out_free_cdev;
f79d5fda 4681
f3ca80fc 4682 return 0;
193a8c7e 4683out_free_cdev:
3a12a0b8 4684 nvme_fault_inject_fini(&ctrl->fault_inject);
7ed5cf8e 4685 dev_pm_qos_hide_latency_tolerance(ctrl->device);
193a8c7e 4686 cdev_device_del(&ctrl->cdev, ctrl->device);
d22524a4 4687out_free_name:
b780d741 4688 nvme_put_ctrl(ctrl);
d6a2b953 4689 kfree_const(ctrl->device->kobj.name);
f3ca80fc 4690out_release_instance:
8b850475 4691 ida_free(&nvme_instance_ida, ctrl->instance);
f3ca80fc 4692out:
cb5b7262
JA		 4693 if (ctrl->discard_page)
4694 __free_page(ctrl->discard_page);
f3ca80fc
CH		 4695 return ret;
4696}
576d55d6 4697EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 4698
cd50f9b2
CH		 4699/* let I/O to all namespaces fail in preparation for surprise removal */
4700void nvme_mark_namespaces_dead(struct nvme_ctrl *ctrl)
69d9a99c
KB		 4701{
4702 struct nvme_ns *ns;
4703
765cc031 4704 down_read(&ctrl->namespaces_rwsem);
cf39a6bc 4705 list_for_each_entry(ns, &ctrl->namespaces, list)
cd50f9b2 4706 blk_mark_disk_dead(ns->disk);
765cc031 4707 up_read(&ctrl->namespaces_rwsem);
69d9a99c 4708}
cd50f9b2 4709EXPORT_SYMBOL_GPL(nvme_mark_namespaces_dead);
69d9a99c 4710
302ad8cc
KB		 4711void nvme_unfreeze(struct nvme_ctrl *ctrl)
4712{
4713 struct nvme_ns *ns;
4714
765cc031 4715 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4716 list_for_each_entry(ns, &ctrl->namespaces, list)
4717 blk_mq_unfreeze_queue(ns->queue);
765cc031 4718 up_read(&ctrl->namespaces_rwsem);
839a40d1 4719 clear_bit(NVME_CTRL_FROZEN, &ctrl->flags);
302ad8cc
KB		 4720}
4721EXPORT_SYMBOL_GPL(nvme_unfreeze);
4722
7cf0d7c0 4723int nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
302ad8cc
KB		 4724{
4725 struct nvme_ns *ns;
4726
765cc031 4727 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4728 list_for_each_entry(ns, &ctrl->namespaces, list) {
4729 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
4730 if (timeout <= 0)
4731 break;
4732 }
765cc031 4733 up_read(&ctrl->namespaces_rwsem);
7cf0d7c0 4734 return timeout;
302ad8cc
KB		 4735}
4736EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
4737
4738void nvme_wait_freeze(struct nvme_ctrl *ctrl)
4739{
4740 struct nvme_ns *ns;
4741
765cc031 4742 down_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4743 list_for_each_entry(ns, &ctrl->namespaces, list)
4744 blk_mq_freeze_queue_wait(ns->queue);
765cc031 4745 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4746}
4747EXPORT_SYMBOL_GPL(nvme_wait_freeze);
4748
4749void nvme_start_freeze(struct nvme_ctrl *ctrl)
4750{
4751 struct nvme_ns *ns;
4752
839a40d1 4753 set_bit(NVME_CTRL_FROZEN, &ctrl->flags);
765cc031 4754 down_read(&ctrl->namespaces_rwsem);
302ad8cc 4755 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 4756 blk_freeze_queue_start(ns->queue);
765cc031 4757 up_read(&ctrl->namespaces_rwsem);
302ad8cc
KB		 4758}
4759EXPORT_SYMBOL_GPL(nvme_start_freeze);
4760
9f27bd70 4761void nvme_quiesce_io_queues(struct nvme_ctrl *ctrl)
363c9aac 4762{
ba0718a6
CH		 4763 if (!ctrl->tagset)
4764 return;
98d81f0d
CL		 4765 if (!test_and_set_bit(NVME_CTRL_STOPPED, &ctrl->flags))
4766 blk_mq_quiesce_tagset(ctrl->tagset);
4767 else
4768 blk_mq_wait_quiesce_done(ctrl->tagset);
363c9aac 4769}
9f27bd70 4770EXPORT_SYMBOL_GPL(nvme_quiesce_io_queues);
363c9aac 4771
9f27bd70 4772void nvme_unquiesce_io_queues(struct nvme_ctrl *ctrl)
363c9aac 4773{
ba0718a6
CH		 4774 if (!ctrl->tagset)
4775 return;
98d81f0d
CL		 4776 if (test_and_clear_bit(NVME_CTRL_STOPPED, &ctrl->flags))
4777 blk_mq_unquiesce_tagset(ctrl->tagset);
363c9aac 4778}
9f27bd70 4779EXPORT_SYMBOL_GPL(nvme_unquiesce_io_queues);
363c9aac 4780
9f27bd70 4781void nvme_quiesce_admin_queue(struct nvme_ctrl *ctrl)
a277654b 4782{
9e6a6b12
ML		 4783 if (!test_and_set_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags))
4784 blk_mq_quiesce_queue(ctrl->admin_q);
26af1cd0 4785 else
483239c7 4786 blk_mq_wait_quiesce_done(ctrl->admin_q->tag_set);
a277654b 4787}
9f27bd70 4788EXPORT_SYMBOL_GPL(nvme_quiesce_admin_queue);
a277654b 4789
9f27bd70 4790void nvme_unquiesce_admin_queue(struct nvme_ctrl *ctrl)
a277654b 4791{
9e6a6b12
ML		 4792 if (test_and_clear_bit(NVME_CTRL_ADMIN_Q_STOPPED, &ctrl->flags))
4793 blk_mq_unquiesce_queue(ctrl->admin_q);
a277654b 4794}
9f27bd70 4795EXPORT_SYMBOL_GPL(nvme_unquiesce_admin_queue);
a277654b 4796
04800fbf 4797void nvme_sync_io_queues(struct nvme_ctrl *ctrl)
d6135c3a
KB		 4798{
4799 struct nvme_ns *ns;
4800
4801 down_read(&ctrl->namespaces_rwsem);
4802 list_for_each_entry(ns, &ctrl->namespaces, list)
4803 blk_sync_queue(ns->queue);
4804 up_read(&ctrl->namespaces_rwsem);
04800fbf
CL		 4805}
4806EXPORT_SYMBOL_GPL(nvme_sync_io_queues);
03894b7a 4807
04800fbf
CL		 4808void nvme_sync_queues(struct nvme_ctrl *ctrl)
4809{
4810 nvme_sync_io_queues(ctrl);
03894b7a
EN		 4811 if (ctrl->admin_q)
4812 blk_sync_queue(ctrl->admin_q);
d6135c3a
KB		 4813}
4814EXPORT_SYMBOL_GPL(nvme_sync_queues);
4815
b2702aaa 4816struct nvme_ctrl *nvme_ctrl_from_file(struct file *file)
f783f444 4817{
b2702aaa
CK		 4818 if (file->f_op != &nvme_dev_fops)
4819 return NULL;
4820 return file->private_data;
f783f444 4821}
b2702aaa 4822EXPORT_SYMBOL_NS_GPL(nvme_ctrl_from_file, NVME_TARGET_PASSTHRU);
f783f444 4823
81101540
CH		 4824/*
4825 * Check we didn't inadvertently grow the command structure sizes:
4826 */
4827static inline void _nvme_check_size(void)
4828{
4829 BUILD_BUG_ON(sizeof(struct nvme_common_command) != 64);
4830 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
4831 BUILD_BUG_ON(sizeof(struct nvme_identify) != 64);
4832 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
4833 BUILD_BUG_ON(sizeof(struct nvme_download_firmware) != 64);
4834 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
4835 BUILD_BUG_ON(sizeof(struct nvme_dsm_cmd) != 64);
4836 BUILD_BUG_ON(sizeof(struct nvme_write_zeroes_cmd) != 64);
4837 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
4838 BUILD_BUG_ON(sizeof(struct nvme_get_log_page_command) != 64);
4839 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
4840 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
4841 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
354201c5
CH		 4842 BUILD_BUG_ON(sizeof(struct nvme_id_ns_cs_indep) !=
4843 NVME_IDENTIFY_DATA_SIZE);
240e6ee2 4844 BUILD_BUG_ON(sizeof(struct nvme_id_ns_zns) != NVME_IDENTIFY_DATA_SIZE);
4020aad8 4845 BUILD_BUG_ON(sizeof(struct nvme_id_ns_nvm) != NVME_IDENTIFY_DATA_SIZE);
240e6ee2 4846 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_zns) != NVME_IDENTIFY_DATA_SIZE);
5befc7c2 4847 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl_nvm) != NVME_IDENTIFY_DATA_SIZE);
81101540
CH		 4848 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
4849 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
4850 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
4851 BUILD_BUG_ON(sizeof(struct nvme_directive_cmd) != 64);
4020aad8 4852 BUILD_BUG_ON(sizeof(struct nvme_feat_host_behavior) != 512);
81101540
CH		 4853}
4854
4855
893a74b7 4856static int __init nvme_core_init(void)
5bae7f73 4857{
b227c59b 4858 int result = -ENOMEM;
5bae7f73 4859
81101540
CH		 4860 _nvme_check_size();
4861
9a6327d2
SG		 4862 nvme_wq = alloc_workqueue("nvme-wq",
4863 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4864 if (!nvme_wq)
b227c59b
RS		 4865 goto out;
4866
4867 nvme_reset_wq = alloc_workqueue("nvme-reset-wq",
4868 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4869 if (!nvme_reset_wq)
4870 goto destroy_wq;
4871
4872 nvme_delete_wq = alloc_workqueue("nvme-delete-wq",
4873 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
4874 if (!nvme_delete_wq)
4875 goto destroy_reset_wq;
9a6327d2 4876
f68abd9c
JG		 4877 result = alloc_chrdev_region(&nvme_ctrl_base_chr_devt, 0,
4878 NVME_MINORS, "nvme");
f3ca80fc 4879 if (result < 0)
b227c59b 4880 goto destroy_delete_wq;
f3ca80fc 4881
ab21f3d9
RM		 4882 result = class_register(&nvme_class);
4883 if (result)
f3ca80fc 4884 goto unregister_chrdev;
f3ca80fc 4885
ab21f3d9
RM		 4886 result = class_register(&nvme_subsys_class);
4887 if (result)
ab9e00cc 4888 goto destroy_class;
2637baed
MI		 4889
4890 result = alloc_chrdev_region(&nvme_ns_chr_devt, 0, NVME_MINORS,
4891 "nvme-generic");
4892 if (result < 0)
4893 goto destroy_subsys_class;
4894
ab21f3d9
RM		 4895 result = class_register(&nvme_ns_chr_class);
4896 if (result)
2637baed 4897 goto unregister_generic_ns;
ab21f3d9 4898
9d77eb52
HR		 4899 result = nvme_init_auth();
4900 if (result)
706add13 4901 goto destroy_ns_chr;
5bae7f73 4902 return 0;
f3ca80fc 4903
e481fc0a 4904destroy_ns_chr:
ab21f3d9 4905 class_unregister(&nvme_ns_chr_class);
2637baed
MI		 4906unregister_generic_ns:
4907 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
4908destroy_subsys_class:
ab21f3d9 4909 class_unregister(&nvme_subsys_class);
ab9e00cc 4910destroy_class:
ab21f3d9 4911 class_unregister(&nvme_class);
9a6327d2 4912unregister_chrdev:
f68abd9c 4913 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS		 4914destroy_delete_wq:
4915 destroy_workqueue(nvme_delete_wq);
4916destroy_reset_wq:
4917 destroy_workqueue(nvme_reset_wq);
9a6327d2
SG		 4918destroy_wq:
4919 destroy_workqueue(nvme_wq);
b227c59b 4920out:
f3ca80fc 4921 return result;
5bae7f73
CH		 4922}
4923
893a74b7 4924static void __exit nvme_core_exit(void)
5bae7f73 4925{
e481fc0a 4926 nvme_exit_auth();
ab21f3d9
RM		 4927 class_unregister(&nvme_ns_chr_class);
4928 class_unregister(&nvme_subsys_class);
4929 class_unregister(&nvme_class);
2637baed 4930 unregister_chrdev_region(nvme_ns_chr_devt, NVME_MINORS);
f68abd9c 4931 unregister_chrdev_region(nvme_ctrl_base_chr_devt, NVME_MINORS);
b227c59b
RS		 4932 destroy_workqueue(nvme_delete_wq);
4933 destroy_workqueue(nvme_reset_wq);
9a6327d2 4934 destroy_workqueue(nvme_wq);
2637baed 4935 ida_destroy(&nvme_ns_chr_minor_ida);
f41cfd5d 4936 ida_destroy(&nvme_instance_ida);
5bae7f73 4937}
576d55d6
ML		 4938
4939MODULE_LICENSE("GPL");
4940MODULE_VERSION("1.0");
92b0b0ff 4941MODULE_DESCRIPTION("NVMe host core framework");
576d55d6
ML		 4942module_init(nvme_core_init);
4943module_exit(nvme_core_exit);
Linux 6.x block layer and io_uring tree(s)