Commit | Line | Data |
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1f7df6f8 DW |
1 | /* |
2 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of version 2 of the GNU General Public License as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
eaf96153 | 13 | #include <linux/scatterlist.h> |
047fc8a1 | 14 | #include <linux/highmem.h> |
eaf96153 | 15 | #include <linux/sched.h> |
1f7df6f8 | 16 | #include <linux/slab.h> |
0c27af60 | 17 | #include <linux/hash.h> |
eaf96153 | 18 | #include <linux/sort.h> |
1f7df6f8 | 19 | #include <linux/io.h> |
bf9bccc1 | 20 | #include <linux/nd.h> |
1f7df6f8 DW |
21 | #include "nd-core.h" |
22 | #include "nd.h" | |
23 | ||
f284a4f2 DW |
24 | /* |
25 | * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is | |
26 | * irrelevant. | |
27 | */ | |
28 | #include <linux/io-64-nonatomic-hi-lo.h> | |
29 | ||
1f7df6f8 | 30 | static DEFINE_IDA(region_ida); |
0c27af60 | 31 | static DEFINE_PER_CPU(int, flush_idx); |
1f7df6f8 | 32 | |
e5ae3b25 DW |
33 | static int nvdimm_map_flush(struct device *dev, struct nvdimm *nvdimm, int dimm, |
34 | struct nd_region_data *ndrd) | |
35 | { | |
36 | int i, j; | |
37 | ||
38 | dev_dbg(dev, "%s: map %d flush address%s\n", nvdimm_name(nvdimm), | |
39 | nvdimm->num_flush, nvdimm->num_flush == 1 ? "" : "es"); | |
595c7307 | 40 | for (i = 0; i < (1 << ndrd->hints_shift); i++) { |
e5ae3b25 DW |
41 | struct resource *res = &nvdimm->flush_wpq[i]; |
42 | unsigned long pfn = PHYS_PFN(res->start); | |
43 | void __iomem *flush_page; | |
44 | ||
45 | /* check if flush hints share a page */ | |
46 | for (j = 0; j < i; j++) { | |
47 | struct resource *res_j = &nvdimm->flush_wpq[j]; | |
48 | unsigned long pfn_j = PHYS_PFN(res_j->start); | |
49 | ||
50 | if (pfn == pfn_j) | |
51 | break; | |
52 | } | |
53 | ||
54 | if (j < i) | |
55 | flush_page = (void __iomem *) ((unsigned long) | |
595c7307 DW |
56 | ndrd_get_flush_wpq(ndrd, dimm, j) |
57 | & PAGE_MASK); | |
e5ae3b25 DW |
58 | else |
59 | flush_page = devm_nvdimm_ioremap(dev, | |
480b6837 | 60 | PFN_PHYS(pfn), PAGE_SIZE); |
e5ae3b25 DW |
61 | if (!flush_page) |
62 | return -ENXIO; | |
595c7307 DW |
63 | ndrd_set_flush_wpq(ndrd, dimm, i, flush_page |
64 | + (res->start & ~PAGE_MASK)); | |
e5ae3b25 DW |
65 | } |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | int nd_region_activate(struct nd_region *nd_region) | |
71 | { | |
db58028e | 72 | int i, j, num_flush = 0; |
e5ae3b25 DW |
73 | struct nd_region_data *ndrd; |
74 | struct device *dev = &nd_region->dev; | |
75 | size_t flush_data_size = sizeof(void *); | |
76 | ||
77 | nvdimm_bus_lock(&nd_region->dev); | |
78 | for (i = 0; i < nd_region->ndr_mappings; i++) { | |
79 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
80 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
81 | ||
82 | /* at least one null hint slot per-dimm for the "no-hint" case */ | |
83 | flush_data_size += sizeof(void *); | |
0c27af60 | 84 | num_flush = min_not_zero(num_flush, nvdimm->num_flush); |
e5ae3b25 DW |
85 | if (!nvdimm->num_flush) |
86 | continue; | |
87 | flush_data_size += nvdimm->num_flush * sizeof(void *); | |
88 | } | |
89 | nvdimm_bus_unlock(&nd_region->dev); | |
90 | ||
91 | ndrd = devm_kzalloc(dev, sizeof(*ndrd) + flush_data_size, GFP_KERNEL); | |
92 | if (!ndrd) | |
93 | return -ENOMEM; | |
94 | dev_set_drvdata(dev, ndrd); | |
95 | ||
595c7307 DW |
96 | if (!num_flush) |
97 | return 0; | |
98 | ||
99 | ndrd->hints_shift = ilog2(num_flush); | |
e5ae3b25 DW |
100 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
101 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
102 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
103 | int rc = nvdimm_map_flush(&nd_region->dev, nvdimm, i, ndrd); | |
104 | ||
105 | if (rc) | |
106 | return rc; | |
107 | } | |
108 | ||
db58028e DJ |
109 | /* |
110 | * Clear out entries that are duplicates. This should prevent the | |
111 | * extra flushings. | |
112 | */ | |
113 | for (i = 0; i < nd_region->ndr_mappings - 1; i++) { | |
114 | /* ignore if NULL already */ | |
115 | if (!ndrd_get_flush_wpq(ndrd, i, 0)) | |
116 | continue; | |
117 | ||
118 | for (j = i + 1; j < nd_region->ndr_mappings; j++) | |
119 | if (ndrd_get_flush_wpq(ndrd, i, 0) == | |
120 | ndrd_get_flush_wpq(ndrd, j, 0)) | |
121 | ndrd_set_flush_wpq(ndrd, j, 0, NULL); | |
122 | } | |
123 | ||
e5ae3b25 DW |
124 | return 0; |
125 | } | |
126 | ||
1f7df6f8 DW |
127 | static void nd_region_release(struct device *dev) |
128 | { | |
129 | struct nd_region *nd_region = to_nd_region(dev); | |
130 | u16 i; | |
131 | ||
132 | for (i = 0; i < nd_region->ndr_mappings; i++) { | |
133 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
134 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
135 | ||
136 | put_device(&nvdimm->dev); | |
137 | } | |
5212e11f | 138 | free_percpu(nd_region->lane); |
1f7df6f8 | 139 | ida_simple_remove(®ion_ida, nd_region->id); |
047fc8a1 RZ |
140 | if (is_nd_blk(dev)) |
141 | kfree(to_nd_blk_region(dev)); | |
142 | else | |
143 | kfree(nd_region); | |
1f7df6f8 DW |
144 | } |
145 | ||
146 | static struct device_type nd_blk_device_type = { | |
147 | .name = "nd_blk", | |
148 | .release = nd_region_release, | |
149 | }; | |
150 | ||
151 | static struct device_type nd_pmem_device_type = { | |
152 | .name = "nd_pmem", | |
153 | .release = nd_region_release, | |
154 | }; | |
155 | ||
156 | static struct device_type nd_volatile_device_type = { | |
157 | .name = "nd_volatile", | |
158 | .release = nd_region_release, | |
159 | }; | |
160 | ||
3d88002e | 161 | bool is_nd_pmem(struct device *dev) |
1f7df6f8 DW |
162 | { |
163 | return dev ? dev->type == &nd_pmem_device_type : false; | |
164 | } | |
165 | ||
3d88002e DW |
166 | bool is_nd_blk(struct device *dev) |
167 | { | |
168 | return dev ? dev->type == &nd_blk_device_type : false; | |
169 | } | |
170 | ||
c9e582aa DW |
171 | bool is_nd_volatile(struct device *dev) |
172 | { | |
173 | return dev ? dev->type == &nd_volatile_device_type : false; | |
174 | } | |
175 | ||
1f7df6f8 DW |
176 | struct nd_region *to_nd_region(struct device *dev) |
177 | { | |
178 | struct nd_region *nd_region = container_of(dev, struct nd_region, dev); | |
179 | ||
180 | WARN_ON(dev->type->release != nd_region_release); | |
181 | return nd_region; | |
182 | } | |
183 | EXPORT_SYMBOL_GPL(to_nd_region); | |
184 | ||
047fc8a1 RZ |
185 | struct nd_blk_region *to_nd_blk_region(struct device *dev) |
186 | { | |
187 | struct nd_region *nd_region = to_nd_region(dev); | |
188 | ||
189 | WARN_ON(!is_nd_blk(dev)); | |
190 | return container_of(nd_region, struct nd_blk_region, nd_region); | |
191 | } | |
192 | EXPORT_SYMBOL_GPL(to_nd_blk_region); | |
193 | ||
194 | void *nd_region_provider_data(struct nd_region *nd_region) | |
195 | { | |
196 | return nd_region->provider_data; | |
197 | } | |
198 | EXPORT_SYMBOL_GPL(nd_region_provider_data); | |
199 | ||
200 | void *nd_blk_region_provider_data(struct nd_blk_region *ndbr) | |
201 | { | |
202 | return ndbr->blk_provider_data; | |
203 | } | |
204 | EXPORT_SYMBOL_GPL(nd_blk_region_provider_data); | |
205 | ||
206 | void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data) | |
207 | { | |
208 | ndbr->blk_provider_data = data; | |
209 | } | |
210 | EXPORT_SYMBOL_GPL(nd_blk_region_set_provider_data); | |
211 | ||
3d88002e DW |
212 | /** |
213 | * nd_region_to_nstype() - region to an integer namespace type | |
214 | * @nd_region: region-device to interrogate | |
215 | * | |
216 | * This is the 'nstype' attribute of a region as well, an input to the | |
217 | * MODALIAS for namespace devices, and bit number for a nvdimm_bus to match | |
218 | * namespace devices with namespace drivers. | |
219 | */ | |
220 | int nd_region_to_nstype(struct nd_region *nd_region) | |
221 | { | |
c9e582aa | 222 | if (is_memory(&nd_region->dev)) { |
3d88002e DW |
223 | u16 i, alias; |
224 | ||
225 | for (i = 0, alias = 0; i < nd_region->ndr_mappings; i++) { | |
226 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
227 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
228 | ||
8f078b38 | 229 | if (test_bit(NDD_ALIASING, &nvdimm->flags)) |
3d88002e DW |
230 | alias++; |
231 | } | |
232 | if (alias) | |
233 | return ND_DEVICE_NAMESPACE_PMEM; | |
234 | else | |
235 | return ND_DEVICE_NAMESPACE_IO; | |
236 | } else if (is_nd_blk(&nd_region->dev)) { | |
237 | return ND_DEVICE_NAMESPACE_BLK; | |
238 | } | |
239 | ||
240 | return 0; | |
241 | } | |
bf9bccc1 DW |
242 | EXPORT_SYMBOL(nd_region_to_nstype); |
243 | ||
1f7df6f8 DW |
244 | static ssize_t size_show(struct device *dev, |
245 | struct device_attribute *attr, char *buf) | |
246 | { | |
247 | struct nd_region *nd_region = to_nd_region(dev); | |
248 | unsigned long long size = 0; | |
249 | ||
c9e582aa | 250 | if (is_memory(dev)) { |
1f7df6f8 DW |
251 | size = nd_region->ndr_size; |
252 | } else if (nd_region->ndr_mappings == 1) { | |
253 | struct nd_mapping *nd_mapping = &nd_region->mapping[0]; | |
254 | ||
255 | size = nd_mapping->size; | |
256 | } | |
257 | ||
258 | return sprintf(buf, "%llu\n", size); | |
259 | } | |
260 | static DEVICE_ATTR_RO(size); | |
261 | ||
ab630891 DW |
262 | static ssize_t deep_flush_show(struct device *dev, |
263 | struct device_attribute *attr, char *buf) | |
264 | { | |
265 | struct nd_region *nd_region = to_nd_region(dev); | |
266 | ||
267 | /* | |
268 | * NOTE: in the nvdimm_has_flush() error case this attribute is | |
269 | * not visible. | |
270 | */ | |
271 | return sprintf(buf, "%d\n", nvdimm_has_flush(nd_region)); | |
272 | } | |
273 | ||
274 | static ssize_t deep_flush_store(struct device *dev, struct device_attribute *attr, | |
275 | const char *buf, size_t len) | |
276 | { | |
277 | bool flush; | |
278 | int rc = strtobool(buf, &flush); | |
279 | struct nd_region *nd_region = to_nd_region(dev); | |
280 | ||
281 | if (rc) | |
282 | return rc; | |
283 | if (!flush) | |
284 | return -EINVAL; | |
285 | nvdimm_flush(nd_region); | |
286 | ||
287 | return len; | |
288 | } | |
289 | static DEVICE_ATTR_RW(deep_flush); | |
290 | ||
1f7df6f8 DW |
291 | static ssize_t mappings_show(struct device *dev, |
292 | struct device_attribute *attr, char *buf) | |
293 | { | |
294 | struct nd_region *nd_region = to_nd_region(dev); | |
295 | ||
296 | return sprintf(buf, "%d\n", nd_region->ndr_mappings); | |
297 | } | |
298 | static DEVICE_ATTR_RO(mappings); | |
299 | ||
3d88002e DW |
300 | static ssize_t nstype_show(struct device *dev, |
301 | struct device_attribute *attr, char *buf) | |
302 | { | |
303 | struct nd_region *nd_region = to_nd_region(dev); | |
304 | ||
305 | return sprintf(buf, "%d\n", nd_region_to_nstype(nd_region)); | |
306 | } | |
307 | static DEVICE_ATTR_RO(nstype); | |
308 | ||
eaf96153 DW |
309 | static ssize_t set_cookie_show(struct device *dev, |
310 | struct device_attribute *attr, char *buf) | |
311 | { | |
312 | struct nd_region *nd_region = to_nd_region(dev); | |
313 | struct nd_interleave_set *nd_set = nd_region->nd_set; | |
c12c48ce | 314 | ssize_t rc = 0; |
eaf96153 | 315 | |
c9e582aa | 316 | if (is_memory(dev) && nd_set) |
eaf96153 DW |
317 | /* pass, should be precluded by region_visible */; |
318 | else | |
319 | return -ENXIO; | |
320 | ||
c12c48ce DW |
321 | /* |
322 | * The cookie to show depends on which specification of the | |
323 | * labels we are using. If there are not labels then default to | |
324 | * the v1.1 namespace label cookie definition. To read all this | |
325 | * data we need to wait for probing to settle. | |
326 | */ | |
327 | device_lock(dev); | |
328 | nvdimm_bus_lock(dev); | |
329 | wait_nvdimm_bus_probe_idle(dev); | |
330 | if (nd_region->ndr_mappings) { | |
331 | struct nd_mapping *nd_mapping = &nd_region->mapping[0]; | |
332 | struct nvdimm_drvdata *ndd = to_ndd(nd_mapping); | |
333 | ||
334 | if (ndd) { | |
335 | struct nd_namespace_index *nsindex; | |
336 | ||
337 | nsindex = to_namespace_index(ndd, ndd->ns_current); | |
338 | rc = sprintf(buf, "%#llx\n", | |
339 | nd_region_interleave_set_cookie(nd_region, | |
340 | nsindex)); | |
341 | } | |
342 | } | |
343 | nvdimm_bus_unlock(dev); | |
344 | device_unlock(dev); | |
345 | ||
346 | if (rc) | |
347 | return rc; | |
348 | return sprintf(buf, "%#llx\n", nd_set->cookie1); | |
eaf96153 DW |
349 | } |
350 | static DEVICE_ATTR_RO(set_cookie); | |
351 | ||
bf9bccc1 DW |
352 | resource_size_t nd_region_available_dpa(struct nd_region *nd_region) |
353 | { | |
354 | resource_size_t blk_max_overlap = 0, available, overlap; | |
355 | int i; | |
356 | ||
357 | WARN_ON(!is_nvdimm_bus_locked(&nd_region->dev)); | |
358 | ||
359 | retry: | |
360 | available = 0; | |
361 | overlap = blk_max_overlap; | |
362 | for (i = 0; i < nd_region->ndr_mappings; i++) { | |
363 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
364 | struct nvdimm_drvdata *ndd = to_ndd(nd_mapping); | |
365 | ||
366 | /* if a dimm is disabled the available capacity is zero */ | |
367 | if (!ndd) | |
368 | return 0; | |
369 | ||
c9e582aa | 370 | if (is_memory(&nd_region->dev)) { |
bf9bccc1 DW |
371 | available += nd_pmem_available_dpa(nd_region, |
372 | nd_mapping, &overlap); | |
373 | if (overlap > blk_max_overlap) { | |
374 | blk_max_overlap = overlap; | |
375 | goto retry; | |
376 | } | |
a1f3e4d6 DW |
377 | } else if (is_nd_blk(&nd_region->dev)) |
378 | available += nd_blk_available_dpa(nd_region); | |
bf9bccc1 DW |
379 | } |
380 | ||
381 | return available; | |
382 | } | |
383 | ||
384 | static ssize_t available_size_show(struct device *dev, | |
385 | struct device_attribute *attr, char *buf) | |
386 | { | |
387 | struct nd_region *nd_region = to_nd_region(dev); | |
388 | unsigned long long available = 0; | |
389 | ||
390 | /* | |
391 | * Flush in-flight updates and grab a snapshot of the available | |
392 | * size. Of course, this value is potentially invalidated the | |
393 | * memory nvdimm_bus_lock() is dropped, but that's userspace's | |
394 | * problem to not race itself. | |
395 | */ | |
396 | nvdimm_bus_lock(dev); | |
397 | wait_nvdimm_bus_probe_idle(dev); | |
398 | available = nd_region_available_dpa(nd_region); | |
399 | nvdimm_bus_unlock(dev); | |
400 | ||
401 | return sprintf(buf, "%llu\n", available); | |
402 | } | |
403 | static DEVICE_ATTR_RO(available_size); | |
404 | ||
3d88002e DW |
405 | static ssize_t init_namespaces_show(struct device *dev, |
406 | struct device_attribute *attr, char *buf) | |
407 | { | |
e5ae3b25 | 408 | struct nd_region_data *ndrd = dev_get_drvdata(dev); |
3d88002e DW |
409 | ssize_t rc; |
410 | ||
411 | nvdimm_bus_lock(dev); | |
e5ae3b25 DW |
412 | if (ndrd) |
413 | rc = sprintf(buf, "%d/%d\n", ndrd->ns_active, ndrd->ns_count); | |
3d88002e DW |
414 | else |
415 | rc = -ENXIO; | |
416 | nvdimm_bus_unlock(dev); | |
417 | ||
418 | return rc; | |
419 | } | |
420 | static DEVICE_ATTR_RO(init_namespaces); | |
421 | ||
bf9bccc1 DW |
422 | static ssize_t namespace_seed_show(struct device *dev, |
423 | struct device_attribute *attr, char *buf) | |
424 | { | |
425 | struct nd_region *nd_region = to_nd_region(dev); | |
426 | ssize_t rc; | |
427 | ||
428 | nvdimm_bus_lock(dev); | |
429 | if (nd_region->ns_seed) | |
430 | rc = sprintf(buf, "%s\n", dev_name(nd_region->ns_seed)); | |
431 | else | |
432 | rc = sprintf(buf, "\n"); | |
433 | nvdimm_bus_unlock(dev); | |
434 | return rc; | |
435 | } | |
436 | static DEVICE_ATTR_RO(namespace_seed); | |
437 | ||
8c2f7e86 DW |
438 | static ssize_t btt_seed_show(struct device *dev, |
439 | struct device_attribute *attr, char *buf) | |
440 | { | |
441 | struct nd_region *nd_region = to_nd_region(dev); | |
442 | ssize_t rc; | |
443 | ||
444 | nvdimm_bus_lock(dev); | |
445 | if (nd_region->btt_seed) | |
446 | rc = sprintf(buf, "%s\n", dev_name(nd_region->btt_seed)); | |
447 | else | |
448 | rc = sprintf(buf, "\n"); | |
449 | nvdimm_bus_unlock(dev); | |
450 | ||
451 | return rc; | |
452 | } | |
453 | static DEVICE_ATTR_RO(btt_seed); | |
454 | ||
e1455744 DW |
455 | static ssize_t pfn_seed_show(struct device *dev, |
456 | struct device_attribute *attr, char *buf) | |
457 | { | |
458 | struct nd_region *nd_region = to_nd_region(dev); | |
459 | ssize_t rc; | |
460 | ||
461 | nvdimm_bus_lock(dev); | |
462 | if (nd_region->pfn_seed) | |
463 | rc = sprintf(buf, "%s\n", dev_name(nd_region->pfn_seed)); | |
464 | else | |
465 | rc = sprintf(buf, "\n"); | |
466 | nvdimm_bus_unlock(dev); | |
467 | ||
468 | return rc; | |
469 | } | |
470 | static DEVICE_ATTR_RO(pfn_seed); | |
471 | ||
cd03412a DW |
472 | static ssize_t dax_seed_show(struct device *dev, |
473 | struct device_attribute *attr, char *buf) | |
474 | { | |
475 | struct nd_region *nd_region = to_nd_region(dev); | |
476 | ssize_t rc; | |
477 | ||
478 | nvdimm_bus_lock(dev); | |
479 | if (nd_region->dax_seed) | |
480 | rc = sprintf(buf, "%s\n", dev_name(nd_region->dax_seed)); | |
481 | else | |
482 | rc = sprintf(buf, "\n"); | |
483 | nvdimm_bus_unlock(dev); | |
484 | ||
485 | return rc; | |
486 | } | |
487 | static DEVICE_ATTR_RO(dax_seed); | |
488 | ||
58138820 DW |
489 | static ssize_t read_only_show(struct device *dev, |
490 | struct device_attribute *attr, char *buf) | |
491 | { | |
492 | struct nd_region *nd_region = to_nd_region(dev); | |
493 | ||
494 | return sprintf(buf, "%d\n", nd_region->ro); | |
495 | } | |
496 | ||
497 | static ssize_t read_only_store(struct device *dev, | |
498 | struct device_attribute *attr, const char *buf, size_t len) | |
499 | { | |
500 | bool ro; | |
501 | int rc = strtobool(buf, &ro); | |
502 | struct nd_region *nd_region = to_nd_region(dev); | |
503 | ||
504 | if (rc) | |
505 | return rc; | |
506 | ||
507 | nd_region->ro = ro; | |
508 | return len; | |
509 | } | |
510 | static DEVICE_ATTR_RW(read_only); | |
511 | ||
23f49844 | 512 | static ssize_t region_badblocks_show(struct device *dev, |
6a6bef90 DJ |
513 | struct device_attribute *attr, char *buf) |
514 | { | |
515 | struct nd_region *nd_region = to_nd_region(dev); | |
516 | ||
517 | return badblocks_show(&nd_region->bb, buf, 0); | |
518 | } | |
23f49844 DW |
519 | |
520 | static DEVICE_ATTR(badblocks, 0444, region_badblocks_show, NULL); | |
6a6bef90 | 521 | |
802f4be6 DJ |
522 | static ssize_t resource_show(struct device *dev, |
523 | struct device_attribute *attr, char *buf) | |
524 | { | |
525 | struct nd_region *nd_region = to_nd_region(dev); | |
526 | ||
527 | return sprintf(buf, "%#llx\n", nd_region->ndr_start); | |
528 | } | |
529 | static DEVICE_ATTR_RO(resource); | |
530 | ||
96c3a239 DJ |
531 | static ssize_t persistence_domain_show(struct device *dev, |
532 | struct device_attribute *attr, char *buf) | |
533 | { | |
534 | struct nd_region *nd_region = to_nd_region(dev); | |
535 | unsigned long flags = nd_region->flags; | |
536 | ||
537 | return sprintf(buf, "%s%s\n", | |
538 | flags & BIT(ND_REGION_PERSIST_CACHE) ? "cpu_cache " : "", | |
539 | flags & BIT(ND_REGION_PERSIST_MEMCTRL) ? "memory_controller " : ""); | |
540 | } | |
541 | static DEVICE_ATTR_RO(persistence_domain); | |
542 | ||
1f7df6f8 DW |
543 | static struct attribute *nd_region_attributes[] = { |
544 | &dev_attr_size.attr, | |
3d88002e | 545 | &dev_attr_nstype.attr, |
1f7df6f8 | 546 | &dev_attr_mappings.attr, |
8c2f7e86 | 547 | &dev_attr_btt_seed.attr, |
e1455744 | 548 | &dev_attr_pfn_seed.attr, |
cd03412a | 549 | &dev_attr_dax_seed.attr, |
ab630891 | 550 | &dev_attr_deep_flush.attr, |
58138820 | 551 | &dev_attr_read_only.attr, |
eaf96153 | 552 | &dev_attr_set_cookie.attr, |
bf9bccc1 DW |
553 | &dev_attr_available_size.attr, |
554 | &dev_attr_namespace_seed.attr, | |
3d88002e | 555 | &dev_attr_init_namespaces.attr, |
23f49844 | 556 | &dev_attr_badblocks.attr, |
802f4be6 | 557 | &dev_attr_resource.attr, |
96c3a239 | 558 | &dev_attr_persistence_domain.attr, |
1f7df6f8 DW |
559 | NULL, |
560 | }; | |
561 | ||
eaf96153 DW |
562 | static umode_t region_visible(struct kobject *kobj, struct attribute *a, int n) |
563 | { | |
564 | struct device *dev = container_of(kobj, typeof(*dev), kobj); | |
565 | struct nd_region *nd_region = to_nd_region(dev); | |
566 | struct nd_interleave_set *nd_set = nd_region->nd_set; | |
bf9bccc1 | 567 | int type = nd_region_to_nstype(nd_region); |
eaf96153 | 568 | |
c9e582aa | 569 | if (!is_memory(dev) && a == &dev_attr_pfn_seed.attr) |
6bb691ac DK |
570 | return 0; |
571 | ||
c9e582aa | 572 | if (!is_memory(dev) && a == &dev_attr_dax_seed.attr) |
cd03412a DW |
573 | return 0; |
574 | ||
23f49844 | 575 | if (!is_nd_pmem(dev) && a == &dev_attr_badblocks.attr) |
6a6bef90 DJ |
576 | return 0; |
577 | ||
b8ff981f DW |
578 | if (a == &dev_attr_resource.attr) { |
579 | if (is_nd_pmem(dev)) | |
580 | return 0400; | |
581 | else | |
582 | return 0; | |
583 | } | |
802f4be6 | 584 | |
ab630891 DW |
585 | if (a == &dev_attr_deep_flush.attr) { |
586 | int has_flush = nvdimm_has_flush(nd_region); | |
587 | ||
588 | if (has_flush == 1) | |
589 | return a->mode; | |
590 | else if (has_flush == 0) | |
591 | return 0444; | |
592 | else | |
593 | return 0; | |
594 | } | |
595 | ||
896196dc DW |
596 | if (a == &dev_attr_persistence_domain.attr) { |
597 | if ((nd_region->flags & (BIT(ND_REGION_PERSIST_CACHE) | |
598 | | BIT(ND_REGION_PERSIST_MEMCTRL))) == 0) | |
599 | return 0; | |
600 | return a->mode; | |
601 | } | |
602 | ||
bf9bccc1 DW |
603 | if (a != &dev_attr_set_cookie.attr |
604 | && a != &dev_attr_available_size.attr) | |
eaf96153 DW |
605 | return a->mode; |
606 | ||
bf9bccc1 DW |
607 | if ((type == ND_DEVICE_NAMESPACE_PMEM |
608 | || type == ND_DEVICE_NAMESPACE_BLK) | |
609 | && a == &dev_attr_available_size.attr) | |
610 | return a->mode; | |
c9e582aa | 611 | else if (is_memory(dev) && nd_set) |
bf9bccc1 | 612 | return a->mode; |
eaf96153 DW |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
1f7df6f8 DW |
617 | struct attribute_group nd_region_attribute_group = { |
618 | .attrs = nd_region_attributes, | |
eaf96153 | 619 | .is_visible = region_visible, |
1f7df6f8 DW |
620 | }; |
621 | EXPORT_SYMBOL_GPL(nd_region_attribute_group); | |
622 | ||
c12c48ce DW |
623 | u64 nd_region_interleave_set_cookie(struct nd_region *nd_region, |
624 | struct nd_namespace_index *nsindex) | |
bf9bccc1 DW |
625 | { |
626 | struct nd_interleave_set *nd_set = nd_region->nd_set; | |
627 | ||
c12c48ce DW |
628 | if (!nd_set) |
629 | return 0; | |
630 | ||
631 | if (nsindex && __le16_to_cpu(nsindex->major) == 1 | |
632 | && __le16_to_cpu(nsindex->minor) == 1) | |
633 | return nd_set->cookie1; | |
634 | return nd_set->cookie2; | |
bf9bccc1 DW |
635 | } |
636 | ||
86ef58a4 DW |
637 | u64 nd_region_interleave_set_altcookie(struct nd_region *nd_region) |
638 | { | |
639 | struct nd_interleave_set *nd_set = nd_region->nd_set; | |
640 | ||
641 | if (nd_set) | |
642 | return nd_set->altcookie; | |
643 | return 0; | |
644 | } | |
645 | ||
ae8219f1 DW |
646 | void nd_mapping_free_labels(struct nd_mapping *nd_mapping) |
647 | { | |
648 | struct nd_label_ent *label_ent, *e; | |
649 | ||
9cf8bd52 | 650 | lockdep_assert_held(&nd_mapping->lock); |
ae8219f1 DW |
651 | list_for_each_entry_safe(label_ent, e, &nd_mapping->labels, list) { |
652 | list_del(&label_ent->list); | |
653 | kfree(label_ent); | |
654 | } | |
655 | } | |
656 | ||
eaf96153 DW |
657 | /* |
658 | * Upon successful probe/remove, take/release a reference on the | |
8c2f7e86 | 659 | * associated interleave set (if present), and plant new btt + namespace |
047fc8a1 RZ |
660 | * seeds. Also, on the removal of a BLK region, notify the provider to |
661 | * disable the region. | |
eaf96153 DW |
662 | */ |
663 | static void nd_region_notify_driver_action(struct nvdimm_bus *nvdimm_bus, | |
664 | struct device *dev, bool probe) | |
665 | { | |
8c2f7e86 DW |
666 | struct nd_region *nd_region; |
667 | ||
c9e582aa | 668 | if (!probe && is_nd_region(dev)) { |
eaf96153 DW |
669 | int i; |
670 | ||
8c2f7e86 | 671 | nd_region = to_nd_region(dev); |
eaf96153 DW |
672 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
673 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
bf9bccc1 | 674 | struct nvdimm_drvdata *ndd = nd_mapping->ndd; |
eaf96153 DW |
675 | struct nvdimm *nvdimm = nd_mapping->nvdimm; |
676 | ||
ae8219f1 DW |
677 | mutex_lock(&nd_mapping->lock); |
678 | nd_mapping_free_labels(nd_mapping); | |
679 | mutex_unlock(&nd_mapping->lock); | |
680 | ||
bf9bccc1 DW |
681 | put_ndd(ndd); |
682 | nd_mapping->ndd = NULL; | |
047fc8a1 RZ |
683 | if (ndd) |
684 | atomic_dec(&nvdimm->busy); | |
eaf96153 | 685 | } |
8c2f7e86 | 686 | } |
c9e582aa | 687 | if (dev->parent && is_nd_region(dev->parent) && probe) { |
8c2f7e86 | 688 | nd_region = to_nd_region(dev->parent); |
1b40e09a DW |
689 | nvdimm_bus_lock(dev); |
690 | if (nd_region->ns_seed == dev) | |
98a29c39 | 691 | nd_region_create_ns_seed(nd_region); |
1b40e09a | 692 | nvdimm_bus_unlock(dev); |
eaf96153 | 693 | } |
8c2f7e86 | 694 | if (is_nd_btt(dev) && probe) { |
8ca24353 DW |
695 | struct nd_btt *nd_btt = to_nd_btt(dev); |
696 | ||
8c2f7e86 DW |
697 | nd_region = to_nd_region(dev->parent); |
698 | nvdimm_bus_lock(dev); | |
699 | if (nd_region->btt_seed == dev) | |
700 | nd_region_create_btt_seed(nd_region); | |
98a29c39 DW |
701 | if (nd_region->ns_seed == &nd_btt->ndns->dev) |
702 | nd_region_create_ns_seed(nd_region); | |
8c2f7e86 DW |
703 | nvdimm_bus_unlock(dev); |
704 | } | |
2dc43331 | 705 | if (is_nd_pfn(dev) && probe) { |
98a29c39 DW |
706 | struct nd_pfn *nd_pfn = to_nd_pfn(dev); |
707 | ||
2dc43331 DW |
708 | nd_region = to_nd_region(dev->parent); |
709 | nvdimm_bus_lock(dev); | |
710 | if (nd_region->pfn_seed == dev) | |
711 | nd_region_create_pfn_seed(nd_region); | |
98a29c39 DW |
712 | if (nd_region->ns_seed == &nd_pfn->ndns->dev) |
713 | nd_region_create_ns_seed(nd_region); | |
2dc43331 DW |
714 | nvdimm_bus_unlock(dev); |
715 | } | |
cd03412a | 716 | if (is_nd_dax(dev) && probe) { |
98a29c39 DW |
717 | struct nd_dax *nd_dax = to_nd_dax(dev); |
718 | ||
cd03412a DW |
719 | nd_region = to_nd_region(dev->parent); |
720 | nvdimm_bus_lock(dev); | |
721 | if (nd_region->dax_seed == dev) | |
722 | nd_region_create_dax_seed(nd_region); | |
98a29c39 DW |
723 | if (nd_region->ns_seed == &nd_dax->nd_pfn.ndns->dev) |
724 | nd_region_create_ns_seed(nd_region); | |
cd03412a DW |
725 | nvdimm_bus_unlock(dev); |
726 | } | |
eaf96153 DW |
727 | } |
728 | ||
729 | void nd_region_probe_success(struct nvdimm_bus *nvdimm_bus, struct device *dev) | |
730 | { | |
731 | nd_region_notify_driver_action(nvdimm_bus, dev, true); | |
732 | } | |
733 | ||
734 | void nd_region_disable(struct nvdimm_bus *nvdimm_bus, struct device *dev) | |
735 | { | |
736 | nd_region_notify_driver_action(nvdimm_bus, dev, false); | |
737 | } | |
738 | ||
1f7df6f8 DW |
739 | static ssize_t mappingN(struct device *dev, char *buf, int n) |
740 | { | |
741 | struct nd_region *nd_region = to_nd_region(dev); | |
742 | struct nd_mapping *nd_mapping; | |
743 | struct nvdimm *nvdimm; | |
744 | ||
745 | if (n >= nd_region->ndr_mappings) | |
746 | return -ENXIO; | |
747 | nd_mapping = &nd_region->mapping[n]; | |
748 | nvdimm = nd_mapping->nvdimm; | |
749 | ||
401c0a19 DW |
750 | return sprintf(buf, "%s,%llu,%llu,%d\n", dev_name(&nvdimm->dev), |
751 | nd_mapping->start, nd_mapping->size, | |
752 | nd_mapping->position); | |
1f7df6f8 DW |
753 | } |
754 | ||
755 | #define REGION_MAPPING(idx) \ | |
756 | static ssize_t mapping##idx##_show(struct device *dev, \ | |
757 | struct device_attribute *attr, char *buf) \ | |
758 | { \ | |
759 | return mappingN(dev, buf, idx); \ | |
760 | } \ | |
761 | static DEVICE_ATTR_RO(mapping##idx) | |
762 | ||
763 | /* | |
764 | * 32 should be enough for a while, even in the presence of socket | |
765 | * interleave a 32-way interleave set is a degenerate case. | |
766 | */ | |
767 | REGION_MAPPING(0); | |
768 | REGION_MAPPING(1); | |
769 | REGION_MAPPING(2); | |
770 | REGION_MAPPING(3); | |
771 | REGION_MAPPING(4); | |
772 | REGION_MAPPING(5); | |
773 | REGION_MAPPING(6); | |
774 | REGION_MAPPING(7); | |
775 | REGION_MAPPING(8); | |
776 | REGION_MAPPING(9); | |
777 | REGION_MAPPING(10); | |
778 | REGION_MAPPING(11); | |
779 | REGION_MAPPING(12); | |
780 | REGION_MAPPING(13); | |
781 | REGION_MAPPING(14); | |
782 | REGION_MAPPING(15); | |
783 | REGION_MAPPING(16); | |
784 | REGION_MAPPING(17); | |
785 | REGION_MAPPING(18); | |
786 | REGION_MAPPING(19); | |
787 | REGION_MAPPING(20); | |
788 | REGION_MAPPING(21); | |
789 | REGION_MAPPING(22); | |
790 | REGION_MAPPING(23); | |
791 | REGION_MAPPING(24); | |
792 | REGION_MAPPING(25); | |
793 | REGION_MAPPING(26); | |
794 | REGION_MAPPING(27); | |
795 | REGION_MAPPING(28); | |
796 | REGION_MAPPING(29); | |
797 | REGION_MAPPING(30); | |
798 | REGION_MAPPING(31); | |
799 | ||
800 | static umode_t mapping_visible(struct kobject *kobj, struct attribute *a, int n) | |
801 | { | |
802 | struct device *dev = container_of(kobj, struct device, kobj); | |
803 | struct nd_region *nd_region = to_nd_region(dev); | |
804 | ||
805 | if (n < nd_region->ndr_mappings) | |
806 | return a->mode; | |
807 | return 0; | |
808 | } | |
809 | ||
810 | static struct attribute *mapping_attributes[] = { | |
811 | &dev_attr_mapping0.attr, | |
812 | &dev_attr_mapping1.attr, | |
813 | &dev_attr_mapping2.attr, | |
814 | &dev_attr_mapping3.attr, | |
815 | &dev_attr_mapping4.attr, | |
816 | &dev_attr_mapping5.attr, | |
817 | &dev_attr_mapping6.attr, | |
818 | &dev_attr_mapping7.attr, | |
819 | &dev_attr_mapping8.attr, | |
820 | &dev_attr_mapping9.attr, | |
821 | &dev_attr_mapping10.attr, | |
822 | &dev_attr_mapping11.attr, | |
823 | &dev_attr_mapping12.attr, | |
824 | &dev_attr_mapping13.attr, | |
825 | &dev_attr_mapping14.attr, | |
826 | &dev_attr_mapping15.attr, | |
827 | &dev_attr_mapping16.attr, | |
828 | &dev_attr_mapping17.attr, | |
829 | &dev_attr_mapping18.attr, | |
830 | &dev_attr_mapping19.attr, | |
831 | &dev_attr_mapping20.attr, | |
832 | &dev_attr_mapping21.attr, | |
833 | &dev_attr_mapping22.attr, | |
834 | &dev_attr_mapping23.attr, | |
835 | &dev_attr_mapping24.attr, | |
836 | &dev_attr_mapping25.attr, | |
837 | &dev_attr_mapping26.attr, | |
838 | &dev_attr_mapping27.attr, | |
839 | &dev_attr_mapping28.attr, | |
840 | &dev_attr_mapping29.attr, | |
841 | &dev_attr_mapping30.attr, | |
842 | &dev_attr_mapping31.attr, | |
843 | NULL, | |
844 | }; | |
845 | ||
846 | struct attribute_group nd_mapping_attribute_group = { | |
847 | .is_visible = mapping_visible, | |
848 | .attrs = mapping_attributes, | |
849 | }; | |
850 | EXPORT_SYMBOL_GPL(nd_mapping_attribute_group); | |
851 | ||
047fc8a1 | 852 | int nd_blk_region_init(struct nd_region *nd_region) |
1f7df6f8 | 853 | { |
047fc8a1 RZ |
854 | struct device *dev = &nd_region->dev; |
855 | struct nvdimm_bus *nvdimm_bus = walk_to_nvdimm_bus(dev); | |
856 | ||
857 | if (!is_nd_blk(dev)) | |
858 | return 0; | |
859 | ||
860 | if (nd_region->ndr_mappings < 1) { | |
d5d51fec | 861 | dev_dbg(dev, "invalid BLK region\n"); |
047fc8a1 RZ |
862 | return -ENXIO; |
863 | } | |
864 | ||
865 | return to_nd_blk_region(dev)->enable(nvdimm_bus, dev); | |
1f7df6f8 | 866 | } |
1f7df6f8 | 867 | |
5212e11f VV |
868 | /** |
869 | * nd_region_acquire_lane - allocate and lock a lane | |
870 | * @nd_region: region id and number of lanes possible | |
871 | * | |
872 | * A lane correlates to a BLK-data-window and/or a log slot in the BTT. | |
873 | * We optimize for the common case where there are 256 lanes, one | |
874 | * per-cpu. For larger systems we need to lock to share lanes. For now | |
875 | * this implementation assumes the cost of maintaining an allocator for | |
876 | * free lanes is on the order of the lock hold time, so it implements a | |
877 | * static lane = cpu % num_lanes mapping. | |
878 | * | |
879 | * In the case of a BTT instance on top of a BLK namespace a lane may be | |
880 | * acquired recursively. We lock on the first instance. | |
881 | * | |
882 | * In the case of a BTT instance on top of PMEM, we only acquire a lane | |
883 | * for the BTT metadata updates. | |
884 | */ | |
885 | unsigned int nd_region_acquire_lane(struct nd_region *nd_region) | |
886 | { | |
887 | unsigned int cpu, lane; | |
888 | ||
889 | cpu = get_cpu(); | |
890 | if (nd_region->num_lanes < nr_cpu_ids) { | |
891 | struct nd_percpu_lane *ndl_lock, *ndl_count; | |
892 | ||
893 | lane = cpu % nd_region->num_lanes; | |
894 | ndl_count = per_cpu_ptr(nd_region->lane, cpu); | |
895 | ndl_lock = per_cpu_ptr(nd_region->lane, lane); | |
896 | if (ndl_count->count++ == 0) | |
897 | spin_lock(&ndl_lock->lock); | |
898 | } else | |
899 | lane = cpu; | |
900 | ||
901 | return lane; | |
902 | } | |
903 | EXPORT_SYMBOL(nd_region_acquire_lane); | |
904 | ||
905 | void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane) | |
906 | { | |
907 | if (nd_region->num_lanes < nr_cpu_ids) { | |
908 | unsigned int cpu = get_cpu(); | |
909 | struct nd_percpu_lane *ndl_lock, *ndl_count; | |
910 | ||
911 | ndl_count = per_cpu_ptr(nd_region->lane, cpu); | |
912 | ndl_lock = per_cpu_ptr(nd_region->lane, lane); | |
913 | if (--ndl_count->count == 0) | |
914 | spin_unlock(&ndl_lock->lock); | |
915 | put_cpu(); | |
916 | } | |
917 | put_cpu(); | |
918 | } | |
919 | EXPORT_SYMBOL(nd_region_release_lane); | |
920 | ||
1f7df6f8 DW |
921 | static struct nd_region *nd_region_create(struct nvdimm_bus *nvdimm_bus, |
922 | struct nd_region_desc *ndr_desc, struct device_type *dev_type, | |
923 | const char *caller) | |
924 | { | |
925 | struct nd_region *nd_region; | |
926 | struct device *dev; | |
047fc8a1 | 927 | void *region_buf; |
5212e11f | 928 | unsigned int i; |
58138820 | 929 | int ro = 0; |
1f7df6f8 DW |
930 | |
931 | for (i = 0; i < ndr_desc->num_mappings; i++) { | |
44c462eb DW |
932 | struct nd_mapping_desc *mapping = &ndr_desc->mapping[i]; |
933 | struct nvdimm *nvdimm = mapping->nvdimm; | |
1f7df6f8 | 934 | |
44c462eb | 935 | if ((mapping->start | mapping->size) % SZ_4K) { |
1f7df6f8 DW |
936 | dev_err(&nvdimm_bus->dev, "%s: %s mapping%d is not 4K aligned\n", |
937 | caller, dev_name(&nvdimm->dev), i); | |
938 | ||
939 | return NULL; | |
940 | } | |
58138820 | 941 | |
8f078b38 | 942 | if (test_bit(NDD_UNARMED, &nvdimm->flags)) |
58138820 | 943 | ro = 1; |
1f7df6f8 DW |
944 | } |
945 | ||
047fc8a1 RZ |
946 | if (dev_type == &nd_blk_device_type) { |
947 | struct nd_blk_region_desc *ndbr_desc; | |
948 | struct nd_blk_region *ndbr; | |
949 | ||
950 | ndbr_desc = to_blk_region_desc(ndr_desc); | |
951 | ndbr = kzalloc(sizeof(*ndbr) + sizeof(struct nd_mapping) | |
952 | * ndr_desc->num_mappings, | |
953 | GFP_KERNEL); | |
954 | if (ndbr) { | |
955 | nd_region = &ndbr->nd_region; | |
956 | ndbr->enable = ndbr_desc->enable; | |
047fc8a1 RZ |
957 | ndbr->do_io = ndbr_desc->do_io; |
958 | } | |
959 | region_buf = ndbr; | |
960 | } else { | |
961 | nd_region = kzalloc(sizeof(struct nd_region) | |
962 | + sizeof(struct nd_mapping) | |
963 | * ndr_desc->num_mappings, | |
964 | GFP_KERNEL); | |
965 | region_buf = nd_region; | |
966 | } | |
967 | ||
968 | if (!region_buf) | |
1f7df6f8 DW |
969 | return NULL; |
970 | nd_region->id = ida_simple_get(®ion_ida, 0, 0, GFP_KERNEL); | |
5212e11f VV |
971 | if (nd_region->id < 0) |
972 | goto err_id; | |
973 | ||
974 | nd_region->lane = alloc_percpu(struct nd_percpu_lane); | |
975 | if (!nd_region->lane) | |
976 | goto err_percpu; | |
977 | ||
978 | for (i = 0; i < nr_cpu_ids; i++) { | |
979 | struct nd_percpu_lane *ndl; | |
980 | ||
981 | ndl = per_cpu_ptr(nd_region->lane, i); | |
982 | spin_lock_init(&ndl->lock); | |
983 | ndl->count = 0; | |
1f7df6f8 DW |
984 | } |
985 | ||
1f7df6f8 | 986 | for (i = 0; i < ndr_desc->num_mappings; i++) { |
44c462eb DW |
987 | struct nd_mapping_desc *mapping = &ndr_desc->mapping[i]; |
988 | struct nvdimm *nvdimm = mapping->nvdimm; | |
989 | ||
990 | nd_region->mapping[i].nvdimm = nvdimm; | |
991 | nd_region->mapping[i].start = mapping->start; | |
992 | nd_region->mapping[i].size = mapping->size; | |
401c0a19 | 993 | nd_region->mapping[i].position = mapping->position; |
ae8219f1 DW |
994 | INIT_LIST_HEAD(&nd_region->mapping[i].labels); |
995 | mutex_init(&nd_region->mapping[i].lock); | |
1f7df6f8 DW |
996 | |
997 | get_device(&nvdimm->dev); | |
998 | } | |
999 | nd_region->ndr_mappings = ndr_desc->num_mappings; | |
1000 | nd_region->provider_data = ndr_desc->provider_data; | |
eaf96153 | 1001 | nd_region->nd_set = ndr_desc->nd_set; |
5212e11f | 1002 | nd_region->num_lanes = ndr_desc->num_lanes; |
004f1afb | 1003 | nd_region->flags = ndr_desc->flags; |
58138820 | 1004 | nd_region->ro = ro; |
41d7a6d6 | 1005 | nd_region->numa_node = ndr_desc->numa_node; |
1b40e09a | 1006 | ida_init(&nd_region->ns_ida); |
8c2f7e86 | 1007 | ida_init(&nd_region->btt_ida); |
e1455744 | 1008 | ida_init(&nd_region->pfn_ida); |
cd03412a | 1009 | ida_init(&nd_region->dax_ida); |
1f7df6f8 DW |
1010 | dev = &nd_region->dev; |
1011 | dev_set_name(dev, "region%d", nd_region->id); | |
1012 | dev->parent = &nvdimm_bus->dev; | |
1013 | dev->type = dev_type; | |
1014 | dev->groups = ndr_desc->attr_groups; | |
1015 | nd_region->ndr_size = resource_size(ndr_desc->res); | |
1016 | nd_region->ndr_start = ndr_desc->res->start; | |
1017 | nd_device_register(dev); | |
1018 | ||
1019 | return nd_region; | |
5212e11f VV |
1020 | |
1021 | err_percpu: | |
1022 | ida_simple_remove(®ion_ida, nd_region->id); | |
1023 | err_id: | |
047fc8a1 | 1024 | kfree(region_buf); |
5212e11f | 1025 | return NULL; |
1f7df6f8 DW |
1026 | } |
1027 | ||
1028 | struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, | |
1029 | struct nd_region_desc *ndr_desc) | |
1030 | { | |
5212e11f | 1031 | ndr_desc->num_lanes = ND_MAX_LANES; |
1f7df6f8 DW |
1032 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_pmem_device_type, |
1033 | __func__); | |
1034 | } | |
1035 | EXPORT_SYMBOL_GPL(nvdimm_pmem_region_create); | |
1036 | ||
1037 | struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, | |
1038 | struct nd_region_desc *ndr_desc) | |
1039 | { | |
1040 | if (ndr_desc->num_mappings > 1) | |
1041 | return NULL; | |
5212e11f | 1042 | ndr_desc->num_lanes = min(ndr_desc->num_lanes, ND_MAX_LANES); |
1f7df6f8 DW |
1043 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_blk_device_type, |
1044 | __func__); | |
1045 | } | |
1046 | EXPORT_SYMBOL_GPL(nvdimm_blk_region_create); | |
1047 | ||
1048 | struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus, | |
1049 | struct nd_region_desc *ndr_desc) | |
1050 | { | |
5212e11f | 1051 | ndr_desc->num_lanes = ND_MAX_LANES; |
1f7df6f8 DW |
1052 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_volatile_device_type, |
1053 | __func__); | |
1054 | } | |
1055 | EXPORT_SYMBOL_GPL(nvdimm_volatile_region_create); | |
b354aba0 | 1056 | |
f284a4f2 DW |
1057 | /** |
1058 | * nvdimm_flush - flush any posted write queues between the cpu and pmem media | |
1059 | * @nd_region: blk or interleaved pmem region | |
1060 | */ | |
1061 | void nvdimm_flush(struct nd_region *nd_region) | |
1062 | { | |
1063 | struct nd_region_data *ndrd = dev_get_drvdata(&nd_region->dev); | |
0c27af60 DW |
1064 | int i, idx; |
1065 | ||
1066 | /* | |
1067 | * Try to encourage some diversity in flush hint addresses | |
1068 | * across cpus assuming a limited number of flush hints. | |
1069 | */ | |
1070 | idx = this_cpu_read(flush_idx); | |
1071 | idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8)); | |
f284a4f2 DW |
1072 | |
1073 | /* | |
1074 | * The first wmb() is needed to 'sfence' all previous writes | |
1075 | * such that they are architecturally visible for the platform | |
1076 | * buffer flush. Note that we've already arranged for pmem | |
0aed55af DW |
1077 | * writes to avoid the cache via memcpy_flushcache(). The final |
1078 | * wmb() ensures ordering for the NVDIMM flush write. | |
f284a4f2 DW |
1079 | */ |
1080 | wmb(); | |
1081 | for (i = 0; i < nd_region->ndr_mappings; i++) | |
595c7307 DW |
1082 | if (ndrd_get_flush_wpq(ndrd, i, 0)) |
1083 | writeq(1, ndrd_get_flush_wpq(ndrd, i, idx)); | |
f284a4f2 DW |
1084 | wmb(); |
1085 | } | |
1086 | EXPORT_SYMBOL_GPL(nvdimm_flush); | |
1087 | ||
1088 | /** | |
1089 | * nvdimm_has_flush - determine write flushing requirements | |
1090 | * @nd_region: blk or interleaved pmem region | |
1091 | * | |
1092 | * Returns 1 if writes require flushing | |
1093 | * Returns 0 if writes do not require flushing | |
1094 | * Returns -ENXIO if flushing capability can not be determined | |
1095 | */ | |
1096 | int nvdimm_has_flush(struct nd_region *nd_region) | |
1097 | { | |
f284a4f2 DW |
1098 | int i; |
1099 | ||
c00b396e DW |
1100 | /* no nvdimm or pmem api == flushing capability unknown */ |
1101 | if (nd_region->ndr_mappings == 0 | |
1102 | || !IS_ENABLED(CONFIG_ARCH_HAS_PMEM_API)) | |
f284a4f2 DW |
1103 | return -ENXIO; |
1104 | ||
bc042fdf DW |
1105 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
1106 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
1107 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
1108 | ||
1109 | /* flush hints present / available */ | |
1110 | if (nvdimm->num_flush) | |
f284a4f2 | 1111 | return 1; |
bc042fdf | 1112 | } |
f284a4f2 DW |
1113 | |
1114 | /* | |
1115 | * The platform defines dimm devices without hints, assume | |
1116 | * platform persistence mechanism like ADR | |
1117 | */ | |
1118 | return 0; | |
1119 | } | |
1120 | EXPORT_SYMBOL_GPL(nvdimm_has_flush); | |
1121 | ||
0b277961 DW |
1122 | int nvdimm_has_cache(struct nd_region *nd_region) |
1123 | { | |
1124 | return is_nd_pmem(&nd_region->dev); | |
1125 | } | |
1126 | EXPORT_SYMBOL_GPL(nvdimm_has_cache); | |
1127 | ||
b354aba0 DW |
1128 | void __exit nd_region_devs_exit(void) |
1129 | { | |
1130 | ida_destroy(®ion_ida); | |
1131 | } |