Commit | Line | Data |
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1f7df6f8 DW |
1 | /* |
2 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of version 2 of the GNU General Public License as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | */ | |
eaf96153 | 13 | #include <linux/scatterlist.h> |
047fc8a1 | 14 | #include <linux/highmem.h> |
eaf96153 | 15 | #include <linux/sched.h> |
1f7df6f8 | 16 | #include <linux/slab.h> |
0c27af60 | 17 | #include <linux/hash.h> |
eaf96153 | 18 | #include <linux/sort.h> |
1f7df6f8 | 19 | #include <linux/io.h> |
bf9bccc1 | 20 | #include <linux/nd.h> |
1f7df6f8 DW |
21 | #include "nd-core.h" |
22 | #include "nd.h" | |
23 | ||
f284a4f2 DW |
24 | /* |
25 | * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is | |
26 | * irrelevant. | |
27 | */ | |
28 | #include <linux/io-64-nonatomic-hi-lo.h> | |
29 | ||
1f7df6f8 | 30 | static DEFINE_IDA(region_ida); |
0c27af60 | 31 | static DEFINE_PER_CPU(int, flush_idx); |
1f7df6f8 | 32 | |
e5ae3b25 DW |
33 | static int nvdimm_map_flush(struct device *dev, struct nvdimm *nvdimm, int dimm, |
34 | struct nd_region_data *ndrd) | |
35 | { | |
36 | int i, j; | |
37 | ||
38 | dev_dbg(dev, "%s: map %d flush address%s\n", nvdimm_name(nvdimm), | |
39 | nvdimm->num_flush, nvdimm->num_flush == 1 ? "" : "es"); | |
595c7307 | 40 | for (i = 0; i < (1 << ndrd->hints_shift); i++) { |
e5ae3b25 DW |
41 | struct resource *res = &nvdimm->flush_wpq[i]; |
42 | unsigned long pfn = PHYS_PFN(res->start); | |
43 | void __iomem *flush_page; | |
44 | ||
45 | /* check if flush hints share a page */ | |
46 | for (j = 0; j < i; j++) { | |
47 | struct resource *res_j = &nvdimm->flush_wpq[j]; | |
48 | unsigned long pfn_j = PHYS_PFN(res_j->start); | |
49 | ||
50 | if (pfn == pfn_j) | |
51 | break; | |
52 | } | |
53 | ||
54 | if (j < i) | |
55 | flush_page = (void __iomem *) ((unsigned long) | |
595c7307 DW |
56 | ndrd_get_flush_wpq(ndrd, dimm, j) |
57 | & PAGE_MASK); | |
e5ae3b25 DW |
58 | else |
59 | flush_page = devm_nvdimm_ioremap(dev, | |
480b6837 | 60 | PFN_PHYS(pfn), PAGE_SIZE); |
e5ae3b25 DW |
61 | if (!flush_page) |
62 | return -ENXIO; | |
595c7307 DW |
63 | ndrd_set_flush_wpq(ndrd, dimm, i, flush_page |
64 | + (res->start & ~PAGE_MASK)); | |
e5ae3b25 DW |
65 | } |
66 | ||
67 | return 0; | |
68 | } | |
69 | ||
70 | int nd_region_activate(struct nd_region *nd_region) | |
71 | { | |
db58028e | 72 | int i, j, num_flush = 0; |
e5ae3b25 DW |
73 | struct nd_region_data *ndrd; |
74 | struct device *dev = &nd_region->dev; | |
75 | size_t flush_data_size = sizeof(void *); | |
76 | ||
77 | nvdimm_bus_lock(&nd_region->dev); | |
78 | for (i = 0; i < nd_region->ndr_mappings; i++) { | |
79 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
80 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
81 | ||
82 | /* at least one null hint slot per-dimm for the "no-hint" case */ | |
83 | flush_data_size += sizeof(void *); | |
0c27af60 | 84 | num_flush = min_not_zero(num_flush, nvdimm->num_flush); |
e5ae3b25 DW |
85 | if (!nvdimm->num_flush) |
86 | continue; | |
87 | flush_data_size += nvdimm->num_flush * sizeof(void *); | |
88 | } | |
89 | nvdimm_bus_unlock(&nd_region->dev); | |
90 | ||
91 | ndrd = devm_kzalloc(dev, sizeof(*ndrd) + flush_data_size, GFP_KERNEL); | |
92 | if (!ndrd) | |
93 | return -ENOMEM; | |
94 | dev_set_drvdata(dev, ndrd); | |
95 | ||
595c7307 DW |
96 | if (!num_flush) |
97 | return 0; | |
98 | ||
99 | ndrd->hints_shift = ilog2(num_flush); | |
e5ae3b25 DW |
100 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
101 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
102 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
103 | int rc = nvdimm_map_flush(&nd_region->dev, nvdimm, i, ndrd); | |
104 | ||
105 | if (rc) | |
106 | return rc; | |
107 | } | |
108 | ||
db58028e DJ |
109 | /* |
110 | * Clear out entries that are duplicates. This should prevent the | |
111 | * extra flushings. | |
112 | */ | |
113 | for (i = 0; i < nd_region->ndr_mappings - 1; i++) { | |
114 | /* ignore if NULL already */ | |
115 | if (!ndrd_get_flush_wpq(ndrd, i, 0)) | |
116 | continue; | |
117 | ||
118 | for (j = i + 1; j < nd_region->ndr_mappings; j++) | |
119 | if (ndrd_get_flush_wpq(ndrd, i, 0) == | |
120 | ndrd_get_flush_wpq(ndrd, j, 0)) | |
121 | ndrd_set_flush_wpq(ndrd, j, 0, NULL); | |
122 | } | |
123 | ||
e5ae3b25 DW |
124 | return 0; |
125 | } | |
126 | ||
1f7df6f8 DW |
127 | static void nd_region_release(struct device *dev) |
128 | { | |
129 | struct nd_region *nd_region = to_nd_region(dev); | |
130 | u16 i; | |
131 | ||
132 | for (i = 0; i < nd_region->ndr_mappings; i++) { | |
133 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
134 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
135 | ||
136 | put_device(&nvdimm->dev); | |
137 | } | |
5212e11f | 138 | free_percpu(nd_region->lane); |
1f7df6f8 | 139 | ida_simple_remove(®ion_ida, nd_region->id); |
047fc8a1 RZ |
140 | if (is_nd_blk(dev)) |
141 | kfree(to_nd_blk_region(dev)); | |
142 | else | |
143 | kfree(nd_region); | |
1f7df6f8 DW |
144 | } |
145 | ||
146 | static struct device_type nd_blk_device_type = { | |
147 | .name = "nd_blk", | |
148 | .release = nd_region_release, | |
149 | }; | |
150 | ||
151 | static struct device_type nd_pmem_device_type = { | |
152 | .name = "nd_pmem", | |
153 | .release = nd_region_release, | |
154 | }; | |
155 | ||
156 | static struct device_type nd_volatile_device_type = { | |
157 | .name = "nd_volatile", | |
158 | .release = nd_region_release, | |
159 | }; | |
160 | ||
3d88002e | 161 | bool is_nd_pmem(struct device *dev) |
1f7df6f8 DW |
162 | { |
163 | return dev ? dev->type == &nd_pmem_device_type : false; | |
164 | } | |
165 | ||
3d88002e DW |
166 | bool is_nd_blk(struct device *dev) |
167 | { | |
168 | return dev ? dev->type == &nd_blk_device_type : false; | |
169 | } | |
170 | ||
c9e582aa DW |
171 | bool is_nd_volatile(struct device *dev) |
172 | { | |
173 | return dev ? dev->type == &nd_volatile_device_type : false; | |
174 | } | |
175 | ||
1f7df6f8 DW |
176 | struct nd_region *to_nd_region(struct device *dev) |
177 | { | |
178 | struct nd_region *nd_region = container_of(dev, struct nd_region, dev); | |
179 | ||
180 | WARN_ON(dev->type->release != nd_region_release); | |
181 | return nd_region; | |
182 | } | |
183 | EXPORT_SYMBOL_GPL(to_nd_region); | |
184 | ||
243f29fe DW |
185 | struct device *nd_region_dev(struct nd_region *nd_region) |
186 | { | |
187 | if (!nd_region) | |
188 | return NULL; | |
189 | return &nd_region->dev; | |
190 | } | |
191 | EXPORT_SYMBOL_GPL(nd_region_dev); | |
192 | ||
047fc8a1 RZ |
193 | struct nd_blk_region *to_nd_blk_region(struct device *dev) |
194 | { | |
195 | struct nd_region *nd_region = to_nd_region(dev); | |
196 | ||
197 | WARN_ON(!is_nd_blk(dev)); | |
198 | return container_of(nd_region, struct nd_blk_region, nd_region); | |
199 | } | |
200 | EXPORT_SYMBOL_GPL(to_nd_blk_region); | |
201 | ||
202 | void *nd_region_provider_data(struct nd_region *nd_region) | |
203 | { | |
204 | return nd_region->provider_data; | |
205 | } | |
206 | EXPORT_SYMBOL_GPL(nd_region_provider_data); | |
207 | ||
208 | void *nd_blk_region_provider_data(struct nd_blk_region *ndbr) | |
209 | { | |
210 | return ndbr->blk_provider_data; | |
211 | } | |
212 | EXPORT_SYMBOL_GPL(nd_blk_region_provider_data); | |
213 | ||
214 | void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data) | |
215 | { | |
216 | ndbr->blk_provider_data = data; | |
217 | } | |
218 | EXPORT_SYMBOL_GPL(nd_blk_region_set_provider_data); | |
219 | ||
3d88002e DW |
220 | /** |
221 | * nd_region_to_nstype() - region to an integer namespace type | |
222 | * @nd_region: region-device to interrogate | |
223 | * | |
224 | * This is the 'nstype' attribute of a region as well, an input to the | |
225 | * MODALIAS for namespace devices, and bit number for a nvdimm_bus to match | |
226 | * namespace devices with namespace drivers. | |
227 | */ | |
228 | int nd_region_to_nstype(struct nd_region *nd_region) | |
229 | { | |
c9e582aa | 230 | if (is_memory(&nd_region->dev)) { |
3d88002e DW |
231 | u16 i, alias; |
232 | ||
233 | for (i = 0, alias = 0; i < nd_region->ndr_mappings; i++) { | |
234 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
235 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
236 | ||
8f078b38 | 237 | if (test_bit(NDD_ALIASING, &nvdimm->flags)) |
3d88002e DW |
238 | alias++; |
239 | } | |
240 | if (alias) | |
241 | return ND_DEVICE_NAMESPACE_PMEM; | |
242 | else | |
243 | return ND_DEVICE_NAMESPACE_IO; | |
244 | } else if (is_nd_blk(&nd_region->dev)) { | |
245 | return ND_DEVICE_NAMESPACE_BLK; | |
246 | } | |
247 | ||
248 | return 0; | |
249 | } | |
bf9bccc1 DW |
250 | EXPORT_SYMBOL(nd_region_to_nstype); |
251 | ||
1f7df6f8 DW |
252 | static ssize_t size_show(struct device *dev, |
253 | struct device_attribute *attr, char *buf) | |
254 | { | |
255 | struct nd_region *nd_region = to_nd_region(dev); | |
256 | unsigned long long size = 0; | |
257 | ||
c9e582aa | 258 | if (is_memory(dev)) { |
1f7df6f8 DW |
259 | size = nd_region->ndr_size; |
260 | } else if (nd_region->ndr_mappings == 1) { | |
261 | struct nd_mapping *nd_mapping = &nd_region->mapping[0]; | |
262 | ||
263 | size = nd_mapping->size; | |
264 | } | |
265 | ||
266 | return sprintf(buf, "%llu\n", size); | |
267 | } | |
268 | static DEVICE_ATTR_RO(size); | |
269 | ||
ab630891 DW |
270 | static ssize_t deep_flush_show(struct device *dev, |
271 | struct device_attribute *attr, char *buf) | |
272 | { | |
273 | struct nd_region *nd_region = to_nd_region(dev); | |
274 | ||
275 | /* | |
276 | * NOTE: in the nvdimm_has_flush() error case this attribute is | |
277 | * not visible. | |
278 | */ | |
279 | return sprintf(buf, "%d\n", nvdimm_has_flush(nd_region)); | |
280 | } | |
281 | ||
282 | static ssize_t deep_flush_store(struct device *dev, struct device_attribute *attr, | |
283 | const char *buf, size_t len) | |
284 | { | |
285 | bool flush; | |
286 | int rc = strtobool(buf, &flush); | |
287 | struct nd_region *nd_region = to_nd_region(dev); | |
288 | ||
289 | if (rc) | |
290 | return rc; | |
291 | if (!flush) | |
292 | return -EINVAL; | |
293 | nvdimm_flush(nd_region); | |
294 | ||
295 | return len; | |
296 | } | |
297 | static DEVICE_ATTR_RW(deep_flush); | |
298 | ||
1f7df6f8 DW |
299 | static ssize_t mappings_show(struct device *dev, |
300 | struct device_attribute *attr, char *buf) | |
301 | { | |
302 | struct nd_region *nd_region = to_nd_region(dev); | |
303 | ||
304 | return sprintf(buf, "%d\n", nd_region->ndr_mappings); | |
305 | } | |
306 | static DEVICE_ATTR_RO(mappings); | |
307 | ||
3d88002e DW |
308 | static ssize_t nstype_show(struct device *dev, |
309 | struct device_attribute *attr, char *buf) | |
310 | { | |
311 | struct nd_region *nd_region = to_nd_region(dev); | |
312 | ||
313 | return sprintf(buf, "%d\n", nd_region_to_nstype(nd_region)); | |
314 | } | |
315 | static DEVICE_ATTR_RO(nstype); | |
316 | ||
eaf96153 DW |
317 | static ssize_t set_cookie_show(struct device *dev, |
318 | struct device_attribute *attr, char *buf) | |
319 | { | |
320 | struct nd_region *nd_region = to_nd_region(dev); | |
321 | struct nd_interleave_set *nd_set = nd_region->nd_set; | |
c12c48ce | 322 | ssize_t rc = 0; |
eaf96153 | 323 | |
c9e582aa | 324 | if (is_memory(dev) && nd_set) |
eaf96153 DW |
325 | /* pass, should be precluded by region_visible */; |
326 | else | |
327 | return -ENXIO; | |
328 | ||
c12c48ce DW |
329 | /* |
330 | * The cookie to show depends on which specification of the | |
331 | * labels we are using. If there are not labels then default to | |
332 | * the v1.1 namespace label cookie definition. To read all this | |
333 | * data we need to wait for probing to settle. | |
334 | */ | |
335 | device_lock(dev); | |
336 | nvdimm_bus_lock(dev); | |
337 | wait_nvdimm_bus_probe_idle(dev); | |
338 | if (nd_region->ndr_mappings) { | |
339 | struct nd_mapping *nd_mapping = &nd_region->mapping[0]; | |
340 | struct nvdimm_drvdata *ndd = to_ndd(nd_mapping); | |
341 | ||
342 | if (ndd) { | |
343 | struct nd_namespace_index *nsindex; | |
344 | ||
345 | nsindex = to_namespace_index(ndd, ndd->ns_current); | |
346 | rc = sprintf(buf, "%#llx\n", | |
347 | nd_region_interleave_set_cookie(nd_region, | |
348 | nsindex)); | |
349 | } | |
350 | } | |
351 | nvdimm_bus_unlock(dev); | |
352 | device_unlock(dev); | |
353 | ||
354 | if (rc) | |
355 | return rc; | |
356 | return sprintf(buf, "%#llx\n", nd_set->cookie1); | |
eaf96153 DW |
357 | } |
358 | static DEVICE_ATTR_RO(set_cookie); | |
359 | ||
bf9bccc1 DW |
360 | resource_size_t nd_region_available_dpa(struct nd_region *nd_region) |
361 | { | |
362 | resource_size_t blk_max_overlap = 0, available, overlap; | |
363 | int i; | |
364 | ||
365 | WARN_ON(!is_nvdimm_bus_locked(&nd_region->dev)); | |
366 | ||
367 | retry: | |
368 | available = 0; | |
369 | overlap = blk_max_overlap; | |
370 | for (i = 0; i < nd_region->ndr_mappings; i++) { | |
371 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
372 | struct nvdimm_drvdata *ndd = to_ndd(nd_mapping); | |
373 | ||
374 | /* if a dimm is disabled the available capacity is zero */ | |
375 | if (!ndd) | |
376 | return 0; | |
377 | ||
c9e582aa | 378 | if (is_memory(&nd_region->dev)) { |
bf9bccc1 DW |
379 | available += nd_pmem_available_dpa(nd_region, |
380 | nd_mapping, &overlap); | |
381 | if (overlap > blk_max_overlap) { | |
382 | blk_max_overlap = overlap; | |
383 | goto retry; | |
384 | } | |
a1f3e4d6 DW |
385 | } else if (is_nd_blk(&nd_region->dev)) |
386 | available += nd_blk_available_dpa(nd_region); | |
bf9bccc1 DW |
387 | } |
388 | ||
389 | return available; | |
390 | } | |
391 | ||
12e3129e KB |
392 | resource_size_t nd_region_allocatable_dpa(struct nd_region *nd_region) |
393 | { | |
394 | resource_size_t available = 0; | |
395 | int i; | |
396 | ||
397 | if (is_memory(&nd_region->dev)) | |
398 | available = PHYS_ADDR_MAX; | |
399 | ||
400 | WARN_ON(!is_nvdimm_bus_locked(&nd_region->dev)); | |
401 | for (i = 0; i < nd_region->ndr_mappings; i++) { | |
402 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
403 | ||
404 | if (is_memory(&nd_region->dev)) | |
405 | available = min(available, | |
406 | nd_pmem_max_contiguous_dpa(nd_region, | |
407 | nd_mapping)); | |
408 | else if (is_nd_blk(&nd_region->dev)) | |
409 | available += nd_blk_available_dpa(nd_region); | |
410 | } | |
411 | if (is_memory(&nd_region->dev)) | |
412 | return available * nd_region->ndr_mappings; | |
413 | return available; | |
414 | } | |
415 | ||
bf9bccc1 DW |
416 | static ssize_t available_size_show(struct device *dev, |
417 | struct device_attribute *attr, char *buf) | |
418 | { | |
419 | struct nd_region *nd_region = to_nd_region(dev); | |
420 | unsigned long long available = 0; | |
421 | ||
422 | /* | |
423 | * Flush in-flight updates and grab a snapshot of the available | |
424 | * size. Of course, this value is potentially invalidated the | |
425 | * memory nvdimm_bus_lock() is dropped, but that's userspace's | |
426 | * problem to not race itself. | |
427 | */ | |
428 | nvdimm_bus_lock(dev); | |
429 | wait_nvdimm_bus_probe_idle(dev); | |
430 | available = nd_region_available_dpa(nd_region); | |
431 | nvdimm_bus_unlock(dev); | |
432 | ||
433 | return sprintf(buf, "%llu\n", available); | |
434 | } | |
435 | static DEVICE_ATTR_RO(available_size); | |
436 | ||
1e687220 KB |
437 | static ssize_t max_available_extent_show(struct device *dev, |
438 | struct device_attribute *attr, char *buf) | |
439 | { | |
440 | struct nd_region *nd_region = to_nd_region(dev); | |
441 | unsigned long long available = 0; | |
442 | ||
443 | nvdimm_bus_lock(dev); | |
444 | wait_nvdimm_bus_probe_idle(dev); | |
445 | available = nd_region_allocatable_dpa(nd_region); | |
446 | nvdimm_bus_unlock(dev); | |
447 | ||
448 | return sprintf(buf, "%llu\n", available); | |
449 | } | |
450 | static DEVICE_ATTR_RO(max_available_extent); | |
451 | ||
3d88002e DW |
452 | static ssize_t init_namespaces_show(struct device *dev, |
453 | struct device_attribute *attr, char *buf) | |
454 | { | |
e5ae3b25 | 455 | struct nd_region_data *ndrd = dev_get_drvdata(dev); |
3d88002e DW |
456 | ssize_t rc; |
457 | ||
458 | nvdimm_bus_lock(dev); | |
e5ae3b25 DW |
459 | if (ndrd) |
460 | rc = sprintf(buf, "%d/%d\n", ndrd->ns_active, ndrd->ns_count); | |
3d88002e DW |
461 | else |
462 | rc = -ENXIO; | |
463 | nvdimm_bus_unlock(dev); | |
464 | ||
465 | return rc; | |
466 | } | |
467 | static DEVICE_ATTR_RO(init_namespaces); | |
468 | ||
bf9bccc1 DW |
469 | static ssize_t namespace_seed_show(struct device *dev, |
470 | struct device_attribute *attr, char *buf) | |
471 | { | |
472 | struct nd_region *nd_region = to_nd_region(dev); | |
473 | ssize_t rc; | |
474 | ||
475 | nvdimm_bus_lock(dev); | |
476 | if (nd_region->ns_seed) | |
477 | rc = sprintf(buf, "%s\n", dev_name(nd_region->ns_seed)); | |
478 | else | |
479 | rc = sprintf(buf, "\n"); | |
480 | nvdimm_bus_unlock(dev); | |
481 | return rc; | |
482 | } | |
483 | static DEVICE_ATTR_RO(namespace_seed); | |
484 | ||
8c2f7e86 DW |
485 | static ssize_t btt_seed_show(struct device *dev, |
486 | struct device_attribute *attr, char *buf) | |
487 | { | |
488 | struct nd_region *nd_region = to_nd_region(dev); | |
489 | ssize_t rc; | |
490 | ||
491 | nvdimm_bus_lock(dev); | |
492 | if (nd_region->btt_seed) | |
493 | rc = sprintf(buf, "%s\n", dev_name(nd_region->btt_seed)); | |
494 | else | |
495 | rc = sprintf(buf, "\n"); | |
496 | nvdimm_bus_unlock(dev); | |
497 | ||
498 | return rc; | |
499 | } | |
500 | static DEVICE_ATTR_RO(btt_seed); | |
501 | ||
e1455744 DW |
502 | static ssize_t pfn_seed_show(struct device *dev, |
503 | struct device_attribute *attr, char *buf) | |
504 | { | |
505 | struct nd_region *nd_region = to_nd_region(dev); | |
506 | ssize_t rc; | |
507 | ||
508 | nvdimm_bus_lock(dev); | |
509 | if (nd_region->pfn_seed) | |
510 | rc = sprintf(buf, "%s\n", dev_name(nd_region->pfn_seed)); | |
511 | else | |
512 | rc = sprintf(buf, "\n"); | |
513 | nvdimm_bus_unlock(dev); | |
514 | ||
515 | return rc; | |
516 | } | |
517 | static DEVICE_ATTR_RO(pfn_seed); | |
518 | ||
cd03412a DW |
519 | static ssize_t dax_seed_show(struct device *dev, |
520 | struct device_attribute *attr, char *buf) | |
521 | { | |
522 | struct nd_region *nd_region = to_nd_region(dev); | |
523 | ssize_t rc; | |
524 | ||
525 | nvdimm_bus_lock(dev); | |
526 | if (nd_region->dax_seed) | |
527 | rc = sprintf(buf, "%s\n", dev_name(nd_region->dax_seed)); | |
528 | else | |
529 | rc = sprintf(buf, "\n"); | |
530 | nvdimm_bus_unlock(dev); | |
531 | ||
532 | return rc; | |
533 | } | |
534 | static DEVICE_ATTR_RO(dax_seed); | |
535 | ||
58138820 DW |
536 | static ssize_t read_only_show(struct device *dev, |
537 | struct device_attribute *attr, char *buf) | |
538 | { | |
539 | struct nd_region *nd_region = to_nd_region(dev); | |
540 | ||
541 | return sprintf(buf, "%d\n", nd_region->ro); | |
542 | } | |
543 | ||
544 | static ssize_t read_only_store(struct device *dev, | |
545 | struct device_attribute *attr, const char *buf, size_t len) | |
546 | { | |
547 | bool ro; | |
548 | int rc = strtobool(buf, &ro); | |
549 | struct nd_region *nd_region = to_nd_region(dev); | |
550 | ||
551 | if (rc) | |
552 | return rc; | |
553 | ||
554 | nd_region->ro = ro; | |
555 | return len; | |
556 | } | |
557 | static DEVICE_ATTR_RW(read_only); | |
558 | ||
23f49844 | 559 | static ssize_t region_badblocks_show(struct device *dev, |
6a6bef90 DJ |
560 | struct device_attribute *attr, char *buf) |
561 | { | |
562 | struct nd_region *nd_region = to_nd_region(dev); | |
5d394eee | 563 | ssize_t rc; |
6a6bef90 | 564 | |
5d394eee DW |
565 | device_lock(dev); |
566 | if (dev->driver) | |
567 | rc = badblocks_show(&nd_region->bb, buf, 0); | |
568 | else | |
569 | rc = -ENXIO; | |
570 | device_unlock(dev); | |
23f49844 | 571 | |
5d394eee DW |
572 | return rc; |
573 | } | |
23f49844 | 574 | static DEVICE_ATTR(badblocks, 0444, region_badblocks_show, NULL); |
6a6bef90 | 575 | |
802f4be6 DJ |
576 | static ssize_t resource_show(struct device *dev, |
577 | struct device_attribute *attr, char *buf) | |
578 | { | |
579 | struct nd_region *nd_region = to_nd_region(dev); | |
580 | ||
581 | return sprintf(buf, "%#llx\n", nd_region->ndr_start); | |
582 | } | |
583 | static DEVICE_ATTR_RO(resource); | |
584 | ||
96c3a239 DJ |
585 | static ssize_t persistence_domain_show(struct device *dev, |
586 | struct device_attribute *attr, char *buf) | |
587 | { | |
588 | struct nd_region *nd_region = to_nd_region(dev); | |
96c3a239 | 589 | |
fe9a552e DW |
590 | if (test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags)) |
591 | return sprintf(buf, "cpu_cache\n"); | |
592 | else if (test_bit(ND_REGION_PERSIST_MEMCTRL, &nd_region->flags)) | |
593 | return sprintf(buf, "memory_controller\n"); | |
594 | else | |
595 | return sprintf(buf, "\n"); | |
96c3a239 DJ |
596 | } |
597 | static DEVICE_ATTR_RO(persistence_domain); | |
598 | ||
1f7df6f8 DW |
599 | static struct attribute *nd_region_attributes[] = { |
600 | &dev_attr_size.attr, | |
3d88002e | 601 | &dev_attr_nstype.attr, |
1f7df6f8 | 602 | &dev_attr_mappings.attr, |
8c2f7e86 | 603 | &dev_attr_btt_seed.attr, |
e1455744 | 604 | &dev_attr_pfn_seed.attr, |
cd03412a | 605 | &dev_attr_dax_seed.attr, |
ab630891 | 606 | &dev_attr_deep_flush.attr, |
58138820 | 607 | &dev_attr_read_only.attr, |
eaf96153 | 608 | &dev_attr_set_cookie.attr, |
bf9bccc1 | 609 | &dev_attr_available_size.attr, |
1e687220 | 610 | &dev_attr_max_available_extent.attr, |
bf9bccc1 | 611 | &dev_attr_namespace_seed.attr, |
3d88002e | 612 | &dev_attr_init_namespaces.attr, |
23f49844 | 613 | &dev_attr_badblocks.attr, |
802f4be6 | 614 | &dev_attr_resource.attr, |
96c3a239 | 615 | &dev_attr_persistence_domain.attr, |
1f7df6f8 DW |
616 | NULL, |
617 | }; | |
618 | ||
eaf96153 DW |
619 | static umode_t region_visible(struct kobject *kobj, struct attribute *a, int n) |
620 | { | |
621 | struct device *dev = container_of(kobj, typeof(*dev), kobj); | |
622 | struct nd_region *nd_region = to_nd_region(dev); | |
623 | struct nd_interleave_set *nd_set = nd_region->nd_set; | |
bf9bccc1 | 624 | int type = nd_region_to_nstype(nd_region); |
eaf96153 | 625 | |
c9e582aa | 626 | if (!is_memory(dev) && a == &dev_attr_pfn_seed.attr) |
6bb691ac DK |
627 | return 0; |
628 | ||
c9e582aa | 629 | if (!is_memory(dev) && a == &dev_attr_dax_seed.attr) |
cd03412a DW |
630 | return 0; |
631 | ||
23f49844 | 632 | if (!is_nd_pmem(dev) && a == &dev_attr_badblocks.attr) |
6a6bef90 DJ |
633 | return 0; |
634 | ||
b8ff981f DW |
635 | if (a == &dev_attr_resource.attr) { |
636 | if (is_nd_pmem(dev)) | |
637 | return 0400; | |
638 | else | |
639 | return 0; | |
640 | } | |
802f4be6 | 641 | |
ab630891 DW |
642 | if (a == &dev_attr_deep_flush.attr) { |
643 | int has_flush = nvdimm_has_flush(nd_region); | |
644 | ||
645 | if (has_flush == 1) | |
646 | return a->mode; | |
647 | else if (has_flush == 0) | |
648 | return 0444; | |
649 | else | |
650 | return 0; | |
651 | } | |
652 | ||
896196dc DW |
653 | if (a == &dev_attr_persistence_domain.attr) { |
654 | if ((nd_region->flags & (BIT(ND_REGION_PERSIST_CACHE) | |
655 | | BIT(ND_REGION_PERSIST_MEMCTRL))) == 0) | |
656 | return 0; | |
657 | return a->mode; | |
658 | } | |
659 | ||
bf9bccc1 DW |
660 | if (a != &dev_attr_set_cookie.attr |
661 | && a != &dev_attr_available_size.attr) | |
eaf96153 DW |
662 | return a->mode; |
663 | ||
bf9bccc1 DW |
664 | if ((type == ND_DEVICE_NAMESPACE_PMEM |
665 | || type == ND_DEVICE_NAMESPACE_BLK) | |
666 | && a == &dev_attr_available_size.attr) | |
667 | return a->mode; | |
c9e582aa | 668 | else if (is_memory(dev) && nd_set) |
bf9bccc1 | 669 | return a->mode; |
eaf96153 DW |
670 | |
671 | return 0; | |
672 | } | |
673 | ||
1f7df6f8 DW |
674 | struct attribute_group nd_region_attribute_group = { |
675 | .attrs = nd_region_attributes, | |
eaf96153 | 676 | .is_visible = region_visible, |
1f7df6f8 DW |
677 | }; |
678 | EXPORT_SYMBOL_GPL(nd_region_attribute_group); | |
679 | ||
c12c48ce DW |
680 | u64 nd_region_interleave_set_cookie(struct nd_region *nd_region, |
681 | struct nd_namespace_index *nsindex) | |
bf9bccc1 DW |
682 | { |
683 | struct nd_interleave_set *nd_set = nd_region->nd_set; | |
684 | ||
c12c48ce DW |
685 | if (!nd_set) |
686 | return 0; | |
687 | ||
688 | if (nsindex && __le16_to_cpu(nsindex->major) == 1 | |
689 | && __le16_to_cpu(nsindex->minor) == 1) | |
690 | return nd_set->cookie1; | |
691 | return nd_set->cookie2; | |
bf9bccc1 DW |
692 | } |
693 | ||
86ef58a4 DW |
694 | u64 nd_region_interleave_set_altcookie(struct nd_region *nd_region) |
695 | { | |
696 | struct nd_interleave_set *nd_set = nd_region->nd_set; | |
697 | ||
698 | if (nd_set) | |
699 | return nd_set->altcookie; | |
700 | return 0; | |
701 | } | |
702 | ||
ae8219f1 DW |
703 | void nd_mapping_free_labels(struct nd_mapping *nd_mapping) |
704 | { | |
705 | struct nd_label_ent *label_ent, *e; | |
706 | ||
9cf8bd52 | 707 | lockdep_assert_held(&nd_mapping->lock); |
ae8219f1 DW |
708 | list_for_each_entry_safe(label_ent, e, &nd_mapping->labels, list) { |
709 | list_del(&label_ent->list); | |
710 | kfree(label_ent); | |
711 | } | |
712 | } | |
713 | ||
eaf96153 DW |
714 | /* |
715 | * Upon successful probe/remove, take/release a reference on the | |
8c2f7e86 | 716 | * associated interleave set (if present), and plant new btt + namespace |
047fc8a1 RZ |
717 | * seeds. Also, on the removal of a BLK region, notify the provider to |
718 | * disable the region. | |
eaf96153 DW |
719 | */ |
720 | static void nd_region_notify_driver_action(struct nvdimm_bus *nvdimm_bus, | |
721 | struct device *dev, bool probe) | |
722 | { | |
8c2f7e86 DW |
723 | struct nd_region *nd_region; |
724 | ||
c9e582aa | 725 | if (!probe && is_nd_region(dev)) { |
eaf96153 DW |
726 | int i; |
727 | ||
8c2f7e86 | 728 | nd_region = to_nd_region(dev); |
eaf96153 DW |
729 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
730 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
bf9bccc1 | 731 | struct nvdimm_drvdata *ndd = nd_mapping->ndd; |
eaf96153 DW |
732 | struct nvdimm *nvdimm = nd_mapping->nvdimm; |
733 | ||
ae8219f1 DW |
734 | mutex_lock(&nd_mapping->lock); |
735 | nd_mapping_free_labels(nd_mapping); | |
736 | mutex_unlock(&nd_mapping->lock); | |
737 | ||
bf9bccc1 DW |
738 | put_ndd(ndd); |
739 | nd_mapping->ndd = NULL; | |
047fc8a1 RZ |
740 | if (ndd) |
741 | atomic_dec(&nvdimm->busy); | |
eaf96153 | 742 | } |
8c2f7e86 | 743 | } |
c9e582aa | 744 | if (dev->parent && is_nd_region(dev->parent) && probe) { |
8c2f7e86 | 745 | nd_region = to_nd_region(dev->parent); |
1b40e09a DW |
746 | nvdimm_bus_lock(dev); |
747 | if (nd_region->ns_seed == dev) | |
98a29c39 | 748 | nd_region_create_ns_seed(nd_region); |
1b40e09a | 749 | nvdimm_bus_unlock(dev); |
eaf96153 | 750 | } |
8c2f7e86 | 751 | if (is_nd_btt(dev) && probe) { |
8ca24353 DW |
752 | struct nd_btt *nd_btt = to_nd_btt(dev); |
753 | ||
8c2f7e86 DW |
754 | nd_region = to_nd_region(dev->parent); |
755 | nvdimm_bus_lock(dev); | |
756 | if (nd_region->btt_seed == dev) | |
757 | nd_region_create_btt_seed(nd_region); | |
98a29c39 DW |
758 | if (nd_region->ns_seed == &nd_btt->ndns->dev) |
759 | nd_region_create_ns_seed(nd_region); | |
8c2f7e86 DW |
760 | nvdimm_bus_unlock(dev); |
761 | } | |
2dc43331 | 762 | if (is_nd_pfn(dev) && probe) { |
98a29c39 DW |
763 | struct nd_pfn *nd_pfn = to_nd_pfn(dev); |
764 | ||
2dc43331 DW |
765 | nd_region = to_nd_region(dev->parent); |
766 | nvdimm_bus_lock(dev); | |
767 | if (nd_region->pfn_seed == dev) | |
768 | nd_region_create_pfn_seed(nd_region); | |
98a29c39 DW |
769 | if (nd_region->ns_seed == &nd_pfn->ndns->dev) |
770 | nd_region_create_ns_seed(nd_region); | |
2dc43331 DW |
771 | nvdimm_bus_unlock(dev); |
772 | } | |
cd03412a | 773 | if (is_nd_dax(dev) && probe) { |
98a29c39 DW |
774 | struct nd_dax *nd_dax = to_nd_dax(dev); |
775 | ||
cd03412a DW |
776 | nd_region = to_nd_region(dev->parent); |
777 | nvdimm_bus_lock(dev); | |
778 | if (nd_region->dax_seed == dev) | |
779 | nd_region_create_dax_seed(nd_region); | |
98a29c39 DW |
780 | if (nd_region->ns_seed == &nd_dax->nd_pfn.ndns->dev) |
781 | nd_region_create_ns_seed(nd_region); | |
cd03412a DW |
782 | nvdimm_bus_unlock(dev); |
783 | } | |
eaf96153 DW |
784 | } |
785 | ||
786 | void nd_region_probe_success(struct nvdimm_bus *nvdimm_bus, struct device *dev) | |
787 | { | |
788 | nd_region_notify_driver_action(nvdimm_bus, dev, true); | |
789 | } | |
790 | ||
791 | void nd_region_disable(struct nvdimm_bus *nvdimm_bus, struct device *dev) | |
792 | { | |
793 | nd_region_notify_driver_action(nvdimm_bus, dev, false); | |
794 | } | |
795 | ||
1f7df6f8 DW |
796 | static ssize_t mappingN(struct device *dev, char *buf, int n) |
797 | { | |
798 | struct nd_region *nd_region = to_nd_region(dev); | |
799 | struct nd_mapping *nd_mapping; | |
800 | struct nvdimm *nvdimm; | |
801 | ||
802 | if (n >= nd_region->ndr_mappings) | |
803 | return -ENXIO; | |
804 | nd_mapping = &nd_region->mapping[n]; | |
805 | nvdimm = nd_mapping->nvdimm; | |
806 | ||
401c0a19 DW |
807 | return sprintf(buf, "%s,%llu,%llu,%d\n", dev_name(&nvdimm->dev), |
808 | nd_mapping->start, nd_mapping->size, | |
809 | nd_mapping->position); | |
1f7df6f8 DW |
810 | } |
811 | ||
812 | #define REGION_MAPPING(idx) \ | |
813 | static ssize_t mapping##idx##_show(struct device *dev, \ | |
814 | struct device_attribute *attr, char *buf) \ | |
815 | { \ | |
816 | return mappingN(dev, buf, idx); \ | |
817 | } \ | |
818 | static DEVICE_ATTR_RO(mapping##idx) | |
819 | ||
820 | /* | |
821 | * 32 should be enough for a while, even in the presence of socket | |
822 | * interleave a 32-way interleave set is a degenerate case. | |
823 | */ | |
824 | REGION_MAPPING(0); | |
825 | REGION_MAPPING(1); | |
826 | REGION_MAPPING(2); | |
827 | REGION_MAPPING(3); | |
828 | REGION_MAPPING(4); | |
829 | REGION_MAPPING(5); | |
830 | REGION_MAPPING(6); | |
831 | REGION_MAPPING(7); | |
832 | REGION_MAPPING(8); | |
833 | REGION_MAPPING(9); | |
834 | REGION_MAPPING(10); | |
835 | REGION_MAPPING(11); | |
836 | REGION_MAPPING(12); | |
837 | REGION_MAPPING(13); | |
838 | REGION_MAPPING(14); | |
839 | REGION_MAPPING(15); | |
840 | REGION_MAPPING(16); | |
841 | REGION_MAPPING(17); | |
842 | REGION_MAPPING(18); | |
843 | REGION_MAPPING(19); | |
844 | REGION_MAPPING(20); | |
845 | REGION_MAPPING(21); | |
846 | REGION_MAPPING(22); | |
847 | REGION_MAPPING(23); | |
848 | REGION_MAPPING(24); | |
849 | REGION_MAPPING(25); | |
850 | REGION_MAPPING(26); | |
851 | REGION_MAPPING(27); | |
852 | REGION_MAPPING(28); | |
853 | REGION_MAPPING(29); | |
854 | REGION_MAPPING(30); | |
855 | REGION_MAPPING(31); | |
856 | ||
857 | static umode_t mapping_visible(struct kobject *kobj, struct attribute *a, int n) | |
858 | { | |
859 | struct device *dev = container_of(kobj, struct device, kobj); | |
860 | struct nd_region *nd_region = to_nd_region(dev); | |
861 | ||
862 | if (n < nd_region->ndr_mappings) | |
863 | return a->mode; | |
864 | return 0; | |
865 | } | |
866 | ||
867 | static struct attribute *mapping_attributes[] = { | |
868 | &dev_attr_mapping0.attr, | |
869 | &dev_attr_mapping1.attr, | |
870 | &dev_attr_mapping2.attr, | |
871 | &dev_attr_mapping3.attr, | |
872 | &dev_attr_mapping4.attr, | |
873 | &dev_attr_mapping5.attr, | |
874 | &dev_attr_mapping6.attr, | |
875 | &dev_attr_mapping7.attr, | |
876 | &dev_attr_mapping8.attr, | |
877 | &dev_attr_mapping9.attr, | |
878 | &dev_attr_mapping10.attr, | |
879 | &dev_attr_mapping11.attr, | |
880 | &dev_attr_mapping12.attr, | |
881 | &dev_attr_mapping13.attr, | |
882 | &dev_attr_mapping14.attr, | |
883 | &dev_attr_mapping15.attr, | |
884 | &dev_attr_mapping16.attr, | |
885 | &dev_attr_mapping17.attr, | |
886 | &dev_attr_mapping18.attr, | |
887 | &dev_attr_mapping19.attr, | |
888 | &dev_attr_mapping20.attr, | |
889 | &dev_attr_mapping21.attr, | |
890 | &dev_attr_mapping22.attr, | |
891 | &dev_attr_mapping23.attr, | |
892 | &dev_attr_mapping24.attr, | |
893 | &dev_attr_mapping25.attr, | |
894 | &dev_attr_mapping26.attr, | |
895 | &dev_attr_mapping27.attr, | |
896 | &dev_attr_mapping28.attr, | |
897 | &dev_attr_mapping29.attr, | |
898 | &dev_attr_mapping30.attr, | |
899 | &dev_attr_mapping31.attr, | |
900 | NULL, | |
901 | }; | |
902 | ||
903 | struct attribute_group nd_mapping_attribute_group = { | |
904 | .is_visible = mapping_visible, | |
905 | .attrs = mapping_attributes, | |
906 | }; | |
907 | EXPORT_SYMBOL_GPL(nd_mapping_attribute_group); | |
908 | ||
047fc8a1 | 909 | int nd_blk_region_init(struct nd_region *nd_region) |
1f7df6f8 | 910 | { |
047fc8a1 RZ |
911 | struct device *dev = &nd_region->dev; |
912 | struct nvdimm_bus *nvdimm_bus = walk_to_nvdimm_bus(dev); | |
913 | ||
914 | if (!is_nd_blk(dev)) | |
915 | return 0; | |
916 | ||
917 | if (nd_region->ndr_mappings < 1) { | |
d5d51fec | 918 | dev_dbg(dev, "invalid BLK region\n"); |
047fc8a1 RZ |
919 | return -ENXIO; |
920 | } | |
921 | ||
922 | return to_nd_blk_region(dev)->enable(nvdimm_bus, dev); | |
1f7df6f8 | 923 | } |
1f7df6f8 | 924 | |
5212e11f VV |
925 | /** |
926 | * nd_region_acquire_lane - allocate and lock a lane | |
927 | * @nd_region: region id and number of lanes possible | |
928 | * | |
929 | * A lane correlates to a BLK-data-window and/or a log slot in the BTT. | |
930 | * We optimize for the common case where there are 256 lanes, one | |
931 | * per-cpu. For larger systems we need to lock to share lanes. For now | |
932 | * this implementation assumes the cost of maintaining an allocator for | |
933 | * free lanes is on the order of the lock hold time, so it implements a | |
934 | * static lane = cpu % num_lanes mapping. | |
935 | * | |
936 | * In the case of a BTT instance on top of a BLK namespace a lane may be | |
937 | * acquired recursively. We lock on the first instance. | |
938 | * | |
939 | * In the case of a BTT instance on top of PMEM, we only acquire a lane | |
940 | * for the BTT metadata updates. | |
941 | */ | |
942 | unsigned int nd_region_acquire_lane(struct nd_region *nd_region) | |
943 | { | |
944 | unsigned int cpu, lane; | |
945 | ||
946 | cpu = get_cpu(); | |
947 | if (nd_region->num_lanes < nr_cpu_ids) { | |
948 | struct nd_percpu_lane *ndl_lock, *ndl_count; | |
949 | ||
950 | lane = cpu % nd_region->num_lanes; | |
951 | ndl_count = per_cpu_ptr(nd_region->lane, cpu); | |
952 | ndl_lock = per_cpu_ptr(nd_region->lane, lane); | |
953 | if (ndl_count->count++ == 0) | |
954 | spin_lock(&ndl_lock->lock); | |
955 | } else | |
956 | lane = cpu; | |
957 | ||
958 | return lane; | |
959 | } | |
960 | EXPORT_SYMBOL(nd_region_acquire_lane); | |
961 | ||
962 | void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane) | |
963 | { | |
964 | if (nd_region->num_lanes < nr_cpu_ids) { | |
965 | unsigned int cpu = get_cpu(); | |
966 | struct nd_percpu_lane *ndl_lock, *ndl_count; | |
967 | ||
968 | ndl_count = per_cpu_ptr(nd_region->lane, cpu); | |
969 | ndl_lock = per_cpu_ptr(nd_region->lane, lane); | |
970 | if (--ndl_count->count == 0) | |
971 | spin_unlock(&ndl_lock->lock); | |
972 | put_cpu(); | |
973 | } | |
974 | put_cpu(); | |
975 | } | |
976 | EXPORT_SYMBOL(nd_region_release_lane); | |
977 | ||
1f7df6f8 DW |
978 | static struct nd_region *nd_region_create(struct nvdimm_bus *nvdimm_bus, |
979 | struct nd_region_desc *ndr_desc, struct device_type *dev_type, | |
980 | const char *caller) | |
981 | { | |
982 | struct nd_region *nd_region; | |
983 | struct device *dev; | |
047fc8a1 | 984 | void *region_buf; |
5212e11f | 985 | unsigned int i; |
58138820 | 986 | int ro = 0; |
1f7df6f8 DW |
987 | |
988 | for (i = 0; i < ndr_desc->num_mappings; i++) { | |
44c462eb DW |
989 | struct nd_mapping_desc *mapping = &ndr_desc->mapping[i]; |
990 | struct nvdimm *nvdimm = mapping->nvdimm; | |
1f7df6f8 | 991 | |
44c462eb | 992 | if ((mapping->start | mapping->size) % SZ_4K) { |
1f7df6f8 DW |
993 | dev_err(&nvdimm_bus->dev, "%s: %s mapping%d is not 4K aligned\n", |
994 | caller, dev_name(&nvdimm->dev), i); | |
995 | ||
996 | return NULL; | |
997 | } | |
58138820 | 998 | |
8f078b38 | 999 | if (test_bit(NDD_UNARMED, &nvdimm->flags)) |
58138820 | 1000 | ro = 1; |
1f7df6f8 DW |
1001 | } |
1002 | ||
047fc8a1 RZ |
1003 | if (dev_type == &nd_blk_device_type) { |
1004 | struct nd_blk_region_desc *ndbr_desc; | |
1005 | struct nd_blk_region *ndbr; | |
1006 | ||
1007 | ndbr_desc = to_blk_region_desc(ndr_desc); | |
1008 | ndbr = kzalloc(sizeof(*ndbr) + sizeof(struct nd_mapping) | |
1009 | * ndr_desc->num_mappings, | |
1010 | GFP_KERNEL); | |
1011 | if (ndbr) { | |
1012 | nd_region = &ndbr->nd_region; | |
1013 | ndbr->enable = ndbr_desc->enable; | |
047fc8a1 RZ |
1014 | ndbr->do_io = ndbr_desc->do_io; |
1015 | } | |
1016 | region_buf = ndbr; | |
1017 | } else { | |
1018 | nd_region = kzalloc(sizeof(struct nd_region) | |
1019 | + sizeof(struct nd_mapping) | |
1020 | * ndr_desc->num_mappings, | |
1021 | GFP_KERNEL); | |
1022 | region_buf = nd_region; | |
1023 | } | |
1024 | ||
1025 | if (!region_buf) | |
1f7df6f8 DW |
1026 | return NULL; |
1027 | nd_region->id = ida_simple_get(®ion_ida, 0, 0, GFP_KERNEL); | |
5212e11f VV |
1028 | if (nd_region->id < 0) |
1029 | goto err_id; | |
1030 | ||
1031 | nd_region->lane = alloc_percpu(struct nd_percpu_lane); | |
1032 | if (!nd_region->lane) | |
1033 | goto err_percpu; | |
1034 | ||
1035 | for (i = 0; i < nr_cpu_ids; i++) { | |
1036 | struct nd_percpu_lane *ndl; | |
1037 | ||
1038 | ndl = per_cpu_ptr(nd_region->lane, i); | |
1039 | spin_lock_init(&ndl->lock); | |
1040 | ndl->count = 0; | |
1f7df6f8 DW |
1041 | } |
1042 | ||
1f7df6f8 | 1043 | for (i = 0; i < ndr_desc->num_mappings; i++) { |
44c462eb DW |
1044 | struct nd_mapping_desc *mapping = &ndr_desc->mapping[i]; |
1045 | struct nvdimm *nvdimm = mapping->nvdimm; | |
1046 | ||
1047 | nd_region->mapping[i].nvdimm = nvdimm; | |
1048 | nd_region->mapping[i].start = mapping->start; | |
1049 | nd_region->mapping[i].size = mapping->size; | |
401c0a19 | 1050 | nd_region->mapping[i].position = mapping->position; |
ae8219f1 DW |
1051 | INIT_LIST_HEAD(&nd_region->mapping[i].labels); |
1052 | mutex_init(&nd_region->mapping[i].lock); | |
1f7df6f8 DW |
1053 | |
1054 | get_device(&nvdimm->dev); | |
1055 | } | |
1056 | nd_region->ndr_mappings = ndr_desc->num_mappings; | |
1057 | nd_region->provider_data = ndr_desc->provider_data; | |
eaf96153 | 1058 | nd_region->nd_set = ndr_desc->nd_set; |
5212e11f | 1059 | nd_region->num_lanes = ndr_desc->num_lanes; |
004f1afb | 1060 | nd_region->flags = ndr_desc->flags; |
58138820 | 1061 | nd_region->ro = ro; |
41d7a6d6 | 1062 | nd_region->numa_node = ndr_desc->numa_node; |
1b40e09a | 1063 | ida_init(&nd_region->ns_ida); |
8c2f7e86 | 1064 | ida_init(&nd_region->btt_ida); |
e1455744 | 1065 | ida_init(&nd_region->pfn_ida); |
cd03412a | 1066 | ida_init(&nd_region->dax_ida); |
1f7df6f8 DW |
1067 | dev = &nd_region->dev; |
1068 | dev_set_name(dev, "region%d", nd_region->id); | |
1069 | dev->parent = &nvdimm_bus->dev; | |
1070 | dev->type = dev_type; | |
1071 | dev->groups = ndr_desc->attr_groups; | |
1ff19f48 | 1072 | dev->of_node = ndr_desc->of_node; |
1f7df6f8 DW |
1073 | nd_region->ndr_size = resource_size(ndr_desc->res); |
1074 | nd_region->ndr_start = ndr_desc->res->start; | |
1075 | nd_device_register(dev); | |
1076 | ||
1077 | return nd_region; | |
5212e11f VV |
1078 | |
1079 | err_percpu: | |
1080 | ida_simple_remove(®ion_ida, nd_region->id); | |
1081 | err_id: | |
047fc8a1 | 1082 | kfree(region_buf); |
5212e11f | 1083 | return NULL; |
1f7df6f8 DW |
1084 | } |
1085 | ||
1086 | struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, | |
1087 | struct nd_region_desc *ndr_desc) | |
1088 | { | |
5212e11f | 1089 | ndr_desc->num_lanes = ND_MAX_LANES; |
1f7df6f8 DW |
1090 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_pmem_device_type, |
1091 | __func__); | |
1092 | } | |
1093 | EXPORT_SYMBOL_GPL(nvdimm_pmem_region_create); | |
1094 | ||
1095 | struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, | |
1096 | struct nd_region_desc *ndr_desc) | |
1097 | { | |
1098 | if (ndr_desc->num_mappings > 1) | |
1099 | return NULL; | |
5212e11f | 1100 | ndr_desc->num_lanes = min(ndr_desc->num_lanes, ND_MAX_LANES); |
1f7df6f8 DW |
1101 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_blk_device_type, |
1102 | __func__); | |
1103 | } | |
1104 | EXPORT_SYMBOL_GPL(nvdimm_blk_region_create); | |
1105 | ||
1106 | struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus, | |
1107 | struct nd_region_desc *ndr_desc) | |
1108 | { | |
5212e11f | 1109 | ndr_desc->num_lanes = ND_MAX_LANES; |
1f7df6f8 DW |
1110 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_volatile_device_type, |
1111 | __func__); | |
1112 | } | |
1113 | EXPORT_SYMBOL_GPL(nvdimm_volatile_region_create); | |
b354aba0 | 1114 | |
f284a4f2 DW |
1115 | /** |
1116 | * nvdimm_flush - flush any posted write queues between the cpu and pmem media | |
1117 | * @nd_region: blk or interleaved pmem region | |
1118 | */ | |
1119 | void nvdimm_flush(struct nd_region *nd_region) | |
1120 | { | |
1121 | struct nd_region_data *ndrd = dev_get_drvdata(&nd_region->dev); | |
0c27af60 DW |
1122 | int i, idx; |
1123 | ||
1124 | /* | |
1125 | * Try to encourage some diversity in flush hint addresses | |
1126 | * across cpus assuming a limited number of flush hints. | |
1127 | */ | |
1128 | idx = this_cpu_read(flush_idx); | |
1129 | idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8)); | |
f284a4f2 DW |
1130 | |
1131 | /* | |
1132 | * The first wmb() is needed to 'sfence' all previous writes | |
1133 | * such that they are architecturally visible for the platform | |
1134 | * buffer flush. Note that we've already arranged for pmem | |
0aed55af DW |
1135 | * writes to avoid the cache via memcpy_flushcache(). The final |
1136 | * wmb() ensures ordering for the NVDIMM flush write. | |
f284a4f2 DW |
1137 | */ |
1138 | wmb(); | |
1139 | for (i = 0; i < nd_region->ndr_mappings; i++) | |
595c7307 DW |
1140 | if (ndrd_get_flush_wpq(ndrd, i, 0)) |
1141 | writeq(1, ndrd_get_flush_wpq(ndrd, i, idx)); | |
f284a4f2 DW |
1142 | wmb(); |
1143 | } | |
1144 | EXPORT_SYMBOL_GPL(nvdimm_flush); | |
1145 | ||
1146 | /** | |
1147 | * nvdimm_has_flush - determine write flushing requirements | |
1148 | * @nd_region: blk or interleaved pmem region | |
1149 | * | |
1150 | * Returns 1 if writes require flushing | |
1151 | * Returns 0 if writes do not require flushing | |
1152 | * Returns -ENXIO if flushing capability can not be determined | |
1153 | */ | |
1154 | int nvdimm_has_flush(struct nd_region *nd_region) | |
1155 | { | |
f284a4f2 DW |
1156 | int i; |
1157 | ||
c00b396e DW |
1158 | /* no nvdimm or pmem api == flushing capability unknown */ |
1159 | if (nd_region->ndr_mappings == 0 | |
1160 | || !IS_ENABLED(CONFIG_ARCH_HAS_PMEM_API)) | |
f284a4f2 DW |
1161 | return -ENXIO; |
1162 | ||
bc042fdf DW |
1163 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
1164 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; | |
1165 | struct nvdimm *nvdimm = nd_mapping->nvdimm; | |
1166 | ||
1167 | /* flush hints present / available */ | |
1168 | if (nvdimm->num_flush) | |
f284a4f2 | 1169 | return 1; |
bc042fdf | 1170 | } |
f284a4f2 DW |
1171 | |
1172 | /* | |
1173 | * The platform defines dimm devices without hints, assume | |
1174 | * platform persistence mechanism like ADR | |
1175 | */ | |
1176 | return 0; | |
1177 | } | |
1178 | EXPORT_SYMBOL_GPL(nvdimm_has_flush); | |
1179 | ||
0b277961 DW |
1180 | int nvdimm_has_cache(struct nd_region *nd_region) |
1181 | { | |
546eb031 RZ |
1182 | return is_nd_pmem(&nd_region->dev) && |
1183 | !test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags); | |
0b277961 DW |
1184 | } |
1185 | EXPORT_SYMBOL_GPL(nvdimm_has_cache); | |
1186 | ||
ae86cbfe DW |
1187 | struct conflict_context { |
1188 | struct nd_region *nd_region; | |
1189 | resource_size_t start, size; | |
1190 | }; | |
1191 | ||
1192 | static int region_conflict(struct device *dev, void *data) | |
1193 | { | |
1194 | struct nd_region *nd_region; | |
1195 | struct conflict_context *ctx = data; | |
1196 | resource_size_t res_end, region_end, region_start; | |
1197 | ||
1198 | if (!is_memory(dev)) | |
1199 | return 0; | |
1200 | ||
1201 | nd_region = to_nd_region(dev); | |
1202 | if (nd_region == ctx->nd_region) | |
1203 | return 0; | |
1204 | ||
1205 | res_end = ctx->start + ctx->size; | |
1206 | region_start = nd_region->ndr_start; | |
1207 | region_end = region_start + nd_region->ndr_size; | |
1208 | if (ctx->start >= region_start && ctx->start < region_end) | |
1209 | return -EBUSY; | |
1210 | if (res_end > region_start && res_end <= region_end) | |
1211 | return -EBUSY; | |
1212 | return 0; | |
1213 | } | |
1214 | ||
1215 | int nd_region_conflict(struct nd_region *nd_region, resource_size_t start, | |
1216 | resource_size_t size) | |
1217 | { | |
1218 | struct nvdimm_bus *nvdimm_bus = walk_to_nvdimm_bus(&nd_region->dev); | |
1219 | struct conflict_context ctx = { | |
1220 | .nd_region = nd_region, | |
1221 | .start = start, | |
1222 | .size = size, | |
1223 | }; | |
1224 | ||
1225 | return device_for_each_child(&nvdimm_bus->dev, &ctx, region_conflict); | |
1226 | } | |
1227 | ||
b354aba0 DW |
1228 | void __exit nd_region_devs_exit(void) |
1229 | { | |
1230 | ida_destroy(®ion_ida); | |
1231 | } |