[linux-block.git] / drivers / ntb / hw / intel / ntb_hw_intel.h

/*
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 *   redistributing this file, you may do so under either license.
 *
 *   GPL LICENSE SUMMARY
 *
 *   Copyright(c) 2012 Intel Corporation. All rights reserved.
 *   Copyright (C) 2015 EMC Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of version 2 of the GNU General Public License as
 *   published by the Free Software Foundation.
 *
 *   BSD LICENSE
 *
 *   Copyright(c) 2012 Intel Corporation. All rights reserved.
 *   Copyright (C) 2015 EMC Corporation. All Rights Reserved.
 *
 *   Redistribution and use in source and binary forms, with or without
 *   modification, are permitted provided that the following conditions
 *   are met:
 *
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copy
 *       notice, this list of conditions and the following disclaimer in
 *       the documentation and/or other materials provided with the
 *       distribution.
 *     * Neither the name of Intel Corporation nor the names of its
 *       contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Intel PCIe NTB Linux driver
 */

#ifndef NTB_HW_INTEL_H
#define NTB_HW_INTEL_H

#include <linux/ntb.h>
#include <linux/pci.h>
#include <linux/io-64-nonatomic-lo-hi.h>

/* PCI device IDs */
#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF	0x3725
#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF	0x3726
#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF	0x3727
#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB	0x3C0D
#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB	0x3C0E
#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB	0x3C0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT	0x0E0D
#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT	0x0E0E
#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT	0x0E0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX	0x2F0D
#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX	0x2F0E
#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX	0x2F0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX	0x6F0D
#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX	0x6F0E
#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX	0x6F0F
#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX	0x201C
#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX	0x347e
#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR	0x0db4

/* Ntb control and link status */
#define NTB_CTL_CFG_LOCK		BIT(0)
#define NTB_CTL_DISABLE			BIT(1)
#define NTB_CTL_S2P_BAR2_SNOOP		BIT(2)
#define NTB_CTL_P2S_BAR2_SNOOP		BIT(4)
#define NTB_CTL_S2P_BAR4_SNOOP		BIT(6)
#define NTB_CTL_P2S_BAR4_SNOOP		BIT(8)
#define NTB_CTL_S2P_BAR5_SNOOP		BIT(12)
#define NTB_CTL_P2S_BAR5_SNOOP		BIT(14)

#define NTB_LNK_STA_ACTIVE_BIT		0x2000
#define NTB_LNK_STA_SPEED_MASK		0x000f
#define NTB_LNK_STA_WIDTH_MASK		0x03f0
#define NTB_LNK_STA_ACTIVE(x)		(!!((x) & NTB_LNK_STA_ACTIVE_BIT))
#define NTB_LNK_STA_SPEED(x)		((x) & NTB_LNK_STA_SPEED_MASK)
#define NTB_LNK_STA_WIDTH(x)		(((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)

/* flags to indicate unsafe api */
#define NTB_UNSAFE_DB			BIT_ULL(0)
#define NTB_UNSAFE_SPAD			BIT_ULL(1)

#define NTB_BAR_MASK_64			~(0xfull)
#define NTB_BAR_MASK_32			~(0xfu)

struct intel_ntb_dev;

struct intel_ntb_reg {
	int (*poll_link)(struct intel_ntb_dev *ndev);
	int (*link_is_up)(struct intel_ntb_dev *ndev);
	u64 (*db_ioread)(const void __iomem *mmio);
	void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
	unsigned long			ntb_ctl;
	resource_size_t			db_size;
	int				mw_bar[];
};

struct intel_ntb_alt_reg {
	unsigned long			db_bell;
	unsigned long			db_mask;
	unsigned long			db_clear;
	unsigned long			spad;
};

struct intel_ntb_xlat_reg {
	unsigned long			bar0_base;
	unsigned long			bar2_xlat;
	unsigned long			bar2_limit;
	unsigned short			bar2_idx;
};

struct intel_b2b_addr {
	phys_addr_t			bar0_addr;
	phys_addr_t			bar2_addr64;
	phys_addr_t			bar4_addr64;
	phys_addr_t			bar4_addr32;
	phys_addr_t			bar5_addr32;
};

struct intel_ntb_vec {
	struct intel_ntb_dev		*ndev;
	int				num;
};

struct intel_ntb_dev {
	struct ntb_dev			ntb;

	/* offset of peer bar0 in b2b bar */
	unsigned long			b2b_off;
	/* mw idx used to access peer bar0 */
	unsigned int			b2b_idx;

	/* BAR45 is split into BAR4 and BAR5 */
	bool				bar4_split;

	u32				ntb_ctl;
	u32				lnk_sta;

	unsigned char			mw_count;
	unsigned char			spad_count;
	unsigned char			db_count;
	unsigned char			db_vec_count;
	unsigned char			db_vec_shift;

	u64				db_valid_mask;
	u64				db_link_mask;
	u64				db_mask;

	/* synchronize rmw access of db_mask and hw reg */
	spinlock_t			db_mask_lock;

	struct msix_entry		*msix;
	struct intel_ntb_vec		*vec;

	const struct intel_ntb_reg	*reg;
	const struct intel_ntb_alt_reg	*self_reg;
	const struct intel_ntb_alt_reg	*peer_reg;
	const struct intel_ntb_xlat_reg	*xlat_reg;
	void				__iomem *self_mmio;
	void				__iomem *peer_mmio;
	phys_addr_t			peer_addr;

	unsigned long			last_ts;
	struct delayed_work		hb_timer;

	unsigned long			hwerr_flags;
	unsigned long			unsafe_flags;
	unsigned long			unsafe_flags_ignore;

	struct dentry			*debugfs_dir;
	struct dentry			*debugfs_info;

	/* gen4 entries */
	int				dev_up;
};

#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
				     hb_timer.work)

static inline int pdev_is_gen1(struct pci_dev *pdev)
{
	switch (pdev->device) {
	case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
	case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
	case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
	case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
	case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
	case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
	case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
	case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
	case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
	case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
	case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
	case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
	case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
	case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
	case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
		return 1;
	}
	return 0;
}

static inline int pdev_is_gen3(struct pci_dev *pdev)
{
	if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)
		return 1;

	return 0;
}

static inline int pdev_is_gen4(struct pci_dev *pdev)
{
	if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
		return 1;

	return 0;
}

static inline int pdev_is_gen5(struct pci_dev *pdev)
{
	return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;
}

#endif
Commit	Line	Data
fce8a7bb JM	1	/*
	2	* This file is provided under a dual BSD/GPLv2 license. When using or
	3	* redistributing this file, you may do so under either license.
	4	*
	5	* GPL LICENSE SUMMARY
	6	*
	7	* Copyright(c) 2012 Intel Corporation. All rights reserved.
e26a5843	8	* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
fce8a7bb JM	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of version 2 of the GNU General Public License as
	12	* published by the Free Software Foundation.
	13	*
	14	* BSD LICENSE
	15	*
	16	* Copyright(c) 2012 Intel Corporation. All rights reserved.
e26a5843	17	* Copyright (C) 2015 EMC Corporation. All Rights Reserved.
fce8a7bb JM	18	*
	19	* Redistribution and use in source and binary forms, with or without
	20	* modification, are permitted provided that the following conditions
	21	* are met:
	22	*
	23	* * Redistributions of source code must retain the above copyright
	24	* notice, this list of conditions and the following disclaimer.
	25	* * Redistributions in binary form must reproduce the above copy
	26	* notice, this list of conditions and the following disclaimer in
	27	* the documentation and/or other materials provided with the
	28	* distribution.
	29	* * Neither the name of Intel Corporation nor the names of its
	30	* contributors may be used to endorse or promote products derived
	31	* from this software without specific prior written permission.
	32	*
	33	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	34	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	35	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	36	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	37	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	38	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	39	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	40	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	41	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	42	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	43	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	44	*
	45	* Intel PCIe NTB Linux driver
fce8a7bb	46	*/
ec110bc7	47
e26a5843 AH	48	#ifndef NTB_HW_INTEL_H
	49	#define NTB_HW_INTEL_H
	50
	51	#include <linux/ntb.h>
	52	#include <linux/pci.h>
0795ccde	53	#include <linux/io-64-nonatomic-lo-hi.h>
e26a5843	54
a9065055	55	/* PCI device IDs */
e26a5843 AH	56	#define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
	57	#define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
	58	#define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
	59	#define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
	60	#define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
	61	#define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
	62	#define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
	63	#define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
	64	#define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
	65	#define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
	66	#define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
	67	#define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
0a5d19d9 DJ	68	#define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D
	69	#define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
	70	#define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
783dfa6c	71	#define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
26bfe3d0	72	#define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
a914fc52	73	#define PCI_DEVICE_ID_INTEL_NTB_B2B_GNR 0x0db4
e26a5843	74
e26a5843	75	/* Ntb control and link status */
e26a5843 AH	76	#define NTB_CTL_CFG_LOCK BIT(0)
	77	#define NTB_CTL_DISABLE BIT(1)
	78	#define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
	79	#define NTB_CTL_P2S_BAR2_SNOOP BIT(4)
	80	#define NTB_CTL_S2P_BAR4_SNOOP BIT(6)
	81	#define NTB_CTL_P2S_BAR4_SNOOP BIT(8)
	82	#define NTB_CTL_S2P_BAR5_SNOOP BIT(12)
	83	#define NTB_CTL_P2S_BAR5_SNOOP BIT(14)
	84
	85	#define NTB_LNK_STA_ACTIVE_BIT 0x2000
	86	#define NTB_LNK_STA_SPEED_MASK 0x000f
	87	#define NTB_LNK_STA_WIDTH_MASK 0x03f0
	88	#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
	89	#define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
	90	#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
	91
e26a5843 AH	92	/* flags to indicate unsafe api */
	93	#define NTB_UNSAFE_DB BIT_ULL(0)
	94	#define NTB_UNSAFE_SPAD BIT_ULL(1)
	95
703872c2 DJ	96	#define NTB_BAR_MASK_64 ~(0xfull)
	97	#define NTB_BAR_MASK_32 ~(0xfu)
	98
e26a5843 AH	99	struct intel_ntb_dev;
	100
	101	struct intel_ntb_reg {
	102	int (poll_link)(struct intel_ntb_dev ndev);
	103	int (link_is_up)(struct intel_ntb_dev ndev);
58184e95	104	u64 (db_ioread)(const void __iomem mmio);
e26a5843 AH	105	void (db_iowrite)(u64 db_bits, void __iomem mmio);
	106	unsigned long ntb_ctl;
	107	resource_size_t db_size;
	108	int mw_bar[];
	109	};
ec110bc7	110
e26a5843 AH	111	struct intel_ntb_alt_reg {
	112	unsigned long db_bell;
	113	unsigned long db_mask;
783dfa6c	114	unsigned long db_clear;
e26a5843 AH	115	unsigned long spad;
e26a5843 AH	116	};
ac477afb	117
e26a5843 AH	118	struct intel_ntb_xlat_reg {
	119	unsigned long bar0_base;
	120	unsigned long bar2_xlat;
	121	unsigned long bar2_limit;
26bfe3d0	122	unsigned short bar2_idx;
fce8a7bb JM	123	};
fce8a7bb JM	124
e26a5843 AH	125	struct intel_b2b_addr {
	126	phys_addr_t bar0_addr;
	127	phys_addr_t bar2_addr64;
	128	phys_addr_t bar4_addr64;
	129	phys_addr_t bar4_addr32;
	130	phys_addr_t bar5_addr32;
fce8a7bb JM	131	};
fce8a7bb JM	132
e26a5843 AH	133	struct intel_ntb_vec {
	134	struct intel_ntb_dev *ndev;
	135	int num;
fce8a7bb JM	136	};
fce8a7bb JM	137
e26a5843 AH	138	struct intel_ntb_dev {
	139	struct ntb_dev ntb;
	140
	141	/* offset of peer bar0 in b2b bar */
	142	unsigned long b2b_off;
	143	/* mw idx used to access peer bar0 */
	144	unsigned int b2b_idx;
	145
	146	/* BAR45 is split into BAR4 and BAR5 */
	147	bool bar4_split;
	148
	149	u32 ntb_ctl;
	150	u32 lnk_sta;
	151
	152	unsigned char mw_count;
	153	unsigned char spad_count;
	154	unsigned char db_count;
	155	unsigned char db_vec_count;
	156	unsigned char db_vec_shift;
	157
	158	u64 db_valid_mask;
	159	u64 db_link_mask;
	160	u64 db_mask;
	161
	162	/* synchronize rmw access of db_mask and hw reg */
	163	spinlock_t db_mask_lock;
	164
	165	struct msix_entry *msix;
	166	struct intel_ntb_vec *vec;
	167
	168	const struct intel_ntb_reg *reg;
	169	const struct intel_ntb_alt_reg *self_reg;
	170	const struct intel_ntb_alt_reg *peer_reg;
	171	const struct intel_ntb_xlat_reg *xlat_reg;
	172	void __iomem *self_mmio;
	173	void __iomem *peer_mmio;
	174	phys_addr_t peer_addr;
	175
	176	unsigned long last_ts;
	177	struct delayed_work hb_timer;
	178
	179	unsigned long hwerr_flags;
	180	unsigned long unsafe_flags;
	181	unsigned long unsafe_flags_ignore;
	182
	183	struct dentry *debugfs_dir;
	184	struct dentry *debugfs_info;
26bfe3d0 DJ	185
	186	/* gen4 entries */
	187	int dev_up;
fce8a7bb JM	188	};
fce8a7bb JM	189
03beaec8 AH	190	#define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
	191	#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
	192	hb_timer.work)
e26a5843	193
6c1e8ab2	194	static inline int pdev_is_gen1(struct pci_dev *pdev)
f6e51c35 DJ	195	{
	196	switch (pdev->device) {
	197	case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
	198	case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
	199	case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
	200	case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
	201	case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
	202	case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
	203	case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
	204	case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
	205	case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
	206	case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
	207	case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
	208	case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
	209	case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
	210	case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
	211	case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
	212	return 1;
	213	}
	214	return 0;
	215	}
	216
6c1e8ab2	217	static inline int pdev_is_gen3(struct pci_dev *pdev)
f6e51c35 DJ	218	{
	219	if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)
	220	return 1;
	221
	222	return 0;
	223	}
	224
26bfe3d0 DJ	225	static inline int pdev_is_gen4(struct pci_dev *pdev)
	226	{
	227	if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
	228	return 1;
	229
	230	return 0;
	231	}
a914fc52 DJ	232
	233	static inline int pdev_is_gen5(struct pci_dev *pdev)
	234	{
	235	return pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_GNR;
	236	}
	237
e26a5843	238	#endif