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netdev: convert bulk of drivers to netdev_tx_t
[linux-2.6-block.git] / drivers / net / yellowfin.c
CommitLineData
1da177e4
LT		 1/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2/*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
03a8c661 22 [link no longer provides useful info -jgarzik]
1da177e4 23
1da177e4
LT		 24*/
25
26#define DRV_NAME "yellowfin"
d5b20697
AG		 27#define DRV_VERSION "2.1"
28#define DRV_RELDATE "Sep 11, 2006"
1da177e4
LT		 29
30#define PFX DRV_NAME ": "
31
32/* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37static int max_interrupt_work = 20;
38static int mtu;
39#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40/* System-wide count of bogus-rx frames. */
41static int bogus_rx;
42static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44#elif defined(YF_NEW) /* A future perfect board :->. */
45static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46static int fifo_cfg = 0x0028;
47#else
f71e1309
AV		 48static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
1da177e4
LT		 50#endif
51
52/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54static int rx_copybreak;
55
56/* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
58 interoperability.
59*/
60#define MAX_UNITS 8 /* More are supported, limit only on options */
61static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
63
64/* Do ugly workaround for GX server chipset errata. */
65static int gx_fix;
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73#define TX_RING_SIZE 16
74#define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75#define RX_RING_SIZE 64
76#define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77#define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
79
80/* Operational parameters that usually are not changed. */
81/* Time in jiffies before concluding the transmitter is hung. */
82#define TX_TIMEOUT (2*HZ)
83#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85#define yellowfin_debug debug
86
87#include <linux/module.h>
88#include <linux/kernel.h>
89#include <linux/string.h>
90#include <linux/timer.h>
91#include <linux/errno.h>
92#include <linux/ioport.h>
93#include <linux/slab.h>
94#include <linux/interrupt.h>
95#include <linux/pci.h>
96#include <linux/init.h>
97#include <linux/mii.h>
98#include <linux/netdevice.h>
99#include <linux/etherdevice.h>
100#include <linux/skbuff.h>
101#include <linux/ethtool.h>
102#include <linux/crc32.h>
103#include <linux/bitops.h>
104#include <asm/uaccess.h>
105#include <asm/processor.h> /* Processor type for cache alignment. */
106#include <asm/unaligned.h>
107#include <asm/io.h>
108
109/* These identify the driver base version and may not be removed. */
7285484a
SH		 110static const char version[] __devinitconst =
111 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
ad361c98 112 " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
1da177e4
LT		 113
114MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
115MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
116MODULE_LICENSE("GPL");
117
118module_param(max_interrupt_work, int, 0);
119module_param(mtu, int, 0);
120module_param(debug, int, 0);
121module_param(rx_copybreak, int, 0);
122module_param_array(options, int, NULL, 0);
123module_param_array(full_duplex, int, NULL, 0);
124module_param(gx_fix, int, 0);
125MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
126MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
127MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
128MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
129MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
130MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
131MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
132
133/*
134 Theory of Operation
135
136I. Board Compatibility
137
138This device driver is designed for the Packet Engines "Yellowfin" Gigabit
6aa20a22 139Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
1da177e4
LT		 140Symbios 53C885E dual function chip.
141
142II. Board-specific settings
143
144PCI bus devices are configured by the system at boot time, so no jumpers
145need to be set on the board. The system BIOS preferably should assign the
146PCI INTA signal to an otherwise unused system IRQ line.
147Note: Kernel versions earlier than 1.3.73 do not support shared PCI
148interrupt lines.
149
150III. Driver operation
151
152IIIa. Ring buffers
153
154The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
155This is a descriptor list scheme similar to that used by the EEPro100 and
156Tulip. This driver uses two statically allocated fixed-size descriptor lists
157formed into rings by a branch from the final descriptor to the beginning of
158the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
159
160The driver allocates full frame size skbuffs for the Rx ring buffers at
161open() time and passes the skb->data field to the Yellowfin as receive data
162buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
163a fresh skbuff is allocated and the frame is copied to the new skbuff.
164When the incoming frame is larger, the skbuff is passed directly up the
165protocol stack and replaced by a newly allocated skbuff.
166
167The RX_COPYBREAK value is chosen to trade-off the memory wasted by
168using a full-sized skbuff for small frames vs. the copying costs of larger
169frames. For small frames the copying cost is negligible (esp. considering
170that we are pre-loading the cache with immediately useful header
171information). For large frames the copying cost is non-trivial, and the
172larger copy might flush the cache of useful data.
173
174IIIC. Synchronization
175
176The driver runs as two independent, single-threaded flows of control. One
177is the send-packet routine, which enforces single-threaded use by the
178dev->tbusy flag. The other thread is the interrupt handler, which is single
179threaded by the hardware and other software.
180
181The send packet thread has partial control over the Tx ring and 'dev->tbusy'
182flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
183queue slot is empty, it clears the tbusy flag when finished otherwise it sets
184the 'yp->tx_full' flag.
185
186The interrupt handler has exclusive control over the Rx ring and records stats
187from the Tx ring. After reaping the stats, it marks the Tx queue entry as
188empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
189clears both the tx_full and tbusy flags.
190
191IV. Notes
192
193Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
194Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
195and an AlphaStation to verifty the Alpha port!
196
197IVb. References
198
199Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
200Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
201 Data Manual v3.0
202http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
203http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
204
205IVc. Errata
206
207See Packet Engines confidential appendix (prototype chips only).
208*/
209
6aa20a22 210
1da177e4 211
1da177e4
LT		 212enum capability_flags {
213 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
214 HasMACAddrBug=32, /* Only on early revs. */
215 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
216};
c3d8e682 217
1da177e4 218/* The PCI I/O space extent. */
c3d8e682
JG		 219enum {
220 YELLOWFIN_SIZE = 0x100,
221};
1da177e4
LT		 222
223struct pci_id_info {
224 const char *name;
225 struct match_info {
226 int pci, pci_mask, subsystem, subsystem_mask;
227 int revision, revision_mask; /* Only 8 bits. */
228 } id;
1da177e4
LT		 229 int drv_flags; /* Driver use, intended as capability flags. */
230};
231
f71e1309 232static const struct pci_id_info pci_id_tbl[] = {
1da177e4 233 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
1da177e4
LT		 234 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
235 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
c3d8e682 236 HasMII | DontUseEeprom },
1f1bd5fc 237 { }
1da177e4
LT		 238};
239
1f1bd5fc 240static const struct pci_device_id yellowfin_pci_tbl[] = {
1da177e4
LT		 241 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
242 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
1f1bd5fc 243 { }
1da177e4
LT		 244};
245MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
246
247
248/* Offsets to the Yellowfin registers. Various sizes and alignments. */
249enum yellowfin_offsets {
250 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
251 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
252 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
253 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
254 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
255 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
256 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
257 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
258 MII_Status=0xAE,
259 RxDepth=0xB8, FlowCtrl=0xBC,
260 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
261 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
262 EEFeature=0xF5,
263};
264
265/* The Yellowfin Rx and Tx buffer descriptors.
266 Elements are written as 32 bit for endian portability. */
267struct yellowfin_desc {
e5a31421
AV		 268 __le32 dbdma_cmd;
269 __le32 addr;
270 __le32 branch_addr;
271 __le32 result_status;
1da177e4
LT		 272};
273
274struct tx_status_words {
275#ifdef __BIG_ENDIAN
276 u16 tx_errs;
277 u16 tx_cnt;
278 u16 paused;
279 u16 total_tx_cnt;
280#else /* Little endian chips. */
281 u16 tx_cnt;
282 u16 tx_errs;
283 u16 total_tx_cnt;
284 u16 paused;
285#endif /* __BIG_ENDIAN */
286};
287
288/* Bits in yellowfin_desc.cmd */
289enum desc_cmd_bits {
290 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
291 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
292 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
293 BRANCH_IFTRUE=0x040000,
294};
295
296/* Bits in yellowfin_desc.status */
297enum desc_status_bits { RX_EOP=0x0040, };
298
299/* Bits in the interrupt status/mask registers. */
300enum intr_status_bits {
301 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
302 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
303 IntrEarlyRx=0x100, IntrWakeup=0x200, };
304
305#define PRIV_ALIGN 31 /* Required alignment mask */
306#define MII_CNT 4
307struct yellowfin_private {
308 /* Descriptor rings first for alignment.
309 Tx requires a second descriptor for status. */
310 struct yellowfin_desc *rx_ring;
311 struct yellowfin_desc *tx_ring;
312 struct sk_buff* rx_skbuff[RX_RING_SIZE];
313 struct sk_buff* tx_skbuff[TX_RING_SIZE];
314 dma_addr_t rx_ring_dma;
315 dma_addr_t tx_ring_dma;
316
317 struct tx_status_words *tx_status;
318 dma_addr_t tx_status_dma;
319
320 struct timer_list timer; /* Media selection timer. */
1da177e4
LT		 321 /* Frequently used and paired value: keep adjacent for cache effect. */
322 int chip_id, drv_flags;
323 struct pci_dev *pci_dev;
324 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
325 unsigned int rx_buf_sz; /* Based on MTU+slack. */
326 struct tx_status_words *tx_tail_desc;
327 unsigned int cur_tx, dirty_tx;
328 int tx_threshold;
329 unsigned int tx_full:1; /* The Tx queue is full. */
330 unsigned int full_duplex:1; /* Full-duplex operation requested. */
331 unsigned int duplex_lock:1;
332 unsigned int medialock:1; /* Do not sense media. */
333 unsigned int default_port:4; /* Last dev->if_port value. */
334 /* MII transceiver section. */
335 int mii_cnt; /* MII device addresses. */
336 u16 advertising; /* NWay media advertisement */
337 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
338 spinlock_t lock;
339 void __iomem *base;
340};
341
342static int read_eeprom(void __iomem *ioaddr, int location);
343static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
344static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
345static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
346static int yellowfin_open(struct net_device *dev);
347static void yellowfin_timer(unsigned long data);
348static void yellowfin_tx_timeout(struct net_device *dev);
349static void yellowfin_init_ring(struct net_device *dev);
61357325
SH		 350static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
351 struct net_device *dev);
7d12e780 352static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
1da177e4
LT		 353static int yellowfin_rx(struct net_device *dev);
354static void yellowfin_error(struct net_device *dev, int intr_status);
355static int yellowfin_close(struct net_device *dev);
1da177e4 356static void set_rx_mode(struct net_device *dev);
7282d491 357static const struct ethtool_ops ethtool_ops;
1da177e4 358
bfd82c35
SH		 359static const struct net_device_ops netdev_ops = {
360 .ndo_open = yellowfin_open,
361 .ndo_stop = yellowfin_close,
362 .ndo_start_xmit = yellowfin_start_xmit,
363 .ndo_set_multicast_list = set_rx_mode,
364 .ndo_change_mtu = eth_change_mtu,
365 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 366 .ndo_set_mac_address = eth_mac_addr,
bfd82c35
SH		 367 .ndo_do_ioctl = netdev_ioctl,
368 .ndo_tx_timeout = yellowfin_tx_timeout,
369};
1da177e4
LT		 370
371static int __devinit yellowfin_init_one(struct pci_dev *pdev,
372 const struct pci_device_id *ent)
373{
374 struct net_device *dev;
375 struct yellowfin_private *np;
376 int irq;
377 int chip_idx = ent->driver_data;
378 static int find_cnt;
379 void __iomem *ioaddr;
380 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
381 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
382 void *ring_space;
383 dma_addr_t ring_dma;
384#ifdef USE_IO_OPS
385 int bar = 0;
386#else
387 int bar = 1;
388#endif
6aa20a22 389
1da177e4
LT		 390/* when built into the kernel, we only print version if device is found */
391#ifndef MODULE
392 static int printed_version;
393 if (!printed_version++)
394 printk(version);
395#endif
396
397 i = pci_enable_device(pdev);
398 if (i) return i;
399
400 dev = alloc_etherdev(sizeof(*np));
401 if (!dev) {
402 printk (KERN_ERR PFX "cannot allocate ethernet device\n");
403 return -ENOMEM;
404 }
1da177e4
LT		 405 SET_NETDEV_DEV(dev, &pdev->dev);
406
407 np = netdev_priv(dev);
408
409 if (pci_request_regions(pdev, DRV_NAME))
410 goto err_out_free_netdev;
411
412 pci_set_master (pdev);
413
414 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
415 if (!ioaddr)
416 goto err_out_free_res;
417
418 irq = pdev->irq;
419
420 if (drv_flags & DontUseEeprom)
421 for (i = 0; i < 6; i++)
422 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
423 else {
424 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
425 for (i = 0; i < 6; i++)
426 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
427 }
428
429 /* Reset the chip. */
430 iowrite32(0x80000000, ioaddr + DMACtrl);
431
432 dev->base_addr = (unsigned long)ioaddr;
433 dev->irq = irq;
434
435 pci_set_drvdata(pdev, dev);
436 spin_lock_init(&np->lock);
437
438 np->pci_dev = pdev;
439 np->chip_id = chip_idx;
440 np->drv_flags = drv_flags;
441 np->base = ioaddr;
442
443 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
444 if (!ring_space)
445 goto err_out_cleardev;
446 np->tx_ring = (struct yellowfin_desc *)ring_space;
447 np->tx_ring_dma = ring_dma;
448
449 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
450 if (!ring_space)
451 goto err_out_unmap_tx;
452 np->rx_ring = (struct yellowfin_desc *)ring_space;
453 np->rx_ring_dma = ring_dma;
454
455 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
456 if (!ring_space)
457 goto err_out_unmap_rx;
458 np->tx_status = (struct tx_status_words *)ring_space;
459 np->tx_status_dma = ring_dma;
460
461 if (dev->mem_start)
462 option = dev->mem_start;
463
464 /* The lower four bits are the media type. */
465 if (option > 0) {
466 if (option & 0x200)
467 np->full_duplex = 1;
468 np->default_port = option & 15;
469 if (np->default_port)
470 np->medialock = 1;
471 }
472 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
473 np->full_duplex = 1;
474
475 if (np->full_duplex)
476 np->duplex_lock = 1;
477
478 /* The Yellowfin-specific entries in the device structure. */
bfd82c35 479 dev->netdev_ops = &netdev_ops;
1da177e4 480 SET_ETHTOOL_OPS(dev, &ethtool_ops);
1da177e4
LT		 481 dev->watchdog_timeo = TX_TIMEOUT;
482
483 if (mtu)
484 dev->mtu = mtu;
485
486 i = register_netdev(dev);
487 if (i)
488 goto err_out_unmap_status;
489
e174961c 490 printk(KERN_INFO "%s: %s type %8x at %p, %pM, IRQ %d.\n",
1da177e4 491 dev->name, pci_id_tbl[chip_idx].name,
0795af57 492 ioread32(ioaddr + ChipRev), ioaddr,
e174961c 493 dev->dev_addr, irq);
1da177e4
LT		 494
495 if (np->drv_flags & HasMII) {
496 int phy, phy_idx = 0;
497 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
498 int mii_status = mdio_read(ioaddr, phy, 1);
499 if (mii_status != 0xffff && mii_status != 0x0000) {
500 np->phys[phy_idx++] = phy;
501 np->advertising = mdio_read(ioaddr, phy, 4);
502 printk(KERN_INFO "%s: MII PHY found at address %d, status "
503 "0x%4.4x advertising %4.4x.\n",
504 dev->name, phy, mii_status, np->advertising);
505 }
506 }
507 np->mii_cnt = phy_idx;
508 }
509
510 find_cnt++;
6aa20a22 511
1da177e4
LT		 512 return 0;
513
514err_out_unmap_status:
6aa20a22 515 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1da177e4
LT		 516 np->tx_status_dma);
517err_out_unmap_rx:
518 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
519err_out_unmap_tx:
520 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
521err_out_cleardev:
522 pci_set_drvdata(pdev, NULL);
523 pci_iounmap(pdev, ioaddr);
524err_out_free_res:
525 pci_release_regions(pdev);
526err_out_free_netdev:
527 free_netdev (dev);
528 return -ENODEV;
529}
530
531static int __devinit read_eeprom(void __iomem *ioaddr, int location)
532{
533 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
534
535 iowrite8(location, ioaddr + EEAddr);
536 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
537 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
538 ;
539 return ioread8(ioaddr + EERead);
540}
541
542/* MII Managemen Data I/O accesses.
543 These routines assume the MDIO controller is idle, and do not exit until
544 the command is finished. */
545
546static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
547{
548 int i;
549
550 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
551 iowrite16(1, ioaddr + MII_Cmd);
552 for (i = 10000; i >= 0; i--)
553 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
554 break;
555 return ioread16(ioaddr + MII_Rd_Data);
556}
557
558static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
559{
560 int i;
561
562 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
563 iowrite16(value, ioaddr + MII_Wr_Data);
564
565 /* Wait for the command to finish. */
566 for (i = 10000; i >= 0; i--)
567 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
568 break;
569 return;
570}
571
6aa20a22 572
1da177e4
LT		 573static int yellowfin_open(struct net_device *dev)
574{
575 struct yellowfin_private *yp = netdev_priv(dev);
576 void __iomem *ioaddr = yp->base;
577 int i;
578
579 /* Reset the chip. */
580 iowrite32(0x80000000, ioaddr + DMACtrl);
581
1fb9df5d 582 i = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 583 if (i) return i;
584
585 if (yellowfin_debug > 1)
586 printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
587 dev->name, dev->irq);
588
589 yellowfin_init_ring(dev);
590
591 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
592 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
593
594 for (i = 0; i < 6; i++)
595 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
596
597 /* Set up various condition 'select' registers.
598 There are no options here. */
599 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
600 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
601 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
602 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
603 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
604 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
605
606 /* Initialize other registers: with so many this eventually this will
607 converted to an offset/value list. */
608 iowrite32(dma_ctrl, ioaddr + DMACtrl);
609 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
610 /* Enable automatic generation of flow control frames, period 0xffff. */
611 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
612
613 yp->tx_threshold = 32;
614 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
615
616 if (dev->if_port == 0)
617 dev->if_port = yp->default_port;
618
619 netif_start_queue(dev);
620
621 /* Setting the Rx mode will start the Rx process. */
622 if (yp->drv_flags & IsGigabit) {
623 /* We are always in full-duplex mode with gigabit! */
624 yp->full_duplex = 1;
625 iowrite16(0x01CF, ioaddr + Cnfg);
626 } else {
627 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
628 iowrite16(0x1018, ioaddr + FrameGap1);
629 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
630 }
631 set_rx_mode(dev);
632
633 /* Enable interrupts by setting the interrupt mask. */
634 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
635 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
636 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
637 iowrite32(0x80008000, ioaddr + TxCtrl);
638
639 if (yellowfin_debug > 2) {
640 printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
641 dev->name);
642 }
643
644 /* Set the timer to check for link beat. */
645 init_timer(&yp->timer);
646 yp->timer.expires = jiffies + 3*HZ;
647 yp->timer.data = (unsigned long)dev;
648 yp->timer.function = &yellowfin_timer; /* timer handler */
649 add_timer(&yp->timer);
650
651 return 0;
652}
653
654static void yellowfin_timer(unsigned long data)
655{
656 struct net_device *dev = (struct net_device *)data;
657 struct yellowfin_private *yp = netdev_priv(dev);
658 void __iomem *ioaddr = yp->base;
659 int next_tick = 60*HZ;
660
661 if (yellowfin_debug > 3) {
662 printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
663 dev->name, ioread16(ioaddr + IntrStatus));
664 }
665
666 if (yp->mii_cnt) {
667 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
668 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
669 int negotiated = lpa & yp->advertising;
670 if (yellowfin_debug > 1)
671 printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
672 "link partner capability %4.4x.\n",
673 dev->name, yp->phys[0], bmsr, lpa);
674
675 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
6aa20a22 676
1da177e4
LT		 677 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
678
679 if (bmsr & BMSR_LSTATUS)
680 next_tick = 60*HZ;
681 else
682 next_tick = 3*HZ;
683 }
684
685 yp->timer.expires = jiffies + next_tick;
686 add_timer(&yp->timer);
687}
688
689static void yellowfin_tx_timeout(struct net_device *dev)
690{
691 struct yellowfin_private *yp = netdev_priv(dev);
692 void __iomem *ioaddr = yp->base;
693
694 printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
695 "status %4.4x, Rx status %4.4x, resetting...\n",
696 dev->name, yp->cur_tx, yp->dirty_tx,
697 ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
698
699 /* Note: these should be KERN_DEBUG. */
700 if (yellowfin_debug) {
701 int i;
702 printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring);
703 for (i = 0; i < RX_RING_SIZE; i++)
ad361c98
JP		 704 printk(KERN_CONT " %8.8x",
705 yp->rx_ring[i].result_status);
706 printk(KERN_CONT "\n");
707 printk(KERN_WARNING" Tx ring %p: ", yp->tx_ring);
1da177e4 708 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98
JP		 709 printk(KERN_CONT " %4.4x /%8.8x",
710 yp->tx_status[i].tx_errs,
711 yp->tx_ring[i].result_status);
712 printk(KERN_CONT "\n");
1da177e4
LT		 713 }
714
715 /* If the hardware is found to hang regularly, we will update the code
716 to reinitialize the chip here. */
717 dev->if_port = 0;
718
719 /* Wake the potentially-idle transmit channel. */
720 iowrite32(0x10001000, yp->base + TxCtrl);
721 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
722 netif_wake_queue (dev); /* Typical path */
723
cdd0db05 724 dev->trans_start = jiffies; /* prevent tx timeout */
09f75cd7 725 dev->stats.tx_errors++;
1da177e4
LT		 726}
727
728/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
729static void yellowfin_init_ring(struct net_device *dev)
730{
731 struct yellowfin_private *yp = netdev_priv(dev);
732 int i;
733
734 yp->tx_full = 0;
735 yp->cur_rx = yp->cur_tx = 0;
736 yp->dirty_tx = 0;
737
738 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
739
740 for (i = 0; i < RX_RING_SIZE; i++) {
741 yp->rx_ring[i].dbdma_cmd =
742 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
743 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
744 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
745 }
746
747 for (i = 0; i < RX_RING_SIZE; i++) {
748 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
749 yp->rx_skbuff[i] = skb;
750 if (skb == NULL)
751 break;
752 skb->dev = dev; /* Mark as being used by this device. */
753 skb_reserve(skb, 2); /* 16 byte align the IP header. */
754 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
689be439 755 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT		 756 }
757 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
758 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
759
760#define NO_TXSTATS
761#ifdef NO_TXSTATS
762 /* In this mode the Tx ring needs only a single descriptor. */
763 for (i = 0; i < TX_RING_SIZE; i++) {
764 yp->tx_skbuff[i] = NULL;
765 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
766 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
767 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
768 }
769 /* Wrap ring */
770 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
771#else
772{
773 int j;
774
775 /* Tx ring needs a pair of descriptors, the second for the status. */
776 for (i = 0; i < TX_RING_SIZE; i++) {
777 j = 2*i;
778 yp->tx_skbuff[i] = 0;
779 /* Branch on Tx error. */
780 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
781 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
80950f8b 782 (j+1)*sizeof(struct yellowfin_desc));
1da177e4
LT		 783 j++;
784 if (yp->flags & FullTxStatus) {
785 yp->tx_ring[j].dbdma_cmd =
786 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
787 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
788 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
80950f8b 789 i*sizeof(struct tx_status_words));
1da177e4
LT		 790 } else {
791 /* Symbios chips write only tx_errs word. */
792 yp->tx_ring[j].dbdma_cmd =
793 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
794 yp->tx_ring[j].request_cnt = 2;
795 /* Om pade ummmmm... */
796 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
797 i*sizeof(struct tx_status_words) +
6aa20a22 798 &(yp->tx_status[0].tx_errs) -
1da177e4
LT		 799 &(yp->tx_status[0]));
800 }
6aa20a22 801 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
1da177e4
LT		 802 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
803 }
804 /* Wrap ring */
805 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
806}
807#endif
808 yp->tx_tail_desc = &yp->tx_status[0];
809 return;
810}
811
61357325
SH		 812static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
813 struct net_device *dev)
1da177e4
LT		 814{
815 struct yellowfin_private *yp = netdev_priv(dev);
816 unsigned entry;
817 int len = skb->len;
818
819 netif_stop_queue (dev);
820
821 /* Note: Ordering is important here, set the field with the
822 "ownership" bit last, and only then increment cur_tx. */
823
824 /* Calculate the next Tx descriptor entry. */
825 entry = yp->cur_tx % TX_RING_SIZE;
826
827 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
828 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
829 /* Fix GX chipset errata. */
830 if (cacheline_end > 24 || cacheline_end == 0) {
831 len = skb->len + 32 - cacheline_end + 1;
5b057c6b
HX		 832 if (skb_padto(skb, len)) {
833 yp->tx_skbuff[entry] = NULL;
834 netif_wake_queue(dev);
6ed10654 835 return NETDEV_TX_OK;
5b057c6b 836 }
1da177e4
LT		 837 }
838 }
839 yp->tx_skbuff[entry] = skb;
840
841#ifdef NO_TXSTATS
6aa20a22 842 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1da177e4
LT		 843 skb->data, len, PCI_DMA_TODEVICE));
844 yp->tx_ring[entry].result_status = 0;
845 if (entry >= TX_RING_SIZE-1) {
846 /* New stop command. */
847 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
848 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
849 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
850 } else {
851 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
852 yp->tx_ring[entry].dbdma_cmd =
853 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
854 }
855 yp->cur_tx++;
856#else
857 yp->tx_ring[entry<<1].request_cnt = len;
6aa20a22 858 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1da177e4 859 skb->data, len, PCI_DMA_TODEVICE));
6aa20a22 860 /* The input_last (status-write) command is constant, but we must
1da177e4
LT		 861 rewrite the subsequent 'stop' command. */
862
863 yp->cur_tx++;
864 {
865 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
866 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
867 }
868 /* Final step -- overwrite the old 'stop' command. */
869
870 yp->tx_ring[entry<<1].dbdma_cmd =
871 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
872 CMD_TX_PKT | BRANCH_IFTRUE) | len);
873#endif
874
875 /* Non-x86 Todo: explicitly flush cache lines here. */
876
877 /* Wake the potentially-idle transmit channel. */
878 iowrite32(0x10001000, yp->base + TxCtrl);
879
880 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
881 netif_start_queue (dev); /* Typical path */
882 else
883 yp->tx_full = 1;
1da177e4
LT		 884
885 if (yellowfin_debug > 4) {
886 printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
887 dev->name, yp->cur_tx, entry);
888 }
6ed10654 889 return NETDEV_TX_OK;
1da177e4
LT		 890}
891
892/* The interrupt handler does all of the Rx thread work and cleans up
893 after the Tx thread. */
7d12e780 894static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
1da177e4
LT		 895{
896 struct net_device *dev = dev_instance;
897 struct yellowfin_private *yp;
898 void __iomem *ioaddr;
899 int boguscnt = max_interrupt_work;
900 unsigned int handled = 0;
901
1da177e4
LT		 902 yp = netdev_priv(dev);
903 ioaddr = yp->base;
6aa20a22 904
1da177e4
LT		 905 spin_lock (&yp->lock);
906
907 do {
908 u16 intr_status = ioread16(ioaddr + IntrClear);
909
910 if (yellowfin_debug > 4)
911 printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
912 dev->name, intr_status);
913
914 if (intr_status == 0)
915 break;
916 handled = 1;
917
918 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
919 yellowfin_rx(dev);
920 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
921 }
922
923#ifdef NO_TXSTATS
924 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
925 int entry = yp->dirty_tx % TX_RING_SIZE;
926 struct sk_buff *skb;
927
928 if (yp->tx_ring[entry].result_status == 0)
929 break;
930 skb = yp->tx_skbuff[entry];
09f75cd7
JG		 931 dev->stats.tx_packets++;
932 dev->stats.tx_bytes += skb->len;
1da177e4 933 /* Free the original skb. */
e5a31421 934 pci_unmap_single(yp->pci_dev, le32_to_cpu(yp->tx_ring[entry].addr),
1da177e4
LT		 935 skb->len, PCI_DMA_TODEVICE);
936 dev_kfree_skb_irq(skb);
937 yp->tx_skbuff[entry] = NULL;
938 }
939 if (yp->tx_full
940 && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
941 /* The ring is no longer full, clear tbusy. */
942 yp->tx_full = 0;
943 netif_wake_queue(dev);
944 }
945#else
946 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
947 unsigned dirty_tx = yp->dirty_tx;
948
949 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
950 dirty_tx++) {
951 /* Todo: optimize this. */
952 int entry = dirty_tx % TX_RING_SIZE;
953 u16 tx_errs = yp->tx_status[entry].tx_errs;
954 struct sk_buff *skb;
955
956#ifndef final_version
957 if (yellowfin_debug > 5)
958 printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
959 "%4.4x %4.4x %4.4x %4.4x.\n",
960 dev->name, entry,
961 yp->tx_status[entry].tx_cnt,
962 yp->tx_status[entry].tx_errs,
963 yp->tx_status[entry].total_tx_cnt,
964 yp->tx_status[entry].paused);
965#endif
966 if (tx_errs == 0)
967 break; /* It still hasn't been Txed */
968 skb = yp->tx_skbuff[entry];
969 if (tx_errs & 0xF810) {
970 /* There was an major error, log it. */
971#ifndef final_version
972 if (yellowfin_debug > 1)
973 printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
974 dev->name, tx_errs);
975#endif
09f75cd7
JG		 976 dev->stats.tx_errors++;
977 if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
978 if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
979 if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
980 if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
1da177e4
LT		 981 } else {
982#ifndef final_version
983 if (yellowfin_debug > 4)
984 printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
985 dev->name, tx_errs);
986#endif
09f75cd7
JG		 987 dev->stats.tx_bytes += skb->len;
988 dev->stats.collisions += tx_errs & 15;
989 dev->stats.tx_packets++;
1da177e4
LT		 990 }
991 /* Free the original skb. */
6aa20a22
JG		 992 pci_unmap_single(yp->pci_dev,
993 yp->tx_ring[entry<<1].addr, skb->len,
1da177e4
LT		 994 PCI_DMA_TODEVICE);
995 dev_kfree_skb_irq(skb);
996 yp->tx_skbuff[entry] = 0;
997 /* Mark status as empty. */
998 yp->tx_status[entry].tx_errs = 0;
999 }
1000
1001#ifndef final_version
1002 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
1003 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1004 dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
1005 dirty_tx += TX_RING_SIZE;
1006 }
1007#endif
1008
1009 if (yp->tx_full
1010 && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1011 /* The ring is no longer full, clear tbusy. */
1012 yp->tx_full = 0;
1013 netif_wake_queue(dev);
1014 }
1015
1016 yp->dirty_tx = dirty_tx;
1017 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1018 }
1019#endif
1020
1021 /* Log errors and other uncommon events. */
1022 if (intr_status & 0x2ee) /* Abnormal error summary. */
1023 yellowfin_error(dev, intr_status);
1024
1025 if (--boguscnt < 0) {
1026 printk(KERN_WARNING "%s: Too much work at interrupt, "
1027 "status=0x%4.4x.\n",
1028 dev->name, intr_status);
1029 break;
1030 }
1031 } while (1);
1032
1033 if (yellowfin_debug > 3)
1034 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1035 dev->name, ioread16(ioaddr + IntrStatus));
1036
1037 spin_unlock (&yp->lock);
1038 return IRQ_RETVAL(handled);
1039}
1040
1041/* This routine is logically part of the interrupt handler, but separated
1042 for clarity and better register allocation. */
1043static int yellowfin_rx(struct net_device *dev)
1044{
1045 struct yellowfin_private *yp = netdev_priv(dev);
1046 int entry = yp->cur_rx % RX_RING_SIZE;
1047 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1048
1049 if (yellowfin_debug > 4) {
1050 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1051 entry, yp->rx_ring[entry].result_status);
1052 printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
1053 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1054 yp->rx_ring[entry].result_status);
1055 }
1056
1057 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1058 while (1) {
1059 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1060 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1061 s16 frame_status;
1062 u16 desc_status;
1063 int data_size;
1064 u8 *buf_addr;
1065
1066 if(!desc->result_status)
1067 break;
e5a31421 1068 pci_dma_sync_single_for_cpu(yp->pci_dev, le32_to_cpu(desc->addr),
1da177e4
LT		 1069 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1070 desc_status = le32_to_cpu(desc->result_status) >> 16;
689be439 1071 buf_addr = rx_skb->data;
6aa20a22 1072 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1da177e4 1073 le32_to_cpu(desc->result_status)) & 0xffff;
6caf52a4 1074 frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1da177e4
LT		 1075 if (yellowfin_debug > 4)
1076 printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n",
1077 frame_status);
1078 if (--boguscnt < 0)
1079 break;
1080 if ( ! (desc_status & RX_EOP)) {
1081 if (data_size != 0)
1082 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1083 " status %4.4x, data_size %d!\n", dev->name, desc_status, data_size);
09f75cd7 1084 dev->stats.rx_length_errors++;
1da177e4
LT		 1085 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1086 /* There was a error. */
1087 if (yellowfin_debug > 3)
1088 printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n",
1089 frame_status);
09f75cd7
JG		 1090 dev->stats.rx_errors++;
1091 if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1092 if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1093 if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1094 if (frame_status < 0) dev->stats.rx_dropped++;
1da177e4
LT		 1095 } else if ( !(yp->drv_flags & IsGigabit) &&
1096 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1097 u8 status1 = buf_addr[data_size-2];
1098 u8 status2 = buf_addr[data_size-1];
09f75cd7
JG		 1099 dev->stats.rx_errors++;
1100 if (status1 & 0xC0) dev->stats.rx_length_errors++;
1101 if (status2 & 0x03) dev->stats.rx_frame_errors++;
1102 if (status2 & 0x04) dev->stats.rx_crc_errors++;
1103 if (status2 & 0x80) dev->stats.rx_dropped++;
1da177e4
LT		 1104#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1105 } else if ((yp->flags & HasMACAddrBug) &&
1106 memcmp(le32_to_cpu(yp->rx_ring_dma +
1107 entry*sizeof(struct yellowfin_desc)),
6aa20a22 1108 dev->dev_addr, 6) != 0 &&
1da177e4
LT		 1109 memcmp(le32_to_cpu(yp->rx_ring_dma +
1110 entry*sizeof(struct yellowfin_desc)),
1111 "\377\377\377\377\377\377", 6) != 0) {
e174961c
JB		 1112 if (bogus_rx++ == 0)
1113 printk(KERN_WARNING "%s: Bad frame to %pM\n",
1114 dev->name, buf_addr);
1da177e4
LT		 1115#endif
1116 } else {
1117 struct sk_buff *skb;
1118 int pkt_len = data_size -
1119 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1120 /* To verify: Yellowfin Length should omit the CRC! */
1121
1122#ifndef final_version
1123 if (yellowfin_debug > 4)
1124 printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d"
1125 " of %d, bogus_cnt %d.\n",
1126 pkt_len, data_size, boguscnt);
1127#endif
1128 /* Check if the packet is long enough to just pass up the skbuff
1129 without copying to a properly sized skbuff. */
1130 if (pkt_len > rx_copybreak) {
1131 skb_put(skb = rx_skb, pkt_len);
6aa20a22 1132 pci_unmap_single(yp->pci_dev,
e5a31421 1133 le32_to_cpu(yp->rx_ring[entry].addr),
6aa20a22 1134 yp->rx_buf_sz,
1da177e4
LT		 1135 PCI_DMA_FROMDEVICE);
1136 yp->rx_skbuff[entry] = NULL;
1137 } else {
1138 skb = dev_alloc_skb(pkt_len + 2);
1139 if (skb == NULL)
1140 break;
1da177e4 1141 skb_reserve(skb, 2); /* 16 byte align the IP header */
8c7b7faa 1142 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1da177e4 1143 skb_put(skb, pkt_len);
e5a31421
AV		 1144 pci_dma_sync_single_for_device(yp->pci_dev,
1145 le32_to_cpu(desc->addr),
1146 yp->rx_buf_sz,
1147 PCI_DMA_FROMDEVICE);
1da177e4
LT		 1148 }
1149 skb->protocol = eth_type_trans(skb, dev);
1150 netif_rx(skb);
09f75cd7
JG		 1151 dev->stats.rx_packets++;
1152 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 1153 }
1154 entry = (++yp->cur_rx) % RX_RING_SIZE;
1155 }
1156
1157 /* Refill the Rx ring buffers. */
1158 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1159 entry = yp->dirty_rx % RX_RING_SIZE;
1160 if (yp->rx_skbuff[entry] == NULL) {
1161 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1162 if (skb == NULL)
1163 break; /* Better luck next round. */
1164 yp->rx_skbuff[entry] = skb;
1165 skb->dev = dev; /* Mark as being used by this device. */
1166 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1167 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
689be439 1168 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1169 }
1170 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1171 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1172 if (entry != 0)
1173 yp->rx_ring[entry - 1].dbdma_cmd =
1174 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1175 else
1176 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1177 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1178 | yp->rx_buf_sz);
1179 }
1180
1181 return 0;
1182}
1183
1184static void yellowfin_error(struct net_device *dev, int intr_status)
1185{
1da177e4
LT		 1186 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1187 dev->name, intr_status);
1188 /* Hmmmmm, it's not clear what to do here. */
1189 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
09f75cd7 1190 dev->stats.tx_errors++;
1da177e4 1191 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
09f75cd7 1192 dev->stats.rx_errors++;
1da177e4
LT		 1193}
1194
1195static int yellowfin_close(struct net_device *dev)
1196{
1197 struct yellowfin_private *yp = netdev_priv(dev);
1198 void __iomem *ioaddr = yp->base;
1199 int i;
1200
1201 netif_stop_queue (dev);
1202
1203 if (yellowfin_debug > 1) {
1204 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1205 "Rx %4.4x Int %2.2x.\n",
1206 dev->name, ioread16(ioaddr + TxStatus),
1207 ioread16(ioaddr + RxStatus),
1208 ioread16(ioaddr + IntrStatus));
1209 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1210 dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1211 }
1212
1213 /* Disable interrupts by clearing the interrupt mask. */
1214 iowrite16(0x0000, ioaddr + IntrEnb);
1215
1216 /* Stop the chip's Tx and Rx processes. */
1217 iowrite32(0x80000000, ioaddr + RxCtrl);
1218 iowrite32(0x80000000, ioaddr + TxCtrl);
1219
1220 del_timer(&yp->timer);
1221
1222#if defined(__i386__)
1223 if (yellowfin_debug > 2) {
ad361c98 1224 printk(KERN_DEBUG" Tx ring at %8.8llx:\n",
1da177e4
LT		 1225 (unsigned long long)yp->tx_ring_dma);
1226 for (i = 0; i < TX_RING_SIZE*2; i++)
ad361c98 1227 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1da177e4
LT		 1228 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1229 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1230 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1231 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1232 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98 1233 printk(KERN_DEBUG " #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1da177e4
LT		 1234 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1235 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1236
ad361c98 1237 printk(KERN_DEBUG " Rx ring %8.8llx:\n",
1da177e4
LT		 1238 (unsigned long long)yp->rx_ring_dma);
1239 for (i = 0; i < RX_RING_SIZE; i++) {
1240 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1241 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1242 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1243 yp->rx_ring[i].result_status);
1244 if (yellowfin_debug > 6) {
1245 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1246 int j;
1247 for (j = 0; j < 0x50; j++)
1248 printk(" %4.4x",
1249 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1250 printk("\n");
1251 }
1252 }
1253 }
1254 }
1255#endif /* __i386__ debugging only */
1256
1257 free_irq(dev->irq, dev);
1258
1259 /* Free all the skbuffs in the Rx queue. */
1260 for (i = 0; i < RX_RING_SIZE; i++) {
1261 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
e5a31421 1262 yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1da177e4
LT		 1263 if (yp->rx_skbuff[i]) {
1264 dev_kfree_skb(yp->rx_skbuff[i]);
1265 }
1266 yp->rx_skbuff[i] = NULL;
1267 }
1268 for (i = 0; i < TX_RING_SIZE; i++) {
1269 if (yp->tx_skbuff[i])
1270 dev_kfree_skb(yp->tx_skbuff[i]);
1271 yp->tx_skbuff[i] = NULL;
1272 }
1273
1274#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1275 if (yellowfin_debug > 0) {
1276 printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1277 dev->name, bogus_rx);
1278 }
1279#endif
1280
1281 return 0;
1282}
1283
1da177e4
LT		 1284/* Set or clear the multicast filter for this adaptor. */
1285
1286static void set_rx_mode(struct net_device *dev)
1287{
1288 struct yellowfin_private *yp = netdev_priv(dev);
1289 void __iomem *ioaddr = yp->base;
1290 u16 cfg_value = ioread16(ioaddr + Cnfg);
1291
1292 /* Stop the Rx process to change any value. */
1293 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1294 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 1295 iowrite16(0x000F, ioaddr + AddrMode);
1296 } else if ((dev->mc_count > 64) || (dev->flags & IFF_ALLMULTI)) {
1297 /* Too many to filter well, or accept all multicasts. */
1298 iowrite16(0x000B, ioaddr + AddrMode);
1299 } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1300 struct dev_mc_list *mclist;
1301 u16 hash_table[4];
1302 int i;
1303 memset(hash_table, 0, sizeof(hash_table));
1304 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1305 i++, mclist = mclist->next) {
1306 unsigned int bit;
1307
1308 /* Due to a bug in the early chip versions, multiple filter
1309 slots must be set for each address. */
1310 if (yp->drv_flags & HasMulticastBug) {
1311 bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1312 hash_table[bit >> 4] |= (1 << bit);
1313 bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1314 hash_table[bit >> 4] |= (1 << bit);
1315 bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1316 hash_table[bit >> 4] |= (1 << bit);
1317 }
1318 bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1319 hash_table[bit >> 4] |= (1 << bit);
1320 }
1321 /* Copy the hash table to the chip. */
1322 for (i = 0; i < 4; i++)
1323 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1324 iowrite16(0x0003, ioaddr + AddrMode);
1325 } else { /* Normal, unicast/broadcast-only mode. */
1326 iowrite16(0x0001, ioaddr + AddrMode);
1327 }
1328 /* Restart the Rx process. */
1329 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1330}
1331
1332static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1333{
1334 struct yellowfin_private *np = netdev_priv(dev);
1335 strcpy(info->driver, DRV_NAME);
1336 strcpy(info->version, DRV_VERSION);
1337 strcpy(info->bus_info, pci_name(np->pci_dev));
1338}
1339
7282d491 1340static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1341 .get_drvinfo = yellowfin_get_drvinfo
1342};
1343
1344static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1345{
1346 struct yellowfin_private *np = netdev_priv(dev);
1347 void __iomem *ioaddr = np->base;
1348 struct mii_ioctl_data *data = if_mii(rq);
1349
1350 switch(cmd) {
1351 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1352 data->phy_id = np->phys[0] & 0x1f;
1353 /* Fall Through */
1354
1355 case SIOCGMIIREG: /* Read MII PHY register. */
1356 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1357 return 0;
1358
1359 case SIOCSMIIREG: /* Write MII PHY register. */
1360 if (!capable(CAP_NET_ADMIN))
1361 return -EPERM;
1362 if (data->phy_id == np->phys[0]) {
1363 u16 value = data->val_in;
1364 switch (data->reg_num) {
1365 case 0:
1366 /* Check for autonegotiation on or reset. */
1367 np->medialock = (value & 0x9000) ? 0 : 1;
1368 if (np->medialock)
1369 np->full_duplex = (value & 0x0100) ? 1 : 0;
1370 break;
1371 case 4: np->advertising = value; break;
1372 }
1373 /* Perhaps check_duplex(dev), depending on chip semantics. */
1374 }
1375 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1376 return 0;
1377 default:
1378 return -EOPNOTSUPP;
1379 }
1380}
1381
1382
1383static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1384{
1385 struct net_device *dev = pci_get_drvdata(pdev);
1386 struct yellowfin_private *np;
1387
5d9428de 1388 BUG_ON(!dev);
1da177e4
LT		 1389 np = netdev_priv(dev);
1390
6aa20a22 1391 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1da177e4
LT		 1392 np->tx_status_dma);
1393 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1394 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1395 unregister_netdev (dev);
1396
1397 pci_iounmap(pdev, np->base);
1398
1399 pci_release_regions (pdev);
1400
1401 free_netdev (dev);
1402 pci_set_drvdata(pdev, NULL);
1403}
1404
1405
1406static struct pci_driver yellowfin_driver = {
1407 .name = DRV_NAME,
1408 .id_table = yellowfin_pci_tbl,
1409 .probe = yellowfin_init_one,
1410 .remove = __devexit_p(yellowfin_remove_one),
1411};
1412
1413
1414static int __init yellowfin_init (void)
1415{
1416/* when a module, this is printed whether or not devices are found in probe */
1417#ifdef MODULE
1418 printk(version);
1419#endif
29917620 1420 return pci_register_driver(&yellowfin_driver);
1da177e4
LT		 1421}
1422
1423
1424static void __exit yellowfin_cleanup (void)
1425{
1426 pci_unregister_driver (&yellowfin_driver);
1427}
1428
1429
1430module_init(yellowfin_init);
1431module_exit(yellowfin_cleanup);
Linux 6.x block layer and io_uring tree(s)