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[linux-2.6-block.git] / drivers / net / yellowfin.c
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1da177e4
LT		 1/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2/*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
03a8c661 22 [link no longer provides useful info -jgarzik]
1da177e4 23
1da177e4
LT		 24*/
25
acbbf1f1
JP		 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
1da177e4 28#define DRV_NAME "yellowfin"
d5b20697
AG		 29#define DRV_VERSION "2.1"
30#define DRV_RELDATE "Sep 11, 2006"
1da177e4 31
1da177e4
LT		 32/* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37static int max_interrupt_work = 20;
38static int mtu;
39#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40/* System-wide count of bogus-rx frames. */
41static int bogus_rx;
42static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44#elif defined(YF_NEW) /* A future perfect board :->. */
45static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46static int fifo_cfg = 0x0028;
47#else
f71e1309
AV		 48static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
1da177e4
LT		 50#endif
51
52/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54static int rx_copybreak;
55
56/* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
58 interoperability.
59*/
60#define MAX_UNITS 8 /* More are supported, limit only on options */
61static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
63
64/* Do ugly workaround for GX server chipset errata. */
65static int gx_fix;
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73#define TX_RING_SIZE 16
74#define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75#define RX_RING_SIZE 64
76#define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77#define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
79
80/* Operational parameters that usually are not changed. */
81/* Time in jiffies before concluding the transmitter is hung. */
82#define TX_TIMEOUT (2*HZ)
83#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85#define yellowfin_debug debug
86
87#include <linux/module.h>
88#include <linux/kernel.h>
89#include <linux/string.h>
90#include <linux/timer.h>
91#include <linux/errno.h>
92#include <linux/ioport.h>
93#include <linux/slab.h>
94#include <linux/interrupt.h>
95#include <linux/pci.h>
96#include <linux/init.h>
97#include <linux/mii.h>
98#include <linux/netdevice.h>
99#include <linux/etherdevice.h>
100#include <linux/skbuff.h>
101#include <linux/ethtool.h>
102#include <linux/crc32.h>
103#include <linux/bitops.h>
104#include <asm/uaccess.h>
105#include <asm/processor.h> /* Processor type for cache alignment. */
106#include <asm/unaligned.h>
107#include <asm/io.h>
108
109/* These identify the driver base version and may not be removed. */
7285484a
SH		 110static const char version[] __devinitconst =
111 KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
ad361c98 112 " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
1da177e4
LT		 113
114MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
115MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
116MODULE_LICENSE("GPL");
117
118module_param(max_interrupt_work, int, 0);
119module_param(mtu, int, 0);
120module_param(debug, int, 0);
121module_param(rx_copybreak, int, 0);
122module_param_array(options, int, NULL, 0);
123module_param_array(full_duplex, int, NULL, 0);
124module_param(gx_fix, int, 0);
125MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
126MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
127MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
128MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
129MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
130MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
131MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
132
133/*
134 Theory of Operation
135
136I. Board Compatibility
137
138This device driver is designed for the Packet Engines "Yellowfin" Gigabit
6aa20a22 139Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
1da177e4
LT		 140Symbios 53C885E dual function chip.
141
142II. Board-specific settings
143
144PCI bus devices are configured by the system at boot time, so no jumpers
145need to be set on the board. The system BIOS preferably should assign the
146PCI INTA signal to an otherwise unused system IRQ line.
147Note: Kernel versions earlier than 1.3.73 do not support shared PCI
148interrupt lines.
149
150III. Driver operation
151
152IIIa. Ring buffers
153
154The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
155This is a descriptor list scheme similar to that used by the EEPro100 and
156Tulip. This driver uses two statically allocated fixed-size descriptor lists
157formed into rings by a branch from the final descriptor to the beginning of
158the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
159
160The driver allocates full frame size skbuffs for the Rx ring buffers at
161open() time and passes the skb->data field to the Yellowfin as receive data
162buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
163a fresh skbuff is allocated and the frame is copied to the new skbuff.
164When the incoming frame is larger, the skbuff is passed directly up the
165protocol stack and replaced by a newly allocated skbuff.
166
167The RX_COPYBREAK value is chosen to trade-off the memory wasted by
168using a full-sized skbuff for small frames vs. the copying costs of larger
169frames. For small frames the copying cost is negligible (esp. considering
170that we are pre-loading the cache with immediately useful header
171information). For large frames the copying cost is non-trivial, and the
172larger copy might flush the cache of useful data.
173
174IIIC. Synchronization
175
176The driver runs as two independent, single-threaded flows of control. One
177is the send-packet routine, which enforces single-threaded use by the
178dev->tbusy flag. The other thread is the interrupt handler, which is single
179threaded by the hardware and other software.
180
181The send packet thread has partial control over the Tx ring and 'dev->tbusy'
182flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
183queue slot is empty, it clears the tbusy flag when finished otherwise it sets
184the 'yp->tx_full' flag.
185
186The interrupt handler has exclusive control over the Rx ring and records stats
187from the Tx ring. After reaping the stats, it marks the Tx queue entry as
188empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
189clears both the tx_full and tbusy flags.
190
191IV. Notes
192
193Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
194Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
195and an AlphaStation to verifty the Alpha port!
196
197IVb. References
198
199Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
200Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
201 Data Manual v3.0
202http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
203http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
204
205IVc. Errata
206
207See Packet Engines confidential appendix (prototype chips only).
208*/
209
6aa20a22 210
1da177e4 211
1da177e4
LT		 212enum capability_flags {
213 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
214 HasMACAddrBug=32, /* Only on early revs. */
215 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
216};
c3d8e682 217
1da177e4 218/* The PCI I/O space extent. */
c3d8e682
JG		 219enum {
220 YELLOWFIN_SIZE = 0x100,
221};
1da177e4
LT		 222
223struct pci_id_info {
224 const char *name;
225 struct match_info {
226 int pci, pci_mask, subsystem, subsystem_mask;
227 int revision, revision_mask; /* Only 8 bits. */
228 } id;
1da177e4
LT		 229 int drv_flags; /* Driver use, intended as capability flags. */
230};
231
f71e1309 232static const struct pci_id_info pci_id_tbl[] = {
1da177e4 233 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
1da177e4
LT		 234 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
235 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
c3d8e682 236 HasMII | DontUseEeprom },
1f1bd5fc 237 { }
1da177e4
LT		 238};
239
a3aa1884 240static DEFINE_PCI_DEVICE_TABLE(yellowfin_pci_tbl) = {
1da177e4
LT		 241 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
242 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
1f1bd5fc 243 { }
1da177e4
LT		 244};
245MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
246
247
248/* Offsets to the Yellowfin registers. Various sizes and alignments. */
249enum yellowfin_offsets {
250 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
251 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
252 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
253 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
254 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
255 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
256 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
257 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
258 MII_Status=0xAE,
259 RxDepth=0xB8, FlowCtrl=0xBC,
260 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
261 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
262 EEFeature=0xF5,
263};
264
265/* The Yellowfin Rx and Tx buffer descriptors.
266 Elements are written as 32 bit for endian portability. */
267struct yellowfin_desc {
e5a31421
AV		 268 __le32 dbdma_cmd;
269 __le32 addr;
270 __le32 branch_addr;
271 __le32 result_status;
1da177e4
LT		 272};
273
274struct tx_status_words {
275#ifdef __BIG_ENDIAN
276 u16 tx_errs;
277 u16 tx_cnt;
278 u16 paused;
279 u16 total_tx_cnt;
280#else /* Little endian chips. */
281 u16 tx_cnt;
282 u16 tx_errs;
283 u16 total_tx_cnt;
284 u16 paused;
285#endif /* __BIG_ENDIAN */
286};
287
288/* Bits in yellowfin_desc.cmd */
289enum desc_cmd_bits {
290 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
291 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
292 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
293 BRANCH_IFTRUE=0x040000,
294};
295
296/* Bits in yellowfin_desc.status */
297enum desc_status_bits { RX_EOP=0x0040, };
298
299/* Bits in the interrupt status/mask registers. */
300enum intr_status_bits {
301 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
302 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
303 IntrEarlyRx=0x100, IntrWakeup=0x200, };
304
305#define PRIV_ALIGN 31 /* Required alignment mask */
306#define MII_CNT 4
307struct yellowfin_private {
308 /* Descriptor rings first for alignment.
309 Tx requires a second descriptor for status. */
310 struct yellowfin_desc *rx_ring;
311 struct yellowfin_desc *tx_ring;
312 struct sk_buff* rx_skbuff[RX_RING_SIZE];
313 struct sk_buff* tx_skbuff[TX_RING_SIZE];
314 dma_addr_t rx_ring_dma;
315 dma_addr_t tx_ring_dma;
316
317 struct tx_status_words *tx_status;
318 dma_addr_t tx_status_dma;
319
320 struct timer_list timer; /* Media selection timer. */
1da177e4
LT		 321 /* Frequently used and paired value: keep adjacent for cache effect. */
322 int chip_id, drv_flags;
323 struct pci_dev *pci_dev;
324 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
325 unsigned int rx_buf_sz; /* Based on MTU+slack. */
326 struct tx_status_words *tx_tail_desc;
327 unsigned int cur_tx, dirty_tx;
328 int tx_threshold;
329 unsigned int tx_full:1; /* The Tx queue is full. */
330 unsigned int full_duplex:1; /* Full-duplex operation requested. */
331 unsigned int duplex_lock:1;
332 unsigned int medialock:1; /* Do not sense media. */
333 unsigned int default_port:4; /* Last dev->if_port value. */
334 /* MII transceiver section. */
335 int mii_cnt; /* MII device addresses. */
336 u16 advertising; /* NWay media advertisement */
337 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
338 spinlock_t lock;
339 void __iomem *base;
340};
341
342static int read_eeprom(void __iomem *ioaddr, int location);
343static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
344static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
345static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
346static int yellowfin_open(struct net_device *dev);
347static void yellowfin_timer(unsigned long data);
348static void yellowfin_tx_timeout(struct net_device *dev);
e7a5965a 349static int yellowfin_init_ring(struct net_device *dev);
61357325
SH		 350static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
351 struct net_device *dev);
7d12e780 352static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
1da177e4
LT		 353static int yellowfin_rx(struct net_device *dev);
354static void yellowfin_error(struct net_device *dev, int intr_status);
355static int yellowfin_close(struct net_device *dev);
1da177e4 356static void set_rx_mode(struct net_device *dev);
7282d491 357static const struct ethtool_ops ethtool_ops;
1da177e4 358
bfd82c35
SH		 359static const struct net_device_ops netdev_ops = {
360 .ndo_open = yellowfin_open,
361 .ndo_stop = yellowfin_close,
362 .ndo_start_xmit = yellowfin_start_xmit,
363 .ndo_set_multicast_list = set_rx_mode,
364 .ndo_change_mtu = eth_change_mtu,
365 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 366 .ndo_set_mac_address = eth_mac_addr,
bfd82c35
SH		 367 .ndo_do_ioctl = netdev_ioctl,
368 .ndo_tx_timeout = yellowfin_tx_timeout,
369};
1da177e4
LT		 370
371static int __devinit yellowfin_init_one(struct pci_dev *pdev,
372 const struct pci_device_id *ent)
373{
374 struct net_device *dev;
375 struct yellowfin_private *np;
376 int irq;
377 int chip_idx = ent->driver_data;
378 static int find_cnt;
379 void __iomem *ioaddr;
380 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
381 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
382 void *ring_space;
383 dma_addr_t ring_dma;
384#ifdef USE_IO_OPS
385 int bar = 0;
386#else
387 int bar = 1;
388#endif
6aa20a22 389
1da177e4
LT		 390/* when built into the kernel, we only print version if device is found */
391#ifndef MODULE
392 static int printed_version;
393 if (!printed_version++)
394 printk(version);
395#endif
396
397 i = pci_enable_device(pdev);
398 if (i) return i;
399
400 dev = alloc_etherdev(sizeof(*np));
401 if (!dev) {
acbbf1f1 402 pr_err("cannot allocate ethernet device\n");
1da177e4
LT		 403 return -ENOMEM;
404 }
1da177e4
LT		 405 SET_NETDEV_DEV(dev, &pdev->dev);
406
407 np = netdev_priv(dev);
408
409 if (pci_request_regions(pdev, DRV_NAME))
410 goto err_out_free_netdev;
411
412 pci_set_master (pdev);
413
414 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
415 if (!ioaddr)
416 goto err_out_free_res;
417
418 irq = pdev->irq;
419
420 if (drv_flags & DontUseEeprom)
421 for (i = 0; i < 6; i++)
422 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
423 else {
424 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
425 for (i = 0; i < 6; i++)
426 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
427 }
428
429 /* Reset the chip. */
430 iowrite32(0x80000000, ioaddr + DMACtrl);
431
432 dev->base_addr = (unsigned long)ioaddr;
433 dev->irq = irq;
434
435 pci_set_drvdata(pdev, dev);
436 spin_lock_init(&np->lock);
437
438 np->pci_dev = pdev;
439 np->chip_id = chip_idx;
440 np->drv_flags = drv_flags;
441 np->base = ioaddr;
442
443 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
444 if (!ring_space)
445 goto err_out_cleardev;
446 np->tx_ring = (struct yellowfin_desc *)ring_space;
447 np->tx_ring_dma = ring_dma;
448
449 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
450 if (!ring_space)
451 goto err_out_unmap_tx;
452 np->rx_ring = (struct yellowfin_desc *)ring_space;
453 np->rx_ring_dma = ring_dma;
454
455 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
456 if (!ring_space)
457 goto err_out_unmap_rx;
458 np->tx_status = (struct tx_status_words *)ring_space;
459 np->tx_status_dma = ring_dma;
460
461 if (dev->mem_start)
462 option = dev->mem_start;
463
464 /* The lower four bits are the media type. */
465 if (option > 0) {
466 if (option & 0x200)
467 np->full_duplex = 1;
468 np->default_port = option & 15;
469 if (np->default_port)
470 np->medialock = 1;
471 }
472 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
473 np->full_duplex = 1;
474
475 if (np->full_duplex)
476 np->duplex_lock = 1;
477
478 /* The Yellowfin-specific entries in the device structure. */
bfd82c35 479 dev->netdev_ops = &netdev_ops;
1da177e4 480 SET_ETHTOOL_OPS(dev, &ethtool_ops);
1da177e4
LT		 481 dev->watchdog_timeo = TX_TIMEOUT;
482
483 if (mtu)
484 dev->mtu = mtu;
485
486 i = register_netdev(dev);
487 if (i)
488 goto err_out_unmap_status;
489
acbbf1f1
JP		 490 netdev_info(dev, "%s type %8x at %p, %pM, IRQ %d\n",
491 pci_id_tbl[chip_idx].name,
492 ioread32(ioaddr + ChipRev), ioaddr,
493 dev->dev_addr, irq);
1da177e4
LT		 494
495 if (np->drv_flags & HasMII) {
496 int phy, phy_idx = 0;
497 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
498 int mii_status = mdio_read(ioaddr, phy, 1);
499 if (mii_status != 0xffff && mii_status != 0x0000) {
500 np->phys[phy_idx++] = phy;
501 np->advertising = mdio_read(ioaddr, phy, 4);
acbbf1f1
JP		 502 netdev_info(dev, "MII PHY found at address %d, status 0x%04x advertising %04x\n",
503 phy, mii_status, np->advertising);
1da177e4
LT		 504 }
505 }
506 np->mii_cnt = phy_idx;
507 }
508
509 find_cnt++;
6aa20a22 510
1da177e4
LT		 511 return 0;
512
513err_out_unmap_status:
6aa20a22 514 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1da177e4
LT		 515 np->tx_status_dma);
516err_out_unmap_rx:
517 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
518err_out_unmap_tx:
519 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
520err_out_cleardev:
521 pci_set_drvdata(pdev, NULL);
522 pci_iounmap(pdev, ioaddr);
523err_out_free_res:
524 pci_release_regions(pdev);
525err_out_free_netdev:
526 free_netdev (dev);
527 return -ENODEV;
528}
529
530static int __devinit read_eeprom(void __iomem *ioaddr, int location)
531{
532 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
533
534 iowrite8(location, ioaddr + EEAddr);
535 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
536 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
537 ;
538 return ioread8(ioaddr + EERead);
539}
540
541/* MII Managemen Data I/O accesses.
542 These routines assume the MDIO controller is idle, and do not exit until
543 the command is finished. */
544
545static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
546{
547 int i;
548
549 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
550 iowrite16(1, ioaddr + MII_Cmd);
551 for (i = 10000; i >= 0; i--)
552 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
553 break;
554 return ioread16(ioaddr + MII_Rd_Data);
555}
556
557static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
558{
559 int i;
560
561 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
562 iowrite16(value, ioaddr + MII_Wr_Data);
563
564 /* Wait for the command to finish. */
565 for (i = 10000; i >= 0; i--)
566 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
567 break;
568 return;
569}
570
6aa20a22 571
1da177e4
LT		 572static int yellowfin_open(struct net_device *dev)
573{
574 struct yellowfin_private *yp = netdev_priv(dev);
575 void __iomem *ioaddr = yp->base;
e7a5965a 576 int i, ret;
1da177e4
LT		 577
578 /* Reset the chip. */
579 iowrite32(0x80000000, ioaddr + DMACtrl);
580
a0607fd3 581 ret = request_irq(dev->irq, yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
e7a5965a
RK		 582 if (ret)
583 return ret;
1da177e4
LT		 584
585 if (yellowfin_debug > 1)
acbbf1f1
JP		 586 netdev_printk(KERN_DEBUG, dev, "%s() irq %d\n",
587 __func__, dev->irq);
1da177e4 588
e7a5965a
RK		 589 ret = yellowfin_init_ring(dev);
590 if (ret) {
591 free_irq(dev->irq, dev);
592 return ret;
593 }
1da177e4
LT		 594
595 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
596 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
597
598 for (i = 0; i < 6; i++)
599 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
600
601 /* Set up various condition 'select' registers.
602 There are no options here. */
603 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
604 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
605 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
606 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
607 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
608 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
609
610 /* Initialize other registers: with so many this eventually this will
611 converted to an offset/value list. */
612 iowrite32(dma_ctrl, ioaddr + DMACtrl);
613 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
614 /* Enable automatic generation of flow control frames, period 0xffff. */
615 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
616
617 yp->tx_threshold = 32;
618 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
619
620 if (dev->if_port == 0)
621 dev->if_port = yp->default_port;
622
623 netif_start_queue(dev);
624
625 /* Setting the Rx mode will start the Rx process. */
626 if (yp->drv_flags & IsGigabit) {
627 /* We are always in full-duplex mode with gigabit! */
628 yp->full_duplex = 1;
629 iowrite16(0x01CF, ioaddr + Cnfg);
630 } else {
631 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
632 iowrite16(0x1018, ioaddr + FrameGap1);
633 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
634 }
635 set_rx_mode(dev);
636
637 /* Enable interrupts by setting the interrupt mask. */
638 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
639 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
640 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
641 iowrite32(0x80008000, ioaddr + TxCtrl);
642
643 if (yellowfin_debug > 2) {
acbbf1f1 644 netdev_printk(KERN_DEBUG, dev, "Done %s()\n", __func__);
1da177e4
LT		 645 }
646
647 /* Set the timer to check for link beat. */
648 init_timer(&yp->timer);
649 yp->timer.expires = jiffies + 3*HZ;
650 yp->timer.data = (unsigned long)dev;
651 yp->timer.function = &yellowfin_timer; /* timer handler */
652 add_timer(&yp->timer);
653
654 return 0;
655}
656
657static void yellowfin_timer(unsigned long data)
658{
659 struct net_device *dev = (struct net_device *)data;
660 struct yellowfin_private *yp = netdev_priv(dev);
661 void __iomem *ioaddr = yp->base;
662 int next_tick = 60*HZ;
663
664 if (yellowfin_debug > 3) {
acbbf1f1
JP		 665 netdev_printk(KERN_DEBUG, dev, "Yellowfin timer tick, status %08x\n",
666 ioread16(ioaddr + IntrStatus));
1da177e4
LT		 667 }
668
669 if (yp->mii_cnt) {
670 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
671 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
672 int negotiated = lpa & yp->advertising;
673 if (yellowfin_debug > 1)
acbbf1f1
JP		 674 netdev_printk(KERN_DEBUG, dev, "MII #%d status register is %04x, link partner capability %04x\n",
675 yp->phys[0], bmsr, lpa);
1da177e4
LT		 676
677 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
6aa20a22 678
1da177e4
LT		 679 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
680
681 if (bmsr & BMSR_LSTATUS)
682 next_tick = 60*HZ;
683 else
684 next_tick = 3*HZ;
685 }
686
687 yp->timer.expires = jiffies + next_tick;
688 add_timer(&yp->timer);
689}
690
691static void yellowfin_tx_timeout(struct net_device *dev)
692{
693 struct yellowfin_private *yp = netdev_priv(dev);
694 void __iomem *ioaddr = yp->base;
695
acbbf1f1
JP		 696 netdev_warn(dev, "Yellowfin transmit timed out at %d/%d Tx status %04x, Rx status %04x, resetting...\n",
697 yp->cur_tx, yp->dirty_tx,
698 ioread32(ioaddr + TxStatus),
699 ioread32(ioaddr + RxStatus));
1da177e4
LT		 700
701 /* Note: these should be KERN_DEBUG. */
702 if (yellowfin_debug) {
703 int i;
acbbf1f1 704 pr_warning(" Rx ring %p: ", yp->rx_ring);
1da177e4 705 for (i = 0; i < RX_RING_SIZE; i++)
acbbf1f1
JP		 706 pr_cont(" %08x", yp->rx_ring[i].result_status);
707 pr_cont("\n");
708 pr_warning(" Tx ring %p: ", yp->tx_ring);
1da177e4 709 for (i = 0; i < TX_RING_SIZE; i++)
acbbf1f1 710 pr_cont(" %04x /%08x",
ad361c98
JP		 711 yp->tx_status[i].tx_errs,
712 yp->tx_ring[i].result_status);
acbbf1f1 713 pr_cont("\n");
1da177e4
LT		 714 }
715
716 /* If the hardware is found to hang regularly, we will update the code
717 to reinitialize the chip here. */
718 dev->if_port = 0;
719
720 /* Wake the potentially-idle transmit channel. */
721 iowrite32(0x10001000, yp->base + TxCtrl);
722 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
723 netif_wake_queue (dev); /* Typical path */
724
cdd0db05 725 dev->trans_start = jiffies; /* prevent tx timeout */
09f75cd7 726 dev->stats.tx_errors++;
1da177e4
LT		 727}
728
729/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
e7a5965a 730static int yellowfin_init_ring(struct net_device *dev)
1da177e4
LT		 731{
732 struct yellowfin_private *yp = netdev_priv(dev);
e7a5965a 733 int i, j;
1da177e4
LT		 734
735 yp->tx_full = 0;
736 yp->cur_rx = yp->cur_tx = 0;
737 yp->dirty_tx = 0;
738
739 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
740
741 for (i = 0; i < RX_RING_SIZE; i++) {
742 yp->rx_ring[i].dbdma_cmd =
743 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
744 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
745 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
746 }
747
748 for (i = 0; i < RX_RING_SIZE; i++) {
749 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
750 yp->rx_skbuff[i] = skb;
751 if (skb == NULL)
752 break;
753 skb->dev = dev; /* Mark as being used by this device. */
754 skb_reserve(skb, 2); /* 16 byte align the IP header. */
755 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
689be439 756 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4 757 }
e7a5965a
RK		 758 if (i != RX_RING_SIZE) {
759 for (j = 0; j < i; j++)
760 dev_kfree_skb(yp->rx_skbuff[j]);
761 return -ENOMEM;
762 }
1da177e4
LT		 763 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
764 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
765
766#define NO_TXSTATS
767#ifdef NO_TXSTATS
768 /* In this mode the Tx ring needs only a single descriptor. */
769 for (i = 0; i < TX_RING_SIZE; i++) {
770 yp->tx_skbuff[i] = NULL;
771 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
772 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
773 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
774 }
775 /* Wrap ring */
776 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
777#else
778{
1da177e4
LT		 779 /* Tx ring needs a pair of descriptors, the second for the status. */
780 for (i = 0; i < TX_RING_SIZE; i++) {
781 j = 2*i;
782 yp->tx_skbuff[i] = 0;
783 /* Branch on Tx error. */
784 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
785 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
80950f8b 786 (j+1)*sizeof(struct yellowfin_desc));
1da177e4
LT		 787 j++;
788 if (yp->flags & FullTxStatus) {
789 yp->tx_ring[j].dbdma_cmd =
790 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
791 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
792 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
80950f8b 793 i*sizeof(struct tx_status_words));
1da177e4
LT		 794 } else {
795 /* Symbios chips write only tx_errs word. */
796 yp->tx_ring[j].dbdma_cmd =
797 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
798 yp->tx_ring[j].request_cnt = 2;
799 /* Om pade ummmmm... */
800 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
801 i*sizeof(struct tx_status_words) +
6aa20a22 802 &(yp->tx_status[0].tx_errs) -
1da177e4
LT		 803 &(yp->tx_status[0]));
804 }
6aa20a22 805 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
1da177e4
LT		 806 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
807 }
808 /* Wrap ring */
809 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
810}
811#endif
812 yp->tx_tail_desc = &yp->tx_status[0];
e7a5965a 813 return 0;
1da177e4
LT		 814}
815
61357325
SH		 816static netdev_tx_t yellowfin_start_xmit(struct sk_buff *skb,
817 struct net_device *dev)
1da177e4
LT		 818{
819 struct yellowfin_private *yp = netdev_priv(dev);
820 unsigned entry;
821 int len = skb->len;
822
823 netif_stop_queue (dev);
824
825 /* Note: Ordering is important here, set the field with the
826 "ownership" bit last, and only then increment cur_tx. */
827
828 /* Calculate the next Tx descriptor entry. */
829 entry = yp->cur_tx % TX_RING_SIZE;
830
831 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
832 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
833 /* Fix GX chipset errata. */
834 if (cacheline_end > 24 || cacheline_end == 0) {
835 len = skb->len + 32 - cacheline_end + 1;
5b057c6b
HX		 836 if (skb_padto(skb, len)) {
837 yp->tx_skbuff[entry] = NULL;
838 netif_wake_queue(dev);
6ed10654 839 return NETDEV_TX_OK;
5b057c6b 840 }
1da177e4
LT		 841 }
842 }
843 yp->tx_skbuff[entry] = skb;
844
845#ifdef NO_TXSTATS
6aa20a22 846 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1da177e4
LT		 847 skb->data, len, PCI_DMA_TODEVICE));
848 yp->tx_ring[entry].result_status = 0;
849 if (entry >= TX_RING_SIZE-1) {
850 /* New stop command. */
851 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
852 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
853 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
854 } else {
855 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
856 yp->tx_ring[entry].dbdma_cmd =
857 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
858 }
859 yp->cur_tx++;
860#else
861 yp->tx_ring[entry<<1].request_cnt = len;
6aa20a22 862 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1da177e4 863 skb->data, len, PCI_DMA_TODEVICE));
6aa20a22 864 /* The input_last (status-write) command is constant, but we must
1da177e4
LT		 865 rewrite the subsequent 'stop' command. */
866
867 yp->cur_tx++;
868 {
869 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
870 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
871 }
872 /* Final step -- overwrite the old 'stop' command. */
873
874 yp->tx_ring[entry<<1].dbdma_cmd =
875 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
876 CMD_TX_PKT | BRANCH_IFTRUE) | len);
877#endif
878
879 /* Non-x86 Todo: explicitly flush cache lines here. */
880
881 /* Wake the potentially-idle transmit channel. */
882 iowrite32(0x10001000, yp->base + TxCtrl);
883
884 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
885 netif_start_queue (dev); /* Typical path */
886 else
887 yp->tx_full = 1;
1da177e4
LT		 888
889 if (yellowfin_debug > 4) {
acbbf1f1
JP		 890 netdev_printk(KERN_DEBUG, dev, "Yellowfin transmit frame #%d queued in slot %d\n",
891 yp->cur_tx, entry);
1da177e4 892 }
6ed10654 893 return NETDEV_TX_OK;
1da177e4
LT		 894}
895
896/* The interrupt handler does all of the Rx thread work and cleans up
897 after the Tx thread. */
7d12e780 898static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
1da177e4
LT		 899{
900 struct net_device *dev = dev_instance;
901 struct yellowfin_private *yp;
902 void __iomem *ioaddr;
903 int boguscnt = max_interrupt_work;
904 unsigned int handled = 0;
905
1da177e4
LT		 906 yp = netdev_priv(dev);
907 ioaddr = yp->base;
6aa20a22 908
1da177e4
LT		 909 spin_lock (&yp->lock);
910
911 do {
912 u16 intr_status = ioread16(ioaddr + IntrClear);
913
914 if (yellowfin_debug > 4)
acbbf1f1
JP		 915 netdev_printk(KERN_DEBUG, dev, "Yellowfin interrupt, status %04x\n",
916 intr_status);
1da177e4
LT		 917
918 if (intr_status == 0)
919 break;
920 handled = 1;
921
922 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
923 yellowfin_rx(dev);
924 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
925 }
926
927#ifdef NO_TXSTATS
928 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
929 int entry = yp->dirty_tx % TX_RING_SIZE;
930 struct sk_buff *skb;
931
932 if (yp->tx_ring[entry].result_status == 0)
933 break;
934 skb = yp->tx_skbuff[entry];
09f75cd7
JG		 935 dev->stats.tx_packets++;
936 dev->stats.tx_bytes += skb->len;
1da177e4 937 /* Free the original skb. */
e5a31421 938 pci_unmap_single(yp->pci_dev, le32_to_cpu(yp->tx_ring[entry].addr),
1da177e4
LT		 939 skb->len, PCI_DMA_TODEVICE);
940 dev_kfree_skb_irq(skb);
941 yp->tx_skbuff[entry] = NULL;
942 }
8e95a202
JP		 943 if (yp->tx_full &&
944 yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
1da177e4
LT		 945 /* The ring is no longer full, clear tbusy. */
946 yp->tx_full = 0;
947 netif_wake_queue(dev);
948 }
949#else
950 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
951 unsigned dirty_tx = yp->dirty_tx;
952
953 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
954 dirty_tx++) {
955 /* Todo: optimize this. */
956 int entry = dirty_tx % TX_RING_SIZE;
957 u16 tx_errs = yp->tx_status[entry].tx_errs;
958 struct sk_buff *skb;
959
960#ifndef final_version
961 if (yellowfin_debug > 5)
acbbf1f1
JP		 962 netdev_printk(KERN_DEBUG, dev, "Tx queue %d check, Tx status %04x %04x %04x %04x\n",
963 entry,
964 yp->tx_status[entry].tx_cnt,
965 yp->tx_status[entry].tx_errs,
966 yp->tx_status[entry].total_tx_cnt,
967 yp->tx_status[entry].paused);
1da177e4
LT		 968#endif
969 if (tx_errs == 0)
970 break; /* It still hasn't been Txed */
971 skb = yp->tx_skbuff[entry];
972 if (tx_errs & 0xF810) {
973 /* There was an major error, log it. */
974#ifndef final_version
975 if (yellowfin_debug > 1)
acbbf1f1
JP		 976 netdev_printk(KERN_DEBUG, dev, "Transmit error, Tx status %04x\n",
977 tx_errs);
1da177e4 978#endif
09f75cd7
JG		 979 dev->stats.tx_errors++;
980 if (tx_errs & 0xF800) dev->stats.tx_aborted_errors++;
981 if (tx_errs & 0x0800) dev->stats.tx_carrier_errors++;
982 if (tx_errs & 0x2000) dev->stats.tx_window_errors++;
983 if (tx_errs & 0x8000) dev->stats.tx_fifo_errors++;
1da177e4
LT		 984 } else {
985#ifndef final_version
986 if (yellowfin_debug > 4)
acbbf1f1
JP		 987 netdev_printk(KERN_DEBUG, dev, "Normal transmit, Tx status %04x\n",
988 tx_errs);
1da177e4 989#endif
09f75cd7
JG		 990 dev->stats.tx_bytes += skb->len;
991 dev->stats.collisions += tx_errs & 15;
992 dev->stats.tx_packets++;
1da177e4
LT		 993 }
994 /* Free the original skb. */
6aa20a22
JG		 995 pci_unmap_single(yp->pci_dev,
996 yp->tx_ring[entry<<1].addr, skb->len,
1da177e4
LT		 997 PCI_DMA_TODEVICE);
998 dev_kfree_skb_irq(skb);
999 yp->tx_skbuff[entry] = 0;
1000 /* Mark status as empty. */
1001 yp->tx_status[entry].tx_errs = 0;
1002 }
1003
1004#ifndef final_version
1005 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
acbbf1f1
JP		 1006 netdev_err(dev, "Out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1007 dirty_tx, yp->cur_tx, yp->tx_full);
1da177e4
LT		 1008 dirty_tx += TX_RING_SIZE;
1009 }
1010#endif
1011
8e95a202
JP		 1012 if (yp->tx_full &&
1013 yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1da177e4
LT		 1014 /* The ring is no longer full, clear tbusy. */
1015 yp->tx_full = 0;
1016 netif_wake_queue(dev);
1017 }
1018
1019 yp->dirty_tx = dirty_tx;
1020 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1021 }
1022#endif
1023
1024 /* Log errors and other uncommon events. */
1025 if (intr_status & 0x2ee) /* Abnormal error summary. */
1026 yellowfin_error(dev, intr_status);
1027
1028 if (--boguscnt < 0) {
acbbf1f1
JP		 1029 netdev_warn(dev, "Too much work at interrupt, status=%#04x\n",
1030 intr_status);
1da177e4
LT		 1031 break;
1032 }
1033 } while (1);
1034
1035 if (yellowfin_debug > 3)
acbbf1f1
JP		 1036 netdev_printk(KERN_DEBUG, dev, "exiting interrupt, status=%#04x\n",
1037 ioread16(ioaddr + IntrStatus));
1da177e4
LT		 1038
1039 spin_unlock (&yp->lock);
1040 return IRQ_RETVAL(handled);
1041}
1042
1043/* This routine is logically part of the interrupt handler, but separated
1044 for clarity and better register allocation. */
1045static int yellowfin_rx(struct net_device *dev)
1046{
1047 struct yellowfin_private *yp = netdev_priv(dev);
1048 int entry = yp->cur_rx % RX_RING_SIZE;
1049 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1050
1051 if (yellowfin_debug > 4) {
acbbf1f1 1052 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %08x\n",
1da177e4 1053 entry, yp->rx_ring[entry].result_status);
acbbf1f1 1054 printk(KERN_DEBUG " #%d desc. %08x %08x %08x\n",
1da177e4
LT		 1055 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1056 yp->rx_ring[entry].result_status);
1057 }
1058
1059 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1060 while (1) {
1061 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1062 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1063 s16 frame_status;
1064 u16 desc_status;
1065 int data_size;
1066 u8 *buf_addr;
1067
1068 if(!desc->result_status)
1069 break;
e5a31421 1070 pci_dma_sync_single_for_cpu(yp->pci_dev, le32_to_cpu(desc->addr),
1da177e4
LT		 1071 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1072 desc_status = le32_to_cpu(desc->result_status) >> 16;
689be439 1073 buf_addr = rx_skb->data;
6aa20a22 1074 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1da177e4 1075 le32_to_cpu(desc->result_status)) & 0xffff;
6caf52a4 1076 frame_status = get_unaligned_le16(&(buf_addr[data_size - 2]));
1da177e4 1077 if (yellowfin_debug > 4)
acbbf1f1
JP		 1078 printk(KERN_DEBUG " %s() status was %04x\n",
1079 __func__, frame_status);
1da177e4
LT		 1080 if (--boguscnt < 0)
1081 break;
1082 if ( ! (desc_status & RX_EOP)) {
1083 if (data_size != 0)
acbbf1f1
JP		 1084 netdev_warn(dev, "Oversized Ethernet frame spanned multiple buffers, status %04x, data_size %d!\n",
1085 desc_status, data_size);
09f75cd7 1086 dev->stats.rx_length_errors++;
1da177e4
LT		 1087 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1088 /* There was a error. */
1089 if (yellowfin_debug > 3)
acbbf1f1
JP		 1090 printk(KERN_DEBUG " %s() Rx error was %04x\n",
1091 __func__, frame_status);
09f75cd7
JG		 1092 dev->stats.rx_errors++;
1093 if (frame_status & 0x0060) dev->stats.rx_length_errors++;
1094 if (frame_status & 0x0008) dev->stats.rx_frame_errors++;
1095 if (frame_status & 0x0010) dev->stats.rx_crc_errors++;
1096 if (frame_status < 0) dev->stats.rx_dropped++;
1da177e4
LT		 1097 } else if ( !(yp->drv_flags & IsGigabit) &&
1098 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1099 u8 status1 = buf_addr[data_size-2];
1100 u8 status2 = buf_addr[data_size-1];
09f75cd7
JG		 1101 dev->stats.rx_errors++;
1102 if (status1 & 0xC0) dev->stats.rx_length_errors++;
1103 if (status2 & 0x03) dev->stats.rx_frame_errors++;
1104 if (status2 & 0x04) dev->stats.rx_crc_errors++;
1105 if (status2 & 0x80) dev->stats.rx_dropped++;
1da177e4
LT		 1106#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1107 } else if ((yp->flags & HasMACAddrBug) &&
1108 memcmp(le32_to_cpu(yp->rx_ring_dma +
1109 entry*sizeof(struct yellowfin_desc)),
6aa20a22 1110 dev->dev_addr, 6) != 0 &&
1da177e4
LT		 1111 memcmp(le32_to_cpu(yp->rx_ring_dma +
1112 entry*sizeof(struct yellowfin_desc)),
1113 "\377\377\377\377\377\377", 6) != 0) {
e174961c 1114 if (bogus_rx++ == 0)
acbbf1f1
JP		 1115 netdev_warn(dev, "Bad frame to %pM\n",
1116 buf_addr);
1da177e4
LT		 1117#endif
1118 } else {
1119 struct sk_buff *skb;
1120 int pkt_len = data_size -
1121 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1122 /* To verify: Yellowfin Length should omit the CRC! */
1123
1124#ifndef final_version
1125 if (yellowfin_debug > 4)
acbbf1f1
JP		 1126 printk(KERN_DEBUG " %s() normal Rx pkt length %d of %d, bogus_cnt %d\n",
1127 __func__, pkt_len, data_size, boguscnt);
1da177e4
LT		 1128#endif
1129 /* Check if the packet is long enough to just pass up the skbuff
1130 without copying to a properly sized skbuff. */
1131 if (pkt_len > rx_copybreak) {
1132 skb_put(skb = rx_skb, pkt_len);
6aa20a22 1133 pci_unmap_single(yp->pci_dev,
e5a31421 1134 le32_to_cpu(yp->rx_ring[entry].addr),
6aa20a22 1135 yp->rx_buf_sz,
1da177e4
LT		 1136 PCI_DMA_FROMDEVICE);
1137 yp->rx_skbuff[entry] = NULL;
1138 } else {
1139 skb = dev_alloc_skb(pkt_len + 2);
1140 if (skb == NULL)
1141 break;
1da177e4 1142 skb_reserve(skb, 2); /* 16 byte align the IP header */
8c7b7faa 1143 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1da177e4 1144 skb_put(skb, pkt_len);
e5a31421
AV		 1145 pci_dma_sync_single_for_device(yp->pci_dev,
1146 le32_to_cpu(desc->addr),
1147 yp->rx_buf_sz,
1148 PCI_DMA_FROMDEVICE);
1da177e4
LT		 1149 }
1150 skb->protocol = eth_type_trans(skb, dev);
1151 netif_rx(skb);
09f75cd7
JG		 1152 dev->stats.rx_packets++;
1153 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 1154 }
1155 entry = (++yp->cur_rx) % RX_RING_SIZE;
1156 }
1157
1158 /* Refill the Rx ring buffers. */
1159 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1160 entry = yp->dirty_rx % RX_RING_SIZE;
1161 if (yp->rx_skbuff[entry] == NULL) {
1162 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1163 if (skb == NULL)
1164 break; /* Better luck next round. */
1165 yp->rx_skbuff[entry] = skb;
1166 skb->dev = dev; /* Mark as being used by this device. */
1167 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1168 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
689be439 1169 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1170 }
1171 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1172 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1173 if (entry != 0)
1174 yp->rx_ring[entry - 1].dbdma_cmd =
1175 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1176 else
1177 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1178 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1179 | yp->rx_buf_sz);
1180 }
1181
1182 return 0;
1183}
1184
1185static void yellowfin_error(struct net_device *dev, int intr_status)
1186{
acbbf1f1 1187 netdev_err(dev, "Something Wicked happened! %04x\n", intr_status);
1da177e4
LT		 1188 /* Hmmmmm, it's not clear what to do here. */
1189 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
09f75cd7 1190 dev->stats.tx_errors++;
1da177e4 1191 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
09f75cd7 1192 dev->stats.rx_errors++;
1da177e4
LT		 1193}
1194
1195static int yellowfin_close(struct net_device *dev)
1196{
1197 struct yellowfin_private *yp = netdev_priv(dev);
1198 void __iomem *ioaddr = yp->base;
1199 int i;
1200
1201 netif_stop_queue (dev);
1202
1203 if (yellowfin_debug > 1) {
acbbf1f1
JP		 1204 netdev_printk(KERN_DEBUG, dev, "Shutting down ethercard, status was Tx %04x Rx %04x Int %02x\n",
1205 ioread16(ioaddr + TxStatus),
1206 ioread16(ioaddr + RxStatus),
1207 ioread16(ioaddr + IntrStatus));
1208 netdev_printk(KERN_DEBUG, dev, "Queue pointers were Tx %d / %d, Rx %d / %d\n",
1209 yp->cur_tx, yp->dirty_tx,
1210 yp->cur_rx, yp->dirty_rx);
1da177e4
LT		 1211 }
1212
1213 /* Disable interrupts by clearing the interrupt mask. */
1214 iowrite16(0x0000, ioaddr + IntrEnb);
1215
1216 /* Stop the chip's Tx and Rx processes. */
1217 iowrite32(0x80000000, ioaddr + RxCtrl);
1218 iowrite32(0x80000000, ioaddr + TxCtrl);
1219
1220 del_timer(&yp->timer);
1221
1222#if defined(__i386__)
1223 if (yellowfin_debug > 2) {
acbbf1f1 1224 printk(KERN_DEBUG " Tx ring at %08llx:\n",
1da177e4
LT		 1225 (unsigned long long)yp->tx_ring_dma);
1226 for (i = 0; i < TX_RING_SIZE*2; i++)
acbbf1f1 1227 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x %08x\n",
1da177e4
LT		 1228 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1229 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1230 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1231 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1232 for (i = 0; i < TX_RING_SIZE; i++)
acbbf1f1 1233 printk(KERN_DEBUG " #%d status %04x %04x %04x %04x\n",
1da177e4
LT		 1234 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1235 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1236
acbbf1f1 1237 printk(KERN_DEBUG " Rx ring %08llx:\n",
1da177e4
LT		 1238 (unsigned long long)yp->rx_ring_dma);
1239 for (i = 0; i < RX_RING_SIZE; i++) {
acbbf1f1 1240 printk(KERN_DEBUG " %c #%d desc. %08x %08x %08x\n",
1da177e4
LT		 1241 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1242 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1243 yp->rx_ring[i].result_status);
1244 if (yellowfin_debug > 6) {
1245 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1246 int j;
acbbf1f1
JP		 1247
1248 printk(KERN_DEBUG);
1da177e4 1249 for (j = 0; j < 0x50; j++)
acbbf1f1
JP		 1250 pr_cont(" %04x",
1251 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1252 pr_cont("\n");
1da177e4
LT		 1253 }
1254 }
1255 }
1256 }
1257#endif /* __i386__ debugging only */
1258
1259 free_irq(dev->irq, dev);
1260
1261 /* Free all the skbuffs in the Rx queue. */
1262 for (i = 0; i < RX_RING_SIZE; i++) {
1263 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
e5a31421 1264 yp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
1da177e4
LT		 1265 if (yp->rx_skbuff[i]) {
1266 dev_kfree_skb(yp->rx_skbuff[i]);
1267 }
1268 yp->rx_skbuff[i] = NULL;
1269 }
1270 for (i = 0; i < TX_RING_SIZE; i++) {
1271 if (yp->tx_skbuff[i])
1272 dev_kfree_skb(yp->tx_skbuff[i]);
1273 yp->tx_skbuff[i] = NULL;
1274 }
1275
1276#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1277 if (yellowfin_debug > 0) {
acbbf1f1
JP		 1278 netdev_printk(KERN_DEBUG, dev, "Received %d frames that we should not have\n",
1279 bogus_rx);
1da177e4
LT		 1280 }
1281#endif
1282
1283 return 0;
1284}
1285
1da177e4
LT		 1286/* Set or clear the multicast filter for this adaptor. */
1287
1288static void set_rx_mode(struct net_device *dev)
1289{
1290 struct yellowfin_private *yp = netdev_priv(dev);
1291 void __iomem *ioaddr = yp->base;
1292 u16 cfg_value = ioread16(ioaddr + Cnfg);
1293
1294 /* Stop the Rx process to change any value. */
1295 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1296 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4 1297 iowrite16(0x000F, ioaddr + AddrMode);
4cd24eaf
JP		 1298 } else if ((netdev_mc_count(dev) > 64) ||
1299 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 1300 /* Too many to filter well, or accept all multicasts. */
1301 iowrite16(0x000B, ioaddr + AddrMode);
4cd24eaf 1302 } else if (!netdev_mc_empty(dev)) { /* Must use the multicast hash table. */
22bedad3 1303 struct netdev_hw_addr *ha;
1da177e4
LT		 1304 u16 hash_table[4];
1305 int i;
567ec874 1306
1da177e4 1307 memset(hash_table, 0, sizeof(hash_table));
22bedad3 1308 netdev_for_each_mc_addr(ha, dev) {
1da177e4
LT		 1309 unsigned int bit;
1310
1311 /* Due to a bug in the early chip versions, multiple filter
1312 slots must be set for each address. */
1313 if (yp->drv_flags & HasMulticastBug) {
22bedad3 1314 bit = (ether_crc_le(3, ha->addr) >> 3) & 0x3f;
1da177e4 1315 hash_table[bit >> 4] |= (1 << bit);
22bedad3 1316 bit = (ether_crc_le(4, ha->addr) >> 3) & 0x3f;
1da177e4 1317 hash_table[bit >> 4] |= (1 << bit);
22bedad3 1318 bit = (ether_crc_le(5, ha->addr) >> 3) & 0x3f;
1da177e4
LT		 1319 hash_table[bit >> 4] |= (1 << bit);
1320 }
22bedad3 1321 bit = (ether_crc_le(6, ha->addr) >> 3) & 0x3f;
1da177e4
LT		 1322 hash_table[bit >> 4] |= (1 << bit);
1323 }
1324 /* Copy the hash table to the chip. */
1325 for (i = 0; i < 4; i++)
1326 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1327 iowrite16(0x0003, ioaddr + AddrMode);
1328 } else { /* Normal, unicast/broadcast-only mode. */
1329 iowrite16(0x0001, ioaddr + AddrMode);
1330 }
1331 /* Restart the Rx process. */
1332 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1333}
1334
1335static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1336{
1337 struct yellowfin_private *np = netdev_priv(dev);
1338 strcpy(info->driver, DRV_NAME);
1339 strcpy(info->version, DRV_VERSION);
1340 strcpy(info->bus_info, pci_name(np->pci_dev));
1341}
1342
7282d491 1343static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1344 .get_drvinfo = yellowfin_get_drvinfo
1345};
1346
1347static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1348{
1349 struct yellowfin_private *np = netdev_priv(dev);
1350 void __iomem *ioaddr = np->base;
1351 struct mii_ioctl_data *data = if_mii(rq);
1352
1353 switch(cmd) {
1354 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1355 data->phy_id = np->phys[0] & 0x1f;
1356 /* Fall Through */
1357
1358 case SIOCGMIIREG: /* Read MII PHY register. */
1359 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1360 return 0;
1361
1362 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT		 1363 if (data->phy_id == np->phys[0]) {
1364 u16 value = data->val_in;
1365 switch (data->reg_num) {
1366 case 0:
1367 /* Check for autonegotiation on or reset. */
1368 np->medialock = (value & 0x9000) ? 0 : 1;
1369 if (np->medialock)
1370 np->full_duplex = (value & 0x0100) ? 1 : 0;
1371 break;
1372 case 4: np->advertising = value; break;
1373 }
1374 /* Perhaps check_duplex(dev), depending on chip semantics. */
1375 }
1376 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1377 return 0;
1378 default:
1379 return -EOPNOTSUPP;
1380 }
1381}
1382
1383
1384static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1385{
1386 struct net_device *dev = pci_get_drvdata(pdev);
1387 struct yellowfin_private *np;
1388
5d9428de 1389 BUG_ON(!dev);
1da177e4
LT		 1390 np = netdev_priv(dev);
1391
6aa20a22 1392 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1da177e4
LT		 1393 np->tx_status_dma);
1394 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1395 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1396 unregister_netdev (dev);
1397
1398 pci_iounmap(pdev, np->base);
1399
1400 pci_release_regions (pdev);
1401
1402 free_netdev (dev);
1403 pci_set_drvdata(pdev, NULL);
1404}
1405
1406
1407static struct pci_driver yellowfin_driver = {
1408 .name = DRV_NAME,
1409 .id_table = yellowfin_pci_tbl,
1410 .probe = yellowfin_init_one,
1411 .remove = __devexit_p(yellowfin_remove_one),
1412};
1413
1414
1415static int __init yellowfin_init (void)
1416{
1417/* when a module, this is printed whether or not devices are found in probe */
1418#ifdef MODULE
1419 printk(version);
1420#endif
29917620 1421 return pci_register_driver(&yellowfin_driver);
1da177e4
LT		 1422}
1423
1424
1425static void __exit yellowfin_cleanup (void)
1426{
1427 pci_unregister_driver (&yellowfin_driver);
1428}
1429
1430
1431module_init(yellowfin_init);
1432module_exit(yellowfin_cleanup);
Linux 6.x block layer and io_uring tree(s)