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[NET]: Nuke SET_MODULE_OWNER macro.
[linux-2.6-block.git] / drivers / net / yellowfin.c
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1da177e4
LT		 1/* yellowfin.c: A Packet Engines G-NIC ethernet driver for linux. */
2/*
3 Written 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the Packet Engines G-NIC PCI Gigabit Ethernet adapter.
13 It also supports the Symbios Logic version of the same chip core.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Support and updates available at
21 http://www.scyld.com/network/yellowfin.html
03a8c661 22 [link no longer provides useful info -jgarzik]
1da177e4 23
1da177e4
LT		 24*/
25
26#define DRV_NAME "yellowfin"
d5b20697
AG		 27#define DRV_VERSION "2.1"
28#define DRV_RELDATE "Sep 11, 2006"
1da177e4
LT		 29
30#define PFX DRV_NAME ": "
31
32/* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
37static int max_interrupt_work = 20;
38static int mtu;
39#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
40/* System-wide count of bogus-rx frames. */
41static int bogus_rx;
42static int dma_ctrl = 0x004A0263; /* Constrained by errata */
43static int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
44#elif defined(YF_NEW) /* A future perfect board :->. */
45static int dma_ctrl = 0x00CAC277; /* Override when loading module! */
46static int fifo_cfg = 0x0028;
47#else
f71e1309
AV		 48static const int dma_ctrl = 0x004A0263; /* Constrained by errata */
49static const int fifo_cfg = 0x0020; /* Bypass external Tx FIFO. */
1da177e4
LT		 50#endif
51
52/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
53 Setting to > 1514 effectively disables this feature. */
54static int rx_copybreak;
55
56/* Used to pass the media type, etc.
57 No media types are currently defined. These exist for driver
58 interoperability.
59*/
60#define MAX_UNITS 8 /* More are supported, limit only on options */
61static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
62static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
63
64/* Do ugly workaround for GX server chipset errata. */
65static int gx_fix;
66
67/* Operational parameters that are set at compile time. */
68
69/* Keep the ring sizes a power of two for efficiency.
70 Making the Tx ring too long decreases the effectiveness of channel
71 bonding and packet priority.
72 There are no ill effects from too-large receive rings. */
73#define TX_RING_SIZE 16
74#define TX_QUEUE_SIZE 12 /* Must be > 4 && <= TX_RING_SIZE */
75#define RX_RING_SIZE 64
76#define STATUS_TOTAL_SIZE TX_RING_SIZE*sizeof(struct tx_status_words)
77#define TX_TOTAL_SIZE 2*TX_RING_SIZE*sizeof(struct yellowfin_desc)
78#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct yellowfin_desc)
79
80/* Operational parameters that usually are not changed. */
81/* Time in jiffies before concluding the transmitter is hung. */
82#define TX_TIMEOUT (2*HZ)
83#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
84
85#define yellowfin_debug debug
86
87#include <linux/module.h>
88#include <linux/kernel.h>
89#include <linux/string.h>
90#include <linux/timer.h>
91#include <linux/errno.h>
92#include <linux/ioport.h>
93#include <linux/slab.h>
94#include <linux/interrupt.h>
95#include <linux/pci.h>
96#include <linux/init.h>
97#include <linux/mii.h>
98#include <linux/netdevice.h>
99#include <linux/etherdevice.h>
100#include <linux/skbuff.h>
101#include <linux/ethtool.h>
102#include <linux/crc32.h>
103#include <linux/bitops.h>
104#include <asm/uaccess.h>
105#include <asm/processor.h> /* Processor type for cache alignment. */
106#include <asm/unaligned.h>
107#include <asm/io.h>
108
109/* These identify the driver base version and may not be removed. */
110static char version[] __devinitdata =
111KERN_INFO DRV_NAME ".c:v1.05 1/09/2001 Written by Donald Becker <becker@scyld.com>\n"
1da177e4
LT		 112KERN_INFO " (unofficial 2.4.x port, " DRV_VERSION ", " DRV_RELDATE ")\n";
113
114MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
115MODULE_DESCRIPTION("Packet Engines Yellowfin G-NIC Gigabit Ethernet driver");
116MODULE_LICENSE("GPL");
117
118module_param(max_interrupt_work, int, 0);
119module_param(mtu, int, 0);
120module_param(debug, int, 0);
121module_param(rx_copybreak, int, 0);
122module_param_array(options, int, NULL, 0);
123module_param_array(full_duplex, int, NULL, 0);
124module_param(gx_fix, int, 0);
125MODULE_PARM_DESC(max_interrupt_work, "G-NIC maximum events handled per interrupt");
126MODULE_PARM_DESC(mtu, "G-NIC MTU (all boards)");
127MODULE_PARM_DESC(debug, "G-NIC debug level (0-7)");
128MODULE_PARM_DESC(rx_copybreak, "G-NIC copy breakpoint for copy-only-tiny-frames");
129MODULE_PARM_DESC(options, "G-NIC: Bits 0-3: media type, bit 17: full duplex");
130MODULE_PARM_DESC(full_duplex, "G-NIC full duplex setting(s) (1)");
131MODULE_PARM_DESC(gx_fix, "G-NIC: enable GX server chipset bug workaround (0-1)");
132
133/*
134 Theory of Operation
135
136I. Board Compatibility
137
138This device driver is designed for the Packet Engines "Yellowfin" Gigabit
6aa20a22 139Ethernet adapter. The G-NIC 64-bit PCI card is supported, as well as the
1da177e4
LT		 140Symbios 53C885E dual function chip.
141
142II. Board-specific settings
143
144PCI bus devices are configured by the system at boot time, so no jumpers
145need to be set on the board. The system BIOS preferably should assign the
146PCI INTA signal to an otherwise unused system IRQ line.
147Note: Kernel versions earlier than 1.3.73 do not support shared PCI
148interrupt lines.
149
150III. Driver operation
151
152IIIa. Ring buffers
153
154The Yellowfin uses the Descriptor Based DMA Architecture specified by Apple.
155This is a descriptor list scheme similar to that used by the EEPro100 and
156Tulip. This driver uses two statically allocated fixed-size descriptor lists
157formed into rings by a branch from the final descriptor to the beginning of
158the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
159
160The driver allocates full frame size skbuffs for the Rx ring buffers at
161open() time and passes the skb->data field to the Yellowfin as receive data
162buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
163a fresh skbuff is allocated and the frame is copied to the new skbuff.
164When the incoming frame is larger, the skbuff is passed directly up the
165protocol stack and replaced by a newly allocated skbuff.
166
167The RX_COPYBREAK value is chosen to trade-off the memory wasted by
168using a full-sized skbuff for small frames vs. the copying costs of larger
169frames. For small frames the copying cost is negligible (esp. considering
170that we are pre-loading the cache with immediately useful header
171information). For large frames the copying cost is non-trivial, and the
172larger copy might flush the cache of useful data.
173
174IIIC. Synchronization
175
176The driver runs as two independent, single-threaded flows of control. One
177is the send-packet routine, which enforces single-threaded use by the
178dev->tbusy flag. The other thread is the interrupt handler, which is single
179threaded by the hardware and other software.
180
181The send packet thread has partial control over the Tx ring and 'dev->tbusy'
182flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
183queue slot is empty, it clears the tbusy flag when finished otherwise it sets
184the 'yp->tx_full' flag.
185
186The interrupt handler has exclusive control over the Rx ring and records stats
187from the Tx ring. After reaping the stats, it marks the Tx queue entry as
188empty by incrementing the dirty_tx mark. Iff the 'yp->tx_full' flag is set, it
189clears both the tx_full and tbusy flags.
190
191IV. Notes
192
193Thanks to Kim Stearns of Packet Engines for providing a pair of G-NIC boards.
194Thanks to Bruce Faust of Digitalscape for providing both their SYM53C885 board
195and an AlphaStation to verifty the Alpha port!
196
197IVb. References
198
199Yellowfin Engineering Design Specification, 4/23/97 Preliminary/Confidential
200Symbios SYM53C885 PCI-SCSI/Fast Ethernet Multifunction Controller Preliminary
201 Data Manual v3.0
202http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html
203http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html
204
205IVc. Errata
206
207See Packet Engines confidential appendix (prototype chips only).
208*/
209
6aa20a22 210
1da177e4 211
1da177e4
LT		 212enum capability_flags {
213 HasMII=1, FullTxStatus=2, IsGigabit=4, HasMulticastBug=8, FullRxStatus=16,
214 HasMACAddrBug=32, /* Only on early revs. */
215 DontUseEeprom=64, /* Don't read the MAC from the EEPROm. */
216};
c3d8e682 217
1da177e4 218/* The PCI I/O space extent. */
c3d8e682
JG		 219enum {
220 YELLOWFIN_SIZE = 0x100,
221};
1da177e4
LT		 222
223struct pci_id_info {
224 const char *name;
225 struct match_info {
226 int pci, pci_mask, subsystem, subsystem_mask;
227 int revision, revision_mask; /* Only 8 bits. */
228 } id;
1da177e4
LT		 229 int drv_flags; /* Driver use, intended as capability flags. */
230};
231
f71e1309 232static const struct pci_id_info pci_id_tbl[] = {
1da177e4 233 {"Yellowfin G-NIC Gigabit Ethernet", { 0x07021000, 0xffffffff},
1da177e4
LT		 234 FullTxStatus | IsGigabit | HasMulticastBug | HasMACAddrBug | DontUseEeprom},
235 {"Symbios SYM83C885", { 0x07011000, 0xffffffff},
c3d8e682 236 HasMII | DontUseEeprom },
1f1bd5fc 237 { }
1da177e4
LT		 238};
239
1f1bd5fc 240static const struct pci_device_id yellowfin_pci_tbl[] = {
1da177e4
LT		 241 { 0x1000, 0x0702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
242 { 0x1000, 0x0701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
1f1bd5fc 243 { }
1da177e4
LT		 244};
245MODULE_DEVICE_TABLE (pci, yellowfin_pci_tbl);
246
247
248/* Offsets to the Yellowfin registers. Various sizes and alignments. */
249enum yellowfin_offsets {
250 TxCtrl=0x00, TxStatus=0x04, TxPtr=0x0C,
251 TxIntrSel=0x10, TxBranchSel=0x14, TxWaitSel=0x18,
252 RxCtrl=0x40, RxStatus=0x44, RxPtr=0x4C,
253 RxIntrSel=0x50, RxBranchSel=0x54, RxWaitSel=0x58,
254 EventStatus=0x80, IntrEnb=0x82, IntrClear=0x84, IntrStatus=0x86,
255 ChipRev=0x8C, DMACtrl=0x90, TxThreshold=0x94,
256 Cnfg=0xA0, FrameGap0=0xA2, FrameGap1=0xA4,
257 MII_Cmd=0xA6, MII_Addr=0xA8, MII_Wr_Data=0xAA, MII_Rd_Data=0xAC,
258 MII_Status=0xAE,
259 RxDepth=0xB8, FlowCtrl=0xBC,
260 AddrMode=0xD0, StnAddr=0xD2, HashTbl=0xD8, FIFOcfg=0xF8,
261 EEStatus=0xF0, EECtrl=0xF1, EEAddr=0xF2, EERead=0xF3, EEWrite=0xF4,
262 EEFeature=0xF5,
263};
264
265/* The Yellowfin Rx and Tx buffer descriptors.
266 Elements are written as 32 bit for endian portability. */
267struct yellowfin_desc {
268 u32 dbdma_cmd;
269 u32 addr;
270 u32 branch_addr;
271 u32 result_status;
272};
273
274struct tx_status_words {
275#ifdef __BIG_ENDIAN
276 u16 tx_errs;
277 u16 tx_cnt;
278 u16 paused;
279 u16 total_tx_cnt;
280#else /* Little endian chips. */
281 u16 tx_cnt;
282 u16 tx_errs;
283 u16 total_tx_cnt;
284 u16 paused;
285#endif /* __BIG_ENDIAN */
286};
287
288/* Bits in yellowfin_desc.cmd */
289enum desc_cmd_bits {
290 CMD_TX_PKT=0x10000000, CMD_RX_BUF=0x20000000, CMD_TXSTATUS=0x30000000,
291 CMD_NOP=0x60000000, CMD_STOP=0x70000000,
292 BRANCH_ALWAYS=0x0C0000, INTR_ALWAYS=0x300000, WAIT_ALWAYS=0x030000,
293 BRANCH_IFTRUE=0x040000,
294};
295
296/* Bits in yellowfin_desc.status */
297enum desc_status_bits { RX_EOP=0x0040, };
298
299/* Bits in the interrupt status/mask registers. */
300enum intr_status_bits {
301 IntrRxDone=0x01, IntrRxInvalid=0x02, IntrRxPCIFault=0x04,IntrRxPCIErr=0x08,
302 IntrTxDone=0x10, IntrTxInvalid=0x20, IntrTxPCIFault=0x40,IntrTxPCIErr=0x80,
303 IntrEarlyRx=0x100, IntrWakeup=0x200, };
304
305#define PRIV_ALIGN 31 /* Required alignment mask */
306#define MII_CNT 4
307struct yellowfin_private {
308 /* Descriptor rings first for alignment.
309 Tx requires a second descriptor for status. */
310 struct yellowfin_desc *rx_ring;
311 struct yellowfin_desc *tx_ring;
312 struct sk_buff* rx_skbuff[RX_RING_SIZE];
313 struct sk_buff* tx_skbuff[TX_RING_SIZE];
314 dma_addr_t rx_ring_dma;
315 dma_addr_t tx_ring_dma;
316
317 struct tx_status_words *tx_status;
318 dma_addr_t tx_status_dma;
319
320 struct timer_list timer; /* Media selection timer. */
321 struct net_device_stats stats;
322 /* Frequently used and paired value: keep adjacent for cache effect. */
323 int chip_id, drv_flags;
324 struct pci_dev *pci_dev;
325 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
326 unsigned int rx_buf_sz; /* Based on MTU+slack. */
327 struct tx_status_words *tx_tail_desc;
328 unsigned int cur_tx, dirty_tx;
329 int tx_threshold;
330 unsigned int tx_full:1; /* The Tx queue is full. */
331 unsigned int full_duplex:1; /* Full-duplex operation requested. */
332 unsigned int duplex_lock:1;
333 unsigned int medialock:1; /* Do not sense media. */
334 unsigned int default_port:4; /* Last dev->if_port value. */
335 /* MII transceiver section. */
336 int mii_cnt; /* MII device addresses. */
337 u16 advertising; /* NWay media advertisement */
338 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used */
339 spinlock_t lock;
340 void __iomem *base;
341};
342
343static int read_eeprom(void __iomem *ioaddr, int location);
344static int mdio_read(void __iomem *ioaddr, int phy_id, int location);
345static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value);
346static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
347static int yellowfin_open(struct net_device *dev);
348static void yellowfin_timer(unsigned long data);
349static void yellowfin_tx_timeout(struct net_device *dev);
350static void yellowfin_init_ring(struct net_device *dev);
351static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 352static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance);
1da177e4
LT		 353static int yellowfin_rx(struct net_device *dev);
354static void yellowfin_error(struct net_device *dev, int intr_status);
355static int yellowfin_close(struct net_device *dev);
356static struct net_device_stats *yellowfin_get_stats(struct net_device *dev);
357static void set_rx_mode(struct net_device *dev);
7282d491 358static const struct ethtool_ops ethtool_ops;
1da177e4
LT		 359
360
361static int __devinit yellowfin_init_one(struct pci_dev *pdev,
362 const struct pci_device_id *ent)
363{
364 struct net_device *dev;
365 struct yellowfin_private *np;
366 int irq;
367 int chip_idx = ent->driver_data;
368 static int find_cnt;
369 void __iomem *ioaddr;
370 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
371 int drv_flags = pci_id_tbl[chip_idx].drv_flags;
372 void *ring_space;
373 dma_addr_t ring_dma;
374#ifdef USE_IO_OPS
375 int bar = 0;
376#else
377 int bar = 1;
378#endif
6aa20a22 379
1da177e4
LT		 380/* when built into the kernel, we only print version if device is found */
381#ifndef MODULE
382 static int printed_version;
383 if (!printed_version++)
384 printk(version);
385#endif
386
387 i = pci_enable_device(pdev);
388 if (i) return i;
389
390 dev = alloc_etherdev(sizeof(*np));
391 if (!dev) {
392 printk (KERN_ERR PFX "cannot allocate ethernet device\n");
393 return -ENOMEM;
394 }
1da177e4
LT		 395 SET_NETDEV_DEV(dev, &pdev->dev);
396
397 np = netdev_priv(dev);
398
399 if (pci_request_regions(pdev, DRV_NAME))
400 goto err_out_free_netdev;
401
402 pci_set_master (pdev);
403
404 ioaddr = pci_iomap(pdev, bar, YELLOWFIN_SIZE);
405 if (!ioaddr)
406 goto err_out_free_res;
407
408 irq = pdev->irq;
409
410 if (drv_flags & DontUseEeprom)
411 for (i = 0; i < 6; i++)
412 dev->dev_addr[i] = ioread8(ioaddr + StnAddr + i);
413 else {
414 int ee_offset = (read_eeprom(ioaddr, 6) == 0xff ? 0x100 : 0);
415 for (i = 0; i < 6; i++)
416 dev->dev_addr[i] = read_eeprom(ioaddr, ee_offset + i);
417 }
418
419 /* Reset the chip. */
420 iowrite32(0x80000000, ioaddr + DMACtrl);
421
422 dev->base_addr = (unsigned long)ioaddr;
423 dev->irq = irq;
424
425 pci_set_drvdata(pdev, dev);
426 spin_lock_init(&np->lock);
427
428 np->pci_dev = pdev;
429 np->chip_id = chip_idx;
430 np->drv_flags = drv_flags;
431 np->base = ioaddr;
432
433 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
434 if (!ring_space)
435 goto err_out_cleardev;
436 np->tx_ring = (struct yellowfin_desc *)ring_space;
437 np->tx_ring_dma = ring_dma;
438
439 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
440 if (!ring_space)
441 goto err_out_unmap_tx;
442 np->rx_ring = (struct yellowfin_desc *)ring_space;
443 np->rx_ring_dma = ring_dma;
444
445 ring_space = pci_alloc_consistent(pdev, STATUS_TOTAL_SIZE, &ring_dma);
446 if (!ring_space)
447 goto err_out_unmap_rx;
448 np->tx_status = (struct tx_status_words *)ring_space;
449 np->tx_status_dma = ring_dma;
450
451 if (dev->mem_start)
452 option = dev->mem_start;
453
454 /* The lower four bits are the media type. */
455 if (option > 0) {
456 if (option & 0x200)
457 np->full_duplex = 1;
458 np->default_port = option & 15;
459 if (np->default_port)
460 np->medialock = 1;
461 }
462 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
463 np->full_duplex = 1;
464
465 if (np->full_duplex)
466 np->duplex_lock = 1;
467
468 /* The Yellowfin-specific entries in the device structure. */
469 dev->open = &yellowfin_open;
470 dev->hard_start_xmit = &yellowfin_start_xmit;
471 dev->stop = &yellowfin_close;
472 dev->get_stats = &yellowfin_get_stats;
473 dev->set_multicast_list = &set_rx_mode;
474 dev->do_ioctl = &netdev_ioctl;
475 SET_ETHTOOL_OPS(dev, &ethtool_ops);
476 dev->tx_timeout = yellowfin_tx_timeout;
477 dev->watchdog_timeo = TX_TIMEOUT;
478
479 if (mtu)
480 dev->mtu = mtu;
481
482 i = register_netdev(dev);
483 if (i)
484 goto err_out_unmap_status;
485
486 printk(KERN_INFO "%s: %s type %8x at %p, ",
487 dev->name, pci_id_tbl[chip_idx].name,
488 ioread32(ioaddr + ChipRev), ioaddr);
489 for (i = 0; i < 5; i++)
490 printk("%2.2x:", dev->dev_addr[i]);
491 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
492
493 if (np->drv_flags & HasMII) {
494 int phy, phy_idx = 0;
495 for (phy = 0; phy < 32 && phy_idx < MII_CNT; phy++) {
496 int mii_status = mdio_read(ioaddr, phy, 1);
497 if (mii_status != 0xffff && mii_status != 0x0000) {
498 np->phys[phy_idx++] = phy;
499 np->advertising = mdio_read(ioaddr, phy, 4);
500 printk(KERN_INFO "%s: MII PHY found at address %d, status "
501 "0x%4.4x advertising %4.4x.\n",
502 dev->name, phy, mii_status, np->advertising);
503 }
504 }
505 np->mii_cnt = phy_idx;
506 }
507
508 find_cnt++;
6aa20a22 509
1da177e4
LT		 510 return 0;
511
512err_out_unmap_status:
6aa20a22 513 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1da177e4
LT		 514 np->tx_status_dma);
515err_out_unmap_rx:
516 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
517err_out_unmap_tx:
518 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
519err_out_cleardev:
520 pci_set_drvdata(pdev, NULL);
521 pci_iounmap(pdev, ioaddr);
522err_out_free_res:
523 pci_release_regions(pdev);
524err_out_free_netdev:
525 free_netdev (dev);
526 return -ENODEV;
527}
528
529static int __devinit read_eeprom(void __iomem *ioaddr, int location)
530{
531 int bogus_cnt = 10000; /* Typical 33Mhz: 1050 ticks */
532
533 iowrite8(location, ioaddr + EEAddr);
534 iowrite8(0x30 | ((location >> 8) & 7), ioaddr + EECtrl);
535 while ((ioread8(ioaddr + EEStatus) & 0x80) && --bogus_cnt > 0)
536 ;
537 return ioread8(ioaddr + EERead);
538}
539
540/* MII Managemen Data I/O accesses.
541 These routines assume the MDIO controller is idle, and do not exit until
542 the command is finished. */
543
544static int mdio_read(void __iomem *ioaddr, int phy_id, int location)
545{
546 int i;
547
548 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
549 iowrite16(1, ioaddr + MII_Cmd);
550 for (i = 10000; i >= 0; i--)
551 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
552 break;
553 return ioread16(ioaddr + MII_Rd_Data);
554}
555
556static void mdio_write(void __iomem *ioaddr, int phy_id, int location, int value)
557{
558 int i;
559
560 iowrite16((phy_id<<8) + location, ioaddr + MII_Addr);
561 iowrite16(value, ioaddr + MII_Wr_Data);
562
563 /* Wait for the command to finish. */
564 for (i = 10000; i >= 0; i--)
565 if ((ioread16(ioaddr + MII_Status) & 1) == 0)
566 break;
567 return;
568}
569
6aa20a22 570
1da177e4
LT		 571static int yellowfin_open(struct net_device *dev)
572{
573 struct yellowfin_private *yp = netdev_priv(dev);
574 void __iomem *ioaddr = yp->base;
575 int i;
576
577 /* Reset the chip. */
578 iowrite32(0x80000000, ioaddr + DMACtrl);
579
1fb9df5d 580 i = request_irq(dev->irq, &yellowfin_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 581 if (i) return i;
582
583 if (yellowfin_debug > 1)
584 printk(KERN_DEBUG "%s: yellowfin_open() irq %d.\n",
585 dev->name, dev->irq);
586
587 yellowfin_init_ring(dev);
588
589 iowrite32(yp->rx_ring_dma, ioaddr + RxPtr);
590 iowrite32(yp->tx_ring_dma, ioaddr + TxPtr);
591
592 for (i = 0; i < 6; i++)
593 iowrite8(dev->dev_addr[i], ioaddr + StnAddr + i);
594
595 /* Set up various condition 'select' registers.
596 There are no options here. */
597 iowrite32(0x00800080, ioaddr + TxIntrSel); /* Interrupt on Tx abort */
598 iowrite32(0x00800080, ioaddr + TxBranchSel); /* Branch on Tx abort */
599 iowrite32(0x00400040, ioaddr + TxWaitSel); /* Wait on Tx status */
600 iowrite32(0x00400040, ioaddr + RxIntrSel); /* Interrupt on Rx done */
601 iowrite32(0x00400040, ioaddr + RxBranchSel); /* Branch on Rx error */
602 iowrite32(0x00400040, ioaddr + RxWaitSel); /* Wait on Rx done */
603
604 /* Initialize other registers: with so many this eventually this will
605 converted to an offset/value list. */
606 iowrite32(dma_ctrl, ioaddr + DMACtrl);
607 iowrite16(fifo_cfg, ioaddr + FIFOcfg);
608 /* Enable automatic generation of flow control frames, period 0xffff. */
609 iowrite32(0x0030FFFF, ioaddr + FlowCtrl);
610
611 yp->tx_threshold = 32;
612 iowrite32(yp->tx_threshold, ioaddr + TxThreshold);
613
614 if (dev->if_port == 0)
615 dev->if_port = yp->default_port;
616
617 netif_start_queue(dev);
618
619 /* Setting the Rx mode will start the Rx process. */
620 if (yp->drv_flags & IsGigabit) {
621 /* We are always in full-duplex mode with gigabit! */
622 yp->full_duplex = 1;
623 iowrite16(0x01CF, ioaddr + Cnfg);
624 } else {
625 iowrite16(0x0018, ioaddr + FrameGap0); /* 0060/4060 for non-MII 10baseT */
626 iowrite16(0x1018, ioaddr + FrameGap1);
627 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
628 }
629 set_rx_mode(dev);
630
631 /* Enable interrupts by setting the interrupt mask. */
632 iowrite16(0x81ff, ioaddr + IntrEnb); /* See enum intr_status_bits */
633 iowrite16(0x0000, ioaddr + EventStatus); /* Clear non-interrupting events */
634 iowrite32(0x80008000, ioaddr + RxCtrl); /* Start Rx and Tx channels. */
635 iowrite32(0x80008000, ioaddr + TxCtrl);
636
637 if (yellowfin_debug > 2) {
638 printk(KERN_DEBUG "%s: Done yellowfin_open().\n",
639 dev->name);
640 }
641
642 /* Set the timer to check for link beat. */
643 init_timer(&yp->timer);
644 yp->timer.expires = jiffies + 3*HZ;
645 yp->timer.data = (unsigned long)dev;
646 yp->timer.function = &yellowfin_timer; /* timer handler */
647 add_timer(&yp->timer);
648
649 return 0;
650}
651
652static void yellowfin_timer(unsigned long data)
653{
654 struct net_device *dev = (struct net_device *)data;
655 struct yellowfin_private *yp = netdev_priv(dev);
656 void __iomem *ioaddr = yp->base;
657 int next_tick = 60*HZ;
658
659 if (yellowfin_debug > 3) {
660 printk(KERN_DEBUG "%s: Yellowfin timer tick, status %8.8x.\n",
661 dev->name, ioread16(ioaddr + IntrStatus));
662 }
663
664 if (yp->mii_cnt) {
665 int bmsr = mdio_read(ioaddr, yp->phys[0], MII_BMSR);
666 int lpa = mdio_read(ioaddr, yp->phys[0], MII_LPA);
667 int negotiated = lpa & yp->advertising;
668 if (yellowfin_debug > 1)
669 printk(KERN_DEBUG "%s: MII #%d status register is %4.4x, "
670 "link partner capability %4.4x.\n",
671 dev->name, yp->phys[0], bmsr, lpa);
672
673 yp->full_duplex = mii_duplex(yp->duplex_lock, negotiated);
6aa20a22 674
1da177e4
LT		 675 iowrite16(0x101C | (yp->full_duplex ? 2 : 0), ioaddr + Cnfg);
676
677 if (bmsr & BMSR_LSTATUS)
678 next_tick = 60*HZ;
679 else
680 next_tick = 3*HZ;
681 }
682
683 yp->timer.expires = jiffies + next_tick;
684 add_timer(&yp->timer);
685}
686
687static void yellowfin_tx_timeout(struct net_device *dev)
688{
689 struct yellowfin_private *yp = netdev_priv(dev);
690 void __iomem *ioaddr = yp->base;
691
692 printk(KERN_WARNING "%s: Yellowfin transmit timed out at %d/%d Tx "
693 "status %4.4x, Rx status %4.4x, resetting...\n",
694 dev->name, yp->cur_tx, yp->dirty_tx,
695 ioread32(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
696
697 /* Note: these should be KERN_DEBUG. */
698 if (yellowfin_debug) {
699 int i;
700 printk(KERN_WARNING " Rx ring %p: ", yp->rx_ring);
701 for (i = 0; i < RX_RING_SIZE; i++)
702 printk(" %8.8x", yp->rx_ring[i].result_status);
703 printk("\n"KERN_WARNING" Tx ring %p: ", yp->tx_ring);
704 for (i = 0; i < TX_RING_SIZE; i++)
705 printk(" %4.4x /%8.8x", yp->tx_status[i].tx_errs,
706 yp->tx_ring[i].result_status);
707 printk("\n");
708 }
709
710 /* If the hardware is found to hang regularly, we will update the code
711 to reinitialize the chip here. */
712 dev->if_port = 0;
713
714 /* Wake the potentially-idle transmit channel. */
715 iowrite32(0x10001000, yp->base + TxCtrl);
716 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
717 netif_wake_queue (dev); /* Typical path */
718
719 dev->trans_start = jiffies;
720 yp->stats.tx_errors++;
721}
722
723/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
724static void yellowfin_init_ring(struct net_device *dev)
725{
726 struct yellowfin_private *yp = netdev_priv(dev);
727 int i;
728
729 yp->tx_full = 0;
730 yp->cur_rx = yp->cur_tx = 0;
731 yp->dirty_tx = 0;
732
733 yp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
734
735 for (i = 0; i < RX_RING_SIZE; i++) {
736 yp->rx_ring[i].dbdma_cmd =
737 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
738 yp->rx_ring[i].branch_addr = cpu_to_le32(yp->rx_ring_dma +
739 ((i+1)%RX_RING_SIZE)*sizeof(struct yellowfin_desc));
740 }
741
742 for (i = 0; i < RX_RING_SIZE; i++) {
743 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
744 yp->rx_skbuff[i] = skb;
745 if (skb == NULL)
746 break;
747 skb->dev = dev; /* Mark as being used by this device. */
748 skb_reserve(skb, 2); /* 16 byte align the IP header. */
749 yp->rx_ring[i].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
689be439 750 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT		 751 }
752 yp->rx_ring[i-1].dbdma_cmd = cpu_to_le32(CMD_STOP);
753 yp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
754
755#define NO_TXSTATS
756#ifdef NO_TXSTATS
757 /* In this mode the Tx ring needs only a single descriptor. */
758 for (i = 0; i < TX_RING_SIZE; i++) {
759 yp->tx_skbuff[i] = NULL;
760 yp->tx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
761 yp->tx_ring[i].branch_addr = cpu_to_le32(yp->tx_ring_dma +
762 ((i+1)%TX_RING_SIZE)*sizeof(struct yellowfin_desc));
763 }
764 /* Wrap ring */
765 yp->tx_ring[--i].dbdma_cmd = cpu_to_le32(CMD_STOP | BRANCH_ALWAYS);
766#else
767{
768 int j;
769
770 /* Tx ring needs a pair of descriptors, the second for the status. */
771 for (i = 0; i < TX_RING_SIZE; i++) {
772 j = 2*i;
773 yp->tx_skbuff[i] = 0;
774 /* Branch on Tx error. */
775 yp->tx_ring[j].dbdma_cmd = cpu_to_le32(CMD_STOP);
776 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
777 (j+1)*sizeof(struct yellowfin_desc);
778 j++;
779 if (yp->flags & FullTxStatus) {
780 yp->tx_ring[j].dbdma_cmd =
781 cpu_to_le32(CMD_TXSTATUS | sizeof(*yp->tx_status));
782 yp->tx_ring[j].request_cnt = sizeof(*yp->tx_status);
783 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
784 i*sizeof(struct tx_status_words);
785 } else {
786 /* Symbios chips write only tx_errs word. */
787 yp->tx_ring[j].dbdma_cmd =
788 cpu_to_le32(CMD_TXSTATUS | INTR_ALWAYS | 2);
789 yp->tx_ring[j].request_cnt = 2;
790 /* Om pade ummmmm... */
791 yp->tx_ring[j].addr = cpu_to_le32(yp->tx_status_dma +
792 i*sizeof(struct tx_status_words) +
6aa20a22 793 &(yp->tx_status[0].tx_errs) -
1da177e4
LT		 794 &(yp->tx_status[0]));
795 }
6aa20a22 796 yp->tx_ring[j].branch_addr = cpu_to_le32(yp->tx_ring_dma +
1da177e4
LT		 797 ((j+1)%(2*TX_RING_SIZE))*sizeof(struct yellowfin_desc));
798 }
799 /* Wrap ring */
800 yp->tx_ring[++j].dbdma_cmd |= cpu_to_le32(BRANCH_ALWAYS | INTR_ALWAYS);
801}
802#endif
803 yp->tx_tail_desc = &yp->tx_status[0];
804 return;
805}
806
807static int yellowfin_start_xmit(struct sk_buff *skb, struct net_device *dev)
808{
809 struct yellowfin_private *yp = netdev_priv(dev);
810 unsigned entry;
811 int len = skb->len;
812
813 netif_stop_queue (dev);
814
815 /* Note: Ordering is important here, set the field with the
816 "ownership" bit last, and only then increment cur_tx. */
817
818 /* Calculate the next Tx descriptor entry. */
819 entry = yp->cur_tx % TX_RING_SIZE;
820
821 if (gx_fix) { /* Note: only works for paddable protocols e.g. IP. */
822 int cacheline_end = ((unsigned long)skb->data + skb->len) % 32;
823 /* Fix GX chipset errata. */
824 if (cacheline_end > 24 || cacheline_end == 0) {
825 len = skb->len + 32 - cacheline_end + 1;
5b057c6b
HX		 826 if (skb_padto(skb, len)) {
827 yp->tx_skbuff[entry] = NULL;
828 netif_wake_queue(dev);
829 return 0;
830 }
1da177e4
LT		 831 }
832 }
833 yp->tx_skbuff[entry] = skb;
834
835#ifdef NO_TXSTATS
6aa20a22 836 yp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1da177e4
LT		 837 skb->data, len, PCI_DMA_TODEVICE));
838 yp->tx_ring[entry].result_status = 0;
839 if (entry >= TX_RING_SIZE-1) {
840 /* New stop command. */
841 yp->tx_ring[0].dbdma_cmd = cpu_to_le32(CMD_STOP);
842 yp->tx_ring[TX_RING_SIZE-1].dbdma_cmd =
843 cpu_to_le32(CMD_TX_PKT|BRANCH_ALWAYS | len);
844 } else {
845 yp->tx_ring[entry+1].dbdma_cmd = cpu_to_le32(CMD_STOP);
846 yp->tx_ring[entry].dbdma_cmd =
847 cpu_to_le32(CMD_TX_PKT | BRANCH_IFTRUE | len);
848 }
849 yp->cur_tx++;
850#else
851 yp->tx_ring[entry<<1].request_cnt = len;
6aa20a22 852 yp->tx_ring[entry<<1].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
1da177e4 853 skb->data, len, PCI_DMA_TODEVICE));
6aa20a22 854 /* The input_last (status-write) command is constant, but we must
1da177e4
LT		 855 rewrite the subsequent 'stop' command. */
856
857 yp->cur_tx++;
858 {
859 unsigned next_entry = yp->cur_tx % TX_RING_SIZE;
860 yp->tx_ring[next_entry<<1].dbdma_cmd = cpu_to_le32(CMD_STOP);
861 }
862 /* Final step -- overwrite the old 'stop' command. */
863
864 yp->tx_ring[entry<<1].dbdma_cmd =
865 cpu_to_le32( ((entry % 6) == 0 ? CMD_TX_PKT|INTR_ALWAYS|BRANCH_IFTRUE :
866 CMD_TX_PKT | BRANCH_IFTRUE) | len);
867#endif
868
869 /* Non-x86 Todo: explicitly flush cache lines here. */
870
871 /* Wake the potentially-idle transmit channel. */
872 iowrite32(0x10001000, yp->base + TxCtrl);
873
874 if (yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE)
875 netif_start_queue (dev); /* Typical path */
876 else
877 yp->tx_full = 1;
878 dev->trans_start = jiffies;
879
880 if (yellowfin_debug > 4) {
881 printk(KERN_DEBUG "%s: Yellowfin transmit frame #%d queued in slot %d.\n",
882 dev->name, yp->cur_tx, entry);
883 }
884 return 0;
885}
886
887/* The interrupt handler does all of the Rx thread work and cleans up
888 after the Tx thread. */
7d12e780 889static irqreturn_t yellowfin_interrupt(int irq, void *dev_instance)
1da177e4
LT		 890{
891 struct net_device *dev = dev_instance;
892 struct yellowfin_private *yp;
893 void __iomem *ioaddr;
894 int boguscnt = max_interrupt_work;
895 unsigned int handled = 0;
896
1da177e4
LT		 897 yp = netdev_priv(dev);
898 ioaddr = yp->base;
6aa20a22 899
1da177e4
LT		 900 spin_lock (&yp->lock);
901
902 do {
903 u16 intr_status = ioread16(ioaddr + IntrClear);
904
905 if (yellowfin_debug > 4)
906 printk(KERN_DEBUG "%s: Yellowfin interrupt, status %4.4x.\n",
907 dev->name, intr_status);
908
909 if (intr_status == 0)
910 break;
911 handled = 1;
912
913 if (intr_status & (IntrRxDone | IntrEarlyRx)) {
914 yellowfin_rx(dev);
915 iowrite32(0x10001000, ioaddr + RxCtrl); /* Wake Rx engine. */
916 }
917
918#ifdef NO_TXSTATS
919 for (; yp->cur_tx - yp->dirty_tx > 0; yp->dirty_tx++) {
920 int entry = yp->dirty_tx % TX_RING_SIZE;
921 struct sk_buff *skb;
922
923 if (yp->tx_ring[entry].result_status == 0)
924 break;
925 skb = yp->tx_skbuff[entry];
926 yp->stats.tx_packets++;
927 yp->stats.tx_bytes += skb->len;
928 /* Free the original skb. */
929 pci_unmap_single(yp->pci_dev, yp->tx_ring[entry].addr,
930 skb->len, PCI_DMA_TODEVICE);
931 dev_kfree_skb_irq(skb);
932 yp->tx_skbuff[entry] = NULL;
933 }
934 if (yp->tx_full
935 && yp->cur_tx - yp->dirty_tx < TX_QUEUE_SIZE - 4) {
936 /* The ring is no longer full, clear tbusy. */
937 yp->tx_full = 0;
938 netif_wake_queue(dev);
939 }
940#else
941 if ((intr_status & IntrTxDone) || (yp->tx_tail_desc->tx_errs)) {
942 unsigned dirty_tx = yp->dirty_tx;
943
944 for (dirty_tx = yp->dirty_tx; yp->cur_tx - dirty_tx > 0;
945 dirty_tx++) {
946 /* Todo: optimize this. */
947 int entry = dirty_tx % TX_RING_SIZE;
948 u16 tx_errs = yp->tx_status[entry].tx_errs;
949 struct sk_buff *skb;
950
951#ifndef final_version
952 if (yellowfin_debug > 5)
953 printk(KERN_DEBUG "%s: Tx queue %d check, Tx status "
954 "%4.4x %4.4x %4.4x %4.4x.\n",
955 dev->name, entry,
956 yp->tx_status[entry].tx_cnt,
957 yp->tx_status[entry].tx_errs,
958 yp->tx_status[entry].total_tx_cnt,
959 yp->tx_status[entry].paused);
960#endif
961 if (tx_errs == 0)
962 break; /* It still hasn't been Txed */
963 skb = yp->tx_skbuff[entry];
964 if (tx_errs & 0xF810) {
965 /* There was an major error, log it. */
966#ifndef final_version
967 if (yellowfin_debug > 1)
968 printk(KERN_DEBUG "%s: Transmit error, Tx status %4.4x.\n",
969 dev->name, tx_errs);
970#endif
971 yp->stats.tx_errors++;
972 if (tx_errs & 0xF800) yp->stats.tx_aborted_errors++;
973 if (tx_errs & 0x0800) yp->stats.tx_carrier_errors++;
974 if (tx_errs & 0x2000) yp->stats.tx_window_errors++;
975 if (tx_errs & 0x8000) yp->stats.tx_fifo_errors++;
976 } else {
977#ifndef final_version
978 if (yellowfin_debug > 4)
979 printk(KERN_DEBUG "%s: Normal transmit, Tx status %4.4x.\n",
980 dev->name, tx_errs);
981#endif
982 yp->stats.tx_bytes += skb->len;
983 yp->stats.collisions += tx_errs & 15;
984 yp->stats.tx_packets++;
985 }
986 /* Free the original skb. */
6aa20a22
JG		 987 pci_unmap_single(yp->pci_dev,
988 yp->tx_ring[entry<<1].addr, skb->len,
1da177e4
LT		 989 PCI_DMA_TODEVICE);
990 dev_kfree_skb_irq(skb);
991 yp->tx_skbuff[entry] = 0;
992 /* Mark status as empty. */
993 yp->tx_status[entry].tx_errs = 0;
994 }
995
996#ifndef final_version
997 if (yp->cur_tx - dirty_tx > TX_RING_SIZE) {
998 printk(KERN_ERR "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
999 dev->name, dirty_tx, yp->cur_tx, yp->tx_full);
1000 dirty_tx += TX_RING_SIZE;
1001 }
1002#endif
1003
1004 if (yp->tx_full
1005 && yp->cur_tx - dirty_tx < TX_QUEUE_SIZE - 2) {
1006 /* The ring is no longer full, clear tbusy. */
1007 yp->tx_full = 0;
1008 netif_wake_queue(dev);
1009 }
1010
1011 yp->dirty_tx = dirty_tx;
1012 yp->tx_tail_desc = &yp->tx_status[dirty_tx % TX_RING_SIZE];
1013 }
1014#endif
1015
1016 /* Log errors and other uncommon events. */
1017 if (intr_status & 0x2ee) /* Abnormal error summary. */
1018 yellowfin_error(dev, intr_status);
1019
1020 if (--boguscnt < 0) {
1021 printk(KERN_WARNING "%s: Too much work at interrupt, "
1022 "status=0x%4.4x.\n",
1023 dev->name, intr_status);
1024 break;
1025 }
1026 } while (1);
1027
1028 if (yellowfin_debug > 3)
1029 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1030 dev->name, ioread16(ioaddr + IntrStatus));
1031
1032 spin_unlock (&yp->lock);
1033 return IRQ_RETVAL(handled);
1034}
1035
1036/* This routine is logically part of the interrupt handler, but separated
1037 for clarity and better register allocation. */
1038static int yellowfin_rx(struct net_device *dev)
1039{
1040 struct yellowfin_private *yp = netdev_priv(dev);
1041 int entry = yp->cur_rx % RX_RING_SIZE;
1042 int boguscnt = yp->dirty_rx + RX_RING_SIZE - yp->cur_rx;
1043
1044 if (yellowfin_debug > 4) {
1045 printk(KERN_DEBUG " In yellowfin_rx(), entry %d status %8.8x.\n",
1046 entry, yp->rx_ring[entry].result_status);
1047 printk(KERN_DEBUG " #%d desc. %8.8x %8.8x %8.8x.\n",
1048 entry, yp->rx_ring[entry].dbdma_cmd, yp->rx_ring[entry].addr,
1049 yp->rx_ring[entry].result_status);
1050 }
1051
1052 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1053 while (1) {
1054 struct yellowfin_desc *desc = &yp->rx_ring[entry];
1055 struct sk_buff *rx_skb = yp->rx_skbuff[entry];
1056 s16 frame_status;
1057 u16 desc_status;
1058 int data_size;
1059 u8 *buf_addr;
1060
1061 if(!desc->result_status)
1062 break;
1063 pci_dma_sync_single_for_cpu(yp->pci_dev, desc->addr,
1064 yp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1065 desc_status = le32_to_cpu(desc->result_status) >> 16;
689be439 1066 buf_addr = rx_skb->data;
6aa20a22 1067 data_size = (le32_to_cpu(desc->dbdma_cmd) -
1da177e4
LT		 1068 le32_to_cpu(desc->result_status)) & 0xffff;
1069 frame_status = le16_to_cpu(get_unaligned((s16*)&(buf_addr[data_size - 2])));
1070 if (yellowfin_debug > 4)
1071 printk(KERN_DEBUG " yellowfin_rx() status was %4.4x.\n",
1072 frame_status);
1073 if (--boguscnt < 0)
1074 break;
1075 if ( ! (desc_status & RX_EOP)) {
1076 if (data_size != 0)
1077 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned multiple buffers,"
1078 " status %4.4x, data_size %d!\n", dev->name, desc_status, data_size);
1079 yp->stats.rx_length_errors++;
1080 } else if ((yp->drv_flags & IsGigabit) && (frame_status & 0x0038)) {
1081 /* There was a error. */
1082 if (yellowfin_debug > 3)
1083 printk(KERN_DEBUG " yellowfin_rx() Rx error was %4.4x.\n",
1084 frame_status);
1085 yp->stats.rx_errors++;
1086 if (frame_status & 0x0060) yp->stats.rx_length_errors++;
1087 if (frame_status & 0x0008) yp->stats.rx_frame_errors++;
1088 if (frame_status & 0x0010) yp->stats.rx_crc_errors++;
1089 if (frame_status < 0) yp->stats.rx_dropped++;
1090 } else if ( !(yp->drv_flags & IsGigabit) &&
1091 ((buf_addr[data_size-1] & 0x85) || buf_addr[data_size-2] & 0xC0)) {
1092 u8 status1 = buf_addr[data_size-2];
1093 u8 status2 = buf_addr[data_size-1];
1094 yp->stats.rx_errors++;
1095 if (status1 & 0xC0) yp->stats.rx_length_errors++;
1096 if (status2 & 0x03) yp->stats.rx_frame_errors++;
1097 if (status2 & 0x04) yp->stats.rx_crc_errors++;
1098 if (status2 & 0x80) yp->stats.rx_dropped++;
1099#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1100 } else if ((yp->flags & HasMACAddrBug) &&
1101 memcmp(le32_to_cpu(yp->rx_ring_dma +
1102 entry*sizeof(struct yellowfin_desc)),
6aa20a22 1103 dev->dev_addr, 6) != 0 &&
1da177e4
LT		 1104 memcmp(le32_to_cpu(yp->rx_ring_dma +
1105 entry*sizeof(struct yellowfin_desc)),
1106 "\377\377\377\377\377\377", 6) != 0) {
1107 if (bogus_rx++ == 0)
1108 printk(KERN_WARNING "%s: Bad frame to %2.2x:%2.2x:%2.2x:%2.2x:"
1109 "%2.2x:%2.2x.\n",
1110 dev->name, buf_addr[0], buf_addr[1], buf_addr[2],
1111 buf_addr[3], buf_addr[4], buf_addr[5]);
1112#endif
1113 } else {
1114 struct sk_buff *skb;
1115 int pkt_len = data_size -
1116 (yp->chip_id ? 7 : 8 + buf_addr[data_size - 8]);
1117 /* To verify: Yellowfin Length should omit the CRC! */
1118
1119#ifndef final_version
1120 if (yellowfin_debug > 4)
1121 printk(KERN_DEBUG " yellowfin_rx() normal Rx pkt length %d"
1122 " of %d, bogus_cnt %d.\n",
1123 pkt_len, data_size, boguscnt);
1124#endif
1125 /* Check if the packet is long enough to just pass up the skbuff
1126 without copying to a properly sized skbuff. */
1127 if (pkt_len > rx_copybreak) {
1128 skb_put(skb = rx_skb, pkt_len);
6aa20a22
JG		 1129 pci_unmap_single(yp->pci_dev,
1130 yp->rx_ring[entry].addr,
1131 yp->rx_buf_sz,
1da177e4
LT		 1132 PCI_DMA_FROMDEVICE);
1133 yp->rx_skbuff[entry] = NULL;
1134 } else {
1135 skb = dev_alloc_skb(pkt_len + 2);
1136 if (skb == NULL)
1137 break;
1da177e4 1138 skb_reserve(skb, 2); /* 16 byte align the IP header */
8c7b7faa 1139 skb_copy_to_linear_data(skb, rx_skb->data, pkt_len);
1da177e4
LT		 1140 skb_put(skb, pkt_len);
1141 pci_dma_sync_single_for_device(yp->pci_dev, desc->addr,
1142 yp->rx_buf_sz,
1143 PCI_DMA_FROMDEVICE);
1144 }
1145 skb->protocol = eth_type_trans(skb, dev);
1146 netif_rx(skb);
1147 dev->last_rx = jiffies;
1148 yp->stats.rx_packets++;
1149 yp->stats.rx_bytes += pkt_len;
1150 }
1151 entry = (++yp->cur_rx) % RX_RING_SIZE;
1152 }
1153
1154 /* Refill the Rx ring buffers. */
1155 for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
1156 entry = yp->dirty_rx % RX_RING_SIZE;
1157 if (yp->rx_skbuff[entry] == NULL) {
1158 struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
1159 if (skb == NULL)
1160 break; /* Better luck next round. */
1161 yp->rx_skbuff[entry] = skb;
1162 skb->dev = dev; /* Mark as being used by this device. */
1163 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1164 yp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(yp->pci_dev,
689be439 1165 skb->data, yp->rx_buf_sz, PCI_DMA_FROMDEVICE));
1da177e4
LT		 1166 }
1167 yp->rx_ring[entry].dbdma_cmd = cpu_to_le32(CMD_STOP);
1168 yp->rx_ring[entry].result_status = 0; /* Clear complete bit. */
1169 if (entry != 0)
1170 yp->rx_ring[entry - 1].dbdma_cmd =
1171 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | yp->rx_buf_sz);
1172 else
1173 yp->rx_ring[RX_RING_SIZE - 1].dbdma_cmd =
1174 cpu_to_le32(CMD_RX_BUF | INTR_ALWAYS | BRANCH_ALWAYS
1175 | yp->rx_buf_sz);
1176 }
1177
1178 return 0;
1179}
1180
1181static void yellowfin_error(struct net_device *dev, int intr_status)
1182{
1183 struct yellowfin_private *yp = netdev_priv(dev);
1184
1185 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1186 dev->name, intr_status);
1187 /* Hmmmmm, it's not clear what to do here. */
1188 if (intr_status & (IntrTxPCIErr | IntrTxPCIFault))
1189 yp->stats.tx_errors++;
1190 if (intr_status & (IntrRxPCIErr | IntrRxPCIFault))
1191 yp->stats.rx_errors++;
1192}
1193
1194static int yellowfin_close(struct net_device *dev)
1195{
1196 struct yellowfin_private *yp = netdev_priv(dev);
1197 void __iomem *ioaddr = yp->base;
1198 int i;
1199
1200 netif_stop_queue (dev);
1201
1202 if (yellowfin_debug > 1) {
1203 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %4.4x "
1204 "Rx %4.4x Int %2.2x.\n",
1205 dev->name, ioread16(ioaddr + TxStatus),
1206 ioread16(ioaddr + RxStatus),
1207 ioread16(ioaddr + IntrStatus));
1208 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1209 dev->name, yp->cur_tx, yp->dirty_tx, yp->cur_rx, yp->dirty_rx);
1210 }
1211
1212 /* Disable interrupts by clearing the interrupt mask. */
1213 iowrite16(0x0000, ioaddr + IntrEnb);
1214
1215 /* Stop the chip's Tx and Rx processes. */
1216 iowrite32(0x80000000, ioaddr + RxCtrl);
1217 iowrite32(0x80000000, ioaddr + TxCtrl);
1218
1219 del_timer(&yp->timer);
1220
1221#if defined(__i386__)
1222 if (yellowfin_debug > 2) {
1223 printk("\n"KERN_DEBUG" Tx ring at %8.8llx:\n",
1224 (unsigned long long)yp->tx_ring_dma);
1225 for (i = 0; i < TX_RING_SIZE*2; i++)
1226 printk(" %c #%d desc. %8.8x %8.8x %8.8x %8.8x.\n",
1227 ioread32(ioaddr + TxPtr) == (long)&yp->tx_ring[i] ? '>' : ' ',
1228 i, yp->tx_ring[i].dbdma_cmd, yp->tx_ring[i].addr,
1229 yp->tx_ring[i].branch_addr, yp->tx_ring[i].result_status);
1230 printk(KERN_DEBUG " Tx status %p:\n", yp->tx_status);
1231 for (i = 0; i < TX_RING_SIZE; i++)
1232 printk(" #%d status %4.4x %4.4x %4.4x %4.4x.\n",
1233 i, yp->tx_status[i].tx_cnt, yp->tx_status[i].tx_errs,
1234 yp->tx_status[i].total_tx_cnt, yp->tx_status[i].paused);
1235
1236 printk("\n"KERN_DEBUG " Rx ring %8.8llx:\n",
1237 (unsigned long long)yp->rx_ring_dma);
1238 for (i = 0; i < RX_RING_SIZE; i++) {
1239 printk(KERN_DEBUG " %c #%d desc. %8.8x %8.8x %8.8x\n",
1240 ioread32(ioaddr + RxPtr) == (long)&yp->rx_ring[i] ? '>' : ' ',
1241 i, yp->rx_ring[i].dbdma_cmd, yp->rx_ring[i].addr,
1242 yp->rx_ring[i].result_status);
1243 if (yellowfin_debug > 6) {
1244 if (get_unaligned((u8*)yp->rx_ring[i].addr) != 0x69) {
1245 int j;
1246 for (j = 0; j < 0x50; j++)
1247 printk(" %4.4x",
1248 get_unaligned(((u16*)yp->rx_ring[i].addr) + j));
1249 printk("\n");
1250 }
1251 }
1252 }
1253 }
1254#endif /* __i386__ debugging only */
1255
1256 free_irq(dev->irq, dev);
1257
1258 /* Free all the skbuffs in the Rx queue. */
1259 for (i = 0; i < RX_RING_SIZE; i++) {
1260 yp->rx_ring[i].dbdma_cmd = cpu_to_le32(CMD_STOP);
1261 yp->rx_ring[i].addr = 0xBADF00D0; /* An invalid address. */
1262 if (yp->rx_skbuff[i]) {
1263 dev_kfree_skb(yp->rx_skbuff[i]);
1264 }
1265 yp->rx_skbuff[i] = NULL;
1266 }
1267 for (i = 0; i < TX_RING_SIZE; i++) {
1268 if (yp->tx_skbuff[i])
1269 dev_kfree_skb(yp->tx_skbuff[i]);
1270 yp->tx_skbuff[i] = NULL;
1271 }
1272
1273#ifdef YF_PROTOTYPE /* Support for prototype hardware errata. */
1274 if (yellowfin_debug > 0) {
1275 printk(KERN_DEBUG "%s: Received %d frames that we should not have.\n",
1276 dev->name, bogus_rx);
1277 }
1278#endif
1279
1280 return 0;
1281}
1282
1283static struct net_device_stats *yellowfin_get_stats(struct net_device *dev)
1284{
1285 struct yellowfin_private *yp = netdev_priv(dev);
1286 return &yp->stats;
1287}
1288
1289/* Set or clear the multicast filter for this adaptor. */
1290
1291static void set_rx_mode(struct net_device *dev)
1292{
1293 struct yellowfin_private *yp = netdev_priv(dev);
1294 void __iomem *ioaddr = yp->base;
1295 u16 cfg_value = ioread16(ioaddr + Cnfg);
1296
1297 /* Stop the Rx process to change any value. */
1298 iowrite16(cfg_value & ~0x1000, ioaddr + Cnfg);
1299 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 1300 iowrite16(0x000F, ioaddr + AddrMode);
1301 } else if ((dev->mc_count > 64) || (dev->flags & IFF_ALLMULTI)) {
1302 /* Too many to filter well, or accept all multicasts. */
1303 iowrite16(0x000B, ioaddr + AddrMode);
1304 } else if (dev->mc_count > 0) { /* Must use the multicast hash table. */
1305 struct dev_mc_list *mclist;
1306 u16 hash_table[4];
1307 int i;
1308 memset(hash_table, 0, sizeof(hash_table));
1309 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1310 i++, mclist = mclist->next) {
1311 unsigned int bit;
1312
1313 /* Due to a bug in the early chip versions, multiple filter
1314 slots must be set for each address. */
1315 if (yp->drv_flags & HasMulticastBug) {
1316 bit = (ether_crc_le(3, mclist->dmi_addr) >> 3) & 0x3f;
1317 hash_table[bit >> 4] |= (1 << bit);
1318 bit = (ether_crc_le(4, mclist->dmi_addr) >> 3) & 0x3f;
1319 hash_table[bit >> 4] |= (1 << bit);
1320 bit = (ether_crc_le(5, mclist->dmi_addr) >> 3) & 0x3f;
1321 hash_table[bit >> 4] |= (1 << bit);
1322 }
1323 bit = (ether_crc_le(6, mclist->dmi_addr) >> 3) & 0x3f;
1324 hash_table[bit >> 4] |= (1 << bit);
1325 }
1326 /* Copy the hash table to the chip. */
1327 for (i = 0; i < 4; i++)
1328 iowrite16(hash_table[i], ioaddr + HashTbl + i*2);
1329 iowrite16(0x0003, ioaddr + AddrMode);
1330 } else { /* Normal, unicast/broadcast-only mode. */
1331 iowrite16(0x0001, ioaddr + AddrMode);
1332 }
1333 /* Restart the Rx process. */
1334 iowrite16(cfg_value | 0x1000, ioaddr + Cnfg);
1335}
1336
1337static void yellowfin_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1338{
1339 struct yellowfin_private *np = netdev_priv(dev);
1340 strcpy(info->driver, DRV_NAME);
1341 strcpy(info->version, DRV_VERSION);
1342 strcpy(info->bus_info, pci_name(np->pci_dev));
1343}
1344
7282d491 1345static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1346 .get_drvinfo = yellowfin_get_drvinfo
1347};
1348
1349static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1350{
1351 struct yellowfin_private *np = netdev_priv(dev);
1352 void __iomem *ioaddr = np->base;
1353 struct mii_ioctl_data *data = if_mii(rq);
1354
1355 switch(cmd) {
1356 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1357 data->phy_id = np->phys[0] & 0x1f;
1358 /* Fall Through */
1359
1360 case SIOCGMIIREG: /* Read MII PHY register. */
1361 data->val_out = mdio_read(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f);
1362 return 0;
1363
1364 case SIOCSMIIREG: /* Write MII PHY register. */
1365 if (!capable(CAP_NET_ADMIN))
1366 return -EPERM;
1367 if (data->phy_id == np->phys[0]) {
1368 u16 value = data->val_in;
1369 switch (data->reg_num) {
1370 case 0:
1371 /* Check for autonegotiation on or reset. */
1372 np->medialock = (value & 0x9000) ? 0 : 1;
1373 if (np->medialock)
1374 np->full_duplex = (value & 0x0100) ? 1 : 0;
1375 break;
1376 case 4: np->advertising = value; break;
1377 }
1378 /* Perhaps check_duplex(dev), depending on chip semantics. */
1379 }
1380 mdio_write(ioaddr, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1381 return 0;
1382 default:
1383 return -EOPNOTSUPP;
1384 }
1385}
1386
1387
1388static void __devexit yellowfin_remove_one (struct pci_dev *pdev)
1389{
1390 struct net_device *dev = pci_get_drvdata(pdev);
1391 struct yellowfin_private *np;
1392
5d9428de 1393 BUG_ON(!dev);
1da177e4
LT		 1394 np = netdev_priv(dev);
1395
6aa20a22 1396 pci_free_consistent(pdev, STATUS_TOTAL_SIZE, np->tx_status,
1da177e4
LT		 1397 np->tx_status_dma);
1398 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
1399 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
1400 unregister_netdev (dev);
1401
1402 pci_iounmap(pdev, np->base);
1403
1404 pci_release_regions (pdev);
1405
1406 free_netdev (dev);
1407 pci_set_drvdata(pdev, NULL);
1408}
1409
1410
1411static struct pci_driver yellowfin_driver = {
1412 .name = DRV_NAME,
1413 .id_table = yellowfin_pci_tbl,
1414 .probe = yellowfin_init_one,
1415 .remove = __devexit_p(yellowfin_remove_one),
1416};
1417
1418
1419static int __init yellowfin_init (void)
1420{
1421/* when a module, this is printed whether or not devices are found in probe */
1422#ifdef MODULE
1423 printk(version);
1424#endif
29917620 1425 return pci_register_driver(&yellowfin_driver);
1da177e4
LT		 1426}
1427
1428
1429static void __exit yellowfin_cleanup (void)
1430{
1431 pci_unregister_driver (&yellowfin_driver);
1432}
1433
1434
1435module_init(yellowfin_init);
1436module_exit(yellowfin_cleanup);
6aa20a22 1437
1da177e4
LT		 1438/*
1439 * Local variables:
1440 * compile-command: "gcc -DMODULE -Wall -Wstrict-prototypes -O6 -c yellowfin.c"
1441 * compile-command-alphaLX: "gcc -DMODULE -Wall -Wstrict-prototypes -O2 -c yellowfin.c -fomit-frame-pointer -fno-strength-reduce -mno-fp-regs -Wa,-m21164a -DBWX_USABLE -DBWIO_ENABLED"
1442 * simple-compile-command: "gcc -DMODULE -O6 -c yellowfin.c"
1443 * c-indent-level: 4
1444 * c-basic-offset: 4
1445 * tab-width: 4
1446 * End:
1447 */
Linux 6.x block layer and io_uring tree(s)