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ath9k: use new FIF_PSPOLL configure filter
[linux-2.6-block.git] / drivers / net / wireless / zd1211rw / zd_chip.c
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66bb42fd
DD		 1/* ZD1211 USB-WLAN driver for Linux
2 *
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
e85d0918
DD		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21/* This file implements all the hardware specific functions for the ZD1211
22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
24 */
25
26#include <linux/kernel.h>
27#include <linux/errno.h>
28
29#include "zd_def.h"
30#include "zd_chip.h"
e85d0918
DD		 31#include "zd_mac.h"
32#include "zd_rf.h"
e85d0918
DD		 33
34void zd_chip_init(struct zd_chip *chip,
459c51ad 35 struct ieee80211_hw *hw,
e85d0918
DD		 36 struct usb_interface *intf)
37{
38 memset(chip, 0, sizeof(*chip));
39 mutex_init(&chip->mutex);
459c51ad 40 zd_usb_init(&chip->usb, hw, intf);
e85d0918
DD		 41 zd_rf_init(&chip->rf);
42}
43
44void zd_chip_clear(struct zd_chip *chip)
45{
c48cf125 46 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
e85d0918
DD		 47 zd_usb_clear(&chip->usb);
48 zd_rf_clear(&chip->rf);
e85d0918 49 mutex_destroy(&chip->mutex);
c48cf125 50 ZD_MEMCLEAR(chip, sizeof(*chip));
e85d0918
DD		 51}
52
74553aed 53static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
e85d0918 54{
459c51ad 55 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
e85d0918
DD		 56 return scnprintf(buffer, size, "%02x-%02x-%02x",
57 addr[0], addr[1], addr[2]);
58}
59
60/* Prints an identifier line, which will support debugging. */
61static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
62{
63 int i = 0;
64
65 i = scnprintf(buffer, size, "zd1211%s chip ",
74553aed 66 zd_chip_is_zd1211b(chip) ? "b" : "");
e85d0918
DD		 67 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
74553aed 69 i += scnprint_mac_oui(chip, buffer+i, size-i);
e85d0918
DD		 70 i += scnprintf(buffer+i, size-i, " ");
71 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
f2a81a16 72 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
e85d0918
DD		 73 chip->patch_cck_gain ? 'g' : '-',
74 chip->patch_cr157 ? '7' : '-',
20fe2176 75 chip->patch_6m_band_edge ? '6' : '-',
f2a81a16
DD		 76 chip->new_phy_layout ? 'N' : '-',
77 chip->al2230s_bit ? 'S' : '-');
e85d0918
DD		 78 return i;
79}
80
81static void print_id(struct zd_chip *chip)
82{
83 char buffer[80];
84
85 scnprint_id(chip, buffer, sizeof(buffer));
86 buffer[sizeof(buffer)-1] = 0;
87 dev_info(zd_chip_dev(chip), "%s\n", buffer);
88}
89
0ce34bc8
DD		 90static zd_addr_t inc_addr(zd_addr_t addr)
91{
92 u16 a = (u16)addr;
93 /* Control registers use byte addressing, but everything else uses word
94 * addressing. */
95 if ((a & 0xf000) == CR_START)
96 a += 2;
97 else
98 a += 1;
99 return (zd_addr_t)a;
100}
101
e85d0918
DD		 102/* Read a variable number of 32-bit values. Parameter count is not allowed to
103 * exceed USB_MAX_IOREAD32_COUNT.
104 */
105int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
106 unsigned int count)
107{
108 int r;
109 int i;
fa46081c 110 zd_addr_t *a16;
e85d0918
DD		 111 u16 *v16;
112 unsigned int count16;
113
114 if (count > USB_MAX_IOREAD32_COUNT)
115 return -EINVAL;
116
117 /* Allocate a single memory block for values and addresses. */
118 count16 = 2*count;
44956855 119 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
35c3404e 120 GFP_KERNEL);
e85d0918
DD		 121 if (!a16) {
122 dev_dbg_f(zd_chip_dev(chip),
123 "error ENOMEM in allocation of a16\n");
124 r = -ENOMEM;
125 goto out;
126 }
127 v16 = (u16 *)(a16 + count16);
128
129 for (i = 0; i < count; i++) {
130 int j = 2*i;
131 /* We read the high word always first. */
0ce34bc8 132 a16[j] = inc_addr(addr[i]);
e85d0918
DD		 133 a16[j+1] = addr[i];
134 }
135
136 r = zd_ioread16v_locked(chip, v16, a16, count16);
137 if (r) {
138 dev_dbg_f(zd_chip_dev(chip),
139 "error: zd_ioread16v_locked. Error number %d\n", r);
140 goto out;
141 }
142
143 for (i = 0; i < count; i++) {
144 int j = 2*i;
145 values[i] = (v16[j] << 16) | v16[j+1];
146 }
147
148out:
149 kfree((void *)a16);
150 return r;
151}
152
153int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
154 unsigned int count)
155{
156 int i, j, r;
157 struct zd_ioreq16 *ioreqs16;
158 unsigned int count16;
159
160 ZD_ASSERT(mutex_is_locked(&chip->mutex));
161
162 if (count == 0)
163 return 0;
164 if (count > USB_MAX_IOWRITE32_COUNT)
165 return -EINVAL;
166
167 /* Allocate a single memory block for values and addresses. */
168 count16 = 2*count;
35c3404e 169 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
e85d0918
DD		 170 if (!ioreqs16) {
171 r = -ENOMEM;
172 dev_dbg_f(zd_chip_dev(chip),
173 "error %d in ioreqs16 allocation\n", r);
174 goto out;
175 }
176
177 for (i = 0; i < count; i++) {
178 j = 2*i;
179 /* We write the high word always first. */
180 ioreqs16[j].value = ioreqs[i].value >> 16;
0ce34bc8 181 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
e85d0918
DD		 182 ioreqs16[j+1].value = ioreqs[i].value;
183 ioreqs16[j+1].addr = ioreqs[i].addr;
184 }
185
186 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
187#ifdef DEBUG
188 if (r) {
189 dev_dbg_f(zd_chip_dev(chip),
190 "error %d in zd_usb_write16v\n", r);
191 }
192#endif /* DEBUG */
193out:
194 kfree(ioreqs16);
195 return r;
196}
197
198int zd_iowrite16a_locked(struct zd_chip *chip,
199 const struct zd_ioreq16 *ioreqs, unsigned int count)
200{
201 int r;
202 unsigned int i, j, t, max;
203
204 ZD_ASSERT(mutex_is_locked(&chip->mutex));
205 for (i = 0; i < count; i += j + t) {
206 t = 0;
207 max = count-i;
208 if (max > USB_MAX_IOWRITE16_COUNT)
209 max = USB_MAX_IOWRITE16_COUNT;
210 for (j = 0; j < max; j++) {
211 if (!ioreqs[i+j].addr) {
212 t = 1;
213 break;
214 }
215 }
216
217 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
218 if (r) {
219 dev_dbg_f(zd_chip_dev(chip),
220 "error zd_usb_iowrite16v. Error number %d\n",
221 r);
222 return r;
223 }
224 }
225
226 return 0;
227}
228
229/* Writes a variable number of 32 bit registers. The functions will split
230 * that in several USB requests. A split can be forced by inserting an IO
231 * request with an zero address field.
232 */
233int zd_iowrite32a_locked(struct zd_chip *chip,
234 const struct zd_ioreq32 *ioreqs, unsigned int count)
235{
236 int r;
237 unsigned int i, j, t, max;
238
239 for (i = 0; i < count; i += j + t) {
240 t = 0;
241 max = count-i;
242 if (max > USB_MAX_IOWRITE32_COUNT)
243 max = USB_MAX_IOWRITE32_COUNT;
244 for (j = 0; j < max; j++) {
245 if (!ioreqs[i+j].addr) {
246 t = 1;
247 break;
248 }
249 }
250
251 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
252 if (r) {
253 dev_dbg_f(zd_chip_dev(chip),
254 "error _zd_iowrite32v_locked."
255 " Error number %d\n", r);
256 return r;
257 }
258 }
259
260 return 0;
261}
262
263int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
264{
265 int r;
266
e85d0918
DD		 267 mutex_lock(&chip->mutex);
268 r = zd_ioread16_locked(chip, value, addr);
269 mutex_unlock(&chip->mutex);
270 return r;
271}
272
273int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
274{
275 int r;
276
e85d0918
DD		 277 mutex_lock(&chip->mutex);
278 r = zd_ioread32_locked(chip, value, addr);
279 mutex_unlock(&chip->mutex);
280 return r;
281}
282
283int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
284{
285 int r;
286
e85d0918
DD		 287 mutex_lock(&chip->mutex);
288 r = zd_iowrite16_locked(chip, value, addr);
289 mutex_unlock(&chip->mutex);
290 return r;
291}
292
293int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
294{
295 int r;
296
e85d0918
DD		 297 mutex_lock(&chip->mutex);
298 r = zd_iowrite32_locked(chip, value, addr);
299 mutex_unlock(&chip->mutex);
300 return r;
301}
302
303int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
304 u32 *values, unsigned int count)
305{
306 int r;
307
e85d0918
DD		 308 mutex_lock(&chip->mutex);
309 r = zd_ioread32v_locked(chip, values, addresses, count);
310 mutex_unlock(&chip->mutex);
311 return r;
312}
313
314int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
315 unsigned int count)
316{
317 int r;
318
e85d0918
DD		 319 mutex_lock(&chip->mutex);
320 r = zd_iowrite32a_locked(chip, ioreqs, count);
321 mutex_unlock(&chip->mutex);
322 return r;
323}
324
325static int read_pod(struct zd_chip *chip, u8 *rf_type)
326{
327 int r;
328 u32 value;
329
330 ZD_ASSERT(mutex_is_locked(&chip->mutex));
331 r = zd_ioread32_locked(chip, &value, E2P_POD);
332 if (r)
333 goto error;
334 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
335
336 /* FIXME: AL2230 handling (Bit 7 in POD) */
337 *rf_type = value & 0x0f;
338 chip->pa_type = (value >> 16) & 0x0f;
339 chip->patch_cck_gain = (value >> 8) & 0x1;
340 chip->patch_cr157 = (value >> 13) & 0x1;
341 chip->patch_6m_band_edge = (value >> 21) & 0x1;
20fe2176 342 chip->new_phy_layout = (value >> 31) & 0x1;
ae6ead46 343 chip->al2230s_bit = (value >> 7) & 0x1;
583afd1e
UK		 344 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
345 chip->supports_tx_led = 1;
346 if (value & (1 << 24)) { /* LED scenario */
347 if (value & (1 << 29))
348 chip->supports_tx_led = 0;
349 }
e85d0918
DD		 350
351 dev_dbg_f(zd_chip_dev(chip),
352 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
583afd1e 353 "patch 6M %d new PHY %d link LED%d tx led %d\n",
e85d0918
DD		 354 zd_rf_name(*rf_type), *rf_type,
355 chip->pa_type, chip->patch_cck_gain,
583afd1e
UK		 356 chip->patch_cr157, chip->patch_6m_band_edge,
357 chip->new_phy_layout,
358 chip->link_led == LED1 ? 1 : 2,
359 chip->supports_tx_led);
e85d0918
DD		 360 return 0;
361error:
362 *rf_type = 0;
363 chip->pa_type = 0;
364 chip->patch_cck_gain = 0;
365 chip->patch_cr157 = 0;
366 chip->patch_6m_band_edge = 0;
20fe2176 367 chip->new_phy_layout = 0;
e85d0918
DD		 368 return r;
369}
370
e85d0918
DD		 371/* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
372 * CR_MAC_ADDR_P2 must be overwritten
373 */
e85d0918
DD		 374int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
375{
376 int r;
377 struct zd_ioreq32 reqs[2] = {
378 [0] = { .addr = CR_MAC_ADDR_P1 },
379 [1] = { .addr = CR_MAC_ADDR_P2 },
380 };
381
459c51ad
DD		 382 if (mac_addr) {
383 reqs[0].value = (mac_addr[3] << 24)
384 | (mac_addr[2] << 16)
385 | (mac_addr[1] << 8)
386 | mac_addr[0];
387 reqs[1].value = (mac_addr[5] << 8)
388 | mac_addr[4];
e174961c 389 dev_dbg_f(zd_chip_dev(chip), "mac addr %pM\n", mac_addr);
459c51ad
DD		 390 } else {
391 dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n");
392 }
e85d0918
DD		 393
394 mutex_lock(&chip->mutex);
395 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
e85d0918
DD		 396 mutex_unlock(&chip->mutex);
397 return r;
398}
399
400int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
401{
402 int r;
403 u32 value;
404
405 mutex_lock(&chip->mutex);
406 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
407 mutex_unlock(&chip->mutex);
408 if (r)
409 return r;
410
411 *regdomain = value >> 16;
412 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
413
414 return 0;
415}
416
417static int read_values(struct zd_chip *chip, u8 *values, size_t count,
418 zd_addr_t e2p_addr, u32 guard)
419{
420 int r;
421 int i;
422 u32 v;
423
424 ZD_ASSERT(mutex_is_locked(&chip->mutex));
425 for (i = 0;;) {
0ce34bc8
DD		 426 r = zd_ioread32_locked(chip, &v,
427 (zd_addr_t)((u16)e2p_addr+i/2));
e85d0918
DD		 428 if (r)
429 return r;
430 v -= guard;
431 if (i+4 < count) {
432 values[i++] = v;
433 values[i++] = v >> 8;
434 values[i++] = v >> 16;
435 values[i++] = v >> 24;
436 continue;
437 }
438 for (;i < count; i++)
439 values[i] = v >> (8*(i%3));
440 return 0;
441 }
442}
443
444static int read_pwr_cal_values(struct zd_chip *chip)
445{
446 return read_values(chip, chip->pwr_cal_values,
447 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
448 0);
449}
450
451static int read_pwr_int_values(struct zd_chip *chip)
452{
453 return read_values(chip, chip->pwr_int_values,
454 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
455 E2P_PWR_INT_GUARD);
456}
457
458static int read_ofdm_cal_values(struct zd_chip *chip)
459{
460 int r;
461 int i;
462 static const zd_addr_t addresses[] = {
463 E2P_36M_CAL_VALUE1,
464 E2P_48M_CAL_VALUE1,
465 E2P_54M_CAL_VALUE1,
466 };
467
468 for (i = 0; i < 3; i++) {
469 r = read_values(chip, chip->ofdm_cal_values[i],
470 E2P_CHANNEL_COUNT, addresses[i], 0);
471 if (r)
472 return r;
473 }
474 return 0;
475}
476
477static int read_cal_int_tables(struct zd_chip *chip)
478{
479 int r;
480
481 r = read_pwr_cal_values(chip);
482 if (r)
483 return r;
484 r = read_pwr_int_values(chip);
485 if (r)
486 return r;
487 r = read_ofdm_cal_values(chip);
488 if (r)
489 return r;
490 return 0;
491}
492
493/* phy means physical registers */
494int zd_chip_lock_phy_regs(struct zd_chip *chip)
495{
496 int r;
497 u32 tmp;
498
499 ZD_ASSERT(mutex_is_locked(&chip->mutex));
500 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
501 if (r) {
502 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
503 return r;
504 }
505
e85d0918
DD		 506 tmp &= ~UNLOCK_PHY_REGS;
507
508 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
509 if (r)
510 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
511 return r;
512}
513
514int zd_chip_unlock_phy_regs(struct zd_chip *chip)
515{
516 int r;
517 u32 tmp;
518
519 ZD_ASSERT(mutex_is_locked(&chip->mutex));
520 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
521 if (r) {
522 dev_err(zd_chip_dev(chip),
523 "error ioread32(CR_REG1): %d\n", r);
524 return r;
525 }
526
e85d0918
DD		 527 tmp |= UNLOCK_PHY_REGS;
528
529 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
530 if (r)
531 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
532 return r;
533}
534
92b3e2e9 535/* CR157 can be optionally patched by the EEPROM for original ZD1211 */
e85d0918
DD		 536static int patch_cr157(struct zd_chip *chip)
537{
538 int r;
92b3e2e9 539 u16 value;
e85d0918
DD		 540
541 if (!chip->patch_cr157)
542 return 0;
543
92b3e2e9 544 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
e85d0918
DD		 545 if (r)
546 return r;
547
548 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
549 return zd_iowrite32_locked(chip, value >> 8, CR157);
550}
551
552/*
553 * 6M band edge can be optionally overwritten for certain RF's
554 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
555 * bit (for AL2230, AL2230S)
556 */
72018b22
DD		 557static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
558{
559 ZD_ASSERT(mutex_is_locked(&chip->mutex));
560 if (!chip->patch_6m_band_edge)
561 return 0;
562
563 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
564}
565
566/* Generic implementation of 6M band edge patching, used by most RFs via
567 * zd_rf_generic_patch_6m() */
568int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
e85d0918
DD		 569{
570 struct zd_ioreq16 ioreqs[] = {
571 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
572 { CR47, 0x1e },
573 };
574
e85d0918
DD		 575 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
576 if (channel == 1 || channel == 11)
577 ioreqs[0].value = 0x12;
578
579 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
580 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
581}
582
583static int zd1211_hw_reset_phy(struct zd_chip *chip)
584{
585 static const struct zd_ioreq16 ioreqs[] = {
586 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
587 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
588 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
589 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
590 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
591 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
592 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
593 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
594 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
595 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
596 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
597 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
598 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
599 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
600 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
601 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
602 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
603 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
604 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
605 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
606 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
607 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
608 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
609 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
610 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
611 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
612 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
613 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
614 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
615 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
616 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
617 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
618 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
619 { },
620 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
621 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
622 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
623 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
624 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
625 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
626 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
627 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
628 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
629 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
630 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
631 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
632 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
633 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
dc536a70
DD		 634 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
635 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
636 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
637 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
638 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
639 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
640 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
641 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
642 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
643 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
644 { CR170, 0xba }, { CR171, 0xba },
e85d0918
DD		 645 /* Note: CR204 must lead the CR203 */
646 { CR204, 0x7d },
647 { },
648 { CR203, 0x30 },
649 };
650
651 int r, t;
652
653 dev_dbg_f(zd_chip_dev(chip), "\n");
654
655 r = zd_chip_lock_phy_regs(chip);
656 if (r)
657 goto out;
658
659 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
660 if (r)
661 goto unlock;
662
663 r = patch_cr157(chip);
664unlock:
665 t = zd_chip_unlock_phy_regs(chip);
666 if (t && !r)
667 r = t;
668out:
669 return r;
670}
671
672static int zd1211b_hw_reset_phy(struct zd_chip *chip)
673{
674 static const struct zd_ioreq16 ioreqs[] = {
675 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
676 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
677 { CR10, 0x81 },
678 /* power control { { CR11, 1 << 6 }, */
679 { CR11, 0x00 },
680 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
681 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
682 { CR18, 0x0a }, { CR19, 0x48 },
683 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
684 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
685 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
686 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
fe7215ca 687 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
e85d0918
DD		 688 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
689 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
690 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
691 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
692 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
693 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
694 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
695 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
696 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
697 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
698 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
699 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
700 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
701 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
702 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
703 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
704 { CR94, 0x01 },
705 { CR95, 0x20 }, /* ZD1211B */
706 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
707 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
708 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
709 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
710 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
711 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
712 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
713 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
714 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
715 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
716 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
717 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
718 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
719 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
720 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
721 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
722 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
723 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
724 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
725 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
726 { CR170, 0xba }, { CR171, 0xba },
727 /* Note: CR204 must lead the CR203 */
728 { CR204, 0x7d },
729 {},
730 { CR203, 0x30 },
731 };
732
733 int r, t;
734
735 dev_dbg_f(zd_chip_dev(chip), "\n");
736
737 r = zd_chip_lock_phy_regs(chip);
738 if (r)
739 goto out;
740
741 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 742 t = zd_chip_unlock_phy_regs(chip);
743 if (t && !r)
744 r = t;
745out:
746 return r;
747}
748
749static int hw_reset_phy(struct zd_chip *chip)
750{
74553aed 751 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
e85d0918
DD		 752 zd1211_hw_reset_phy(chip);
753}
754
755static int zd1211_hw_init_hmac(struct zd_chip *chip)
756{
757 static const struct zd_ioreq32 ioreqs[] = {
e85d0918 758 { CR_ZD1211_RETRY_MAX, 0x2 },
e85d0918 759 { CR_RX_THRESHOLD, 0x000c0640 },
e85d0918
DD		 760 };
761
e85d0918
DD		 762 dev_dbg_f(zd_chip_dev(chip), "\n");
763 ZD_ASSERT(mutex_is_locked(&chip->mutex));
34c44912 764 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 765}
766
767static int zd1211b_hw_init_hmac(struct zd_chip *chip)
768{
769 static const struct zd_ioreq32 ioreqs[] = {
e85d0918 770 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
e51c6837
JC		 771 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f },
772 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f },
773 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f },
774 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f },
e85d0918
DD		 775 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
776 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
777 { CR_ZD1211B_TXOP, 0x01800824 },
34c44912
DD		 778 { CR_RX_THRESHOLD, 0x000c0eff, },
779 };
780
781 dev_dbg_f(zd_chip_dev(chip), "\n");
782 ZD_ASSERT(mutex_is_locked(&chip->mutex));
783 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
784}
785
786static int hw_init_hmac(struct zd_chip *chip)
787{
788 int r;
789 static const struct zd_ioreq32 ioreqs[] = {
790 { CR_ACK_TIMEOUT_EXT, 0x20 },
791 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
e85d0918 792 { CR_SNIFFER_ON, 0 },
fde627b5 793 { CR_RX_FILTER, STA_RX_FILTER },
e85d0918
DD		 794 { CR_GROUP_HASH_P1, 0x00 },
795 { CR_GROUP_HASH_P2, 0x80000000 },
796 { CR_REG1, 0xa4 },
797 { CR_ADDA_PWR_DWN, 0x7f },
798 { CR_BCN_PLCP_CFG, 0x00f00401 },
799 { CR_PHY_DELAY, 0x00 },
800 { CR_ACK_TIMEOUT_EXT, 0x80 },
801 { CR_ADDA_PWR_DWN, 0x00 },
802 { CR_ACK_TIME_80211, 0x100 },
e85d0918
DD		 803 { CR_RX_PE_DELAY, 0x70 },
804 { CR_PS_CTRL, 0x10000000 },
805 { CR_RTS_CTS_RATE, 0x02030203 },
e85d0918
DD		 806 { CR_AFTER_PNP, 0x1 },
807 { CR_WEP_PROTECT, 0x114 },
34c44912 808 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
72e77a8a 809 { CR_CAM_MODE, MODE_AP_WDS},
e85d0918
DD		 810 };
811
e85d0918
DD		 812 ZD_ASSERT(mutex_is_locked(&chip->mutex));
813 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
34c44912
DD		 814 if (r)
815 return r;
e85d0918 816
74553aed 817 return zd_chip_is_zd1211b(chip) ?
e85d0918
DD		 818 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
819}
820
821struct aw_pt_bi {
822 u32 atim_wnd_period;
823 u32 pre_tbtt;
824 u32 beacon_interval;
825};
826
827static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
828{
829 int r;
830 static const zd_addr_t aw_pt_bi_addr[] =
831 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
832 u32 values[3];
833
834 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
835 ARRAY_SIZE(aw_pt_bi_addr));
836 if (r) {
837 memset(s, 0, sizeof(*s));
838 return r;
839 }
840
841 s->atim_wnd_period = values[0];
842 s->pre_tbtt = values[1];
843 s->beacon_interval = values[2];
e85d0918
DD		 844 return 0;
845}
846
847static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
848{
849 struct zd_ioreq32 reqs[3];
850
851 if (s->beacon_interval <= 5)
852 s->beacon_interval = 5;
853 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
854 s->pre_tbtt = s->beacon_interval - 1;
855 if (s->atim_wnd_period >= s->pre_tbtt)
856 s->atim_wnd_period = s->pre_tbtt - 1;
857
858 reqs[0].addr = CR_ATIM_WND_PERIOD;
859 reqs[0].value = s->atim_wnd_period;
860 reqs[1].addr = CR_PRE_TBTT;
861 reqs[1].value = s->pre_tbtt;
862 reqs[2].addr = CR_BCN_INTERVAL;
863 reqs[2].value = s->beacon_interval;
864
e85d0918
DD		 865 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
866}
867
868
869static int set_beacon_interval(struct zd_chip *chip, u32 interval)
870{
871 int r;
872 struct aw_pt_bi s;
873
874 ZD_ASSERT(mutex_is_locked(&chip->mutex));
875 r = get_aw_pt_bi(chip, &s);
876 if (r)
877 return r;
878 s.beacon_interval = interval;
879 return set_aw_pt_bi(chip, &s);
880}
881
882int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
883{
884 int r;
885
886 mutex_lock(&chip->mutex);
887 r = set_beacon_interval(chip, interval);
888 mutex_unlock(&chip->mutex);
889 return r;
890}
891
892static int hw_init(struct zd_chip *chip)
893{
894 int r;
895
896 dev_dbg_f(zd_chip_dev(chip), "\n");
897 ZD_ASSERT(mutex_is_locked(&chip->mutex));
898 r = hw_reset_phy(chip);
899 if (r)
900 return r;
901
902 r = hw_init_hmac(chip);
903 if (r)
904 return r;
98227a90 905
98227a90 906 return set_beacon_interval(chip, 100);
e85d0918
DD		 907}
908
0ce34bc8
DD		 909static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
910{
911 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
912}
913
e85d0918
DD		 914#ifdef DEBUG
915static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
916 const char *addr_string)
917{
918 int r;
919 u32 value;
920
921 r = zd_ioread32_locked(chip, &value, addr);
922 if (r) {
923 dev_dbg_f(zd_chip_dev(chip),
924 "error reading %s. Error number %d\n", addr_string, r);
925 return r;
926 }
927
928 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
929 addr_string, (unsigned int)value);
930 return 0;
931}
932
933static int test_init(struct zd_chip *chip)
934{
935 int r;
936
937 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
938 if (r)
939 return r;
940 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
941 if (r)
942 return r;
943 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
944}
945
946static void dump_fw_registers(struct zd_chip *chip)
947{
0ce34bc8
DD		 948 const zd_addr_t addr[4] = {
949 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
950 fw_reg_addr(chip, FW_REG_USB_SPEED),
951 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
952 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
e85d0918
DD		 953 };
954
955 int r;
956 u16 values[4];
957
958 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
959 ARRAY_SIZE(addr));
960 if (r) {
961 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
962 r);
963 return;
964 }
965
966 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
967 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
968 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
969 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
970}
971#endif /* DEBUG */
972
973static int print_fw_version(struct zd_chip *chip)
974{
975 int r;
976 u16 version;
977
0ce34bc8
DD		 978 r = zd_ioread16_locked(chip, &version,
979 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
e85d0918
DD		 980 if (r)
981 return r;
982
983 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
984 return 0;
985}
986
8318d78a 987static int set_mandatory_rates(struct zd_chip *chip, int gmode)
e85d0918
DD		 988{
989 u32 rates;
990 ZD_ASSERT(mutex_is_locked(&chip->mutex));
991 /* This sets the mandatory rates, which only depend from the standard
992 * that the device is supporting. Until further notice we should try
993 * to support 802.11g also for full speed USB.
994 */
8318d78a 995 if (!gmode)
e85d0918 996 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
8318d78a 997 else
e85d0918
DD		 998 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
999 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
8318d78a 1000
e85d0918
DD		 1001 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1002}
1003
b1382ede 1004int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
459c51ad 1005 int preamble)
b1382ede 1006{
b1382ede
DD		 1007 u32 value = 0;
1008
459c51ad 1009 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
b1382ede
DD		 1010 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1011 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1012
459c51ad
DD		 1013 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1014 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1015 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
64f222cc 1016 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
b1382ede
DD		 1017 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1018
1019 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1020}
1021
e85d0918
DD		 1022int zd_chip_enable_hwint(struct zd_chip *chip)
1023{
1024 int r;
1025
1026 mutex_lock(&chip->mutex);
1027 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1028 mutex_unlock(&chip->mutex);
1029 return r;
1030}
1031
1032static int disable_hwint(struct zd_chip *chip)
1033{
1034 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1035}
1036
1037int zd_chip_disable_hwint(struct zd_chip *chip)
1038{
1039 int r;
1040
1041 mutex_lock(&chip->mutex);
1042 r = disable_hwint(chip);
1043 mutex_unlock(&chip->mutex);
1044 return r;
1045}
1046
0ce34bc8
DD		 1047static int read_fw_regs_offset(struct zd_chip *chip)
1048{
1049 int r;
1050
1051 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1052 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1053 FWRAW_REGS_ADDR);
1054 if (r)
1055 return r;
1056 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1057 (u16)chip->fw_regs_base);
1058
1059 return 0;
1060}
1061
74553aed
DD		 1062/* Read mac address using pre-firmware interface */
1063int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1064{
1065 dev_dbg_f(zd_chip_dev(chip), "\n");
1066 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1067 ETH_ALEN);
1068}
0ce34bc8 1069
74553aed 1070int zd_chip_init_hw(struct zd_chip *chip)
e85d0918
DD		 1071{
1072 int r;
1073 u8 rf_type;
1074
1075 dev_dbg_f(zd_chip_dev(chip), "\n");
1076
1077 mutex_lock(&chip->mutex);
e85d0918
DD		 1078
1079#ifdef DEBUG
1080 r = test_init(chip);
1081 if (r)
1082 goto out;
1083#endif
1084 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1085 if (r)
1086 goto out;
1087
0ce34bc8 1088 r = read_fw_regs_offset(chip);
e85d0918
DD		 1089 if (r)
1090 goto out;
1091
1092 /* GPI is always disabled, also in the other driver.
1093 */
1094 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1095 if (r)
1096 goto out;
1097 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1098 if (r)
1099 goto out;
1100 /* Currently we support IEEE 802.11g for full and high speed USB.
1101 * It might be discussed, whether we should suppport pure b mode for
1102 * full speed USB.
1103 */
8318d78a 1104 r = set_mandatory_rates(chip, 1);
e85d0918
DD		 1105 if (r)
1106 goto out;
1107 /* Disabling interrupts is certainly a smart thing here.
1108 */
1109 r = disable_hwint(chip);
1110 if (r)
1111 goto out;
1112 r = read_pod(chip, &rf_type);
1113 if (r)
1114 goto out;
1115 r = hw_init(chip);
1116 if (r)
1117 goto out;
1118 r = zd_rf_init_hw(&chip->rf, rf_type);
1119 if (r)
1120 goto out;
1121
1122 r = print_fw_version(chip);
1123 if (r)
1124 goto out;
1125
1126#ifdef DEBUG
1127 dump_fw_registers(chip);
1128 r = test_init(chip);
1129 if (r)
1130 goto out;
1131#endif /* DEBUG */
1132
e85d0918
DD		 1133 r = read_cal_int_tables(chip);
1134 if (r)
1135 goto out;
1136
1137 print_id(chip);
1138out:
1139 mutex_unlock(&chip->mutex);
1140 return r;
1141}
1142
1143static int update_pwr_int(struct zd_chip *chip, u8 channel)
1144{
1145 u8 value = chip->pwr_int_values[channel - 1];
cbb5e6bb 1146 return zd_iowrite16_locked(chip, value, CR31);
e85d0918
DD		 1147}
1148
1149static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1150{
1151 u8 value = chip->pwr_cal_values[channel-1];
cbb5e6bb 1152 return zd_iowrite16_locked(chip, value, CR68);
e85d0918
DD		 1153}
1154
1155static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1156{
cbb5e6bb 1157 struct zd_ioreq16 ioreqs[3];
e85d0918
DD		 1158
1159 ioreqs[0].addr = CR67;
1160 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1161 ioreqs[1].addr = CR66;
1162 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1163 ioreqs[2].addr = CR65;
1164 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1165
cbb5e6bb 1166 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1167}
1168
1169static int update_channel_integration_and_calibration(struct zd_chip *chip,
1170 u8 channel)
1171{
1172 int r;
1173
9c8fc71d
DD		 1174 if (!zd_rf_should_update_pwr_int(&chip->rf))
1175 return 0;
1176
e85d0918
DD		 1177 r = update_pwr_int(chip, channel);
1178 if (r)
1179 return r;
74553aed 1180 if (zd_chip_is_zd1211b(chip)) {
cbb5e6bb 1181 static const struct zd_ioreq16 ioreqs[] = {
e85d0918
DD		 1182 { CR69, 0x28 },
1183 {},
1184 { CR69, 0x2a },
1185 };
1186
1187 r = update_ofdm_cal(chip, channel);
1188 if (r)
1189 return r;
1190 r = update_pwr_cal(chip, channel);
1191 if (r)
1192 return r;
cbb5e6bb 1193 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
e85d0918
DD		 1194 if (r)
1195 return r;
1196 }
1197
1198 return 0;
1199}
1200
1201/* The CCK baseband gain can be optionally patched by the EEPROM */
1202static int patch_cck_gain(struct zd_chip *chip)
1203{
1204 int r;
1205 u32 value;
1206
aaf83d4f 1207 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
e85d0918
DD		 1208 return 0;
1209
1210 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1211 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1212 if (r)
1213 return r;
1214 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
cbb5e6bb 1215 return zd_iowrite16_locked(chip, value & 0xff, CR47);
e85d0918
DD		 1216}
1217
1218int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1219{
1220 int r, t;
1221
1222 mutex_lock(&chip->mutex);
1223 r = zd_chip_lock_phy_regs(chip);
1224 if (r)
1225 goto out;
1226 r = zd_rf_set_channel(&chip->rf, channel);
1227 if (r)
1228 goto unlock;
1229 r = update_channel_integration_and_calibration(chip, channel);
1230 if (r)
1231 goto unlock;
1232 r = patch_cck_gain(chip);
1233 if (r)
1234 goto unlock;
1235 r = patch_6m_band_edge(chip, channel);
1236 if (r)
1237 goto unlock;
1238 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1239unlock:
1240 t = zd_chip_unlock_phy_regs(chip);
1241 if (t && !r)
1242 r = t;
1243out:
1244 mutex_unlock(&chip->mutex);
1245 return r;
1246}
1247
1248u8 zd_chip_get_channel(struct zd_chip *chip)
1249{
1250 u8 channel;
1251
1252 mutex_lock(&chip->mutex);
1253 channel = chip->rf.channel;
1254 mutex_unlock(&chip->mutex);
1255 return channel;
1256}
1257
583afd1e 1258int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
e85d0918 1259{
0ce34bc8
DD		 1260 const zd_addr_t a[] = {
1261 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
583afd1e
UK		 1262 CR_LED,
1263 };
e85d0918 1264
583afd1e
UK		 1265 int r;
1266 u16 v[ARRAY_SIZE(a)];
1267 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
0ce34bc8 1268 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
583afd1e
UK		 1269 [1] = { CR_LED },
1270 };
1271 u16 other_led;
e85d0918 1272
e85d0918 1273 mutex_lock(&chip->mutex);
583afd1e 1274 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
e85d0918 1275 if (r)
583afd1e
UK		 1276 goto out;
1277
1278 other_led = chip->link_led == LED1 ? LED2 : LED1;
1279
e85d0918 1280 switch (status) {
e85d0918 1281 case LED_OFF:
583afd1e
UK		 1282 ioreqs[0].value = FW_LINK_OFF;
1283 ioreqs[1].value = v[1] & ~(LED1|LED2);
e85d0918 1284 break;
583afd1e
UK		 1285 case LED_SCANNING:
1286 ioreqs[0].value = FW_LINK_OFF;
1287 ioreqs[1].value = v[1] & ~other_led;
1288 if (get_seconds() % 3 == 0) {
1289 ioreqs[1].value &= ~chip->link_led;
1290 } else {
1291 ioreqs[1].value |= chip->link_led;
1292 }
e85d0918 1293 break;
583afd1e
UK		 1294 case LED_ASSOCIATED:
1295 ioreqs[0].value = FW_LINK_TX;
1296 ioreqs[1].value = v[1] & ~other_led;
1297 ioreqs[1].value |= chip->link_led;
e85d0918
DD		 1298 break;
1299 default:
583afd1e 1300 r = -EINVAL;
e85d0918
DD		 1301 goto out;
1302 }
e85d0918 1303
583afd1e
UK		 1304 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1305 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1306 if (r)
e85d0918 1307 goto out;
e85d0918 1308 }
583afd1e 1309 r = 0;
e85d0918 1310out:
583afd1e 1311 mutex_unlock(&chip->mutex);
e85d0918
DD		 1312 return r;
1313}
1314
459c51ad 1315int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
e85d0918 1316{
459c51ad
DD		 1317 int r;
1318
1319 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1320 return -EINVAL;
e85d0918 1321
459c51ad
DD		 1322 mutex_lock(&chip->mutex);
1323 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1324 mutex_unlock(&chip->mutex);
1325 return r;
e85d0918
DD		 1326}
1327
64f222cc 1328static int ofdm_qual_db(u8 status_quality, u8 zd_rate, unsigned int size)
e85d0918
DD		 1329{
1330 static const u16 constants[] = {
1331 715, 655, 585, 540, 470, 410, 360, 315,
1332 270, 235, 205, 175, 150, 125, 105, 85,
1333 65, 50, 40, 25, 15
1334 };
1335
1336 int i;
1337 u32 x;
1338
1339 /* It seems that their quality parameter is somehow per signal
1340 * and is now transferred per bit.
1341 */
64f222cc 1342 switch (zd_rate) {
e85d0918
DD		 1343 case ZD_OFDM_RATE_6M:
1344 case ZD_OFDM_RATE_12M:
1345 case ZD_OFDM_RATE_24M:
1346 size *= 2;
1347 break;
1348 case ZD_OFDM_RATE_9M:
1349 case ZD_OFDM_RATE_18M:
1350 case ZD_OFDM_RATE_36M:
1351 case ZD_OFDM_RATE_54M:
1352 size *= 4;
1353 size /= 3;
1354 break;
1355 case ZD_OFDM_RATE_48M:
1356 size *= 3;
1357 size /= 2;
1358 break;
1359 default:
1360 return -EINVAL;
1361 }
1362
1363 x = (10000 * status_quality)/size;
1364 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1365 if (x > constants[i])
1366 break;
1367 }
1368
64f222cc 1369 switch (zd_rate) {
db888aed
UK		 1370 case ZD_OFDM_RATE_6M:
1371 case ZD_OFDM_RATE_9M:
1372 i += 3;
1373 break;
1374 case ZD_OFDM_RATE_12M:
1375 case ZD_OFDM_RATE_18M:
1376 i += 5;
1377 break;
1378 case ZD_OFDM_RATE_24M:
1379 case ZD_OFDM_RATE_36M:
1380 i += 9;
1381 break;
1382 case ZD_OFDM_RATE_48M:
1383 case ZD_OFDM_RATE_54M:
1384 i += 15;
1385 break;
1386 default:
1387 return -EINVAL;
1388 }
1389
e85d0918
DD		 1390 return i;
1391}
1392
64f222cc 1393static int ofdm_qual_percent(u8 status_quality, u8 zd_rate, unsigned int size)
db888aed
UK		 1394{
1395 int r;
1396
64f222cc 1397 r = ofdm_qual_db(status_quality, zd_rate, size);
db888aed
UK		 1398 ZD_ASSERT(r >= 0);
1399 if (r < 0)
1400 r = 0;
1401
1402 r = (r * 100)/29;
1403 return r <= 100 ? r : 100;
1404}
1405
e85d0918
DD		 1406static unsigned int log10times100(unsigned int x)
1407{
1408 static const u8 log10[] = {
1409 0,
1410 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1411 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1412 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1413 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1414 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1415 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1416 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1417 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1418 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1419 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1420 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1421 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1422 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1423 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1424 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1425 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1426 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1427 223, 223, 223, 224, 224, 224, 224,
1428 };
1429
1430 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1431}
1432
1433enum {
1434 MAX_CCK_EVM_DB = 45,
1435};
1436
1437static int cck_evm_db(u8 status_quality)
1438{
1439 return (20 * log10times100(status_quality)) / 100;
1440}
1441
1442static int cck_snr_db(u8 status_quality)
1443{
1444 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1445 ZD_ASSERT(r >= 0);
1446 return r;
1447}
1448
db888aed 1449static int cck_qual_percent(u8 status_quality)
e85d0918 1450{
db888aed
UK		 1451 int r;
1452
1453 r = cck_snr_db(status_quality);
1454 r = (100*r)/17;
1455 return r <= 100 ? r : 100;
e85d0918
DD		 1456}
1457
64f222cc
UK		 1458static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1459{
1460 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1461}
1462
e85d0918
DD		 1463u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1464 const struct rx_status *status)
1465{
db888aed
UK		 1466 return (status->frame_status&ZD_RX_OFDM) ?
1467 ofdm_qual_percent(status->signal_quality_ofdm,
459c51ad 1468 zd_rate_from_ofdm_plcp_header(rx_frame),
db888aed
UK		 1469 size) :
1470 cck_qual_percent(status->signal_quality_cck);
e85d0918
DD		 1471}
1472
459c51ad
DD		 1473/**
1474 * zd_rx_rate - report zd-rate
1475 * @rx_frame - received frame
1476 * @rx_status - rx_status as given by the device
1477 *
1478 * This function converts the rate as encoded in the received packet to the
1479 * zd-rate, we are using on other places in the driver.
1480 */
1481u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
e85d0918 1482{
459c51ad 1483 u8 zd_rate;
e85d0918 1484 if (status->frame_status & ZD_RX_OFDM) {
459c51ad 1485 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
e85d0918 1486 } else {
64f222cc
UK		 1487 switch (zd_cck_plcp_header_signal(rx_frame)) {
1488 case ZD_CCK_PLCP_SIGNAL_1M:
459c51ad 1489 zd_rate = ZD_CCK_RATE_1M;
e85d0918 1490 break;
64f222cc 1491 case ZD_CCK_PLCP_SIGNAL_2M:
459c51ad 1492 zd_rate = ZD_CCK_RATE_2M;
e85d0918 1493 break;
64f222cc 1494 case ZD_CCK_PLCP_SIGNAL_5M5:
459c51ad 1495 zd_rate = ZD_CCK_RATE_5_5M;
e85d0918 1496 break;
64f222cc 1497 case ZD_CCK_PLCP_SIGNAL_11M:
459c51ad 1498 zd_rate = ZD_CCK_RATE_11M;
e85d0918
DD		 1499 break;
1500 default:
459c51ad 1501 zd_rate = 0;
e85d0918
DD		 1502 }
1503 }
1504
459c51ad 1505 return zd_rate;
e85d0918
DD		 1506}
1507
1508int zd_chip_switch_radio_on(struct zd_chip *chip)
1509{
1510 int r;
1511
1512 mutex_lock(&chip->mutex);
1513 r = zd_switch_radio_on(&chip->rf);
1514 mutex_unlock(&chip->mutex);
1515 return r;
1516}
1517
1518int zd_chip_switch_radio_off(struct zd_chip *chip)
1519{
1520 int r;
1521
1522 mutex_lock(&chip->mutex);
1523 r = zd_switch_radio_off(&chip->rf);
1524 mutex_unlock(&chip->mutex);
1525 return r;
1526}
1527
1528int zd_chip_enable_int(struct zd_chip *chip)
1529{
1530 int r;
1531
1532 mutex_lock(&chip->mutex);
1533 r = zd_usb_enable_int(&chip->usb);
1534 mutex_unlock(&chip->mutex);
1535 return r;
1536}
1537
1538void zd_chip_disable_int(struct zd_chip *chip)
1539{
1540 mutex_lock(&chip->mutex);
1541 zd_usb_disable_int(&chip->usb);
1542 mutex_unlock(&chip->mutex);
1543}
1544
459c51ad 1545int zd_chip_enable_rxtx(struct zd_chip *chip)
e85d0918
DD		 1546{
1547 int r;
1548
1549 mutex_lock(&chip->mutex);
459c51ad 1550 zd_usb_enable_tx(&chip->usb);
e85d0918
DD		 1551 r = zd_usb_enable_rx(&chip->usb);
1552 mutex_unlock(&chip->mutex);
1553 return r;
1554}
1555
459c51ad 1556void zd_chip_disable_rxtx(struct zd_chip *chip)
e85d0918
DD		 1557{
1558 mutex_lock(&chip->mutex);
1559 zd_usb_disable_rx(&chip->usb);
459c51ad 1560 zd_usb_disable_tx(&chip->usb);
e85d0918
DD		 1561 mutex_unlock(&chip->mutex);
1562}
1563
1564int zd_rfwritev_locked(struct zd_chip *chip,
1565 const u32* values, unsigned int count, u8 bits)
1566{
1567 int r;
1568 unsigned int i;
1569
1570 for (i = 0; i < count; i++) {
1571 r = zd_rfwrite_locked(chip, values[i], bits);
1572 if (r)
1573 return r;
1574 }
1575
1576 return 0;
1577}
20fe2176
DD		 1578
1579/*
1580 * We can optionally program the RF directly through CR regs, if supported by
1581 * the hardware. This is much faster than the older method.
1582 */
ec62bd91 1583int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
20fe2176
DD		 1584{
1585 struct zd_ioreq16 ioreqs[] = {
1586 { CR244, (value >> 16) & 0xff },
1587 { CR243, (value >> 8) & 0xff },
1588 { CR242, value & 0xff },
1589 };
1590 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1591 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1592}
1593
1594int zd_rfwritev_cr_locked(struct zd_chip *chip,
1595 const u32 *values, unsigned int count)
1596{
1597 int r;
1598 unsigned int i;
1599
1600 for (i = 0; i < count; i++) {
1601 r = zd_rfwrite_cr_locked(chip, values[i]);
1602 if (r)
1603 return r;
1604 }
1605
1606 return 0;
1607}
9cdac965
UK		 1608
1609int zd_chip_set_multicast_hash(struct zd_chip *chip,
1610 struct zd_mc_hash *hash)
1611{
1612 struct zd_ioreq32 ioreqs[] = {
1613 { CR_GROUP_HASH_P1, hash->low },
1614 { CR_GROUP_HASH_P2, hash->high },
1615 };
1616
9cdac965
UK		 1617 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1618}
5fe73197
AF		 1619
1620u64 zd_chip_get_tsf(struct zd_chip *chip)
1621{
1622 int r;
1623 static const zd_addr_t aw_pt_bi_addr[] =
1624 { CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1625 u32 values[2];
1626 u64 tsf;
1627
1628 mutex_lock(&chip->mutex);
1629 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
1630 ARRAY_SIZE(aw_pt_bi_addr));
1631 mutex_unlock(&chip->mutex);
1632 if (r)
1633 return 0;
1634
1635 tsf = values[1];
1636 tsf = (tsf << 32) | values[0];
1637
1638 return tsf;
1639}
Linux 6.x block layer and io_uring tree(s)