[linux-2.6-block.git] / drivers / net / wireless / wl12xx / wl1271_boot.c

/*
 * This file is part of wl1271
 *
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/gpio.h>

#include "wl1271_acx.h"
#include "wl1271_reg.h"
#include "wl1271_boot.h"
#include "wl1271_spi.h"
#include "wl1271_event.h"

static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
	[PART_DOWN] = {
		.mem = {
			.start = 0x00000000,
			.size  = 0x000177c0
		},
		.reg = {
			.start = REGISTERS_BASE,
			.size  = 0x00008800
		},
		.mem2 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
		.mem3 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
	},

	[PART_WORK] = {
		.mem = {
			.start = 0x00040000,
			.size  = 0x00014fc0
		},
		.reg = {
			.start = REGISTERS_BASE,
			.size  = 0x0000a000
		},
		.mem2 = {
			.start = 0x003004f8,
			.size  = 0x00000004
		},
		.mem3 = {
			.start = 0x00040404,
			.size  = 0x00000000
		},
	},

	[PART_DRPW] = {
		.mem = {
			.start = 0x00040000,
			.size  = 0x00014fc0
		},
		.reg = {
			.start = DRPW_BASE,
			.size  = 0x00006000
		},
		.mem2 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
		.mem3 = {
			.start = 0x00000000,
			.size  = 0x00000000
		}
	}
};

static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
{
	u32 cpu_ctrl;

	/* 10.5.0 run the firmware (I) */
	cpu_ctrl = wl1271_spi_read32(wl, ACX_REG_ECPU_CONTROL);

	/* 10.5.1 run the firmware (II) */
	cpu_ctrl |= flag;
	wl1271_spi_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
}

static void wl1271_boot_fw_version(struct wl1271 *wl)
{
	struct wl1271_static_data static_data;

	wl1271_spi_read(wl, wl->cmd_box_addr,
			&static_data, sizeof(static_data), false);

	strncpy(wl->chip.fw_ver, static_data.fw_version,
		sizeof(wl->chip.fw_ver));

	/* make sure the string is NULL-terminated */
	wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
}

static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
					     size_t fw_data_len, u32 dest)
{
	struct wl1271_partition_set partition;
	int addr, chunk_num, partition_limit;
	u8 *p, *chunk;

	/* whal_FwCtrl_LoadFwImageSm() */

	wl1271_debug(DEBUG_BOOT, "starting firmware upload");

	wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
		     fw_data_len, CHUNK_SIZE);

	if ((fw_data_len % 4) != 0) {
		wl1271_error("firmware length not multiple of four");
		return -EIO;
	}

	chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	if (!buf) {
		wl1271_error("allocation for firmware upload chunk failed");
		return -ENOMEM;
	}

	memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
	partition.mem.start = dest;
	wl1271_set_partition(wl, &partition);

	/* 10.1 set partition limit and chunk num */
	chunk_num = 0;
	partition_limit = part_table[PART_DOWN].mem.size;

	while (chunk_num < fw_data_len / CHUNK_SIZE) {
		/* 10.2 update partition, if needed */
		addr = dest + (chunk_num + 2) * CHUNK_SIZE;
		if (addr > partition_limit) {
			addr = dest + chunk_num * CHUNK_SIZE;
			partition_limit = chunk_num * CHUNK_SIZE +
				part_table[PART_DOWN].mem.size;
			partition.mem.start = addr;
			wl1271_set_partition(wl, &partition);
		}

		/* 10.3 upload the chunk */
		addr = dest + chunk_num * CHUNK_SIZE;
		p = buf + chunk_num * CHUNK_SIZE;
		memcpy(chunk, p, CHUNK_SIZE);
		wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
			     p, addr);
		wl1271_spi_write(wl, addr, chunk, CHUNK_SIZE, false);

		chunk_num++;
	}

	/* 10.4 upload the last chunk */
	addr = dest + chunk_num * CHUNK_SIZE;
	p = buf + chunk_num * CHUNK_SIZE;
	memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
	wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
		     fw_data_len % CHUNK_SIZE, p, addr);
	wl1271_spi_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);

	kfree(chunk);
	return 0;
}

static int wl1271_boot_upload_firmware(struct wl1271 *wl)
{
	u32 chunks, addr, len;
	u8 *fw;

	fw = wl->fw;
	chunks = be32_to_cpup((u32 *) fw);
	fw += sizeof(u32);

	wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);

	while (chunks--) {
		addr = be32_to_cpup((u32 *) fw);
		fw += sizeof(u32);
		len = be32_to_cpup((u32 *) fw);
		fw += sizeof(u32);

		if (len > 300000) {
			wl1271_info("firmware chunk too long: %u", len);
			return -EINVAL;
		}
		wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
			     chunks, addr, len);
		wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
		fw += len;
	}

	return 0;
}

static int wl1271_boot_upload_nvs(struct wl1271 *wl)
{
	size_t nvs_len, burst_len;
	int i;
	u32 dest_addr, val;
	u8 *nvs_ptr, *nvs, *nvs_aligned;

	nvs = wl->nvs;
	if (nvs == NULL)
		return -ENODEV;

	nvs_ptr = nvs;

	nvs_len = wl->nvs_len;

	/* Update the device MAC address into the nvs */
	nvs[11] = wl->mac_addr[0];
	nvs[10] = wl->mac_addr[1];
	nvs[6] = wl->mac_addr[2];
	nvs[5] = wl->mac_addr[3];
	nvs[4] = wl->mac_addr[4];
	nvs[3] = wl->mac_addr[5];

	/*
	 * Layout before the actual NVS tables:
	 * 1 byte : burst length.
	 * 2 bytes: destination address.
	 * n bytes: data to burst copy.
	 *
	 * This is ended by a 0 length, then the NVS tables.
	 */

	/* FIXME: Do we need to check here whether the LSB is 1? */
	while (nvs_ptr[0]) {
		burst_len = nvs_ptr[0];
		dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));

		/* FIXME: Due to our new wl1271_translate_reg_addr function,
		   we need to add the REGISTER_BASE to the destination */
		dest_addr += REGISTERS_BASE;

		/* We move our pointer to the data */
		nvs_ptr += 3;

		for (i = 0; i < burst_len; i++) {
			val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
			       | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));

			wl1271_debug(DEBUG_BOOT,
				     "nvs burst write 0x%x: 0x%x",
				     dest_addr, val);
			wl1271_spi_write32(wl, dest_addr, val);

			nvs_ptr += 4;
			dest_addr += 4;
		}
	}

	/*
	 * We've reached the first zero length, the first NVS table
	 * is 7 bytes further.
	 */
	nvs_ptr += 7;
	nvs_len -= nvs_ptr - nvs;
	nvs_len = ALIGN(nvs_len, 4);

	/* FIXME: The driver sets the partition here, but this is not needed,
	   since it sets to the same one as currently in use */
	/* Now we must set the partition correctly */
	wl1271_set_partition(wl, &part_table[PART_WORK]);

	/* Copy the NVS tables to a new block to ensure alignment */
	nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);

	/* And finally we upload the NVS tables */
	/* FIXME: In wl1271, we upload everything at once.
	   No endianness handling needed here?! The ref driver doesn't do
	   anything about it at this point */
	wl1271_spi_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);

	kfree(nvs_aligned);
	return 0;
}

static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
{
	enable_irq(wl->irq);
	wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
			   WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
	wl1271_spi_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
}

static int wl1271_boot_soft_reset(struct wl1271 *wl)
{
	unsigned long timeout;
	u32 boot_data;

	/* perform soft reset */
	wl1271_spi_write32(wl, ACX_REG_SLV_SOFT_RESET,
			   ACX_SLV_SOFT_RESET_BIT);

	/* SOFT_RESET is self clearing */
	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	while (1) {
		boot_data = wl1271_spi_read32(wl, ACX_REG_SLV_SOFT_RESET);
		wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
		if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
			break;

		if (time_after(jiffies, timeout)) {
			/* 1.2 check pWhalBus->uSelfClearTime if the
			 * timeout was reached */
			wl1271_error("soft reset timeout");
			return -1;
		}

		udelay(SOFT_RESET_STALL_TIME);
	}

	/* disable Rx/Tx */
	wl1271_spi_write32(wl, ENABLE, 0x0);

	/* disable auto calibration on start*/
	wl1271_spi_write32(wl, SPARE_A2, 0xffff);

	return 0;
}

static int wl1271_boot_run_firmware(struct wl1271 *wl)
{
	int loop, ret;
	u32 chip_id, interrupt;

	wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);

	chip_id = wl1271_spi_read32(wl, CHIP_ID_B);

	wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);

	if (chip_id != wl->chip.id) {
		wl1271_error("chip id doesn't match after firmware boot");
		return -EIO;
	}

	/* wait for init to complete */
	loop = 0;
	while (loop++ < INIT_LOOP) {
		udelay(INIT_LOOP_DELAY);
		interrupt = wl1271_spi_read32(wl,
					      ACX_REG_INTERRUPT_NO_CLEAR);

		if (interrupt == 0xffffffff) {
			wl1271_error("error reading hardware complete "
				     "init indication");
			return -EIO;
		}
		/* check that ACX_INTR_INIT_COMPLETE is enabled */
		else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
			wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK,
					   WL1271_ACX_INTR_INIT_COMPLETE);
			break;
		}
	}

	if (loop >= INIT_LOOP) {
		wl1271_error("timeout waiting for the hardware to "
			     "complete initialization");
		return -EIO;
	}

	/* get hardware config command mail box */
	wl->cmd_box_addr = wl1271_spi_read32(wl, REG_COMMAND_MAILBOX_PTR);

	/* get hardware config event mail box */
	wl->event_box_addr = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR);

	/* set the working partition to its "running" mode offset */
	wl1271_set_partition(wl, &part_table[PART_WORK]);

	wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
		     wl->cmd_box_addr, wl->event_box_addr);

	wl1271_boot_fw_version(wl);

	/*
	 * in case of full asynchronous mode the firmware event must be
	 * ready to receive event from the command mailbox
	 */

	/* unmask required mbox events  */
	wl->event_mask = BSS_LOSE_EVENT_ID |
		SCAN_COMPLETE_EVENT_ID;

	ret = wl1271_event_unmask(wl);
	if (ret < 0) {
		wl1271_error("EVENT mask setting failed");
		return ret;
	}

	wl1271_event_mbox_config(wl);

	/* firmware startup completed */
	return 0;
}

static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
{
	u32 polarity;

	polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);

	/* We use HIGH polarity, so unset the LOW bit */
	polarity &= ~POLARITY_LOW;
	wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);

	return 0;
}

int wl1271_boot(struct wl1271 *wl)
{
	int ret = 0;
	u32 tmp, clk, pause;

	if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4)
		/* ref clk: 19.2/38.4/38.4-XTAL */
		clk = 0x3;
	else if (REF_CLOCK == 1 || REF_CLOCK == 3)
		/* ref clk: 26/52 */
		clk = 0x5;

	if (REF_CLOCK != 0) {
		u16 val;
		/* Set clock type */
		val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
		val &= FREF_CLK_TYPE_BITS;
		val |= CLK_REQ_PRCM;
		wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
	} else {
		u16 val;
		/* Set clock polarity */
		val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
		val &= FREF_CLK_POLARITY_BITS;
		val |= CLK_REQ_OUTN_SEL;
		wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
	}

	wl1271_spi_write32(wl, PLL_PARAMETERS, clk);

	pause = wl1271_spi_read32(wl, PLL_PARAMETERS);

	wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);

	pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
					   * WU_COUNTER_PAUSE_VAL instead of
					   * 0x3ff (magic number ).  How does
					   * this work?! */
	pause |= WU_COUNTER_PAUSE_VAL;
	wl1271_spi_write32(wl, WU_COUNTER_PAUSE, pause);

	/* Continue the ELP wake up sequence */
	wl1271_spi_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
	udelay(500);

	wl1271_set_partition(wl, &part_table[PART_DRPW]);

	/* Read-modify-write DRPW_SCRATCH_START register (see next state)
	   to be used by DRPw FW. The RTRIM value will be added by the FW
	   before taking DRPw out of reset */

	wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
	clk = wl1271_spi_read32(wl, DRPW_SCRATCH_START);

	wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);

	/* 2 */
	clk |= (REF_CLOCK << 1) << 4;
	wl1271_spi_write32(wl, DRPW_SCRATCH_START, clk);

	wl1271_set_partition(wl, &part_table[PART_WORK]);

	/* Disable interrupts */
	wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);

	ret = wl1271_boot_soft_reset(wl);
	if (ret < 0)
		goto out;

	/* 2. start processing NVS file */
	ret = wl1271_boot_upload_nvs(wl);
	if (ret < 0)
		goto out;

	/* write firmware's last address (ie. it's length) to
	 * ACX_EEPROMLESS_IND_REG */
	wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");

	wl1271_spi_write32(wl, ACX_EEPROMLESS_IND_REG,
			   ACX_EEPROMLESS_IND_REG);

	tmp = wl1271_spi_read32(wl, CHIP_ID_B);

	wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);

	/* 6. read the EEPROM parameters */
	tmp = wl1271_spi_read32(wl, SCR_PAD2);

	ret = wl1271_boot_write_irq_polarity(wl);
	if (ret < 0)
		goto out;

	/* FIXME: Need to check whether this is really what we want */
	wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
			   WL1271_ACX_ALL_EVENTS_VECTOR);

	/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
	 * to upload_fw) */

	ret = wl1271_boot_upload_firmware(wl);
	if (ret < 0)
		goto out;

	/* 10.5 start firmware */
	ret = wl1271_boot_run_firmware(wl);
	if (ret < 0)
		goto out;

	/* Enable firmware interrupts now */
	wl1271_boot_enable_interrupts(wl);

	/* set the wl1271 default filters */
	wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
	wl->rx_filter = WL1271_DEFAULT_RX_FILTER;

	wl1271_event_mbox_config(wl);

out:
	return ret;
}
Commit	Line	Data
f5fc0f86 LC	1	/*
	2	* This file is part of wl1271
	3	*
	4	* Copyright (C) 2008-2009 Nokia Corporation
	5	*
	6	* Contact: Luciano Coelho <luciano.coelho@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
	24	#include <linux/gpio.h>
	25
	26	#include "wl1271_acx.h"
	27	#include "wl1271_reg.h"
	28	#include "wl1271_boot.h"
	29	#include "wl1271_spi.h"
	30	#include "wl1271_event.h"
	31
	32	static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
	33	[PART_DOWN] = {
	34	.mem = {
	35	.start = 0x00000000,
	36	.size = 0x000177c0
	37	},
	38	.reg = {
	39	.start = REGISTERS_BASE,
	40	.size = 0x00008800
	41	},
451de97a JO	42	.mem2 = {
	43	.start = 0x00000000,
	44	.size = 0x00000000
	45	},
	46	.mem3 = {
	47	.start = 0x00000000,
	48	.size = 0x00000000
	49	},
f5fc0f86 LC	50	},
	51
	52	[PART_WORK] = {
	53	.mem = {
	54	.start = 0x00040000,
	55	.size = 0x00014fc0
	56	},
	57	.reg = {
	58	.start = REGISTERS_BASE,
451de97a JO	59	.size = 0x0000a000
	60	},
	61	.mem2 = {
	62	.start = 0x003004f8,
	63	.size = 0x00000004
	64	},
	65	.mem3 = {
	66	.start = 0x00040404,
	67	.size = 0x00000000
f5fc0f86 LC	68	},
	69	},
	70
	71	[PART_DRPW] = {
	72	.mem = {
	73	.start = 0x00040000,
	74	.size = 0x00014fc0
	75	},
	76	.reg = {
	77	.start = DRPW_BASE,
	78	.size = 0x00006000
451de97a JO	79	},
	80	.mem2 = {
	81	.start = 0x00000000,
	82	.size = 0x00000000
	83	},
	84	.mem3 = {
	85	.start = 0x00000000,
	86	.size = 0x00000000
f5fc0f86 LC	87	}
	88	}
	89	};
	90
	91	static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
	92	{
	93	u32 cpu_ctrl;
	94
	95	/* 10.5.0 run the firmware (I) */
74621417	96	cpu_ctrl = wl1271_spi_read32(wl, ACX_REG_ECPU_CONTROL);
f5fc0f86 LC	97
	98	/* 10.5.1 run the firmware (II) */
	99	cpu_ctrl \|= flag;
74621417	100	wl1271_spi_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
f5fc0f86 LC	101	}
	102
	103	static void wl1271_boot_fw_version(struct wl1271 *wl)
	104	{
	105	struct wl1271_static_data static_data;
	106
74621417 JO	107	wl1271_spi_read(wl, wl->cmd_box_addr,
74621417 JO	108	&static_data, sizeof(static_data), false);
f5fc0f86 LC	109
	110	strncpy(wl->chip.fw_ver, static_data.fw_version,
	111	sizeof(wl->chip.fw_ver));
	112
	113	/* make sure the string is NULL-terminated */
	114	wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
	115	}
	116
	117	static int wl1271_boot_upload_firmware_chunk(struct wl1271 wl, void buf,
	118	size_t fw_data_len, u32 dest)
	119	{
451de97a	120	struct wl1271_partition_set partition;
f5fc0f86	121	int addr, chunk_num, partition_limit;
1fba4974	122	u8 p, chunk;
f5fc0f86 LC	123
	124	/* whal_FwCtrl_LoadFwImageSm() */
	125
	126	wl1271_debug(DEBUG_BOOT, "starting firmware upload");
	127
73d0a13c LC	128	wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
73d0a13c LC	129	fw_data_len, CHUNK_SIZE);
f5fc0f86	130
f5fc0f86 LC	131	if ((fw_data_len % 4) != 0) {
	132	wl1271_error("firmware length not multiple of four");
	133	return -EIO;
	134	}
	135
1fba4974 JO	136	chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	137	if (!buf) {
	138	wl1271_error("allocation for firmware upload chunk failed");
	139	return -ENOMEM;
	140	}
	141
451de97a JO	142	memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
	143	partition.mem.start = dest;
	144	wl1271_set_partition(wl, &partition);
f5fc0f86 LC	145
	146	/* 10.1 set partition limit and chunk num */
	147	chunk_num = 0;
	148	partition_limit = part_table[PART_DOWN].mem.size;
	149
	150	while (chunk_num < fw_data_len / CHUNK_SIZE) {
	151	/* 10.2 update partition, if needed */
	152	addr = dest + (chunk_num + 2) * CHUNK_SIZE;
	153	if (addr > partition_limit) {
	154	addr = dest + chunk_num * CHUNK_SIZE;
	155	partition_limit = chunk_num * CHUNK_SIZE +
	156	part_table[PART_DOWN].mem.size;
451de97a JO	157	partition.mem.start = addr;
451de97a JO	158	wl1271_set_partition(wl, &partition);
f5fc0f86 LC	159	}
	160
	161	/* 10.3 upload the chunk */
	162	addr = dest + chunk_num * CHUNK_SIZE;
	163	p = buf + chunk_num * CHUNK_SIZE;
1fba4974	164	memcpy(chunk, p, CHUNK_SIZE);
f5fc0f86 LC	165	wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
f5fc0f86 LC	166	p, addr);
74621417	167	wl1271_spi_write(wl, addr, chunk, CHUNK_SIZE, false);
f5fc0f86 LC	168
	169	chunk_num++;
	170	}
	171
	172	/* 10.4 upload the last chunk */
	173	addr = dest + chunk_num * CHUNK_SIZE;
	174	p = buf + chunk_num * CHUNK_SIZE;
1fba4974	175	memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
73d0a13c	176	wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
f5fc0f86	177	fw_data_len % CHUNK_SIZE, p, addr);
74621417	178	wl1271_spi_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
f5fc0f86	179
1fba4974	180	kfree(chunk);
f5fc0f86 LC	181	return 0;
	182	}
	183
	184	static int wl1271_boot_upload_firmware(struct wl1271 *wl)
	185	{
	186	u32 chunks, addr, len;
	187	u8 *fw;
	188
	189	fw = wl->fw;
	190	chunks = be32_to_cpup((u32 *) fw);
	191	fw += sizeof(u32);
	192
	193	wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
	194
	195	while (chunks--) {
	196	addr = be32_to_cpup((u32 *) fw);
	197	fw += sizeof(u32);
	198	len = be32_to_cpup((u32 *) fw);
	199	fw += sizeof(u32);
	200
	201	if (len > 300000) {
	202	wl1271_info("firmware chunk too long: %u", len);
	203	return -EINVAL;
	204	}
	205	wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
	206	chunks, addr, len);
	207	wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
	208	fw += len;
	209	}
	210
	211	return 0;
	212	}
	213
	214	static int wl1271_boot_upload_nvs(struct wl1271 *wl)
	215	{
	216	size_t nvs_len, burst_len;
	217	int i;
	218	u32 dest_addr, val;
	219	u8 nvs_ptr, nvs, *nvs_aligned;
	220
	221	nvs = wl->nvs;
	222	if (nvs == NULL)
	223	return -ENODEV;
	224
	225	nvs_ptr = nvs;
	226
	227	nvs_len = wl->nvs_len;
	228
	229	/* Update the device MAC address into the nvs */
	230	nvs[11] = wl->mac_addr[0];
	231	nvs[10] = wl->mac_addr[1];
	232	nvs[6] = wl->mac_addr[2];
	233	nvs[5] = wl->mac_addr[3];
	234	nvs[4] = wl->mac_addr[4];
	235	nvs[3] = wl->mac_addr[5];
	236
	237	/*
	238	* Layout before the actual NVS tables:
	239	* 1 byte : burst length.
	240	* 2 bytes: destination address.
	241	* n bytes: data to burst copy.
	242	*
	243	* This is ended by a 0 length, then the NVS tables.
	244	*/
245
246	/* FIXME: Do we need to check here whether the LSB is 1? */
247	while (nvs_ptr[0]) {
248	burst_len = nvs_ptr[0];
249	dest_addr = (nvs_ptr[1] & 0xfe) \| ((u32)(nvs_ptr[2] << 8));
250
251	/* FIXME: Due to our new wl1271_translate_reg_addr function,
252	we need to add the REGISTER_BASE to the destination */
253	dest_addr += REGISTERS_BASE;
254
255	/* We move our pointer to the data */
256	nvs_ptr += 3;
257
258	for (i = 0; i < burst_len; i++) {
259	val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
260	\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));
261
262	wl1271_debug(DEBUG_BOOT,
263	"nvs burst write 0x%x: 0x%x",
264	dest_addr, val);
74621417	265	wl1271_spi_write32(wl, dest_addr, val);
f5fc0f86 LC	266
	267	nvs_ptr += 4;
	268	dest_addr += 4;
	269	}
	270	}
	271
	272	/*
	273	* We've reached the first zero length, the first NVS table
	274	* is 7 bytes further.
	275	*/
	276	nvs_ptr += 7;
	277	nvs_len -= nvs_ptr - nvs;
	278	nvs_len = ALIGN(nvs_len, 4);
	279
	280	/* FIXME: The driver sets the partition here, but this is not needed,
	281	since it sets to the same one as currently in use */
	282	/* Now we must set the partition correctly */
451de97a	283	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	284
	285	/* Copy the NVS tables to a new block to ensure alignment */
	286	nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
	287
	288	/* And finally we upload the NVS tables */
	289	/* FIXME: In wl1271, we upload everything at once.
	290	No endianness handling needed here?! The ref driver doesn't do
	291	anything about it at this point */
74621417	292	wl1271_spi_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
f5fc0f86 LC	293
	294	kfree(nvs_aligned);
	295	return 0;
	296	}
	297
	298	static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
	299	{
	300	enable_irq(wl->irq);
74621417	301	wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
73d0a13c	302	WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
74621417	303	wl1271_spi_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
f5fc0f86 LC	304	}
	305
	306	static int wl1271_boot_soft_reset(struct wl1271 *wl)
	307	{
	308	unsigned long timeout;
	309	u32 boot_data;
	310
	311	/* perform soft reset */
74621417 JO	312	wl1271_spi_write32(wl, ACX_REG_SLV_SOFT_RESET,
74621417 JO	313	ACX_SLV_SOFT_RESET_BIT);
f5fc0f86 LC	314
	315	/* SOFT_RESET is self clearing */
	316	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	317	while (1) {
74621417	318	boot_data = wl1271_spi_read32(wl, ACX_REG_SLV_SOFT_RESET);
f5fc0f86 LC	319	wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
	320	if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
	321	break;
	322
	323	if (time_after(jiffies, timeout)) {
	324	/* 1.2 check pWhalBus->uSelfClearTime if the
	325	* timeout was reached */
	326	wl1271_error("soft reset timeout");
	327	return -1;
	328	}
	329
	330	udelay(SOFT_RESET_STALL_TIME);
	331	}
	332
	333	/* disable Rx/Tx */
74621417	334	wl1271_spi_write32(wl, ENABLE, 0x0);
f5fc0f86 LC	335
f5fc0f86 LC	336	/* disable auto calibration on start*/
74621417	337	wl1271_spi_write32(wl, SPARE_A2, 0xffff);
f5fc0f86 LC	338
	339	return 0;
	340	}
	341
	342	static int wl1271_boot_run_firmware(struct wl1271 *wl)
	343	{
	344	int loop, ret;
	345	u32 chip_id, interrupt;
	346
	347	wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
	348
74621417	349	chip_id = wl1271_spi_read32(wl, CHIP_ID_B);
f5fc0f86 LC	350
	351	wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
	352
	353	if (chip_id != wl->chip.id) {
	354	wl1271_error("chip id doesn't match after firmware boot");
	355	return -EIO;
	356	}
	357
	358	/* wait for init to complete */
	359	loop = 0;
	360	while (loop++ < INIT_LOOP) {
	361	udelay(INIT_LOOP_DELAY);
74621417 JO	362	interrupt = wl1271_spi_read32(wl,
74621417 JO	363	ACX_REG_INTERRUPT_NO_CLEAR);
f5fc0f86 LC	364
	365	if (interrupt == 0xffffffff) {
	366	wl1271_error("error reading hardware complete "
	367	"init indication");
	368	return -EIO;
	369	}
	370	/* check that ACX_INTR_INIT_COMPLETE is enabled */
	371	else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
74621417	372	wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK,
f5fc0f86 LC	373	WL1271_ACX_INTR_INIT_COMPLETE);
	374	break;
	375	}
	376	}
	377
	378	if (loop >= INIT_LOOP) {
	379	wl1271_error("timeout waiting for the hardware to "
	380	"complete initialization");
	381	return -EIO;
	382	}
	383
	384	/* get hardware config command mail box */
74621417	385	wl->cmd_box_addr = wl1271_spi_read32(wl, REG_COMMAND_MAILBOX_PTR);
f5fc0f86 LC	386
f5fc0f86 LC	387	/* get hardware config event mail box */
74621417	388	wl->event_box_addr = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR);
f5fc0f86 LC	389
f5fc0f86 LC	390	/* set the working partition to its "running" mode offset */
451de97a	391	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	392
	393	wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
	394	wl->cmd_box_addr, wl->event_box_addr);
	395
	396	wl1271_boot_fw_version(wl);
	397
	398	/*
	399	* in case of full asynchronous mode the firmware event must be
	400	* ready to receive event from the command mailbox
	401	*/
	402
be823e5b JO	403	/* unmask required mbox events */
	404	wl->event_mask = BSS_LOSE_EVENT_ID \|
	405	SCAN_COMPLETE_EVENT_ID;
f5fc0f86 LC	406
	407	ret = wl1271_event_unmask(wl);
	408	if (ret < 0) {
	409	wl1271_error("EVENT mask setting failed");
	410	return ret;
	411	}
	412
	413	wl1271_event_mbox_config(wl);
	414
	415	/* firmware startup completed */
	416	return 0;
	417	}
	418
	419	static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
	420	{
e8768eeb	421	u32 polarity;
f5fc0f86	422
e8768eeb	423	polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
f5fc0f86 LC	424
	425	/* We use HIGH polarity, so unset the LOW bit */
	426	polarity &= ~POLARITY_LOW;
e8768eeb	427	wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
f5fc0f86 LC	428
	429	return 0;
	430	}
	431
	432	int wl1271_boot(struct wl1271 *wl)
	433	{
	434	int ret = 0;
	435	u32 tmp, clk, pause;
	436
284134eb JO	437	if (REF_CLOCK == 0 \|\| REF_CLOCK == 2 \|\| REF_CLOCK == 4)
284134eb JO	438	/* ref clk: 19.2/38.4/38.4-XTAL */
f5fc0f86 LC	439	clk = 0x3;
	440	else if (REF_CLOCK == 1 \|\| REF_CLOCK == 3)
	441	/* ref clk: 26/52 */
	442	clk = 0x5;
	443
284134eb JO	444	if (REF_CLOCK != 0) {
	445	u16 val;
	446	/* Set clock type */
	447	val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
	448	val &= FREF_CLK_TYPE_BITS;
	449	val \|= CLK_REQ_PRCM;
	450	wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
	451	} else {
	452	u16 val;
	453	/* Set clock polarity */
	454	val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
	455	val &= FREF_CLK_POLARITY_BITS;
	456	val \|= CLK_REQ_OUTN_SEL;
	457	wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
	458	}
	459
74621417	460	wl1271_spi_write32(wl, PLL_PARAMETERS, clk);
f5fc0f86	461
74621417	462	pause = wl1271_spi_read32(wl, PLL_PARAMETERS);
f5fc0f86 LC	463
	464	wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
	465
	466	pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
	467	* WU_COUNTER_PAUSE_VAL instead of
	468	* 0x3ff (magic number ). How does
	469	* this work?! */
	470	pause \|= WU_COUNTER_PAUSE_VAL;
74621417	471	wl1271_spi_write32(wl, WU_COUNTER_PAUSE, pause);
f5fc0f86 LC	472
f5fc0f86 LC	473	/* Continue the ELP wake up sequence */
74621417	474	wl1271_spi_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
f5fc0f86 LC	475	udelay(500);
f5fc0f86 LC	476
451de97a	477	wl1271_set_partition(wl, &part_table[PART_DRPW]);
f5fc0f86 LC	478
	479	/* Read-modify-write DRPW_SCRATCH_START register (see next state)
	480	to be used by DRPw FW. The RTRIM value will be added by the FW
	481	before taking DRPw out of reset */
	482
	483	wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
74621417	484	clk = wl1271_spi_read32(wl, DRPW_SCRATCH_START);
f5fc0f86 LC	485
	486	wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
	487
	488	/* 2 */
	489	clk \|= (REF_CLOCK << 1) << 4;
74621417	490	wl1271_spi_write32(wl, DRPW_SCRATCH_START, clk);
f5fc0f86	491
451de97a	492	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	493
f5fc0f86 LC	494	/* Disable interrupts */
74621417	495	wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
f5fc0f86 LC	496
	497	ret = wl1271_boot_soft_reset(wl);
	498	if (ret < 0)
	499	goto out;
	500
	501	/* 2. start processing NVS file */
	502	ret = wl1271_boot_upload_nvs(wl);
	503	if (ret < 0)
	504	goto out;
	505
	506	/* write firmware's last address (ie. it's length) to
	507	* ACX_EEPROMLESS_IND_REG */
	508	wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
	509
74621417 JO	510	wl1271_spi_write32(wl, ACX_EEPROMLESS_IND_REG,
74621417 JO	511	ACX_EEPROMLESS_IND_REG);
f5fc0f86	512
74621417	513	tmp = wl1271_spi_read32(wl, CHIP_ID_B);
f5fc0f86 LC	514
	515	wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
	516
	517	/* 6. read the EEPROM parameters */
74621417	518	tmp = wl1271_spi_read32(wl, SCR_PAD2);
f5fc0f86 LC	519
	520	ret = wl1271_boot_write_irq_polarity(wl);
	521	if (ret < 0)
	522	goto out;
	523
	524	/* FIXME: Need to check whether this is really what we want */
74621417	525	wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
f5fc0f86 LC	526	WL1271_ACX_ALL_EVENTS_VECTOR);
	527
	528	/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
	529	* to upload_fw) */
	530
	531	ret = wl1271_boot_upload_firmware(wl);
	532	if (ret < 0)
	533	goto out;
	534
	535	/* 10.5 start firmware */
	536	ret = wl1271_boot_run_firmware(wl);
	537	if (ret < 0)
	538	goto out;
	539
eb5b28d0 JO	540	/* Enable firmware interrupts now */
	541	wl1271_boot_enable_interrupts(wl);
	542
f5fc0f86 LC	543	/* set the wl1271 default filters */
	544	wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
	545	wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
	546
	547	wl1271_event_mbox_config(wl);
	548
	549	out:
	550	return ret;
	551	}