projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
wl1271: add workaround to avoid distortion due to excessive tx power
[linux-2.6-block.git] / drivers / net / wireless / wl12xx / wl1271_acx.h
CommitLineData
f5fc0f86
LC		 1/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __WL1271_ACX_H__
26#define __WL1271_ACX_H__
27
28#include "wl1271.h"
29#include "wl1271_cmd.h"
30
31/*************************************************************************
32
33 Host Interrupt Register (WiLink -> Host)
34
35**************************************************************************/
36/* HW Initiated interrupt Watchdog timer expiration */
37#define WL1271_ACX_INTR_WATCHDOG BIT(0)
38/* Init sequence is done (masked interrupt, detection through polling only ) */
39#define WL1271_ACX_INTR_INIT_COMPLETE BIT(1)
40/* Event was entered to Event MBOX #A*/
41#define WL1271_ACX_INTR_EVENT_A BIT(2)
42/* Event was entered to Event MBOX #B*/
43#define WL1271_ACX_INTR_EVENT_B BIT(3)
44/* Command processing completion*/
45#define WL1271_ACX_INTR_CMD_COMPLETE BIT(4)
46/* Signaling the host on HW wakeup */
47#define WL1271_ACX_INTR_HW_AVAILABLE BIT(5)
48/* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
49#define WL1271_ACX_INTR_DATA BIT(6)
50/* Trace meassge on MBOX #A */
51#define WL1271_ACX_INTR_TRACE_A BIT(7)
52/* Trace meassge on MBOX #B */
53#define WL1271_ACX_INTR_TRACE_B BIT(8)
54
55#define WL1271_ACX_INTR_ALL 0xFFFFFFFF
56#define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
57 WL1271_ACX_INTR_INIT_COMPLETE | \
58 WL1271_ACX_INTR_EVENT_A | \
59 WL1271_ACX_INTR_EVENT_B | \
60 WL1271_ACX_INTR_CMD_COMPLETE | \
61 WL1271_ACX_INTR_HW_AVAILABLE | \
62 WL1271_ACX_INTR_DATA)
63
64#define WL1271_INTR_MASK (WL1271_ACX_INTR_EVENT_A | \
65 WL1271_ACX_INTR_EVENT_B | \
66 WL1271_ACX_INTR_DATA)
67
68/* Target's information element */
69struct acx_header {
70 struct wl1271_cmd_header cmd;
71
72 /* acx (or information element) header */
73 u16 id;
74
75 /* payload length (not including headers */
76 u16 len;
77};
78
79struct acx_error_counter {
80 struct acx_header header;
81
82 /* The number of PLCP errors since the last time this */
83 /* information element was interrogated. This field is */
84 /* automatically cleared when it is interrogated.*/
85 u32 PLCP_error;
86
87 /* The number of FCS errors since the last time this */
88 /* information element was interrogated. This field is */
89 /* automatically cleared when it is interrogated.*/
90 u32 FCS_error;
91
92 /* The number of MPDUs without PLCP header errors received*/
93 /* since the last time this information element was interrogated. */
94 /* This field is automatically cleared when it is interrogated.*/
95 u32 valid_frame;
96
97 /* the number of missed sequence numbers in the squentially */
98 /* values of frames seq numbers */
99 u32 seq_num_miss;
100} __attribute__ ((packed));
101
102struct acx_revision {
103 struct acx_header header;
104
105 /*
106 * The WiLink firmware version, an ASCII string x.x.x.x,
107 * that uniquely identifies the current firmware.
108 * The left most digit is incremented each time a
109 * significant change is made to the firmware, such as
110 * code redesign or new platform support.
111 * The second digit is incremented when major enhancements
112 * are added or major fixes are made.
113 * The third digit is incremented for each GA release.
114 * The fourth digit is incremented for each build.
115 * The first two digits identify a firmware release version,
116 * in other words, a unique set of features.
117 * The first three digits identify a GA release.
118 */
119 char fw_version[20];
120
121 /*
122 * This 4 byte field specifies the WiLink hardware version.
123 * bits 0 - 15: Reserved.
124 * bits 16 - 23: Version ID - The WiLink version ID
125 * (1 = first spin, 2 = second spin, and so on).
126 * bits 24 - 31: Chip ID - The WiLink chip ID.
127 */
128 u32 hw_version;
129} __attribute__ ((packed));
130
131enum wl1271_psm_mode {
132 /* Active mode */
133 WL1271_PSM_CAM = 0,
134
135 /* Power save mode */
136 WL1271_PSM_PS = 1,
137
138 /* Extreme low power */
139 WL1271_PSM_ELP = 2,
140};
141
142struct acx_sleep_auth {
143 struct acx_header header;
144
145 /* The sleep level authorization of the device. */
146 /* 0 - Always active*/
147 /* 1 - Power down mode: light / fast sleep*/
148 /* 2 - ELP mode: Deep / Max sleep*/
149 u8 sleep_auth;
150 u8 padding[3];
151} __attribute__ ((packed));
152
153enum {
154 HOSTIF_PCI_MASTER_HOST_INDIRECT,
155 HOSTIF_PCI_MASTER_HOST_DIRECT,
156 HOSTIF_SLAVE,
157 HOSTIF_PKT_RING,
158 HOSTIF_DONTCARE = 0xFF
159};
160
161#define DEFAULT_UCAST_PRIORITY 0
162#define DEFAULT_RX_Q_PRIORITY 0
163#define DEFAULT_NUM_STATIONS 1
164#define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
165#define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
166#define TRACE_BUFFER_MAX_SIZE 256
167
168#define DP_RX_PACKET_RING_CHUNK_SIZE 1600
169#define DP_TX_PACKET_RING_CHUNK_SIZE 1600
170#define DP_RX_PACKET_RING_CHUNK_NUM 2
171#define DP_TX_PACKET_RING_CHUNK_NUM 2
172#define DP_TX_COMPLETE_TIME_OUT 20
f5fc0f86
LC		 173
174#define TX_MSDU_LIFETIME_MIN 0
175#define TX_MSDU_LIFETIME_MAX 3000
176#define TX_MSDU_LIFETIME_DEF 512
177#define RX_MSDU_LIFETIME_MIN 0
178#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
179#define RX_MSDU_LIFETIME_DEF 512000
180
181struct acx_rx_msdu_lifetime {
182 struct acx_header header;
183
184 /*
185 * The maximum amount of time, in TU, before the
186 * firmware discards the MSDU.
187 */
188 u32 lifetime;
189} __attribute__ ((packed));
190
191/*
192 * RX Config Options Table
193 * Bit Definition
194 * === ==========
195 * 31:14 Reserved
196 * 13 Copy RX Status - when set, write three receive status words
197 * to top of rx'd MPDUs.
198 * When cleared, do not write three status words (added rev 1.5)
199 * 12 Reserved
200 * 11 RX Complete upon FCS error - when set, give rx complete
201 * interrupt for FCS errors, after the rx filtering, e.g. unicast
202 * frames not to us with FCS error will not generate an interrupt.
203 * 10 SSID Filter Enable - When set, the WiLink discards all beacon,
204 * probe request, and probe response frames with an SSID that does
205 * not match the SSID specified by the host in the START/JOIN
206 * command.
207 * When clear, the WiLink receives frames with any SSID.
208 * 9 Broadcast Filter Enable - When set, the WiLink discards all
209 * broadcast frames. When clear, the WiLink receives all received
210 * broadcast frames.
211 * 8:6 Reserved
212 * 5 BSSID Filter Enable - When set, the WiLink discards any frames
213 * with a BSSID that does not match the BSSID specified by the
214 * host.
215 * When clear, the WiLink receives frames from any BSSID.
216 * 4 MAC Addr Filter - When set, the WiLink discards any frames
217 * with a destination address that does not match the MAC address
218 * of the adaptor.
219 * When clear, the WiLink receives frames destined to any MAC
220 * address.
221 * 3 Promiscuous - When set, the WiLink receives all valid frames
222 * (i.e., all frames that pass the FCS check).
223 * When clear, only frames that pass the other filters specified
224 * are received.
225 * 2 FCS - When set, the WiLink includes the FCS with the received
226 * frame.
227 * When cleared, the FCS is discarded.
228 * 1 PLCP header - When set, write all data from baseband to frame
229 * buffer including PHY header.
230 * 0 Reserved - Always equal to 0.
231 *
232 * RX Filter Options Table
233 * Bit Definition
234 * === ==========
235 * 31:12 Reserved - Always equal to 0.
236 * 11 Association - When set, the WiLink receives all association
237 * related frames (association request/response, reassocation
238 * request/response, and disassociation). When clear, these frames
239 * are discarded.
240 * 10 Auth/De auth - When set, the WiLink receives all authentication
241 * and de-authentication frames. When clear, these frames are
242 * discarded.
243 * 9 Beacon - When set, the WiLink receives all beacon frames.
244 * When clear, these frames are discarded.
245 * 8 Contention Free - When set, the WiLink receives all contention
246 * free frames.
247 * When clear, these frames are discarded.
248 * 7 Control - When set, the WiLink receives all control frames.
249 * When clear, these frames are discarded.
250 * 6 Data - When set, the WiLink receives all data frames.
251 * When clear, these frames are discarded.
252 * 5 FCS Error - When set, the WiLink receives frames that have FCS
253 * errors.
254 * When clear, these frames are discarded.
255 * 4 Management - When set, the WiLink receives all management
256 * frames.
257 * When clear, these frames are discarded.
258 * 3 Probe Request - When set, the WiLink receives all probe request
259 * frames.
260 * When clear, these frames are discarded.
261 * 2 Probe Response - When set, the WiLink receives all probe
262 * response frames.
263 * When clear, these frames are discarded.
264 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
265 * frames.
266 * When clear, these frames are discarded.
267 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames
268 * that have reserved frame types and sub types as defined by the
269 * 802.11 specification.
270 * When clear, these frames are discarded.
271 */
272struct acx_rx_config {
273 struct acx_header header;
274
275 u32 config_options;
276 u32 filter_options;
277} __attribute__ ((packed));
278
279struct acx_packet_detection {
280 struct acx_header header;
281
282 u32 threshold;
283} __attribute__ ((packed));
284
285
286enum acx_slot_type {
287 SLOT_TIME_LONG = 0,
288 SLOT_TIME_SHORT = 1,
289 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
290 MAX_SLOT_TIMES = 0xFF
291};
292
293#define STATION_WONE_INDEX 0
294
295struct acx_slot {
296 struct acx_header header;
297
298 u8 wone_index; /* Reserved */
299 u8 slot_time;
300 u8 reserved[6];
301} __attribute__ ((packed));
302
303
c87dec9f
JO		 304#define ACX_MC_ADDRESS_GROUP_MAX (8)
305#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
f5fc0f86
LC		 306
307struct acx_dot11_grp_addr_tbl {
308 struct acx_header header;
309
310 u8 enabled;
311 u8 num_groups;
312 u8 pad[2];
313 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
314} __attribute__ ((packed));
315
f5fc0f86
LC		 316#define RX_TIMEOUT_PS_POLL_MIN 0
317#define RX_TIMEOUT_PS_POLL_MAX (200000)
318#define RX_TIMEOUT_PS_POLL_DEF (15)
319#define RX_TIMEOUT_UPSD_MIN 0
320#define RX_TIMEOUT_UPSD_MAX (200000)
321#define RX_TIMEOUT_UPSD_DEF (15)
322
323struct acx_rx_timeout {
324 struct acx_header header;
325
326 /*
327 * The longest time the STA will wait to receive
328 * traffic from the AP after a PS-poll has been
329 * transmitted.
330 */
331 u16 ps_poll_timeout;
332
333 /*
334 * The longest time the STA will wait to receive
335 * traffic from the AP after a frame has been sent
336 * from an UPSD enabled queue.
337 */
338 u16 upsd_timeout;
339} __attribute__ ((packed));
340
341#define RTS_THRESHOLD_MIN 0
342#define RTS_THRESHOLD_MAX 4096
343#define RTS_THRESHOLD_DEF 2347
344
345struct acx_rts_threshold {
346 struct acx_header header;
347
348 u16 threshold;
349 u8 pad[2];
350} __attribute__ ((packed));
351
352struct acx_beacon_filter_option {
353 struct acx_header header;
354
355 u8 enable;
356
357 /*
358 * The number of beacons without the unicast TIM
359 * bit set that the firmware buffers before
360 * signaling the host about ready frames.
361 * When set to 0 and the filter is enabled, beacons
362 * without the unicast TIM bit set are dropped.
363 */
364 u8 max_num_beacons;
365 u8 pad[2];
366} __attribute__ ((packed));
367
368/*
369 * ACXBeaconFilterEntry (not 221)
370 * Byte Offset Size (Bytes) Definition
371 * =========== ============ ==========
372 * 0 1 IE identifier
373 * 1 1 Treatment bit mask
374 *
375 * ACXBeaconFilterEntry (221)
376 * Byte Offset Size (Bytes) Definition
377 * =========== ============ ==========
378 * 0 1 IE identifier
379 * 1 1 Treatment bit mask
380 * 2 3 OUI
381 * 5 1 Type
382 * 6 2 Version
383 *
384 *
385 * Treatment bit mask - The information element handling:
386 * bit 0 - The information element is compared and transferred
387 * in case of change.
388 * bit 1 - The information element is transferred to the host
389 * with each appearance or disappearance.
390 * Note that both bits can be set at the same time.
391 */
392#define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
393#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
394#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
395#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
396#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
397 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
398 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
399 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
400
1922167b
JO		 401#define BEACON_RULE_PASS_ON_CHANGE BIT(0)
402#define BEACON_RULE_PASS_ON_APPEARANCE BIT(1)
403
404#define BEACON_FILTER_IE_ID_CHANNEL_SWITCH_ANN (37)
405
f5fc0f86
LC		 406struct acx_beacon_filter_ie_table {
407 struct acx_header header;
408
409 u8 num_ie;
410 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
411 u8 pad[3];
412} __attribute__ ((packed));
413
34415236
JO		 414#define SYNCH_FAIL_DEFAULT_THRESHOLD 5 /* number of beacons */
415#define NO_BEACON_DEFAULT_TIMEOUT (100) /* TU */
416
417struct acx_conn_monit_params {
418 struct acx_header header;
419
420 u32 synch_fail_thold; /* number of beacons missed */
421 u32 bss_lose_timeout; /* number of TU's from synch fail */
422};
423
f5fc0f86
LC		 424enum {
425 SG_ENABLE = 0,
426 SG_DISABLE,
427 SG_SENSE_NO_ACTIVITY,
428 SG_SENSE_ACTIVE
429};
430
431struct acx_bt_wlan_coex {
432 struct acx_header header;
433
434 /*
435 * 0 -> PTA enabled
436 * 1 -> PTA disabled
437 * 2 -> sense no active mode, i.e.
438 * an interrupt is sent upon
439 * BT activity.
440 * 3 -> PTA is switched on in response
441 * to the interrupt sending.
442 */
443 u8 enable;
444 u8 pad[3];
445} __attribute__ ((packed));
446
447#define PTA_ANTENNA_TYPE_DEF (0)
448#define PTA_BT_HP_MAXTIME_DEF (2000)
449#define PTA_WLAN_HP_MAX_TIME_DEF (5000)
450#define PTA_SENSE_DISABLE_TIMER_DEF (1350)
451#define PTA_PROTECTIVE_RX_TIME_DEF (1500)
452#define PTA_PROTECTIVE_TX_TIME_DEF (1500)
453#define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000)
454#define PTA_SIGNALING_TYPE_DEF (1)
455#define PTA_AFH_LEVERAGE_ON_DEF (0)
456#define PTA_NUMBER_QUIET_CYCLE_DEF (0)
457#define PTA_MAX_NUM_CTS_DEF (3)
458#define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2)
459#define PTA_NUMBER_OF_BT_PACKETS_DEF (2)
460#define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500)
461#define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000)
462#define PTA_CYCLE_TIME_FAST_DEF (8700)
463#define PTA_RX_FOR_AVALANCHE_DEF (5)
464#define PTA_ELP_HP_DEF (0)
465#define PTA_ANTI_STARVE_PERIOD_DEF (500)
466#define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4)
467#define PTA_ALLOW_PA_SD_DEF (1)
468#define PTA_TIME_BEFORE_BEACON_DEF (6300)
469#define PTA_HPDM_MAX_TIME_DEF (1600)
470#define PTA_TIME_OUT_NEXT_WLAN_DEF (2550)
471#define PTA_AUTO_MODE_NO_CTS_DEF (0)
472#define PTA_BT_HP_RESPECTED_DEF (3)
473#define PTA_WLAN_RX_MIN_RATE_DEF (24)
474#define PTA_ACK_MODE_DEF (1)
475
476struct acx_bt_wlan_coex_param {
477 struct acx_header header;
478
479 /*
480 * The minimum rate of a received WLAN packet in the STA,
481 * during protective mode, of which a new BT-HP request
482 * during this Rx will always be respected and gain the antenna.
483 */
484 u32 min_rate;
485
486 /* Max time the BT HP will be respected. */
487 u16 bt_hp_max_time;
488
489 /* Max time the WLAN HP will be respected. */
490 u16 wlan_hp_max_time;
491
492 /*
493 * The time between the last BT activity
494 * and the moment when the sense mode returns
495 * to SENSE_INACTIVE.
496 */
497 u16 sense_disable_timer;
498
499 /* Time before the next BT HP instance */
500 u16 rx_time_bt_hp;
501 u16 tx_time_bt_hp;
502
503 /* range: 10-20000 default: 1500 */
504 u16 rx_time_bt_hp_fast;
505 u16 tx_time_bt_hp_fast;
506
507 /* range: 2000-65535 default: 8700 */
508 u16 wlan_cycle_fast;
509
510 /* range: 0 - 15000 (Msec) default: 1000 */
511 u16 bt_anti_starvation_period;
512
513 /* range 400-10000(Usec) default: 3000 */
514 u16 next_bt_lp_packet;
515
516 /* Deafult: worst case for BT DH5 traffic */
517 u16 wake_up_beacon;
518
519 /* range: 0-50000(Usec) default: 1050 */
520 u16 hp_dm_max_guard_time;
521
522 /*
523 * This is to prevent both BT & WLAN antenna
524 * starvation.
525 * Range: 100-50000(Usec) default:2550
526 */
527 u16 next_wlan_packet;
528
529 /* 0 -> shared antenna */
530 u8 antenna_type;
531
532 /*
533 * 0 -> TI legacy
534 * 1 -> Palau
535 */
536 u8 signal_type;
537
538 /*
539 * BT AFH status
540 * 0 -> no AFH
541 * 1 -> from dedicated GPIO
542 * 2 -> AFH on (from host)
543 */
544 u8 afh_leverage_on;
545
546 /*
547 * The number of cycles during which no
548 * TX will be sent after 1 cycle of RX
549 * transaction in protective mode
550 */
551 u8 quiet_cycle_num;
552
553 /*
554 * The maximum number of CTSs that will
555 * be sent for receiving RX packet in
556 * protective mode
557 */
558 u8 max_cts;
559
560 /*
561 * The number of WLAN packets
562 * transferred in common mode before
563 * switching to BT.
564 */
565 u8 wlan_packets_num;
566
567 /*
568 * The number of BT packets
569 * transferred in common mode before
570 * switching to WLAN.
571 */
572 u8 bt_packets_num;
573
574 /* range: 1-255 default: 5 */
575 u8 missed_rx_avalanche;
576
577 /* range: 0-1 default: 1 */
578 u8 wlan_elp_hp;
579
580 /* range: 0 - 15 default: 4 */
581 u8 bt_anti_starvation_cycles;
582
583 u8 ack_mode_dual_ant;
584
585 /*
586 * Allow PA_SD assertion/de-assertion
587 * during enabled BT activity.
588 */
589 u8 pa_sd_enable;
590
591 /*
592 * Enable/Disable PTA in auto mode:
593 * Support Both Active & P.S modes
594 */
595 u8 pta_auto_mode_enable;
596
597 /* range: 0 - 20 default: 1 */
598 u8 bt_hp_respected_num;
599} __attribute__ ((packed));
600
601#define CCA_THRSH_ENABLE_ENERGY_D 0x140A
602#define CCA_THRSH_DISABLE_ENERGY_D 0xFFEF
603
604struct acx_energy_detection {
605 struct acx_header header;
606
607 /* The RX Clear Channel Assessment threshold in the PHY */
608 u16 rx_cca_threshold;
609 u8 tx_energy_detection;
610 u8 pad;
611} __attribute__ ((packed));
612
613#define BCN_RX_TIMEOUT_DEF_VALUE 10000
614#define BROADCAST_RX_TIMEOUT_DEF_VALUE 20000
615#define RX_BROADCAST_IN_PS_DEF_VALUE 1
616#define CONSECUTIVE_PS_POLL_FAILURE_DEF 4
617
618struct acx_beacon_broadcast {
619 struct acx_header header;
620
621 u16 beacon_rx_timeout;
622 u16 broadcast_timeout;
623
624 /* Enables receiving of broadcast packets in PS mode */
625 u8 rx_broadcast_in_ps;
626
627 /* Consecutive PS Poll failures before updating the host */
628 u8 ps_poll_threshold;
629 u8 pad[2];
630} __attribute__ ((packed));
631
632struct acx_event_mask {
633 struct acx_header header;
634
635 u32 event_mask;
636 u32 high_event_mask; /* Unused */
637} __attribute__ ((packed));
638
639#define CFG_RX_FCS BIT(2)
640#define CFG_RX_ALL_GOOD BIT(3)
641#define CFG_UNI_FILTER_EN BIT(4)
642#define CFG_BSSID_FILTER_EN BIT(5)
643#define CFG_MC_FILTER_EN BIT(6)
644#define CFG_MC_ADDR0_EN BIT(7)
645#define CFG_MC_ADDR1_EN BIT(8)
646#define CFG_BC_REJECT_EN BIT(9)
647#define CFG_SSID_FILTER_EN BIT(10)
648#define CFG_RX_INT_FCS_ERROR BIT(11)
649#define CFG_RX_INT_ENCRYPTED BIT(12)
650#define CFG_RX_WR_RX_STATUS BIT(13)
651#define CFG_RX_FILTER_NULTI BIT(14)
652#define CFG_RX_RESERVE BIT(15)
653#define CFG_RX_TIMESTAMP_TSF BIT(16)
654
655#define CFG_RX_RSV_EN BIT(0)
656#define CFG_RX_RCTS_ACK BIT(1)
657#define CFG_RX_PRSP_EN BIT(2)
658#define CFG_RX_PREQ_EN BIT(3)
659#define CFG_RX_MGMT_EN BIT(4)
660#define CFG_RX_FCS_ERROR BIT(5)
661#define CFG_RX_DATA_EN BIT(6)
662#define CFG_RX_CTL_EN BIT(7)
663#define CFG_RX_CF_EN BIT(8)
664#define CFG_RX_BCN_EN BIT(9)
665#define CFG_RX_AUTH_EN BIT(10)
666#define CFG_RX_ASSOC_EN BIT(11)
667
668#define SCAN_PASSIVE BIT(0)
669#define SCAN_5GHZ_BAND BIT(1)
670#define SCAN_TRIGGERED BIT(2)
671#define SCAN_PRIORITY_HIGH BIT(3)
672
673struct acx_feature_config {
674 struct acx_header header;
675
676 u32 options;
677 u32 data_flow_options;
678} __attribute__ ((packed));
679
680struct acx_current_tx_power {
681 struct acx_header header;
682
683 u8 current_tx_power;
684 u8 padding[3];
685} __attribute__ ((packed));
686
687enum acx_wake_up_event {
688 WAKE_UP_EVENT_BEACON_BITMAP = 0x01, /* Wake on every Beacon*/
689 WAKE_UP_EVENT_DTIM_BITMAP = 0x02, /* Wake on every DTIM*/
690 WAKE_UP_EVENT_N_DTIM_BITMAP = 0x04, /* Wake on every Nth DTIM */
691 WAKE_UP_EVENT_N_BEACONS_BITMAP = 0x08, /* Wake on every Nth Beacon */
692 WAKE_UP_EVENT_BITS_MASK = 0x0F
693};
694
695struct acx_wake_up_condition {
696 struct acx_header header;
697
698 u8 wake_up_event; /* Only one bit can be set */
699 u8 listen_interval;
700 u8 pad[2];
701} __attribute__ ((packed));
702
703struct acx_aid {
704 struct acx_header header;
705
706 /*
707 * To be set when associated with an AP.
708 */
709 u16 aid;
710 u8 pad[2];
711} __attribute__ ((packed));
712
713enum acx_preamble_type {
714 ACX_PREAMBLE_LONG = 0,
715 ACX_PREAMBLE_SHORT = 1
716};
717
718struct acx_preamble {
719 struct acx_header header;
720
721 /*
722 * When set, the WiLink transmits the frames with a short preamble and
723 * when cleared, the WiLink transmits the frames with a long preamble.
724 */
725 u8 preamble;
726 u8 padding[3];
727} __attribute__ ((packed));
728
729enum acx_ctsprotect_type {
730 CTSPROTECT_DISABLE = 0,
731 CTSPROTECT_ENABLE = 1
732};
733
734struct acx_ctsprotect {
735 struct acx_header header;
736 u8 ctsprotect;
737 u8 padding[3];
738} __attribute__ ((packed));
739
740struct acx_tx_statistics {
741 u32 internal_desc_overflow;
742} __attribute__ ((packed));
743
744struct acx_rx_statistics {
745 u32 out_of_mem;
746 u32 hdr_overflow;
747 u32 hw_stuck;
748 u32 dropped;
749 u32 fcs_err;
750 u32 xfr_hint_trig;
751 u32 path_reset;
752 u32 reset_counter;
753} __attribute__ ((packed));
754
755struct acx_dma_statistics {
756 u32 rx_requested;
757 u32 rx_errors;
758 u32 tx_requested;
759 u32 tx_errors;
760} __attribute__ ((packed));
761
762struct acx_isr_statistics {
763 /* host command complete */
764 u32 cmd_cmplt;
765
766 /* fiqisr() */
767 u32 fiqs;
768
769 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
770 u32 rx_headers;
771
772 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
773 u32 rx_completes;
774
775 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
776 u32 rx_mem_overflow;
777
778 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
779 u32 rx_rdys;
780
781 /* irqisr() */
782 u32 irqs;
783
784 /* (INT_STS_ND & INT_TRIG_TX_PROC) */
785 u32 tx_procs;
786
787 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
788 u32 decrypt_done;
789
790 /* (INT_STS_ND & INT_TRIG_DMA0) */
791 u32 dma0_done;
792
793 /* (INT_STS_ND & INT_TRIG_DMA1) */
794 u32 dma1_done;
795
796 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
797 u32 tx_exch_complete;
798
799 /* (INT_STS_ND & INT_TRIG_COMMAND) */
800 u32 commands;
801
802 /* (INT_STS_ND & INT_TRIG_RX_PROC) */
803 u32 rx_procs;
804
805 /* (INT_STS_ND & INT_TRIG_PM_802) */
806 u32 hw_pm_mode_changes;
807
808 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
809 u32 host_acknowledges;
810
811 /* (INT_STS_ND & INT_TRIG_PM_PCI) */
812 u32 pci_pm;
813
814 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
815 u32 wakeups;
816
817 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
818 u32 low_rssi;
819} __attribute__ ((packed));
820
821struct acx_wep_statistics {
822 /* WEP address keys configured */
823 u32 addr_key_count;
824
825 /* default keys configured */
826 u32 default_key_count;
827
828 u32 reserved;
829
830 /* number of times that WEP key not found on lookup */
831 u32 key_not_found;
832
833 /* number of times that WEP key decryption failed */
834 u32 decrypt_fail;
835
836 /* WEP packets decrypted */
837 u32 packets;
838
839 /* WEP decrypt interrupts */
840 u32 interrupt;
841} __attribute__ ((packed));
842
843#define ACX_MISSED_BEACONS_SPREAD 10
844
845struct acx_pwr_statistics {
846 /* the amount of enters into power save mode (both PD & ELP) */
847 u32 ps_enter;
848
849 /* the amount of enters into ELP mode */
850 u32 elp_enter;
851
852 /* the amount of missing beacon interrupts to the host */
853 u32 missing_bcns;
854
855 /* the amount of wake on host-access times */
856 u32 wake_on_host;
857
858 /* the amount of wake on timer-expire */
859 u32 wake_on_timer_exp;
860
861 /* the number of packets that were transmitted with PS bit set */
862 u32 tx_with_ps;
863
864 /* the number of packets that were transmitted with PS bit clear */
865 u32 tx_without_ps;
866
867 /* the number of received beacons */
868 u32 rcvd_beacons;
869
870 /* the number of entering into PowerOn (power save off) */
871 u32 power_save_off;
872
873 /* the number of entries into power save mode */
874 u16 enable_ps;
875
876 /*
877 * the number of exits from power save, not including failed PS
878 * transitions
879 */
880 u16 disable_ps;
881
882 /*
883 * the number of times the TSF counter was adjusted because
884 * of drift
885 */
886 u32 fix_tsf_ps;
887
888 /* Gives statistics about the spread continuous missed beacons.
889 * The 16 LSB are dedicated for the PS mode.
890 * The 16 MSB are dedicated for the PS mode.
891 * cont_miss_bcns_spread[0] - single missed beacon.
892 * cont_miss_bcns_spread[1] - two continuous missed beacons.
893 * cont_miss_bcns_spread[2] - three continuous missed beacons.
894 * ...
895 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
896 */
897 u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
898
899 /* the number of beacons in awake mode */
900 u32 rcvd_awake_beacons;
901} __attribute__ ((packed));
902
903struct acx_mic_statistics {
904 u32 rx_pkts;
905 u32 calc_failure;
906} __attribute__ ((packed));
907
908struct acx_aes_statistics {
909 u32 encrypt_fail;
910 u32 decrypt_fail;
911 u32 encrypt_packets;
912 u32 decrypt_packets;
913 u32 encrypt_interrupt;
914 u32 decrypt_interrupt;
915} __attribute__ ((packed));
916
917struct acx_event_statistics {
918 u32 heart_beat;
919 u32 calibration;
920 u32 rx_mismatch;
921 u32 rx_mem_empty;
922 u32 rx_pool;
923 u32 oom_late;
924 u32 phy_transmit_error;
925 u32 tx_stuck;
926} __attribute__ ((packed));
927
928struct acx_ps_statistics {
929 u32 pspoll_timeouts;
930 u32 upsd_timeouts;
931 u32 upsd_max_sptime;
932 u32 upsd_max_apturn;
933 u32 pspoll_max_apturn;
934 u32 pspoll_utilization;
935 u32 upsd_utilization;
936} __attribute__ ((packed));
937
938struct acx_rxpipe_statistics {
939 u32 rx_prep_beacon_drop;
940 u32 descr_host_int_trig_rx_data;
941 u32 beacon_buffer_thres_host_int_trig_rx_data;
942 u32 missed_beacon_host_int_trig_rx_data;
943 u32 tx_xfr_host_int_trig_rx_data;
944} __attribute__ ((packed));
945
946struct acx_statistics {
947 struct acx_header header;
948
949 struct acx_tx_statistics tx;
950 struct acx_rx_statistics rx;
951 struct acx_dma_statistics dma;
952 struct acx_isr_statistics isr;
953 struct acx_wep_statistics wep;
954 struct acx_pwr_statistics pwr;
955 struct acx_aes_statistics aes;
956 struct acx_mic_statistics mic;
957 struct acx_event_statistics event;
958 struct acx_ps_statistics ps;
959 struct acx_rxpipe_statistics rxpipe;
960} __attribute__ ((packed));
961
962#define ACX_MAX_RATE_CLASSES 8
963#define ACX_RATE_MASK_UNSPECIFIED 0
964#define ACX_RATE_MASK_ALL 0x1eff
965#define ACX_RATE_RETRY_LIMIT 10
966
967struct acx_rate_class {
968 u32 enabled_rates;
969 u8 short_retry_limit;
970 u8 long_retry_limit;
971 u8 aflags;
972 u8 reserved;
973};
974
975struct acx_rate_policy {
976 struct acx_header header;
977
978 u32 rate_class_cnt;
979 struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES];
980} __attribute__ ((packed));
981
982#define WL1271_ACX_AC_COUNT 4
983
984struct acx_ac_cfg {
985 struct acx_header header;
986 u8 ac;
987 u8 cw_min;
988 u16 cw_max;
989 u8 aifsn;
990 u8 reserved;
991 u16 tx_op_limit;
992} __attribute__ ((packed));
993
994enum wl1271_acx_ac {
995 WL1271_ACX_AC_BE = 0,
996 WL1271_ACX_AC_BK = 1,
997 WL1271_ACX_AC_VI = 2,
998 WL1271_ACX_AC_VO = 3,
999 WL1271_ACX_AC_CTS2SELF = 4,
1000 WL1271_ACX_AC_ANY_TID = 0x1F,
1001 WL1271_ACX_AC_INVALID = 0xFF,
1002};
1003
1004enum wl1271_acx_ps_scheme {
1005 WL1271_ACX_PS_SCHEME_LEGACY = 0,
1006 WL1271_ACX_PS_SCHEME_UPSD_TRIGGER = 1,
1007 WL1271_ACX_PS_SCHEME_LEGACY_PSPOLL = 2,
1008 WL1271_ACX_PS_SCHEME_SAPSD = 3,
1009};
1010
1011enum wl1271_acx_ack_policy {
1012 WL1271_ACX_ACK_POLICY_LEGACY = 0,
1013 WL1271_ACX_ACK_POLICY_NO_ACK = 1,
1014 WL1271_ACX_ACK_POLICY_BLOCK = 2,
1015};
1016
1017#define WL1271_ACX_TID_COUNT 7
1018
1019struct acx_tid_config {
1020 struct acx_header header;
1021 u8 queue_id;
1022 u8 channel_type;
1023 u8 tsid;
1024 u8 ps_scheme;
1025 u8 ack_policy;
1026 u8 padding[3];
1027 u32 apsd_conf[2];
1028} __attribute__ ((packed));
1029
1030struct acx_frag_threshold {
1031 struct acx_header header;
1032 u16 frag_threshold;
1033 u8 padding[2];
1034} __attribute__ ((packed));
1035
1036#define WL1271_ACX_TX_COMPL_TIMEOUT 5
1037#define WL1271_ACX_TX_COMPL_THRESHOLD 5
1038
1039struct acx_tx_config_options {
1040 struct acx_header header;
1041 u16 tx_compl_timeout; /* msec */
1042 u16 tx_compl_threshold; /* number of packets */
1043} __attribute__ ((packed));
1044
1045#define ACX_RX_MEM_BLOCKS 64
1046#define ACX_TX_MIN_MEM_BLOCKS 64
1047#define ACX_TX_DESCRIPTORS 32
1048#define ACX_NUM_SSID_PROFILES 1
1049
1050struct wl1271_acx_config_memory {
1051 struct acx_header header;
1052
1053 u8 rx_mem_block_num;
1054 u8 tx_min_mem_block_num;
1055 u8 num_stations;
1056 u8 num_ssid_profiles;
1057 u32 total_tx_descriptors;
1058} __attribute__ ((packed));
1059
1060struct wl1271_acx_mem_map {
1061 struct acx_header header;
1062
1063 void *code_start;
1064 void *code_end;
1065
1066 void *wep_defkey_start;
1067 void *wep_defkey_end;
1068
1069 void *sta_table_start;
1070 void *sta_table_end;
1071
1072 void *packet_template_start;
1073 void *packet_template_end;
1074
1075 /* Address of the TX result interface (control block) */
1076 u32 tx_result;
1077 u32 tx_result_queue_start;
1078
1079 void *queue_memory_start;
1080 void *queue_memory_end;
1081
1082 u32 packet_memory_pool_start;
1083 u32 packet_memory_pool_end;
1084
1085 void *debug_buffer1_start;
1086 void *debug_buffer1_end;
1087
1088 void *debug_buffer2_start;
1089 void *debug_buffer2_end;
1090
1091 /* Number of blocks FW allocated for TX packets */
1092 u32 num_tx_mem_blocks;
1093
1094 /* Number of blocks FW allocated for RX packets */
1095 u32 num_rx_mem_blocks;
1096
1097 /* the following 4 fields are valid in SLAVE mode only */
1098 u8 *tx_cbuf;
1099 u8 *rx_cbuf;
1100 void *rx_ctrl;
1101 void *tx_ctrl;
1102} __attribute__ ((packed));
1103
1104enum wl1271_acx_rx_queue_type {
1105 RX_QUEUE_TYPE_RX_LOW_PRIORITY, /* All except the high priority */
1106 RX_QUEUE_TYPE_RX_HIGH_PRIORITY, /* Management and voice packets */
1107 RX_QUEUE_TYPE_NUM,
1108 RX_QUEUE_TYPE_MAX = USHORT_MAX
1109};
1110
1111#define WL1271_RX_INTR_THRESHOLD_DEF 0 /* no pacing, send interrupt on
1112 * every event */
1113#define WL1271_RX_INTR_THRESHOLD_MIN 0
1114#define WL1271_RX_INTR_THRESHOLD_MAX 15
1115
1116#define WL1271_RX_INTR_TIMEOUT_DEF 5
1117#define WL1271_RX_INTR_TIMEOUT_MIN 1
1118#define WL1271_RX_INTR_TIMEOUT_MAX 100
1119
1120struct wl1271_acx_rx_config_opt {
1121 struct acx_header header;
1122
1123 u16 mblk_threshold;
1124 u16 threshold;
1125 u16 timeout;
1126 u8 queue_type;
1127 u8 reserved;
1128} __attribute__ ((packed));
1129
1130enum {
1131 ACX_WAKE_UP_CONDITIONS = 0x0002,
1132 ACX_MEM_CFG = 0x0003,
1133 ACX_SLOT = 0x0004,
1134 ACX_AC_CFG = 0x0007,
1135 ACX_MEM_MAP = 0x0008,
1136 ACX_AID = 0x000A,
1137 /* ACX_FW_REV is missing in the ref driver, but seems to work */
1138 ACX_FW_REV = 0x000D,
1139 ACX_MEDIUM_USAGE = 0x000F,
1140 ACX_RX_CFG = 0x0010,
1141 ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */
1142 ACX_STATISTICS = 0x0013, /* Debug API */
1143 ACX_PWR_CONSUMPTION_STATISTICS = 0x0014,
1144 ACX_FEATURE_CFG = 0x0015,
1145 ACX_TID_CFG = 0x001A,
1146 ACX_PS_RX_STREAMING = 0x001B,
1147 ACX_BEACON_FILTER_OPT = 0x001F,
1148 ACX_NOISE_HIST = 0x0021,
1149 ACX_HDK_VERSION = 0x0022, /* ??? */
1150 ACX_PD_THRESHOLD = 0x0023,
1151 ACX_TX_CONFIG_OPT = 0x0024,
1152 ACX_CCA_THRESHOLD = 0x0025,
1153 ACX_EVENT_MBOX_MASK = 0x0026,
1154 ACX_CONN_MONIT_PARAMS = 0x002D,
1155 ACX_CONS_TX_FAILURE = 0x002F,
1156 ACX_BCN_DTIM_OPTIONS = 0x0031,
1157 ACX_SG_ENABLE = 0x0032,
1158 ACX_SG_CFG = 0x0033,
1159 ACX_BEACON_FILTER_TABLE = 0x0038,
1160 ACX_ARP_IP_FILTER = 0x0039,
1161 ACX_ROAMING_STATISTICS_TBL = 0x003B,
1162 ACX_RATE_POLICY = 0x003D,
1163 ACX_CTS_PROTECTION = 0x003E,
1164 ACX_SLEEP_AUTH = 0x003F,
1165 ACX_PREAMBLE_TYPE = 0x0040,
1166 ACX_ERROR_CNT = 0x0041,
1167 ACX_IBSS_FILTER = 0x0044,
1168 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045,
1169 ACX_TSF_INFO = 0x0046,
1170 ACX_CONFIG_PS_WMM = 0x0049,
1171 ACX_ENABLE_RX_DATA_FILTER = 0x004A,
1172 ACX_SET_RX_DATA_FILTER = 0x004B,
1173 ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1174 ACX_RX_CONFIG_OPT = 0x004E,
1175 ACX_FRAG_CFG = 0x004F,
1176 ACX_BET_ENABLE = 0x0050,
1177 ACX_RSSI_SNR_TRIGGER = 0x0051,
1178 ACX_RSSI_SNR_WEIGHTS = 0x0051,
1179 ACX_KEEP_ALIVE_MODE = 0x0052,
1180 ACX_SET_KEEP_ALIVE_CONFIG = 0x0054,
1181 ACX_BA_SESSION_RESPONDER_POLICY = 0x0055,
1182 ACX_BA_SESSION_INITIATOR_POLICY = 0x0056,
1183 ACX_PEER_HT_CAP = 0x0057,
1184 ACX_HT_BSS_OPERATION = 0x0058,
1185 ACX_COEX_ACTIVITY = 0x0059,
1186 DOT11_RX_MSDU_LIFE_TIME = 0x1004,
1187 DOT11_CUR_TX_PWR = 0x100D,
1188 DOT11_RX_DOT11_MODE = 0x1012,
1189 DOT11_RTS_THRESHOLD = 0x1013,
1190 DOT11_GROUP_ADDRESS_TBL = 0x1014,
1191
1192 MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
1193
1194 MAX_IE = 0xFFFF
1195};
1196
1197
1198int wl1271_acx_wake_up_conditions(struct wl1271 *wl, u8 wake_up_event,
1199 u8 listen_interval);
1200int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1201int wl1271_acx_fw_version(struct wl1271 *wl, char *buf, size_t len);
1202int wl1271_acx_tx_power(struct wl1271 *wl, int power);
1203int wl1271_acx_feature_cfg(struct wl1271 *wl);
1204int wl1271_acx_mem_map(struct wl1271 *wl,
1205 struct acx_header *mem_map, size_t len);
1206int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl, u32 life_time);
1207int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter);
1208int wl1271_acx_pd_threshold(struct wl1271 *wl);
1209int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time);
c87dec9f
JO		 1210int wl1271_acx_group_address_tbl(struct wl1271 *wl, bool enable,
1211 void *mc_list, u32 mc_list_len);
f5fc0f86
LC		 1212int wl1271_acx_service_period_timeout(struct wl1271 *wl);
1213int wl1271_acx_rts_threshold(struct wl1271 *wl, u16 rts_threshold);
1922167b 1214int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, bool enable_filter);
f5fc0f86 1215int wl1271_acx_beacon_filter_table(struct wl1271 *wl);
34415236 1216int wl1271_acx_conn_monit_params(struct wl1271 *wl);
f5fc0f86
LC		 1217int wl1271_acx_sg_enable(struct wl1271 *wl);
1218int wl1271_acx_sg_cfg(struct wl1271 *wl);
1219int wl1271_acx_cca_threshold(struct wl1271 *wl);
1220int wl1271_acx_bcn_dtim_options(struct wl1271 *wl);
1221int wl1271_acx_aid(struct wl1271 *wl, u16 aid);
1222int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1223int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble);
1224int wl1271_acx_cts_protect(struct wl1271 *wl,
1225 enum acx_ctsprotect_type ctsprotect);
1226int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
8a5a37a6 1227int wl1271_acx_rate_policies(struct wl1271 *wl, u32 enabled_rates);
f5fc0f86
LC		 1228int wl1271_acx_ac_cfg(struct wl1271 *wl);
1229int wl1271_acx_tid_cfg(struct wl1271 *wl);
1230int wl1271_acx_frag_threshold(struct wl1271 *wl);
1231int wl1271_acx_tx_config_options(struct wl1271 *wl);
1232int wl1271_acx_mem_cfg(struct wl1271 *wl);
1233int wl1271_acx_init_mem_config(struct wl1271 *wl);
1234int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1235
1236#endif /* __WL1271_ACX_H__ */
Linux 6.x block layer and io_uring tree(s)