[linux-2.6-block.git] / drivers / net / wireless / wl12xx / spi.c

/*
 * This file is part of wl1271
 *
 * Copyright (C) 2008-2009 Nokia Corporation
 *
 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/irq.h>
#include <linux/module.h>
#include <linux/crc7.h>
#include <linux/spi/spi.h>
#include <linux/wl12xx.h>
#include <linux/slab.h>

#include "wl12xx.h"
#include "wl12xx_80211.h"
#include "io.h"

#include "reg.h"

#define WSPI_CMD_READ                 0x40000000
#define WSPI_CMD_WRITE                0x00000000
#define WSPI_CMD_FIXED                0x20000000
#define WSPI_CMD_BYTE_LENGTH          0x1FFE0000
#define WSPI_CMD_BYTE_LENGTH_OFFSET   17
#define WSPI_CMD_BYTE_ADDR            0x0001FFFF

#define WSPI_INIT_CMD_CRC_LEN       5

#define WSPI_INIT_CMD_START         0x00
#define WSPI_INIT_CMD_TX            0x40
/* the extra bypass bit is sampled by the TNET as '1' */
#define WSPI_INIT_CMD_BYPASS_BIT    0x80
#define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
#define WSPI_INIT_CMD_EN_FIXEDBUSY  0x80
#define WSPI_INIT_CMD_DIS_FIXEDBUSY 0x00
#define WSPI_INIT_CMD_IOD           0x40
#define WSPI_INIT_CMD_IP            0x20
#define WSPI_INIT_CMD_CS            0x10
#define WSPI_INIT_CMD_WS            0x08
#define WSPI_INIT_CMD_WSPI          0x01
#define WSPI_INIT_CMD_END           0x01

#define WSPI_INIT_CMD_LEN           8

#define HW_ACCESS_WSPI_FIXED_BUSY_LEN \
		((WL1271_BUSY_WORD_LEN - 4) / sizeof(u32))
#define HW_ACCESS_WSPI_INIT_CMD_MASK  0

/* HW limitation: maximum possible chunk size is 4095 bytes */
#define WSPI_MAX_CHUNK_SIZE    4092

#define WSPI_MAX_NUM_OF_CHUNKS (WL1271_AGGR_BUFFER_SIZE / WSPI_MAX_CHUNK_SIZE)

static inline struct spi_device *wl_to_spi(struct wl1271 *wl)
{
	return wl->if_priv;
}

static struct device *wl1271_spi_wl_to_dev(struct wl1271 *wl)
{
	return &(wl_to_spi(wl)->dev);
}

static void wl1271_spi_disable_interrupts(struct wl1271 *wl)
{
	disable_irq(wl->irq);
}

static void wl1271_spi_enable_interrupts(struct wl1271 *wl)
{
	enable_irq(wl->irq);
}

static void wl1271_spi_reset(struct wl1271 *wl)
{
	u8 *cmd;
	struct spi_transfer t;
	struct spi_message m;

	cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
	if (!cmd) {
		wl1271_error("could not allocate cmd for spi reset");
		return;
	}

	memset(&t, 0, sizeof(t));
	spi_message_init(&m);

	memset(cmd, 0xff, WSPI_INIT_CMD_LEN);

	t.tx_buf = cmd;
	t.len = WSPI_INIT_CMD_LEN;
	spi_message_add_tail(&t, &m);

	spi_sync(wl_to_spi(wl), &m);

	wl1271_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
	kfree(cmd);
}

static void wl1271_spi_init(struct wl1271 *wl)
{
	u8 crc[WSPI_INIT_CMD_CRC_LEN], *cmd;
	struct spi_transfer t;
	struct spi_message m;

	cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
	if (!cmd) {
		wl1271_error("could not allocate cmd for spi init");
		return;
	}

	memset(crc, 0, sizeof(crc));
	memset(&t, 0, sizeof(t));
	spi_message_init(&m);

	/*
	 * Set WSPI_INIT_COMMAND
	 * the data is being send from the MSB to LSB
	 */
	cmd[2] = 0xff;
	cmd[3] = 0xff;
	cmd[1] = WSPI_INIT_CMD_START | WSPI_INIT_CMD_TX;
	cmd[0] = 0;
	cmd[7] = 0;
	cmd[6] |= HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
	cmd[6] |= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;

	if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
		cmd[5] |=  WSPI_INIT_CMD_DIS_FIXEDBUSY;
	else
		cmd[5] |= WSPI_INIT_CMD_EN_FIXEDBUSY;

	cmd[5] |= WSPI_INIT_CMD_IOD | WSPI_INIT_CMD_IP | WSPI_INIT_CMD_CS
		| WSPI_INIT_CMD_WSPI | WSPI_INIT_CMD_WS;

	crc[0] = cmd[1];
	crc[1] = cmd[0];
	crc[2] = cmd[7];
	crc[3] = cmd[6];
	crc[4] = cmd[5];

	cmd[4] |= crc7(0, crc, WSPI_INIT_CMD_CRC_LEN) << 1;
	cmd[4] |= WSPI_INIT_CMD_END;

	t.tx_buf = cmd;
	t.len = WSPI_INIT_CMD_LEN;
	spi_message_add_tail(&t, &m);

	spi_sync(wl_to_spi(wl), &m);
	wl1271_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
	kfree(cmd);
}

#define WL1271_BUSY_WORD_TIMEOUT 1000

static int wl1271_spi_read_busy(struct wl1271 *wl)
{
	struct spi_transfer t[1];
	struct spi_message m;
	u32 *busy_buf;
	int num_busy_bytes = 0;

	/*
	 * Read further busy words from SPI until a non-busy word is
	 * encountered, then read the data itself into the buffer.
	 */

	num_busy_bytes = WL1271_BUSY_WORD_TIMEOUT;
	busy_buf = wl->buffer_busyword;
	while (num_busy_bytes) {
		num_busy_bytes--;
		spi_message_init(&m);
		memset(t, 0, sizeof(t));
		t[0].rx_buf = busy_buf;
		t[0].len = sizeof(u32);
		t[0].cs_change = true;
		spi_message_add_tail(&t[0], &m);
		spi_sync(wl_to_spi(wl), &m);

		if (*busy_buf & 0x1)
			return 0;
	}

	/* The SPI bus is unresponsive, the read failed. */
	wl1271_error("SPI read busy-word timeout!\n");
	return -ETIMEDOUT;
}

static void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf,
				size_t len, bool fixed)
{
	struct spi_transfer t[2];
	struct spi_message m;
	u32 *busy_buf;
	u32 *cmd;
	u32 chunk_len;

	while (len > 0) {
		chunk_len = min((size_t)WSPI_MAX_CHUNK_SIZE, len);

		cmd = &wl->buffer_cmd;
		busy_buf = wl->buffer_busyword;

		*cmd = 0;
		*cmd |= WSPI_CMD_READ;
		*cmd |= (chunk_len << WSPI_CMD_BYTE_LENGTH_OFFSET) &
			WSPI_CMD_BYTE_LENGTH;
		*cmd |= addr & WSPI_CMD_BYTE_ADDR;

		if (fixed)
			*cmd |= WSPI_CMD_FIXED;

		spi_message_init(&m);
		memset(t, 0, sizeof(t));

		t[0].tx_buf = cmd;
		t[0].len = 4;
		t[0].cs_change = true;
		spi_message_add_tail(&t[0], &m);

		/* Busy and non busy words read */
		t[1].rx_buf = busy_buf;
		t[1].len = WL1271_BUSY_WORD_LEN;
		t[1].cs_change = true;
		spi_message_add_tail(&t[1], &m);

		spi_sync(wl_to_spi(wl), &m);

		if (!(busy_buf[WL1271_BUSY_WORD_CNT - 1] & 0x1) &&
		    wl1271_spi_read_busy(wl)) {
			memset(buf, 0, chunk_len);
			return;
		}

		spi_message_init(&m);
		memset(t, 0, sizeof(t));

		t[0].rx_buf = buf;
		t[0].len = chunk_len;
		t[0].cs_change = true;
		spi_message_add_tail(&t[0], &m);

		spi_sync(wl_to_spi(wl), &m);

		wl1271_dump(DEBUG_SPI, "spi_read cmd -> ", cmd, sizeof(*cmd));
		wl1271_dump(DEBUG_SPI, "spi_read buf <- ", buf, chunk_len);

		if (!fixed)
			addr += chunk_len;
		buf += chunk_len;
		len -= chunk_len;
	}
}

static void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf,
			  size_t len, bool fixed)
{
	struct spi_transfer t[2 * WSPI_MAX_NUM_OF_CHUNKS];
	struct spi_message m;
	u32 commands[WSPI_MAX_NUM_OF_CHUNKS];
	u32 *cmd;
	u32 chunk_len;
	int i;

	WARN_ON(len > WL1271_AGGR_BUFFER_SIZE);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	cmd = &commands[0];
	i = 0;
	while (len > 0) {
		chunk_len = min((size_t)WSPI_MAX_CHUNK_SIZE, len);

		*cmd = 0;
		*cmd |= WSPI_CMD_WRITE;
		*cmd |= (chunk_len << WSPI_CMD_BYTE_LENGTH_OFFSET) &
			WSPI_CMD_BYTE_LENGTH;
		*cmd |= addr & WSPI_CMD_BYTE_ADDR;

		if (fixed)
			*cmd |= WSPI_CMD_FIXED;

		t[i].tx_buf = cmd;
		t[i].len = sizeof(*cmd);
		spi_message_add_tail(&t[i++], &m);

		t[i].tx_buf = buf;
		t[i].len = chunk_len;
		spi_message_add_tail(&t[i++], &m);

		wl1271_dump(DEBUG_SPI, "spi_write cmd -> ", cmd, sizeof(*cmd));
		wl1271_dump(DEBUG_SPI, "spi_write buf -> ", buf, chunk_len);

		if (!fixed)
			addr += chunk_len;
		buf += chunk_len;
		len -= chunk_len;
		cmd++;
	}

	spi_sync(wl_to_spi(wl), &m);
}

static irqreturn_t wl1271_hardirq(int irq, void *cookie)
{
	struct wl1271 *wl = cookie;
	unsigned long flags;

	wl1271_debug(DEBUG_IRQ, "IRQ");

	/* complete the ELP completion */
	spin_lock_irqsave(&wl->wl_lock, flags);
	set_bit(WL1271_FLAG_IRQ_RUNNING, &wl->flags);
	if (wl->elp_compl) {
		complete(wl->elp_compl);
		wl->elp_compl = NULL;
	}
	spin_unlock_irqrestore(&wl->wl_lock, flags);

	return IRQ_WAKE_THREAD;
}

static int wl1271_spi_set_power(struct wl1271 *wl, bool enable)
{
	if (wl->set_power)
		wl->set_power(enable);

	return 0;
}

static struct wl1271_if_operations spi_ops = {
	.read		= wl1271_spi_raw_read,
	.write		= wl1271_spi_raw_write,
	.reset		= wl1271_spi_reset,
	.init		= wl1271_spi_init,
	.power		= wl1271_spi_set_power,
	.dev		= wl1271_spi_wl_to_dev,
	.enable_irq	= wl1271_spi_enable_interrupts,
	.disable_irq	= wl1271_spi_disable_interrupts,
	.set_block_size = NULL,
};

static int __devinit wl1271_probe(struct spi_device *spi)
{
	struct wl12xx_platform_data *pdata;
	struct ieee80211_hw *hw;
	struct wl1271 *wl;
	unsigned long irqflags;
	int ret;

	pdata = spi->dev.platform_data;
	if (!pdata) {
		wl1271_error("no platform data");
		return -ENODEV;
	}

	hw = wl1271_alloc_hw();
	if (IS_ERR(hw))
		return PTR_ERR(hw);

	wl = hw->priv;

	dev_set_drvdata(&spi->dev, wl);
	wl->if_priv = spi;

	wl->if_ops = &spi_ops;

	/* This is the only SPI value that we need to set here, the rest
	 * comes from the board-peripherals file */
	spi->bits_per_word = 32;

	ret = spi_setup(spi);
	if (ret < 0) {
		wl1271_error("spi_setup failed");
		goto out_free;
	}

	wl->set_power = pdata->set_power;
	if (!wl->set_power) {
		wl1271_error("set power function missing in platform data");
		ret = -ENODEV;
		goto out_free;
	}

	wl->ref_clock = pdata->board_ref_clock;
	wl->tcxo_clock = pdata->board_tcxo_clock;
	wl->platform_quirks = pdata->platform_quirks;

	if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ)
		irqflags = IRQF_TRIGGER_RISING;
	else
		irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;

	wl->irq = spi->irq;
	if (wl->irq < 0) {
		wl1271_error("irq missing in platform data");
		ret = -ENODEV;
		goto out_free;
	}

	ret = request_threaded_irq(wl->irq, wl1271_hardirq, wl1271_irq,
				   irqflags,
				   DRIVER_NAME, wl);
	if (ret < 0) {
		wl1271_error("request_irq() failed: %d", ret);
		goto out_free;
	}

	disable_irq(wl->irq);

	ret = wl1271_init_ieee80211(wl);
	if (ret)
		goto out_irq;

	ret = wl1271_register_hw(wl);
	if (ret)
		goto out_irq;

	wl1271_notice("initialized");

	return 0;

 out_irq:
	free_irq(wl->irq, wl);

 out_free:
	wl1271_free_hw(wl);

	return ret;
}

static int __devexit wl1271_remove(struct spi_device *spi)
{
	struct wl1271 *wl = dev_get_drvdata(&spi->dev);

	wl1271_unregister_hw(wl);
	free_irq(wl->irq, wl);
	wl1271_free_hw(wl);

	return 0;
}


static struct spi_driver wl1271_spi_driver = {
	.driver = {
		.name		= "wl1271_spi",
		.bus		= &spi_bus_type,
		.owner		= THIS_MODULE,
	},

	.probe		= wl1271_probe,
	.remove		= __devexit_p(wl1271_remove),
};

static int __init wl1271_init(void)
{
	int ret;

	ret = spi_register_driver(&wl1271_spi_driver);
	if (ret < 0) {
		wl1271_error("failed to register spi driver: %d", ret);
		goto out;
	}

out:
	return ret;
}

static void __exit wl1271_exit(void)
{
	spi_unregister_driver(&wl1271_spi_driver);

	wl1271_notice("unloaded");
}

module_init(wl1271_init);
module_exit(wl1271_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
MODULE_AUTHOR("Juuso Oikarinen <juuso.oikarinen@nokia.com>");
MODULE_FIRMWARE(WL1271_FW_NAME);
MODULE_FIRMWARE(WL128X_FW_NAME);
MODULE_FIRMWARE(WL127X_AP_FW_NAME);
MODULE_FIRMWARE(WL128X_AP_FW_NAME);
MODULE_ALIAS("spi:wl1271");
Commit	Line	Data
f5fc0f86 LC	1	/*
	2	* This file is part of wl1271
	3	*
	4	* Copyright (C) 2008-2009 Nokia Corporation
	5	*
	6	* Contact: Luciano Coelho <luciano.coelho@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
2d5e82b8	24	#include <linux/irq.h>
f5fc0f86	25	#include <linux/module.h>
f5fc0f86 LC	26	#include <linux/crc7.h>
f5fc0f86 LC	27	#include <linux/spi/spi.h>
c1f9a095	28	#include <linux/wl12xx.h>
5a0e3ad6	29	#include <linux/slab.h>
f5fc0f86	30
00d20100	31	#include "wl12xx.h"
f5fc0f86	32	#include "wl12xx_80211.h"
00d20100	33	#include "io.h"
f5fc0f86	34
00d20100	35	#include "reg.h"
760d969f TP	36
	37	#define WSPI_CMD_READ 0x40000000
	38	#define WSPI_CMD_WRITE 0x00000000
	39	#define WSPI_CMD_FIXED 0x20000000
	40	#define WSPI_CMD_BYTE_LENGTH 0x1FFE0000
	41	#define WSPI_CMD_BYTE_LENGTH_OFFSET 17
	42	#define WSPI_CMD_BYTE_ADDR 0x0001FFFF
	43
	44	#define WSPI_INIT_CMD_CRC_LEN 5
	45
	46	#define WSPI_INIT_CMD_START 0x00
	47	#define WSPI_INIT_CMD_TX 0x40
	48	/* the extra bypass bit is sampled by the TNET as '1' */
	49	#define WSPI_INIT_CMD_BYPASS_BIT 0x80
	50	#define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
	51	#define WSPI_INIT_CMD_EN_FIXEDBUSY 0x80
	52	#define WSPI_INIT_CMD_DIS_FIXEDBUSY 0x00
	53	#define WSPI_INIT_CMD_IOD 0x40
	54	#define WSPI_INIT_CMD_IP 0x20
	55	#define WSPI_INIT_CMD_CS 0x10
	56	#define WSPI_INIT_CMD_WS 0x08
	57	#define WSPI_INIT_CMD_WSPI 0x01
	58	#define WSPI_INIT_CMD_END 0x01
	59
	60	#define WSPI_INIT_CMD_LEN 8
	61
	62	#define HW_ACCESS_WSPI_FIXED_BUSY_LEN \
	63	((WL1271_BUSY_WORD_LEN - 4) / sizeof(u32))
	64	#define HW_ACCESS_WSPI_INIT_CMD_MASK 0
	65
5c57a901 IY	66	/* HW limitation: maximum possible chunk size is 4095 bytes */
	67	#define WSPI_MAX_CHUNK_SIZE 4092
	68
	69	#define WSPI_MAX_NUM_OF_CHUNKS (WL1271_AGGR_BUFFER_SIZE / WSPI_MAX_CHUNK_SIZE)
	70
b42f91ba	71	static inline struct spi_device wl_to_spi(struct wl1271 wl)
8197b711 TP	72	{
	73	return wl->if_priv;
	74	}
	75
	76	static struct device wl1271_spi_wl_to_dev(struct wl1271 wl)
	77	{
	78	return &(wl_to_spi(wl)->dev);
	79	}
f5fc0f86	80
760d969f	81	static void wl1271_spi_disable_interrupts(struct wl1271 *wl)
54f7e503 TP	82	{
	83	disable_irq(wl->irq);
	84	}
	85
760d969f	86	static void wl1271_spi_enable_interrupts(struct wl1271 *wl)
54f7e503 TP	87	{
	88	enable_irq(wl->irq);
	89	}
	90
760d969f	91	static void wl1271_spi_reset(struct wl1271 *wl)
f5fc0f86 LC	92	{
	93	u8 *cmd;
	94	struct spi_transfer t;
	95	struct spi_message m;
	96
	97	cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
	98	if (!cmd) {
	99	wl1271_error("could not allocate cmd for spi reset");
	100	return;
	101	}
	102
	103	memset(&t, 0, sizeof(t));
	104	spi_message_init(&m);
	105
	106	memset(cmd, 0xff, WSPI_INIT_CMD_LEN);
	107
	108	t.tx_buf = cmd;
	109	t.len = WSPI_INIT_CMD_LEN;
	110	spi_message_add_tail(&t, &m);
	111
8197b711	112	spi_sync(wl_to_spi(wl), &m);
f5fc0f86 LC	113
f5fc0f86 LC	114	wl1271_dump(DEBUG_SPI, "spi reset -> ", cmd, WSPI_INIT_CMD_LEN);
0dd38667	115	kfree(cmd);
f5fc0f86 LC	116	}
f5fc0f86 LC	117
760d969f	118	static void wl1271_spi_init(struct wl1271 *wl)
f5fc0f86 LC	119	{
	120	u8 crc[WSPI_INIT_CMD_CRC_LEN], *cmd;
	121	struct spi_transfer t;
	122	struct spi_message m;
	123
	124	cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
	125	if (!cmd) {
	126	wl1271_error("could not allocate cmd for spi init");
	127	return;
	128	}
	129
	130	memset(crc, 0, sizeof(crc));
	131	memset(&t, 0, sizeof(t));
	132	spi_message_init(&m);
	133
	134	/*
	135	* Set WSPI_INIT_COMMAND
	136	* the data is being send from the MSB to LSB
	137	*/
	138	cmd[2] = 0xff;
	139	cmd[3] = 0xff;
	140	cmd[1] = WSPI_INIT_CMD_START \| WSPI_INIT_CMD_TX;
	141	cmd[0] = 0;
	142	cmd[7] = 0;
	143	cmd[6] \|= HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
	144	cmd[6] \|= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;
	145
	146	if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
	147	cmd[5] \|= WSPI_INIT_CMD_DIS_FIXEDBUSY;
	148	else
	149	cmd[5] \|= WSPI_INIT_CMD_EN_FIXEDBUSY;
	150
	151	cmd[5] \|= WSPI_INIT_CMD_IOD \| WSPI_INIT_CMD_IP \| WSPI_INIT_CMD_CS
	152	\| WSPI_INIT_CMD_WSPI \| WSPI_INIT_CMD_WS;
	153
	154	crc[0] = cmd[1];
	155	crc[1] = cmd[0];
	156	crc[2] = cmd[7];
	157	crc[3] = cmd[6];
	158	crc[4] = cmd[5];
	159
	160	cmd[4] \|= crc7(0, crc, WSPI_INIT_CMD_CRC_LEN) << 1;
	161	cmd[4] \|= WSPI_INIT_CMD_END;
	162
	163	t.tx_buf = cmd;
	164	t.len = WSPI_INIT_CMD_LEN;
	165	spi_message_add_tail(&t, &m);
	166
8197b711	167	spi_sync(wl_to_spi(wl), &m);
f5fc0f86	168	wl1271_dump(DEBUG_SPI, "spi init -> ", cmd, WSPI_INIT_CMD_LEN);
bb123611	169	kfree(cmd);
f5fc0f86 LC	170	}
f5fc0f86 LC	171
545f1da8 JO	172	#define WL1271_BUSY_WORD_TIMEOUT 1000
545f1da8 JO	173
259da430	174	static int wl1271_spi_read_busy(struct wl1271 *wl)
545f1da8 JO	175	{
	176	struct spi_transfer t[1];
	177	struct spi_message m;
	178	u32 *busy_buf;
	179	int num_busy_bytes = 0;
	180
545f1da8 JO	181	/*
	182	* Read further busy words from SPI until a non-busy word is
	183	* encountered, then read the data itself into the buffer.
	184	*/
545f1da8 JO	185
	186	num_busy_bytes = WL1271_BUSY_WORD_TIMEOUT;
	187	busy_buf = wl->buffer_busyword;
	188	while (num_busy_bytes) {
	189	num_busy_bytes--;
	190	spi_message_init(&m);
	191	memset(t, 0, sizeof(t));
	192	t[0].rx_buf = busy_buf;
	193	t[0].len = sizeof(u32);
259da430	194	t[0].cs_change = true;
545f1da8	195	spi_message_add_tail(&t[0], &m);
8197b711	196	spi_sync(wl_to_spi(wl), &m);
545f1da8	197
259da430 JO	198	if (*busy_buf & 0x1)
259da430 JO	199	return 0;
545f1da8 JO	200	}
	201
	202	/* The SPI bus is unresponsive, the read failed. */
545f1da8	203	wl1271_error("SPI read busy-word timeout!\n");
259da430	204	return -ETIMEDOUT;
545f1da8 JO	205	}
545f1da8 JO	206
760d969f	207	static void wl1271_spi_raw_read(struct wl1271 wl, int addr, void buf,
259da430	208	size_t len, bool fixed)
f5fc0f86	209	{
5c57a901	210	struct spi_transfer t[2];
f5fc0f86	211	struct spi_message m;
545f1da8	212	u32 *busy_buf;
f5fc0f86	213	u32 *cmd;
5c57a901	214	u32 chunk_len;
f5fc0f86	215
5c57a901 IY	216	while (len > 0) {
5c57a901 IY	217	chunk_len = min((size_t)WSPI_MAX_CHUNK_SIZE, len);
f5fc0f86	218
5c57a901 IY	219	cmd = &wl->buffer_cmd;
5c57a901 IY	220	busy_buf = wl->buffer_busyword;
f5fc0f86	221
5c57a901 IY	222	*cmd = 0;
	223	*cmd \|= WSPI_CMD_READ;
	224	*cmd \|= (chunk_len << WSPI_CMD_BYTE_LENGTH_OFFSET) &
	225	WSPI_CMD_BYTE_LENGTH;
	226	*cmd \|= addr & WSPI_CMD_BYTE_ADDR;
f5fc0f86	227
5c57a901 IY	228	if (fixed)
5c57a901 IY	229	*cmd \|= WSPI_CMD_FIXED;
f5fc0f86	230
5c57a901 IY	231	spi_message_init(&m);
5c57a901 IY	232	memset(t, 0, sizeof(t));
f5fc0f86	233
5c57a901 IY	234	t[0].tx_buf = cmd;
	235	t[0].len = 4;
	236	t[0].cs_change = true;
	237	spi_message_add_tail(&t[0], &m);
f5fc0f86	238
5c57a901 IY	239	/* Busy and non busy words read */
	240	t[1].rx_buf = busy_buf;
	241	t[1].len = WL1271_BUSY_WORD_LEN;
	242	t[1].cs_change = true;
	243	spi_message_add_tail(&t[1], &m);
f5fc0f86	244
5c57a901	245	spi_sync(wl_to_spi(wl), &m);
259da430	246
5c57a901 IY	247	if (!(busy_buf[WL1271_BUSY_WORD_CNT - 1] & 0x1) &&
	248	wl1271_spi_read_busy(wl)) {
	249	memset(buf, 0, chunk_len);
	250	return;
	251	}
259da430	252
5c57a901 IY	253	spi_message_init(&m);
5c57a901 IY	254	memset(t, 0, sizeof(t));
259da430	255
5c57a901 IY	256	t[0].rx_buf = buf;
	257	t[0].len = chunk_len;
	258	t[0].cs_change = true;
	259	spi_message_add_tail(&t[0], &m);
	260
	261	spi_sync(wl_to_spi(wl), &m);
f5fc0f86	262
5c57a901 IY	263	wl1271_dump(DEBUG_SPI, "spi_read cmd -> ", cmd, sizeof(*cmd));
	264	wl1271_dump(DEBUG_SPI, "spi_read buf <- ", buf, chunk_len);
	265
	266	if (!fixed)
	267	addr += chunk_len;
	268	buf += chunk_len;
	269	len -= chunk_len;
	270	}
f5fc0f86 LC	271	}
f5fc0f86 LC	272
760d969f	273	static void wl1271_spi_raw_write(struct wl1271 wl, int addr, void buf,
74621417	274	size_t len, bool fixed)
f5fc0f86	275	{
5c57a901	276	struct spi_transfer t[2 * WSPI_MAX_NUM_OF_CHUNKS];
f5fc0f86	277	struct spi_message m;
5c57a901	278	u32 commands[WSPI_MAX_NUM_OF_CHUNKS];
f5fc0f86	279	u32 *cmd;
5c57a901 IY	280	u32 chunk_len;
5c57a901 IY	281	int i;
f5fc0f86	282
5c57a901	283	WARN_ON(len > WL1271_AGGR_BUFFER_SIZE);
f5fc0f86 LC	284
	285	spi_message_init(&m);
	286	memset(t, 0, sizeof(t));
	287
5c57a901 IY	288	cmd = &commands[0];
	289	i = 0;
	290	while (len > 0) {
	291	chunk_len = min((size_t)WSPI_MAX_CHUNK_SIZE, len);
f5fc0f86	292
5c57a901 IY	293	*cmd = 0;
	294	*cmd \|= WSPI_CMD_WRITE;
	295	*cmd \|= (chunk_len << WSPI_CMD_BYTE_LENGTH_OFFSET) &
	296	WSPI_CMD_BYTE_LENGTH;
	297	*cmd \|= addr & WSPI_CMD_BYTE_ADDR;
f5fc0f86	298
5c57a901 IY	299	if (fixed)
	300	*cmd \|= WSPI_CMD_FIXED;
	301
	302	t[i].tx_buf = cmd;
	303	t[i].len = sizeof(*cmd);
	304	spi_message_add_tail(&t[i++], &m);
	305
	306	t[i].tx_buf = buf;
	307	t[i].len = chunk_len;
	308	spi_message_add_tail(&t[i++], &m);
f5fc0f86	309
5c57a901 IY	310	wl1271_dump(DEBUG_SPI, "spi_write cmd -> ", cmd, sizeof(*cmd));
	311	wl1271_dump(DEBUG_SPI, "spi_write buf -> ", buf, chunk_len);
	312
	313	if (!fixed)
	314	addr += chunk_len;
	315	buf += chunk_len;
	316	len -= chunk_len;
	317	cmd++;
	318	}
	319
	320	spi_sync(wl_to_spi(wl), &m);
f5fc0f86	321	}
2d5e82b8	322
a620865e	323	static irqreturn_t wl1271_hardirq(int irq, void *cookie)
2d5e82b8	324	{
a620865e	325	struct wl1271 *wl = cookie;
2d5e82b8 TP	326	unsigned long flags;
	327
	328	wl1271_debug(DEBUG_IRQ, "IRQ");
	329
2d5e82b8 TP	330	/* complete the ELP completion */
2d5e82b8 TP	331	spin_lock_irqsave(&wl->wl_lock, flags);
a620865e	332	set_bit(WL1271_FLAG_IRQ_RUNNING, &wl->flags);
2d5e82b8 TP	333	if (wl->elp_compl) {
	334	complete(wl->elp_compl);
	335	wl->elp_compl = NULL;
	336	}
2d5e82b8 TP	337	spin_unlock_irqrestore(&wl->wl_lock, flags);
2d5e82b8 TP	338
a620865e	339	return IRQ_WAKE_THREAD;
2d5e82b8 TP	340	}
2d5e82b8 TP	341
2cc78ff7	342	static int wl1271_spi_set_power(struct wl1271 *wl, bool enable)
becd551c TP	343	{
	344	if (wl->set_power)
	345	wl->set_power(enable);
2cc78ff7 OBC	346
2cc78ff7 OBC	347	return 0;
becd551c TP	348	}
becd551c TP	349
8197b711 TP	350	static struct wl1271_if_operations spi_ops = {
	351	.read = wl1271_spi_raw_read,
	352	.write = wl1271_spi_raw_write,
	353	.reset = wl1271_spi_reset,
	354	.init = wl1271_spi_init,
becd551c	355	.power = wl1271_spi_set_power,
8197b711 TP	356	.dev = wl1271_spi_wl_to_dev,
8197b711 TP	357	.enable_irq = wl1271_spi_enable_interrupts,
a81159ed LC	358	.disable_irq = wl1271_spi_disable_interrupts,
a81159ed LC	359	.set_block_size = NULL,
8197b711 TP	360	};
8197b711 TP	361
2d5e82b8 TP	362	static int __devinit wl1271_probe(struct spi_device *spi)
	363	{
	364	struct wl12xx_platform_data *pdata;
	365	struct ieee80211_hw *hw;
	366	struct wl1271 *wl;
341b7cde	367	unsigned long irqflags;
2d5e82b8 TP	368	int ret;
	369
	370	pdata = spi->dev.platform_data;
	371	if (!pdata) {
	372	wl1271_error("no platform data");
	373	return -ENODEV;
	374	}
	375
	376	hw = wl1271_alloc_hw();
	377	if (IS_ERR(hw))
	378	return PTR_ERR(hw);
	379
	380	wl = hw->priv;
	381
	382	dev_set_drvdata(&spi->dev, wl);
8197b711 TP	383	wl->if_priv = spi;
	384
	385	wl->if_ops = &spi_ops;
2d5e82b8 TP	386
	387	/* This is the only SPI value that we need to set here, the rest
	388	* comes from the board-peripherals file */
	389	spi->bits_per_word = 32;
	390
	391	ret = spi_setup(spi);
	392	if (ret < 0) {
	393	wl1271_error("spi_setup failed");
	394	goto out_free;
	395	}
	396
	397	wl->set_power = pdata->set_power;
	398	if (!wl->set_power) {
	399	wl1271_error("set power function missing in platform data");
	400	ret = -ENODEV;
	401	goto out_free;
	402	}
	403
15cea993	404	wl->ref_clock = pdata->board_ref_clock;
5ea417ae	405	wl->tcxo_clock = pdata->board_tcxo_clock;
341b7cde IY	406	wl->platform_quirks = pdata->platform_quirks;
	407
	408	if (wl->platform_quirks & WL12XX_PLATFORM_QUIRK_EDGE_IRQ)
	409	irqflags = IRQF_TRIGGER_RISING;
	410	else
	411	irqflags = IRQF_TRIGGER_HIGH \| IRQF_ONESHOT;
15cea993	412
2d5e82b8 TP	413	wl->irq = spi->irq;
	414	if (wl->irq < 0) {
	415	wl1271_error("irq missing in platform data");
	416	ret = -ENODEV;
	417	goto out_free;
	418	}
	419
a620865e	420	ret = request_threaded_irq(wl->irq, wl1271_hardirq, wl1271_irq,
341b7cde	421	irqflags,
a620865e	422	DRIVER_NAME, wl);
2d5e82b8 TP	423	if (ret < 0) {
	424	wl1271_error("request_irq() failed: %d", ret);
	425	goto out_free;
	426	}
	427
2d5e82b8 TP	428	disable_irq(wl->irq);
2d5e82b8 TP	429
2d5e82b8 TP	430	ret = wl1271_init_ieee80211(wl);
2d5e82b8 TP	431	if (ret)
a1dd8187	432	goto out_irq;
2d5e82b8 TP	433
	434	ret = wl1271_register_hw(wl);
	435	if (ret)
a1dd8187	436	goto out_irq;
2d5e82b8 TP	437
	438	wl1271_notice("initialized");
	439
	440	return 0;
	441
2d5e82b8 TP	442	out_irq:
	443	free_irq(wl->irq, wl);
	444
	445	out_free:
3b56dd6a	446	wl1271_free_hw(wl);
2d5e82b8 TP	447
	448	return ret;
	449	}
	450
	451	static int __devexit wl1271_remove(struct spi_device *spi)
	452	{
	453	struct wl1271 *wl = dev_get_drvdata(&spi->dev);
	454
3b56dd6a	455	wl1271_unregister_hw(wl);
4e23b11b	456	free_irq(wl->irq, wl);
2d5e82b8 TP	457	wl1271_free_hw(wl);
	458
	459	return 0;
	460	}
	461
	462
	463	static struct spi_driver wl1271_spi_driver = {
	464	.driver = {
7fdd50d0	465	.name = "wl1271_spi",
2d5e82b8 TP	466	.bus = &spi_bus_type,
	467	.owner = THIS_MODULE,
	468	},
	469
	470	.probe = wl1271_probe,
	471	.remove = __devexit_p(wl1271_remove),
	472	};
	473
	474	static int __init wl1271_init(void)
	475	{
	476	int ret;
	477
	478	ret = spi_register_driver(&wl1271_spi_driver);
	479	if (ret < 0) {
	480	wl1271_error("failed to register spi driver: %d", ret);
	481	goto out;
	482	}
	483
	484	out:
	485	return ret;
	486	}
	487
	488	static void __exit wl1271_exit(void)
	489	{
	490	spi_unregister_driver(&wl1271_spi_driver);
	491
	492	wl1271_notice("unloaded");
	493	}
	494
	495	module_init(wl1271_init);
	496	module_exit(wl1271_exit);
	497
	498	MODULE_LICENSE("GPL");
5245e3a9	499	MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
2d5e82b8 TP	500	MODULE_AUTHOR("Juuso Oikarinen <juuso.oikarinen@nokia.com>");
2d5e82b8 TP	501	MODULE_FIRMWARE(WL1271_FW_NAME);
5aa42346	502	MODULE_FIRMWARE(WL128X_FW_NAME);
1aed55fd AN	503	MODULE_FIRMWARE(WL127X_AP_FW_NAME);
1aed55fd AN	504	MODULE_FIRMWARE(WL128X_AP_FW_NAME);
f148cfdd	505	MODULE_ALIAS("spi:wl1271");