[linux-2.6-block.git] / drivers / net / wireless / wl12xx / rx.c

/*
 * This file is part of wl1271
 *
 * Copyright (C) 2009 Nokia Corporation
 *
 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/gfp.h>
#include <linux/sched.h>

#include "wl12xx.h"
#include "acx.h"
#include "reg.h"
#include "rx.h"
#include "io.h"

static u8 wl12xx_rx_get_mem_block(struct wl12xx_fw_status *status,
				  u32 drv_rx_counter)
{
	return le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) &
		RX_MEM_BLOCK_MASK;
}

static u32 wl12xx_rx_get_buf_size(struct wl12xx_fw_status *status,
				 u32 drv_rx_counter)
{
	return (le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) &
		RX_BUF_SIZE_MASK) >> RX_BUF_SIZE_SHIFT_DIV;
}

static bool wl12xx_rx_get_unaligned(struct wl12xx_fw_status *status,
				    u32 drv_rx_counter)
{
	/* Convert the value to bool */
	return !!(le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) &
		RX_BUF_UNALIGNED_PAYLOAD);
}

static void wl1271_rx_status(struct wl1271 *wl,
			     struct wl1271_rx_descriptor *desc,
			     struct ieee80211_rx_status *status,
			     u8 beacon)
{
	memset(status, 0, sizeof(struct ieee80211_rx_status));

	if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == WL1271_RX_DESC_BAND_BG)
		status->band = IEEE80211_BAND_2GHZ;
	else
		status->band = IEEE80211_BAND_5GHZ;

	status->rate_idx = wl1271_rate_to_idx(desc->rate, status->band);

	/* 11n support */
	if (desc->rate <= CONF_HW_RXTX_RATE_MCS0)
		status->flag |= RX_FLAG_HT;

	status->signal = desc->rssi;

	/*
	 * FIXME: In wl1251, the SNR should be divided by two.  In wl1271 we
	 * need to divide by two for now, but TI has been discussing about
	 * changing it.  This needs to be rechecked.
	 */
	wl->noise = desc->rssi - (desc->snr >> 1);

	status->freq = ieee80211_channel_to_frequency(desc->channel,
						      status->band);

	if (desc->flags & WL1271_RX_DESC_ENCRYPT_MASK) {
		u8 desc_err_code = desc->status & WL1271_RX_DESC_STATUS_MASK;

		status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED |
				RX_FLAG_DECRYPTED;

		if (unlikely(desc_err_code == WL1271_RX_DESC_MIC_FAIL)) {
			status->flag |= RX_FLAG_MMIC_ERROR;
			wl1271_warning("Michael MIC error");
		}
	}
}

static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length,
				 bool unaligned)
{
	struct wl1271_rx_descriptor *desc;
	struct sk_buff *skb;
	struct ieee80211_hdr *hdr;
	u8 *buf;
	u8 beacon = 0;
	u8 is_data = 0;
	u8 reserved = unaligned ? NET_IP_ALIGN : 0;
	u16 seq_num;

	/*
	 * In PLT mode we seem to get frames and mac80211 warns about them,
	 * workaround this by not retrieving them at all.
	 */
	if (unlikely(wl->state == WL1271_STATE_PLT))
		return -EINVAL;

	/* the data read starts with the descriptor */
	desc = (struct wl1271_rx_descriptor *) data;

	if (desc->packet_class == WL12XX_RX_CLASS_LOGGER) {
		size_t len = length - sizeof(*desc);
		wl12xx_copy_fwlog(wl, data + sizeof(*desc), len);
		wake_up_interruptible(&wl->fwlog_waitq);
		return 0;
	}

	switch (desc->status & WL1271_RX_DESC_STATUS_MASK) {
	/* discard corrupted packets */
	case WL1271_RX_DESC_DRIVER_RX_Q_FAIL:
	case WL1271_RX_DESC_DECRYPT_FAIL:
		wl1271_warning("corrupted packet in RX with status: 0x%x",
			       desc->status & WL1271_RX_DESC_STATUS_MASK);
		return -EINVAL;
	case WL1271_RX_DESC_SUCCESS:
	case WL1271_RX_DESC_MIC_FAIL:
		break;
	default:
		wl1271_error("invalid RX descriptor status: 0x%x",
			     desc->status & WL1271_RX_DESC_STATUS_MASK);
		return -EINVAL;
	}

	/* skb length not included rx descriptor */
	skb = __dev_alloc_skb(length + reserved - sizeof(*desc), GFP_KERNEL);
	if (!skb) {
		wl1271_error("Couldn't allocate RX frame");
		return -ENOMEM;
	}

	/* reserve the unaligned payload(if any) */
	skb_reserve(skb, reserved);

	buf = skb_put(skb, length - sizeof(*desc));

	/*
	 * Copy packets from aggregation buffer to the skbs without rx
	 * descriptor and with packet payload aligned care. In case of unaligned
	 * packets copy the packets in offset of 2 bytes guarantee IP header
	 * payload aligned to 4 bytes.
	 */
	memcpy(buf, data + sizeof(*desc), length - sizeof(*desc));

	hdr = (struct ieee80211_hdr *)skb->data;
	if (ieee80211_is_beacon(hdr->frame_control))
		beacon = 1;
	if (ieee80211_is_data_present(hdr->frame_control))
		is_data = 1;

	wl1271_rx_status(wl, desc, IEEE80211_SKB_RXCB(skb), beacon);

	seq_num = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
	wl1271_debug(DEBUG_RX, "rx skb 0x%p: %d B %s seq %d", skb,
		     skb->len - desc->pad_len,
		     beacon ? "beacon" : "",
		     seq_num);

	skb_trim(skb, skb->len - desc->pad_len);

	skb_queue_tail(&wl->deferred_rx_queue, skb);
	queue_work(wl->freezable_wq, &wl->netstack_work);

	return is_data;
}

void wl12xx_rx(struct wl1271 *wl, struct wl12xx_fw_status *status)
{
	struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
	u32 buf_size;
	u32 fw_rx_counter  = status->fw_rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
	u32 drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
	u32 rx_counter;
	u32 mem_block;
	u32 pkt_length;
	u32 pkt_offset;
	bool is_ap = (wl->bss_type == BSS_TYPE_AP_BSS);
	bool had_data = false;
	bool unaligned = false;

	while (drv_rx_counter != fw_rx_counter) {
		buf_size = 0;
		rx_counter = drv_rx_counter;
		while (rx_counter != fw_rx_counter) {
			pkt_length = wl12xx_rx_get_buf_size(status, rx_counter);
			if (buf_size + pkt_length > WL1271_AGGR_BUFFER_SIZE)
				break;
			buf_size += pkt_length;
			rx_counter++;
			rx_counter &= NUM_RX_PKT_DESC_MOD_MASK;
		}

		if (buf_size == 0) {
			wl1271_warning("received empty data");
			break;
		}

		if (wl->chip.id != CHIP_ID_1283_PG20) {
			/*
			 * Choose the block we want to read
			 * For aggregated packets, only the first memory block
			 * should be retrieved. The FW takes care of the rest.
			 */
			mem_block = wl12xx_rx_get_mem_block(status,
							    drv_rx_counter);

			wl->rx_mem_pool_addr.addr = (mem_block << 8) +
			   le32_to_cpu(wl_mem_map->packet_memory_pool_start);

			wl->rx_mem_pool_addr.addr_extra =
				wl->rx_mem_pool_addr.addr + 4;

			wl1271_write(wl, WL1271_SLV_REG_DATA,
				     &wl->rx_mem_pool_addr,
				     sizeof(wl->rx_mem_pool_addr), false);
		}

		/* Read all available packets at once */
		wl1271_read(wl, WL1271_SLV_MEM_DATA, wl->aggr_buf,
				buf_size, true);

		/* Split data into separate packets */
		pkt_offset = 0;
		while (pkt_offset < buf_size) {
			pkt_length = wl12xx_rx_get_buf_size(status,
					drv_rx_counter);

			unaligned = wl12xx_rx_get_unaligned(status,
					drv_rx_counter);

			/*
			 * the handle data call can only fail in memory-outage
			 * conditions, in that case the received frame will just
			 * be dropped.
			 */
			if (wl1271_rx_handle_data(wl,
						  wl->aggr_buf + pkt_offset,
						  pkt_length, unaligned) == 1)
				had_data = true;

			wl->rx_counter++;
			drv_rx_counter++;
			drv_rx_counter &= NUM_RX_PKT_DESC_MOD_MASK;
			pkt_offset += pkt_length;
		}
	}

	/*
	 * Write the driver's packet counter to the FW. This is only required
	 * for older hardware revisions
	 */
	if (wl->quirks & WL12XX_QUIRK_END_OF_TRANSACTION)
		wl1271_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter);

	if (!is_ap && wl->conf.rx_streaming.interval && had_data &&
	    (wl->conf.rx_streaming.always ||
	     test_bit(WL1271_FLAG_SOFT_GEMINI, &wl->flags))) {
		u32 timeout = wl->conf.rx_streaming.duration;

		/* restart rx streaming */
		if (!test_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags))
			ieee80211_queue_work(wl->hw,
					     &wl->rx_streaming_enable_work);

		mod_timer(&wl->rx_streaming_timer,
			  jiffies + msecs_to_jiffies(timeout));
	}
}
Commit	Line	Data
f5fc0f86 LC	1	/*
	2	* This file is part of wl1271
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	*
	6	* Contact: Luciano Coelho <luciano.coelho@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
5a0e3ad6	24	#include <linux/gfp.h>
95dac04f	25	#include <linux/sched.h>
5a0e3ad6	26
00d20100 SL	27	#include "wl12xx.h"
	28	#include "acx.h"
	29	#include "reg.h"
	30	#include "rx.h"
	31	#include "io.h"
f5fc0f86	32
4d56ad9c	33	static u8 wl12xx_rx_get_mem_block(struct wl12xx_fw_status *status,
f5fc0f86 LC	34	u32 drv_rx_counter)
f5fc0f86 LC	35	{
d0f63b20 LC	36	return le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) &
d0f63b20 LC	37	RX_MEM_BLOCK_MASK;
f5fc0f86 LC	38	}
f5fc0f86 LC	39
4d56ad9c EP	40	static u32 wl12xx_rx_get_buf_size(struct wl12xx_fw_status *status,
4d56ad9c EP	41	u32 drv_rx_counter)
f5fc0f86	42	{
d0f63b20 LC	43	return (le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) &
d0f63b20 LC	44	RX_BUF_SIZE_MASK) >> RX_BUF_SIZE_SHIFT_DIV;
f5fc0f86 LC	45	}
f5fc0f86 LC	46
4d56ad9c	47	static bool wl12xx_rx_get_unaligned(struct wl12xx_fw_status *status,
0a1d3abc SL	48	u32 drv_rx_counter)
	49	{
	50	/* Convert the value to bool */
	51	return !!(le32_to_cpu(status->rx_pkt_descs[drv_rx_counter]) &
	52	RX_BUF_UNALIGNED_PAYLOAD);
	53	}
	54
f5fc0f86 LC	55	static void wl1271_rx_status(struct wl1271 *wl,
	56	struct wl1271_rx_descriptor *desc,
	57	struct ieee80211_rx_status *status,
	58	u8 beacon)
	59	{
	60	memset(status, 0, sizeof(struct ieee80211_rx_status));
	61
6a2de93b	62	if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == WL1271_RX_DESC_BAND_BG)
0af0467f	63	status->band = IEEE80211_BAND_2GHZ;
6a2de93b	64	else
0af0467f	65	status->band = IEEE80211_BAND_5GHZ;
6a2de93b	66
0af0467f	67	status->rate_idx = wl1271_rate_to_idx(desc->rate, status->band);
a4102645	68
18357850 SL	69	/* 11n support */
	70	if (desc->rate <= CONF_HW_RXTX_RATE_MCS0)
	71	status->flag \|= RX_FLAG_HT;
18357850	72
f5fc0f86 LC	73	status->signal = desc->rssi;
f5fc0f86 LC	74
ece550d0 JL	75	/*
	76	* FIXME: In wl1251, the SNR should be divided by two. In wl1271 we
	77	* need to divide by two for now, but TI has been discussing about
	78	* changing it. This needs to be rechecked.
	79	*/
	80	wl->noise = desc->rssi - (desc->snr >> 1);
	81
0af0467f JO	82	status->freq = ieee80211_channel_to_frequency(desc->channel,
0af0467f JO	83	status->band);
f5fc0f86 LC	84
f5fc0f86 LC	85	if (desc->flags & WL1271_RX_DESC_ENCRYPT_MASK) {
34c8e3d2	86	u8 desc_err_code = desc->status & WL1271_RX_DESC_STATUS_MASK;
f5fc0f86	87
34c8e3d2 AN	88	status->flag \|= RX_FLAG_IV_STRIPPED \| RX_FLAG_MMIC_STRIPPED \|
	89	RX_FLAG_DECRYPTED;
	90
	91	if (unlikely(desc_err_code == WL1271_RX_DESC_MIC_FAIL)) {
5d07b668	92	status->flag \|= RX_FLAG_MMIC_ERROR;
34c8e3d2 AN	93	wl1271_warning("Michael MIC error");
34c8e3d2 AN	94	}
f5fc0f86	95	}
f5fc0f86 LC	96	}
f5fc0f86 LC	97
0a1d3abc SL	98	static int wl1271_rx_handle_data(struct wl1271 wl, u8 data, u32 length,
0a1d3abc SL	99	bool unaligned)
f5fc0f86	100	{
f5fc0f86 LC	101	struct wl1271_rx_descriptor *desc;
f5fc0f86 LC	102	struct sk_buff *skb;
92fe9b5f	103	struct ieee80211_hdr *hdr;
f5fc0f86 LC	104	u8 *buf;
f5fc0f86 LC	105	u8 beacon = 0;
77ddaa10	106	u8 is_data = 0;
0a1d3abc	107	u8 reserved = unaligned ? NET_IP_ALIGN : 0;
5c472148	108	u16 seq_num;
f5fc0f86	109
93c5bb68 KV	110	/*
	111	* In PLT mode we seem to get frames and mac80211 warns about them,
	112	* workaround this by not retrieving them at all.
	113	*/
	114	if (unlikely(wl->state == WL1271_STATE_PLT))
1f37cbc9	115	return -EINVAL;
93c5bb68	116
34c8e3d2 AN	117	/* the data read starts with the descriptor */
	118	desc = (struct wl1271_rx_descriptor *) data;
	119
95dac04f IY	120	if (desc->packet_class == WL12XX_RX_CLASS_LOGGER) {
	121	size_t len = length - sizeof(*desc);
	122	wl12xx_copy_fwlog(wl, data + sizeof(*desc), len);
	123	wake_up_interruptible(&wl->fwlog_waitq);
	124	return 0;
	125	}
	126
34c8e3d2 AN	127	switch (desc->status & WL1271_RX_DESC_STATUS_MASK) {
	128	/* discard corrupted packets */
	129	case WL1271_RX_DESC_DRIVER_RX_Q_FAIL:
	130	case WL1271_RX_DESC_DECRYPT_FAIL:
	131	wl1271_warning("corrupted packet in RX with status: 0x%x",
	132	desc->status & WL1271_RX_DESC_STATUS_MASK);
	133	return -EINVAL;
	134	case WL1271_RX_DESC_SUCCESS:
	135	case WL1271_RX_DESC_MIC_FAIL:
	136	break;
	137	default:
	138	wl1271_error("invalid RX descriptor status: 0x%x",
	139	desc->status & WL1271_RX_DESC_STATUS_MASK);
	140	return -EINVAL;
	141	}
	142
0a1d3abc SL	143	/* skb length not included rx descriptor */
0a1d3abc SL	144	skb = __dev_alloc_skb(length + reserved - sizeof(*desc), GFP_KERNEL);
f5fc0f86 LC	145	if (!skb) {
f5fc0f86 LC	146	wl1271_error("Couldn't allocate RX frame");
1f37cbc9	147	return -ENOMEM;
f5fc0f86 LC	148	}
f5fc0f86 LC	149
0a1d3abc SL	150	/* reserve the unaligned payload(if any) */
	151	skb_reserve(skb, reserved);
	152
	153	buf = skb_put(skb, length - sizeof(*desc));
f5fc0f86	154
0a1d3abc SL	155	/*
	156	* Copy packets from aggregation buffer to the skbs without rx
	157	* descriptor and with packet payload aligned care. In case of unaligned
	158	* packets copy the packets in offset of 2 bytes guarantee IP header
	159	* payload aligned to 4 bytes.
	160	*/
	161	memcpy(buf, data + sizeof(desc), length - sizeof(desc));
f5fc0f86	162
92fe9b5f EP	163	hdr = (struct ieee80211_hdr *)skb->data;
92fe9b5f EP	164	if (ieee80211_is_beacon(hdr->frame_control))
f5fc0f86	165	beacon = 1;
77ddaa10 EP	166	if (ieee80211_is_data_present(hdr->frame_control))
77ddaa10 EP	167	is_data = 1;
f5fc0f86	168
58be4607	169	wl1271_rx_status(wl, desc, IEEE80211_SKB_RXCB(skb), beacon);
f5fc0f86	170
5c472148 EP	171	seq_num = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
5c472148 EP	172	wl1271_debug(DEBUG_RX, "rx skb 0x%p: %d B %s seq %d", skb,
a20a5b7e	173	skb->len - desc->pad_len,
5c472148 EP	174	beacon ? "beacon" : "",
5c472148 EP	175	seq_num);
f5fc0f86	176
b9f2e39d JO	177	skb_trim(skb, skb->len - desc->pad_len);
b9f2e39d JO	178
a620865e	179	skb_queue_tail(&wl->deferred_rx_queue, skb);
92ef8960	180	queue_work(wl->freezable_wq, &wl->netstack_work);
1f37cbc9	181
77ddaa10	182	return is_data;
f5fc0f86 LC	183	}
f5fc0f86 LC	184
4d56ad9c	185	void wl12xx_rx(struct wl1271 wl, struct wl12xx_fw_status status)
f5fc0f86 LC	186	{
	187	struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map;
	188	u32 buf_size;
	189	u32 fw_rx_counter = status->fw_rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
	190	u32 drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
1f37cbc9	191	u32 rx_counter;
f5fc0f86	192	u32 mem_block;
1f37cbc9 IY	193	u32 pkt_length;
1f37cbc9 IY	194	u32 pkt_offset;
77ddaa10 EP	195	bool is_ap = (wl->bss_type == BSS_TYPE_AP_BSS);
77ddaa10 EP	196	bool had_data = false;
0a1d3abc	197	bool unaligned = false;
f5fc0f86 LC	198
f5fc0f86 LC	199	while (drv_rx_counter != fw_rx_counter) {
1f37cbc9 IY	200	buf_size = 0;
	201	rx_counter = drv_rx_counter;
	202	while (rx_counter != fw_rx_counter) {
4d56ad9c	203	pkt_length = wl12xx_rx_get_buf_size(status, rx_counter);
1f37cbc9 IY	204	if (buf_size + pkt_length > WL1271_AGGR_BUFFER_SIZE)
	205	break;
	206	buf_size += pkt_length;
	207	rx_counter++;
	208	rx_counter &= NUM_RX_PKT_DESC_MOD_MASK;
	209	}
f5fc0f86 LC	210
	211	if (buf_size == 0) {
	212	wl1271_warning("received empty data");
	213	break;
	214	}
	215
ae77eccf SL	216	if (wl->chip.id != CHIP_ID_1283_PG20) {
	217	/*
	218	* Choose the block we want to read
	219	* For aggregated packets, only the first memory block
	220	* should be retrieved. The FW takes care of the rest.
	221	*/
4d56ad9c	222	mem_block = wl12xx_rx_get_mem_block(status,
ae77eccf SL	223	drv_rx_counter);
	224
	225	wl->rx_mem_pool_addr.addr = (mem_block << 8) +
	226	le32_to_cpu(wl_mem_map->packet_memory_pool_start);
	227
	228	wl->rx_mem_pool_addr.addr_extra =
	229	wl->rx_mem_pool_addr.addr + 4;
	230
	231	wl1271_write(wl, WL1271_SLV_REG_DATA,
	232	&wl->rx_mem_pool_addr,
	233	sizeof(wl->rx_mem_pool_addr), false);
	234	}
1f37cbc9 IY	235
	236	/* Read all available packets at once */
	237	wl1271_read(wl, WL1271_SLV_MEM_DATA, wl->aggr_buf,
	238	buf_size, true);
	239
	240	/* Split data into separate packets */
	241	pkt_offset = 0;
	242	while (pkt_offset < buf_size) {
4d56ad9c	243	pkt_length = wl12xx_rx_get_buf_size(status,
1f37cbc9	244	drv_rx_counter);
0a1d3abc	245
4d56ad9c	246	unaligned = wl12xx_rx_get_unaligned(status,
0a1d3abc SL	247	drv_rx_counter);
0a1d3abc SL	248
fb2382c7 JO	249	/*
	250	* the handle data call can only fail in memory-outage
	251	* conditions, in that case the received frame will just
	252	* be dropped.
	253	*/
77ddaa10 EP	254	if (wl1271_rx_handle_data(wl,
77ddaa10 EP	255	wl->aggr_buf + pkt_offset,
0a1d3abc	256	pkt_length, unaligned) == 1)
77ddaa10 EP	257	had_data = true;
77ddaa10 EP	258
1f37cbc9 IY	259	wl->rx_counter++;
	260	drv_rx_counter++;
	261	drv_rx_counter &= NUM_RX_PKT_DESC_MOD_MASK;
	262	pkt_offset += pkt_length;
	263	}
f5fc0f86	264	}
606ea9fa IY	265
	266	/*
	267	* Write the driver's packet counter to the FW. This is only required
	268	* for older hardware revisions
	269	*/
	270	if (wl->quirks & WL12XX_QUIRK_END_OF_TRANSACTION)
	271	wl1271_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter);
77ddaa10 EP	272
	273	if (!is_ap && wl->conf.rx_streaming.interval && had_data &&
	274	(wl->conf.rx_streaming.always \|\|
	275	test_bit(WL1271_FLAG_SOFT_GEMINI, &wl->flags))) {
	276	u32 timeout = wl->conf.rx_streaming.duration;
	277
	278	/* restart rx streaming */
	279	if (!test_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags))
	280	ieee80211_queue_work(wl->hw,
	281	&wl->rx_streaming_enable_work);
	282
	283	mod_timer(&wl->rx_streaming_timer,
	284	jiffies + msecs_to_jiffies(timeout));
	285	}
f5fc0f86	286	}