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1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 2008-2009 Nokia Corporation | |
5 | * | |
6 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #ifndef __BOOT_H__ | |
25 | #define __BOOT_H__ | |
26 | ||
00d20100 | 27 | #include "wl12xx.h" |
f5fc0f86 LC |
28 | |
29 | int wl1271_boot(struct wl1271 *wl); | |
870c367c | 30 | int wl1271_load_firmware(struct wl1271 *wl); |
f5fc0f86 LC |
31 | |
32 | #define WL1271_NO_SUBBANDS 8 | |
33 | #define WL1271_NO_POWER_LEVELS 4 | |
34 | #define WL1271_FW_VERSION_MAX_LEN 20 | |
35 | ||
36 | struct wl1271_static_data { | |
37 | u8 mac_address[ETH_ALEN]; | |
38 | u8 padding[2]; | |
39 | u8 fw_version[WL1271_FW_VERSION_MAX_LEN]; | |
40 | u32 hw_version; | |
41 | u8 tx_power_table[WL1271_NO_SUBBANDS][WL1271_NO_POWER_LEVELS]; | |
42 | }; | |
43 | ||
44 | /* number of times we try to read the INIT interrupt */ | |
45 | #define INIT_LOOP 20000 | |
46 | ||
47 | /* delay between retries */ | |
48 | #define INIT_LOOP_DELAY 50 | |
49 | ||
f5fc0f86 LC |
50 | #define WU_COUNTER_PAUSE_VAL 0x3FF |
51 | #define WELP_ARM_COMMAND_VAL 0x4 | |
52 | ||
284134eb JO |
53 | #define OCP_REG_POLARITY 0x0064 |
54 | #define OCP_REG_CLK_TYPE 0x0448 | |
55 | #define OCP_REG_CLK_POLARITY 0x0cb2 | |
9d4e5bb3 | 56 | #define OCP_REG_CLK_PULL 0x0cb4 |
f5fc0f86 | 57 | |
9d4e5bb3 JO |
58 | #define CMD_MBOX_ADDRESS 0x407B4 |
59 | ||
60 | #define POLARITY_LOW BIT(1) | |
61 | #define NO_PULL (BIT(14) | BIT(15)) | |
f5fc0f86 | 62 | |
284134eb JO |
63 | #define FREF_CLK_TYPE_BITS 0xfffffe7f |
64 | #define CLK_REQ_PRCM 0x100 | |
65 | #define FREF_CLK_POLARITY_BITS 0xfffff8ff | |
66 | #define CLK_REQ_OUTN_SEL 0x700 | |
67 | ||
5aa42346 SL |
68 | /* PLL configuration algorithm for wl128x */ |
69 | #define SYS_CLK_CFG_REG 0x2200 | |
70 | /* Bit[0] - 0-TCXO, 1-FREF */ | |
71 | #define MCS_PLL_CLK_SEL_FREF BIT(0) | |
72 | /* Bit[3:2] - 01-TCXO, 10-FREF */ | |
73 | #define WL_CLK_REQ_TYPE_FREF BIT(3) | |
74 | #define WL_CLK_REQ_TYPE_PG2 (BIT(3) | BIT(2)) | |
75 | /* Bit[4] - 0-TCXO, 1-FREF */ | |
76 | #define PRCM_CM_EN_MUX_WLAN_FREF BIT(4) | |
77 | ||
78 | #define TCXO_ILOAD_INT_REG 0x2264 | |
79 | #define TCXO_CLK_DETECT_REG 0x2266 | |
80 | ||
81 | #define TCXO_DET_FAILED BIT(4) | |
82 | ||
83 | #define FREF_ILOAD_INT_REG 0x2084 | |
84 | #define FREF_CLK_DETECT_REG 0x2086 | |
85 | #define FREF_CLK_DETECT_FAIL BIT(4) | |
86 | ||
87 | /* Use this reg for masking during driver access */ | |
88 | #define WL_SPARE_REG 0x2320 | |
89 | #define WL_SPARE_VAL BIT(2) | |
90 | /* Bit[6:5:3] - mask wl write SYS_CLK_CFG[8:5:2:4] */ | |
91 | #define WL_SPARE_MASK_8526 (BIT(6) | BIT(5) | BIT(3)) | |
92 | ||
93 | #define PLL_LOCK_COUNTERS_REG 0xD8C | |
94 | #define PLL_LOCK_COUNTERS_COEX 0x0F | |
95 | #define PLL_LOCK_COUNTERS_MCS 0xF0 | |
96 | #define MCS_PLL_OVERRIDE_REG 0xD90 | |
97 | #define MCS_PLL_CONFIG_REG 0xD92 | |
98 | #define MCS_SEL_IN_FREQ_MASK 0x0070 | |
99 | #define MCS_SEL_IN_FREQ_SHIFT 4 | |
100 | #define MCS_PLL_CONFIG_REG_VAL 0x73 | |
d29633b4 | 101 | #define MCS_PLL_ENABLE_HP (BIT(0) | BIT(1)) |
5aa42346 SL |
102 | |
103 | #define MCS_PLL_M_REG 0xD94 | |
104 | #define MCS_PLL_N_REG 0xD96 | |
105 | #define MCS_PLL_M_REG_VAL 0xC8 | |
106 | #define MCS_PLL_N_REG_VAL 0x07 | |
107 | ||
108 | #define SDIO_IO_DS 0xd14 | |
109 | ||
110 | /* SDIO/wSPI DS configuration values */ | |
afb7d3cd LC |
111 | enum { |
112 | HCI_IO_DS_8MA = 0, | |
113 | HCI_IO_DS_4MA = 1, /* default */ | |
114 | HCI_IO_DS_6MA = 2, | |
115 | HCI_IO_DS_2MA = 3, | |
116 | }; | |
117 | ||
5aa42346 SL |
118 | /* end PLL configuration algorithm for wl128x */ |
119 | ||
f5fc0f86 | 120 | #endif |