[linux-2.6-block.git] / drivers / net / wireless / wl12xx / boot.c

/*
 * This file is part of wl1271
 *
 * Copyright (C) 2008-2010 Nokia Corporation
 *
 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#include <linux/slab.h>

#include "acx.h"
#include "reg.h"
#include "boot.h"
#include "io.h"
#include "event.h"
#include "rx.h"

static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
	[PART_DOWN] = {
		.mem = {
			.start = 0x00000000,
			.size  = 0x000177c0
		},
		.reg = {
			.start = REGISTERS_BASE,
			.size  = 0x00008800
		},
		.mem2 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
		.mem3 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
	},

	[PART_WORK] = {
		.mem = {
			.start = 0x00040000,
			.size  = 0x00014fc0
		},
		.reg = {
			.start = REGISTERS_BASE,
			.size  = 0x0000a000
		},
		.mem2 = {
			.start = 0x003004f8,
			.size  = 0x00000004
		},
		.mem3 = {
			.start = 0x00040404,
			.size  = 0x00000000
		},
	},

	[PART_DRPW] = {
		.mem = {
			.start = 0x00040000,
			.size  = 0x00014fc0
		},
		.reg = {
			.start = DRPW_BASE,
			.size  = 0x00006000
		},
		.mem2 = {
			.start = 0x00000000,
			.size  = 0x00000000
		},
		.mem3 = {
			.start = 0x00000000,
			.size  = 0x00000000
		}
	}
};

static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
{
	u32 cpu_ctrl;

	/* 10.5.0 run the firmware (I) */
	cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);

	/* 10.5.1 run the firmware (II) */
	cpu_ctrl |= flag;
	wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
}

static void wl1271_parse_fw_ver(struct wl1271 *wl)
{
	int ret;

	ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
		     &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
		     &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
		     &wl->chip.fw_ver[4]);

	if (ret != 5) {
		wl1271_warning("fw version incorrect value");
		memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
		return;
	}
}

static void wl1271_boot_fw_version(struct wl1271 *wl)
{
	struct wl1271_static_data static_data;

	wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
		    false);

	strncpy(wl->chip.fw_ver_str, static_data.fw_version,
		sizeof(wl->chip.fw_ver_str));

	/* make sure the string is NULL-terminated */
	wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';

	wl1271_parse_fw_ver(wl);
}

static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
					     size_t fw_data_len, u32 dest)
{
	struct wl1271_partition_set partition;
	int addr, chunk_num, partition_limit;
	u8 *p, *chunk;

	/* whal_FwCtrl_LoadFwImageSm() */

	wl1271_debug(DEBUG_BOOT, "starting firmware upload");

	wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
		     fw_data_len, CHUNK_SIZE);

	if ((fw_data_len % 4) != 0) {
		wl1271_error("firmware length not multiple of four");
		return -EIO;
	}

	chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
	if (!chunk) {
		wl1271_error("allocation for firmware upload chunk failed");
		return -ENOMEM;
	}

	memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
	partition.mem.start = dest;
	wl1271_set_partition(wl, &partition);

	/* 10.1 set partition limit and chunk num */
	chunk_num = 0;
	partition_limit = part_table[PART_DOWN].mem.size;

	while (chunk_num < fw_data_len / CHUNK_SIZE) {
		/* 10.2 update partition, if needed */
		addr = dest + (chunk_num + 2) * CHUNK_SIZE;
		if (addr > partition_limit) {
			addr = dest + chunk_num * CHUNK_SIZE;
			partition_limit = chunk_num * CHUNK_SIZE +
				part_table[PART_DOWN].mem.size;
			partition.mem.start = addr;
			wl1271_set_partition(wl, &partition);
		}

		/* 10.3 upload the chunk */
		addr = dest + chunk_num * CHUNK_SIZE;
		p = buf + chunk_num * CHUNK_SIZE;
		memcpy(chunk, p, CHUNK_SIZE);
		wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
			     p, addr);
		wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);

		chunk_num++;
	}

	/* 10.4 upload the last chunk */
	addr = dest + chunk_num * CHUNK_SIZE;
	p = buf + chunk_num * CHUNK_SIZE;
	memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
	wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
		     fw_data_len % CHUNK_SIZE, p, addr);
	wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);

	kfree(chunk);
	return 0;
}

static int wl1271_boot_upload_firmware(struct wl1271 *wl)
{
	u32 chunks, addr, len;
	int ret = 0;
	u8 *fw;

	fw = wl->fw;
	chunks = be32_to_cpup((__be32 *) fw);
	fw += sizeof(u32);

	wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);

	while (chunks--) {
		addr = be32_to_cpup((__be32 *) fw);
		fw += sizeof(u32);
		len = be32_to_cpup((__be32 *) fw);
		fw += sizeof(u32);

		if (len > 300000) {
			wl1271_info("firmware chunk too long: %u", len);
			return -EINVAL;
		}
		wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
			     chunks, addr, len);
		ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
		if (ret != 0)
			break;
		fw += len;
	}

	return ret;
}

static int wl1271_boot_upload_nvs(struct wl1271 *wl)
{
	size_t nvs_len, burst_len;
	int i;
	u32 dest_addr, val;
	u8 *nvs_ptr, *nvs_aligned;

	if (wl->nvs == NULL)
		return -ENODEV;

	/*
	 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz band
	 * configurations) can be removed when those NVS files stop floating
	 * around.
	 */
	if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
	    wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
		/* for now 11a is unsupported in AP mode */
		if (wl->bss_type != BSS_TYPE_AP_BSS &&
		    wl->nvs->general_params.dual_mode_select)
			wl->enable_11a = true;
	}

	if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
	    (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
	     wl->enable_11a)) {
		wl1271_error("nvs size is not as expected: %zu != %zu",
			     wl->nvs_len, sizeof(struct wl1271_nvs_file));
		kfree(wl->nvs);
		wl->nvs = NULL;
		wl->nvs_len = 0;
		return -EILSEQ;
	}

	/* only the first part of the NVS needs to be uploaded */
	nvs_len = sizeof(wl->nvs->nvs);
	nvs_ptr = (u8 *)wl->nvs->nvs;

	/* update current MAC address to NVS */
	nvs_ptr[11] = wl->mac_addr[0];
	nvs_ptr[10] = wl->mac_addr[1];
	nvs_ptr[6] = wl->mac_addr[2];
	nvs_ptr[5] = wl->mac_addr[3];
	nvs_ptr[4] = wl->mac_addr[4];
	nvs_ptr[3] = wl->mac_addr[5];

	/*
	 * Layout before the actual NVS tables:
	 * 1 byte : burst length.
	 * 2 bytes: destination address.
	 * n bytes: data to burst copy.
	 *
	 * This is ended by a 0 length, then the NVS tables.
	 */

	/* FIXME: Do we need to check here whether the LSB is 1? */
	while (nvs_ptr[0]) {
		burst_len = nvs_ptr[0];
		dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));

		/*
		 * Due to our new wl1271_translate_reg_addr function,
		 * we need to add the REGISTER_BASE to the destination
		 */
		dest_addr += REGISTERS_BASE;

		/* We move our pointer to the data */
		nvs_ptr += 3;

		for (i = 0; i < burst_len; i++) {
			val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
			       | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));

			wl1271_debug(DEBUG_BOOT,
				     "nvs burst write 0x%x: 0x%x",
				     dest_addr, val);
			wl1271_write32(wl, dest_addr, val);

			nvs_ptr += 4;
			dest_addr += 4;
		}
	}

	/*
	 * We've reached the first zero length, the first NVS table
	 * is located at an aligned offset which is at least 7 bytes further.
	 */
	nvs_ptr = (u8 *)wl->nvs->nvs +
			ALIGN(nvs_ptr - (u8 *)wl->nvs->nvs + 7, 4);
	nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;

	/* Now we must set the partition correctly */
	wl1271_set_partition(wl, &part_table[PART_WORK]);

	/* Copy the NVS tables to a new block to ensure alignment */
	nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
	if (!nvs_aligned)
		return -ENOMEM;

	/* And finally we upload the NVS tables */
	wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);

	kfree(nvs_aligned);
	return 0;
}

static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
{
	wl1271_enable_interrupts(wl);
	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
		       WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
	wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
}

static int wl1271_boot_soft_reset(struct wl1271 *wl)
{
	unsigned long timeout;
	u32 boot_data;

	/* perform soft reset */
	wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);

	/* SOFT_RESET is self clearing */
	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	while (1) {
		boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
		wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
		if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
			break;

		if (time_after(jiffies, timeout)) {
			/* 1.2 check pWhalBus->uSelfClearTime if the
			 * timeout was reached */
			wl1271_error("soft reset timeout");
			return -1;
		}

		udelay(SOFT_RESET_STALL_TIME);
	}

	/* disable Rx/Tx */
	wl1271_write32(wl, ENABLE, 0x0);

	/* disable auto calibration on start*/
	wl1271_write32(wl, SPARE_A2, 0xffff);

	return 0;
}

static int wl1271_boot_run_firmware(struct wl1271 *wl)
{
	int loop, ret;
	u32 chip_id, intr;

	wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);

	chip_id = wl1271_read32(wl, CHIP_ID_B);

	wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);

	if (chip_id != wl->chip.id) {
		wl1271_error("chip id doesn't match after firmware boot");
		return -EIO;
	}

	/* wait for init to complete */
	loop = 0;
	while (loop++ < INIT_LOOP) {
		udelay(INIT_LOOP_DELAY);
		intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);

		if (intr == 0xffffffff) {
			wl1271_error("error reading hardware complete "
				     "init indication");
			return -EIO;
		}
		/* check that ACX_INTR_INIT_COMPLETE is enabled */
		else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
			wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
				       WL1271_ACX_INTR_INIT_COMPLETE);
			break;
		}
	}

	if (loop > INIT_LOOP) {
		wl1271_error("timeout waiting for the hardware to "
			     "complete initialization");
		return -EIO;
	}

	/* get hardware config command mail box */
	wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);

	/* get hardware config event mail box */
	wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);

	/* set the working partition to its "running" mode offset */
	wl1271_set_partition(wl, &part_table[PART_WORK]);

	wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
		     wl->cmd_box_addr, wl->event_box_addr);

	wl1271_boot_fw_version(wl);

	/*
	 * in case of full asynchronous mode the firmware event must be
	 * ready to receive event from the command mailbox
	 */

	/* unmask required mbox events  */
	wl->event_mask = BSS_LOSE_EVENT_ID |
		SCAN_COMPLETE_EVENT_ID |
		PS_REPORT_EVENT_ID |
		JOIN_EVENT_COMPLETE_ID |
		DISCONNECT_EVENT_COMPLETE_ID |
		RSSI_SNR_TRIGGER_0_EVENT_ID |
		PSPOLL_DELIVERY_FAILURE_EVENT_ID |
		SOFT_GEMINI_SENSE_EVENT_ID;

	if (wl->bss_type == BSS_TYPE_AP_BSS)
		wl->event_mask |= STA_REMOVE_COMPLETE_EVENT_ID;

	ret = wl1271_event_unmask(wl);
	if (ret < 0) {
		wl1271_error("EVENT mask setting failed");
		return ret;
	}

	wl1271_event_mbox_config(wl);

	/* firmware startup completed */
	return 0;
}

static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
{
	u32 polarity;

	polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);

	/* We use HIGH polarity, so unset the LOW bit */
	polarity &= ~POLARITY_LOW;
	wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);

	return 0;
}

static void wl1271_boot_hw_version(struct wl1271 *wl)
{
	u32 fuse;

	fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
	fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;

	wl->hw_pg_ver = (s8)fuse;

	if (((wl->hw_pg_ver & PG_MAJOR_VER_MASK) >> PG_MAJOR_VER_OFFSET) < 3)
		wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION;
}

/* uploads NVS and firmware */
int wl1271_load_firmware(struct wl1271 *wl)
{
	int ret = 0;
	u32 tmp, clk, pause;

	wl1271_boot_hw_version(wl);

	if (wl->ref_clock == 0 || wl->ref_clock == 2 || wl->ref_clock == 4)
		/* ref clk: 19.2/38.4/38.4-XTAL */
		clk = 0x3;
	else if (wl->ref_clock == 1 || wl->ref_clock == 3)
		/* ref clk: 26/52 */
		clk = 0x5;
	else
		return -EINVAL;

	if (wl->ref_clock != 0) {
		u16 val;
		/* Set clock type (open drain) */
		val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
		val &= FREF_CLK_TYPE_BITS;
		wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);

		/* Set clock pull mode (no pull) */
		val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
		val |= NO_PULL;
		wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
	} else {
		u16 val;
		/* Set clock polarity */
		val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
		val &= FREF_CLK_POLARITY_BITS;
		val |= CLK_REQ_OUTN_SEL;
		wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
	}

	wl1271_write32(wl, PLL_PARAMETERS, clk);

	pause = wl1271_read32(wl, PLL_PARAMETERS);

	wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);

	pause &= ~(WU_COUNTER_PAUSE_VAL);
	pause |= WU_COUNTER_PAUSE_VAL;
	wl1271_write32(wl, WU_COUNTER_PAUSE, pause);

	/* Continue the ELP wake up sequence */
	wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
	udelay(500);

	wl1271_set_partition(wl, &part_table[PART_DRPW]);

	/* Read-modify-write DRPW_SCRATCH_START register (see next state)
	   to be used by DRPw FW. The RTRIM value will be added by the FW
	   before taking DRPw out of reset */

	wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
	clk = wl1271_read32(wl, DRPW_SCRATCH_START);

	wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);

	clk |= (wl->ref_clock << 1) << 4;
	wl1271_write32(wl, DRPW_SCRATCH_START, clk);

	wl1271_set_partition(wl, &part_table[PART_WORK]);

	/* Disable interrupts */
	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);

	ret = wl1271_boot_soft_reset(wl);
	if (ret < 0)
		goto out;

	/* 2. start processing NVS file */
	ret = wl1271_boot_upload_nvs(wl);
	if (ret < 0)
		goto out;

	/* write firmware's last address (ie. it's length) to
	 * ACX_EEPROMLESS_IND_REG */
	wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");

	wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);

	tmp = wl1271_read32(wl, CHIP_ID_B);

	wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);

	/* 6. read the EEPROM parameters */
	tmp = wl1271_read32(wl, SCR_PAD2);

	ret = wl1271_boot_write_irq_polarity(wl);
	if (ret < 0)
		goto out;

	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
		       WL1271_ACX_ALL_EVENTS_VECTOR);

	/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
	 * to upload_fw) */

	ret = wl1271_boot_upload_firmware(wl);
	if (ret < 0)
		goto out;

out:
	return ret;
}
EXPORT_SYMBOL_GPL(wl1271_load_firmware);

int wl1271_boot(struct wl1271 *wl)
{
	int ret;

	/* upload NVS and firmware */
	ret = wl1271_load_firmware(wl);
	if (ret)
		return ret;

	/* 10.5 start firmware */
	ret = wl1271_boot_run_firmware(wl);
	if (ret < 0)
		goto out;

	/* Enable firmware interrupts now */
	wl1271_boot_enable_interrupts(wl);

	/* set the wl1271 default filters */
	wl1271_set_default_filters(wl);

	wl1271_event_mbox_config(wl);

out:
	return ret;
}
Commit	Line	Data
f5fc0f86 LC	1	/*
	2	* This file is part of wl1271
	3	*
2f826f55	4	* Copyright (C) 2008-2010 Nokia Corporation
f5fc0f86 LC	5	*
	6	* Contact: Luciano Coelho <luciano.coelho@nokia.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*
	22	*/
	23
5a0e3ad6	24	#include <linux/slab.h>
f5fc0f86	25
00d20100 SL	26	#include "acx.h"
	27	#include "reg.h"
	28	#include "boot.h"
	29	#include "io.h"
	30	#include "event.h"
ae113b57	31	#include "rx.h"
f5fc0f86 LC	32
	33	static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
	34	[PART_DOWN] = {
	35	.mem = {
	36	.start = 0x00000000,
	37	.size = 0x000177c0
	38	},
	39	.reg = {
	40	.start = REGISTERS_BASE,
	41	.size = 0x00008800
	42	},
451de97a JO	43	.mem2 = {
	44	.start = 0x00000000,
	45	.size = 0x00000000
	46	},
	47	.mem3 = {
	48	.start = 0x00000000,
	49	.size = 0x00000000
	50	},
f5fc0f86 LC	51	},
	52
	53	[PART_WORK] = {
	54	.mem = {
	55	.start = 0x00040000,
	56	.size = 0x00014fc0
	57	},
	58	.reg = {
	59	.start = REGISTERS_BASE,
451de97a JO	60	.size = 0x0000a000
	61	},
	62	.mem2 = {
	63	.start = 0x003004f8,
	64	.size = 0x00000004
	65	},
	66	.mem3 = {
	67	.start = 0x00040404,
	68	.size = 0x00000000
f5fc0f86 LC	69	},
	70	},
	71
	72	[PART_DRPW] = {
	73	.mem = {
	74	.start = 0x00040000,
	75	.size = 0x00014fc0
	76	},
	77	.reg = {
	78	.start = DRPW_BASE,
	79	.size = 0x00006000
451de97a JO	80	},
	81	.mem2 = {
	82	.start = 0x00000000,
	83	.size = 0x00000000
	84	},
	85	.mem3 = {
	86	.start = 0x00000000,
	87	.size = 0x00000000
f5fc0f86 LC	88	}
	89	}
	90	};
	91
	92	static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
	93	{
	94	u32 cpu_ctrl;
	95
	96	/* 10.5.0 run the firmware (I) */
7b048c52	97	cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
f5fc0f86 LC	98
	99	/* 10.5.1 run the firmware (II) */
	100	cpu_ctrl \|= flag;
7b048c52	101	wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
f5fc0f86 LC	102	}
f5fc0f86 LC	103
4b7fac77 LS	104	static void wl1271_parse_fw_ver(struct wl1271 *wl)
	105	{
	106	int ret;
	107
	108	ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
	109	&wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
	110	&wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
	111	&wl->chip.fw_ver[4]);
	112
	113	if (ret != 5) {
	114	wl1271_warning("fw version incorrect value");
	115	memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
	116	return;
	117	}
	118	}
	119
f5fc0f86 LC	120	static void wl1271_boot_fw_version(struct wl1271 *wl)
	121	{
	122	struct wl1271_static_data static_data;
	123
7b048c52 TP	124	wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
7b048c52 TP	125	false);
f5fc0f86	126
4b7fac77 LS	127	strncpy(wl->chip.fw_ver_str, static_data.fw_version,
4b7fac77 LS	128	sizeof(wl->chip.fw_ver_str));
f5fc0f86 LC	129
f5fc0f86 LC	130	/* make sure the string is NULL-terminated */
4b7fac77 LS	131	wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
	132
	133	wl1271_parse_fw_ver(wl);
f5fc0f86 LC	134	}
	135
	136	static int wl1271_boot_upload_firmware_chunk(struct wl1271 wl, void buf,
	137	size_t fw_data_len, u32 dest)
	138	{
451de97a	139	struct wl1271_partition_set partition;
f5fc0f86	140	int addr, chunk_num, partition_limit;
1fba4974	141	u8 p, chunk;
f5fc0f86 LC	142
	143	/* whal_FwCtrl_LoadFwImageSm() */
	144
	145	wl1271_debug(DEBUG_BOOT, "starting firmware upload");
	146
73d0a13c LC	147	wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
73d0a13c LC	148	fw_data_len, CHUNK_SIZE);
f5fc0f86	149
f5fc0f86 LC	150	if ((fw_data_len % 4) != 0) {
	151	wl1271_error("firmware length not multiple of four");
	152	return -EIO;
	153	}
	154
1fba4974	155	chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
ed317788	156	if (!chunk) {
1fba4974 JO	157	wl1271_error("allocation for firmware upload chunk failed");
	158	return -ENOMEM;
	159	}
	160
451de97a JO	161	memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
	162	partition.mem.start = dest;
	163	wl1271_set_partition(wl, &partition);
f5fc0f86 LC	164
	165	/* 10.1 set partition limit and chunk num */
	166	chunk_num = 0;
	167	partition_limit = part_table[PART_DOWN].mem.size;
	168
	169	while (chunk_num < fw_data_len / CHUNK_SIZE) {
	170	/* 10.2 update partition, if needed */
	171	addr = dest + (chunk_num + 2) * CHUNK_SIZE;
	172	if (addr > partition_limit) {
	173	addr = dest + chunk_num * CHUNK_SIZE;
	174	partition_limit = chunk_num * CHUNK_SIZE +
	175	part_table[PART_DOWN].mem.size;
451de97a JO	176	partition.mem.start = addr;
451de97a JO	177	wl1271_set_partition(wl, &partition);
f5fc0f86 LC	178	}
	179
	180	/* 10.3 upload the chunk */
	181	addr = dest + chunk_num * CHUNK_SIZE;
	182	p = buf + chunk_num * CHUNK_SIZE;
1fba4974	183	memcpy(chunk, p, CHUNK_SIZE);
f5fc0f86 LC	184	wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
f5fc0f86 LC	185	p, addr);
7b048c52	186	wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
f5fc0f86 LC	187
	188	chunk_num++;
	189	}
	190
	191	/* 10.4 upload the last chunk */
	192	addr = dest + chunk_num * CHUNK_SIZE;
	193	p = buf + chunk_num * CHUNK_SIZE;
1fba4974	194	memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
73d0a13c	195	wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
f5fc0f86	196	fw_data_len % CHUNK_SIZE, p, addr);
7b048c52	197	wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
f5fc0f86	198
1fba4974	199	kfree(chunk);
f5fc0f86 LC	200	return 0;
	201	}
	202
	203	static int wl1271_boot_upload_firmware(struct wl1271 *wl)
	204	{
	205	u32 chunks, addr, len;
ed317788	206	int ret = 0;
f5fc0f86 LC	207	u8 *fw;
	208
	209	fw = wl->fw;
d0f63b20	210	chunks = be32_to_cpup((__be32 *) fw);
f5fc0f86 LC	211	fw += sizeof(u32);
	212
	213	wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
	214
	215	while (chunks--) {
d0f63b20	216	addr = be32_to_cpup((__be32 *) fw);
f5fc0f86	217	fw += sizeof(u32);
d0f63b20	218	len = be32_to_cpup((__be32 *) fw);
f5fc0f86 LC	219	fw += sizeof(u32);
	220
	221	if (len > 300000) {
	222	wl1271_info("firmware chunk too long: %u", len);
	223	return -EINVAL;
	224	}
	225	wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
	226	chunks, addr, len);
ed317788 JO	227	ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
	228	if (ret != 0)
	229	break;
f5fc0f86 LC	230	fw += len;
	231	}
	232
ed317788	233	return ret;
f5fc0f86 LC	234	}
	235
	236	static int wl1271_boot_upload_nvs(struct wl1271 *wl)
	237	{
	238	size_t nvs_len, burst_len;
	239	int i;
	240	u32 dest_addr, val;
152ee6e0	241	u8 nvs_ptr, nvs_aligned;
f5fc0f86	242
152ee6e0	243	if (wl->nvs == NULL)
f5fc0f86 LC	244	return -ENODEV;
f5fc0f86 LC	245
02fabb0e JO	246	/*
	247	* FIXME: the LEGACY NVS image support (NVS's missing the 5GHz band
	248	* configurations) can be removed when those NVS files stop floating
	249	* around.
	250	*/
	251	if (wl->nvs_len == sizeof(struct wl1271_nvs_file) \|\|
	252	wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
038d925b AN	253	/* for now 11a is unsupported in AP mode */
	254	if (wl->bss_type != BSS_TYPE_AP_BSS &&
	255	wl->nvs->general_params.dual_mode_select)
02fabb0e JO	256	wl->enable_11a = true;
	257	}
	258
	259	if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
	260	(wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE \|\|
	261	wl->enable_11a)) {
	262	wl1271_error("nvs size is not as expected: %zu != %zu",
	263	wl->nvs_len, sizeof(struct wl1271_nvs_file));
	264	kfree(wl->nvs);
	265	wl->nvs = NULL;
	266	wl->nvs_len = 0;
	267	return -EILSEQ;
	268	}
	269
8cf5e8e5	270	/* only the first part of the NVS needs to be uploaded */
152ee6e0 JO	271	nvs_len = sizeof(wl->nvs->nvs);
152ee6e0 JO	272	nvs_ptr = (u8 *)wl->nvs->nvs;
f5fc0f86	273
1b72aecd JO	274	/* update current MAC address to NVS */
	275	nvs_ptr[11] = wl->mac_addr[0];
	276	nvs_ptr[10] = wl->mac_addr[1];
	277	nvs_ptr[6] = wl->mac_addr[2];
	278	nvs_ptr[5] = wl->mac_addr[3];
	279	nvs_ptr[4] = wl->mac_addr[4];
	280	nvs_ptr[3] = wl->mac_addr[5];
	281
f5fc0f86 LC	282	/*
	283	* Layout before the actual NVS tables:
	284	* 1 byte : burst length.
	285	* 2 bytes: destination address.
	286	* n bytes: data to burst copy.
	287	*
	288	* This is ended by a 0 length, then the NVS tables.
	289	*/
	290
	291	/* FIXME: Do we need to check here whether the LSB is 1? */
	292	while (nvs_ptr[0]) {
	293	burst_len = nvs_ptr[0];
	294	dest_addr = (nvs_ptr[1] & 0xfe) \| ((u32)(nvs_ptr[2] << 8));
	295
2f63b011 JO	296	/*
	297	* Due to our new wl1271_translate_reg_addr function,
	298	* we need to add the REGISTER_BASE to the destination
	299	*/
f5fc0f86 LC	300	dest_addr += REGISTERS_BASE;
	301
	302	/* We move our pointer to the data */
	303	nvs_ptr += 3;
	304
	305	for (i = 0; i < burst_len; i++) {
	306	val = (nvs_ptr[0] \| (nvs_ptr[1] << 8)
	307	\| (nvs_ptr[2] << 16) \| (nvs_ptr[3] << 24));
	308
	309	wl1271_debug(DEBUG_BOOT,
	310	"nvs burst write 0x%x: 0x%x",
	311	dest_addr, val);
7b048c52	312	wl1271_write32(wl, dest_addr, val);
f5fc0f86 LC	313
	314	nvs_ptr += 4;
	315	dest_addr += 4;
	316	}
	317	}
	318
	319	/*
	320	* We've reached the first zero length, the first NVS table
67e0208a	321	* is located at an aligned offset which is at least 7 bytes further.
f5fc0f86	322	*/
67e0208a IY	323	nvs_ptr = (u8 *)wl->nvs->nvs +
67e0208a IY	324	ALIGN(nvs_ptr - (u8 *)wl->nvs->nvs + 7, 4);
152ee6e0	325	nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
f5fc0f86	326
f5fc0f86	327	/* Now we must set the partition correctly */
451de97a	328	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	329
f5fc0f86 LC	330	/* Copy the NVS tables to a new block to ensure alignment */
67e0208a IY	331	nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
	332	if (!nvs_aligned)
	333	return -ENOMEM;
f5fc0f86 LC	334
f5fc0f86 LC	335	/* And finally we upload the NVS tables */
7b048c52	336	wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
f5fc0f86 LC	337
	338	kfree(nvs_aligned);
	339	return 0;
	340	}
	341
	342	static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
	343	{
54f7e503	344	wl1271_enable_interrupts(wl);
7b048c52 TP	345	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
	346	WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
	347	wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
f5fc0f86 LC	348	}
	349
	350	static int wl1271_boot_soft_reset(struct wl1271 *wl)
	351	{
	352	unsigned long timeout;
	353	u32 boot_data;
	354
	355	/* perform soft reset */
7b048c52	356	wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
f5fc0f86 LC	357
	358	/* SOFT_RESET is self clearing */
	359	timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
	360	while (1) {
7b048c52	361	boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
f5fc0f86 LC	362	wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
	363	if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
	364	break;
	365
	366	if (time_after(jiffies, timeout)) {
	367	/* 1.2 check pWhalBus->uSelfClearTime if the
	368	* timeout was reached */
	369	wl1271_error("soft reset timeout");
	370	return -1;
	371	}
	372
	373	udelay(SOFT_RESET_STALL_TIME);
	374	}
	375
	376	/* disable Rx/Tx */
7b048c52	377	wl1271_write32(wl, ENABLE, 0x0);
f5fc0f86 LC	378
f5fc0f86 LC	379	/* disable auto calibration on start*/
7b048c52	380	wl1271_write32(wl, SPARE_A2, 0xffff);
f5fc0f86 LC	381
	382	return 0;
	383	}
	384
	385	static int wl1271_boot_run_firmware(struct wl1271 *wl)
	386	{
	387	int loop, ret;
23a7a51c	388	u32 chip_id, intr;
f5fc0f86 LC	389
	390	wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
	391
7b048c52	392	chip_id = wl1271_read32(wl, CHIP_ID_B);
f5fc0f86 LC	393
	394	wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
	395
	396	if (chip_id != wl->chip.id) {
	397	wl1271_error("chip id doesn't match after firmware boot");
	398	return -EIO;
	399	}
	400
	401	/* wait for init to complete */
	402	loop = 0;
	403	while (loop++ < INIT_LOOP) {
	404	udelay(INIT_LOOP_DELAY);
23a7a51c	405	intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
f5fc0f86	406
23a7a51c	407	if (intr == 0xffffffff) {
f5fc0f86 LC	408	wl1271_error("error reading hardware complete "
	409	"init indication");
	410	return -EIO;
	411	}
	412	/* check that ACX_INTR_INIT_COMPLETE is enabled */
23a7a51c	413	else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
7b048c52 TP	414	wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
7b048c52 TP	415	WL1271_ACX_INTR_INIT_COMPLETE);
f5fc0f86 LC	416	break;
	417	}
	418	}
	419
e7d17cf4	420	if (loop > INIT_LOOP) {
f5fc0f86 LC	421	wl1271_error("timeout waiting for the hardware to "
	422	"complete initialization");
	423	return -EIO;
	424	}
	425
	426	/* get hardware config command mail box */
7b048c52	427	wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
f5fc0f86 LC	428
f5fc0f86 LC	429	/* get hardware config event mail box */
7b048c52	430	wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
f5fc0f86 LC	431
f5fc0f86 LC	432	/* set the working partition to its "running" mode offset */
451de97a	433	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	434
	435	wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
	436	wl->cmd_box_addr, wl->event_box_addr);
	437
	438	wl1271_boot_fw_version(wl);
	439
	440	/*
	441	* in case of full asynchronous mode the firmware event must be
	442	* ready to receive event from the command mailbox
	443	*/
	444
be823e5b JO	445	/* unmask required mbox events */
be823e5b JO	446	wl->event_mask = BSS_LOSE_EVENT_ID \|
19ad0715	447	SCAN_COMPLETE_EVENT_ID \|
99d84c1d	448	PS_REPORT_EVENT_ID \|
2f826f55	449	JOIN_EVENT_COMPLETE_ID \|
00236aed	450	DISCONNECT_EVENT_COMPLETE_ID \|
90494a90	451	RSSI_SNR_TRIGGER_0_EVENT_ID \|
8d2ef7bd JO	452	PSPOLL_DELIVERY_FAILURE_EVENT_ID \|
8d2ef7bd JO	453	SOFT_GEMINI_SENSE_EVENT_ID;
f5fc0f86	454
203c903c AN	455	if (wl->bss_type == BSS_TYPE_AP_BSS)
	456	wl->event_mask \|= STA_REMOVE_COMPLETE_EVENT_ID;
	457
f5fc0f86 LC	458	ret = wl1271_event_unmask(wl);
	459	if (ret < 0) {
	460	wl1271_error("EVENT mask setting failed");
	461	return ret;
	462	}
	463
	464	wl1271_event_mbox_config(wl);
	465
	466	/* firmware startup completed */
	467	return 0;
	468	}
	469
	470	static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
	471	{
e8768eeb	472	u32 polarity;
f5fc0f86	473
e8768eeb	474	polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
f5fc0f86 LC	475
	476	/* We use HIGH polarity, so unset the LOW bit */
	477	polarity &= ~POLARITY_LOW;
e8768eeb	478	wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
f5fc0f86 LC	479
	480	return 0;
	481	}
	482
d717fd61 JO	483	static void wl1271_boot_hw_version(struct wl1271 *wl)
	484	{
	485	u32 fuse;
	486
	487	fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
	488	fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
	489
	490	wl->hw_pg_ver = (s8)fuse;
606ea9fa IY	491
	492	if (((wl->hw_pg_ver & PG_MAJOR_VER_MASK) >> PG_MAJOR_VER_OFFSET) < 3)
	493	wl->quirks \|= WL12XX_QUIRK_END_OF_TRANSACTION;
d717fd61 JO	494	}
d717fd61 JO	495
870c367c RQ	496	/* uploads NVS and firmware */
870c367c RQ	497	int wl1271_load_firmware(struct wl1271 *wl)
f5fc0f86 LC	498	{
	499	int ret = 0;
	500	u32 tmp, clk, pause;
	501
d717fd61 JO	502	wl1271_boot_hw_version(wl);
d717fd61 JO	503
c8aea565	504	if (wl->ref_clock == 0 \|\| wl->ref_clock == 2 \|\| wl->ref_clock == 4)
284134eb	505	/* ref clk: 19.2/38.4/38.4-XTAL */
f5fc0f86	506	clk = 0x3;
c8aea565	507	else if (wl->ref_clock == 1 \|\| wl->ref_clock == 3)
f5fc0f86 LC	508	/* ref clk: 26/52 */
f5fc0f86 LC	509	clk = 0x5;
15cea993 OBC	510	else
15cea993 OBC	511	return -EINVAL;
f5fc0f86	512
c8aea565	513	if (wl->ref_clock != 0) {
284134eb	514	u16 val;
9d4e5bb3	515	/* Set clock type (open drain) */
284134eb JO	516	val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
284134eb JO	517	val &= FREF_CLK_TYPE_BITS;
284134eb	518	wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
9d4e5bb3 JO	519
	520	/* Set clock pull mode (no pull) */
	521	val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
	522	val \|= NO_PULL;
	523	wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
284134eb JO	524	} else {
	525	u16 val;
	526	/* Set clock polarity */
	527	val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
	528	val &= FREF_CLK_POLARITY_BITS;
	529	val \|= CLK_REQ_OUTN_SEL;
	530	wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
	531	}
	532
7b048c52	533	wl1271_write32(wl, PLL_PARAMETERS, clk);
f5fc0f86	534
7b048c52	535	pause = wl1271_read32(wl, PLL_PARAMETERS);
f5fc0f86 LC	536
	537	wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
	538
2f63b011	539	pause &= ~(WU_COUNTER_PAUSE_VAL);
f5fc0f86	540	pause \|= WU_COUNTER_PAUSE_VAL;
7b048c52	541	wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
f5fc0f86 LC	542
f5fc0f86 LC	543	/* Continue the ELP wake up sequence */
7b048c52	544	wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
f5fc0f86 LC	545	udelay(500);
f5fc0f86 LC	546
451de97a	547	wl1271_set_partition(wl, &part_table[PART_DRPW]);
f5fc0f86 LC	548
	549	/* Read-modify-write DRPW_SCRATCH_START register (see next state)
	550	to be used by DRPw FW. The RTRIM value will be added by the FW
	551	before taking DRPw out of reset */
	552
	553	wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
7b048c52	554	clk = wl1271_read32(wl, DRPW_SCRATCH_START);
f5fc0f86 LC	555
	556	wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
	557
c8aea565	558	clk \|= (wl->ref_clock << 1) << 4;
7b048c52	559	wl1271_write32(wl, DRPW_SCRATCH_START, clk);
f5fc0f86	560
451de97a	561	wl1271_set_partition(wl, &part_table[PART_WORK]);
f5fc0f86 LC	562
f5fc0f86 LC	563	/* Disable interrupts */
7b048c52	564	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
f5fc0f86 LC	565
	566	ret = wl1271_boot_soft_reset(wl);
	567	if (ret < 0)
	568	goto out;
	569
	570	/* 2. start processing NVS file */
	571	ret = wl1271_boot_upload_nvs(wl);
	572	if (ret < 0)
	573	goto out;
	574
	575	/* write firmware's last address (ie. it's length) to
	576	* ACX_EEPROMLESS_IND_REG */
	577	wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
	578
7b048c52	579	wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
f5fc0f86	580
7b048c52	581	tmp = wl1271_read32(wl, CHIP_ID_B);
f5fc0f86 LC	582
	583	wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
	584
	585	/* 6. read the EEPROM parameters */
7b048c52	586	tmp = wl1271_read32(wl, SCR_PAD2);
f5fc0f86 LC	587
	588	ret = wl1271_boot_write_irq_polarity(wl);
	589	if (ret < 0)
	590	goto out;
	591
7b048c52 TP	592	wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
7b048c52 TP	593	WL1271_ACX_ALL_EVENTS_VECTOR);
f5fc0f86 LC	594
	595	/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
	596	* to upload_fw) */
	597
	598	ret = wl1271_boot_upload_firmware(wl);
	599	if (ret < 0)
	600	goto out;
	601
870c367c RQ	602	out:
	603	return ret;
	604	}
	605	EXPORT_SYMBOL_GPL(wl1271_load_firmware);
	606
	607	int wl1271_boot(struct wl1271 *wl)
	608	{
	609	int ret;
	610
	611	/* upload NVS and firmware */
	612	ret = wl1271_load_firmware(wl);
	613	if (ret)
	614	return ret;
	615
f5fc0f86 LC	616	/* 10.5 start firmware */
	617	ret = wl1271_boot_run_firmware(wl);
	618	if (ret < 0)
	619	goto out;
	620
eb5b28d0 JO	621	/* Enable firmware interrupts now */
	622	wl1271_boot_enable_interrupts(wl);
	623
f5fc0f86	624	/* set the wl1271 default filters */
ae113b57	625	wl1271_set_default_filters(wl);
f5fc0f86 LC	626
	627	wl1271_event_mbox_config(wl);
	628
	629	out:
	630	return ret;
	631	}