Commit | Line | Data |
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f5fc0f86 LC |
1 | /* |
2 | * This file is part of wl1271 | |
3 | * | |
4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
1937e742 | 5 | * Copyright (C) 2008-2010 Nokia Corporation |
f5fc0f86 LC |
6 | * |
7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
00d20100 SL |
25 | #ifndef __ACX_H__ |
26 | #define __ACX_H__ | |
f5fc0f86 | 27 | |
00d20100 SL |
28 | #include "wl12xx.h" |
29 | #include "cmd.h" | |
f5fc0f86 LC |
30 | |
31 | /************************************************************************* | |
32 | ||
33 | Host Interrupt Register (WiLink -> Host) | |
34 | ||
35 | **************************************************************************/ | |
36 | /* HW Initiated interrupt Watchdog timer expiration */ | |
37 | #define WL1271_ACX_INTR_WATCHDOG BIT(0) | |
38 | /* Init sequence is done (masked interrupt, detection through polling only ) */ | |
39 | #define WL1271_ACX_INTR_INIT_COMPLETE BIT(1) | |
40 | /* Event was entered to Event MBOX #A*/ | |
41 | #define WL1271_ACX_INTR_EVENT_A BIT(2) | |
42 | /* Event was entered to Event MBOX #B*/ | |
43 | #define WL1271_ACX_INTR_EVENT_B BIT(3) | |
44 | /* Command processing completion*/ | |
45 | #define WL1271_ACX_INTR_CMD_COMPLETE BIT(4) | |
46 | /* Signaling the host on HW wakeup */ | |
47 | #define WL1271_ACX_INTR_HW_AVAILABLE BIT(5) | |
48 | /* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */ | |
49 | #define WL1271_ACX_INTR_DATA BIT(6) | |
e8a8b252 | 50 | /* Trace message on MBOX #A */ |
f5fc0f86 | 51 | #define WL1271_ACX_INTR_TRACE_A BIT(7) |
e8a8b252 | 52 | /* Trace message on MBOX #B */ |
f5fc0f86 LC |
53 | #define WL1271_ACX_INTR_TRACE_B BIT(8) |
54 | ||
55 | #define WL1271_ACX_INTR_ALL 0xFFFFFFFF | |
56 | #define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \ | |
57 | WL1271_ACX_INTR_INIT_COMPLETE | \ | |
58 | WL1271_ACX_INTR_EVENT_A | \ | |
59 | WL1271_ACX_INTR_EVENT_B | \ | |
60 | WL1271_ACX_INTR_CMD_COMPLETE | \ | |
61 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
62 | WL1271_ACX_INTR_DATA) | |
63 | ||
ccc83b04 EP |
64 | #define WL1271_INTR_MASK (WL1271_ACX_INTR_WATCHDOG | \ |
65 | WL1271_ACX_INTR_EVENT_A | \ | |
37079a83 LC |
66 | WL1271_ACX_INTR_EVENT_B | \ |
67 | WL1271_ACX_INTR_HW_AVAILABLE | \ | |
f5fc0f86 LC |
68 | WL1271_ACX_INTR_DATA) |
69 | ||
70 | /* Target's information element */ | |
71 | struct acx_header { | |
72 | struct wl1271_cmd_header cmd; | |
73 | ||
74 | /* acx (or information element) header */ | |
d0f63b20 | 75 | __le16 id; |
f5fc0f86 LC |
76 | |
77 | /* payload length (not including headers */ | |
d0f63b20 | 78 | __le16 len; |
ba2d3587 | 79 | } __packed; |
f5fc0f86 LC |
80 | |
81 | struct acx_error_counter { | |
82 | struct acx_header header; | |
83 | ||
84 | /* The number of PLCP errors since the last time this */ | |
85 | /* information element was interrogated. This field is */ | |
86 | /* automatically cleared when it is interrogated.*/ | |
d0f63b20 | 87 | __le32 PLCP_error; |
f5fc0f86 LC |
88 | |
89 | /* The number of FCS errors since the last time this */ | |
90 | /* information element was interrogated. This field is */ | |
91 | /* automatically cleared when it is interrogated.*/ | |
d0f63b20 | 92 | __le32 FCS_error; |
f5fc0f86 LC |
93 | |
94 | /* The number of MPDUs without PLCP header errors received*/ | |
95 | /* since the last time this information element was interrogated. */ | |
96 | /* This field is automatically cleared when it is interrogated.*/ | |
d0f63b20 | 97 | __le32 valid_frame; |
f5fc0f86 LC |
98 | |
99 | /* the number of missed sequence numbers in the squentially */ | |
100 | /* values of frames seq numbers */ | |
d0f63b20 | 101 | __le32 seq_num_miss; |
ba2d3587 | 102 | } __packed; |
f5fc0f86 | 103 | |
7f097988 EP |
104 | enum wl12xx_role { |
105 | WL1271_ROLE_STA = 0, | |
106 | WL1271_ROLE_IBSS, | |
107 | WL1271_ROLE_AP, | |
108 | WL1271_ROLE_DEVICE, | |
109 | WL1271_ROLE_P2P_CL, | |
110 | WL1271_ROLE_P2P_GO, | |
111 | ||
112 | WL12XX_INVALID_ROLE_TYPE = 0xff | |
113 | }; | |
114 | ||
f5fc0f86 LC |
115 | enum wl1271_psm_mode { |
116 | /* Active mode */ | |
117 | WL1271_PSM_CAM = 0, | |
118 | ||
119 | /* Power save mode */ | |
120 | WL1271_PSM_PS = 1, | |
121 | ||
122 | /* Extreme low power */ | |
123 | WL1271_PSM_ELP = 2, | |
124 | }; | |
125 | ||
126 | struct acx_sleep_auth { | |
127 | struct acx_header header; | |
128 | ||
129 | /* The sleep level authorization of the device. */ | |
130 | /* 0 - Always active*/ | |
131 | /* 1 - Power down mode: light / fast sleep*/ | |
132 | /* 2 - ELP mode: Deep / Max sleep*/ | |
133 | u8 sleep_auth; | |
134 | u8 padding[3]; | |
ba2d3587 | 135 | } __packed; |
f5fc0f86 LC |
136 | |
137 | enum { | |
138 | HOSTIF_PCI_MASTER_HOST_INDIRECT, | |
139 | HOSTIF_PCI_MASTER_HOST_DIRECT, | |
140 | HOSTIF_SLAVE, | |
141 | HOSTIF_PKT_RING, | |
142 | HOSTIF_DONTCARE = 0xFF | |
143 | }; | |
144 | ||
145 | #define DEFAULT_UCAST_PRIORITY 0 | |
146 | #define DEFAULT_RX_Q_PRIORITY 0 | |
f5fc0f86 LC |
147 | #define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */ |
148 | #define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */ | |
149 | #define TRACE_BUFFER_MAX_SIZE 256 | |
150 | ||
151 | #define DP_RX_PACKET_RING_CHUNK_SIZE 1600 | |
152 | #define DP_TX_PACKET_RING_CHUNK_SIZE 1600 | |
153 | #define DP_RX_PACKET_RING_CHUNK_NUM 2 | |
154 | #define DP_TX_PACKET_RING_CHUNK_NUM 2 | |
155 | #define DP_TX_COMPLETE_TIME_OUT 20 | |
f5fc0f86 LC |
156 | |
157 | #define TX_MSDU_LIFETIME_MIN 0 | |
158 | #define TX_MSDU_LIFETIME_MAX 3000 | |
159 | #define TX_MSDU_LIFETIME_DEF 512 | |
160 | #define RX_MSDU_LIFETIME_MIN 0 | |
161 | #define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF | |
162 | #define RX_MSDU_LIFETIME_DEF 512000 | |
163 | ||
164 | struct acx_rx_msdu_lifetime { | |
165 | struct acx_header header; | |
166 | ||
167 | /* | |
168 | * The maximum amount of time, in TU, before the | |
169 | * firmware discards the MSDU. | |
170 | */ | |
d0f63b20 | 171 | __le32 lifetime; |
ba2d3587 | 172 | } __packed; |
f5fc0f86 | 173 | |
f5fc0f86 LC |
174 | struct acx_packet_detection { |
175 | struct acx_header header; | |
176 | ||
d0f63b20 | 177 | __le32 threshold; |
ba2d3587 | 178 | } __packed; |
f5fc0f86 LC |
179 | |
180 | ||
181 | enum acx_slot_type { | |
182 | SLOT_TIME_LONG = 0, | |
183 | SLOT_TIME_SHORT = 1, | |
184 | DEFAULT_SLOT_TIME = SLOT_TIME_SHORT, | |
185 | MAX_SLOT_TIMES = 0xFF | |
186 | }; | |
187 | ||
188 | #define STATION_WONE_INDEX 0 | |
189 | ||
190 | struct acx_slot { | |
191 | struct acx_header header; | |
192 | ||
7f097988 | 193 | u8 role_id; |
f5fc0f86 LC |
194 | u8 wone_index; /* Reserved */ |
195 | u8 slot_time; | |
7f097988 | 196 | u8 reserved[5]; |
ba2d3587 | 197 | } __packed; |
f5fc0f86 LC |
198 | |
199 | ||
c87dec9f JO |
200 | #define ACX_MC_ADDRESS_GROUP_MAX (8) |
201 | #define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX) | |
f5fc0f86 LC |
202 | |
203 | struct acx_dot11_grp_addr_tbl { | |
204 | struct acx_header header; | |
205 | ||
7f097988 | 206 | u8 role_id; |
f5fc0f86 LC |
207 | u8 enabled; |
208 | u8 num_groups; | |
7f097988 | 209 | u8 pad[1]; |
f5fc0f86 | 210 | u8 mac_table[ADDRESS_GROUP_MAX_LEN]; |
ba2d3587 | 211 | } __packed; |
f5fc0f86 | 212 | |
f5fc0f86 LC |
213 | struct acx_rx_timeout { |
214 | struct acx_header header; | |
215 | ||
7f097988 EP |
216 | u8 role_id; |
217 | u8 reserved; | |
d0f63b20 LC |
218 | __le16 ps_poll_timeout; |
219 | __le16 upsd_timeout; | |
7f097988 | 220 | u8 padding[2]; |
ba2d3587 | 221 | } __packed; |
f5fc0f86 | 222 | |
f5fc0f86 LC |
223 | struct acx_rts_threshold { |
224 | struct acx_header header; | |
225 | ||
7f097988 EP |
226 | u8 role_id; |
227 | u8 reserved; | |
d0f63b20 | 228 | __le16 threshold; |
ba2d3587 | 229 | } __packed; |
f5fc0f86 LC |
230 | |
231 | struct acx_beacon_filter_option { | |
232 | struct acx_header header; | |
233 | ||
7f097988 | 234 | u8 role_id; |
f5fc0f86 | 235 | u8 enable; |
f5fc0f86 LC |
236 | /* |
237 | * The number of beacons without the unicast TIM | |
238 | * bit set that the firmware buffers before | |
239 | * signaling the host about ready frames. | |
240 | * When set to 0 and the filter is enabled, beacons | |
241 | * without the unicast TIM bit set are dropped. | |
242 | */ | |
243 | u8 max_num_beacons; | |
7f097988 | 244 | u8 pad[1]; |
ba2d3587 | 245 | } __packed; |
f5fc0f86 LC |
246 | |
247 | /* | |
248 | * ACXBeaconFilterEntry (not 221) | |
249 | * Byte Offset Size (Bytes) Definition | |
250 | * =========== ============ ========== | |
1937e742 | 251 | * 0 1 IE identifier |
f5fc0f86 LC |
252 | * 1 1 Treatment bit mask |
253 | * | |
254 | * ACXBeaconFilterEntry (221) | |
255 | * Byte Offset Size (Bytes) Definition | |
256 | * =========== ============ ========== | |
257 | * 0 1 IE identifier | |
258 | * 1 1 Treatment bit mask | |
259 | * 2 3 OUI | |
260 | * 5 1 Type | |
261 | * 6 2 Version | |
262 | * | |
263 | * | |
264 | * Treatment bit mask - The information element handling: | |
265 | * bit 0 - The information element is compared and transferred | |
266 | * in case of change. | |
267 | * bit 1 - The information element is transferred to the host | |
268 | * with each appearance or disappearance. | |
269 | * Note that both bits can be set at the same time. | |
270 | */ | |
271 | #define BEACON_FILTER_TABLE_MAX_IE_NUM (32) | |
272 | #define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6) | |
273 | #define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2) | |
274 | #define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6) | |
275 | #define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \ | |
276 | BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \ | |
277 | (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \ | |
278 | BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE)) | |
279 | ||
280 | struct acx_beacon_filter_ie_table { | |
281 | struct acx_header header; | |
282 | ||
7f097988 | 283 | u8 role_id; |
f5fc0f86 | 284 | u8 num_ie; |
7f097988 | 285 | u8 pad[2]; |
1937e742 | 286 | u8 table[BEACON_FILTER_TABLE_MAX_SIZE]; |
ba2d3587 | 287 | } __packed; |
f5fc0f86 | 288 | |
34415236 JO |
289 | struct acx_conn_monit_params { |
290 | struct acx_header header; | |
291 | ||
7f097988 EP |
292 | u8 role_id; |
293 | u8 padding[3]; | |
d0f63b20 LC |
294 | __le32 synch_fail_thold; /* number of beacons missed */ |
295 | __le32 bss_lose_timeout; /* number of TU's from synch fail */ | |
ba2d3587 | 296 | } __packed; |
34415236 | 297 | |
f5fc0f86 LC |
298 | struct acx_bt_wlan_coex { |
299 | struct acx_header header; | |
300 | ||
f5fc0f86 LC |
301 | u8 enable; |
302 | u8 pad[3]; | |
ba2d3587 | 303 | } __packed; |
f5fc0f86 | 304 | |
3be4112c | 305 | struct acx_bt_wlan_coex_param { |
6e92b416 LC |
306 | struct acx_header header; |
307 | ||
3be4112c | 308 | __le32 params[CONF_SG_PARAMS_MAX]; |
885c9907 | 309 | u8 param_idx; |
6e92b416 | 310 | u8 padding[3]; |
ba2d3587 | 311 | } __packed; |
6e92b416 | 312 | |
885c9907 | 313 | struct acx_dco_itrim_params { |
f5fc0f86 LC |
314 | struct acx_header header; |
315 | ||
885c9907 | 316 | u8 enable; |
2b60100b | 317 | u8 padding[3]; |
885c9907 | 318 | __le32 timeout; |
ba2d3587 | 319 | } __packed; |
f5fc0f86 | 320 | |
f5fc0f86 LC |
321 | struct acx_energy_detection { |
322 | struct acx_header header; | |
323 | ||
324 | /* The RX Clear Channel Assessment threshold in the PHY */ | |
d0f63b20 | 325 | __le16 rx_cca_threshold; |
f5fc0f86 LC |
326 | u8 tx_energy_detection; |
327 | u8 pad; | |
ba2d3587 | 328 | } __packed; |
f5fc0f86 | 329 | |
f5fc0f86 LC |
330 | struct acx_beacon_broadcast { |
331 | struct acx_header header; | |
332 | ||
7f097988 | 333 | u8 role_id; |
f5fc0f86 LC |
334 | /* Enables receiving of broadcast packets in PS mode */ |
335 | u8 rx_broadcast_in_ps; | |
336 | ||
7f097988 EP |
337 | __le16 beacon_rx_timeout; |
338 | __le16 broadcast_timeout; | |
339 | ||
f5fc0f86 LC |
340 | /* Consecutive PS Poll failures before updating the host */ |
341 | u8 ps_poll_threshold; | |
7f097988 | 342 | u8 pad[1]; |
ba2d3587 | 343 | } __packed; |
f5fc0f86 LC |
344 | |
345 | struct acx_event_mask { | |
346 | struct acx_header header; | |
347 | ||
d0f63b20 LC |
348 | __le32 event_mask; |
349 | __le32 high_event_mask; /* Unused */ | |
ba2d3587 | 350 | } __packed; |
f5fc0f86 | 351 | |
f5fc0f86 LC |
352 | #define SCAN_PASSIVE BIT(0) |
353 | #define SCAN_5GHZ_BAND BIT(1) | |
354 | #define SCAN_TRIGGERED BIT(2) | |
355 | #define SCAN_PRIORITY_HIGH BIT(3) | |
356 | ||
2b60100b JO |
357 | /* When set, disable HW encryption */ |
358 | #define DF_ENCRYPTION_DISABLE 0x01 | |
359 | #define DF_SNIFF_MODE_ENABLE 0x80 | |
360 | ||
f5fc0f86 LC |
361 | struct acx_feature_config { |
362 | struct acx_header header; | |
363 | ||
7f097988 EP |
364 | u8 role_id; |
365 | u8 padding[3]; | |
d0f63b20 LC |
366 | __le32 options; |
367 | __le32 data_flow_options; | |
ba2d3587 | 368 | } __packed; |
f5fc0f86 LC |
369 | |
370 | struct acx_current_tx_power { | |
371 | struct acx_header header; | |
372 | ||
7f097988 | 373 | u8 role_id; |
f5fc0f86 | 374 | u8 current_tx_power; |
7f097988 | 375 | u8 padding[2]; |
ba2d3587 | 376 | } __packed; |
f5fc0f86 | 377 | |
f5fc0f86 LC |
378 | struct acx_wake_up_condition { |
379 | struct acx_header header; | |
380 | ||
7f097988 | 381 | u8 role_id; |
f5fc0f86 LC |
382 | u8 wake_up_event; /* Only one bit can be set */ |
383 | u8 listen_interval; | |
7f097988 | 384 | u8 pad[1]; |
ba2d3587 | 385 | } __packed; |
f5fc0f86 LC |
386 | |
387 | struct acx_aid { | |
388 | struct acx_header header; | |
389 | ||
390 | /* | |
391 | * To be set when associated with an AP. | |
392 | */ | |
7f097988 EP |
393 | u8 role_id; |
394 | u8 reserved; | |
d0f63b20 | 395 | __le16 aid; |
ba2d3587 | 396 | } __packed; |
f5fc0f86 LC |
397 | |
398 | enum acx_preamble_type { | |
399 | ACX_PREAMBLE_LONG = 0, | |
400 | ACX_PREAMBLE_SHORT = 1 | |
401 | }; | |
402 | ||
403 | struct acx_preamble { | |
404 | struct acx_header header; | |
405 | ||
406 | /* | |
407 | * When set, the WiLink transmits the frames with a short preamble and | |
408 | * when cleared, the WiLink transmits the frames with a long preamble. | |
409 | */ | |
7f097988 | 410 | u8 role_id; |
f5fc0f86 | 411 | u8 preamble; |
7f097988 | 412 | u8 padding[2]; |
ba2d3587 | 413 | } __packed; |
f5fc0f86 LC |
414 | |
415 | enum acx_ctsprotect_type { | |
416 | CTSPROTECT_DISABLE = 0, | |
417 | CTSPROTECT_ENABLE = 1 | |
418 | }; | |
419 | ||
420 | struct acx_ctsprotect { | |
421 | struct acx_header header; | |
7f097988 | 422 | u8 role_id; |
f5fc0f86 | 423 | u8 ctsprotect; |
7f097988 | 424 | u8 padding[2]; |
ba2d3587 | 425 | } __packed; |
f5fc0f86 LC |
426 | |
427 | struct acx_tx_statistics { | |
d0f63b20 | 428 | __le32 internal_desc_overflow; |
ba2d3587 | 429 | } __packed; |
f5fc0f86 LC |
430 | |
431 | struct acx_rx_statistics { | |
d0f63b20 LC |
432 | __le32 out_of_mem; |
433 | __le32 hdr_overflow; | |
434 | __le32 hw_stuck; | |
435 | __le32 dropped; | |
436 | __le32 fcs_err; | |
437 | __le32 xfr_hint_trig; | |
438 | __le32 path_reset; | |
439 | __le32 reset_counter; | |
ba2d3587 | 440 | } __packed; |
f5fc0f86 LC |
441 | |
442 | struct acx_dma_statistics { | |
d0f63b20 LC |
443 | __le32 rx_requested; |
444 | __le32 rx_errors; | |
445 | __le32 tx_requested; | |
446 | __le32 tx_errors; | |
ba2d3587 | 447 | } __packed; |
f5fc0f86 LC |
448 | |
449 | struct acx_isr_statistics { | |
450 | /* host command complete */ | |
d0f63b20 | 451 | __le32 cmd_cmplt; |
f5fc0f86 LC |
452 | |
453 | /* fiqisr() */ | |
d0f63b20 | 454 | __le32 fiqs; |
f5fc0f86 LC |
455 | |
456 | /* (INT_STS_ND & INT_TRIG_RX_HEADER) */ | |
d0f63b20 | 457 | __le32 rx_headers; |
f5fc0f86 LC |
458 | |
459 | /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */ | |
d0f63b20 | 460 | __le32 rx_completes; |
f5fc0f86 LC |
461 | |
462 | /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */ | |
d0f63b20 | 463 | __le32 rx_mem_overflow; |
f5fc0f86 LC |
464 | |
465 | /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */ | |
d0f63b20 | 466 | __le32 rx_rdys; |
f5fc0f86 LC |
467 | |
468 | /* irqisr() */ | |
d0f63b20 | 469 | __le32 irqs; |
f5fc0f86 LC |
470 | |
471 | /* (INT_STS_ND & INT_TRIG_TX_PROC) */ | |
d0f63b20 | 472 | __le32 tx_procs; |
f5fc0f86 LC |
473 | |
474 | /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */ | |
d0f63b20 | 475 | __le32 decrypt_done; |
f5fc0f86 LC |
476 | |
477 | /* (INT_STS_ND & INT_TRIG_DMA0) */ | |
d0f63b20 | 478 | __le32 dma0_done; |
f5fc0f86 LC |
479 | |
480 | /* (INT_STS_ND & INT_TRIG_DMA1) */ | |
d0f63b20 | 481 | __le32 dma1_done; |
f5fc0f86 LC |
482 | |
483 | /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */ | |
d0f63b20 | 484 | __le32 tx_exch_complete; |
f5fc0f86 LC |
485 | |
486 | /* (INT_STS_ND & INT_TRIG_COMMAND) */ | |
d0f63b20 | 487 | __le32 commands; |
f5fc0f86 LC |
488 | |
489 | /* (INT_STS_ND & INT_TRIG_RX_PROC) */ | |
d0f63b20 | 490 | __le32 rx_procs; |
f5fc0f86 LC |
491 | |
492 | /* (INT_STS_ND & INT_TRIG_PM_802) */ | |
d0f63b20 | 493 | __le32 hw_pm_mode_changes; |
f5fc0f86 LC |
494 | |
495 | /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */ | |
d0f63b20 | 496 | __le32 host_acknowledges; |
f5fc0f86 LC |
497 | |
498 | /* (INT_STS_ND & INT_TRIG_PM_PCI) */ | |
d0f63b20 | 499 | __le32 pci_pm; |
f5fc0f86 LC |
500 | |
501 | /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */ | |
d0f63b20 | 502 | __le32 wakeups; |
f5fc0f86 LC |
503 | |
504 | /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */ | |
d0f63b20 | 505 | __le32 low_rssi; |
ba2d3587 | 506 | } __packed; |
f5fc0f86 LC |
507 | |
508 | struct acx_wep_statistics { | |
509 | /* WEP address keys configured */ | |
d0f63b20 | 510 | __le32 addr_key_count; |
f5fc0f86 LC |
511 | |
512 | /* default keys configured */ | |
d0f63b20 | 513 | __le32 default_key_count; |
f5fc0f86 | 514 | |
d0f63b20 | 515 | __le32 reserved; |
f5fc0f86 LC |
516 | |
517 | /* number of times that WEP key not found on lookup */ | |
d0f63b20 | 518 | __le32 key_not_found; |
f5fc0f86 LC |
519 | |
520 | /* number of times that WEP key decryption failed */ | |
d0f63b20 | 521 | __le32 decrypt_fail; |
f5fc0f86 LC |
522 | |
523 | /* WEP packets decrypted */ | |
d0f63b20 | 524 | __le32 packets; |
f5fc0f86 LC |
525 | |
526 | /* WEP decrypt interrupts */ | |
d0f63b20 | 527 | __le32 interrupt; |
ba2d3587 | 528 | } __packed; |
f5fc0f86 LC |
529 | |
530 | #define ACX_MISSED_BEACONS_SPREAD 10 | |
531 | ||
532 | struct acx_pwr_statistics { | |
533 | /* the amount of enters into power save mode (both PD & ELP) */ | |
d0f63b20 | 534 | __le32 ps_enter; |
f5fc0f86 LC |
535 | |
536 | /* the amount of enters into ELP mode */ | |
d0f63b20 | 537 | __le32 elp_enter; |
f5fc0f86 LC |
538 | |
539 | /* the amount of missing beacon interrupts to the host */ | |
d0f63b20 | 540 | __le32 missing_bcns; |
f5fc0f86 LC |
541 | |
542 | /* the amount of wake on host-access times */ | |
d0f63b20 | 543 | __le32 wake_on_host; |
f5fc0f86 LC |
544 | |
545 | /* the amount of wake on timer-expire */ | |
d0f63b20 | 546 | __le32 wake_on_timer_exp; |
f5fc0f86 LC |
547 | |
548 | /* the number of packets that were transmitted with PS bit set */ | |
d0f63b20 | 549 | __le32 tx_with_ps; |
f5fc0f86 LC |
550 | |
551 | /* the number of packets that were transmitted with PS bit clear */ | |
d0f63b20 | 552 | __le32 tx_without_ps; |
f5fc0f86 LC |
553 | |
554 | /* the number of received beacons */ | |
d0f63b20 | 555 | __le32 rcvd_beacons; |
f5fc0f86 LC |
556 | |
557 | /* the number of entering into PowerOn (power save off) */ | |
d0f63b20 | 558 | __le32 power_save_off; |
f5fc0f86 LC |
559 | |
560 | /* the number of entries into power save mode */ | |
d0f63b20 | 561 | __le16 enable_ps; |
f5fc0f86 LC |
562 | |
563 | /* | |
564 | * the number of exits from power save, not including failed PS | |
565 | * transitions | |
566 | */ | |
d0f63b20 | 567 | __le16 disable_ps; |
f5fc0f86 LC |
568 | |
569 | /* | |
570 | * the number of times the TSF counter was adjusted because | |
571 | * of drift | |
572 | */ | |
d0f63b20 | 573 | __le32 fix_tsf_ps; |
f5fc0f86 LC |
574 | |
575 | /* Gives statistics about the spread continuous missed beacons. | |
576 | * The 16 LSB are dedicated for the PS mode. | |
577 | * The 16 MSB are dedicated for the PS mode. | |
578 | * cont_miss_bcns_spread[0] - single missed beacon. | |
579 | * cont_miss_bcns_spread[1] - two continuous missed beacons. | |
580 | * cont_miss_bcns_spread[2] - three continuous missed beacons. | |
581 | * ... | |
582 | * cont_miss_bcns_spread[9] - ten and more continuous missed beacons. | |
583 | */ | |
d0f63b20 | 584 | __le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD]; |
f5fc0f86 LC |
585 | |
586 | /* the number of beacons in awake mode */ | |
d0f63b20 | 587 | __le32 rcvd_awake_beacons; |
ba2d3587 | 588 | } __packed; |
f5fc0f86 LC |
589 | |
590 | struct acx_mic_statistics { | |
d0f63b20 LC |
591 | __le32 rx_pkts; |
592 | __le32 calc_failure; | |
ba2d3587 | 593 | } __packed; |
f5fc0f86 LC |
594 | |
595 | struct acx_aes_statistics { | |
d0f63b20 LC |
596 | __le32 encrypt_fail; |
597 | __le32 decrypt_fail; | |
598 | __le32 encrypt_packets; | |
599 | __le32 decrypt_packets; | |
600 | __le32 encrypt_interrupt; | |
601 | __le32 decrypt_interrupt; | |
ba2d3587 | 602 | } __packed; |
f5fc0f86 LC |
603 | |
604 | struct acx_event_statistics { | |
d0f63b20 LC |
605 | __le32 heart_beat; |
606 | __le32 calibration; | |
607 | __le32 rx_mismatch; | |
608 | __le32 rx_mem_empty; | |
609 | __le32 rx_pool; | |
610 | __le32 oom_late; | |
611 | __le32 phy_transmit_error; | |
612 | __le32 tx_stuck; | |
ba2d3587 | 613 | } __packed; |
f5fc0f86 LC |
614 | |
615 | struct acx_ps_statistics { | |
d0f63b20 LC |
616 | __le32 pspoll_timeouts; |
617 | __le32 upsd_timeouts; | |
618 | __le32 upsd_max_sptime; | |
619 | __le32 upsd_max_apturn; | |
620 | __le32 pspoll_max_apturn; | |
621 | __le32 pspoll_utilization; | |
622 | __le32 upsd_utilization; | |
ba2d3587 | 623 | } __packed; |
f5fc0f86 LC |
624 | |
625 | struct acx_rxpipe_statistics { | |
d0f63b20 LC |
626 | __le32 rx_prep_beacon_drop; |
627 | __le32 descr_host_int_trig_rx_data; | |
628 | __le32 beacon_buffer_thres_host_int_trig_rx_data; | |
629 | __le32 missed_beacon_host_int_trig_rx_data; | |
630 | __le32 tx_xfr_host_int_trig_rx_data; | |
ba2d3587 | 631 | } __packed; |
f5fc0f86 LC |
632 | |
633 | struct acx_statistics { | |
634 | struct acx_header header; | |
635 | ||
636 | struct acx_tx_statistics tx; | |
637 | struct acx_rx_statistics rx; | |
638 | struct acx_dma_statistics dma; | |
639 | struct acx_isr_statistics isr; | |
640 | struct acx_wep_statistics wep; | |
641 | struct acx_pwr_statistics pwr; | |
642 | struct acx_aes_statistics aes; | |
643 | struct acx_mic_statistics mic; | |
644 | struct acx_event_statistics event; | |
645 | struct acx_ps_statistics ps; | |
646 | struct acx_rxpipe_statistics rxpipe; | |
ba2d3587 | 647 | } __packed; |
f5fc0f86 | 648 | |
f5fc0f86 | 649 | struct acx_rate_class { |
d0f63b20 | 650 | __le32 enabled_rates; |
f5fc0f86 LC |
651 | u8 short_retry_limit; |
652 | u8 long_retry_limit; | |
653 | u8 aflags; | |
654 | u8 reserved; | |
655 | }; | |
656 | ||
830fb67b JO |
657 | #define ACX_TX_BASIC_RATE 0 |
658 | #define ACX_TX_AP_FULL_RATE 1 | |
4b29886f | 659 | #define ACX_TX_BASIC_RATE_P2P 2 |
79b223f4 AN |
660 | #define ACX_TX_AP_MODE_MGMT_RATE 4 |
661 | #define ACX_TX_AP_MODE_BCST_RATE 5 | |
7f097988 | 662 | struct acx_rate_policy { |
79b223f4 AN |
663 | struct acx_header header; |
664 | ||
665 | __le32 rate_policy_idx; | |
666 | struct acx_rate_class rate_policy; | |
667 | } __packed; | |
668 | ||
f5fc0f86 LC |
669 | struct acx_ac_cfg { |
670 | struct acx_header header; | |
7f097988 | 671 | u8 role_id; |
f5fc0f86 | 672 | u8 ac; |
7f097988 | 673 | u8 aifsn; |
f5fc0f86 | 674 | u8 cw_min; |
d0f63b20 | 675 | __le16 cw_max; |
d0f63b20 | 676 | __le16 tx_op_limit; |
ba2d3587 | 677 | } __packed; |
f5fc0f86 | 678 | |
f5fc0f86 LC |
679 | struct acx_tid_config { |
680 | struct acx_header header; | |
7f097988 | 681 | u8 role_id; |
f5fc0f86 LC |
682 | u8 queue_id; |
683 | u8 channel_type; | |
684 | u8 tsid; | |
685 | u8 ps_scheme; | |
686 | u8 ack_policy; | |
7f097988 | 687 | u8 padding[2]; |
d0f63b20 | 688 | __le32 apsd_conf[2]; |
ba2d3587 | 689 | } __packed; |
f5fc0f86 LC |
690 | |
691 | struct acx_frag_threshold { | |
692 | struct acx_header header; | |
d0f63b20 | 693 | __le16 frag_threshold; |
f5fc0f86 | 694 | u8 padding[2]; |
ba2d3587 | 695 | } __packed; |
f5fc0f86 | 696 | |
f5fc0f86 LC |
697 | struct acx_tx_config_options { |
698 | struct acx_header header; | |
d0f63b20 LC |
699 | __le16 tx_compl_timeout; /* msec */ |
700 | __le16 tx_compl_threshold; /* number of packets */ | |
ba2d3587 | 701 | } __packed; |
f5fc0f86 | 702 | |
7f097988 | 703 | struct wl12xx_acx_config_memory { |
c8bde243 EP |
704 | struct acx_header header; |
705 | ||
706 | u8 rx_mem_block_num; | |
707 | u8 tx_min_mem_block_num; | |
708 | u8 num_stations; | |
709 | u8 num_ssid_profiles; | |
710 | __le32 total_tx_descriptors; | |
711 | u8 dyn_mem_enable; | |
712 | u8 tx_free_req; | |
713 | u8 rx_free_req; | |
714 | u8 tx_min; | |
95dac04f IY |
715 | u8 fwlog_blocks; |
716 | u8 padding[3]; | |
c8bde243 EP |
717 | } __packed; |
718 | ||
f5fc0f86 LC |
719 | struct wl1271_acx_mem_map { |
720 | struct acx_header header; | |
721 | ||
d0f63b20 LC |
722 | __le32 code_start; |
723 | __le32 code_end; | |
f5fc0f86 | 724 | |
d0f63b20 LC |
725 | __le32 wep_defkey_start; |
726 | __le32 wep_defkey_end; | |
f5fc0f86 | 727 | |
d0f63b20 LC |
728 | __le32 sta_table_start; |
729 | __le32 sta_table_end; | |
f5fc0f86 | 730 | |
d0f63b20 LC |
731 | __le32 packet_template_start; |
732 | __le32 packet_template_end; | |
f5fc0f86 LC |
733 | |
734 | /* Address of the TX result interface (control block) */ | |
d0f63b20 LC |
735 | __le32 tx_result; |
736 | __le32 tx_result_queue_start; | |
f5fc0f86 | 737 | |
d0f63b20 LC |
738 | __le32 queue_memory_start; |
739 | __le32 queue_memory_end; | |
f5fc0f86 | 740 | |
d0f63b20 LC |
741 | __le32 packet_memory_pool_start; |
742 | __le32 packet_memory_pool_end; | |
f5fc0f86 | 743 | |
d0f63b20 LC |
744 | __le32 debug_buffer1_start; |
745 | __le32 debug_buffer1_end; | |
f5fc0f86 | 746 | |
d0f63b20 LC |
747 | __le32 debug_buffer2_start; |
748 | __le32 debug_buffer2_end; | |
f5fc0f86 LC |
749 | |
750 | /* Number of blocks FW allocated for TX packets */ | |
d0f63b20 | 751 | __le32 num_tx_mem_blocks; |
f5fc0f86 LC |
752 | |
753 | /* Number of blocks FW allocated for RX packets */ | |
d0f63b20 | 754 | __le32 num_rx_mem_blocks; |
f5fc0f86 LC |
755 | |
756 | /* the following 4 fields are valid in SLAVE mode only */ | |
757 | u8 *tx_cbuf; | |
758 | u8 *rx_cbuf; | |
d0f63b20 LC |
759 | __le32 rx_ctrl; |
760 | __le32 tx_ctrl; | |
ba2d3587 | 761 | } __packed; |
f5fc0f86 | 762 | |
f5fc0f86 LC |
763 | struct wl1271_acx_rx_config_opt { |
764 | struct acx_header header; | |
765 | ||
d0f63b20 LC |
766 | __le16 mblk_threshold; |
767 | __le16 threshold; | |
768 | __le16 timeout; | |
f5fc0f86 LC |
769 | u8 queue_type; |
770 | u8 reserved; | |
ba2d3587 | 771 | } __packed; |
f5fc0f86 | 772 | |
11f70f97 JO |
773 | |
774 | struct wl1271_acx_bet_enable { | |
775 | struct acx_header header; | |
776 | ||
7f097988 | 777 | u8 role_id; |
11f70f97 JO |
778 | u8 enable; |
779 | u8 max_consecutive; | |
7f097988 | 780 | u8 padding[1]; |
ba2d3587 | 781 | } __packed; |
11f70f97 | 782 | |
01c09162 JO |
783 | #define ACX_IPV4_VERSION 4 |
784 | #define ACX_IPV6_VERSION 6 | |
785 | #define ACX_IPV4_ADDR_SIZE 4 | |
c5312772 EP |
786 | |
787 | /* bitmap of enabled arp_filter features */ | |
788 | #define ACX_ARP_FILTER_ARP_FILTERING BIT(0) | |
789 | #define ACX_ARP_FILTER_AUTO_ARP BIT(1) | |
790 | ||
01c09162 JO |
791 | struct wl1271_acx_arp_filter { |
792 | struct acx_header header; | |
7f097988 | 793 | u8 role_id; |
01c09162 | 794 | u8 version; /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */ |
c5312772 | 795 | u8 enable; /* bitmap of enabled ARP filtering features */ |
7f097988 | 796 | u8 padding[1]; |
01c09162 JO |
797 | u8 address[16]; /* The configured device IP address - all ARP |
798 | requests directed to this IP address will pass | |
799 | through. For IPv4, the first four bytes are | |
800 | used. */ | |
ba2d3587 | 801 | } __packed; |
01c09162 | 802 | |
38ad2d87 JO |
803 | struct wl1271_acx_pm_config { |
804 | struct acx_header header; | |
805 | ||
806 | __le32 host_clk_settling_time; | |
807 | u8 host_fast_wakeup_support; | |
808 | u8 padding[3]; | |
ba2d3587 | 809 | } __packed; |
01c09162 | 810 | |
c1899554 JO |
811 | struct wl1271_acx_keep_alive_mode { |
812 | struct acx_header header; | |
813 | ||
7f097988 | 814 | u8 role_id; |
c1899554 | 815 | u8 enabled; |
7f097988 | 816 | u8 padding[2]; |
ba2d3587 | 817 | } __packed; |
c1899554 JO |
818 | |
819 | enum { | |
820 | ACX_KEEP_ALIVE_NO_TX = 0, | |
821 | ACX_KEEP_ALIVE_PERIOD_ONLY | |
822 | }; | |
823 | ||
824 | enum { | |
825 | ACX_KEEP_ALIVE_TPL_INVALID = 0, | |
826 | ACX_KEEP_ALIVE_TPL_VALID | |
827 | }; | |
828 | ||
829 | struct wl1271_acx_keep_alive_config { | |
830 | struct acx_header header; | |
831 | ||
7f097988 | 832 | u8 role_id; |
c1899554 JO |
833 | u8 index; |
834 | u8 tpl_validation; | |
835 | u8 trigger; | |
7f097988 | 836 | __le32 period; |
ba2d3587 | 837 | } __packed; |
c1899554 | 838 | |
48a61477 SL |
839 | #define HOST_IF_CFG_RX_FIFO_ENABLE BIT(0) |
840 | #define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1) | |
841 | #define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3) | |
842 | ||
843 | struct wl1271_acx_host_config_bitmap { | |
844 | struct acx_header header; | |
845 | ||
846 | __le32 host_cfg_bitmap; | |
847 | } __packed; | |
848 | ||
00236aed JO |
849 | enum { |
850 | WL1271_ACX_TRIG_TYPE_LEVEL = 0, | |
851 | WL1271_ACX_TRIG_TYPE_EDGE, | |
852 | }; | |
853 | ||
854 | enum { | |
855 | WL1271_ACX_TRIG_DIR_LOW = 0, | |
856 | WL1271_ACX_TRIG_DIR_HIGH, | |
857 | WL1271_ACX_TRIG_DIR_BIDIR, | |
858 | }; | |
859 | ||
860 | enum { | |
861 | WL1271_ACX_TRIG_ENABLE = 1, | |
862 | WL1271_ACX_TRIG_DISABLE, | |
863 | }; | |
864 | ||
865 | enum { | |
866 | WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0, | |
867 | WL1271_ACX_TRIG_METRIC_RSSI_DATA, | |
868 | WL1271_ACX_TRIG_METRIC_SNR_BEACON, | |
869 | WL1271_ACX_TRIG_METRIC_SNR_DATA, | |
870 | }; | |
871 | ||
872 | enum { | |
873 | WL1271_ACX_TRIG_IDX_RSSI = 0, | |
874 | WL1271_ACX_TRIG_COUNT = 8, | |
875 | }; | |
876 | ||
877 | struct wl1271_acx_rssi_snr_trigger { | |
878 | struct acx_header header; | |
879 | ||
7f097988 | 880 | u8 role_id; |
00236aed JO |
881 | u8 metric; |
882 | u8 type; | |
883 | u8 dir; | |
7f097988 EP |
884 | __le16 threshold; |
885 | __le16 pacing; /* 0 - 60000 ms */ | |
00236aed JO |
886 | u8 hysteresis; |
887 | u8 index; | |
888 | u8 enable; | |
7f097988 | 889 | u8 padding[1]; |
00236aed JO |
890 | }; |
891 | ||
892 | struct wl1271_acx_rssi_snr_avg_weights { | |
893 | struct acx_header header; | |
894 | ||
7f097988 EP |
895 | u8 role_id; |
896 | u8 padding[3]; | |
00236aed JO |
897 | u8 rssi_beacon; |
898 | u8 rssi_data; | |
899 | u8 snr_beacon; | |
900 | u8 snr_data; | |
901 | }; | |
902 | ||
0f9c8250 AN |
903 | |
904 | /* special capability bit (not employed by the 802.11n spec) */ | |
905 | #define WL12XX_HT_CAP_HT_OPERATION BIT(16) | |
906 | ||
e8b03a2b SL |
907 | /* |
908 | * ACX_PEER_HT_CAP | |
909 | * Configure HT capabilities - declare the capabilities of the peer | |
910 | * we are connected to. | |
911 | */ | |
912 | struct wl1271_acx_ht_capabilities { | |
913 | struct acx_header header; | |
914 | ||
0f9c8250 | 915 | /* bitmask of capability bits supported by the peer */ |
e8b03a2b SL |
916 | __le32 ht_capabilites; |
917 | ||
7f097988 EP |
918 | /* Indicates to which link these capabilities apply. */ |
919 | u8 hlid; | |
e8b03a2b SL |
920 | |
921 | /* | |
922 | * This the maximum A-MPDU length supported by the AP. The FW may not | |
923 | * exceed this length when sending A-MPDUs | |
924 | */ | |
925 | u8 ampdu_max_length; | |
926 | ||
927 | /* This is the minimal spacing required when sending A-MPDUs to the AP*/ | |
928 | u8 ampdu_min_spacing; | |
7f097988 EP |
929 | |
930 | u8 padding; | |
e8b03a2b SL |
931 | } __packed; |
932 | ||
e8b03a2b SL |
933 | /* |
934 | * ACX_HT_BSS_OPERATION | |
935 | * Configure HT capabilities - AP rules for behavior in the BSS. | |
936 | */ | |
937 | struct wl1271_acx_ht_information { | |
938 | struct acx_header header; | |
939 | ||
7f097988 EP |
940 | u8 role_id; |
941 | ||
e8b03a2b SL |
942 | /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */ |
943 | u8 rifs_mode; | |
944 | ||
945 | /* Values: 0 - 3 like in spec */ | |
946 | u8 ht_protection; | |
947 | ||
948 | /* Values: 0 - GF protection not required, 1 - GF protection required */ | |
949 | u8 gf_protection; | |
950 | ||
951 | /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/ | |
952 | u8 ht_tx_burst_limit; | |
953 | ||
954 | /* | |
955 | * Values: 0 - Dual CTS protection not required, | |
956 | * 1 - Dual CTS Protection required | |
957 | * Note: When this value is set to 1 FW will protect all TXOP with RTS | |
958 | * frame and will not use CTS-to-self regardless of the value of the | |
959 | * ACX_CTS_PROTECTION information element | |
960 | */ | |
961 | u8 dual_cts_protection; | |
962 | ||
7f097988 | 963 | u8 padding[2]; |
e8b03a2b SL |
964 | } __packed; |
965 | ||
0f9c8250 | 966 | #define RX_BA_MAX_SESSIONS 2 |
4b7fac77 | 967 | |
0f9c8250 | 968 | struct wl1271_acx_ba_initiator_policy { |
4b7fac77 | 969 | struct acx_header header; |
0f9c8250 AN |
970 | |
971 | /* Specifies role Id, Range 0-7, 0xFF means ANY role. */ | |
4b7fac77 | 972 | u8 role_id; |
0f9c8250 | 973 | |
4b7fac77 | 974 | /* |
0f9c8250 AN |
975 | * Per TID setting for allowing TX BA. Set a bit to 1 to allow |
976 | * TX BA sessions for the corresponding TID. | |
4b7fac77 | 977 | */ |
0f9c8250 | 978 | u8 tid_bitmap; |
4b7fac77 LS |
979 | |
980 | /* Windows size in number of packets */ | |
0f9c8250 | 981 | u8 win_size; |
4b7fac77 | 982 | |
0f9c8250 | 983 | u8 padding1[1]; |
4b7fac77 | 984 | |
0f9c8250 AN |
985 | /* As initiator inactivity timeout in time units(TU) of 1024us */ |
986 | u16 inactivity_timeout; | |
4b7fac77 | 987 | |
0f9c8250 | 988 | u8 padding[2]; |
4b7fac77 LS |
989 | } __packed; |
990 | ||
bbba3e68 LS |
991 | struct wl1271_acx_ba_receiver_setup { |
992 | struct acx_header header; | |
993 | ||
0f9c8250 AN |
994 | /* Specifies link id, range 0-31 */ |
995 | u8 hlid; | |
bbba3e68 LS |
996 | |
997 | u8 tid; | |
998 | ||
999 | u8 enable; | |
1000 | ||
bbba3e68 | 1001 | /* Windows size in number of packets */ |
0f9c8250 | 1002 | u8 win_size; |
bbba3e68 LS |
1003 | |
1004 | /* BA session starting sequence number. RANGE 0-FFF */ | |
1005 | u16 ssn; | |
0f9c8250 AN |
1006 | |
1007 | u8 padding[2]; | |
bbba3e68 LS |
1008 | } __packed; |
1009 | ||
bbbb538e JO |
1010 | struct wl1271_acx_fw_tsf_information { |
1011 | struct acx_header header; | |
1012 | ||
1013 | __le32 current_tsf_high; | |
1014 | __le32 current_tsf_low; | |
1015 | __le32 last_bttt_high; | |
1016 | __le32 last_tbtt_low; | |
1017 | u8 last_dtim_count; | |
1018 | u8 padding[3]; | |
72e93e91 | 1019 | } __packed; |
bbbb538e | 1020 | |
f84673d5 EP |
1021 | struct wl1271_acx_ps_rx_streaming { |
1022 | struct acx_header header; | |
1023 | ||
7f097988 | 1024 | u8 role_id; |
f84673d5 EP |
1025 | u8 tid; |
1026 | u8 enable; | |
1027 | ||
1028 | /* interval between triggers (10-100 msec) */ | |
1029 | u8 period; | |
1030 | ||
1031 | /* timeout before first trigger (0-200 msec) */ | |
1032 | u8 timeout; | |
7f097988 | 1033 | u8 padding[3]; |
f84673d5 EP |
1034 | } __packed; |
1035 | ||
3618f30f | 1036 | struct wl1271_acx_ap_max_tx_retry { |
79b223f4 AN |
1037 | struct acx_header header; |
1038 | ||
7f097988 EP |
1039 | u8 role_id; |
1040 | u8 padding_1; | |
1041 | ||
79b223f4 AN |
1042 | /* |
1043 | * the number of frames transmission failures before | |
1044 | * issuing the aging event. | |
1045 | */ | |
1046 | __le16 max_tx_retry; | |
79b223f4 AN |
1047 | } __packed; |
1048 | ||
ee60833a EP |
1049 | struct wl1271_acx_config_ps { |
1050 | struct acx_header header; | |
1051 | ||
1052 | u8 exit_retries; | |
1053 | u8 enter_retries; | |
1054 | u8 padding[2]; | |
1055 | __le32 null_data_rate; | |
1056 | } __packed; | |
1057 | ||
99a2775d AN |
1058 | struct wl1271_acx_inconnection_sta { |
1059 | struct acx_header header; | |
1060 | ||
1061 | u8 addr[ETH_ALEN]; | |
1062 | u8 padding1[2]; | |
1063 | } __packed; | |
1064 | ||
ff86843d SL |
1065 | /* |
1066 | * ACX_FM_COEX_CFG | |
1067 | * set the FM co-existence parameters. | |
1068 | */ | |
1069 | struct wl1271_acx_fm_coex { | |
1070 | struct acx_header header; | |
1071 | /* enable(1) / disable(0) the FM Coex feature */ | |
1072 | u8 enable; | |
1073 | /* | |
1074 | * Swallow period used in COEX PLL swallowing mechanism. | |
1075 | * 0xFF = use FW default | |
1076 | */ | |
1077 | u8 swallow_period; | |
1078 | /* | |
1079 | * The N divider used in COEX PLL swallowing mechanism for Fref of | |
1080 | * 38.4/19.2 Mhz. 0xFF = use FW default | |
1081 | */ | |
1082 | u8 n_divider_fref_set_1; | |
1083 | /* | |
1084 | * The N divider used in COEX PLL swallowing mechanism for Fref of | |
1085 | * 26/52 Mhz. 0xFF = use FW default | |
1086 | */ | |
1087 | u8 n_divider_fref_set_2; | |
1088 | /* | |
1089 | * The M divider used in COEX PLL swallowing mechanism for Fref of | |
1090 | * 38.4/19.2 Mhz. 0xFFFF = use FW default | |
1091 | */ | |
1092 | __le16 m_divider_fref_set_1; | |
1093 | /* | |
1094 | * The M divider used in COEX PLL swallowing mechanism for Fref of | |
1095 | * 26/52 Mhz. 0xFFFF = use FW default | |
1096 | */ | |
1097 | __le16 m_divider_fref_set_2; | |
1098 | /* | |
1099 | * The time duration in uSec required for COEX PLL to stabilize. | |
1100 | * 0xFFFFFFFF = use FW default | |
1101 | */ | |
1102 | __le32 coex_pll_stabilization_time; | |
1103 | /* | |
1104 | * The time duration in uSec required for LDO to stabilize. | |
1105 | * 0xFFFFFFFF = use FW default | |
1106 | */ | |
1107 | __le16 ldo_stabilization_time; | |
1108 | /* | |
1109 | * The disturbed frequency band margin around the disturbed frequency | |
1110 | * center (single sided). | |
1111 | * For example, if 2 is configured, the following channels will be | |
1112 | * considered disturbed channel: | |
1113 | * 80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH | |
1114 | * 0xFF = use FW default | |
1115 | */ | |
1116 | u8 fm_disturbed_band_margin; | |
1117 | /* | |
1118 | * The swallow clock difference of the swallowing mechanism. | |
1119 | * 0xFF = use FW default | |
1120 | */ | |
1121 | u8 swallow_clk_diff; | |
1122 | } __packed; | |
1123 | ||
fa6ad9f0 EP |
1124 | #define ACX_RATE_MGMT_ALL_PARAMS 0xff |
1125 | struct wl12xx_acx_set_rate_mgmt_params { | |
1126 | struct acx_header header; | |
1127 | ||
1128 | u8 index; /* 0xff to configure all params */ | |
1129 | u8 padding1; | |
1130 | __le16 rate_retry_score; | |
1131 | __le16 per_add; | |
1132 | __le16 per_th1; | |
1133 | __le16 per_th2; | |
1134 | __le16 max_per; | |
1135 | u8 inverse_curiosity_factor; | |
1136 | u8 tx_fail_low_th; | |
1137 | u8 tx_fail_high_th; | |
1138 | u8 per_alpha_shift; | |
1139 | u8 per_add_shift; | |
1140 | u8 per_beta1_shift; | |
1141 | u8 per_beta2_shift; | |
1142 | u8 rate_check_up; | |
1143 | u8 rate_check_down; | |
1144 | u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES]; | |
1145 | u8 padding2[2]; | |
1146 | } __packed; | |
1147 | ||
9487775c EP |
1148 | struct wl12xx_acx_config_hangover { |
1149 | struct acx_header header; | |
1150 | ||
1151 | __le32 recover_time; | |
1152 | u8 hangover_period; | |
1153 | u8 dynamic_mode; | |
1154 | u8 early_termination_mode; | |
1155 | u8 max_period; | |
1156 | u8 min_period; | |
1157 | u8 increase_delta; | |
1158 | u8 decrease_delta; | |
1159 | u8 quiet_time; | |
1160 | u8 increase_time; | |
1161 | u8 window_size; | |
1162 | u8 padding[2]; | |
1163 | } __packed; | |
1164 | ||
f5fc0f86 LC |
1165 | enum { |
1166 | ACX_WAKE_UP_CONDITIONS = 0x0002, | |
1167 | ACX_MEM_CFG = 0x0003, | |
1168 | ACX_SLOT = 0x0004, | |
1169 | ACX_AC_CFG = 0x0007, | |
1170 | ACX_MEM_MAP = 0x0008, | |
1171 | ACX_AID = 0x000A, | |
f5fc0f86 | 1172 | ACX_MEDIUM_USAGE = 0x000F, |
f5fc0f86 LC |
1173 | ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */ |
1174 | ACX_STATISTICS = 0x0013, /* Debug API */ | |
1175 | ACX_PWR_CONSUMPTION_STATISTICS = 0x0014, | |
1176 | ACX_FEATURE_CFG = 0x0015, | |
1177 | ACX_TID_CFG = 0x001A, | |
1178 | ACX_PS_RX_STREAMING = 0x001B, | |
1179 | ACX_BEACON_FILTER_OPT = 0x001F, | |
1180 | ACX_NOISE_HIST = 0x0021, | |
1181 | ACX_HDK_VERSION = 0x0022, /* ??? */ | |
1182 | ACX_PD_THRESHOLD = 0x0023, | |
1183 | ACX_TX_CONFIG_OPT = 0x0024, | |
1184 | ACX_CCA_THRESHOLD = 0x0025, | |
1185 | ACX_EVENT_MBOX_MASK = 0x0026, | |
1186 | ACX_CONN_MONIT_PARAMS = 0x002D, | |
f5fc0f86 LC |
1187 | ACX_BCN_DTIM_OPTIONS = 0x0031, |
1188 | ACX_SG_ENABLE = 0x0032, | |
1189 | ACX_SG_CFG = 0x0033, | |
ff86843d | 1190 | ACX_FM_COEX_CFG = 0x0034, |
f5fc0f86 LC |
1191 | ACX_BEACON_FILTER_TABLE = 0x0038, |
1192 | ACX_ARP_IP_FILTER = 0x0039, | |
1193 | ACX_ROAMING_STATISTICS_TBL = 0x003B, | |
1194 | ACX_RATE_POLICY = 0x003D, | |
1195 | ACX_CTS_PROTECTION = 0x003E, | |
1196 | ACX_SLEEP_AUTH = 0x003F, | |
1197 | ACX_PREAMBLE_TYPE = 0x0040, | |
1198 | ACX_ERROR_CNT = 0x0041, | |
1199 | ACX_IBSS_FILTER = 0x0044, | |
1200 | ACX_SERVICE_PERIOD_TIMEOUT = 0x0045, | |
1201 | ACX_TSF_INFO = 0x0046, | |
1202 | ACX_CONFIG_PS_WMM = 0x0049, | |
1203 | ACX_ENABLE_RX_DATA_FILTER = 0x004A, | |
1204 | ACX_SET_RX_DATA_FILTER = 0x004B, | |
1205 | ACX_GET_DATA_FILTER_STATISTICS = 0x004C, | |
1206 | ACX_RX_CONFIG_OPT = 0x004E, | |
1207 | ACX_FRAG_CFG = 0x004F, | |
1208 | ACX_BET_ENABLE = 0x0050, | |
1209 | ACX_RSSI_SNR_TRIGGER = 0x0051, | |
00236aed | 1210 | ACX_RSSI_SNR_WEIGHTS = 0x0052, |
c1899554 | 1211 | ACX_KEEP_ALIVE_MODE = 0x0053, |
f5fc0f86 | 1212 | ACX_SET_KEEP_ALIVE_CONFIG = 0x0054, |
0f9c8250 | 1213 | ACX_BA_SESSION_INIT_POLICY = 0x0055, |
4b7fac77 | 1214 | ACX_BA_SESSION_RX_SETUP = 0x0056, |
f5fc0f86 LC |
1215 | ACX_PEER_HT_CAP = 0x0057, |
1216 | ACX_HT_BSS_OPERATION = 0x0058, | |
1217 | ACX_COEX_ACTIVITY = 0x0059, | |
7f097988 EP |
1218 | ACX_BURST_MODE = 0x005C, |
1219 | ACX_SET_RATE_MGMT_PARAMS = 0x005D, | |
1220 | ACX_SET_RATE_ADAPT_PARAMS = 0x0060, | |
6e92b416 | 1221 | ACX_SET_DCO_ITRIM_PARAMS = 0x0061, |
c8bde243 EP |
1222 | ACX_GEN_FW_CMD = 0x0070, |
1223 | ACX_HOST_IF_CFG_BITMAP = 0x0071, | |
79b223f4 | 1224 | ACX_MAX_TX_FAILURE = 0x0072, |
99a2775d | 1225 | ACX_UPDATE_INCONNECTION_STA_LIST = 0x0073, |
f5fc0f86 LC |
1226 | DOT11_RX_MSDU_LIFE_TIME = 0x1004, |
1227 | DOT11_CUR_TX_PWR = 0x100D, | |
1228 | DOT11_RX_DOT11_MODE = 0x1012, | |
1229 | DOT11_RTS_THRESHOLD = 0x1013, | |
1230 | DOT11_GROUP_ADDRESS_TBL = 0x1014, | |
38ad2d87 | 1231 | ACX_PM_CONFIG = 0x1016, |
ee60833a | 1232 | ACX_CONFIG_PS = 0x1017, |
c8bde243 | 1233 | ACX_CONFIG_HANGOVER = 0x1018, |
f5fc0f86 LC |
1234 | }; |
1235 | ||
1236 | ||
0603d891 EP |
1237 | int wl1271_acx_wake_up_conditions(struct wl1271 *wl, |
1238 | struct wl12xx_vif *wlvif); | |
f5fc0f86 | 1239 | int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth); |
0603d891 EP |
1240 | int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1241 | int power); | |
1242 | int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif); | |
f5fc0f86 LC |
1243 | int wl1271_acx_mem_map(struct wl1271 *wl, |
1244 | struct acx_header *mem_map, size_t len); | |
8793f9bb | 1245 | int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl); |
f5fc0f86 | 1246 | int wl1271_acx_pd_threshold(struct wl1271 *wl); |
0603d891 EP |
1247 | int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1248 | enum acx_slot_type slot_time); | |
1249 | int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1250 | bool enable, void *mc_list, u32 mc_list_len); | |
1251 | int wl1271_acx_service_period_timeout(struct wl1271 *wl, | |
1252 | struct wl12xx_vif *wlvif); | |
1253 | int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1254 | u32 rts_threshold); | |
6e92b416 | 1255 | int wl1271_acx_dco_itrim_params(struct wl1271 *wl); |
0603d891 EP |
1256 | int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1257 | bool enable_filter); | |
1258 | int wl1271_acx_beacon_filter_table(struct wl1271 *wl, | |
1259 | struct wl12xx_vif *wlvif); | |
1260 | int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1261 | bool enable); | |
7fc3a864 | 1262 | int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable); |
3be4112c | 1263 | int wl12xx_acx_sg_cfg(struct wl1271 *wl); |
f5fc0f86 | 1264 | int wl1271_acx_cca_threshold(struct wl1271 *wl); |
0603d891 EP |
1265 | int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
1266 | int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid); | |
f5fc0f86 | 1267 | int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask); |
0603d891 EP |
1268 | int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1269 | enum acx_preamble_type preamble); | |
1270 | int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
11f70f97 | 1271 | enum acx_ctsprotect_type ctsprotect); |
f5fc0f86 | 1272 | int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats); |
30d0c8fd | 1273 | int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
79b223f4 AN |
1274 | int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c, |
1275 | u8 idx); | |
0603d891 EP |
1276 | int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1277 | u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop); | |
1278 | int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1279 | u8 queue_id, u8 channel_type, | |
f2054df5 KV |
1280 | u8 tsid, u8 ps_scheme, u8 ack_policy, |
1281 | u32 apsd_conf0, u32 apsd_conf1); | |
5f704d18 | 1282 | int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold); |
f5fc0f86 | 1283 | int wl1271_acx_tx_config_options(struct wl1271 *wl); |
7f097988 | 1284 | int wl12xx_acx_mem_cfg(struct wl1271 *wl); |
f5fc0f86 | 1285 | int wl1271_acx_init_mem_config(struct wl1271 *wl); |
48a61477 | 1286 | int wl1271_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap); |
f5fc0f86 | 1287 | int wl1271_acx_init_rx_interrupt(struct wl1271 *wl); |
3cfd6cf9 | 1288 | int wl1271_acx_smart_reflex(struct wl1271 *wl); |
0603d891 EP |
1289 | int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
1290 | bool enable); | |
1291 | int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1292 | u8 enable, __be32 address); | |
38ad2d87 | 1293 | int wl1271_acx_pm_config(struct wl1271 *wl); |
0603d891 EP |
1294 | int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif, |
1295 | bool enable); | |
1296 | int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1297 | u8 index, u8 tpl_valid); | |
1298 | int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif, | |
1299 | bool enable, s16 thold, u8 hyst); | |
1300 | int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl, | |
1301 | struct wl12xx_vif *wlvif); | |
c4db1c87 SL |
1302 | int wl1271_acx_set_ht_capabilities(struct wl1271 *wl, |
1303 | struct ieee80211_sta_ht_cap *ht_cap, | |
0b932ab9 | 1304 | bool allow_ht_operation, u8 hlid); |
c4db1c87 | 1305 | int wl1271_acx_set_ht_information(struct wl1271 *wl, |
0603d891 | 1306 | struct wl12xx_vif *wlvif, |
c4db1c87 | 1307 | u16 ht_operation_mode); |
0603d891 EP |
1308 | int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl, |
1309 | struct wl12xx_vif *wlvif); | |
0f9c8250 AN |
1310 | int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index, |
1311 | u16 ssn, bool enable, u8 peer_hlid); | |
bbbb538e | 1312 | int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime); |
f84673d5 | 1313 | int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, bool enable); |
0603d891 | 1314 | int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
d2d66c56 | 1315 | int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
99a2775d | 1316 | int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr); |
ff86843d | 1317 | int wl1271_acx_fm_coex(struct wl1271 *wl); |
fa6ad9f0 | 1318 | int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl); |
9487775c | 1319 | int wl12xx_acx_config_hangover(struct wl1271 *wl); |
f5fc0f86 LC |
1320 | |
1321 | #endif /* __WL1271_ACX_H__ */ |