Commit | Line | Data |
---|---|---|
b2ba99ff LC |
1 | /* |
2 | * This file is part of wlcore | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #ifndef __WLCORE_H__ | |
23 | #define __WLCORE_H__ | |
24 | ||
c31be25a LC |
25 | #include <linux/platform_device.h> |
26 | ||
8388569a | 27 | #include "wlcore_i.h" |
c31be25a | 28 | #include "event.h" |
7140df6e | 29 | #include "boot.h" |
c31be25a | 30 | |
72b0624f AN |
31 | /* The maximum number of Tx descriptors in all chip families */ |
32 | #define WLCORE_MAX_TX_DESCRIPTORS 32 | |
33 | ||
f4afbed9 AN |
34 | /* |
35 | * We always allocate this number of mac addresses. If we don't | |
36 | * have enough allocated addresses, the LAA bit is used | |
37 | */ | |
38 | #define WLCORE_NUM_MAC_ADDRESSES 3 | |
39 | ||
583f8164 VG |
40 | /* wl12xx/wl18xx maximum transmission power (in dBm) */ |
41 | #define WLCORE_MAX_TXPWR 25 | |
42 | ||
cd70f6a4 AN |
43 | /* forward declaration */ |
44 | struct wl1271_tx_hw_descr; | |
45 | enum wl_rx_buf_align; | |
169da04f | 46 | struct wl1271_rx_descriptor; |
4158149c | 47 | |
c31be25a | 48 | struct wlcore_ops { |
3992eb2b | 49 | int (*setup)(struct wl1271 *wl); |
6f7dd16c | 50 | int (*identify_chip)(struct wl1271 *wl); |
80cd6610 | 51 | int (*identify_fw)(struct wl1271 *wl); |
dd5512eb | 52 | int (*boot)(struct wl1271 *wl); |
c331b344 | 53 | int (*plt_init)(struct wl1271 *wl); |
eb96f841 IY |
54 | int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr, |
55 | void *buf, size_t len); | |
b0f0ad39 | 56 | int (*ack_event)(struct wl1271 *wl); |
c50a2825 EP |
57 | int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event, |
58 | bool *timeout); | |
59 | int (*process_mailbox_events)(struct wl1271 *wl); | |
b3b4b4b8 | 60 | u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks); |
4a3b97ee AN |
61 | void (*set_tx_desc_blocks)(struct wl1271 *wl, |
62 | struct wl1271_tx_hw_descr *desc, | |
63 | u32 blks, u32 spare_blks); | |
6f266e91 AN |
64 | void (*set_tx_desc_data_len)(struct wl1271 *wl, |
65 | struct wl1271_tx_hw_descr *desc, | |
66 | struct sk_buff *skb); | |
cd70f6a4 AN |
67 | enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl, |
68 | u32 rx_desc); | |
eb96f841 | 69 | int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len); |
4158149c AN |
70 | u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data, |
71 | u32 data_len); | |
045b9b5f | 72 | int (*tx_delayed_compl)(struct wl1271 *wl); |
53d67a50 | 73 | void (*tx_immediate_compl)(struct wl1271 *wl); |
9d68d1ee | 74 | int (*hw_init)(struct wl1271 *wl); |
8a9affc0 | 75 | int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
75fb4df7 EP |
76 | void (*convert_fw_status)(struct wl1271 *wl, void *raw_fw_status, |
77 | struct wl_fw_status *fw_status); | |
fa7930af AN |
78 | u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl, |
79 | struct wl12xx_vif *wlvif); | |
6134323f IY |
80 | int (*get_pg_ver)(struct wl1271 *wl, s8 *ver); |
81 | int (*get_mac)(struct wl1271 *wl); | |
2fc28de5 AN |
82 | void (*set_tx_desc_csum)(struct wl1271 *wl, |
83 | struct wl1271_tx_hw_descr *desc, | |
84 | struct sk_buff *skb); | |
169da04f AN |
85 | void (*set_rx_csum)(struct wl1271 *wl, |
86 | struct wl1271_rx_descriptor *desc, | |
87 | struct sk_buff *skb); | |
ebc7e57d AN |
88 | u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl, |
89 | struct wl12xx_vif *wlvif); | |
4987257c | 90 | int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir); |
7140df6e LC |
91 | int (*handle_static_data)(struct wl1271 *wl, |
92 | struct wl1271_static_data *static_data); | |
78e28062 EP |
93 | int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
94 | struct cfg80211_scan_request *req); | |
95 | int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif); | |
78e28062 EP |
96 | int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
97 | struct cfg80211_sched_scan_request *req, | |
633e2713 | 98 | struct ieee80211_scan_ies *ies); |
78e28062 | 99 | void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
32bb2c03 | 100 | int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem); |
a1c597f2 AN |
101 | int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd, |
102 | struct ieee80211_vif *vif, | |
103 | struct ieee80211_sta *sta, | |
104 | struct ieee80211_key_conf *key_conf); | |
fcab1890 EP |
105 | int (*channel_switch)(struct wl1271 *wl, |
106 | struct wl12xx_vif *wlvif, | |
107 | struct ieee80211_channel_switch *ch_switch); | |
9fccc82e | 108 | u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len); |
7d3b29e5 | 109 | void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
530abe19 EP |
110 | int (*set_peer_cap)(struct wl1271 *wl, |
111 | struct ieee80211_sta_ht_cap *ht_cap, | |
112 | bool allow_ht_operation, | |
113 | u32 rate_set, u8 hlid); | |
c83cb803 | 114 | u32 (*convert_hwaddr)(struct wl1271 *wl, u32 hwaddr); |
f1626fd8 AN |
115 | bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid, |
116 | struct wl1271_link *lnk); | |
117 | bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid, | |
118 | struct wl1271_link *lnk); | |
6d5a748d RA |
119 | int (*interrupt_notify)(struct wl1271 *wl, bool action); |
120 | int (*rx_ba_filter)(struct wl1271 *wl, bool action); | |
e2f1e50f | 121 | int (*ap_sleep)(struct wl1271 *wl); |
ccb1df94 EP |
122 | int (*smart_config_start)(struct wl1271 *wl, u32 group_bitmap); |
123 | int (*smart_config_stop)(struct wl1271 *wl); | |
124 | int (*smart_config_set_group_key)(struct wl1271 *wl, u16 group_id, | |
125 | u8 key_len, u8 *key); | |
750e9d15 EP |
126 | int (*set_cac)(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
127 | bool start); | |
830513ab | 128 | int (*dfs_master_restart)(struct wl1271 *wl, struct wl12xx_vif *wlvif); |
c31be25a LC |
129 | }; |
130 | ||
25a43d78 LC |
131 | enum wlcore_partitions { |
132 | PART_DOWN, | |
133 | PART_WORK, | |
134 | PART_BOOT, | |
135 | PART_DRPW, | |
136 | PART_TOP_PRCM_ELP_SOC, | |
137 | PART_PHY_INIT, | |
138 | ||
139 | PART_TABLE_LEN, | |
140 | }; | |
141 | ||
142 | struct wlcore_partition { | |
143 | u32 size; | |
144 | u32 start; | |
145 | }; | |
146 | ||
147 | struct wlcore_partition_set { | |
148 | struct wlcore_partition mem; | |
149 | struct wlcore_partition reg; | |
150 | struct wlcore_partition mem2; | |
151 | struct wlcore_partition mem3; | |
152 | }; | |
153 | ||
00782136 LC |
154 | enum wlcore_registers { |
155 | /* register addresses, used with partition translation */ | |
156 | REG_ECPU_CONTROL, | |
157 | REG_INTERRUPT_NO_CLEAR, | |
158 | REG_INTERRUPT_ACK, | |
159 | REG_COMMAND_MAILBOX_PTR, | |
160 | REG_EVENT_MAILBOX_PTR, | |
161 | REG_INTERRUPT_TRIG, | |
162 | REG_INTERRUPT_MASK, | |
163 | REG_PC_ON_RECOVERY, | |
164 | REG_CHIP_ID_B, | |
165 | REG_CMD_MBOX_ADDRESS, | |
166 | ||
167 | /* data access memory addresses, used with partition translation */ | |
168 | REG_SLV_MEM_DATA, | |
169 | REG_SLV_REG_DATA, | |
170 | ||
171 | /* raw data access memory addresses */ | |
172 | REG_RAW_FW_STATUS_ADDR, | |
173 | ||
174 | REG_TABLE_LEN, | |
175 | }; | |
176 | ||
4987257c LC |
177 | struct wl1271_stats { |
178 | void *fw_stats; | |
179 | unsigned long fw_stats_update; | |
180 | size_t fw_stats_len; | |
181 | ||
182 | unsigned int retry_count; | |
183 | unsigned int excessive_retries; | |
184 | }; | |
185 | ||
c31be25a | 186 | struct wl1271 { |
6f8d6b20 | 187 | bool initialized; |
c31be25a LC |
188 | struct ieee80211_hw *hw; |
189 | bool mac80211_registered; | |
190 | ||
191 | struct device *dev; | |
3992eb2b | 192 | struct platform_device *pdev; |
c31be25a LC |
193 | |
194 | void *if_priv; | |
195 | ||
196 | struct wl1271_if_operations *if_ops; | |
197 | ||
c31be25a | 198 | int irq; |
c31be25a | 199 | |
6f921fab LC |
200 | int irq_flags; |
201 | ||
c31be25a LC |
202 | spinlock_t wl_lock; |
203 | ||
4cc53383 | 204 | enum wlcore_state state; |
c31be25a LC |
205 | enum wl12xx_fw_type fw_type; |
206 | bool plt; | |
7019c80e | 207 | enum plt_mode plt_mode; |
ff324317 | 208 | u8 fem_manuf; |
c31be25a LC |
209 | u8 last_vif_count; |
210 | struct mutex mutex; | |
211 | ||
212 | unsigned long flags; | |
213 | ||
25a43d78 | 214 | struct wlcore_partition_set curr_part; |
c31be25a LC |
215 | |
216 | struct wl1271_chip chip; | |
217 | ||
218 | int cmd_box_addr; | |
c31be25a LC |
219 | |
220 | u8 *fw; | |
221 | size_t fw_len; | |
222 | void *nvs; | |
223 | size_t nvs_len; | |
224 | ||
225 | s8 hw_pg_ver; | |
226 | ||
227 | /* address read from the fuse ROM */ | |
228 | u32 fuse_oui_addr; | |
229 | u32 fuse_nic_addr; | |
230 | ||
231 | /* we have up to 2 MAC addresses */ | |
f4afbed9 | 232 | struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES]; |
c31be25a LC |
233 | int channel; |
234 | u8 system_hlid; | |
235 | ||
da08fdfa | 236 | unsigned long links_map[BITS_TO_LONGS(WLCORE_MAX_LINKS)]; |
c31be25a LC |
237 | unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)]; |
238 | unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)]; | |
239 | unsigned long rate_policies_map[ | |
240 | BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)]; | |
001e39a8 EP |
241 | unsigned long klv_templates_map[ |
242 | BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)]; | |
c31be25a | 243 | |
da08fdfa | 244 | u8 session_ids[WLCORE_MAX_LINKS]; |
978cd3a0 | 245 | |
c31be25a LC |
246 | struct list_head wlvif_list; |
247 | ||
248 | u8 sta_count; | |
249 | u8 ap_count; | |
250 | ||
251 | struct wl1271_acx_mem_map *target_mem_map; | |
252 | ||
253 | /* Accounting for allocated / available TX blocks on HW */ | |
254 | u32 tx_blocks_freed; | |
255 | u32 tx_blocks_available; | |
256 | u32 tx_allocated_blocks; | |
257 | u32 tx_results_count; | |
258 | ||
c31be25a LC |
259 | /* Accounting for allocated / available Tx packets in HW */ |
260 | u32 tx_pkts_freed[NUM_TX_QUEUES]; | |
261 | u32 tx_allocated_pkts[NUM_TX_QUEUES]; | |
262 | ||
263 | /* Transmitted TX packets counter for chipset interface */ | |
264 | u32 tx_packets_count; | |
265 | ||
266 | /* Time-offset between host and chipset clocks */ | |
267 | s64 time_offset; | |
268 | ||
269 | /* Frames scheduled for transmission, not handled yet */ | |
270 | int tx_queue_count[NUM_TX_QUEUES]; | |
1c33db78 AN |
271 | unsigned long queue_stop_reasons[ |
272 | NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES]; | |
c31be25a LC |
273 | |
274 | /* Frames received, not handled yet by mac80211 */ | |
275 | struct sk_buff_head deferred_rx_queue; | |
276 | ||
277 | /* Frames sent, not returned yet to mac80211 */ | |
278 | struct sk_buff_head deferred_tx_queue; | |
279 | ||
280 | struct work_struct tx_work; | |
281 | struct workqueue_struct *freezable_wq; | |
282 | ||
283 | /* Pending TX frames */ | |
72b0624f AN |
284 | unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)]; |
285 | struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS]; | |
c31be25a LC |
286 | int tx_frames_cnt; |
287 | ||
288 | /* FW Rx counter */ | |
289 | u32 rx_counter; | |
290 | ||
c31be25a LC |
291 | /* Intermediate buffer, used for packet aggregation */ |
292 | u8 *aggr_buf; | |
26a309c7 | 293 | u32 aggr_buf_size; |
c31be25a LC |
294 | |
295 | /* Reusable dummy packet template */ | |
296 | struct sk_buff *dummy_packet; | |
297 | ||
298 | /* Network stack work */ | |
299 | struct work_struct netstack_work; | |
300 | ||
301 | /* FW log buffer */ | |
302 | u8 *fwlog; | |
303 | ||
304 | /* Number of valid bytes in the FW log buffer */ | |
305 | ssize_t fwlog_size; | |
306 | ||
c83cb803 IC |
307 | /* FW log end marker */ |
308 | u32 fwlog_end; | |
309 | ||
310 | /* FW memory block size */ | |
311 | u32 fw_mem_block_size; | |
312 | ||
c31be25a LC |
313 | /* Hardware recovery work */ |
314 | struct work_struct recovery_work; | |
afbe3718 | 315 | bool watchdog_recovery; |
c31be25a | 316 | |
6b70e7eb | 317 | /* Reg domain last configuration */ |
32677b25 | 318 | u32 reg_ch_conf_last[2] __aligned(8); |
6b70e7eb VG |
319 | /* Reg domain pending configuration */ |
320 | u32 reg_ch_conf_pending[2]; | |
321 | ||
c31be25a | 322 | /* Pointer that holds DMA-friendly block for the mailbox */ |
c50a2825 | 323 | void *mbox; |
c31be25a LC |
324 | |
325 | /* The mbox event mask */ | |
326 | u32 event_mask; | |
71e996be EP |
327 | /* events to unmask only when ap interface is up */ |
328 | u32 ap_event_mask; | |
c31be25a LC |
329 | |
330 | /* Mailbox pointers */ | |
c50a2825 | 331 | u32 mbox_size; |
c31be25a LC |
332 | u32 mbox_ptr[2]; |
333 | ||
334 | /* Are we currently scanning */ | |
c50a2825 | 335 | struct wl12xx_vif *scan_wlvif; |
c31be25a LC |
336 | struct wl1271_scan scan; |
337 | struct delayed_work scan_complete_work; | |
338 | ||
dabf37db EP |
339 | struct ieee80211_vif *roc_vif; |
340 | struct delayed_work roc_complete_work; | |
5f561f68 | 341 | |
10199756 | 342 | struct wl12xx_vif *sched_vif; |
c31be25a LC |
343 | |
344 | /* The current band */ | |
57fbcce3 | 345 | enum nl80211_band band; |
c31be25a LC |
346 | |
347 | struct completion *elp_compl; | |
348 | struct delayed_work elp_work; | |
349 | ||
350 | /* in dBm */ | |
351 | int power_level; | |
352 | ||
353 | struct wl1271_stats stats; | |
354 | ||
2e07d028 | 355 | __le32 *buffer_32; |
c31be25a LC |
356 | u32 buffer_cmd; |
357 | u32 buffer_busyword[WL1271_BUSY_WORD_CNT]; | |
358 | ||
75fb4df7 EP |
359 | void *raw_fw_status; |
360 | struct wl_fw_status *fw_status; | |
c31be25a LC |
361 | struct wl1271_tx_hw_res_if *tx_res_if; |
362 | ||
363 | /* Current chipset configuration */ | |
e87288f0 | 364 | struct wlcore_conf conf; |
c31be25a LC |
365 | |
366 | bool sg_enabled; | |
367 | ||
368 | bool enable_11a; | |
369 | ||
c108c905 LC |
370 | int recovery_count; |
371 | ||
c31be25a LC |
372 | /* Most recently reported noise in dBm */ |
373 | s8 noise; | |
374 | ||
375 | /* bands supported by this instance of wl12xx */ | |
091185d6 | 376 | struct ieee80211_supported_band bands[WLCORE_NUM_BANDS]; |
c31be25a | 377 | |
c31be25a LC |
378 | /* |
379 | * wowlan trigger was configured during suspend. | |
380 | * (currently, only "ANY" trigger is supported) | |
381 | */ | |
382 | bool wow_enabled; | |
383 | bool irq_wake_enabled; | |
384 | ||
385 | /* | |
386 | * AP-mode - links indexed by HLID. The global and broadcast links | |
387 | * are always active. | |
388 | */ | |
da08fdfa | 389 | struct wl1271_link links[WLCORE_MAX_LINKS]; |
c31be25a | 390 | |
9a100968 AN |
391 | /* number of currently active links */ |
392 | int active_link_count; | |
393 | ||
0e810479 | 394 | /* Fast/slow links bitmap according to FW */ |
5e74b3aa | 395 | unsigned long fw_fast_lnk_map; |
0e810479 | 396 | |
c31be25a | 397 | /* AP-mode - a bitmap of links currently in PS mode according to FW */ |
5e74b3aa | 398 | unsigned long ap_fw_ps_map; |
c31be25a LC |
399 | |
400 | /* AP-mode - a bitmap of links currently in PS mode in mac80211 */ | |
401 | unsigned long ap_ps_map; | |
402 | ||
403 | /* Quirks of specific hardware revisions */ | |
404 | unsigned int quirks; | |
405 | ||
c31be25a LC |
406 | /* number of currently active RX BA sessions */ |
407 | int ba_rx_session_count; | |
408 | ||
d21553f8 IC |
409 | /* Maximum number of supported RX BA sessions */ |
410 | int ba_rx_session_count_max; | |
411 | ||
c31be25a LC |
412 | /* AP-mode - number of currently connected stations */ |
413 | int active_sta_count; | |
414 | ||
bc566f92 AN |
415 | /* Flag determining whether AP should broadcast OFDM-only rates */ |
416 | bool ofdm_only_ap; | |
417 | ||
c31be25a LC |
418 | /* last wlvif we transmitted from */ |
419 | struct wl12xx_vif *last_wlvif; | |
420 | ||
421 | /* work to fire when Tx is stuck */ | |
422 | struct delayed_work tx_watchdog_work; | |
423 | ||
424 | struct wlcore_ops *ops; | |
25a43d78 LC |
425 | /* pointer to the lower driver partition table */ |
426 | const struct wlcore_partition_set *ptable; | |
00782136 LC |
427 | /* pointer to the lower driver register table */ |
428 | const int *rtable; | |
6f7dd16c LC |
429 | /* name of the firmwares to load - for PLT, single role, multi-role */ |
430 | const char *plt_fw_name; | |
431 | const char *sr_fw_name; | |
432 | const char *mr_fw_name; | |
96e0c683 | 433 | |
78e28062 EP |
434 | u8 scan_templ_id_2_4; |
435 | u8 scan_templ_id_5; | |
436 | u8 sched_scan_templ_id_2_4; | |
437 | u8 sched_scan_templ_id_5; | |
0a1c720c | 438 | u8 max_channels_5; |
78e28062 | 439 | |
96e0c683 AN |
440 | /* per-chip-family private structure */ |
441 | void *priv; | |
72b0624f AN |
442 | |
443 | /* number of TX descriptors the HW supports. */ | |
444 | u32 num_tx_desc; | |
0afd04e5 AN |
445 | /* number of RX descriptors the HW supports. */ |
446 | u32 num_rx_desc; | |
da08fdfa EP |
447 | /* number of links the HW supports */ |
448 | u8 num_links; | |
32f0fd5b EP |
449 | /* max stations a single AP can support */ |
450 | u8 max_ap_stations; | |
3edab305 | 451 | |
43a8bc5a AN |
452 | /* translate HW Tx rates to standard rate-indices */ |
453 | const u8 **band_rate_to_idx; | |
454 | ||
455 | /* size of table for HW rates that can be received from chip */ | |
456 | u8 hw_tx_rate_tbl_size; | |
457 | ||
458 | /* this HW rate and below are considered HT rates for this chip */ | |
459 | u8 hw_min_ht_rate; | |
4a589a6f AN |
460 | |
461 | /* HW HT (11n) capabilities */ | |
091185d6 | 462 | struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS]; |
6bac40a6 | 463 | |
1cd91b2c GM |
464 | /* the current dfs region */ |
465 | enum nl80211_dfs_regions dfs_region; | |
8cf77e17 | 466 | bool radar_debug_mode; |
1cd91b2c | 467 | |
6bac40a6 | 468 | /* size of the private FW status data */ |
75fb4df7 | 469 | size_t fw_status_len; |
6bac40a6 | 470 | size_t fw_status_priv_len; |
dbe0a8cd ES |
471 | |
472 | /* RX Data filter rule state - enabled/disabled */ | |
02d0727c | 473 | unsigned long rx_filter_enabled[BITS_TO_LONGS(WL1271_MAX_RX_FILTERS)]; |
83d08d3f | 474 | |
7140df6e LC |
475 | /* size of the private static data */ |
476 | size_t static_data_priv_len; | |
477 | ||
83d08d3f AN |
478 | /* the current channel type */ |
479 | enum nl80211_channel_type channel_type; | |
2c38849f AN |
480 | |
481 | /* mutex for protecting the tx_flush function */ | |
482 | struct mutex flush_mutex; | |
26b5858a LC |
483 | |
484 | /* sleep auth value currently configured to FW */ | |
485 | int sleep_auth; | |
4a1ccce8 | 486 | |
f4afbed9 AN |
487 | /* the number of allocated MAC addresses in this chip */ |
488 | int num_mac_addr; | |
489 | ||
8675f9ab LC |
490 | /* minimum FW version required for the driver to work in single-role */ |
491 | unsigned int min_sr_fw_ver[NUM_FW_VER]; | |
492 | ||
493 | /* minimum FW version required for the driver to work in multi-role */ | |
494 | unsigned int min_mr_fw_ver[NUM_FW_VER]; | |
6f8d6b20 IY |
495 | |
496 | struct completion nvs_loading_complete; | |
de40750f | 497 | |
abf0b249 EP |
498 | /* interface combinations supported by the hw */ |
499 | const struct ieee80211_iface_combination *iface_combinations; | |
500 | u8 n_iface_combinations; | |
d1c54096 GM |
501 | |
502 | /* dynamic fw traces */ | |
503 | u32 dynamic_fw_traces; | |
c31be25a | 504 | }; |
ffeb501c | 505 | |
b74324d1 BP |
506 | int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev); |
507 | int wlcore_remove(struct platform_device *pdev); | |
c50a2825 EP |
508 | struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size, |
509 | u32 mbox_size); | |
ffeb501c | 510 | int wlcore_free_hw(struct wl1271 *wl); |
a1c597f2 AN |
511 | int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd, |
512 | struct ieee80211_vif *vif, | |
513 | struct ieee80211_sta *sta, | |
514 | struct ieee80211_key_conf *key_conf); | |
6b70e7eb | 515 | void wlcore_regdomain_config(struct wl1271 *wl); |
187e52cc AN |
516 | void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif, |
517 | struct wl1271_station *wl_sta, bool in_conn); | |
ffeb501c | 518 | |
fa2adfcd | 519 | static inline void |
57fbcce3 | 520 | wlcore_set_ht_cap(struct wl1271 *wl, enum nl80211_band band, |
fa2adfcd AN |
521 | struct ieee80211_sta_ht_cap *ht_cap) |
522 | { | |
523 | memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap)); | |
524 | } | |
525 | ||
af4e94c5 LC |
526 | /* Tell wlcore not to care about this element when checking the version */ |
527 | #define WLCORE_FW_VER_IGNORE -1 | |
528 | ||
4a1ccce8 AN |
529 | static inline void |
530 | wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip, | |
8675f9ab LC |
531 | unsigned int iftype_sr, unsigned int major_sr, |
532 | unsigned int subtype_sr, unsigned int minor_sr, | |
533 | unsigned int iftype_mr, unsigned int major_mr, | |
534 | unsigned int subtype_mr, unsigned int minor_mr) | |
4a1ccce8 | 535 | { |
8675f9ab LC |
536 | wl->min_sr_fw_ver[FW_VER_CHIP] = chip; |
537 | wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr; | |
538 | wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr; | |
539 | wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr; | |
540 | wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr; | |
541 | ||
542 | wl->min_mr_fw_ver[FW_VER_CHIP] = chip; | |
543 | wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr; | |
544 | wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr; | |
545 | wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr; | |
546 | wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr; | |
4a1ccce8 AN |
547 | } |
548 | ||
00782136 LC |
549 | /* Firmware image load chunk size */ |
550 | #define CHUNK_SIZE 16384 | |
551 | ||
6f7dd16c LC |
552 | /* Quirks */ |
553 | ||
554 | /* Each RX/TX transaction requires an end-of-transaction transfer */ | |
555 | #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0) | |
556 | ||
18eab430 EP |
557 | /* the first start_role(sta) sometimes doesn't work on wl12xx */ |
558 | #define WLCORE_QUIRK_START_STA_FAILS BIT(1) | |
559 | ||
6f7dd16c | 560 | /* wl127x and SPI don't support SDIO block size alignment */ |
f83985bb | 561 | #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2) |
6f7dd16c | 562 | |
5766435e AN |
563 | /* means aggregated Rx packets are aligned to a SDIO block */ |
564 | #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3) | |
565 | ||
6f7dd16c LC |
566 | /* Older firmwares did not implement the FW logger over bus feature */ |
567 | #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4) | |
568 | ||
d203e59c LC |
569 | /* Older firmwares use an old NVS format */ |
570 | #define WLCORE_QUIRK_LEGACY_NVS BIT(5) | |
571 | ||
9fccc82e IR |
572 | /* pad only the last frame in the aggregate buffer */ |
573 | #define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7) | |
574 | ||
2c0133a4 AN |
575 | /* extra header space is required for TKIP */ |
576 | #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8) | |
577 | ||
01b3c0e4 VG |
578 | /* Some firmwares not support sched scans while connected */ |
579 | #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9) | |
580 | ||
3df74f46 YD |
581 | /* separate probe response templates for one-shot and sched scans */ |
582 | #define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10) | |
583 | ||
6b70e7eb VG |
584 | /* Firmware requires reg domain configuration for active calibration */ |
585 | #define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11) | |
586 | ||
3ea186d1 AN |
587 | /* The FW only support a zero session id for AP */ |
588 | #define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12) | |
00782136 LC |
589 | |
590 | /* TODO: move all these common registers and values elsewhere */ | |
591 | #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC | |
592 | ||
593 | /* ELP register commands */ | |
594 | #define ELPCTRL_WAKE_UP 0x1 | |
595 | #define ELPCTRL_WAKE_UP_WLAN_READY 0x5 | |
596 | #define ELPCTRL_SLEEP 0x0 | |
597 | /* ELP WLAN_READY bit */ | |
598 | #define ELPCTRL_WLAN_READY 0x2 | |
599 | ||
600 | /************************************************************************* | |
601 | ||
602 | Interrupt Trigger Register (Host -> WiLink) | |
603 | ||
604 | **************************************************************************/ | |
605 | ||
606 | /* Hardware to Embedded CPU Interrupts - first 32-bit register set */ | |
607 | ||
00782136 LC |
608 | /* |
609 | * The host sets this bit to inform the Wlan | |
610 | * FW that a TX packet is in the XFER | |
611 | * Buffer #0. | |
612 | */ | |
613 | #define INTR_TRIG_TX_PROC0 BIT(2) | |
614 | ||
615 | /* | |
616 | * The host sets this bit to inform the FW | |
617 | * that it read a packet from RX XFER | |
618 | * Buffer #0. | |
619 | */ | |
620 | #define INTR_TRIG_RX_PROC0 BIT(3) | |
621 | ||
622 | #define INTR_TRIG_DEBUG_ACK BIT(4) | |
623 | ||
624 | #define INTR_TRIG_STATE_CHANGED BIT(5) | |
625 | ||
626 | /* Hardware to Embedded CPU Interrupts - second 32-bit register set */ | |
627 | ||
628 | /* | |
629 | * The host sets this bit to inform the FW | |
630 | * that it read a packet from RX XFER | |
631 | * Buffer #1. | |
632 | */ | |
633 | #define INTR_TRIG_RX_PROC1 BIT(17) | |
634 | ||
635 | /* | |
636 | * The host sets this bit to inform the Wlan | |
637 | * hardware that a TX packet is in the XFER | |
638 | * Buffer #1. | |
639 | */ | |
640 | #define INTR_TRIG_TX_PROC1 BIT(18) | |
641 | ||
642 | #define ACX_SLV_SOFT_RESET_BIT BIT(1) | |
643 | #define SOFT_RESET_MAX_TIME 1000000 | |
644 | #define SOFT_RESET_STALL_TIME 1000 | |
645 | ||
646 | #define ECPU_CONTROL_HALT 0x00000101 | |
b2ba99ff | 647 | |
6f7dd16c LC |
648 | #define WELP_ARM_COMMAND_VAL 0x4 |
649 | ||
b2ba99ff | 650 | #endif /* __WLCORE_H__ */ |