projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| f5fc0f86 LC |
1 | /* |
| 2 | * This file is part of wl1271 | |
| 3 | * | |
| 4 | * Copyright (C) 1998-2009 Texas Instruments. All rights reserved. | |
| 5 | * Copyright (C) 2008-2009 Nokia Corporation | |
| 6 | * | |
| 7 | * Contact: Luciano Coelho <luciano.coelho@nokia.com> | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License | |
| 11 | * version 2 as published by the Free Software Foundation. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, but | |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 16 | * General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
| 21 | * 02110-1301 USA | |
| 22 | * | |
| 23 | */ | |
| 24 | ||
| 00d20100 SL |
25 | #ifndef __RX_H__ |
| 26 | #define __RX_H__ | |
| f5fc0f86 LC |
27 | |
| 28 | #include <linux/bitops.h> | |
| 29 | ||
| 30 | #define WL1271_RX_MAX_RSSI -30 | |
| 31 | #define WL1271_RX_MIN_RSSI -95 | |
| 32 | ||
| 5d6af28a GM |
33 | #define RSSI_LEVEL_BITMASK 0x7F |
| 34 | #define ANT_DIVERSITY_BITMASK BIT(7) | |
| 35 | ||
| f5fc0f86 LC |
36 | #define SHORT_PREAMBLE_BIT BIT(0) |
| 37 | #define OFDM_RATE_BIT BIT(6) | |
| 38 | #define PBCC_RATE_BIT BIT(7) | |
| 39 | ||
| 40 | #define PLCP_HEADER_LENGTH 8 | |
| 41 | #define RX_DESC_PACKETID_SHIFT 11 | |
| 42 | #define RX_MAX_PACKET_ID 3 | |
| 43 | ||
| f5fc0f86 LC |
44 | #define RX_DESC_VALID_FCS 0x0001 |
| 45 | #define RX_DESC_MATCH_RXADDR1 0x0002 | |
| 46 | #define RX_DESC_MCAST 0x0004 | |
| 47 | #define RX_DESC_STAINTIM 0x0008 | |
| 48 | #define RX_DESC_VIRTUAL_BM 0x0010 | |
| 49 | #define RX_DESC_BCAST 0x0020 | |
| 50 | #define RX_DESC_MATCH_SSID 0x0040 | |
| 51 | #define RX_DESC_MATCH_BSSID 0x0080 | |
| 52 | #define RX_DESC_ENCRYPTION_MASK 0x0300 | |
| 53 | #define RX_DESC_MEASURMENT 0x0400 | |
| 54 | #define RX_DESC_SEQNUM_MASK 0x1800 | |
| 55 | #define RX_DESC_MIC_FAIL 0x2000 | |
| 56 | #define RX_DESC_DECRYPT_FAIL 0x4000 | |
| 57 | ||
| 58 | /* | |
| 59 | * RX Descriptor flags: | |
| 60 | * | |
| 61 | * Bits 0-1 - band | |
| 62 | * Bit 2 - STBC | |
| 63 | * Bit 3 - A-MPDU | |
| 64 | * Bit 4 - HT | |
| 65 | * Bits 5-7 - encryption | |
| 66 | */ | |
| 67 | #define WL1271_RX_DESC_BAND_MASK 0x03 | |
| 68 | #define WL1271_RX_DESC_ENCRYPT_MASK 0xE0 | |
| 69 | ||
| 70 | #define WL1271_RX_DESC_BAND_BG 0x00 | |
| 71 | #define WL1271_RX_DESC_BAND_J 0x01 | |
| 72 | #define WL1271_RX_DESC_BAND_A 0x02 | |
| 73 | ||
| 74 | #define WL1271_RX_DESC_STBC BIT(2) | |
| 75 | #define WL1271_RX_DESC_A_MPDU BIT(3) | |
| 76 | #define WL1271_RX_DESC_HT BIT(4) | |
| 77 | ||
| 78 | #define WL1271_RX_DESC_ENCRYPT_WEP 0x20 | |
| 79 | #define WL1271_RX_DESC_ENCRYPT_TKIP 0x40 | |
| 80 | #define WL1271_RX_DESC_ENCRYPT_AES 0x60 | |
| 81 | #define WL1271_RX_DESC_ENCRYPT_GEM 0x80 | |
| 82 | ||
| 83 | /* | |
| 84 | * RX Descriptor status | |
| 85 | * | |
| beb6c880 AN |
86 | * Bits 0-2 - error code |
| 87 | * Bits 3-5 - process_id tag (AP mode FW) | |
| 88 | * Bits 6-7 - reserved | |
| f5fc0f86 | 89 | */ |
| 387116b8 | 90 | #define WL1271_RX_DESC_STATUS_MASK 0x07 |
| f5fc0f86 LC |
91 | |
| 92 | #define WL1271_RX_DESC_SUCCESS 0x00 | |
| 93 | #define WL1271_RX_DESC_DECRYPT_FAIL 0x01 | |
| 94 | #define WL1271_RX_DESC_MIC_FAIL 0x02 | |
| f5fc0f86 | 95 | |
| 0a1d3abc SL |
96 | #define RX_MEM_BLOCK_MASK 0xFF |
| 97 | #define RX_BUF_SIZE_MASK 0xFFF00 | |
| 98 | #define RX_BUF_SIZE_SHIFT_DIV 6 | |
| 5766435e AN |
99 | #define ALIGNED_RX_BUF_SIZE_MASK 0xFFFF00 |
| 100 | #define ALIGNED_RX_BUF_SIZE_SHIFT 8 | |
| 101 | ||
| 0a1d3abc SL |
102 | /* If set, the start of IP payload is not 4 bytes aligned */ |
| 103 | #define RX_BUF_UNALIGNED_PAYLOAD BIT(20) | |
| f5fc0f86 | 104 | |
| 9c809f88 AN |
105 | /* If set, the buffer was padded by the FW to be 4 bytes aligned */ |
| 106 | #define RX_BUF_PADDED_PAYLOAD BIT(30) | |
| 107 | ||
| 04414e2a ES |
108 | /* |
| 109 | * Account for the padding inserted by the FW in case of RX_ALIGNMENT | |
| 110 | * or for fixing alignment in case the packet wasn't aligned. | |
| 111 | */ | |
| 112 | #define RX_BUF_ALIGN 2 | |
| 113 | ||
| cd70f6a4 AN |
114 | /* Describes the alignment state of a Rx buffer */ |
| 115 | enum wl_rx_buf_align { | |
| 116 | WLCORE_RX_BUF_ALIGNED, | |
| 117 | WLCORE_RX_BUF_UNALIGNED, | |
| 118 | WLCORE_RX_BUF_PADDED, | |
| 119 | }; | |
| 120 | ||
| 95dac04f IY |
121 | enum { |
| 122 | WL12XX_RX_CLASS_UNKNOWN, | |
| 123 | WL12XX_RX_CLASS_MANAGEMENT, | |
| 124 | WL12XX_RX_CLASS_DATA, | |
| 125 | WL12XX_RX_CLASS_QOS_DATA, | |
| 126 | WL12XX_RX_CLASS_BCN_PRBRSP, | |
| 127 | WL12XX_RX_CLASS_EAPOL, | |
| 128 | WL12XX_RX_CLASS_BA_EVENT, | |
| 129 | WL12XX_RX_CLASS_AMSDU, | |
| 130 | WL12XX_RX_CLASS_LOGGER, | |
| 131 | }; | |
| 132 | ||
| f5fc0f86 | 133 | struct wl1271_rx_descriptor { |
| d0f63b20 | 134 | __le16 length; |
| f5fc0f86 LC |
135 | u8 status; |
| 136 | u8 flags; | |
| 137 | u8 rate; | |
| 138 | u8 channel; | |
| 139 | s8 rssi; | |
| 140 | u8 snr; | |
| d0f63b20 | 141 | __le32 timestamp; |
| f5fc0f86 | 142 | u8 packet_class; |
| 79b122dc | 143 | u8 hlid; |
| f5fc0f86 LC |
144 | u8 pad_len; |
| 145 | u8 reserved; | |
| ba2d3587 | 146 | } __packed; |
| f5fc0f86 | 147 | |
| 75fb4df7 | 148 | int wlcore_rx(struct wl1271 *wl, struct wl_fw_status *status); |
| 57fbcce3 | 149 | u8 wl1271_rate_to_idx(int rate, enum nl80211_band band); |
| dbe0a8cd ES |
150 | int wl1271_rx_filter_enable(struct wl1271 *wl, |
| 151 | int index, bool enable, | |
| 152 | struct wl12xx_rx_filter *filter); | |
| c439a1ca | 153 | int wl1271_rx_filter_clear_all(struct wl1271 *wl); |
| f5fc0f86 LC |
154 | |
| 155 | #endif |