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0c817338 LF |
1 | /****************************************************************************** |
2 | * | |
9003a4ab | 3 | * Copyright(c) 2009-2012 Realtek Corporation. |
0c817338 LF |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #ifndef __RTL92CE_TRX_H__ | |
31 | #define __RTL92CE_TRX_H__ | |
32 | ||
33 | #define TX_DESC_SIZE 64 | |
34 | #define TX_DESC_AGGR_SUBFRAME_SIZE 32 | |
35 | ||
36 | #define RX_DESC_SIZE 32 | |
37 | #define RX_DRV_INFO_SIZE_UNIT 8 | |
38 | ||
39 | #define TX_DESC_NEXT_DESC_OFFSET 40 | |
40 | #define USB_HWDESC_HEADER_LEN 32 | |
41 | #define CRCLENGTH 4 | |
42 | ||
17c9ac62 LF |
43 | /* Define a macro that takes a le32 word, converts it to host ordering, |
44 | * right shifts by a specified count, creates a mask of the specified | |
45 | * bit count, and extracts that number of bits. | |
46 | */ | |
47 | ||
48 | #define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \ | |
49 | ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \ | |
50 | BIT_LEN_MASK_32(__mask)) | |
51 | ||
52 | /* Define a macro that clears a bit field in an le32 word and | |
53 | * sets the specified value into that bit field. The resulting | |
54 | * value remains in le32 ordering; however, it is properly converted | |
55 | * to host ordering for the clear and set operations before conversion | |
56 | * back to le32. | |
57 | */ | |
58 | ||
59 | #define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \ | |
60 | (*(__le32 *)(__pdesc) = \ | |
61 | (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \ | |
62 | (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \ | |
63 | (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift))))); | |
64 | ||
65 | /* macros to read/write various fields in RX or TX descriptors */ | |
66 | ||
0c817338 | 67 | #define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ |
17c9ac62 | 68 | SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val) |
0c817338 | 69 | #define SET_TX_DESC_OFFSET(__pdesc, __val) \ |
17c9ac62 | 70 | SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val) |
0c817338 | 71 | #define SET_TX_DESC_BMC(__pdesc, __val) \ |
17c9ac62 | 72 | SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val) |
0c817338 | 73 | #define SET_TX_DESC_HTC(__pdesc, __val) \ |
17c9ac62 | 74 | SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val) |
0c817338 | 75 | #define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ |
17c9ac62 | 76 | SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val) |
0c817338 | 77 | #define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ |
17c9ac62 | 78 | SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val) |
0c817338 | 79 | #define SET_TX_DESC_LINIP(__pdesc, __val) \ |
17c9ac62 | 80 | SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val) |
0c817338 | 81 | #define SET_TX_DESC_NO_ACM(__pdesc, __val) \ |
17c9ac62 | 82 | SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val) |
0c817338 | 83 | #define SET_TX_DESC_GF(__pdesc, __val) \ |
17c9ac62 | 84 | SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) |
0c817338 | 85 | #define SET_TX_DESC_OWN(__pdesc, __val) \ |
17c9ac62 | 86 | SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) |
0c817338 LF |
87 | |
88 | #define GET_TX_DESC_PKT_SIZE(__pdesc) \ | |
17c9ac62 | 89 | SHIFT_AND_MASK_LE(__pdesc, 0, 16) |
0c817338 | 90 | #define GET_TX_DESC_OFFSET(__pdesc) \ |
17c9ac62 | 91 | SHIFT_AND_MASK_LE(__pdesc, 16, 8) |
0c817338 | 92 | #define GET_TX_DESC_BMC(__pdesc) \ |
17c9ac62 | 93 | SHIFT_AND_MASK_LE(__pdesc, 24, 1) |
0c817338 | 94 | #define GET_TX_DESC_HTC(__pdesc) \ |
17c9ac62 | 95 | SHIFT_AND_MASK_LE(__pdesc, 25, 1) |
0c817338 | 96 | #define GET_TX_DESC_LAST_SEG(__pdesc) \ |
17c9ac62 | 97 | SHIFT_AND_MASK_LE(__pdesc, 26, 1) |
0c817338 | 98 | #define GET_TX_DESC_FIRST_SEG(__pdesc) \ |
17c9ac62 | 99 | SHIFT_AND_MASK_LE(__pdesc, 27, 1) |
0c817338 | 100 | #define GET_TX_DESC_LINIP(__pdesc) \ |
17c9ac62 | 101 | SHIFT_AND_MASK_LE(__pdesc, 28, 1) |
0c817338 | 102 | #define GET_TX_DESC_NO_ACM(__pdesc) \ |
17c9ac62 | 103 | SHIFT_AND_MASK_LE(__pdesc, 29, 1) |
0c817338 | 104 | #define GET_TX_DESC_GF(__pdesc) \ |
17c9ac62 | 105 | SHIFT_AND_MASK_LE(__pdesc, 30, 1) |
0c817338 | 106 | #define GET_TX_DESC_OWN(__pdesc) \ |
17c9ac62 | 107 | SHIFT_AND_MASK_LE(__pdesc, 31, 1) |
0c817338 LF |
108 | |
109 | #define SET_TX_DESC_MACID(__pdesc, __val) \ | |
17c9ac62 | 110 | SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val) |
0c817338 | 111 | #define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \ |
17c9ac62 | 112 | SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val) |
0c817338 | 113 | #define SET_TX_DESC_BK(__pdesc, __val) \ |
17c9ac62 | 114 | SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val) |
0c817338 | 115 | #define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \ |
17c9ac62 | 116 | SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val) |
0c817338 | 117 | #define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ |
17c9ac62 | 118 | SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val) |
0c817338 | 119 | #define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \ |
17c9ac62 | 120 | SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val) |
0c817338 | 121 | #define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \ |
17c9ac62 | 122 | SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val) |
0c817338 | 123 | #define SET_TX_DESC_PIFS(__pdesc, __val) \ |
17c9ac62 | 124 | SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val) |
0c817338 | 125 | #define SET_TX_DESC_RATE_ID(__pdesc, __val) \ |
17c9ac62 | 126 | SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val) |
0c817338 | 127 | #define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \ |
17c9ac62 | 128 | SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val) |
0c817338 | 129 | #define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \ |
17c9ac62 | 130 | SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val) |
0c817338 | 131 | #define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ |
17c9ac62 | 132 | SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val) |
0c817338 | 133 | #define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ |
17c9ac62 | 134 | SET_BITS_OFFSET_LE(__pdesc+4, 24, 8, __val) |
0c817338 LF |
135 | |
136 | #define GET_TX_DESC_MACID(__pdesc) \ | |
17c9ac62 | 137 | SHIFT_AND_MASK_LE(__pdesc+4, 0, 5) |
0c817338 | 138 | #define GET_TX_DESC_AGG_ENABLE(__pdesc) \ |
17c9ac62 | 139 | SHIFT_AND_MASK_LE(__pdesc+4, 5, 1) |
0c817338 | 140 | #define GET_TX_DESC_AGG_BREAK(__pdesc) \ |
17c9ac62 | 141 | SHIFT_AND_MASK_LE(__pdesc+4, 6, 1) |
0c817338 | 142 | #define GET_TX_DESC_RDG_ENABLE(__pdesc) \ |
17c9ac62 | 143 | SHIFT_AND_MASK_LE(__pdesc+4, 7, 1) |
0c817338 | 144 | #define GET_TX_DESC_QUEUE_SEL(__pdesc) \ |
17c9ac62 | 145 | SHIFT_AND_MASK_LE(__pdesc+4, 8, 5) |
0c817338 | 146 | #define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \ |
17c9ac62 | 147 | SHIFT_AND_MASK_LE(__pdesc+4, 13, 1) |
0c817338 | 148 | #define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \ |
17c9ac62 | 149 | SHIFT_AND_MASK_LE(__pdesc+4, 14, 1) |
0c817338 | 150 | #define GET_TX_DESC_PIFS(__pdesc) \ |
17c9ac62 | 151 | SHIFT_AND_MASK_LE(__pdesc+4, 15, 1) |
0c817338 | 152 | #define GET_TX_DESC_RATE_ID(__pdesc) \ |
17c9ac62 | 153 | SHIFT_AND_MASK_LE(__pdesc+4, 16, 4) |
0c817338 | 154 | #define GET_TX_DESC_NAV_USE_HDR(__pdesc) \ |
17c9ac62 | 155 | SHIFT_AND_MASK_LE(__pdesc+4, 20, 1) |
0c817338 | 156 | #define GET_TX_DESC_EN_DESC_ID(__pdesc) \ |
17c9ac62 | 157 | SHIFT_AND_MASK_LE(__pdesc+4, 21, 1) |
0c817338 | 158 | #define GET_TX_DESC_SEC_TYPE(__pdesc) \ |
17c9ac62 | 159 | SHIFT_AND_MASK_LE(__pdesc+4, 22, 2) |
0c817338 | 160 | #define GET_TX_DESC_PKT_OFFSET(__pdesc) \ |
17c9ac62 | 161 | SHIFT_AND_MASK_LE(__pdesc+4, 24, 8) |
0c817338 LF |
162 | |
163 | #define SET_TX_DESC_RTS_RC(__pdesc, __val) \ | |
17c9ac62 | 164 | SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val) |
0c817338 | 165 | #define SET_TX_DESC_DATA_RC(__pdesc, __val) \ |
17c9ac62 | 166 | SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val) |
0c817338 | 167 | #define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \ |
17c9ac62 | 168 | SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val) |
0c817338 | 169 | #define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ |
17c9ac62 | 170 | SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val) |
0c817338 | 171 | #define SET_TX_DESC_RAW(__pdesc, __val) \ |
17c9ac62 | 172 | SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val) |
0c817338 | 173 | #define SET_TX_DESC_CCX(__pdesc, __val) \ |
17c9ac62 | 174 | SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val) |
0c817338 | 175 | #define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \ |
17c9ac62 | 176 | SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val) |
0c817338 | 177 | #define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \ |
17c9ac62 | 178 | SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val) |
0c817338 | 179 | #define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \ |
17c9ac62 | 180 | SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val) |
0c817338 | 181 | #define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \ |
17c9ac62 | 182 | SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val) |
0c817338 | 183 | #define SET_TX_DESC_TX_ANTL(__pdesc, __val) \ |
17c9ac62 | 184 | SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val) |
0c817338 | 185 | #define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \ |
17c9ac62 | 186 | SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val) |
0c817338 LF |
187 | |
188 | #define GET_TX_DESC_RTS_RC(__pdesc) \ | |
17c9ac62 | 189 | SHIFT_AND_MASK_LE(__pdesc+8, 0, 6) |
0c817338 | 190 | #define GET_TX_DESC_DATA_RC(__pdesc) \ |
17c9ac62 | 191 | SHIFT_AND_MASK_LE(__pdesc+8, 6, 6) |
0c817338 | 192 | #define GET_TX_DESC_BAR_RTY_TH(__pdesc) \ |
17c9ac62 | 193 | SHIFT_AND_MASK_LE(__pdesc+8, 14, 2) |
0c817338 | 194 | #define GET_TX_DESC_MORE_FRAG(__pdesc) \ |
17c9ac62 | 195 | SHIFT_AND_MASK_LE(__pdesc+8, 17, 1) |
0c817338 | 196 | #define GET_TX_DESC_RAW(__pdesc) \ |
17c9ac62 | 197 | SHIFT_AND_MASK_LE(__pdesc+8, 18, 1) |
0c817338 | 198 | #define GET_TX_DESC_CCX(__pdesc) \ |
17c9ac62 | 199 | SHIFT_AND_MASK_LE(__pdesc+8, 19, 1) |
0c817338 | 200 | #define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \ |
17c9ac62 | 201 | SHIFT_AND_MASK_LE(__pdesc+8, 20, 3) |
0c817338 | 202 | #define GET_TX_DESC_ANTSEL_A(__pdesc) \ |
17c9ac62 | 203 | SHIFT_AND_MASK_LE(__pdesc+8, 24, 1) |
0c817338 | 204 | #define GET_TX_DESC_ANTSEL_B(__pdesc) \ |
17c9ac62 | 205 | SHIFT_AND_MASK_LE(__pdesc+8, 25, 1) |
0c817338 | 206 | #define GET_TX_DESC_TX_ANT_CCK(__pdesc) \ |
17c9ac62 | 207 | SHIFT_AND_MASK_LE(__pdesc+8, 26, 2) |
0c817338 | 208 | #define GET_TX_DESC_TX_ANTL(__pdesc) \ |
17c9ac62 | 209 | SHIFT_AND_MASK_LE(__pdesc+8, 28, 2) |
0c817338 | 210 | #define GET_TX_DESC_TX_ANT_HT(__pdesc) \ |
17c9ac62 | 211 | SHIFT_AND_MASK_LE(__pdesc+8, 30, 2) |
0c817338 LF |
212 | |
213 | #define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \ | |
17c9ac62 | 214 | SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val) |
0c817338 | 215 | #define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ |
17c9ac62 | 216 | SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val) |
0c817338 | 217 | #define SET_TX_DESC_SEQ(__pdesc, __val) \ |
17c9ac62 | 218 | SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val) |
0c817338 | 219 | #define SET_TX_DESC_PKT_ID(__pdesc, __val) \ |
17c9ac62 | 220 | SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val) |
0c817338 LF |
221 | |
222 | #define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \ | |
17c9ac62 | 223 | SHIFT_AND_MASK_LE(__pdesc+12, 0, 8) |
0c817338 | 224 | #define GET_TX_DESC_TAIL_PAGE(__pdesc) \ |
17c9ac62 | 225 | SHIFT_AND_MASK_LE(__pdesc+12, 8, 8) |
0c817338 | 226 | #define GET_TX_DESC_SEQ(__pdesc) \ |
17c9ac62 | 227 | SHIFT_AND_MASK_LE(__pdesc+12, 16, 12) |
0c817338 | 228 | #define GET_TX_DESC_PKT_ID(__pdesc) \ |
17c9ac62 | 229 | SHIFT_AND_MASK_LE(__pdesc+12, 28, 4) |
0c817338 LF |
230 | |
231 | #define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ | |
17c9ac62 | 232 | SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val) |
0c817338 | 233 | #define SET_TX_DESC_AP_DCFE(__pdesc, __val) \ |
17c9ac62 | 234 | SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val) |
0c817338 | 235 | #define SET_TX_DESC_QOS(__pdesc, __val) \ |
17c9ac62 | 236 | SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val) |
0c817338 | 237 | #define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \ |
17c9ac62 | 238 | SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val) |
0c817338 | 239 | #define SET_TX_DESC_USE_RATE(__pdesc, __val) \ |
17c9ac62 | 240 | SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val) |
0c817338 | 241 | #define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \ |
17c9ac62 | 242 | SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val) |
0c817338 | 243 | #define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ |
17c9ac62 | 244 | SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val) |
0c817338 | 245 | #define SET_TX_DESC_CTS2SELF(__pdesc, __val) \ |
17c9ac62 | 246 | SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val) |
0c817338 | 247 | #define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ |
17c9ac62 | 248 | SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val) |
0c817338 | 249 | #define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \ |
17c9ac62 | 250 | SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val) |
0c817338 | 251 | #define SET_TX_DESC_PORT_ID(__pdesc, __val) \ |
17c9ac62 | 252 | SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val) |
0c817338 | 253 | #define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \ |
17c9ac62 | 254 | SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val) |
0c817338 | 255 | #define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \ |
17c9ac62 | 256 | SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val) |
0c817338 | 257 | #define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ |
17c9ac62 | 258 | SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val) |
0c817338 | 259 | #define SET_TX_DESC_TX_STBC(__pdesc, __val) \ |
17c9ac62 | 260 | SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val) |
0c817338 | 261 | #define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \ |
17c9ac62 | 262 | SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val) |
0c817338 | 263 | #define SET_TX_DESC_DATA_BW(__pdesc, __val) \ |
17c9ac62 | 264 | SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val) |
0c817338 | 265 | #define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ |
17c9ac62 | 266 | SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val) |
0c817338 | 267 | #define SET_TX_DESC_RTS_BW(__pdesc, __val) \ |
17c9ac62 | 268 | SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val) |
0c817338 | 269 | #define SET_TX_DESC_RTS_SC(__pdesc, __val) \ |
17c9ac62 | 270 | SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val) |
0c817338 | 271 | #define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ |
17c9ac62 | 272 | SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val) |
0c817338 LF |
273 | |
274 | #define GET_TX_DESC_RTS_RATE(__pdesc) \ | |
17c9ac62 | 275 | SHIFT_AND_MASK_LE(__pdesc+16, 0, 5) |
0c817338 | 276 | #define GET_TX_DESC_AP_DCFE(__pdesc) \ |
17c9ac62 | 277 | SHIFT_AND_MASK_LE(__pdesc+16, 5, 1) |
0c817338 | 278 | #define GET_TX_DESC_QOS(__pdesc) \ |
17c9ac62 | 279 | SHIFT_AND_MASK_LE(__pdesc+16, 6, 1) |
0c817338 | 280 | #define GET_TX_DESC_HWSEQ_EN(__pdesc) \ |
17c9ac62 | 281 | SHIFT_AND_MASK_LE(__pdesc+16, 7, 1) |
0c817338 | 282 | #define GET_TX_DESC_USE_RATE(__pdesc) \ |
17c9ac62 | 283 | SHIFT_AND_MASK_LE(__pdesc+16, 8, 1) |
0c817338 | 284 | #define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \ |
17c9ac62 | 285 | SHIFT_AND_MASK_LE(__pdesc+16, 9, 1) |
0c817338 | 286 | #define GET_TX_DESC_DISABLE_FB(__pdesc) \ |
17c9ac62 | 287 | SHIFT_AND_MASK_LE(__pdesc+16, 10, 1) |
0c817338 | 288 | #define GET_TX_DESC_CTS2SELF(__pdesc) \ |
17c9ac62 | 289 | SHIFT_AND_MASK_LE(__pdesc+16, 11, 1) |
0c817338 | 290 | #define GET_TX_DESC_RTS_ENABLE(__pdesc) \ |
17c9ac62 | 291 | SHIFT_AND_MASK_LE(__pdesc+16, 12, 1) |
0c817338 | 292 | #define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \ |
17c9ac62 | 293 | SHIFT_AND_MASK_LE(__pdesc+16, 13, 1) |
0c817338 | 294 | #define GET_TX_DESC_PORT_ID(__pdesc) \ |
17c9ac62 | 295 | SHIFT_AND_MASK_LE(__pdesc+16, 14, 1) |
0c817338 | 296 | #define GET_TX_DESC_WAIT_DCTS(__pdesc) \ |
17c9ac62 | 297 | SHIFT_AND_MASK_LE(__pdesc+16, 18, 1) |
0c817338 | 298 | #define GET_TX_DESC_CTS2AP_EN(__pdesc) \ |
17c9ac62 | 299 | SHIFT_AND_MASK_LE(__pdesc+16, 19, 1) |
0c817338 | 300 | #define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \ |
17c9ac62 | 301 | SHIFT_AND_MASK_LE(__pdesc+16, 20, 2) |
0c817338 | 302 | #define GET_TX_DESC_TX_STBC(__pdesc) \ |
17c9ac62 | 303 | SHIFT_AND_MASK_LE(__pdesc+16, 22, 2) |
0c817338 | 304 | #define GET_TX_DESC_DATA_SHORT(__pdesc) \ |
17c9ac62 | 305 | SHIFT_AND_MASK_LE(__pdesc+16, 24, 1) |
0c817338 | 306 | #define GET_TX_DESC_DATA_BW(__pdesc) \ |
17c9ac62 | 307 | SHIFT_AND_MASK_LE(__pdesc+16, 25, 1) |
0c817338 | 308 | #define GET_TX_DESC_RTS_SHORT(__pdesc) \ |
17c9ac62 | 309 | SHIFT_AND_MASK_LE(__pdesc+16, 26, 1) |
0c817338 | 310 | #define GET_TX_DESC_RTS_BW(__pdesc) \ |
17c9ac62 | 311 | SHIFT_AND_MASK_LE(__pdesc+16, 27, 1) |
0c817338 | 312 | #define GET_TX_DESC_RTS_SC(__pdesc) \ |
17c9ac62 | 313 | SHIFT_AND_MASK_LE(__pdesc+16, 28, 2) |
0c817338 | 314 | #define GET_TX_DESC_RTS_STBC(__pdesc) \ |
17c9ac62 | 315 | SHIFT_AND_MASK_LE(__pdesc+16, 30, 2) |
0c817338 LF |
316 | |
317 | #define SET_TX_DESC_TX_RATE(__pdesc, __val) \ | |
17c9ac62 | 318 | SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val) |
0c817338 | 319 | #define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \ |
17c9ac62 | 320 | SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val) |
0c817338 | 321 | #define SET_TX_DESC_CCX_TAG(__pdesc, __val) \ |
17c9ac62 | 322 | SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val) |
0c817338 | 323 | #define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ |
17c9ac62 | 324 | SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val) |
0c817338 | 325 | #define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ |
17c9ac62 | 326 | SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val) |
0c817338 | 327 | #define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \ |
17c9ac62 | 328 | SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val) |
0c817338 | 329 | #define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \ |
17c9ac62 | 330 | SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val) |
0c817338 | 331 | #define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \ |
17c9ac62 | 332 | SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val) |
0c817338 LF |
333 | |
334 | #define GET_TX_DESC_TX_RATE(__pdesc) \ | |
17c9ac62 | 335 | SHIFT_AND_MASK_LE(__pdesc+20, 0, 6) |
0c817338 | 336 | #define GET_TX_DESC_DATA_SHORTGI(__pdesc) \ |
17c9ac62 | 337 | SHIFT_AND_MASK_LE(__pdesc+20, 6, 1) |
0c817338 | 338 | #define GET_TX_DESC_CCX_TAG(__pdesc) \ |
17c9ac62 | 339 | SHIFT_AND_MASK_LE(__pdesc+20, 7, 1) |
0c817338 | 340 | #define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \ |
17c9ac62 | 341 | SHIFT_AND_MASK_LE(__pdesc+20, 8, 5) |
0c817338 | 342 | #define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \ |
17c9ac62 | 343 | SHIFT_AND_MASK_LE(__pdesc+20, 13, 4) |
0c817338 | 344 | #define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \ |
17c9ac62 | 345 | SHIFT_AND_MASK_LE(__pdesc+20, 17, 1) |
0c817338 | 346 | #define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \ |
17c9ac62 | 347 | SHIFT_AND_MASK_LE(__pdesc+20, 18, 6) |
0c817338 | 348 | #define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \ |
17c9ac62 | 349 | SHIFT_AND_MASK_LE(__pdesc+20, 24, 8) |
0c817338 LF |
350 | |
351 | #define SET_TX_DESC_TXAGC_A(__pdesc, __val) \ | |
17c9ac62 | 352 | SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val) |
0c817338 | 353 | #define SET_TX_DESC_TXAGC_B(__pdesc, __val) \ |
17c9ac62 | 354 | SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val) |
0c817338 | 355 | #define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 356 | SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val) |
0c817338 | 357 | #define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \ |
17c9ac62 | 358 | SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val) |
0c817338 | 359 | #define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 360 | SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val) |
0c817338 | 361 | #define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 362 | SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val) |
0c817338 | 363 | #define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 364 | SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val) |
0c817338 | 365 | #define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 366 | SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val) |
0c817338 LF |
367 | |
368 | #define GET_TX_DESC_TXAGC_A(__pdesc) \ | |
17c9ac62 | 369 | SHIFT_AND_MASK_LE(__pdesc+24, 0, 5) |
0c817338 | 370 | #define GET_TX_DESC_TXAGC_B(__pdesc) \ |
17c9ac62 | 371 | SHIFT_AND_MASK_LE(__pdesc+24, 5, 5) |
0c817338 | 372 | #define GET_TX_DESC_USE_MAX_LEN(__pdesc) \ |
17c9ac62 | 373 | SHIFT_AND_MASK_LE(__pdesc+24, 10, 1) |
0c817338 | 374 | #define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \ |
17c9ac62 | 375 | SHIFT_AND_MASK_LE(__pdesc+24, 11, 5) |
0c817338 | 376 | #define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \ |
17c9ac62 | 377 | SHIFT_AND_MASK_LE(__pdesc+24, 16, 4) |
0c817338 | 378 | #define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \ |
17c9ac62 | 379 | SHIFT_AND_MASK_LE(__pdesc+24, 20, 4) |
0c817338 | 380 | #define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \ |
17c9ac62 | 381 | SHIFT_AND_MASK_LE(__pdesc+24, 24, 4) |
0c817338 | 382 | #define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \ |
17c9ac62 | 383 | SHIFT_AND_MASK_LE(__pdesc+24, 28, 4) |
0c817338 LF |
384 | |
385 | #define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ | |
17c9ac62 | 386 | SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val) |
0c817338 | 387 | #define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 388 | SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val) |
0c817338 | 389 | #define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 390 | SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val) |
0c817338 | 391 | #define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 392 | SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val) |
0c817338 | 393 | #define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \ |
17c9ac62 | 394 | SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val) |
0c817338 LF |
395 | |
396 | #define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \ | |
17c9ac62 | 397 | SHIFT_AND_MASK_LE(__pdesc+28, 0, 16) |
0c817338 | 398 | #define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \ |
17c9ac62 | 399 | SHIFT_AND_MASK_LE(__pdesc+28, 16, 4) |
0c817338 | 400 | #define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \ |
17c9ac62 | 401 | SHIFT_AND_MASK_LE(__pdesc+28, 20, 4) |
0c817338 | 402 | #define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \ |
17c9ac62 | 403 | SHIFT_AND_MASK_LE(__pdesc+28, 24, 4) |
0c817338 | 404 | #define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \ |
17c9ac62 | 405 | SHIFT_AND_MASK_LE(__pdesc+28, 28, 4) |
0c817338 LF |
406 | |
407 | #define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ | |
17c9ac62 | 408 | SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val) |
0c817338 | 409 | #define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \ |
17c9ac62 | 410 | SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val) |
0c817338 LF |
411 | |
412 | #define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ | |
17c9ac62 | 413 | SHIFT_AND_MASK_LE(__pdesc+32, 0, 32) |
0c817338 | 414 | #define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \ |
17c9ac62 | 415 | SHIFT_AND_MASK_LE(__pdesc+36, 0, 32) |
0c817338 LF |
416 | |
417 | #define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ | |
17c9ac62 | 418 | SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val) |
0c817338 | 419 | #define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \ |
17c9ac62 | 420 | SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val) |
0c817338 LF |
421 | |
422 | #define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \ | |
17c9ac62 | 423 | SHIFT_AND_MASK_LE(__pdesc+40, 0, 32) |
0c817338 | 424 | #define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \ |
17c9ac62 | 425 | SHIFT_AND_MASK_LE(__pdesc+44, 0, 32) |
0c817338 LF |
426 | |
427 | #define GET_RX_DESC_PKT_LEN(__pdesc) \ | |
17c9ac62 | 428 | SHIFT_AND_MASK_LE(__pdesc, 0, 14) |
0c817338 | 429 | #define GET_RX_DESC_CRC32(__pdesc) \ |
17c9ac62 | 430 | SHIFT_AND_MASK_LE(__pdesc, 14, 1) |
0c817338 | 431 | #define GET_RX_DESC_ICV(__pdesc) \ |
17c9ac62 | 432 | SHIFT_AND_MASK_LE(__pdesc, 15, 1) |
0c817338 | 433 | #define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \ |
17c9ac62 | 434 | SHIFT_AND_MASK_LE(__pdesc, 16, 4) |
0c817338 | 435 | #define GET_RX_DESC_SECURITY(__pdesc) \ |
17c9ac62 | 436 | SHIFT_AND_MASK_LE(__pdesc, 20, 3) |
0c817338 | 437 | #define GET_RX_DESC_QOS(__pdesc) \ |
17c9ac62 | 438 | SHIFT_AND_MASK_LE(__pdesc, 23, 1) |
0c817338 | 439 | #define GET_RX_DESC_SHIFT(__pdesc) \ |
17c9ac62 | 440 | SHIFT_AND_MASK_LE(__pdesc, 24, 2) |
0c817338 | 441 | #define GET_RX_DESC_PHYST(__pdesc) \ |
17c9ac62 | 442 | SHIFT_AND_MASK_LE(__pdesc, 26, 1) |
0c817338 | 443 | #define GET_RX_DESC_SWDEC(__pdesc) \ |
17c9ac62 | 444 | SHIFT_AND_MASK_LE(__pdesc, 27, 1) |
0c817338 | 445 | #define GET_RX_DESC_LS(__pdesc) \ |
17c9ac62 | 446 | SHIFT_AND_MASK_LE(__pdesc, 28, 1) |
0c817338 | 447 | #define GET_RX_DESC_FS(__pdesc) \ |
17c9ac62 | 448 | SHIFT_AND_MASK_LE(__pdesc, 29, 1) |
0c817338 | 449 | #define GET_RX_DESC_EOR(__pdesc) \ |
17c9ac62 | 450 | SHIFT_AND_MASK_LE(__pdesc, 30, 1) |
0c817338 | 451 | #define GET_RX_DESC_OWN(__pdesc) \ |
17c9ac62 | 452 | SHIFT_AND_MASK_LE(__pdesc, 31, 1) |
0c817338 LF |
453 | |
454 | #define SET_RX_DESC_PKT_LEN(__pdesc, __val) \ | |
17c9ac62 | 455 | SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val) |
0c817338 | 456 | #define SET_RX_DESC_EOR(__pdesc, __val) \ |
17c9ac62 | 457 | SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val) |
0c817338 | 458 | #define SET_RX_DESC_OWN(__pdesc, __val) \ |
17c9ac62 | 459 | SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val) |
0c817338 LF |
460 | |
461 | #define GET_RX_DESC_MACID(__pdesc) \ | |
17c9ac62 | 462 | SHIFT_AND_MASK_LE(__pdesc+4, 0, 5) |
0c817338 | 463 | #define GET_RX_DESC_TID(__pdesc) \ |
17c9ac62 | 464 | SHIFT_AND_MASK_LE(__pdesc+4, 5, 4) |
0c817338 | 465 | #define GET_RX_DESC_HWRSVD(__pdesc) \ |
17c9ac62 | 466 | SHIFT_AND_MASK_LE(__pdesc+4, 9, 5) |
0c817338 | 467 | #define GET_RX_DESC_PAGGR(__pdesc) \ |
17c9ac62 | 468 | SHIFT_AND_MASK_LE(__pdesc+4, 14, 1) |
0c817338 | 469 | #define GET_RX_DESC_FAGGR(__pdesc) \ |
17c9ac62 | 470 | SHIFT_AND_MASK_LE(__pdesc+4, 15, 1) |
0c817338 | 471 | #define GET_RX_DESC_A1_FIT(__pdesc) \ |
17c9ac62 | 472 | SHIFT_AND_MASK_LE(__pdesc+4, 16, 4) |
0c817338 | 473 | #define GET_RX_DESC_A2_FIT(__pdesc) \ |
17c9ac62 | 474 | SHIFT_AND_MASK_LE(__pdesc+4, 20, 4) |
0c817338 | 475 | #define GET_RX_DESC_PAM(__pdesc) \ |
17c9ac62 | 476 | SHIFT_AND_MASK_LE(__pdesc+4, 24, 1) |
0c817338 | 477 | #define GET_RX_DESC_PWR(__pdesc) \ |
17c9ac62 | 478 | SHIFT_AND_MASK_LE(__pdesc+4, 25, 1) |
0c817338 | 479 | #define GET_RX_DESC_MD(__pdesc) \ |
17c9ac62 | 480 | SHIFT_AND_MASK_LE(__pdesc+4, 26, 1) |
0c817338 | 481 | #define GET_RX_DESC_MF(__pdesc) \ |
17c9ac62 | 482 | SHIFT_AND_MASK_LE(__pdesc+4, 27, 1) |
0c817338 | 483 | #define GET_RX_DESC_TYPE(__pdesc) \ |
17c9ac62 | 484 | SHIFT_AND_MASK_LE(__pdesc+4, 28, 2) |
0c817338 | 485 | #define GET_RX_DESC_MC(__pdesc) \ |
17c9ac62 | 486 | SHIFT_AND_MASK_LE(__pdesc+4, 30, 1) |
0c817338 | 487 | #define GET_RX_DESC_BC(__pdesc) \ |
17c9ac62 | 488 | SHIFT_AND_MASK_LE(__pdesc+4, 31, 1) |
0c817338 | 489 | #define GET_RX_DESC_SEQ(__pdesc) \ |
17c9ac62 | 490 | SHIFT_AND_MASK_LE(__pdesc+8, 0, 12) |
0c817338 | 491 | #define GET_RX_DESC_FRAG(__pdesc) \ |
17c9ac62 | 492 | SHIFT_AND_MASK_LE(__pdesc+8, 12, 4) |
0c817338 | 493 | #define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \ |
17c9ac62 | 494 | SHIFT_AND_MASK_LE(__pdesc+8, 16, 14) |
0c817338 | 495 | #define GET_RX_DESC_NEXT_IND(__pdesc) \ |
17c9ac62 | 496 | SHIFT_AND_MASK_LE(__pdesc+8, 30, 1) |
0c817338 | 497 | #define GET_RX_DESC_RSVD(__pdesc) \ |
17c9ac62 | 498 | SHIFT_AND_MASK_LE(__pdesc+8, 31, 1) |
0c817338 LF |
499 | |
500 | #define GET_RX_DESC_RXMCS(__pdesc) \ | |
17c9ac62 | 501 | SHIFT_AND_MASK_LE(__pdesc+12, 0, 6) |
0c817338 | 502 | #define GET_RX_DESC_RXHT(__pdesc) \ |
17c9ac62 | 503 | SHIFT_AND_MASK_LE(__pdesc+12, 6, 1) |
0c817338 | 504 | #define GET_RX_DESC_SPLCP(__pdesc) \ |
17c9ac62 | 505 | SHIFT_AND_MASK_LE(__pdesc+12, 8, 1) |
0c817338 | 506 | #define GET_RX_DESC_BW(__pdesc) \ |
17c9ac62 | 507 | SHIFT_AND_MASK_LE(__pdesc+12, 9, 1) |
0c817338 | 508 | #define GET_RX_DESC_HTC(__pdesc) \ |
17c9ac62 | 509 | SHIFT_AND_MASK_LE(__pdesc+12, 10, 1) |
0c817338 | 510 | #define GET_RX_DESC_HWPC_ERR(__pdesc) \ |
17c9ac62 | 511 | SHIFT_AND_MASK_LE(__pdesc+12, 14, 1) |
0c817338 | 512 | #define GET_RX_DESC_HWPC_IND(__pdesc) \ |
17c9ac62 | 513 | SHIFT_AND_MASK_LE(__pdesc+12, 15, 1) |
0c817338 | 514 | #define GET_RX_DESC_IV0(__pdesc) \ |
17c9ac62 | 515 | SHIFT_AND_MASK_LE(__pdesc+12, 16, 16) |
0c817338 LF |
516 | |
517 | #define GET_RX_DESC_IV1(__pdesc) \ | |
17c9ac62 | 518 | SHIFT_AND_MASK_LE(__pdesc+16, 0, 32) |
0c817338 | 519 | #define GET_RX_DESC_TSFL(__pdesc) \ |
17c9ac62 | 520 | SHIFT_AND_MASK_LE(__pdesc+20, 0, 32) |
0c817338 LF |
521 | |
522 | #define GET_RX_DESC_BUFF_ADDR(__pdesc) \ | |
17c9ac62 | 523 | SHIFT_AND_MASK_LE(__pdesc+24, 0, 32) |
0c817338 | 524 | #define GET_RX_DESC_BUFF_ADDR64(__pdesc) \ |
17c9ac62 | 525 | SHIFT_AND_MASK_LE(__pdesc+28, 0, 32) |
0c817338 LF |
526 | |
527 | #define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \ | |
17c9ac62 | 528 | SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val) |
0c817338 | 529 | #define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \ |
17c9ac62 | 530 | SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val) |
0c817338 LF |
531 | |
532 | #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ | |
da951c24 | 533 | memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)) |
0c817338 | 534 | |
0c817338 LF |
535 | struct rx_fwinfo_92c { |
536 | u8 gain_trsw[4]; | |
537 | u8 pwdb_all; | |
538 | u8 cfosho[4]; | |
539 | u8 cfotail[4]; | |
540 | char rxevm[2]; | |
541 | char rxsnr[4]; | |
542 | u8 pdsnr[2]; | |
543 | u8 csi_current[2]; | |
544 | u8 csi_target[2]; | |
545 | u8 sigevm; | |
546 | u8 max_ex_pwr; | |
547 | u8 ex_intf_flag:1; | |
548 | u8 sgi_en:1; | |
549 | u8 rxsc:2; | |
550 | u8 reserve:4; | |
e137478b | 551 | } __packed; |
0c817338 LF |
552 | |
553 | struct tx_desc_92c { | |
554 | u32 pktsize:16; | |
555 | u32 offset:8; | |
556 | u32 bmc:1; | |
557 | u32 htc:1; | |
558 | u32 lastseg:1; | |
559 | u32 firstseg:1; | |
560 | u32 linip:1; | |
561 | u32 noacm:1; | |
562 | u32 gf:1; | |
563 | u32 own:1; | |
564 | ||
565 | u32 macid:5; | |
566 | u32 agg_en:1; | |
567 | u32 bk:1; | |
568 | u32 rdg_en:1; | |
569 | u32 queuesel:5; | |
570 | u32 rd_nav_ext:1; | |
571 | u32 lsig_txop_en:1; | |
572 | u32 pifs:1; | |
573 | u32 rateid:4; | |
574 | u32 nav_usehdr:1; | |
575 | u32 en_descid:1; | |
576 | u32 sectype:2; | |
577 | u32 pktoffset:8; | |
578 | ||
579 | u32 rts_rc:6; | |
580 | u32 data_rc:6; | |
581 | u32 rsvd0:2; | |
582 | u32 bar_retryht:2; | |
583 | u32 rsvd1:1; | |
584 | u32 morefrag:1; | |
585 | u32 raw:1; | |
586 | u32 ccx:1; | |
587 | u32 ampdudensity:3; | |
588 | u32 rsvd2:1; | |
589 | u32 ant_sela:1; | |
590 | u32 ant_selb:1; | |
591 | u32 txant_cck:2; | |
592 | u32 txant_l:2; | |
593 | u32 txant_ht:2; | |
594 | ||
595 | u32 nextheadpage:8; | |
596 | u32 tailpage:8; | |
597 | u32 seq:12; | |
598 | u32 pktid:4; | |
599 | ||
600 | u32 rtsrate:5; | |
601 | u32 apdcfe:1; | |
602 | u32 qos:1; | |
603 | u32 hwseq_enable:1; | |
604 | u32 userrate:1; | |
605 | u32 dis_rtsfb:1; | |
606 | u32 dis_datafb:1; | |
607 | u32 cts2self:1; | |
608 | u32 rts_en:1; | |
609 | u32 hwrts_en:1; | |
610 | u32 portid:1; | |
611 | u32 rsvd3:3; | |
612 | u32 waitdcts:1; | |
613 | u32 cts2ap_en:1; | |
614 | u32 txsc:2; | |
615 | u32 stbc:2; | |
616 | u32 txshort:1; | |
617 | u32 txbw:1; | |
618 | u32 rtsshort:1; | |
619 | u32 rtsbw:1; | |
620 | u32 rtssc:2; | |
621 | u32 rtsstbc:2; | |
622 | ||
623 | u32 txrate:6; | |
624 | u32 shortgi:1; | |
625 | u32 ccxt:1; | |
626 | u32 txrate_fb_lmt:5; | |
627 | u32 rtsrate_fb_lmt:4; | |
628 | u32 retrylmt_en:1; | |
629 | u32 txretrylmt:6; | |
630 | u32 usb_txaggnum:8; | |
631 | ||
632 | u32 txagca:5; | |
633 | u32 txagcb:5; | |
634 | u32 usemaxlen:1; | |
635 | u32 maxaggnum:5; | |
636 | u32 mcsg1maxlen:4; | |
637 | u32 mcsg2maxlen:4; | |
638 | u32 mcsg3maxlen:4; | |
639 | u32 mcs7sgimaxlen:4; | |
640 | ||
641 | u32 txbuffersize:16; | |
642 | u32 mcsg4maxlen:4; | |
643 | u32 mcsg5maxlen:4; | |
644 | u32 mcsg6maxlen:4; | |
645 | u32 mcsg15sgimaxlen:4; | |
646 | ||
647 | u32 txbuffaddr; | |
648 | u32 txbufferaddr64; | |
649 | u32 nextdescaddress; | |
650 | u32 nextdescaddress64; | |
651 | ||
652 | u32 reserve_pass_pcie_mm_limit[4]; | |
e137478b | 653 | } __packed; |
0c817338 LF |
654 | |
655 | struct rx_desc_92c { | |
656 | u32 length:14; | |
657 | u32 crc32:1; | |
658 | u32 icverror:1; | |
659 | u32 drv_infosize:4; | |
660 | u32 security:3; | |
661 | u32 qos:1; | |
662 | u32 shift:2; | |
663 | u32 phystatus:1; | |
664 | u32 swdec:1; | |
665 | u32 lastseg:1; | |
666 | u32 firstseg:1; | |
667 | u32 eor:1; | |
668 | u32 own:1; | |
669 | ||
670 | u32 macid:5; | |
671 | u32 tid:4; | |
672 | u32 hwrsvd:5; | |
673 | u32 paggr:1; | |
674 | u32 faggr:1; | |
675 | u32 a1_fit:4; | |
676 | u32 a2_fit:4; | |
677 | u32 pam:1; | |
678 | u32 pwr:1; | |
679 | u32 moredata:1; | |
680 | u32 morefrag:1; | |
681 | u32 type:2; | |
682 | u32 mc:1; | |
683 | u32 bc:1; | |
684 | ||
685 | u32 seq:12; | |
686 | u32 frag:4; | |
687 | u32 nextpktlen:14; | |
688 | u32 nextind:1; | |
689 | u32 rsvd:1; | |
690 | ||
691 | u32 rxmcs:6; | |
692 | u32 rxht:1; | |
693 | u32 amsdu:1; | |
694 | u32 splcp:1; | |
695 | u32 bandwidth:1; | |
696 | u32 htc:1; | |
697 | u32 tcpchk_rpt:1; | |
698 | u32 ipcchk_rpt:1; | |
699 | u32 tcpchk_valid:1; | |
700 | u32 hwpcerr:1; | |
701 | u32 hwpcind:1; | |
702 | u32 iv0:16; | |
703 | ||
704 | u32 iv1; | |
705 | ||
706 | u32 tsfl; | |
707 | ||
708 | u32 bufferaddress; | |
709 | u32 bufferaddress64; | |
710 | ||
e137478b | 711 | } __packed; |
0c817338 LF |
712 | |
713 | void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw, | |
714 | struct ieee80211_hdr *hdr, | |
715 | u8 *pdesc, struct ieee80211_tx_info *info, | |
36323f81 | 716 | struct ieee80211_sta *sta, |
76c34f91 C |
717 | struct sk_buff *skb, u8 hw_queue, |
718 | struct rtl_tcb_desc *ptcb_desc); | |
0c817338 LF |
719 | bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw, |
720 | struct rtl_stats *stats, | |
721 | struct ieee80211_rx_status *rx_status, | |
722 | u8 *pdesc, struct sk_buff *skb); | |
723 | void rtl92ce_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val); | |
724 | u32 rtl92ce_get_desc(u8 *pdesc, bool istx, u8 desc_name); | |
76c34f91 | 725 | void rtl92ce_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); |
0c817338 LF |
726 | void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, |
727 | bool b_firstseg, bool b_lastseg, | |
728 | struct sk_buff *skb); | |
729 | #endif |