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0c817338 LF |
1 | /****************************************************************************** |
2 | * | |
9003a4ab | 3 | * Copyright(c) 2009-2012 Realtek Corporation. |
0c817338 LF |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #include "../wifi.h" | |
31 | #include "../efuse.h" | |
32 | #include "../base.h" | |
f73b279c | 33 | #include "../regd.h" |
0c817338 LF |
34 | #include "../cam.h" |
35 | #include "../ps.h" | |
36 | #include "../pci.h" | |
5c405b5c JL |
37 | #include "reg.h" |
38 | #include "def.h" | |
39 | #include "phy.h" | |
f73b279c | 40 | #include "../rtl8192c/fw_common.h" |
5c405b5c | 41 | #include "dm.h" |
5c405b5c JL |
42 | #include "led.h" |
43 | #include "hw.h" | |
0c817338 LF |
44 | |
45 | #define LLT_CONFIG 5 | |
46 | ||
47 | static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw, | |
48 | u8 set_bits, u8 clear_bits) | |
49 | { | |
50 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
51 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
52 | ||
53 | rtlpci->reg_bcn_ctrl_val |= set_bits; | |
54 | rtlpci->reg_bcn_ctrl_val &= ~clear_bits; | |
55 | ||
56 | rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); | |
57 | } | |
58 | ||
59 | static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw) | |
60 | { | |
61 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
62 | u8 tmp1byte; | |
63 | ||
64 | tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); | |
65 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); | |
66 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); | |
67 | tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); | |
68 | tmp1byte &= ~(BIT(0)); | |
69 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); | |
70 | } | |
71 | ||
72 | static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw) | |
73 | { | |
74 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
75 | u8 tmp1byte; | |
76 | ||
77 | tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); | |
78 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); | |
79 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
80 | tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); | |
81 | tmp1byte |= BIT(0); | |
82 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); | |
83 | } | |
84 | ||
85 | static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw) | |
86 | { | |
87 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1)); | |
88 | } | |
89 | ||
90 | static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw) | |
91 | { | |
92 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0); | |
93 | } | |
94 | ||
95 | void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) | |
96 | { | |
97 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
98 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
99 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
100 | ||
101 | switch (variable) { | |
102 | case HW_VAR_RCR: | |
103 | *((u32 *) (val)) = rtlpci->receive_config; | |
104 | break; | |
105 | case HW_VAR_RF_STATE: | |
106 | *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; | |
107 | break; | |
108 | case HW_VAR_FWLPS_RF_ON:{ | |
109 | enum rf_pwrstate rfState; | |
110 | u32 val_rcr; | |
111 | ||
112 | rtlpriv->cfg->ops->get_hw_reg(hw, | |
113 | HW_VAR_RF_STATE, | |
114 | (u8 *) (&rfState)); | |
115 | if (rfState == ERFOFF) { | |
116 | *((bool *) (val)) = true; | |
117 | } else { | |
118 | val_rcr = rtl_read_dword(rtlpriv, REG_RCR); | |
119 | val_rcr &= 0x00070000; | |
120 | if (val_rcr) | |
121 | *((bool *) (val)) = false; | |
122 | else | |
123 | *((bool *) (val)) = true; | |
124 | } | |
125 | break; | |
126 | } | |
127 | case HW_VAR_FW_PSMODE_STATUS: | |
7ea47240 | 128 | *((bool *) (val)) = ppsc->fw_current_inpsmode; |
0c817338 LF |
129 | break; |
130 | case HW_VAR_CORRECT_TSF:{ | |
131 | u64 tsf; | |
132 | u32 *ptsf_low = (u32 *)&tsf; | |
133 | u32 *ptsf_high = ((u32 *)&tsf) + 1; | |
134 | ||
135 | *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); | |
136 | *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); | |
137 | ||
138 | *((u64 *) (val)) = tsf; | |
139 | ||
140 | break; | |
141 | } | |
0c817338 LF |
142 | default: |
143 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 144 | "switch case not processed\n"); |
0c817338 LF |
145 | break; |
146 | } | |
147 | } | |
148 | ||
149 | void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) | |
150 | { | |
151 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 152 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0c817338 LF |
153 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
154 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
155 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
156 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
157 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
158 | u8 idx; | |
159 | ||
160 | switch (variable) { | |
161 | case HW_VAR_ETHER_ADDR:{ | |
162 | for (idx = 0; idx < ETH_ALEN; idx++) { | |
163 | rtl_write_byte(rtlpriv, (REG_MACID + idx), | |
164 | val[idx]); | |
165 | } | |
166 | break; | |
167 | } | |
168 | case HW_VAR_BASIC_RATE:{ | |
7ea47240 | 169 | u16 rate_cfg = ((u16 *) val)[0]; |
0c817338 | 170 | u8 rate_index = 0; |
7ea47240 LF |
171 | rate_cfg &= 0x15f; |
172 | rate_cfg |= 0x01; | |
173 | rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); | |
0c817338 | 174 | rtl_write_byte(rtlpriv, REG_RRSR + 1, |
f73b279c | 175 | (rate_cfg >> 8) & 0xff); |
7ea47240 LF |
176 | while (rate_cfg > 0x1) { |
177 | rate_cfg = (rate_cfg >> 1); | |
0c817338 LF |
178 | rate_index++; |
179 | } | |
180 | rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, | |
181 | rate_index); | |
182 | break; | |
183 | } | |
184 | case HW_VAR_BSSID:{ | |
185 | for (idx = 0; idx < ETH_ALEN; idx++) { | |
186 | rtl_write_byte(rtlpriv, (REG_BSSID + idx), | |
187 | val[idx]); | |
188 | } | |
189 | break; | |
190 | } | |
191 | case HW_VAR_SIFS:{ | |
192 | rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); | |
193 | rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); | |
194 | ||
195 | rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); | |
196 | rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); | |
197 | ||
198 | if (!mac->ht_enable) | |
199 | rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, | |
200 | 0x0e0e); | |
201 | else | |
202 | rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, | |
203 | *((u16 *) val)); | |
204 | break; | |
205 | } | |
206 | case HW_VAR_SLOT_TIME:{ | |
207 | u8 e_aci; | |
208 | ||
209 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
f30d7507 | 210 | "HW_VAR_SLOT_TIME %x\n", val[0]); |
0c817338 LF |
211 | |
212 | rtl_write_byte(rtlpriv, REG_SLOT, val[0]); | |
213 | ||
214 | for (e_aci = 0; e_aci < AC_MAX; e_aci++) { | |
215 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
216 | HW_VAR_AC_PARAM, | |
2c208890 | 217 | &e_aci); |
0c817338 LF |
218 | } |
219 | break; | |
220 | } | |
221 | case HW_VAR_ACK_PREAMBLE:{ | |
222 | u8 reg_tmp; | |
2c208890 | 223 | u8 short_preamble = (bool)*val; |
0c817338 LF |
224 | reg_tmp = (mac->cur_40_prime_sc) << 5; |
225 | if (short_preamble) | |
226 | reg_tmp |= 0x80; | |
227 | ||
228 | rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); | |
229 | break; | |
230 | } | |
231 | case HW_VAR_AMPDU_MIN_SPACE:{ | |
232 | u8 min_spacing_to_set; | |
233 | u8 sec_min_space; | |
234 | ||
2c208890 | 235 | min_spacing_to_set = *val; |
0c817338 LF |
236 | if (min_spacing_to_set <= 7) { |
237 | sec_min_space = 0; | |
238 | ||
239 | if (min_spacing_to_set < sec_min_space) | |
240 | min_spacing_to_set = sec_min_space; | |
241 | ||
242 | mac->min_space_cfg = ((mac->min_space_cfg & | |
243 | 0xf8) | | |
244 | min_spacing_to_set); | |
245 | ||
246 | *val = min_spacing_to_set; | |
247 | ||
248 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
f30d7507 JP |
249 | "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", |
250 | mac->min_space_cfg); | |
0c817338 LF |
251 | |
252 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, | |
253 | mac->min_space_cfg); | |
254 | } | |
255 | break; | |
256 | } | |
257 | case HW_VAR_SHORTGI_DENSITY:{ | |
258 | u8 density_to_set; | |
259 | ||
2c208890 | 260 | density_to_set = *val; |
0c817338 LF |
261 | mac->min_space_cfg |= (density_to_set << 3); |
262 | ||
263 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
f30d7507 JP |
264 | "Set HW_VAR_SHORTGI_DENSITY: %#x\n", |
265 | mac->min_space_cfg); | |
0c817338 LF |
266 | |
267 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, | |
268 | mac->min_space_cfg); | |
269 | ||
270 | break; | |
271 | } | |
272 | case HW_VAR_AMPDU_FACTOR:{ | |
f73b279c C |
273 | u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9}; |
274 | u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97}; | |
0c817338 LF |
275 | |
276 | u8 factor_toset; | |
277 | u8 *p_regtoset = NULL; | |
278 | u8 index = 0; | |
279 | ||
f73b279c C |
280 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
281 | (rtlpcipriv->bt_coexist.bt_coexist_type == | |
282 | BT_CSR_BC4)) | |
283 | p_regtoset = regtoset_bt; | |
284 | else | |
285 | p_regtoset = regtoset_normal; | |
0c817338 | 286 | |
2c208890 | 287 | factor_toset = *(val); |
0c817338 LF |
288 | if (factor_toset <= 3) { |
289 | factor_toset = (1 << (factor_toset + 2)); | |
290 | if (factor_toset > 0xf) | |
291 | factor_toset = 0xf; | |
292 | ||
293 | for (index = 0; index < 4; index++) { | |
294 | if ((p_regtoset[index] & 0xf0) > | |
295 | (factor_toset << 4)) | |
296 | p_regtoset[index] = | |
297 | (p_regtoset[index] & 0x0f) | | |
298 | (factor_toset << 4); | |
299 | ||
300 | if ((p_regtoset[index] & 0x0f) > | |
301 | factor_toset) | |
302 | p_regtoset[index] = | |
303 | (p_regtoset[index] & 0xf0) | | |
304 | (factor_toset); | |
305 | ||
306 | rtl_write_byte(rtlpriv, | |
307 | (REG_AGGLEN_LMT + index), | |
308 | p_regtoset[index]); | |
309 | ||
310 | } | |
311 | ||
312 | RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, | |
f30d7507 JP |
313 | "Set HW_VAR_AMPDU_FACTOR: %#x\n", |
314 | factor_toset); | |
0c817338 LF |
315 | } |
316 | break; | |
317 | } | |
318 | case HW_VAR_AC_PARAM:{ | |
2c208890 | 319 | u8 e_aci = *(val); |
f73b279c | 320 | rtl92c_dm_init_edca_turbo(hw); |
0c817338 | 321 | |
2cddad3c | 322 | if (rtlpci->acm_method != EACMWAY2_SW) |
0c817338 LF |
323 | rtlpriv->cfg->ops->set_hw_reg(hw, |
324 | HW_VAR_ACM_CTRL, | |
2c208890 | 325 | (&e_aci)); |
0c817338 LF |
326 | break; |
327 | } | |
328 | case HW_VAR_ACM_CTRL:{ | |
2c208890 | 329 | u8 e_aci = *(val); |
0c817338 LF |
330 | union aci_aifsn *p_aci_aifsn = |
331 | (union aci_aifsn *)(&(mac->ac[0].aifs)); | |
332 | u8 acm = p_aci_aifsn->f.acm; | |
333 | u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); | |
334 | ||
335 | acm_ctrl = | |
336 | acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1); | |
337 | ||
338 | if (acm) { | |
339 | switch (e_aci) { | |
340 | case AC0_BE: | |
341 | acm_ctrl |= AcmHw_BeqEn; | |
342 | break; | |
343 | case AC2_VI: | |
344 | acm_ctrl |= AcmHw_ViqEn; | |
345 | break; | |
346 | case AC3_VO: | |
347 | acm_ctrl |= AcmHw_VoqEn; | |
348 | break; | |
349 | default: | |
350 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
351 | "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", |
352 | acm); | |
0c817338 LF |
353 | break; |
354 | } | |
355 | } else { | |
356 | switch (e_aci) { | |
357 | case AC0_BE: | |
358 | acm_ctrl &= (~AcmHw_BeqEn); | |
359 | break; | |
360 | case AC2_VI: | |
361 | acm_ctrl &= (~AcmHw_ViqEn); | |
362 | break; | |
363 | case AC3_VO: | |
364 | acm_ctrl &= (~AcmHw_BeqEn); | |
365 | break; | |
366 | default: | |
367 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 368 | "switch case not processed\n"); |
0c817338 LF |
369 | break; |
370 | } | |
371 | } | |
372 | ||
373 | RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE, | |
f30d7507 JP |
374 | "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", |
375 | acm_ctrl); | |
0c817338 LF |
376 | rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); |
377 | break; | |
378 | } | |
379 | case HW_VAR_RCR:{ | |
380 | rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); | |
381 | rtlpci->receive_config = ((u32 *) (val))[0]; | |
382 | break; | |
383 | } | |
384 | case HW_VAR_RETRY_LIMIT:{ | |
2c208890 | 385 | u8 retry_limit = val[0]; |
0c817338 LF |
386 | |
387 | rtl_write_word(rtlpriv, REG_RL, | |
388 | retry_limit << RETRY_LIMIT_SHORT_SHIFT | | |
389 | retry_limit << RETRY_LIMIT_LONG_SHIFT); | |
390 | break; | |
391 | } | |
392 | case HW_VAR_DUAL_TSF_RST: | |
393 | rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); | |
394 | break; | |
395 | case HW_VAR_EFUSE_BYTES: | |
396 | rtlefuse->efuse_usedbytes = *((u16 *) val); | |
397 | break; | |
398 | case HW_VAR_EFUSE_USAGE: | |
2c208890 | 399 | rtlefuse->efuse_usedpercentage = *val; |
0c817338 LF |
400 | break; |
401 | case HW_VAR_IO_CMD: | |
402 | rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val)); | |
403 | break; | |
404 | case HW_VAR_WPA_CONFIG: | |
2c208890 | 405 | rtl_write_byte(rtlpriv, REG_SECCFG, *val); |
0c817338 LF |
406 | break; |
407 | case HW_VAR_SET_RPWM:{ | |
408 | u8 rpwm_val; | |
409 | ||
410 | rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); | |
411 | udelay(1); | |
412 | ||
413 | if (rpwm_val & BIT(7)) { | |
2c208890 | 414 | rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val); |
0c817338 LF |
415 | } else { |
416 | rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, | |
2c208890 | 417 | *val | BIT(7)); |
0c817338 LF |
418 | } |
419 | ||
420 | break; | |
421 | } | |
422 | case HW_VAR_H2C_FW_PWRMODE:{ | |
2c208890 | 423 | u8 psmode = *val; |
0c817338 LF |
424 | |
425 | if ((psmode != FW_PS_ACTIVE_MODE) && | |
426 | (!IS_92C_SERIAL(rtlhal->version))) { | |
427 | rtl92c_dm_rf_saving(hw, true); | |
428 | } | |
429 | ||
2c208890 | 430 | rtl92c_set_fw_pwrmode_cmd(hw, *val); |
0c817338 LF |
431 | break; |
432 | } | |
433 | case HW_VAR_FW_PSMODE_STATUS: | |
7ea47240 | 434 | ppsc->fw_current_inpsmode = *((bool *) val); |
0c817338 LF |
435 | break; |
436 | case HW_VAR_H2C_FW_JOINBSSRPT:{ | |
2c208890 | 437 | u8 mstatus = *val; |
0c817338 | 438 | u8 tmp_regcr, tmp_reg422; |
7ea47240 | 439 | bool recover = false; |
0c817338 LF |
440 | |
441 | if (mstatus == RT_MEDIA_CONNECT) { | |
442 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, | |
443 | NULL); | |
444 | ||
445 | tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); | |
446 | rtl_write_byte(rtlpriv, REG_CR + 1, | |
447 | (tmp_regcr | BIT(0))); | |
448 | ||
449 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); | |
450 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); | |
451 | ||
452 | tmp_reg422 = | |
453 | rtl_read_byte(rtlpriv, | |
454 | REG_FWHW_TXQ_CTRL + 2); | |
455 | if (tmp_reg422 & BIT(6)) | |
7ea47240 | 456 | recover = true; |
0c817338 LF |
457 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, |
458 | tmp_reg422 & (~BIT(6))); | |
459 | ||
460 | rtl92c_set_fw_rsvdpagepkt(hw, 0); | |
461 | ||
462 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); | |
463 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); | |
464 | ||
7ea47240 | 465 | if (recover) { |
0c817338 LF |
466 | rtl_write_byte(rtlpriv, |
467 | REG_FWHW_TXQ_CTRL + 2, | |
468 | tmp_reg422); | |
469 | } | |
470 | ||
471 | rtl_write_byte(rtlpriv, REG_CR + 1, | |
472 | (tmp_regcr & ~(BIT(0)))); | |
473 | } | |
2c208890 | 474 | rtl92c_set_fw_joinbss_report_cmd(hw, *val); |
0c817338 LF |
475 | |
476 | break; | |
477 | } | |
3a16b412 LF |
478 | case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: |
479 | rtl92c_set_p2p_ps_offload_cmd(hw, (*(u8 *)val)); | |
480 | break; | |
0c817338 LF |
481 | case HW_VAR_AID:{ |
482 | u16 u2btmp; | |
483 | u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); | |
484 | u2btmp &= 0xC000; | |
485 | rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | | |
486 | mac->assoc_id)); | |
487 | ||
488 | break; | |
489 | } | |
490 | case HW_VAR_CORRECT_TSF:{ | |
2c208890 | 491 | u8 btype_ibss = val[0]; |
0c817338 | 492 | |
e10542c4 | 493 | if (btype_ibss) |
0c817338 LF |
494 | _rtl92ce_stop_tx_beacon(hw); |
495 | ||
496 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); | |
497 | ||
498 | rtl_write_dword(rtlpriv, REG_TSFTR, | |
499 | (u32) (mac->tsf & 0xffffffff)); | |
500 | rtl_write_dword(rtlpriv, REG_TSFTR + 4, | |
f73b279c | 501 | (u32) ((mac->tsf >> 32) & 0xffffffff)); |
0c817338 LF |
502 | |
503 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); | |
504 | ||
e10542c4 | 505 | if (btype_ibss) |
0c817338 LF |
506 | _rtl92ce_resume_tx_beacon(hw); |
507 | ||
508 | break; | |
509 | ||
510 | } | |
3a16b412 LF |
511 | case HW_VAR_FW_LPS_ACTION: { |
512 | bool enter_fwlps = *((bool *)val); | |
513 | u8 rpwm_val, fw_pwrmode; | |
514 | bool fw_current_inps; | |
515 | ||
516 | if (enter_fwlps) { | |
517 | rpwm_val = 0x02; /* RF off */ | |
518 | fw_current_inps = true; | |
519 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
520 | HW_VAR_FW_PSMODE_STATUS, | |
521 | (u8 *)(&fw_current_inps)); | |
522 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
523 | HW_VAR_H2C_FW_PWRMODE, | |
524 | (u8 *)(&ppsc->fwctrl_psmode)); | |
525 | ||
526 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
527 | HW_VAR_SET_RPWM, | |
528 | (u8 *)(&rpwm_val)); | |
529 | } else { | |
530 | rpwm_val = 0x0C; /* RF on */ | |
531 | fw_pwrmode = FW_PS_ACTIVE_MODE; | |
532 | fw_current_inps = false; | |
533 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
534 | HW_VAR_SET_RPWM, | |
535 | (u8 *)(&rpwm_val)); | |
536 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
537 | HW_VAR_H2C_FW_PWRMODE, | |
538 | (u8 *)(&fw_pwrmode)); | |
539 | ||
540 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
541 | HW_VAR_FW_PSMODE_STATUS, | |
542 | (u8 *)(&fw_current_inps)); | |
543 | } | |
544 | break; } | |
2d9d532f LF |
545 | case HW_VAR_KEEP_ALIVE: |
546 | break; | |
0c817338 | 547 | default: |
f30d7507 | 548 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
2d9d532f | 549 | "switch case %d not processed\n", variable); |
0c817338 LF |
550 | break; |
551 | } | |
552 | } | |
553 | ||
554 | static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) | |
555 | { | |
556 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
557 | bool status = true; | |
558 | long count = 0; | |
559 | u32 value = _LLT_INIT_ADDR(address) | | |
560 | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); | |
561 | ||
562 | rtl_write_dword(rtlpriv, REG_LLT_INIT, value); | |
563 | ||
564 | do { | |
565 | value = rtl_read_dword(rtlpriv, REG_LLT_INIT); | |
566 | if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) | |
567 | break; | |
568 | ||
569 | if (count > POLLING_LLT_THRESHOLD) { | |
570 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 JP |
571 | "Failed to polling write LLT done at address %d!\n", |
572 | address); | |
0c817338 LF |
573 | status = false; |
574 | break; | |
575 | } | |
576 | } while (++count); | |
577 | ||
578 | return status; | |
579 | } | |
580 | ||
581 | static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw) | |
582 | { | |
583 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
584 | unsigned short i; | |
585 | u8 txpktbuf_bndy; | |
586 | u8 maxPage; | |
587 | bool status; | |
588 | ||
589 | #if LLT_CONFIG == 1 | |
590 | maxPage = 255; | |
591 | txpktbuf_bndy = 252; | |
592 | #elif LLT_CONFIG == 2 | |
593 | maxPage = 127; | |
594 | txpktbuf_bndy = 124; | |
595 | #elif LLT_CONFIG == 3 | |
596 | maxPage = 255; | |
597 | txpktbuf_bndy = 174; | |
598 | #elif LLT_CONFIG == 4 | |
599 | maxPage = 255; | |
600 | txpktbuf_bndy = 246; | |
601 | #elif LLT_CONFIG == 5 | |
602 | maxPage = 255; | |
603 | txpktbuf_bndy = 246; | |
604 | #endif | |
605 | ||
606 | #if LLT_CONFIG == 1 | |
607 | rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c); | |
608 | rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c); | |
609 | #elif LLT_CONFIG == 2 | |
610 | rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010); | |
611 | #elif LLT_CONFIG == 3 | |
612 | rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484); | |
613 | #elif LLT_CONFIG == 4 | |
614 | rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c); | |
615 | #elif LLT_CONFIG == 5 | |
616 | rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000); | |
617 | ||
618 | rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29); | |
619 | #endif | |
620 | ||
621 | rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy)); | |
622 | rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); | |
623 | ||
624 | rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); | |
625 | rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); | |
626 | ||
627 | rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); | |
628 | rtl_write_byte(rtlpriv, REG_PBP, 0x11); | |
629 | rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); | |
630 | ||
631 | for (i = 0; i < (txpktbuf_bndy - 1); i++) { | |
632 | status = _rtl92ce_llt_write(hw, i, i + 1); | |
633 | if (true != status) | |
634 | return status; | |
635 | } | |
636 | ||
637 | status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); | |
638 | if (true != status) | |
639 | return status; | |
640 | ||
641 | for (i = txpktbuf_bndy; i < maxPage; i++) { | |
642 | status = _rtl92ce_llt_write(hw, i, (i + 1)); | |
643 | if (true != status) | |
644 | return status; | |
645 | } | |
646 | ||
647 | status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy); | |
648 | if (true != status) | |
649 | return status; | |
650 | ||
651 | return true; | |
652 | } | |
653 | ||
654 | static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw) | |
655 | { | |
656 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
657 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
658 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
659 | struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0); | |
660 | ||
661 | if (rtlpci->up_first_time) | |
662 | return; | |
663 | ||
664 | if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) | |
665 | rtl92ce_sw_led_on(hw, pLed0); | |
666 | else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT) | |
667 | rtl92ce_sw_led_on(hw, pLed0); | |
668 | else | |
669 | rtl92ce_sw_led_off(hw, pLed0); | |
0c817338 LF |
670 | } |
671 | ||
672 | static bool _rtl92ce_init_mac(struct ieee80211_hw *hw) | |
673 | { | |
674 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 675 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0c817338 LF |
676 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
677 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
678 | ||
679 | unsigned char bytetmp; | |
680 | unsigned short wordtmp; | |
681 | u16 retry; | |
682 | ||
683 | rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); | |
f73b279c C |
684 | if (rtlpcipriv->bt_coexist.bt_coexistence) { |
685 | u32 value32; | |
686 | value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO); | |
687 | value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK); | |
688 | rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32); | |
689 | } | |
0c817338 LF |
690 | rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); |
691 | rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F); | |
692 | ||
f73b279c C |
693 | if (rtlpcipriv->bt_coexist.bt_coexistence) { |
694 | u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); | |
695 | ||
696 | u4b_tmp &= (~0x00024800); | |
697 | rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); | |
698 | } | |
699 | ||
0c817338 LF |
700 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0); |
701 | udelay(2); | |
702 | ||
703 | rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp); | |
704 | udelay(2); | |
705 | ||
706 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); | |
707 | udelay(2); | |
708 | ||
709 | retry = 0; | |
f30d7507 JP |
710 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", |
711 | rtl_read_dword(rtlpriv, 0xEC), bytetmp); | |
0c817338 LF |
712 | |
713 | while ((bytetmp & BIT(0)) && retry < 1000) { | |
714 | retry++; | |
715 | udelay(50); | |
716 | bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1); | |
f30d7507 JP |
717 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n", |
718 | rtl_read_dword(rtlpriv, 0xEC), bytetmp); | |
0c817338 LF |
719 | udelay(50); |
720 | } | |
721 | ||
722 | rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012); | |
723 | ||
724 | rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82); | |
725 | udelay(2); | |
726 | ||
f73b279c C |
727 | if (rtlpcipriv->bt_coexist.bt_coexistence) { |
728 | bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd; | |
729 | rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp); | |
730 | } | |
731 | ||
0c817338 LF |
732 | rtl_write_word(rtlpriv, REG_CR, 0x2ff); |
733 | ||
23677ce3 | 734 | if (!_rtl92ce_llt_table_init(hw)) |
6eab04a8 | 735 | return false; |
0c817338 LF |
736 | |
737 | rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); | |
738 | rtl_write_byte(rtlpriv, REG_HISRE, 0xff); | |
739 | ||
740 | rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff); | |
741 | ||
742 | wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); | |
743 | wordtmp &= 0xf; | |
744 | wordtmp |= 0xF771; | |
745 | rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); | |
746 | ||
747 | rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); | |
748 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
749 | rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); | |
750 | ||
751 | rtl_write_byte(rtlpriv, 0x4d0, 0x0); | |
752 | ||
753 | rtl_write_dword(rtlpriv, REG_BCNQ_DESA, | |
754 | ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) & | |
755 | DMA_BIT_MASK(32)); | |
756 | rtl_write_dword(rtlpriv, REG_MGQ_DESA, | |
757 | (u64) rtlpci->tx_ring[MGNT_QUEUE].dma & | |
758 | DMA_BIT_MASK(32)); | |
759 | rtl_write_dword(rtlpriv, REG_VOQ_DESA, | |
760 | (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32)); | |
761 | rtl_write_dword(rtlpriv, REG_VIQ_DESA, | |
762 | (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32)); | |
763 | rtl_write_dword(rtlpriv, REG_BEQ_DESA, | |
764 | (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32)); | |
765 | rtl_write_dword(rtlpriv, REG_BKQ_DESA, | |
766 | (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32)); | |
767 | rtl_write_dword(rtlpriv, REG_HQ_DESA, | |
768 | (u64) rtlpci->tx_ring[HIGH_QUEUE].dma & | |
769 | DMA_BIT_MASK(32)); | |
770 | rtl_write_dword(rtlpriv, REG_RX_DESA, | |
771 | (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma & | |
772 | DMA_BIT_MASK(32)); | |
773 | ||
774 | if (IS_92C_SERIAL(rtlhal->version)) | |
775 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77); | |
776 | else | |
777 | rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22); | |
778 | ||
779 | rtl_write_dword(rtlpriv, REG_INT_MIG, 0); | |
780 | ||
781 | bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); | |
782 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6)); | |
783 | do { | |
784 | retry++; | |
785 | bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL); | |
786 | } while ((retry < 200) && (bytetmp & BIT(7))); | |
787 | ||
788 | _rtl92ce_gen_refresh_led_state(hw); | |
789 | ||
790 | rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); | |
791 | ||
6eab04a8 | 792 | return true; |
0c817338 LF |
793 | } |
794 | ||
795 | static void _rtl92ce_hw_configure(struct ieee80211_hw *hw) | |
796 | { | |
797 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
798 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 799 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0c817338 | 800 | u8 reg_bw_opmode; |
6c0d4988 | 801 | u32 reg_prsr; |
0c817338 LF |
802 | |
803 | reg_bw_opmode = BW_OPMODE_20MHZ; | |
0c817338 LF |
804 | reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; |
805 | ||
806 | rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); | |
807 | ||
808 | rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); | |
809 | ||
810 | rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr); | |
811 | ||
812 | rtl_write_byte(rtlpriv, REG_SLOT, 0x09); | |
813 | ||
814 | rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0); | |
815 | ||
816 | rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); | |
817 | ||
818 | rtl_write_word(rtlpriv, REG_RL, 0x0707); | |
819 | ||
820 | rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802); | |
821 | ||
822 | rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); | |
823 | ||
824 | rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); | |
825 | rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); | |
826 | rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); | |
827 | rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); | |
828 | ||
f73b279c C |
829 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
830 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) | |
831 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431); | |
832 | else | |
833 | rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841); | |
0c817338 LF |
834 | |
835 | rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); | |
836 | ||
837 | rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); | |
838 | ||
839 | rtlpci->reg_bcn_ctrl_val = 0x1f; | |
840 | rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); | |
841 | ||
842 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
843 | ||
844 | rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); | |
845 | ||
846 | rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); | |
847 | rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); | |
848 | ||
f73b279c C |
849 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
850 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) { | |
851 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
852 | rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402); | |
853 | } else { | |
854 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
855 | rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020); | |
856 | } | |
0c817338 | 857 | |
f73b279c C |
858 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
859 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) | |
860 | rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); | |
861 | else | |
862 | rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666); | |
0c817338 LF |
863 | |
864 | rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); | |
865 | ||
866 | rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); | |
867 | rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010); | |
868 | ||
869 | rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010); | |
870 | ||
871 | rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); | |
872 | ||
873 | rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); | |
874 | rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); | |
875 | ||
876 | } | |
877 | ||
878 | static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw) | |
879 | { | |
880 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
881 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
882 | ||
883 | rtl_write_byte(rtlpriv, 0x34b, 0x93); | |
884 | rtl_write_word(rtlpriv, 0x350, 0x870c); | |
885 | rtl_write_byte(rtlpriv, 0x352, 0x1); | |
886 | ||
7ea47240 | 887 | if (ppsc->support_backdoor) |
0c817338 LF |
888 | rtl_write_byte(rtlpriv, 0x349, 0x1b); |
889 | else | |
890 | rtl_write_byte(rtlpriv, 0x349, 0x03); | |
891 | ||
892 | rtl_write_word(rtlpriv, 0x350, 0x2718); | |
893 | rtl_write_byte(rtlpriv, 0x352, 0x1); | |
894 | } | |
895 | ||
896 | void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw) | |
897 | { | |
898 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
899 | u8 sec_reg_value; | |
900 | ||
901 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 JP |
902 | "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", |
903 | rtlpriv->sec.pairwise_enc_algorithm, | |
904 | rtlpriv->sec.group_enc_algorithm); | |
0c817338 LF |
905 | |
906 | if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { | |
f30d7507 JP |
907 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, |
908 | "not open hw encryption\n"); | |
0c817338 LF |
909 | return; |
910 | } | |
911 | ||
912 | sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable; | |
913 | ||
914 | if (rtlpriv->sec.use_defaultkey) { | |
915 | sec_reg_value |= SCR_TxUseDK; | |
916 | sec_reg_value |= SCR_RxUseDK; | |
917 | } | |
918 | ||
919 | sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); | |
920 | ||
921 | rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); | |
922 | ||
923 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, | |
f30d7507 | 924 | "The SECR-value %x\n", sec_reg_value); |
0c817338 LF |
925 | |
926 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); | |
927 | ||
928 | } | |
929 | ||
930 | int rtl92ce_hw_init(struct ieee80211_hw *hw) | |
931 | { | |
932 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
933 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
934 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
935 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
936 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
937 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
0c817338 LF |
938 | bool rtstatus = true; |
939 | bool is92c; | |
940 | int err; | |
941 | u8 tmp_u1b; | |
f78bccd7 | 942 | unsigned long flags; |
0c817338 LF |
943 | |
944 | rtlpci->being_init_adapter = true; | |
f78bccd7 OL |
945 | |
946 | /* Since this function can take a very long time (up to 350 ms) | |
947 | * and can be called with irqs disabled, reenable the irqs | |
948 | * to let the other devices continue being serviced. | |
949 | * | |
950 | * It is safe doing so since our own interrupts will only be enabled | |
951 | * in a subsequent step. | |
952 | */ | |
953 | local_save_flags(flags); | |
954 | local_irq_enable(); | |
955 | ||
0c817338 LF |
956 | rtlpriv->intf_ops->disable_aspm(hw); |
957 | rtstatus = _rtl92ce_init_mac(hw); | |
23677ce3 | 958 | if (!rtstatus) { |
f30d7507 | 959 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n"); |
0c817338 | 960 | err = 1; |
f78bccd7 | 961 | goto exit; |
0c817338 LF |
962 | } |
963 | ||
964 | err = rtl92c_download_fw(hw); | |
965 | if (err) { | |
966 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 | 967 | "Failed to download FW. Init HW without FW now..\n"); |
0c817338 | 968 | err = 1; |
f78bccd7 | 969 | goto exit; |
0c817338 LF |
970 | } |
971 | ||
972 | rtlhal->last_hmeboxnum = 0; | |
f73b279c | 973 | rtl92c_phy_mac_config(hw); |
0bd899e7 LF |
974 | /* because last function modify RCR, so we update |
975 | * rcr var here, or TP will unstable for receive_config | |
976 | * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx | |
977 | * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/ | |
978 | rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR); | |
979 | rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV); | |
980 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
f73b279c | 981 | rtl92c_phy_bb_config(hw); |
0c817338 LF |
982 | rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; |
983 | rtl92c_phy_rf_config(hw); | |
0bd899e7 LF |
984 | if (IS_VENDOR_UMC_A_CUT(rtlhal->version) && |
985 | !IS_92C_SERIAL(rtlhal->version)) { | |
986 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255); | |
987 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00); | |
988 | } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) { | |
989 | rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE); | |
990 | rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31); | |
991 | rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425); | |
992 | rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200); | |
993 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053); | |
994 | rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201); | |
995 | } | |
0c817338 LF |
996 | rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, |
997 | RF_CHNLBW, RFREG_OFFSET_MASK); | |
998 | rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1, | |
999 | RF_CHNLBW, RFREG_OFFSET_MASK); | |
1000 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); | |
1001 | rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); | |
1002 | rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); | |
1003 | _rtl92ce_hw_configure(hw); | |
1004 | rtl_cam_reset_all_entry(hw); | |
1005 | rtl92ce_enable_hw_security_config(hw); | |
f73b279c | 1006 | |
0c817338 | 1007 | ppsc->rfpwr_state = ERFON; |
f73b279c | 1008 | |
0c817338 LF |
1009 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); |
1010 | _rtl92ce_enable_aspm_back_door(hw); | |
1011 | rtlpriv->intf_ops->enable_aspm(hw); | |
f73b279c C |
1012 | |
1013 | rtl8192ce_bt_hw_init(hw); | |
1014 | ||
0c817338 LF |
1015 | if (ppsc->rfpwr_state == ERFON) { |
1016 | rtl92c_phy_set_rfpath_switch(hw, 1); | |
0bd899e7 | 1017 | if (rtlphy->iqk_initialized) { |
0c817338 | 1018 | rtl92c_phy_iq_calibrate(hw, true); |
f73b279c | 1019 | } else { |
0c817338 | 1020 | rtl92c_phy_iq_calibrate(hw, false); |
0bd899e7 | 1021 | rtlphy->iqk_initialized = true; |
0c817338 LF |
1022 | } |
1023 | ||
1024 | rtl92c_dm_check_txpower_tracking(hw); | |
1025 | rtl92c_phy_lc_calibrate(hw); | |
1026 | } | |
1027 | ||
1028 | is92c = IS_92C_SERIAL(rtlhal->version); | |
1029 | tmp_u1b = efuse_read_1byte(hw, 0x1FA); | |
1030 | if (!(tmp_u1b & BIT(0))) { | |
1031 | rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05); | |
f30d7507 | 1032 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n"); |
0c817338 LF |
1033 | } |
1034 | ||
1035 | if (!(tmp_u1b & BIT(1)) && is92c) { | |
1036 | rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05); | |
f30d7507 | 1037 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n"); |
0c817338 LF |
1038 | } |
1039 | ||
1040 | if (!(tmp_u1b & BIT(4))) { | |
1041 | tmp_u1b = rtl_read_byte(rtlpriv, 0x16); | |
1042 | tmp_u1b &= 0x0F; | |
1043 | rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80); | |
1044 | udelay(10); | |
1045 | rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90); | |
f30d7507 | 1046 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n"); |
0c817338 LF |
1047 | } |
1048 | rtl92c_dm_init(hw); | |
f78bccd7 OL |
1049 | exit: |
1050 | local_irq_restore(flags); | |
0c817338 LF |
1051 | rtlpci->being_init_adapter = false; |
1052 | return err; | |
1053 | } | |
1054 | ||
1055 | static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw) | |
1056 | { | |
1057 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1058 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1059 | enum version_8192c version = VERSION_UNKNOWN; | |
1060 | u32 value32; | |
07839b14 | 1061 | const char *versionid; |
0c817338 LF |
1062 | |
1063 | value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); | |
1064 | if (value32 & TRP_VAUX_EN) { | |
1065 | version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C : | |
1066 | VERSION_A_CHIP_88C; | |
1067 | } else { | |
022e1d06 LF |
1068 | version = (enum version_8192c) (CHIP_VER_B | |
1069 | ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) | | |
1070 | ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0)); | |
1071 | if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 & | |
1072 | CHIP_VER_RTL_MASK)) { | |
1073 | version = (enum version_8192c)(version | | |
1074 | ((((value32 & CHIP_VER_RTL_MASK) == BIT(12)) | |
1075 | ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) | | |
1076 | CHIP_VENDOR_UMC)); | |
1077 | } | |
0bd899e7 LF |
1078 | if (IS_92C_SERIAL(version)) { |
1079 | value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM); | |
1080 | version = (enum version_8192c)(version | | |
1081 | ((CHIP_BONDING_IDENTIFIER(value32) | |
1082 | == CHIP_BONDING_92C_1T2R) ? | |
1083 | RF_TYPE_1T2R : 0)); | |
1084 | } | |
0c817338 LF |
1085 | } |
1086 | ||
1087 | switch (version) { | |
1088 | case VERSION_B_CHIP_92C: | |
07839b14 | 1089 | versionid = "B_CHIP_92C"; |
0c817338 LF |
1090 | break; |
1091 | case VERSION_B_CHIP_88C: | |
07839b14 | 1092 | versionid = "B_CHIP_88C"; |
0c817338 LF |
1093 | break; |
1094 | case VERSION_A_CHIP_92C: | |
07839b14 | 1095 | versionid = "A_CHIP_92C"; |
0c817338 LF |
1096 | break; |
1097 | case VERSION_A_CHIP_88C: | |
07839b14 | 1098 | versionid = "A_CHIP_88C"; |
0c817338 | 1099 | break; |
0bd899e7 LF |
1100 | case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: |
1101 | versionid = "A_CUT_92C_1T2R"; | |
1102 | break; | |
1103 | case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: | |
1104 | versionid = "A_CUT_92C"; | |
1105 | break; | |
1106 | case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: | |
1107 | versionid = "A_CUT_88C"; | |
1108 | break; | |
1109 | case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: | |
1110 | versionid = "B_CUT_92C_1T2R"; | |
1111 | break; | |
1112 | case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: | |
1113 | versionid = "B_CUT_92C"; | |
1114 | break; | |
1115 | case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: | |
1116 | versionid = "B_CUT_88C"; | |
1117 | break; | |
0c817338 | 1118 | default: |
07839b14 | 1119 | versionid = "Unknown. Bug?"; |
0c817338 LF |
1120 | break; |
1121 | } | |
1122 | ||
0bd899e7 | 1123 | RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, |
07839b14 JP |
1124 | "Chip Version ID: %s\n", versionid); |
1125 | ||
0c817338 LF |
1126 | switch (version & 0x3) { |
1127 | case CHIP_88C: | |
1128 | rtlphy->rf_type = RF_1T1R; | |
1129 | break; | |
1130 | case CHIP_92C: | |
1131 | rtlphy->rf_type = RF_2T2R; | |
1132 | break; | |
1133 | case CHIP_92C_1T2R: | |
1134 | rtlphy->rf_type = RF_1T2R; | |
1135 | break; | |
1136 | default: | |
1137 | rtlphy->rf_type = RF_1T1R; | |
1138 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1139 | "ERROR RF_Type is set!!\n"); |
0c817338 LF |
1140 | break; |
1141 | } | |
1142 | ||
f30d7507 JP |
1143 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n", |
1144 | rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R"); | |
0c817338 LF |
1145 | |
1146 | return version; | |
1147 | } | |
1148 | ||
1149 | static int _rtl92ce_set_media_status(struct ieee80211_hw *hw, | |
1150 | enum nl80211_iftype type) | |
1151 | { | |
1152 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1153 | u8 bt_msr = rtl_read_byte(rtlpriv, MSR); | |
1154 | enum led_ctl_mode ledaction = LED_CTL_NO_LINK; | |
1155 | bt_msr &= 0xfc; | |
1156 | ||
1157 | if (type == NL80211_IFTYPE_UNSPECIFIED || | |
1158 | type == NL80211_IFTYPE_STATION) { | |
1159 | _rtl92ce_stop_tx_beacon(hw); | |
1160 | _rtl92ce_enable_bcn_sub_func(hw); | |
3a16b412 LF |
1161 | } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP || |
1162 | type == NL80211_IFTYPE_MESH_POINT) { | |
0c817338 LF |
1163 | _rtl92ce_resume_tx_beacon(hw); |
1164 | _rtl92ce_disable_bcn_sub_func(hw); | |
1165 | } else { | |
1166 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
1167 | "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n", |
1168 | type); | |
0c817338 LF |
1169 | } |
1170 | ||
1171 | switch (type) { | |
1172 | case NL80211_IFTYPE_UNSPECIFIED: | |
1173 | bt_msr |= MSR_NOLINK; | |
1174 | ledaction = LED_CTL_LINK; | |
1175 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 | 1176 | "Set Network type to NO LINK!\n"); |
0c817338 LF |
1177 | break; |
1178 | case NL80211_IFTYPE_ADHOC: | |
1179 | bt_msr |= MSR_ADHOC; | |
1180 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 | 1181 | "Set Network type to Ad Hoc!\n"); |
0c817338 LF |
1182 | break; |
1183 | case NL80211_IFTYPE_STATION: | |
1184 | bt_msr |= MSR_INFRA; | |
1185 | ledaction = LED_CTL_LINK; | |
1186 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 | 1187 | "Set Network type to STA!\n"); |
0c817338 LF |
1188 | break; |
1189 | case NL80211_IFTYPE_AP: | |
1190 | bt_msr |= MSR_AP; | |
1191 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
f30d7507 | 1192 | "Set Network type to AP!\n"); |
0c817338 | 1193 | break; |
3a16b412 LF |
1194 | case NL80211_IFTYPE_MESH_POINT: |
1195 | bt_msr |= MSR_ADHOC; | |
1196 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, | |
1197 | "Set Network type to Mesh Point!\n"); | |
1198 | break; | |
0c817338 LF |
1199 | default: |
1200 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1201 | "Network type %d not supported!\n", type); |
0c817338 LF |
1202 | return 1; |
1203 | break; | |
1204 | ||
1205 | } | |
1206 | ||
1207 | rtl_write_byte(rtlpriv, (MSR), bt_msr); | |
1208 | rtlpriv->cfg->ops->led_control(hw, ledaction); | |
1209 | if ((bt_msr & 0xfc) == MSR_AP) | |
1210 | rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); | |
1211 | else | |
1212 | rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); | |
1213 | return 0; | |
1214 | } | |
1215 | ||
f73b279c | 1216 | void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) |
0c817338 LF |
1217 | { |
1218 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
e51048cd | 1219 | u32 reg_rcr; |
0c817338 | 1220 | |
f73b279c C |
1221 | if (rtlpriv->psc.rfpwr_state != ERFON) |
1222 | return; | |
0c817338 | 1223 | |
e51048cd PW |
1224 | rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); |
1225 | ||
e10542c4 | 1226 | if (check_bssid) { |
0c817338 LF |
1227 | reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); |
1228 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, | |
1229 | (u8 *) (®_rcr)); | |
1230 | _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); | |
23677ce3 | 1231 | } else if (!check_bssid) { |
0c817338 LF |
1232 | reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); |
1233 | _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0); | |
1234 | rtlpriv->cfg->ops->set_hw_reg(hw, | |
1235 | HW_VAR_RCR, (u8 *) (®_rcr)); | |
1236 | } | |
f73b279c | 1237 | |
0c817338 LF |
1238 | } |
1239 | ||
1240 | int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) | |
1241 | { | |
f73b279c C |
1242 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
1243 | ||
0c817338 LF |
1244 | if (_rtl92ce_set_media_status(hw, type)) |
1245 | return -EOPNOTSUPP; | |
f73b279c C |
1246 | |
1247 | if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { | |
3a16b412 LF |
1248 | if (type != NL80211_IFTYPE_AP && |
1249 | type != NL80211_IFTYPE_MESH_POINT) | |
f73b279c C |
1250 | rtl92ce_set_check_bssid(hw, true); |
1251 | } else { | |
1252 | rtl92ce_set_check_bssid(hw, false); | |
1253 | } | |
1254 | ||
0c817338 LF |
1255 | return 0; |
1256 | } | |
1257 | ||
f73b279c | 1258 | /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */ |
0c817338 LF |
1259 | void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci) |
1260 | { | |
1261 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
0c817338 | 1262 | rtl92c_dm_init_edca_turbo(hw); |
0c817338 LF |
1263 | switch (aci) { |
1264 | case AC1_BK: | |
f73b279c | 1265 | rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); |
0c817338 LF |
1266 | break; |
1267 | case AC0_BE: | |
f73b279c | 1268 | /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */ |
0c817338 LF |
1269 | break; |
1270 | case AC2_VI: | |
f73b279c | 1271 | rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); |
0c817338 LF |
1272 | break; |
1273 | case AC3_VO: | |
f73b279c | 1274 | rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); |
0c817338 LF |
1275 | break; |
1276 | default: | |
9d833ed7 | 1277 | RT_ASSERT(false, "invalid aci: %d !\n", aci); |
0c817338 LF |
1278 | break; |
1279 | } | |
1280 | } | |
1281 | ||
1282 | void rtl92ce_enable_interrupt(struct ieee80211_hw *hw) | |
1283 | { | |
1284 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1285 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1286 | ||
1287 | rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); | |
1288 | rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); | |
0c817338 LF |
1289 | } |
1290 | ||
1291 | void rtl92ce_disable_interrupt(struct ieee80211_hw *hw) | |
1292 | { | |
1293 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1294 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1295 | ||
1296 | rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); | |
1297 | rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); | |
2e69167c | 1298 | synchronize_irq(rtlpci->pdev->irq); |
0c817338 LF |
1299 | } |
1300 | ||
1301 | static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw) | |
1302 | { | |
1303 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 1304 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0bd899e7 | 1305 | struct rtl_hal *rtlhal = rtl_hal(rtlpriv); |
0c817338 | 1306 | u8 u1b_tmp; |
f73b279c | 1307 | u32 u4b_tmp; |
0c817338 LF |
1308 | |
1309 | rtlpriv->intf_ops->enable_aspm(hw); | |
1310 | rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); | |
1311 | rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); | |
1312 | rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); | |
1313 | rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); | |
1314 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); | |
1315 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); | |
b0302aba | 1316 | if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) |
0c817338 LF |
1317 | rtl92c_firmware_selfreset(hw); |
1318 | rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); | |
1319 | rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); | |
1320 | rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000); | |
1321 | u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL); | |
f73b279c C |
1322 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
1323 | ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || | |
1324 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) { | |
1325 | rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 | | |
1326 | (u1b_tmp << 8)); | |
1327 | } else { | |
1328 | rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 | | |
1329 | (u1b_tmp << 8)); | |
1330 | } | |
0c817338 LF |
1331 | rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790); |
1332 | rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080); | |
1333 | rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80); | |
0bd899e7 LF |
1334 | if (!IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) |
1335 | rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); | |
f73b279c C |
1336 | if (rtlpcipriv->bt_coexist.bt_coexistence) { |
1337 | u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL); | |
1338 | u4b_tmp |= 0x03824800; | |
1339 | rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp); | |
1340 | } else { | |
1341 | rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e); | |
1342 | } | |
1343 | ||
0c817338 LF |
1344 | rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); |
1345 | rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10); | |
1346 | } | |
1347 | ||
1348 | void rtl92ce_card_disable(struct ieee80211_hw *hw) | |
1349 | { | |
1350 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1351 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
1352 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1353 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1354 | enum nl80211_iftype opmode; | |
1355 | ||
1356 | mac->link_state = MAC80211_NOLINK; | |
1357 | opmode = NL80211_IFTYPE_UNSPECIFIED; | |
1358 | _rtl92ce_set_media_status(hw, opmode); | |
1359 | if (rtlpci->driver_is_goingto_unload || | |
1360 | ppsc->rfoff_reason > RF_CHANGE_BY_PS) | |
1361 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); | |
1362 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
1363 | _rtl92ce_poweroff_adapter(hw); | |
0bd899e7 LF |
1364 | |
1365 | /* after power off we should do iqk again */ | |
1366 | rtlpriv->phy.iqk_initialized = false; | |
0c817338 LF |
1367 | } |
1368 | ||
1369 | void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw, | |
1370 | u32 *p_inta, u32 *p_intb) | |
1371 | { | |
1372 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1373 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1374 | ||
1375 | *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; | |
1376 | rtl_write_dword(rtlpriv, ISR, *p_inta); | |
1377 | ||
1378 | /* | |
1379 | * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; | |
1380 | * rtl_write_dword(rtlpriv, ISR + 4, *p_intb); | |
1381 | */ | |
1382 | } | |
1383 | ||
1384 | void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw) | |
1385 | { | |
1386 | ||
1387 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1388 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1389 | u16 bcn_interval, atim_window; | |
1390 | ||
1391 | bcn_interval = mac->beacon_interval; | |
1392 | atim_window = 2; /*FIX MERGE */ | |
1393 | rtl92ce_disable_interrupt(hw); | |
1394 | rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); | |
1395 | rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); | |
1396 | rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); | |
1397 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); | |
1398 | rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); | |
1399 | rtl_write_byte(rtlpriv, 0x606, 0x30); | |
1400 | rtl92ce_enable_interrupt(hw); | |
1401 | } | |
1402 | ||
1403 | void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw) | |
1404 | { | |
1405 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1406 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1407 | u16 bcn_interval = mac->beacon_interval; | |
1408 | ||
1409 | RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, | |
f30d7507 | 1410 | "beacon_interval:%d\n", bcn_interval); |
0c817338 LF |
1411 | rtl92ce_disable_interrupt(hw); |
1412 | rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); | |
1413 | rtl92ce_enable_interrupt(hw); | |
1414 | } | |
1415 | ||
1416 | void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw, | |
1417 | u32 add_msr, u32 rm_msr) | |
1418 | { | |
1419 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1420 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1421 | ||
f30d7507 JP |
1422 | RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n", |
1423 | add_msr, rm_msr); | |
f73b279c | 1424 | |
0c817338 LF |
1425 | if (add_msr) |
1426 | rtlpci->irq_mask[0] |= add_msr; | |
1427 | if (rm_msr) | |
1428 | rtlpci->irq_mask[0] &= (~rm_msr); | |
1429 | rtl92ce_disable_interrupt(hw); | |
1430 | rtl92ce_enable_interrupt(hw); | |
1431 | } | |
1432 | ||
0c817338 LF |
1433 | static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, |
1434 | bool autoload_fail, | |
1435 | u8 *hwinfo) | |
1436 | { | |
1437 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1438 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1439 | u8 rf_path, index, tempval; | |
1440 | u16 i; | |
1441 | ||
1442 | for (rf_path = 0; rf_path < 2; rf_path++) { | |
1443 | for (i = 0; i < 3; i++) { | |
1444 | if (!autoload_fail) { | |
1445 | rtlefuse-> | |
1446 | eeprom_chnlarea_txpwr_cck[rf_path][i] = | |
1447 | hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i]; | |
1448 | rtlefuse-> | |
1449 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = | |
1450 | hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + | |
1451 | i]; | |
1452 | } else { | |
1453 | rtlefuse-> | |
1454 | eeprom_chnlarea_txpwr_cck[rf_path][i] = | |
1455 | EEPROM_DEFAULT_TXPOWERLEVEL; | |
1456 | rtlefuse-> | |
1457 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] = | |
1458 | EEPROM_DEFAULT_TXPOWERLEVEL; | |
1459 | } | |
1460 | } | |
1461 | } | |
1462 | ||
1463 | for (i = 0; i < 3; i++) { | |
1464 | if (!autoload_fail) | |
1465 | tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i]; | |
1466 | else | |
1467 | tempval = EEPROM_DEFAULT_HT40_2SDIFF; | |
da17fcff | 1468 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] = |
0c817338 | 1469 | (tempval & 0xf); |
da17fcff | 1470 | rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] = |
0c817338 LF |
1471 | ((tempval & 0xf0) >> 4); |
1472 | } | |
1473 | ||
1474 | for (rf_path = 0; rf_path < 2; rf_path++) | |
1475 | for (i = 0; i < 3; i++) | |
1476 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
4c48869f JP |
1477 | "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", |
1478 | rf_path, i, | |
1479 | rtlefuse-> | |
1480 | eeprom_chnlarea_txpwr_cck[rf_path][i]); | |
0c817338 LF |
1481 | for (rf_path = 0; rf_path < 2; rf_path++) |
1482 | for (i = 0; i < 3; i++) | |
1483 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
4c48869f JP |
1484 | "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n", |
1485 | rf_path, i, | |
1486 | rtlefuse-> | |
1487 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]); | |
0c817338 LF |
1488 | for (rf_path = 0; rf_path < 2; rf_path++) |
1489 | for (i = 0; i < 3; i++) | |
1490 | RTPRINT(rtlpriv, FINIT, INIT_EEPROM, | |
4c48869f JP |
1491 | "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n", |
1492 | rf_path, i, | |
1493 | rtlefuse-> | |
da17fcff | 1494 | eprom_chnl_txpwr_ht40_2sdf[rf_path][i]); |
0c817338 LF |
1495 | |
1496 | for (rf_path = 0; rf_path < 2; rf_path++) { | |
1497 | for (i = 0; i < 14; i++) { | |
1498 | index = _rtl92c_get_chnl_group((u8) i); | |
1499 | ||
1500 | rtlefuse->txpwrlevel_cck[rf_path][i] = | |
1501 | rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index]; | |
1502 | rtlefuse->txpwrlevel_ht40_1s[rf_path][i] = | |
1503 | rtlefuse-> | |
1504 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][index]; | |
1505 | ||
1506 | if ((rtlefuse-> | |
1507 | eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] - | |
1508 | rtlefuse-> | |
da17fcff | 1509 | eprom_chnl_txpwr_ht40_2sdf[rf_path][index]) |
0c817338 LF |
1510 | > 0) { |
1511 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = | |
1512 | rtlefuse-> | |
1513 | eeprom_chnlarea_txpwr_ht40_1s[rf_path] | |
1514 | [index] - | |
1515 | rtlefuse-> | |
da17fcff | 1516 | eprom_chnl_txpwr_ht40_2sdf[rf_path] |
0c817338 LF |
1517 | [index]; |
1518 | } else { | |
1519 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0; | |
1520 | } | |
1521 | } | |
1522 | ||
1523 | for (i = 0; i < 14; i++) { | |
e6deaf81 | 1524 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1525 | "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", |
1526 | rf_path, i, | |
1527 | rtlefuse->txpwrlevel_cck[rf_path][i], | |
1528 | rtlefuse->txpwrlevel_ht40_1s[rf_path][i], | |
1529 | rtlefuse->txpwrlevel_ht40_2s[rf_path][i]); | |
0c817338 LF |
1530 | } |
1531 | } | |
1532 | ||
1533 | for (i = 0; i < 3; i++) { | |
1534 | if (!autoload_fail) { | |
1535 | rtlefuse->eeprom_pwrlimit_ht40[i] = | |
1536 | hwinfo[EEPROM_TXPWR_GROUP + i]; | |
1537 | rtlefuse->eeprom_pwrlimit_ht20[i] = | |
1538 | hwinfo[EEPROM_TXPWR_GROUP + 3 + i]; | |
1539 | } else { | |
1540 | rtlefuse->eeprom_pwrlimit_ht40[i] = 0; | |
1541 | rtlefuse->eeprom_pwrlimit_ht20[i] = 0; | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | for (rf_path = 0; rf_path < 2; rf_path++) { | |
1546 | for (i = 0; i < 14; i++) { | |
1547 | index = _rtl92c_get_chnl_group((u8) i); | |
1548 | ||
1549 | if (rf_path == RF90_PATH_A) { | |
1550 | rtlefuse->pwrgroup_ht20[rf_path][i] = | |
1551 | (rtlefuse->eeprom_pwrlimit_ht20[index] | |
1552 | & 0xf); | |
1553 | rtlefuse->pwrgroup_ht40[rf_path][i] = | |
1554 | (rtlefuse->eeprom_pwrlimit_ht40[index] | |
1555 | & 0xf); | |
1556 | } else if (rf_path == RF90_PATH_B) { | |
1557 | rtlefuse->pwrgroup_ht20[rf_path][i] = | |
1558 | ((rtlefuse->eeprom_pwrlimit_ht20[index] | |
1559 | & 0xf0) >> 4); | |
1560 | rtlefuse->pwrgroup_ht40[rf_path][i] = | |
1561 | ((rtlefuse->eeprom_pwrlimit_ht40[index] | |
1562 | & 0xf0) >> 4); | |
1563 | } | |
1564 | ||
e6deaf81 | 1565 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1566 | "RF-%d pwrgroup_ht20[%d] = 0x%x\n", |
1567 | rf_path, i, | |
1568 | rtlefuse->pwrgroup_ht20[rf_path][i]); | |
e6deaf81 | 1569 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1570 | "RF-%d pwrgroup_ht40[%d] = 0x%x\n", |
1571 | rf_path, i, | |
1572 | rtlefuse->pwrgroup_ht40[rf_path][i]); | |
0c817338 LF |
1573 | } |
1574 | } | |
1575 | ||
1576 | for (i = 0; i < 14; i++) { | |
1577 | index = _rtl92c_get_chnl_group((u8) i); | |
1578 | ||
1579 | if (!autoload_fail) | |
1580 | tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index]; | |
1581 | else | |
1582 | tempval = EEPROM_DEFAULT_HT20_DIFF; | |
1583 | ||
1584 | rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF); | |
1585 | rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] = | |
1586 | ((tempval >> 4) & 0xF); | |
1587 | ||
1588 | if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3)) | |
1589 | rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0; | |
1590 | ||
1591 | if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3)) | |
1592 | rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0; | |
1593 | ||
1594 | index = _rtl92c_get_chnl_group((u8) i); | |
1595 | ||
1596 | if (!autoload_fail) | |
1597 | tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index]; | |
1598 | else | |
1599 | tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; | |
1600 | ||
1601 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF); | |
1602 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] = | |
1603 | ((tempval >> 4) & 0xF); | |
1604 | } | |
1605 | ||
1606 | rtlefuse->legacy_ht_txpowerdiff = | |
1607 | rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7]; | |
1608 | ||
1609 | for (i = 0; i < 14; i++) | |
e6deaf81 | 1610 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1611 | "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", |
1612 | i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]); | |
0c817338 | 1613 | for (i = 0; i < 14; i++) |
e6deaf81 | 1614 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1615 | "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", |
1616 | i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]); | |
0c817338 | 1617 | for (i = 0; i < 14; i++) |
e6deaf81 | 1618 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1619 | "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", |
1620 | i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]); | |
0c817338 | 1621 | for (i = 0; i < 14; i++) |
e6deaf81 | 1622 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f JP |
1623 | "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", |
1624 | i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]); | |
0c817338 LF |
1625 | |
1626 | if (!autoload_fail) | |
1627 | rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7); | |
1628 | else | |
1629 | rtlefuse->eeprom_regulatory = 0; | |
e6deaf81 | 1630 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f | 1631 | "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory); |
0c817338 LF |
1632 | |
1633 | if (!autoload_fail) { | |
1634 | rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A]; | |
1635 | rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B]; | |
1636 | } else { | |
1637 | rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI; | |
1638 | rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI; | |
1639 | } | |
e6deaf81 | 1640 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n", |
4c48869f JP |
1641 | rtlefuse->eeprom_tssi[RF90_PATH_A], |
1642 | rtlefuse->eeprom_tssi[RF90_PATH_B]); | |
0c817338 LF |
1643 | |
1644 | if (!autoload_fail) | |
1645 | tempval = hwinfo[EEPROM_THERMAL_METER]; | |
1646 | else | |
1647 | tempval = EEPROM_DEFAULT_THERMALMETER; | |
1648 | rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); | |
1649 | ||
1650 | if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) | |
7ea47240 | 1651 | rtlefuse->apk_thermalmeterignore = true; |
0c817338 LF |
1652 | |
1653 | rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; | |
e6deaf81 | 1654 | RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, |
4c48869f | 1655 | "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); |
0c817338 LF |
1656 | } |
1657 | ||
1658 | static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw) | |
1659 | { | |
1660 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1661 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1662 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1663 | u16 i, usvalue; | |
1664 | u8 hwinfo[HWSET_MAX_SIZE]; | |
1665 | u16 eeprom_id; | |
1666 | ||
1667 | if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) { | |
1668 | rtl_efuse_shadow_map_update(hw); | |
1669 | ||
1670 | memcpy((void *)hwinfo, | |
1671 | (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0], | |
1672 | HWSET_MAX_SIZE); | |
1673 | } else if (rtlefuse->epromtype == EEPROM_93C46) { | |
1674 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1675 | "RTL819X Not boot from eeprom, check it !!"); |
0c817338 LF |
1676 | } |
1677 | ||
af08687b | 1678 | RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP", |
0c817338 LF |
1679 | hwinfo, HWSET_MAX_SIZE); |
1680 | ||
1681 | eeprom_id = *((u16 *)&hwinfo[0]); | |
1682 | if (eeprom_id != RTL8190_EEPROM_ID) { | |
1683 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 | 1684 | "EEPROM ID(%#x) is invalid!!\n", eeprom_id); |
0c817338 LF |
1685 | rtlefuse->autoload_failflag = true; |
1686 | } else { | |
f30d7507 | 1687 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); |
0c817338 LF |
1688 | rtlefuse->autoload_failflag = false; |
1689 | } | |
1690 | ||
e10542c4 | 1691 | if (rtlefuse->autoload_failflag) |
0c817338 LF |
1692 | return; |
1693 | ||
3a16b412 LF |
1694 | rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; |
1695 | rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID]; | |
1696 | rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID]; | |
1697 | rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID]; | |
1698 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1699 | "EEPROMId = 0x%4x\n", eeprom_id); | |
1700 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1701 | "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); | |
1702 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1703 | "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); | |
1704 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1705 | "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); | |
1706 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1707 | "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); | |
1708 | ||
0c817338 LF |
1709 | for (i = 0; i < 6; i += 2) { |
1710 | usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; | |
1711 | *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; | |
1712 | } | |
1713 | ||
f30d7507 | 1714 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); |
0c817338 LF |
1715 | |
1716 | _rtl92ce_read_txpower_info_from_hwpg(hw, | |
1717 | rtlefuse->autoload_failflag, | |
1718 | hwinfo); | |
1719 | ||
f73b279c C |
1720 | rtl8192ce_read_bt_coexist_info_from_hwpg(hw, |
1721 | rtlefuse->autoload_failflag, | |
1722 | hwinfo); | |
1723 | ||
2c208890 | 1724 | rtlefuse->eeprom_channelplan = *&hwinfo[EEPROM_CHANNELPLAN]; |
0c817338 | 1725 | rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; |
7ea47240 | 1726 | rtlefuse->txpwr_fromeprom = true; |
2c208890 | 1727 | rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMER_ID]; |
0c817338 LF |
1728 | |
1729 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 1730 | "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); |
0c817338 | 1731 | |
f73b279c C |
1732 | /* set channel paln to world wide 13 */ |
1733 | rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13; | |
1734 | ||
0c817338 LF |
1735 | if (rtlhal->oem_id == RT_CID_DEFAULT) { |
1736 | switch (rtlefuse->eeprom_oemid) { | |
1737 | case EEPROM_CID_DEFAULT: | |
1738 | if (rtlefuse->eeprom_did == 0x8176) { | |
1739 | if ((rtlefuse->eeprom_svid == 0x103C && | |
1740 | rtlefuse->eeprom_smid == 0x1629)) | |
2cddad3c | 1741 | rtlhal->oem_id = RT_CID_819X_HP; |
0c817338 LF |
1742 | else |
1743 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1744 | } else { | |
1745 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1746 | } | |
1747 | break; | |
1748 | case EEPROM_CID_TOSHIBA: | |
1749 | rtlhal->oem_id = RT_CID_TOSHIBA; | |
1750 | break; | |
1751 | case EEPROM_CID_QMI: | |
2cddad3c | 1752 | rtlhal->oem_id = RT_CID_819X_QMI; |
0c817338 LF |
1753 | break; |
1754 | case EEPROM_CID_WHQL: | |
1755 | default: | |
1756 | rtlhal->oem_id = RT_CID_DEFAULT; | |
1757 | break; | |
1758 | ||
1759 | } | |
1760 | } | |
1761 | ||
1762 | } | |
1763 | ||
1764 | static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw) | |
1765 | { | |
1766 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1767 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1768 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1769 | ||
1770 | switch (rtlhal->oem_id) { | |
2cddad3c | 1771 | case RT_CID_819X_HP: |
7ea47240 | 1772 | pcipriv->ledctl.led_opendrain = true; |
0c817338 | 1773 | break; |
2cddad3c | 1774 | case RT_CID_819X_LENOVO: |
0c817338 LF |
1775 | case RT_CID_DEFAULT: |
1776 | case RT_CID_TOSHIBA: | |
1777 | case RT_CID_CCX: | |
2cddad3c | 1778 | case RT_CID_819X_ACER: |
0c817338 LF |
1779 | case RT_CID_WHQL: |
1780 | default: | |
1781 | break; | |
1782 | } | |
1783 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 | 1784 | "RT Customized ID: 0x%02X\n", rtlhal->oem_id); |
0c817338 LF |
1785 | } |
1786 | ||
1787 | void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw) | |
1788 | { | |
1789 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1790 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
1791 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1792 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1793 | u8 tmp_u1b; | |
1794 | ||
1795 | rtlhal->version = _rtl92ce_read_chip_version(hw); | |
1796 | if (get_rf_type(rtlphy) == RF_1T1R) | |
7ea47240 | 1797 | rtlpriv->dm.rfpath_rxenable[0] = true; |
0c817338 | 1798 | else |
7ea47240 LF |
1799 | rtlpriv->dm.rfpath_rxenable[0] = |
1800 | rtlpriv->dm.rfpath_rxenable[1] = true; | |
f30d7507 JP |
1801 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", |
1802 | rtlhal->version); | |
0c817338 LF |
1803 | tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); |
1804 | if (tmp_u1b & BIT(4)) { | |
f30d7507 | 1805 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); |
0c817338 LF |
1806 | rtlefuse->epromtype = EEPROM_93C46; |
1807 | } else { | |
f30d7507 | 1808 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); |
0c817338 LF |
1809 | rtlefuse->epromtype = EEPROM_BOOT_EFUSE; |
1810 | } | |
1811 | if (tmp_u1b & BIT(5)) { | |
f30d7507 | 1812 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); |
0c817338 LF |
1813 | rtlefuse->autoload_failflag = false; |
1814 | _rtl92ce_read_adapter_info(hw); | |
1815 | } else { | |
f30d7507 | 1816 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n"); |
0c817338 | 1817 | } |
0c817338 LF |
1818 | _rtl92ce_hal_customized_behavior(hw); |
1819 | } | |
1820 | ||
f73b279c C |
1821 | static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw, |
1822 | struct ieee80211_sta *sta) | |
0c817338 LF |
1823 | { |
1824 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
f73b279c | 1825 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); |
0c817338 LF |
1826 | struct rtl_phy *rtlphy = &(rtlpriv->phy); |
1827 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
f73b279c C |
1828 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
1829 | u32 ratr_value; | |
0c817338 | 1830 | u8 ratr_index = 0; |
7ea47240 | 1831 | u8 nmode = mac->ht_enable; |
f73b279c | 1832 | u8 mimo_ps = IEEE80211_SMPS_OFF; |
0c817338 LF |
1833 | u16 shortgi_rate; |
1834 | u32 tmp_ratr_value; | |
7ea47240 | 1835 | u8 curtxbw_40mhz = mac->bw_40; |
f73b279c C |
1836 | u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? |
1837 | 1 : 0; | |
1838 | u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? | |
1839 | 1 : 0; | |
0c817338 LF |
1840 | enum wireless_mode wirelessmode = mac->mode; |
1841 | ||
f73b279c C |
1842 | if (rtlhal->current_bandtype == BAND_ON_5G) |
1843 | ratr_value = sta->supp_rates[1] << 4; | |
1844 | else | |
1845 | ratr_value = sta->supp_rates[0]; | |
3a16b412 LF |
1846 | if (mac->opmode == NL80211_IFTYPE_ADHOC) |
1847 | ratr_value = 0xfff; | |
1848 | ||
f73b279c C |
1849 | ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 | |
1850 | sta->ht_cap.mcs.rx_mask[0] << 12); | |
0c817338 LF |
1851 | switch (wirelessmode) { |
1852 | case WIRELESS_MODE_B: | |
1853 | if (ratr_value & 0x0000000c) | |
1854 | ratr_value &= 0x0000000d; | |
1855 | else | |
1856 | ratr_value &= 0x0000000f; | |
1857 | break; | |
1858 | case WIRELESS_MODE_G: | |
1859 | ratr_value &= 0x00000FF5; | |
1860 | break; | |
1861 | case WIRELESS_MODE_N_24G: | |
1862 | case WIRELESS_MODE_N_5G: | |
7ea47240 | 1863 | nmode = 1; |
f73b279c | 1864 | if (mimo_ps == IEEE80211_SMPS_STATIC) { |
0c817338 LF |
1865 | ratr_value &= 0x0007F005; |
1866 | } else { | |
1867 | u32 ratr_mask; | |
1868 | ||
1869 | if (get_rf_type(rtlphy) == RF_1T2R || | |
1870 | get_rf_type(rtlphy) == RF_1T1R) | |
1871 | ratr_mask = 0x000ff005; | |
1872 | else | |
1873 | ratr_mask = 0x0f0ff005; | |
1874 | ||
1875 | ratr_value &= ratr_mask; | |
1876 | } | |
1877 | break; | |
1878 | default: | |
1879 | if (rtlphy->rf_type == RF_1T2R) | |
1880 | ratr_value &= 0x000ff0ff; | |
1881 | else | |
1882 | ratr_value &= 0x0f0ff0ff; | |
1883 | ||
1884 | break; | |
1885 | } | |
1886 | ||
f73b279c C |
1887 | if ((rtlpcipriv->bt_coexist.bt_coexistence) && |
1888 | (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) && | |
1889 | (rtlpcipriv->bt_coexist.bt_cur_state) && | |
1890 | (rtlpcipriv->bt_coexist.bt_ant_isolation) && | |
1891 | ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) || | |
1892 | (rtlpcipriv->bt_coexist.bt_service == BT_BUSY))) | |
1893 | ratr_value &= 0x0fffcfc0; | |
1894 | else | |
1895 | ratr_value &= 0x0FFFFFFF; | |
0c817338 | 1896 | |
f73b279c C |
1897 | if (nmode && ((curtxbw_40mhz && |
1898 | curshortgi_40mhz) || (!curtxbw_40mhz && | |
1899 | curshortgi_20mhz))) { | |
0c817338 LF |
1900 | |
1901 | ratr_value |= 0x10000000; | |
1902 | tmp_ratr_value = (ratr_value >> 12); | |
1903 | ||
1904 | for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { | |
1905 | if ((1 << shortgi_rate) & tmp_ratr_value) | |
1906 | break; | |
1907 | } | |
1908 | ||
1909 | shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | | |
1910 | (shortgi_rate << 4) | (shortgi_rate); | |
1911 | } | |
1912 | ||
1913 | rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); | |
1914 | ||
f30d7507 JP |
1915 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", |
1916 | rtl_read_dword(rtlpriv, REG_ARFR0)); | |
0c817338 LF |
1917 | } |
1918 | ||
f73b279c C |
1919 | static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, |
1920 | struct ieee80211_sta *sta, u8 rssi_level) | |
0c817338 LF |
1921 | { |
1922 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1923 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
1924 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
f73b279c C |
1925 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
1926 | struct rtl_sta_info *sta_entry = NULL; | |
1927 | u32 ratr_bitmap; | |
0c817338 | 1928 | u8 ratr_index; |
e1a0c6b3 JB |
1929 | u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; |
1930 | u8 curshortgi_40mhz = curtxbw_40mhz && | |
1931 | (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? | |
f73b279c C |
1932 | 1 : 0; |
1933 | u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? | |
1934 | 1 : 0; | |
1935 | enum wireless_mode wirelessmode = 0; | |
7ea47240 | 1936 | bool shortgi = false; |
0c817338 LF |
1937 | u8 rate_mask[5]; |
1938 | u8 macid = 0; | |
f73b279c C |
1939 | u8 mimo_ps = IEEE80211_SMPS_OFF; |
1940 | ||
1941 | sta_entry = (struct rtl_sta_info *) sta->drv_priv; | |
1942 | wirelessmode = sta_entry->wireless_mode; | |
3a16b412 LF |
1943 | if (mac->opmode == NL80211_IFTYPE_STATION || |
1944 | mac->opmode == NL80211_IFTYPE_MESH_POINT) | |
f73b279c C |
1945 | curtxbw_40mhz = mac->bw_40; |
1946 | else if (mac->opmode == NL80211_IFTYPE_AP || | |
1947 | mac->opmode == NL80211_IFTYPE_ADHOC) | |
1948 | macid = sta->aid + 1; | |
1949 | ||
1950 | if (rtlhal->current_bandtype == BAND_ON_5G) | |
1951 | ratr_bitmap = sta->supp_rates[1] << 4; | |
1952 | else | |
1953 | ratr_bitmap = sta->supp_rates[0]; | |
3a16b412 LF |
1954 | if (mac->opmode == NL80211_IFTYPE_ADHOC) |
1955 | ratr_bitmap = 0xfff; | |
f73b279c C |
1956 | ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 | |
1957 | sta->ht_cap.mcs.rx_mask[0] << 12); | |
0c817338 LF |
1958 | switch (wirelessmode) { |
1959 | case WIRELESS_MODE_B: | |
1960 | ratr_index = RATR_INX_WIRELESS_B; | |
1961 | if (ratr_bitmap & 0x0000000c) | |
1962 | ratr_bitmap &= 0x0000000d; | |
1963 | else | |
1964 | ratr_bitmap &= 0x0000000f; | |
1965 | break; | |
1966 | case WIRELESS_MODE_G: | |
1967 | ratr_index = RATR_INX_WIRELESS_GB; | |
1968 | ||
1969 | if (rssi_level == 1) | |
1970 | ratr_bitmap &= 0x00000f00; | |
1971 | else if (rssi_level == 2) | |
1972 | ratr_bitmap &= 0x00000ff0; | |
1973 | else | |
1974 | ratr_bitmap &= 0x00000ff5; | |
1975 | break; | |
1976 | case WIRELESS_MODE_A: | |
1977 | ratr_index = RATR_INX_WIRELESS_A; | |
1978 | ratr_bitmap &= 0x00000ff0; | |
1979 | break; | |
1980 | case WIRELESS_MODE_N_24G: | |
1981 | case WIRELESS_MODE_N_5G: | |
1982 | ratr_index = RATR_INX_WIRELESS_NGB; | |
1983 | ||
f73b279c | 1984 | if (mimo_ps == IEEE80211_SMPS_STATIC) { |
0c817338 LF |
1985 | if (rssi_level == 1) |
1986 | ratr_bitmap &= 0x00070000; | |
1987 | else if (rssi_level == 2) | |
1988 | ratr_bitmap &= 0x0007f000; | |
1989 | else | |
1990 | ratr_bitmap &= 0x0007f005; | |
1991 | } else { | |
1992 | if (rtlphy->rf_type == RF_1T2R || | |
1993 | rtlphy->rf_type == RF_1T1R) { | |
7ea47240 | 1994 | if (curtxbw_40mhz) { |
0c817338 LF |
1995 | if (rssi_level == 1) |
1996 | ratr_bitmap &= 0x000f0000; | |
1997 | else if (rssi_level == 2) | |
1998 | ratr_bitmap &= 0x000ff000; | |
1999 | else | |
2000 | ratr_bitmap &= 0x000ff015; | |
2001 | } else { | |
2002 | if (rssi_level == 1) | |
2003 | ratr_bitmap &= 0x000f0000; | |
2004 | else if (rssi_level == 2) | |
2005 | ratr_bitmap &= 0x000ff000; | |
2006 | else | |
2007 | ratr_bitmap &= 0x000ff005; | |
2008 | } | |
2009 | } else { | |
7ea47240 | 2010 | if (curtxbw_40mhz) { |
0c817338 LF |
2011 | if (rssi_level == 1) |
2012 | ratr_bitmap &= 0x0f0f0000; | |
2013 | else if (rssi_level == 2) | |
2014 | ratr_bitmap &= 0x0f0ff000; | |
2015 | else | |
2016 | ratr_bitmap &= 0x0f0ff015; | |
2017 | } else { | |
2018 | if (rssi_level == 1) | |
2019 | ratr_bitmap &= 0x0f0f0000; | |
2020 | else if (rssi_level == 2) | |
2021 | ratr_bitmap &= 0x0f0ff000; | |
2022 | else | |
2023 | ratr_bitmap &= 0x0f0ff005; | |
2024 | } | |
2025 | } | |
2026 | } | |
2027 | ||
7ea47240 LF |
2028 | if ((curtxbw_40mhz && curshortgi_40mhz) || |
2029 | (!curtxbw_40mhz && curshortgi_20mhz)) { | |
0c817338 LF |
2030 | |
2031 | if (macid == 0) | |
7ea47240 | 2032 | shortgi = true; |
0c817338 | 2033 | else if (macid == 1) |
7ea47240 | 2034 | shortgi = false; |
0c817338 LF |
2035 | } |
2036 | break; | |
2037 | default: | |
2038 | ratr_index = RATR_INX_WIRELESS_NGB; | |
2039 | ||
2040 | if (rtlphy->rf_type == RF_1T2R) | |
2041 | ratr_bitmap &= 0x000ff0ff; | |
2042 | else | |
2043 | ratr_bitmap &= 0x0f0ff0ff; | |
2044 | break; | |
2045 | } | |
0bd899e7 LF |
2046 | sta_entry->ratr_index = ratr_index; |
2047 | ||
0c817338 | 2048 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, |
f30d7507 | 2049 | "ratr_bitmap :%x\n", ratr_bitmap); |
8e2c406a LF |
2050 | *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) | |
2051 | (ratr_index << 28); | |
7ea47240 | 2052 | rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80; |
f30d7507 | 2053 | RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, |
ed9f0ed3 AS |
2054 | "Rate_index:%x, ratr_val:%x, %5phC\n", |
2055 | ratr_index, ratr_bitmap, rate_mask); | |
0c817338 | 2056 | rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask); |
f73b279c C |
2057 | |
2058 | if (macid != 0) | |
2059 | sta_entry->ratr_index = ratr_index; | |
2060 | } | |
2061 | ||
2062 | void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw, | |
2063 | struct ieee80211_sta *sta, u8 rssi_level) | |
2064 | { | |
2065 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2066 | ||
2067 | if (rtlpriv->dm.useramask) | |
2068 | rtl92ce_update_hal_rate_mask(hw, sta, rssi_level); | |
2069 | else | |
2070 | rtl92ce_update_hal_rate_table(hw, sta); | |
0c817338 LF |
2071 | } |
2072 | ||
2073 | void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw) | |
2074 | { | |
2075 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2076 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2077 | u16 sifs_timer; | |
2078 | ||
2079 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, | |
2c208890 | 2080 | &mac->slot_time); |
0c817338 LF |
2081 | if (!mac->ht_enable) |
2082 | sifs_timer = 0x0a0a; | |
2083 | else | |
2084 | sifs_timer = 0x1010; | |
2085 | rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); | |
2086 | } | |
2087 | ||
f73b279c | 2088 | bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) |
0c817338 LF |
2089 | { |
2090 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2091 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
2092 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
6c0d4988 | 2093 | enum rf_pwrstate e_rfpowerstate_toset; |
0c817338 | 2094 | u8 u1tmp; |
7ea47240 | 2095 | bool actuallyset = false; |
0c817338 LF |
2096 | unsigned long flag; |
2097 | ||
f73b279c | 2098 | if (rtlpci->being_init_adapter) |
0c817338 LF |
2099 | return false; |
2100 | ||
7ea47240 | 2101 | if (ppsc->swrf_processing) |
0c817338 LF |
2102 | return false; |
2103 | ||
2104 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); | |
2105 | if (ppsc->rfchange_inprogress) { | |
2106 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2107 | return false; | |
2108 | } else { | |
2109 | ppsc->rfchange_inprogress = true; | |
2110 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2111 | } | |
2112 | ||
0c817338 LF |
2113 | rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, |
2114 | REG_MAC_PINMUX_CFG)&~(BIT(3))); | |
2115 | ||
2116 | u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); | |
2117 | e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; | |
2118 | ||
e10542c4 | 2119 | if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) { |
0c817338 | 2120 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, |
f30d7507 | 2121 | "GPIOChangeRF - HW Radio ON, RF ON\n"); |
0c817338 LF |
2122 | |
2123 | e_rfpowerstate_toset = ERFON; | |
7ea47240 LF |
2124 | ppsc->hwradiooff = false; |
2125 | actuallyset = true; | |
23677ce3 | 2126 | } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { |
0c817338 | 2127 | RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, |
f30d7507 | 2128 | "GPIOChangeRF - HW Radio OFF, RF OFF\n"); |
0c817338 LF |
2129 | |
2130 | e_rfpowerstate_toset = ERFOFF; | |
7ea47240 LF |
2131 | ppsc->hwradiooff = true; |
2132 | actuallyset = true; | |
0c817338 LF |
2133 | } |
2134 | ||
7ea47240 | 2135 | if (actuallyset) { |
0c817338 LF |
2136 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); |
2137 | ppsc->rfchange_inprogress = false; | |
2138 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
f73b279c | 2139 | } else { |
0c817338 LF |
2140 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) |
2141 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
2142 | ||
0c817338 LF |
2143 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); |
2144 | ppsc->rfchange_inprogress = false; | |
2145 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); | |
2146 | } | |
2147 | ||
2148 | *valid = 1; | |
7ea47240 | 2149 | return !ppsc->hwradiooff; |
0c817338 LF |
2150 | |
2151 | } | |
2152 | ||
2153 | void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index, | |
2154 | u8 *p_macaddr, bool is_group, u8 enc_algo, | |
2155 | bool is_wepkey, bool clear_all) | |
2156 | { | |
2157 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2158 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
2159 | struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); | |
2160 | u8 *macaddr = p_macaddr; | |
2161 | u32 entry_id = 0; | |
2162 | bool is_pairwise = false; | |
2163 | ||
2164 | static u8 cam_const_addr[4][6] = { | |
2165 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, | |
2166 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, | |
2167 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, | |
2168 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} | |
2169 | }; | |
2170 | static u8 cam_const_broad[] = { | |
2171 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff | |
2172 | }; | |
2173 | ||
2174 | if (clear_all) { | |
2175 | u8 idx = 0; | |
2176 | u8 cam_offset = 0; | |
2177 | u8 clear_number = 5; | |
2178 | ||
f30d7507 | 2179 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); |
0c817338 LF |
2180 | |
2181 | for (idx = 0; idx < clear_number; idx++) { | |
2182 | rtl_cam_mark_invalid(hw, cam_offset + idx); | |
2183 | rtl_cam_empty_entry(hw, cam_offset + idx); | |
2184 | ||
2185 | if (idx < 5) { | |
2186 | memset(rtlpriv->sec.key_buf[idx], 0, | |
2187 | MAX_KEY_LEN); | |
2188 | rtlpriv->sec.key_len[idx] = 0; | |
2189 | } | |
2190 | } | |
2191 | ||
2192 | } else { | |
2193 | switch (enc_algo) { | |
2194 | case WEP40_ENCRYPTION: | |
2195 | enc_algo = CAM_WEP40; | |
2196 | break; | |
2197 | case WEP104_ENCRYPTION: | |
2198 | enc_algo = CAM_WEP104; | |
2199 | break; | |
2200 | case TKIP_ENCRYPTION: | |
2201 | enc_algo = CAM_TKIP; | |
2202 | break; | |
2203 | case AESCCMP_ENCRYPTION: | |
2204 | enc_algo = CAM_AES; | |
2205 | break; | |
2206 | default: | |
f30d7507 JP |
2207 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
2208 | "switch case not processed\n"); | |
0c817338 LF |
2209 | enc_algo = CAM_TKIP; |
2210 | break; | |
2211 | } | |
2212 | ||
2213 | if (is_wepkey || rtlpriv->sec.use_defaultkey) { | |
2214 | macaddr = cam_const_addr[key_index]; | |
2215 | entry_id = key_index; | |
2216 | } else { | |
2217 | if (is_group) { | |
2218 | macaddr = cam_const_broad; | |
2219 | entry_id = key_index; | |
2220 | } else { | |
3a16b412 LF |
2221 | if (mac->opmode == NL80211_IFTYPE_AP || |
2222 | mac->opmode == NL80211_IFTYPE_MESH_POINT) { | |
f73b279c C |
2223 | entry_id = rtl_cam_get_free_entry(hw, |
2224 | p_macaddr); | |
2225 | if (entry_id >= TOTAL_CAM_ENTRY) { | |
2226 | RT_TRACE(rtlpriv, COMP_SEC, | |
f30d7507 JP |
2227 | DBG_EMERG, |
2228 | "Can not find free hw security cam entry\n"); | |
f73b279c C |
2229 | return; |
2230 | } | |
2231 | } else { | |
2232 | entry_id = CAM_PAIRWISE_KEY_POSITION; | |
2233 | } | |
2234 | ||
0c817338 | 2235 | key_index = PAIRWISE_KEYIDX; |
0c817338 LF |
2236 | is_pairwise = true; |
2237 | } | |
2238 | } | |
2239 | ||
2240 | if (rtlpriv->sec.key_len[key_index] == 0) { | |
2241 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
f30d7507 JP |
2242 | "delete one entry, entry_id is %d\n", |
2243 | entry_id); | |
3a16b412 LF |
2244 | if (mac->opmode == NL80211_IFTYPE_AP || |
2245 | mac->opmode == NL80211_IFTYPE_MESH_POINT) | |
f73b279c | 2246 | rtl_cam_del_entry(hw, p_macaddr); |
0c817338 LF |
2247 | rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); |
2248 | } else { | |
2249 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, | |
f30d7507 JP |
2250 | "The insert KEY length is %d\n", |
2251 | rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); | |
0c817338 | 2252 | RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, |
f30d7507 JP |
2253 | "The insert KEY is %x %x\n", |
2254 | rtlpriv->sec.key_buf[0][0], | |
2255 | rtlpriv->sec.key_buf[0][1]); | |
0c817338 LF |
2256 | |
2257 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
f30d7507 | 2258 | "add one entry\n"); |
0c817338 LF |
2259 | if (is_pairwise) { |
2260 | RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, | |
af08687b | 2261 | "Pairwise Key content", |
0c817338 LF |
2262 | rtlpriv->sec.pairwise_key, |
2263 | rtlpriv->sec. | |
2264 | key_len[PAIRWISE_KEYIDX]); | |
2265 | ||
2266 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
f30d7507 | 2267 | "set Pairwise key\n"); |
0c817338 LF |
2268 | |
2269 | rtl_cam_add_one_entry(hw, macaddr, key_index, | |
2270 | entry_id, enc_algo, | |
2271 | CAM_CONFIG_NO_USEDK, | |
2272 | rtlpriv->sec. | |
2273 | key_buf[key_index]); | |
2274 | } else { | |
2275 | RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, | |
f30d7507 | 2276 | "set group key\n"); |
0c817338 LF |
2277 | |
2278 | if (mac->opmode == NL80211_IFTYPE_ADHOC) { | |
2279 | rtl_cam_add_one_entry(hw, | |
2280 | rtlefuse->dev_addr, | |
2281 | PAIRWISE_KEYIDX, | |
2282 | CAM_PAIRWISE_KEY_POSITION, | |
2283 | enc_algo, | |
2284 | CAM_CONFIG_NO_USEDK, | |
2285 | rtlpriv->sec.key_buf | |
2286 | [entry_id]); | |
2287 | } | |
2288 | ||
2289 | rtl_cam_add_one_entry(hw, macaddr, key_index, | |
2290 | entry_id, enc_algo, | |
2291 | CAM_CONFIG_NO_USEDK, | |
2292 | rtlpriv->sec.key_buf[entry_id]); | |
2293 | } | |
2294 | ||
2295 | } | |
2296 | } | |
2297 | } | |
f73b279c | 2298 | |
d3bb1429 | 2299 | static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw) |
f73b279c C |
2300 | { |
2301 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); | |
2302 | ||
2303 | rtlpcipriv->bt_coexist.bt_coexistence = | |
2304 | rtlpcipriv->bt_coexist.eeprom_bt_coexist; | |
2305 | rtlpcipriv->bt_coexist.bt_ant_num = | |
2306 | rtlpcipriv->bt_coexist.eeprom_bt_ant_num; | |
2307 | rtlpcipriv->bt_coexist.bt_coexist_type = | |
2308 | rtlpcipriv->bt_coexist.eeprom_bt_type; | |
2309 | ||
2310 | if (rtlpcipriv->bt_coexist.reg_bt_iso == 2) | |
2311 | rtlpcipriv->bt_coexist.bt_ant_isolation = | |
da17fcff | 2312 | rtlpcipriv->bt_coexist.eeprom_bt_ant_isol; |
f73b279c C |
2313 | else |
2314 | rtlpcipriv->bt_coexist.bt_ant_isolation = | |
2315 | rtlpcipriv->bt_coexist.reg_bt_iso; | |
2316 | ||
2317 | rtlpcipriv->bt_coexist.bt_radio_shared_type = | |
2318 | rtlpcipriv->bt_coexist.eeprom_bt_radio_shared; | |
2319 | ||
2320 | if (rtlpcipriv->bt_coexist.bt_coexistence) { | |
2321 | ||
2322 | if (rtlpcipriv->bt_coexist.reg_bt_sco == 1) | |
2323 | rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION; | |
2324 | else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2) | |
2325 | rtlpcipriv->bt_coexist.bt_service = BT_SCO; | |
2326 | else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4) | |
2327 | rtlpcipriv->bt_coexist.bt_service = BT_BUSY; | |
2328 | else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5) | |
2329 | rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY; | |
2330 | else | |
2331 | rtlpcipriv->bt_coexist.bt_service = BT_IDLE; | |
2332 | ||
2333 | rtlpcipriv->bt_coexist.bt_edca_ul = 0; | |
2334 | rtlpcipriv->bt_coexist.bt_edca_dl = 0; | |
2335 | rtlpcipriv->bt_coexist.bt_rssi_state = 0xff; | |
2336 | } | |
2337 | } | |
2338 | ||
2339 | void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw, | |
2340 | bool auto_load_fail, u8 *hwinfo) | |
2341 | { | |
2342 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); | |
da17fcff | 2343 | u8 val; |
f73b279c C |
2344 | |
2345 | if (!auto_load_fail) { | |
2346 | rtlpcipriv->bt_coexist.eeprom_bt_coexist = | |
2347 | ((hwinfo[RF_OPTION1] & 0xe0) >> 5); | |
da17fcff LF |
2348 | val = hwinfo[RF_OPTION4]; |
2349 | rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1); | |
2350 | rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1); | |
2351 | rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4); | |
f73b279c | 2352 | rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = |
da17fcff | 2353 | ((val & 0x20) >> 5); |
f73b279c C |
2354 | } else { |
2355 | rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0; | |
2356 | rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE; | |
2357 | rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2; | |
da17fcff | 2358 | rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0; |
f73b279c C |
2359 | rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED; |
2360 | } | |
2361 | ||
2362 | rtl8192ce_bt_var_init(hw); | |
2363 | } | |
2364 | ||
2365 | void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw) | |
2366 | { | |
2367 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); | |
2368 | ||
2369 | /* 0:Low, 1:High, 2:From Efuse. */ | |
2370 | rtlpcipriv->bt_coexist.reg_bt_iso = 2; | |
2371 | /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */ | |
2372 | rtlpcipriv->bt_coexist.reg_bt_sco = 3; | |
2373 | /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ | |
2374 | rtlpcipriv->bt_coexist.reg_bt_sco = 0; | |
2375 | } | |
2376 | ||
2377 | ||
2378 | void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw) | |
2379 | { | |
2380 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2381 | struct rtl_phy *rtlphy = &(rtlpriv->phy); | |
2382 | struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); | |
2383 | ||
2384 | u8 u1_tmp; | |
2385 | ||
2386 | if (rtlpcipriv->bt_coexist.bt_coexistence && | |
2387 | ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) || | |
2388 | rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) { | |
2389 | ||
2390 | if (rtlpcipriv->bt_coexist.bt_ant_isolation) | |
2391 | rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0); | |
2392 | ||
2393 | u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & | |
2394 | BIT_OFFSET_LEN_MASK_32(0, 1); | |
2395 | u1_tmp = u1_tmp | | |
2396 | ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ? | |
2397 | 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) | | |
2398 | ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ? | |
2399 | 0 : BIT_OFFSET_LEN_MASK_32(2, 1)); | |
2400 | rtl_write_byte(rtlpriv, 0x4fd, u1_tmp); | |
2401 | ||
2402 | rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); | |
2403 | rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040); | |
2404 | rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010); | |
2405 | ||
2406 | /* Config to 1T1R. */ | |
2407 | if (rtlphy->rf_type == RF_1T1R) { | |
2408 | u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE); | |
2409 | u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); | |
2410 | rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp); | |
2411 | ||
2412 | u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE); | |
2413 | u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1)); | |
2414 | rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp); | |
2415 | } | |
2416 | } | |
2417 | } | |
2418 | ||
2419 | void rtl92ce_suspend(struct ieee80211_hw *hw) | |
2420 | { | |
2421 | } | |
2422 | ||
2423 | void rtl92ce_resume(struct ieee80211_hw *hw) | |
2424 | { | |
2425 | } | |
3a16b412 LF |
2426 | |
2427 | /* Turn on AAP (RCR:bit 0) for promicuous mode. */ | |
2428 | void rtl92ce_allow_all_destaddr(struct ieee80211_hw *hw, | |
2429 | bool allow_all_da, bool write_into_reg) | |
2430 | { | |
2431 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2432 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
2433 | ||
2434 | if (allow_all_da) {/* Set BIT0 */ | |
2435 | rtlpci->receive_config |= RCR_AAP; | |
2436 | } else {/* Clear BIT0 */ | |
2437 | rtlpci->receive_config &= ~RCR_AAP; | |
2438 | } | |
2439 | ||
2440 | if (write_into_reg) | |
2441 | rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); | |
2442 | ||
2443 | RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, | |
2444 | "receive_config=0x%08X, write_into_reg=%d\n", | |
2445 | rtlpci->receive_config, write_into_reg); | |
2446 | } |