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f6532111 MW |
1 | |
2 | /* | |
3 | * Linux device driver for RTL8180 / RTL8185 | |
4 | * | |
5 | * Copyright 2007 Michael Wu <flamingice@sourmilk.net> | |
6 | * Copyright 2007 Andrea Merello <andreamrl@tiscali.it> | |
7 | * | |
8 | * Based on the r8180 driver, which is: | |
9 | * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. | |
10 | * | |
11 | * Thanks to Realtek for their support! | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/pci.h> | |
5a0e3ad6 | 20 | #include <linux/slab.h> |
f6532111 MW |
21 | #include <linux/delay.h> |
22 | #include <linux/etherdevice.h> | |
23 | #include <linux/eeprom_93cx6.h> | |
24 | #include <net/mac80211.h> | |
25 | ||
26 | #include "rtl8180.h" | |
27 | #include "rtl8180_rtl8225.h" | |
28 | #include "rtl8180_sa2400.h" | |
29 | #include "rtl8180_max2820.h" | |
30 | #include "rtl8180_grf5101.h" | |
31 | ||
32 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
33 | MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); | |
34 | MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver"); | |
35 | MODULE_LICENSE("GPL"); | |
36 | ||
a3aa1884 | 37 | static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = { |
f6532111 MW |
38 | /* rtl8185 */ |
39 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) }, | |
4fcc5470 | 40 | { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) }, |
f6532111 MW |
41 | { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) }, |
42 | ||
43 | /* rtl8180 */ | |
44 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) }, | |
45 | { PCI_DEVICE(0x1799, 0x6001) }, | |
46 | { PCI_DEVICE(0x1799, 0x6020) }, | |
47 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) }, | |
48 | { } | |
49 | }; | |
50 | ||
51 | MODULE_DEVICE_TABLE(pci, rtl8180_table); | |
52 | ||
8318d78a JB |
53 | static const struct ieee80211_rate rtl818x_rates[] = { |
54 | { .bitrate = 10, .hw_value = 0, }, | |
55 | { .bitrate = 20, .hw_value = 1, }, | |
56 | { .bitrate = 55, .hw_value = 2, }, | |
57 | { .bitrate = 110, .hw_value = 3, }, | |
58 | { .bitrate = 60, .hw_value = 4, }, | |
59 | { .bitrate = 90, .hw_value = 5, }, | |
60 | { .bitrate = 120, .hw_value = 6, }, | |
61 | { .bitrate = 180, .hw_value = 7, }, | |
62 | { .bitrate = 240, .hw_value = 8, }, | |
63 | { .bitrate = 360, .hw_value = 9, }, | |
64 | { .bitrate = 480, .hw_value = 10, }, | |
65 | { .bitrate = 540, .hw_value = 11, }, | |
66 | }; | |
67 | ||
68 | static const struct ieee80211_channel rtl818x_channels[] = { | |
69 | { .center_freq = 2412 }, | |
70 | { .center_freq = 2417 }, | |
71 | { .center_freq = 2422 }, | |
72 | { .center_freq = 2427 }, | |
73 | { .center_freq = 2432 }, | |
74 | { .center_freq = 2437 }, | |
75 | { .center_freq = 2442 }, | |
76 | { .center_freq = 2447 }, | |
77 | { .center_freq = 2452 }, | |
78 | { .center_freq = 2457 }, | |
79 | { .center_freq = 2462 }, | |
80 | { .center_freq = 2467 }, | |
81 | { .center_freq = 2472 }, | |
82 | { .center_freq = 2484 }, | |
83 | }; | |
84 | ||
85 | ||
f6532111 MW |
86 | void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data) |
87 | { | |
88 | struct rtl8180_priv *priv = dev->priv; | |
89 | int i = 10; | |
90 | u32 buf; | |
91 | ||
92 | buf = (data << 8) | addr; | |
93 | ||
94 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80); | |
95 | while (i--) { | |
96 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf); | |
97 | if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF)) | |
98 | return; | |
99 | } | |
100 | } | |
101 | ||
102 | static void rtl8180_handle_rx(struct ieee80211_hw *dev) | |
103 | { | |
104 | struct rtl8180_priv *priv = dev->priv; | |
105 | unsigned int count = 32; | |
106 | ||
107 | while (count--) { | |
108 | struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx]; | |
109 | struct sk_buff *skb = priv->rx_buf[priv->rx_idx]; | |
110 | u32 flags = le32_to_cpu(entry->flags); | |
111 | ||
38e3b0d8 | 112 | if (flags & RTL818X_RX_DESC_FLAG_OWN) |
f6532111 MW |
113 | return; |
114 | ||
38e3b0d8 HRK |
115 | if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL | |
116 | RTL818X_RX_DESC_FLAG_FOF | | |
117 | RTL818X_RX_DESC_FLAG_RX_ERR))) | |
f6532111 MW |
118 | goto done; |
119 | else { | |
120 | u32 flags2 = le32_to_cpu(entry->flags2); | |
121 | struct ieee80211_rx_status rx_status = {0}; | |
122 | struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE); | |
123 | ||
124 | if (unlikely(!new_skb)) | |
125 | goto done; | |
126 | ||
127 | pci_unmap_single(priv->pdev, | |
128 | *((dma_addr_t *)skb->cb), | |
129 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
130 | skb_put(skb, flags & 0xFFF); | |
131 | ||
132 | rx_status.antenna = (flags2 >> 15) & 1; | |
133 | /* TODO: improve signal/rssi reporting */ | |
566bfe5a | 134 | rx_status.signal = (flags2 >> 8) & 0x7F; |
8318d78a JB |
135 | /* XXX: is this correct? */ |
136 | rx_status.rate_idx = (flags >> 20) & 0xF; | |
137 | rx_status.freq = dev->conf.channel->center_freq; | |
138 | rx_status.band = dev->conf.channel->band; | |
f6532111 MW |
139 | rx_status.mactime = le64_to_cpu(entry->tsft); |
140 | rx_status.flag |= RX_FLAG_TSFT; | |
38e3b0d8 | 141 | if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR) |
f6532111 MW |
142 | rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; |
143 | ||
f1d58c25 JB |
144 | memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status)); |
145 | ieee80211_rx_irqsafe(dev, skb); | |
f6532111 MW |
146 | |
147 | skb = new_skb; | |
148 | priv->rx_buf[priv->rx_idx] = skb; | |
149 | *((dma_addr_t *) skb->cb) = | |
150 | pci_map_single(priv->pdev, skb_tail_pointer(skb), | |
151 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
152 | } | |
153 | ||
154 | done: | |
155 | entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb)); | |
38e3b0d8 | 156 | entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | |
f6532111 MW |
157 | MAX_RX_SIZE); |
158 | if (priv->rx_idx == 31) | |
38e3b0d8 | 159 | entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); |
f6532111 MW |
160 | priv->rx_idx = (priv->rx_idx + 1) % 32; |
161 | } | |
162 | } | |
163 | ||
164 | static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio) | |
165 | { | |
166 | struct rtl8180_priv *priv = dev->priv; | |
167 | struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; | |
168 | ||
169 | while (skb_queue_len(&ring->queue)) { | |
170 | struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; | |
171 | struct sk_buff *skb; | |
e039fa4a | 172 | struct ieee80211_tx_info *info; |
f6532111 MW |
173 | u32 flags = le32_to_cpu(entry->flags); |
174 | ||
38e3b0d8 | 175 | if (flags & RTL818X_TX_DESC_FLAG_OWN) |
f6532111 MW |
176 | return; |
177 | ||
178 | ring->idx = (ring->idx + 1) % ring->entries; | |
179 | skb = __skb_dequeue(&ring->queue); | |
180 | pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), | |
181 | skb->len, PCI_DMA_TODEVICE); | |
182 | ||
e039fa4a | 183 | info = IEEE80211_SKB_CB(skb); |
e6a9854b | 184 | ieee80211_tx_info_clear_status(info); |
f6532111 | 185 | |
e6a9854b JB |
186 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && |
187 | (flags & RTL818X_TX_DESC_FLAG_TX_OK)) | |
188 | info->flags |= IEEE80211_TX_STAT_ACK; | |
189 | ||
190 | info->status.rates[0].count = (flags & 0xFF) + 1; | |
f6532111 | 191 | |
e039fa4a | 192 | ieee80211_tx_status_irqsafe(dev, skb); |
f6532111 MW |
193 | if (ring->entries - skb_queue_len(&ring->queue) == 2) |
194 | ieee80211_wake_queue(dev, prio); | |
195 | } | |
196 | } | |
197 | ||
198 | static irqreturn_t rtl8180_interrupt(int irq, void *dev_id) | |
199 | { | |
200 | struct ieee80211_hw *dev = dev_id; | |
201 | struct rtl8180_priv *priv = dev->priv; | |
202 | u16 reg; | |
203 | ||
204 | spin_lock(&priv->lock); | |
205 | reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS); | |
206 | if (unlikely(reg == 0xFFFF)) { | |
207 | spin_unlock(&priv->lock); | |
208 | return IRQ_HANDLED; | |
209 | } | |
210 | ||
211 | rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg); | |
212 | ||
213 | if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR)) | |
214 | rtl8180_handle_tx(dev, 3); | |
215 | ||
216 | if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR)) | |
217 | rtl8180_handle_tx(dev, 2); | |
218 | ||
219 | if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR)) | |
220 | rtl8180_handle_tx(dev, 1); | |
221 | ||
222 | if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR)) | |
223 | rtl8180_handle_tx(dev, 0); | |
224 | ||
225 | if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR)) | |
226 | rtl8180_handle_rx(dev); | |
227 | ||
228 | spin_unlock(&priv->lock); | |
229 | ||
230 | return IRQ_HANDLED; | |
231 | } | |
232 | ||
e039fa4a | 233 | static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb) |
f6532111 | 234 | { |
e039fa4a | 235 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
f6532111 MW |
236 | struct rtl8180_priv *priv = dev->priv; |
237 | struct rtl8180_tx_ring *ring; | |
238 | struct rtl8180_tx_desc *entry; | |
239 | unsigned long flags; | |
240 | unsigned int idx, prio; | |
241 | dma_addr_t mapping; | |
242 | u32 tx_flags; | |
e6a9854b | 243 | u8 rc_flags; |
f6532111 MW |
244 | u16 plcp_len = 0; |
245 | __le16 rts_duration = 0; | |
246 | ||
e2530083 | 247 | prio = skb_get_queue_mapping(skb); |
f6532111 MW |
248 | ring = &priv->tx_ring[prio]; |
249 | ||
250 | mapping = pci_map_single(priv->pdev, skb->data, | |
251 | skb->len, PCI_DMA_TODEVICE); | |
252 | ||
38e3b0d8 HRK |
253 | tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS | |
254 | RTL818X_TX_DESC_FLAG_LS | | |
e039fa4a | 255 | (ieee80211_get_tx_rate(dev, info)->hw_value << 24) | |
2e92e6f2 | 256 | skb->len; |
f6532111 MW |
257 | |
258 | if (priv->r8185) | |
38e3b0d8 HRK |
259 | tx_flags |= RTL818X_TX_DESC_FLAG_DMA | |
260 | RTL818X_TX_DESC_FLAG_NO_ENC; | |
f6532111 | 261 | |
e6a9854b JB |
262 | rc_flags = info->control.rates[0].flags; |
263 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
38e3b0d8 | 264 | tx_flags |= RTL818X_TX_DESC_FLAG_RTS; |
e039fa4a | 265 | tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
e6a9854b | 266 | } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
38e3b0d8 | 267 | tx_flags |= RTL818X_TX_DESC_FLAG_CTS; |
e039fa4a | 268 | tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
aa68cbfb | 269 | } |
f6532111 | 270 | |
e6a9854b | 271 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) |
32bfd35d | 272 | rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len, |
e039fa4a | 273 | info); |
f6532111 MW |
274 | |
275 | if (!priv->r8185) { | |
276 | unsigned int remainder; | |
277 | ||
278 | plcp_len = DIV_ROUND_UP(16 * (skb->len + 4), | |
e039fa4a | 279 | (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); |
f6532111 | 280 | remainder = (16 * (skb->len + 4)) % |
e039fa4a | 281 | ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); |
35a0ace7 | 282 | if (remainder <= 6) |
f6532111 MW |
283 | plcp_len |= 1 << 15; |
284 | } | |
285 | ||
286 | spin_lock_irqsave(&priv->lock, flags); | |
287 | idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; | |
288 | entry = &ring->desc[idx]; | |
289 | ||
290 | entry->rts_duration = rts_duration; | |
291 | entry->plcp_len = cpu_to_le16(plcp_len); | |
292 | entry->tx_buf = cpu_to_le32(mapping); | |
293 | entry->frame_len = cpu_to_le32(skb->len); | |
e6a9854b | 294 | entry->flags2 = info->control.rates[1].idx >= 0 ? |
870abdf6 | 295 | ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0; |
e6a9854b | 296 | entry->retry_limit = info->control.rates[0].count; |
f6532111 MW |
297 | entry->flags = cpu_to_le32(tx_flags); |
298 | __skb_queue_tail(&ring->queue, skb); | |
299 | if (ring->entries - skb_queue_len(&ring->queue) < 2) | |
e2530083 | 300 | ieee80211_stop_queue(dev, skb_get_queue_mapping(skb)); |
f6532111 MW |
301 | spin_unlock_irqrestore(&priv->lock, flags); |
302 | ||
303 | rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4))); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
308 | void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam) | |
309 | { | |
310 | u8 reg; | |
311 | ||
312 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
313 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
314 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, | |
315 | reg | RTL818X_CONFIG3_ANAPARAM_WRITE); | |
316 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam); | |
317 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, | |
318 | reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); | |
319 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
320 | } | |
321 | ||
322 | static int rtl8180_init_hw(struct ieee80211_hw *dev) | |
323 | { | |
324 | struct rtl8180_priv *priv = dev->priv; | |
325 | u16 reg; | |
326 | ||
327 | rtl818x_iowrite8(priv, &priv->map->CMD, 0); | |
328 | rtl818x_ioread8(priv, &priv->map->CMD); | |
329 | msleep(10); | |
330 | ||
331 | /* reset */ | |
332 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); | |
333 | rtl818x_ioread8(priv, &priv->map->CMD); | |
334 | ||
335 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
336 | reg &= (1 << 1); | |
337 | reg |= RTL818X_CMD_RESET; | |
338 | rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET); | |
339 | rtl818x_ioread8(priv, &priv->map->CMD); | |
340 | msleep(200); | |
341 | ||
342 | /* check success of reset */ | |
343 | if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) { | |
344 | printk(KERN_ERR "%s: reset timeout!\n", wiphy_name(dev->wiphy)); | |
345 | return -ETIMEDOUT; | |
346 | } | |
347 | ||
348 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD); | |
349 | rtl818x_ioread8(priv, &priv->map->CMD); | |
350 | msleep(200); | |
351 | ||
352 | if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) { | |
353 | /* For cardbus */ | |
354 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
355 | reg |= 1 << 1; | |
356 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); | |
357 | reg = rtl818x_ioread16(priv, &priv->map->FEMR); | |
358 | reg |= (1 << 15) | (1 << 14) | (1 << 4); | |
359 | rtl818x_iowrite16(priv, &priv->map->FEMR, reg); | |
360 | } | |
361 | ||
362 | rtl818x_iowrite8(priv, &priv->map->MSR, 0); | |
363 | ||
364 | if (!priv->r8185) | |
365 | rtl8180_set_anaparam(priv, priv->anaparam); | |
366 | ||
367 | rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); | |
368 | rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); | |
369 | rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); | |
370 | rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); | |
371 | rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); | |
372 | ||
373 | /* TODO: necessary? specs indicate not */ | |
374 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
375 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); | |
376 | rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3)); | |
377 | if (priv->r8185) { | |
378 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); | |
379 | rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4)); | |
380 | } | |
381 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
382 | ||
383 | /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */ | |
384 | ||
385 | /* TODO: turn off hw wep on rtl8180 */ | |
386 | ||
387 | rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0); | |
388 | ||
389 | if (priv->r8185) { | |
390 | rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0); | |
391 | rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81); | |
392 | rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0); | |
393 | ||
394 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
395 | ||
396 | /* TODO: set ClkRun enable? necessary? */ | |
397 | reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE); | |
398 | rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6)); | |
399 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
400 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
401 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2)); | |
402 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
403 | } else { | |
404 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1); | |
405 | rtl818x_iowrite8(priv, &priv->map->SECURITY, 0); | |
406 | ||
407 | rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6); | |
408 | rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C); | |
409 | } | |
410 | ||
411 | priv->rf->init(dev); | |
412 | if (priv->r8185) | |
413 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static int rtl8180_init_rx_ring(struct ieee80211_hw *dev) | |
418 | { | |
419 | struct rtl8180_priv *priv = dev->priv; | |
420 | struct rtl8180_rx_desc *entry; | |
421 | int i; | |
422 | ||
423 | priv->rx_ring = pci_alloc_consistent(priv->pdev, | |
424 | sizeof(*priv->rx_ring) * 32, | |
425 | &priv->rx_ring_dma); | |
426 | ||
427 | if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) { | |
428 | printk(KERN_ERR "%s: Cannot allocate RX ring\n", | |
429 | wiphy_name(dev->wiphy)); | |
430 | return -ENOMEM; | |
431 | } | |
432 | ||
433 | memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32); | |
434 | priv->rx_idx = 0; | |
435 | ||
436 | for (i = 0; i < 32; i++) { | |
437 | struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE); | |
438 | dma_addr_t *mapping; | |
439 | entry = &priv->rx_ring[i]; | |
440 | if (!skb) | |
441 | return 0; | |
442 | ||
443 | priv->rx_buf[i] = skb; | |
444 | mapping = (dma_addr_t *)skb->cb; | |
445 | *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb), | |
446 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
447 | entry->rx_buf = cpu_to_le32(*mapping); | |
38e3b0d8 | 448 | entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | |
f6532111 MW |
449 | MAX_RX_SIZE); |
450 | } | |
38e3b0d8 | 451 | entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); |
f6532111 MW |
452 | return 0; |
453 | } | |
454 | ||
455 | static void rtl8180_free_rx_ring(struct ieee80211_hw *dev) | |
456 | { | |
457 | struct rtl8180_priv *priv = dev->priv; | |
458 | int i; | |
459 | ||
460 | for (i = 0; i < 32; i++) { | |
461 | struct sk_buff *skb = priv->rx_buf[i]; | |
462 | if (!skb) | |
463 | continue; | |
464 | ||
465 | pci_unmap_single(priv->pdev, | |
466 | *((dma_addr_t *)skb->cb), | |
467 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
468 | kfree_skb(skb); | |
469 | } | |
470 | ||
471 | pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32, | |
472 | priv->rx_ring, priv->rx_ring_dma); | |
473 | priv->rx_ring = NULL; | |
474 | } | |
475 | ||
476 | static int rtl8180_init_tx_ring(struct ieee80211_hw *dev, | |
477 | unsigned int prio, unsigned int entries) | |
478 | { | |
479 | struct rtl8180_priv *priv = dev->priv; | |
480 | struct rtl8180_tx_desc *ring; | |
481 | dma_addr_t dma; | |
482 | int i; | |
483 | ||
484 | ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma); | |
485 | if (!ring || (unsigned long)ring & 0xFF) { | |
486 | printk(KERN_ERR "%s: Cannot allocate TX ring (prio = %d)\n", | |
487 | wiphy_name(dev->wiphy), prio); | |
488 | return -ENOMEM; | |
489 | } | |
490 | ||
491 | memset(ring, 0, sizeof(*ring)*entries); | |
492 | priv->tx_ring[prio].desc = ring; | |
493 | priv->tx_ring[prio].dma = dma; | |
494 | priv->tx_ring[prio].idx = 0; | |
495 | priv->tx_ring[prio].entries = entries; | |
496 | skb_queue_head_init(&priv->tx_ring[prio].queue); | |
497 | ||
498 | for (i = 0; i < entries; i++) | |
499 | ring[i].next_tx_desc = | |
500 | cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring)); | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
505 | static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio) | |
506 | { | |
507 | struct rtl8180_priv *priv = dev->priv; | |
508 | struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; | |
509 | ||
510 | while (skb_queue_len(&ring->queue)) { | |
511 | struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; | |
512 | struct sk_buff *skb = __skb_dequeue(&ring->queue); | |
513 | ||
514 | pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), | |
515 | skb->len, PCI_DMA_TODEVICE); | |
f6532111 MW |
516 | kfree_skb(skb); |
517 | ring->idx = (ring->idx + 1) % ring->entries; | |
518 | } | |
519 | ||
520 | pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries, | |
521 | ring->desc, ring->dma); | |
522 | ring->desc = NULL; | |
523 | } | |
524 | ||
525 | static int rtl8180_start(struct ieee80211_hw *dev) | |
526 | { | |
527 | struct rtl8180_priv *priv = dev->priv; | |
528 | int ret, i; | |
529 | u32 reg; | |
530 | ||
531 | ret = rtl8180_init_rx_ring(dev); | |
532 | if (ret) | |
533 | return ret; | |
534 | ||
535 | for (i = 0; i < 4; i++) | |
536 | if ((ret = rtl8180_init_tx_ring(dev, i, 16))) | |
537 | goto err_free_rings; | |
538 | ||
539 | ret = rtl8180_init_hw(dev); | |
540 | if (ret) | |
541 | goto err_free_rings; | |
542 | ||
543 | rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); | |
544 | rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); | |
545 | rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); | |
546 | rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); | |
547 | rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); | |
548 | ||
ea31ba35 | 549 | ret = request_irq(priv->pdev->irq, rtl8180_interrupt, |
f6532111 MW |
550 | IRQF_SHARED, KBUILD_MODNAME, dev); |
551 | if (ret) { | |
552 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
553 | wiphy_name(dev->wiphy)); | |
554 | goto err_free_rings; | |
555 | } | |
556 | ||
557 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); | |
558 | ||
559 | rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); | |
560 | rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0); | |
561 | ||
562 | reg = RTL818X_RX_CONF_ONLYERLPKT | | |
563 | RTL818X_RX_CONF_RX_AUTORESETPHY | | |
564 | RTL818X_RX_CONF_MGMT | | |
565 | RTL818X_RX_CONF_DATA | | |
566 | (7 << 8 /* MAX RX DMA */) | | |
567 | RTL818X_RX_CONF_BROADCAST | | |
568 | RTL818X_RX_CONF_NICMAC; | |
569 | ||
570 | if (priv->r8185) | |
571 | reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2; | |
572 | else { | |
573 | reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1) | |
574 | ? RTL818X_RX_CONF_CSDM1 : 0; | |
575 | reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2) | |
576 | ? RTL818X_RX_CONF_CSDM2 : 0; | |
577 | } | |
578 | ||
579 | priv->rx_conf = reg; | |
580 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); | |
581 | ||
582 | if (priv->r8185) { | |
583 | reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); | |
584 | reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT; | |
585 | reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; | |
586 | rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); | |
587 | ||
588 | reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); | |
589 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT; | |
590 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT; | |
591 | reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT; | |
592 | rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); | |
593 | ||
594 | /* disable early TX */ | |
595 | rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f); | |
596 | } | |
597 | ||
598 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
599 | reg |= (6 << 21 /* MAX TX DMA */) | | |
600 | RTL818X_TX_CONF_NO_ICV; | |
601 | ||
602 | if (priv->r8185) | |
603 | reg &= ~RTL818X_TX_CONF_PROBE_DTS; | |
604 | else | |
605 | reg &= ~RTL818X_TX_CONF_HW_SEQNUM; | |
606 | ||
607 | /* different meaning, same value on both rtl8185 and rtl8180 */ | |
608 | reg &= ~RTL818X_TX_CONF_SAT_HWPLCP; | |
609 | ||
610 | rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); | |
611 | ||
612 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
613 | reg |= RTL818X_CMD_RX_ENABLE; | |
614 | reg |= RTL818X_CMD_TX_ENABLE; | |
615 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
616 | ||
f6532111 MW |
617 | return 0; |
618 | ||
619 | err_free_rings: | |
620 | rtl8180_free_rx_ring(dev); | |
621 | for (i = 0; i < 4; i++) | |
622 | if (priv->tx_ring[i].desc) | |
623 | rtl8180_free_tx_ring(dev, i); | |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
628 | static void rtl8180_stop(struct ieee80211_hw *dev) | |
629 | { | |
630 | struct rtl8180_priv *priv = dev->priv; | |
631 | u8 reg; | |
632 | int i; | |
633 | ||
f6532111 MW |
634 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); |
635 | ||
636 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
637 | reg &= ~RTL818X_CMD_TX_ENABLE; | |
638 | reg &= ~RTL818X_CMD_RX_ENABLE; | |
639 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
640 | ||
641 | priv->rf->stop(dev); | |
642 | ||
643 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
644 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG4); | |
645 | rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF); | |
646 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
647 | ||
648 | free_irq(priv->pdev->irq, dev); | |
649 | ||
650 | rtl8180_free_rx_ring(dev); | |
651 | for (i = 0; i < 4; i++) | |
652 | rtl8180_free_tx_ring(dev, i); | |
653 | } | |
654 | ||
655 | static int rtl8180_add_interface(struct ieee80211_hw *dev, | |
1ed32e4f | 656 | struct ieee80211_vif *vif) |
f6532111 MW |
657 | { |
658 | struct rtl8180_priv *priv = dev->priv; | |
659 | ||
643aab67 JL |
660 | /* |
661 | * We only support one active interface at a time. | |
662 | */ | |
663 | if (priv->vif) | |
664 | return -EBUSY; | |
f6532111 | 665 | |
1ed32e4f | 666 | switch (vif->type) { |
05c914fe | 667 | case NL80211_IFTYPE_STATION: |
f6532111 MW |
668 | break; |
669 | default: | |
670 | return -EOPNOTSUPP; | |
671 | } | |
672 | ||
1ed32e4f | 673 | priv->vif = vif; |
32bfd35d | 674 | |
f6532111 MW |
675 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); |
676 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0], | |
1ed32e4f | 677 | le32_to_cpu(*(__le32 *)vif->addr)); |
f6532111 | 678 | rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4], |
1ed32e4f | 679 | le16_to_cpu(*(__le16 *)(vif->addr + 4))); |
f6532111 MW |
680 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
685 | static void rtl8180_remove_interface(struct ieee80211_hw *dev, | |
1ed32e4f | 686 | struct ieee80211_vif *vif) |
f6532111 MW |
687 | { |
688 | struct rtl8180_priv *priv = dev->priv; | |
32bfd35d | 689 | priv->vif = NULL; |
f6532111 MW |
690 | } |
691 | ||
e8975581 | 692 | static int rtl8180_config(struct ieee80211_hw *dev, u32 changed) |
f6532111 MW |
693 | { |
694 | struct rtl8180_priv *priv = dev->priv; | |
e8975581 | 695 | struct ieee80211_conf *conf = &dev->conf; |
f6532111 MW |
696 | |
697 | priv->rf->set_chan(dev, conf); | |
698 | ||
699 | return 0; | |
700 | } | |
701 | ||
da81dede JL |
702 | static void rtl8180_bss_info_changed(struct ieee80211_hw *dev, |
703 | struct ieee80211_vif *vif, | |
704 | struct ieee80211_bss_conf *info, | |
705 | u32 changed) | |
706 | { | |
707 | struct rtl8180_priv *priv = dev->priv; | |
2d0ddec5 JB |
708 | int i; |
709 | ||
710 | if (changed & BSS_CHANGED_BSSID) { | |
711 | for (i = 0; i < ETH_ALEN; i++) | |
712 | rtl818x_iowrite8(priv, &priv->map->BSSID[i], | |
713 | info->bssid[i]); | |
714 | ||
715 | if (is_valid_ether_addr(info->bssid)) | |
716 | rtl818x_iowrite8(priv, &priv->map->MSR, | |
717 | RTL818X_MSR_INFRA); | |
718 | else | |
719 | rtl818x_iowrite8(priv, &priv->map->MSR, | |
720 | RTL818X_MSR_NO_LINK); | |
721 | } | |
da81dede JL |
722 | |
723 | if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp) | |
724 | priv->rf->conf_erp(dev, info); | |
725 | } | |
726 | ||
3ac64bee JB |
727 | static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev, int mc_count, |
728 | struct dev_addr_list *mc_list) | |
729 | { | |
730 | return mc_count; | |
731 | } | |
732 | ||
f6532111 MW |
733 | static void rtl8180_configure_filter(struct ieee80211_hw *dev, |
734 | unsigned int changed_flags, | |
735 | unsigned int *total_flags, | |
3ac64bee | 736 | u64 multicast) |
f6532111 MW |
737 | { |
738 | struct rtl8180_priv *priv = dev->priv; | |
739 | ||
740 | if (changed_flags & FIF_FCSFAIL) | |
741 | priv->rx_conf ^= RTL818X_RX_CONF_FCS; | |
742 | if (changed_flags & FIF_CONTROL) | |
743 | priv->rx_conf ^= RTL818X_RX_CONF_CTRL; | |
744 | if (changed_flags & FIF_OTHER_BSS) | |
745 | priv->rx_conf ^= RTL818X_RX_CONF_MONITOR; | |
3ac64bee | 746 | if (*total_flags & FIF_ALLMULTI || multicast > 0) |
f6532111 MW |
747 | priv->rx_conf |= RTL818X_RX_CONF_MULTICAST; |
748 | else | |
749 | priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST; | |
750 | ||
751 | *total_flags = 0; | |
752 | ||
753 | if (priv->rx_conf & RTL818X_RX_CONF_FCS) | |
754 | *total_flags |= FIF_FCSFAIL; | |
755 | if (priv->rx_conf & RTL818X_RX_CONF_CTRL) | |
756 | *total_flags |= FIF_CONTROL; | |
757 | if (priv->rx_conf & RTL818X_RX_CONF_MONITOR) | |
758 | *total_flags |= FIF_OTHER_BSS; | |
759 | if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST) | |
760 | *total_flags |= FIF_ALLMULTI; | |
761 | ||
762 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf); | |
763 | } | |
764 | ||
d2bb8e02 JL |
765 | static u64 rtl8180_get_tsf(struct ieee80211_hw *dev) |
766 | { | |
767 | struct rtl8180_priv *priv = dev->priv; | |
768 | ||
769 | return rtl818x_ioread32(priv, &priv->map->TSFT[0]) | | |
770 | (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32; | |
771 | } | |
772 | ||
f6532111 MW |
773 | static const struct ieee80211_ops rtl8180_ops = { |
774 | .tx = rtl8180_tx, | |
775 | .start = rtl8180_start, | |
776 | .stop = rtl8180_stop, | |
777 | .add_interface = rtl8180_add_interface, | |
778 | .remove_interface = rtl8180_remove_interface, | |
779 | .config = rtl8180_config, | |
da81dede | 780 | .bss_info_changed = rtl8180_bss_info_changed, |
3ac64bee | 781 | .prepare_multicast = rtl8180_prepare_multicast, |
f6532111 | 782 | .configure_filter = rtl8180_configure_filter, |
d2bb8e02 | 783 | .get_tsf = rtl8180_get_tsf, |
f6532111 MW |
784 | }; |
785 | ||
786 | static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom) | |
787 | { | |
788 | struct ieee80211_hw *dev = eeprom->data; | |
789 | struct rtl8180_priv *priv = dev->priv; | |
790 | u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
791 | ||
792 | eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; | |
793 | eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; | |
794 | eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; | |
795 | eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; | |
796 | } | |
797 | ||
798 | static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom) | |
799 | { | |
800 | struct ieee80211_hw *dev = eeprom->data; | |
801 | struct rtl8180_priv *priv = dev->priv; | |
802 | u8 reg = 2 << 6; | |
803 | ||
804 | if (eeprom->reg_data_in) | |
805 | reg |= RTL818X_EEPROM_CMD_WRITE; | |
806 | if (eeprom->reg_data_out) | |
807 | reg |= RTL818X_EEPROM_CMD_READ; | |
808 | if (eeprom->reg_data_clock) | |
809 | reg |= RTL818X_EEPROM_CMD_CK; | |
810 | if (eeprom->reg_chip_select) | |
811 | reg |= RTL818X_EEPROM_CMD_CS; | |
812 | ||
813 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg); | |
814 | rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
815 | udelay(10); | |
816 | } | |
817 | ||
818 | static int __devinit rtl8180_probe(struct pci_dev *pdev, | |
819 | const struct pci_device_id *id) | |
820 | { | |
821 | struct ieee80211_hw *dev; | |
822 | struct rtl8180_priv *priv; | |
823 | unsigned long mem_addr, mem_len; | |
824 | unsigned int io_addr, io_len; | |
825 | int err, i; | |
826 | struct eeprom_93cx6 eeprom; | |
827 | const char *chip_name, *rf_name = NULL; | |
828 | u32 reg; | |
829 | u16 eeprom_val; | |
f6532111 MW |
830 | |
831 | err = pci_enable_device(pdev); | |
832 | if (err) { | |
833 | printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n", | |
834 | pci_name(pdev)); | |
835 | return err; | |
836 | } | |
837 | ||
838 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
839 | if (err) { | |
840 | printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n", | |
841 | pci_name(pdev)); | |
842 | return err; | |
843 | } | |
844 | ||
845 | io_addr = pci_resource_start(pdev, 0); | |
846 | io_len = pci_resource_len(pdev, 0); | |
847 | mem_addr = pci_resource_start(pdev, 1); | |
848 | mem_len = pci_resource_len(pdev, 1); | |
849 | ||
850 | if (mem_len < sizeof(struct rtl818x_csr) || | |
851 | io_len < sizeof(struct rtl818x_csr)) { | |
852 | printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n", | |
853 | pci_name(pdev)); | |
854 | err = -ENOMEM; | |
855 | goto err_free_reg; | |
856 | } | |
857 | ||
858 | if ((err = pci_set_dma_mask(pdev, 0xFFFFFF00ULL)) || | |
859 | (err = pci_set_consistent_dma_mask(pdev, 0xFFFFFF00ULL))) { | |
860 | printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n", | |
861 | pci_name(pdev)); | |
862 | goto err_free_reg; | |
863 | } | |
864 | ||
865 | pci_set_master(pdev); | |
866 | ||
867 | dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops); | |
868 | if (!dev) { | |
869 | printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n", | |
870 | pci_name(pdev)); | |
871 | err = -ENOMEM; | |
872 | goto err_free_reg; | |
873 | } | |
874 | ||
875 | priv = dev->priv; | |
876 | priv->pdev = pdev; | |
877 | ||
e6a9854b | 878 | dev->max_rates = 2; |
f6532111 MW |
879 | SET_IEEE80211_DEV(dev, &pdev->dev); |
880 | pci_set_drvdata(pdev, dev); | |
881 | ||
882 | priv->map = pci_iomap(pdev, 1, mem_len); | |
883 | if (!priv->map) | |
884 | priv->map = pci_iomap(pdev, 0, io_len); | |
885 | ||
886 | if (!priv->map) { | |
887 | printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n", | |
888 | pci_name(pdev)); | |
889 | goto err_free_dev; | |
890 | } | |
891 | ||
8318d78a JB |
892 | BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels)); |
893 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates)); | |
894 | ||
f6532111 MW |
895 | memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels)); |
896 | memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates)); | |
8318d78a JB |
897 | |
898 | priv->band.band = IEEE80211_BAND_2GHZ; | |
899 | priv->band.channels = priv->channels; | |
900 | priv->band.n_channels = ARRAY_SIZE(rtl818x_channels); | |
901 | priv->band.bitrates = priv->rates; | |
902 | priv->band.n_bitrates = 4; | |
903 | dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
904 | ||
f6532111 | 905 | dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
566bfe5a BR |
906 | IEEE80211_HW_RX_INCLUDES_FCS | |
907 | IEEE80211_HW_SIGNAL_UNSPEC; | |
b55eae33 | 908 | dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); |
f6532111 | 909 | dev->queues = 1; |
566bfe5a | 910 | dev->max_signal = 65; |
f6532111 MW |
911 | |
912 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
913 | reg &= RTL818X_TX_CONF_HWVER_MASK; | |
914 | switch (reg) { | |
915 | case RTL818X_TX_CONF_R8180_ABCD: | |
916 | chip_name = "RTL8180"; | |
917 | break; | |
918 | case RTL818X_TX_CONF_R8180_F: | |
919 | chip_name = "RTL8180vF"; | |
920 | break; | |
921 | case RTL818X_TX_CONF_R8185_ABC: | |
922 | chip_name = "RTL8185"; | |
923 | break; | |
924 | case RTL818X_TX_CONF_R8185_D: | |
925 | chip_name = "RTL8185vD"; | |
926 | break; | |
927 | default: | |
928 | printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n", | |
929 | pci_name(pdev), reg >> 25); | |
930 | goto err_iounmap; | |
931 | } | |
932 | ||
933 | priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC; | |
934 | if (priv->r8185) { | |
8318d78a | 935 | priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates); |
f6532111 MW |
936 | pci_try_set_mwi(pdev); |
937 | } | |
938 | ||
f6532111 MW |
939 | eeprom.data = dev; |
940 | eeprom.register_read = rtl8180_eeprom_register_read; | |
941 | eeprom.register_write = rtl8180_eeprom_register_write; | |
942 | if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6)) | |
943 | eeprom.width = PCI_EEPROM_WIDTH_93C66; | |
944 | else | |
945 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
946 | ||
947 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM); | |
948 | rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
949 | udelay(10); | |
950 | ||
951 | eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val); | |
952 | eeprom_val &= 0xFF; | |
953 | switch (eeprom_val) { | |
954 | case 1: rf_name = "Intersil"; | |
955 | break; | |
956 | case 2: rf_name = "RFMD"; | |
957 | break; | |
958 | case 3: priv->rf = &sa2400_rf_ops; | |
959 | break; | |
960 | case 4: priv->rf = &max2820_rf_ops; | |
961 | break; | |
962 | case 5: priv->rf = &grf5101_rf_ops; | |
963 | break; | |
964 | case 9: priv->rf = rtl8180_detect_rf(dev); | |
965 | break; | |
966 | case 10: | |
967 | rf_name = "RTL8255"; | |
968 | break; | |
969 | default: | |
970 | printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n", | |
971 | pci_name(pdev), eeprom_val); | |
972 | goto err_iounmap; | |
973 | } | |
974 | ||
975 | if (!priv->rf) { | |
976 | printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n", | |
977 | pci_name(pdev), rf_name); | |
978 | goto err_iounmap; | |
979 | } | |
980 | ||
981 | eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val); | |
982 | priv->csthreshold = eeprom_val >> 8; | |
983 | if (!priv->r8185) { | |
984 | __le32 anaparam; | |
985 | eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2); | |
986 | priv->anaparam = le32_to_cpu(anaparam); | |
987 | eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam); | |
988 | } | |
989 | ||
990 | eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)dev->wiphy->perm_addr, 3); | |
991 | if (!is_valid_ether_addr(dev->wiphy->perm_addr)) { | |
992 | printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using" | |
993 | " randomly generated MAC addr\n", pci_name(pdev)); | |
994 | random_ether_addr(dev->wiphy->perm_addr); | |
995 | } | |
996 | ||
997 | /* CCK TX power */ | |
998 | for (i = 0; i < 14; i += 2) { | |
999 | u16 txpwr; | |
1000 | eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr); | |
8318d78a JB |
1001 | priv->channels[i].hw_value = txpwr & 0xFF; |
1002 | priv->channels[i + 1].hw_value = txpwr >> 8; | |
f6532111 MW |
1003 | } |
1004 | ||
1005 | /* OFDM TX power */ | |
1006 | if (priv->r8185) { | |
1007 | for (i = 0; i < 14; i += 2) { | |
1008 | u16 txpwr; | |
1009 | eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr); | |
8318d78a JB |
1010 | priv->channels[i].hw_value |= (txpwr & 0xFF) << 8; |
1011 | priv->channels[i + 1].hw_value |= txpwr & 0xFF00; | |
f6532111 MW |
1012 | } |
1013 | } | |
1014 | ||
1015 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
1016 | ||
1017 | spin_lock_init(&priv->lock); | |
1018 | ||
1019 | err = ieee80211_register_hw(dev); | |
1020 | if (err) { | |
1021 | printk(KERN_ERR "%s (rtl8180): Cannot register device\n", | |
1022 | pci_name(pdev)); | |
1023 | goto err_iounmap; | |
1024 | } | |
1025 | ||
e174961c JB |
1026 | printk(KERN_INFO "%s: hwaddr %pM, %s + %s\n", |
1027 | wiphy_name(dev->wiphy), dev->wiphy->perm_addr, | |
f6532111 MW |
1028 | chip_name, priv->rf->name); |
1029 | ||
1030 | return 0; | |
1031 | ||
1032 | err_iounmap: | |
1033 | iounmap(priv->map); | |
1034 | ||
1035 | err_free_dev: | |
1036 | pci_set_drvdata(pdev, NULL); | |
1037 | ieee80211_free_hw(dev); | |
1038 | ||
1039 | err_free_reg: | |
1040 | pci_release_regions(pdev); | |
1041 | pci_disable_device(pdev); | |
1042 | return err; | |
1043 | } | |
1044 | ||
1045 | static void __devexit rtl8180_remove(struct pci_dev *pdev) | |
1046 | { | |
1047 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
1048 | struct rtl8180_priv *priv; | |
1049 | ||
1050 | if (!dev) | |
1051 | return; | |
1052 | ||
1053 | ieee80211_unregister_hw(dev); | |
1054 | ||
1055 | priv = dev->priv; | |
1056 | ||
1057 | pci_iounmap(pdev, priv->map); | |
1058 | pci_release_regions(pdev); | |
1059 | pci_disable_device(pdev); | |
1060 | ieee80211_free_hw(dev); | |
1061 | } | |
1062 | ||
1063 | #ifdef CONFIG_PM | |
1064 | static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state) | |
1065 | { | |
1066 | pci_save_state(pdev); | |
1067 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | static int rtl8180_resume(struct pci_dev *pdev) | |
1072 | { | |
1073 | pci_set_power_state(pdev, PCI_D0); | |
1074 | pci_restore_state(pdev); | |
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | #endif /* CONFIG_PM */ | |
1079 | ||
1080 | static struct pci_driver rtl8180_driver = { | |
1081 | .name = KBUILD_MODNAME, | |
1082 | .id_table = rtl8180_table, | |
1083 | .probe = rtl8180_probe, | |
1084 | .remove = __devexit_p(rtl8180_remove), | |
1085 | #ifdef CONFIG_PM | |
1086 | .suspend = rtl8180_suspend, | |
1087 | .resume = rtl8180_resume, | |
1088 | #endif /* CONFIG_PM */ | |
1089 | }; | |
1090 | ||
1091 | static int __init rtl8180_init(void) | |
1092 | { | |
1093 | return pci_register_driver(&rtl8180_driver); | |
1094 | } | |
1095 | ||
1096 | static void __exit rtl8180_exit(void) | |
1097 | { | |
1098 | pci_unregister_driver(&rtl8180_driver); | |
1099 | } | |
1100 | ||
1101 | module_init(rtl8180_init); | |
1102 | module_exit(rtl8180_exit); |