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net: remove interrupt.h inclusion from netdevice.h
[linux-2.6-block.git] / drivers / net / wireless / rtl818x / rtl8180 / dev.c
CommitLineData
f6532111
MW		 1
2/*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
a6b7a407 19#include <linux/interrupt.h>
f6532111 20#include <linux/pci.h>
5a0e3ad6 21#include <linux/slab.h>
f6532111
MW		 22#include <linux/delay.h>
23#include <linux/etherdevice.h>
24#include <linux/eeprom_93cx6.h>
25#include <net/mac80211.h>
26
27#include "rtl8180.h"
3cfeb0c3
JL		 28#include "rtl8225.h"
29#include "sa2400.h"
30#include "max2820.h"
31#include "grf5101.h"
f6532111
MW		 32
33MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
35MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36MODULE_LICENSE("GPL");
37
a3aa1884 38static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
f6532111
MW		 39 /* rtl8185 */
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
4fcc5470 41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
f6532111
MW		 42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
43
44 /* rtl8180 */
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
49 { }
50};
51
52MODULE_DEVICE_TABLE(pci, rtl8180_table);
53
8318d78a
JB		 54static const struct ieee80211_rate rtl818x_rates[] = {
55 { .bitrate = 10, .hw_value = 0, },
56 { .bitrate = 20, .hw_value = 1, },
57 { .bitrate = 55, .hw_value = 2, },
58 { .bitrate = 110, .hw_value = 3, },
59 { .bitrate = 60, .hw_value = 4, },
60 { .bitrate = 90, .hw_value = 5, },
61 { .bitrate = 120, .hw_value = 6, },
62 { .bitrate = 180, .hw_value = 7, },
63 { .bitrate = 240, .hw_value = 8, },
64 { .bitrate = 360, .hw_value = 9, },
65 { .bitrate = 480, .hw_value = 10, },
66 { .bitrate = 540, .hw_value = 11, },
67};
68
69static const struct ieee80211_channel rtl818x_channels[] = {
70 { .center_freq = 2412 },
71 { .center_freq = 2417 },
72 { .center_freq = 2422 },
73 { .center_freq = 2427 },
74 { .center_freq = 2432 },
75 { .center_freq = 2437 },
76 { .center_freq = 2442 },
77 { .center_freq = 2447 },
78 { .center_freq = 2452 },
79 { .center_freq = 2457 },
80 { .center_freq = 2462 },
81 { .center_freq = 2467 },
82 { .center_freq = 2472 },
83 { .center_freq = 2484 },
84};
85
86
f6532111
MW		 87void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
88{
89 struct rtl8180_priv *priv = dev->priv;
90 int i = 10;
91 u32 buf;
92
93 buf = (data << 8) | addr;
94
95 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
96 while (i--) {
97 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
98 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
99 return;
100 }
101}
102
a6d27d2a 103static void rtl8180_handle_rx(struct ieee80211_hw *dev)
f6532111
MW		 104{
105 struct rtl8180_priv *priv = dev->priv;
a6d27d2a 106 unsigned int count = 32;
8b73fb8e 107 u8 signal, agc, sq;
f6532111 108
a6d27d2a 109 while (count--) {
f6532111
MW		 110 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
111 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
112 u32 flags = le32_to_cpu(entry->flags);
113
38e3b0d8 114 if (flags & RTL818X_RX_DESC_FLAG_OWN)
a6d27d2a 115 return;
f6532111 116
38e3b0d8
HRK		 117 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
118 RTL818X_RX_DESC_FLAG_FOF |
119 RTL818X_RX_DESC_FLAG_RX_ERR)))
f6532111
MW		 120 goto done;
121 else {
122 u32 flags2 = le32_to_cpu(entry->flags2);
123 struct ieee80211_rx_status rx_status = {0};
124 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
125
126 if (unlikely(!new_skb))
127 goto done;
128
129 pci_unmap_single(priv->pdev,
130 *((dma_addr_t *)skb->cb),
131 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
132 skb_put(skb, flags & 0xFFF);
133
134 rx_status.antenna = (flags2 >> 15) & 1;
8318d78a 135 rx_status.rate_idx = (flags >> 20) & 0xF;
8b73fb8e
JL		 136 agc = (flags2 >> 17) & 0x7F;
137 if (priv->r8185) {
138 if (rx_status.rate_idx > 3)
139 signal = 90 - clamp_t(u8, agc, 25, 90);
140 else
141 signal = 95 - clamp_t(u8, agc, 30, 95);
142 } else {
143 sq = flags2 & 0xff;
144 signal = priv->rf->calc_rssi(agc, sq);
145 }
8b74964c 146 rx_status.signal = signal;
8318d78a
JB		 147 rx_status.freq = dev->conf.channel->center_freq;
148 rx_status.band = dev->conf.channel->band;
f6532111 149 rx_status.mactime = le64_to_cpu(entry->tsft);
6ebacbb7 150 rx_status.flag |= RX_FLAG_MACTIME_MPDU;
38e3b0d8 151 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
f6532111
MW		 152 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
153
f1d58c25 154 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
a6d27d2a 155 ieee80211_rx_irqsafe(dev, skb);
f6532111
MW		 156
157 skb = new_skb;
158 priv->rx_buf[priv->rx_idx] = skb;
159 *((dma_addr_t *) skb->cb) =
160 pci_map_single(priv->pdev, skb_tail_pointer(skb),
161 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
162 }
163
164 done:
165 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
38e3b0d8 166 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
f6532111
MW		 167 MAX_RX_SIZE);
168 if (priv->rx_idx == 31)
38e3b0d8 169 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
f6532111
MW		 170 priv->rx_idx = (priv->rx_idx + 1) % 32;
171 }
a6d27d2a
JL		 172}
173
174static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
175{
176 struct rtl8180_priv *priv = dev->priv;
177 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
e6a9854b 178
a6d27d2a
JL		 179 while (skb_queue_len(&ring->queue)) {
180 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
181 struct sk_buff *skb;
182 struct ieee80211_tx_info *info;
183 u32 flags = le32_to_cpu(entry->flags);
f6532111 184
a6d27d2a
JL		 185 if (flags & RTL818X_TX_DESC_FLAG_OWN)
186 return;
187
188 ring->idx = (ring->idx + 1) % ring->entries;
189 skb = __skb_dequeue(&ring->queue);
190 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
191 skb->len, PCI_DMA_TODEVICE);
192
193 info = IEEE80211_SKB_CB(skb);
194 ieee80211_tx_info_clear_status(info);
195
196 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
197 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
198 info->flags |= IEEE80211_TX_STAT_ACK;
199
200 info->status.rates[0].count = (flags & 0xFF) + 1;
201 info->status.rates[1].idx = -1;
030725d2 202
a6d27d2a
JL		 203 ieee80211_tx_status_irqsafe(dev, skb);
204 if (ring->entries - skb_queue_len(&ring->queue) == 2)
205 ieee80211_wake_queue(dev, prio);
206 }
f6532111
MW		 207}
208
209static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
210{
211 struct ieee80211_hw *dev = dev_id;
212 struct rtl8180_priv *priv = dev->priv;
213 u16 reg;
214
a6d27d2a 215 spin_lock(&priv->lock);
f6532111 216 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
a6d27d2a
JL		 217 if (unlikely(reg == 0xFFFF)) {
218 spin_unlock(&priv->lock);
f6532111 219 return IRQ_HANDLED;
a6d27d2a 220 }
f6532111
MW		 221
222 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
223
a6d27d2a
JL		 224 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
225 rtl8180_handle_tx(dev, 3);
226
227 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
228 rtl8180_handle_tx(dev, 2);
229
230 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
231 rtl8180_handle_tx(dev, 1);
f6532111 232
a6d27d2a
JL		 233 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
234 rtl8180_handle_tx(dev, 0);
235
236 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
237 rtl8180_handle_rx(dev);
238
239 spin_unlock(&priv->lock);
f6532111
MW		 240
241 return IRQ_HANDLED;
242}
243
7bb45683 244static void rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
f6532111 245{
e039fa4a 246 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
51e080de 247 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
f6532111
MW		 248 struct rtl8180_priv *priv = dev->priv;
249 struct rtl8180_tx_ring *ring;
250 struct rtl8180_tx_desc *entry;
a6d27d2a 251 unsigned long flags;
f6532111
MW		 252 unsigned int idx, prio;
253 dma_addr_t mapping;
254 u32 tx_flags;
e6a9854b 255 u8 rc_flags;
f6532111
MW		 256 u16 plcp_len = 0;
257 __le16 rts_duration = 0;
258
e2530083 259 prio = skb_get_queue_mapping(skb);
f6532111
MW		 260 ring = &priv->tx_ring[prio];
261
262 mapping = pci_map_single(priv->pdev, skb->data,
263 skb->len, PCI_DMA_TODEVICE);
264
38e3b0d8
HRK		 265 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
266 RTL818X_TX_DESC_FLAG_LS |
e039fa4a 267 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
2e92e6f2 268 skb->len;
f6532111
MW		 269
270 if (priv->r8185)
38e3b0d8
HRK		 271 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
272 RTL818X_TX_DESC_FLAG_NO_ENC;
f6532111 273
e6a9854b
JB		 274 rc_flags = info->control.rates[0].flags;
275 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 276 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 277 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
e6a9854b 278 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 279 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 280 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 281 }
f6532111 282
e6a9854b 283 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
32bfd35d 284 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
e039fa4a 285 info);
f6532111
MW		 286
287 if (!priv->r8185) {
288 unsigned int remainder;
289
290 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
e039fa4a 291 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
f6532111 292 remainder = (16 * (skb->len + 4)) %
e039fa4a 293 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
35a0ace7 294 if (remainder <= 6)
f6532111
MW		 295 plcp_len |= 1 << 15;
296 }
297
a6d27d2a 298 spin_lock_irqsave(&priv->lock, flags);
51e080de
JL		 299
300 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
301 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
302 priv->seqno += 0x10;
303 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
304 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
305 }
306
f6532111
MW		 307 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
308 entry = &ring->desc[idx];
309
310 entry->rts_duration = rts_duration;
311 entry->plcp_len = cpu_to_le16(plcp_len);
312 entry->tx_buf = cpu_to_le32(mapping);
313 entry->frame_len = cpu_to_le32(skb->len);
e6a9854b 314 entry->flags2 = info->control.rates[1].idx >= 0 ?
870abdf6 315 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
e6a9854b 316 entry->retry_limit = info->control.rates[0].count;
f6532111
MW		 317 entry->flags = cpu_to_le32(tx_flags);
318 __skb_queue_tail(&ring->queue, skb);
319 if (ring->entries - skb_queue_len(&ring->queue) < 2)
d10e2e02 320 ieee80211_stop_queue(dev, prio);
51e080de 321
a6d27d2a 322 spin_unlock_irqrestore(&priv->lock, flags);
f6532111
MW		 323
324 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
f6532111
MW		 325}
326
327void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
328{
329 u8 reg;
330
331 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
332 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
333 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
334 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
335 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
336 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
337 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
338 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
339}
340
341static int rtl8180_init_hw(struct ieee80211_hw *dev)
342{
343 struct rtl8180_priv *priv = dev->priv;
344 u16 reg;
345
346 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
347 rtl818x_ioread8(priv, &priv->map->CMD);
348 msleep(10);
349
350 /* reset */
351 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
352 rtl818x_ioread8(priv, &priv->map->CMD);
353
354 reg = rtl818x_ioread8(priv, &priv->map->CMD);
355 reg &= (1 << 1);
356 reg |= RTL818X_CMD_RESET;
357 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
358 rtl818x_ioread8(priv, &priv->map->CMD);
359 msleep(200);
360
361 /* check success of reset */
362 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
c96c31e4 363 wiphy_err(dev->wiphy, "reset timeout!\n");
f6532111
MW		 364 return -ETIMEDOUT;
365 }
366
367 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
368 rtl818x_ioread8(priv, &priv->map->CMD);
369 msleep(200);
370
371 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
372 /* For cardbus */
373 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
374 reg |= 1 << 1;
375 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
376 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
377 reg |= (1 << 15) | (1 << 14) | (1 << 4);
378 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
379 }
380
381 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
382
383 if (!priv->r8185)
384 rtl8180_set_anaparam(priv, priv->anaparam);
385
386 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
387 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
388 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
389 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
390 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
391
392 /* TODO: necessary? specs indicate not */
393 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
394 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
395 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
396 if (priv->r8185) {
397 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
398 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
399 }
400 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
401
402 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
403
404 /* TODO: turn off hw wep on rtl8180 */
405
406 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
407
408 if (priv->r8185) {
409 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
410 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
411 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
412
413 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
414
415 /* TODO: set ClkRun enable? necessary? */
416 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
417 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
418 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
419 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
420 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
421 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
422 } else {
423 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
424 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
425
426 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
427 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
428 }
429
430 priv->rf->init(dev);
431 if (priv->r8185)
432 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
433 return 0;
434}
435
436static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
437{
438 struct rtl8180_priv *priv = dev->priv;
439 struct rtl8180_rx_desc *entry;
440 int i;
441
442 priv->rx_ring = pci_alloc_consistent(priv->pdev,
443 sizeof(*priv->rx_ring) * 32,
444 &priv->rx_ring_dma);
445
446 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
5db55844 447 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
f6532111
MW		 448 return -ENOMEM;
449 }
450
451 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
452 priv->rx_idx = 0;
453
454 for (i = 0; i < 32; i++) {
455 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
456 dma_addr_t *mapping;
457 entry = &priv->rx_ring[i];
458 if (!skb)
459 return 0;
460
461 priv->rx_buf[i] = skb;
462 mapping = (dma_addr_t *)skb->cb;
463 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
464 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
465 entry->rx_buf = cpu_to_le32(*mapping);
38e3b0d8 466 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
f6532111
MW		 467 MAX_RX_SIZE);
468 }
38e3b0d8 469 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
f6532111
MW		 470 return 0;
471}
472
473static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
474{
475 struct rtl8180_priv *priv = dev->priv;
476 int i;
477
478 for (i = 0; i < 32; i++) {
479 struct sk_buff *skb = priv->rx_buf[i];
480 if (!skb)
481 continue;
482
483 pci_unmap_single(priv->pdev,
484 *((dma_addr_t *)skb->cb),
485 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
486 kfree_skb(skb);
487 }
488
489 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
490 priv->rx_ring, priv->rx_ring_dma);
491 priv->rx_ring = NULL;
492}
493
494static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
495 unsigned int prio, unsigned int entries)
496{
497 struct rtl8180_priv *priv = dev->priv;
498 struct rtl8180_tx_desc *ring;
499 dma_addr_t dma;
500 int i;
501
502 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
503 if (!ring || (unsigned long)ring & 0xFF) {
5db55844 504 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
c96c31e4 505 prio);
f6532111
MW		 506 return -ENOMEM;
507 }
508
509 memset(ring, 0, sizeof(*ring)*entries);
510 priv->tx_ring[prio].desc = ring;
511 priv->tx_ring[prio].dma = dma;
512 priv->tx_ring[prio].idx = 0;
513 priv->tx_ring[prio].entries = entries;
514 skb_queue_head_init(&priv->tx_ring[prio].queue);
515
516 for (i = 0; i < entries; i++)
517 ring[i].next_tx_desc =
518 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
519
520 return 0;
521}
522
523static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
524{
525 struct rtl8180_priv *priv = dev->priv;
526 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
527
528 while (skb_queue_len(&ring->queue)) {
529 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
530 struct sk_buff *skb = __skb_dequeue(&ring->queue);
531
532 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
533 skb->len, PCI_DMA_TODEVICE);
f6532111
MW		 534 kfree_skb(skb);
535 ring->idx = (ring->idx + 1) % ring->entries;
536 }
537
538 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
539 ring->desc, ring->dma);
540 ring->desc = NULL;
541}
542
543static int rtl8180_start(struct ieee80211_hw *dev)
544{
545 struct rtl8180_priv *priv = dev->priv;
546 int ret, i;
547 u32 reg;
548
549 ret = rtl8180_init_rx_ring(dev);
550 if (ret)
551 return ret;
552
553 for (i = 0; i < 4; i++)
554 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
555 goto err_free_rings;
556
557 ret = rtl8180_init_hw(dev);
558 if (ret)
559 goto err_free_rings;
560
561 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
562 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
563 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
564 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
565 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
566
ea31ba35 567 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
f6532111
MW		 568 IRQF_SHARED, KBUILD_MODNAME, dev);
569 if (ret) {
5db55844 570 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
f6532111
MW		 571 goto err_free_rings;
572 }
573
574 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
575
576 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
577 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
578
579 reg = RTL818X_RX_CONF_ONLYERLPKT |
580 RTL818X_RX_CONF_RX_AUTORESETPHY |
581 RTL818X_RX_CONF_MGMT |
582 RTL818X_RX_CONF_DATA |
583 (7 << 8 /* MAX RX DMA */) |
584 RTL818X_RX_CONF_BROADCAST |
585 RTL818X_RX_CONF_NICMAC;
586
587 if (priv->r8185)
588 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
589 else {
590 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
591 ? RTL818X_RX_CONF_CSDM1 : 0;
592 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
593 ? RTL818X_RX_CONF_CSDM2 : 0;
594 }
595
596 priv->rx_conf = reg;
597 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
598
599 if (priv->r8185) {
600 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
601 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
602 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
603 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
604
605 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
606 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
607 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
608 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
609 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
610
611 /* disable early TX */
612 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
613 }
614
615 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
616 reg |= (6 << 21 /* MAX TX DMA */) |
617 RTL818X_TX_CONF_NO_ICV;
618
619 if (priv->r8185)
620 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
621 else
622 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
623
624 /* different meaning, same value on both rtl8185 and rtl8180 */
625 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
626
627 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
628
629 reg = rtl818x_ioread8(priv, &priv->map->CMD);
630 reg |= RTL818X_CMD_RX_ENABLE;
631 reg |= RTL818X_CMD_TX_ENABLE;
632 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
633
f6532111
MW		 634 return 0;
635
636 err_free_rings:
637 rtl8180_free_rx_ring(dev);
638 for (i = 0; i < 4; i++)
639 if (priv->tx_ring[i].desc)
640 rtl8180_free_tx_ring(dev, i);
641
642 return ret;
643}
644
645static void rtl8180_stop(struct ieee80211_hw *dev)
646{
647 struct rtl8180_priv *priv = dev->priv;
648 u8 reg;
649 int i;
650
f6532111
MW		 651 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
652
653 reg = rtl818x_ioread8(priv, &priv->map->CMD);
654 reg &= ~RTL818X_CMD_TX_ENABLE;
655 reg &= ~RTL818X_CMD_RX_ENABLE;
656 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
657
658 priv->rf->stop(dev);
659
660 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
661 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
662 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
663 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
664
665 free_irq(priv->pdev->irq, dev);
666
667 rtl8180_free_rx_ring(dev);
668 for (i = 0; i < 4; i++)
669 rtl8180_free_tx_ring(dev, i);
670}
671
c809e86c
JL		 672static u64 rtl8180_get_tsf(struct ieee80211_hw *dev)
673{
674 struct rtl8180_priv *priv = dev->priv;
675
676 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
677 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
678}
679
a3275e24 680static void rtl8180_beacon_work(struct work_struct *work)
c809e86c
JL		 681{
682 struct rtl8180_vif *vif_priv =
683 container_of(work, struct rtl8180_vif, beacon_work.work);
684 struct ieee80211_vif *vif =
685 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
686 struct ieee80211_hw *dev = vif_priv->dev;
687 struct ieee80211_mgmt *mgmt;
688 struct sk_buff *skb;
c809e86c
JL		 689
690 /* don't overflow the tx ring */
691 if (ieee80211_queue_stopped(dev, 0))
692 goto resched;
693
694 /* grab a fresh beacon */
695 skb = ieee80211_beacon_get(dev, vif);
8f1d2d2b
JL		 696 if (!skb)
697 goto resched;
c809e86c
JL		 698
699 /*
700 * update beacon timestamp w/ TSF value
701 * TODO: make hardware update beacon timestamp
702 */
703 mgmt = (struct ieee80211_mgmt *)skb->data;
704 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev));
705
706 /* TODO: use actual beacon queue */
707 skb_set_queue_mapping(skb, 0);
708
7bb45683 709 rtl8180_tx(dev, skb);
c809e86c
JL		 710
711resched:
712 /*
713 * schedule next beacon
714 * TODO: use hardware support for beacon timing
715 */
716 schedule_delayed_work(&vif_priv->beacon_work,
717 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
718}
719
f6532111 720static int rtl8180_add_interface(struct ieee80211_hw *dev,
1ed32e4f 721 struct ieee80211_vif *vif)
f6532111
MW		 722{
723 struct rtl8180_priv *priv = dev->priv;
c809e86c 724 struct rtl8180_vif *vif_priv;
f6532111 725
643aab67
JL		 726 /*
727 * We only support one active interface at a time.
728 */
729 if (priv->vif)
730 return -EBUSY;
f6532111 731
1ed32e4f 732 switch (vif->type) {
05c914fe 733 case NL80211_IFTYPE_STATION:
c809e86c 734 case NL80211_IFTYPE_ADHOC:
f6532111
MW		 735 break;
736 default:
737 return -EOPNOTSUPP;
738 }
739
1ed32e4f 740 priv->vif = vif;
32bfd35d 741
c809e86c
JL		 742 /* Initialize driver private area */
743 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
744 vif_priv->dev = dev;
745 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
746 vif_priv->enable_beacon = false;
747
f6532111
MW		 748 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
749 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
1ed32e4f 750 le32_to_cpu(*(__le32 *)vif->addr));
f6532111 751 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
1ed32e4f 752 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
f6532111
MW		 753 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
754
755 return 0;
756}
757
758static void rtl8180_remove_interface(struct ieee80211_hw *dev,
1ed32e4f 759 struct ieee80211_vif *vif)
f6532111
MW		 760{
761 struct rtl8180_priv *priv = dev->priv;
32bfd35d 762 priv->vif = NULL;
f6532111
MW		 763}
764
e8975581 765static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
f6532111
MW		 766{
767 struct rtl8180_priv *priv = dev->priv;
e8975581 768 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 769
770 priv->rf->set_chan(dev, conf);
771
772 return 0;
773}
774
da81dede
JL		 775static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
776 struct ieee80211_vif *vif,
777 struct ieee80211_bss_conf *info,
778 u32 changed)
779{
780 struct rtl8180_priv *priv = dev->priv;
c809e86c 781 struct rtl8180_vif *vif_priv;
2d0ddec5 782 int i;
0f956e71 783 u8 reg;
2d0ddec5 784
c809e86c
JL		 785 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
786
2d0ddec5
JB		 787 if (changed & BSS_CHANGED_BSSID) {
788 for (i = 0; i < ETH_ALEN; i++)
789 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
790 info->bssid[i]);
791
0f956e71
JL		 792 if (is_valid_ether_addr(info->bssid)) {
793 if (vif->type == NL80211_IFTYPE_ADHOC)
794 reg = RTL818X_MSR_ADHOC;
795 else
796 reg = RTL818X_MSR_INFRA;
797 } else
798 reg = RTL818X_MSR_NO_LINK;
799 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
2d0ddec5 800 }
da81dede
JL		 801
802 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
c809e86c
JL		 803 priv->rf->conf_erp(dev, info);
804
805 if (changed & BSS_CHANGED_BEACON_ENABLED)
806 vif_priv->enable_beacon = info->enable_beacon;
807
808 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
809 cancel_delayed_work_sync(&vif_priv->beacon_work);
810 if (vif_priv->enable_beacon)
811 schedule_work(&vif_priv->beacon_work.work);
812 }
da81dede
JL		 813}
814
22bedad3
JP		 815static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
816 struct netdev_hw_addr_list *mc_list)
3ac64bee 817{
22bedad3 818 return netdev_hw_addr_list_count(mc_list);
3ac64bee
JB		 819}
820
f6532111
MW		 821static void rtl8180_configure_filter(struct ieee80211_hw *dev,
822 unsigned int changed_flags,
823 unsigned int *total_flags,
3ac64bee 824 u64 multicast)
f6532111
MW		 825{
826 struct rtl8180_priv *priv = dev->priv;
827
828 if (changed_flags & FIF_FCSFAIL)
829 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
830 if (changed_flags & FIF_CONTROL)
831 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
832 if (changed_flags & FIF_OTHER_BSS)
833 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
3ac64bee 834 if (*total_flags & FIF_ALLMULTI || multicast > 0)
f6532111
MW		 835 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
836 else
837 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
838
839 *total_flags = 0;
840
841 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
842 *total_flags |= FIF_FCSFAIL;
843 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
844 *total_flags |= FIF_CONTROL;
845 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
846 *total_flags |= FIF_OTHER_BSS;
847 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
848 *total_flags |= FIF_ALLMULTI;
849
850 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
851}
852
853static const struct ieee80211_ops rtl8180_ops = {
854 .tx = rtl8180_tx,
855 .start = rtl8180_start,
856 .stop = rtl8180_stop,
857 .add_interface = rtl8180_add_interface,
858 .remove_interface = rtl8180_remove_interface,
859 .config = rtl8180_config,
da81dede 860 .bss_info_changed = rtl8180_bss_info_changed,
3ac64bee 861 .prepare_multicast = rtl8180_prepare_multicast,
f6532111 862 .configure_filter = rtl8180_configure_filter,
d2bb8e02 863 .get_tsf = rtl8180_get_tsf,
f6532111
MW		 864};
865
866static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
867{
868 struct ieee80211_hw *dev = eeprom->data;
869 struct rtl8180_priv *priv = dev->priv;
870 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
871
872 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
873 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
874 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
875 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
876}
877
878static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
879{
880 struct ieee80211_hw *dev = eeprom->data;
881 struct rtl8180_priv *priv = dev->priv;
882 u8 reg = 2 << 6;
883
884 if (eeprom->reg_data_in)
885 reg |= RTL818X_EEPROM_CMD_WRITE;
886 if (eeprom->reg_data_out)
887 reg |= RTL818X_EEPROM_CMD_READ;
888 if (eeprom->reg_data_clock)
889 reg |= RTL818X_EEPROM_CMD_CK;
890 if (eeprom->reg_chip_select)
891 reg |= RTL818X_EEPROM_CMD_CS;
892
893 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
894 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
895 udelay(10);
896}
897
898static int __devinit rtl8180_probe(struct pci_dev *pdev,
899 const struct pci_device_id *id)
900{
901 struct ieee80211_hw *dev;
902 struct rtl8180_priv *priv;
903 unsigned long mem_addr, mem_len;
904 unsigned int io_addr, io_len;
905 int err, i;
906 struct eeprom_93cx6 eeprom;
907 const char *chip_name, *rf_name = NULL;
908 u32 reg;
909 u16 eeprom_val;
c693bf90 910 u8 mac_addr[ETH_ALEN];
f6532111
MW		 911
912 err = pci_enable_device(pdev);
913 if (err) {
914 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
915 pci_name(pdev));
916 return err;
917 }
918
919 err = pci_request_regions(pdev, KBUILD_MODNAME);
920 if (err) {
921 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
922 pci_name(pdev));
923 return err;
924 }
925
926 io_addr = pci_resource_start(pdev, 0);
927 io_len = pci_resource_len(pdev, 0);
928 mem_addr = pci_resource_start(pdev, 1);
929 mem_len = pci_resource_len(pdev, 1);
930
931 if (mem_len < sizeof(struct rtl818x_csr) ||
932 io_len < sizeof(struct rtl818x_csr)) {
933 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
934 pci_name(pdev));
935 err = -ENOMEM;
936 goto err_free_reg;
937 }
938
9e385c56
JL		 939 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
940 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
f6532111
MW		 941 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
942 pci_name(pdev));
943 goto err_free_reg;
944 }
945
946 pci_set_master(pdev);
947
948 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
949 if (!dev) {
950 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
951 pci_name(pdev));
952 err = -ENOMEM;
953 goto err_free_reg;
954 }
955
956 priv = dev->priv;
957 priv->pdev = pdev;
958
e6a9854b 959 dev->max_rates = 2;
f6532111
MW		 960 SET_IEEE80211_DEV(dev, &pdev->dev);
961 pci_set_drvdata(pdev, dev);
962
963 priv->map = pci_iomap(pdev, 1, mem_len);
964 if (!priv->map)
965 priv->map = pci_iomap(pdev, 0, io_len);
966
967 if (!priv->map) {
968 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
969 pci_name(pdev));
970 goto err_free_dev;
971 }
972
8318d78a
JB		 973 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
974 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
975
f6532111
MW		 976 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
977 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
8318d78a
JB		 978
979 priv->band.band = IEEE80211_BAND_2GHZ;
980 priv->band.channels = priv->channels;
981 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
982 priv->band.bitrates = priv->rates;
983 priv->band.n_bitrates = 4;
984 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
985
f6532111 986 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 987 IEEE80211_HW_RX_INCLUDES_FCS |
988 IEEE80211_HW_SIGNAL_UNSPEC;
c809e86c
JL		 989 dev->vif_data_size = sizeof(struct rtl8180_vif);
990 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
991 BIT(NL80211_IFTYPE_ADHOC);
f6532111 992 dev->queues = 1;
566bfe5a 993 dev->max_signal = 65;
f6532111
MW		 994
995 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
996 reg &= RTL818X_TX_CONF_HWVER_MASK;
997 switch (reg) {
998 case RTL818X_TX_CONF_R8180_ABCD:
999 chip_name = "RTL8180";
1000 break;
1001 case RTL818X_TX_CONF_R8180_F:
1002 chip_name = "RTL8180vF";
1003 break;
1004 case RTL818X_TX_CONF_R8185_ABC:
1005 chip_name = "RTL8185";
1006 break;
1007 case RTL818X_TX_CONF_R8185_D:
1008 chip_name = "RTL8185vD";
1009 break;
1010 default:
1011 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1012 pci_name(pdev), reg >> 25);
1013 goto err_iounmap;
1014 }
1015
1016 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1017 if (priv->r8185) {
8318d78a 1018 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
f6532111
MW		 1019 pci_try_set_mwi(pdev);
1020 }
1021
f6532111
MW		 1022 eeprom.data = dev;
1023 eeprom.register_read = rtl8180_eeprom_register_read;
1024 eeprom.register_write = rtl8180_eeprom_register_write;
1025 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1026 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1027 else
1028 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1029
1030 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1031 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1032 udelay(10);
1033
1034 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1035 eeprom_val &= 0xFF;
1036 switch (eeprom_val) {
1037 case 1: rf_name = "Intersil";
1038 break;
1039 case 2: rf_name = "RFMD";
1040 break;
1041 case 3: priv->rf = &sa2400_rf_ops;
1042 break;
1043 case 4: priv->rf = &max2820_rf_ops;
1044 break;
1045 case 5: priv->rf = &grf5101_rf_ops;
1046 break;
1047 case 9: priv->rf = rtl8180_detect_rf(dev);
1048 break;
1049 case 10:
1050 rf_name = "RTL8255";
1051 break;
1052 default:
1053 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1054 pci_name(pdev), eeprom_val);
1055 goto err_iounmap;
1056 }
1057
1058 if (!priv->rf) {
1059 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1060 pci_name(pdev), rf_name);
1061 goto err_iounmap;
1062 }
1063
1064 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1065 priv->csthreshold = eeprom_val >> 8;
1066 if (!priv->r8185) {
1067 __le32 anaparam;
1068 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1069 priv->anaparam = le32_to_cpu(anaparam);
1070 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1071 }
1072
c693bf90
JL		 1073 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1074 if (!is_valid_ether_addr(mac_addr)) {
f6532111
MW		 1075 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1076 " randomly generated MAC addr\n", pci_name(pdev));
c693bf90 1077 random_ether_addr(mac_addr);
f6532111 1078 }
c693bf90 1079 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
f6532111
MW		 1080
1081 /* CCK TX power */
1082 for (i = 0; i < 14; i += 2) {
1083 u16 txpwr;
1084 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
8318d78a
JB		 1085 priv->channels[i].hw_value = txpwr & 0xFF;
1086 priv->channels[i + 1].hw_value = txpwr >> 8;
f6532111
MW		 1087 }
1088
1089 /* OFDM TX power */
1090 if (priv->r8185) {
1091 for (i = 0; i < 14; i += 2) {
1092 u16 txpwr;
1093 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
8318d78a
JB		 1094 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1095 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
f6532111
MW		 1096 }
1097 }
1098
1099 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1100
1101 spin_lock_init(&priv->lock);
1102
1103 err = ieee80211_register_hw(dev);
1104 if (err) {
1105 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1106 pci_name(pdev));
1107 goto err_iounmap;
1108 }
1109
c96c31e4
JP		 1110 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1111 mac_addr, chip_name, priv->rf->name);
f6532111
MW		 1112
1113 return 0;
1114
1115 err_iounmap:
1116 iounmap(priv->map);
1117
1118 err_free_dev:
1119 pci_set_drvdata(pdev, NULL);
1120 ieee80211_free_hw(dev);
1121
1122 err_free_reg:
1123 pci_release_regions(pdev);
1124 pci_disable_device(pdev);
1125 return err;
1126}
1127
1128static void __devexit rtl8180_remove(struct pci_dev *pdev)
1129{
1130 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1131 struct rtl8180_priv *priv;
1132
1133 if (!dev)
1134 return;
1135
1136 ieee80211_unregister_hw(dev);
1137
1138 priv = dev->priv;
1139
1140 pci_iounmap(pdev, priv->map);
1141 pci_release_regions(pdev);
1142 pci_disable_device(pdev);
1143 ieee80211_free_hw(dev);
1144}
1145
1146#ifdef CONFIG_PM
1147static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1148{
1149 pci_save_state(pdev);
1150 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1151 return 0;
1152}
1153
1154static int rtl8180_resume(struct pci_dev *pdev)
1155{
1156 pci_set_power_state(pdev, PCI_D0);
1157 pci_restore_state(pdev);
1158 return 0;
1159}
1160
1161#endif /* CONFIG_PM */
1162
1163static struct pci_driver rtl8180_driver = {
1164 .name = KBUILD_MODNAME,
1165 .id_table = rtl8180_table,
1166 .probe = rtl8180_probe,
1167 .remove = __devexit_p(rtl8180_remove),
1168#ifdef CONFIG_PM
1169 .suspend = rtl8180_suspend,
1170 .resume = rtl8180_resume,
1171#endif /* CONFIG_PM */
1172};
1173
1174static int __init rtl8180_init(void)
1175{
1176 return pci_register_driver(&rtl8180_driver);
1177}
1178
1179static void __exit rtl8180_exit(void)
1180{
1181 pci_unregister_driver(&rtl8180_driver);
1182}
1183
1184module_init(rtl8180_init);
1185module_exit(rtl8180_exit);
Linux 6.x block layer and io_uring tree(s)