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mwifiex: add AMSDU inside AMPDU support
[linux-2.6-block.git] / drivers / net / wireless / rtl818x / rtl8180 / dev.c
CommitLineData
f6532111
MW		 1
2/*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
93ba2a85 6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
f6532111
MW		 7 *
8 * Based on the r8180 driver, which is:
93ba2a85 9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
f6532111
MW		 10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
a6b7a407 18#include <linux/interrupt.h>
f6532111 19#include <linux/pci.h>
5a0e3ad6 20#include <linux/slab.h>
f6532111
MW		 21#include <linux/delay.h>
22#include <linux/etherdevice.h>
23#include <linux/eeprom_93cx6.h>
9d9779e7 24#include <linux/module.h>
f6532111
MW		 25#include <net/mac80211.h>
26
27#include "rtl8180.h"
3cfeb0c3
JL		 28#include "rtl8225.h"
29#include "sa2400.h"
30#include "max2820.h"
31#include "grf5101.h"
f6532111
MW		 32
33MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
93ba2a85 34MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
f6532111
MW		 35MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36MODULE_LICENSE("GPL");
37
a3aa1884 38static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
f6532111
MW		 39 /* rtl8185 */
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
4fcc5470 41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
f6532111
MW		 42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
43
44 /* rtl8180 */
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
29a6b508
XVP		 49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
f6532111
MW		 51 { }
52};
53
54MODULE_DEVICE_TABLE(pci, rtl8180_table);
55
8318d78a
JB		 56static const struct ieee80211_rate rtl818x_rates[] = {
57 { .bitrate = 10, .hw_value = 0, },
58 { .bitrate = 20, .hw_value = 1, },
59 { .bitrate = 55, .hw_value = 2, },
60 { .bitrate = 110, .hw_value = 3, },
61 { .bitrate = 60, .hw_value = 4, },
62 { .bitrate = 90, .hw_value = 5, },
63 { .bitrate = 120, .hw_value = 6, },
64 { .bitrate = 180, .hw_value = 7, },
65 { .bitrate = 240, .hw_value = 8, },
66 { .bitrate = 360, .hw_value = 9, },
67 { .bitrate = 480, .hw_value = 10, },
68 { .bitrate = 540, .hw_value = 11, },
69};
70
71static const struct ieee80211_channel rtl818x_channels[] = {
72 { .center_freq = 2412 },
73 { .center_freq = 2417 },
74 { .center_freq = 2422 },
75 { .center_freq = 2427 },
76 { .center_freq = 2432 },
77 { .center_freq = 2437 },
78 { .center_freq = 2442 },
79 { .center_freq = 2447 },
80 { .center_freq = 2452 },
81 { .center_freq = 2457 },
82 { .center_freq = 2462 },
83 { .center_freq = 2467 },
84 { .center_freq = 2472 },
85 { .center_freq = 2484 },
86};
87
88
f6532111
MW		 89void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
90{
91 struct rtl8180_priv *priv = dev->priv;
92 int i = 10;
93 u32 buf;
94
95 buf = (data << 8) | addr;
96
97 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
98 while (i--) {
99 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
100 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
101 return;
102 }
103}
104
a6d27d2a 105static void rtl8180_handle_rx(struct ieee80211_hw *dev)
f6532111
MW		 106{
107 struct rtl8180_priv *priv = dev->priv;
a6d27d2a 108 unsigned int count = 32;
8b73fb8e 109 u8 signal, agc, sq;
2b4db05e 110 dma_addr_t mapping;
f6532111 111
a6d27d2a 112 while (count--) {
f6532111
MW		 113 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
114 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
115 u32 flags = le32_to_cpu(entry->flags);
116
38e3b0d8 117 if (flags & RTL818X_RX_DESC_FLAG_OWN)
a6d27d2a 118 return;
f6532111 119
38e3b0d8
HRK		 120 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
121 RTL818X_RX_DESC_FLAG_FOF |
122 RTL818X_RX_DESC_FLAG_RX_ERR)))
f6532111
MW		 123 goto done;
124 else {
125 u32 flags2 = le32_to_cpu(entry->flags2);
126 struct ieee80211_rx_status rx_status = {0};
127 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
128
129 if (unlikely(!new_skb))
130 goto done;
131
2b4db05e 132 mapping = pci_map_single(priv->pdev,
133 skb_tail_pointer(new_skb),
134 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
135
136 if (pci_dma_mapping_error(priv->pdev, mapping)) {
137 kfree_skb(new_skb);
138 dev_err(&priv->pdev->dev, "RX DMA map error\n");
139
140 goto done;
141 }
142
f6532111
MW		 143 pci_unmap_single(priv->pdev,
144 *((dma_addr_t *)skb->cb),
145 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
146 skb_put(skb, flags & 0xFFF);
147
148 rx_status.antenna = (flags2 >> 15) & 1;
8318d78a 149 rx_status.rate_idx = (flags >> 20) & 0xF;
8b73fb8e
JL		 150 agc = (flags2 >> 17) & 0x7F;
151 if (priv->r8185) {
152 if (rx_status.rate_idx > 3)
153 signal = 90 - clamp_t(u8, agc, 25, 90);
154 else
155 signal = 95 - clamp_t(u8, agc, 30, 95);
156 } else {
157 sq = flags2 & 0xff;
158 signal = priv->rf->calc_rssi(agc, sq);
159 }
8b74964c 160 rx_status.signal = signal;
675a0b04
KB		 161 rx_status.freq = dev->conf.chandef.chan->center_freq;
162 rx_status.band = dev->conf.chandef.chan->band;
f6532111 163 rx_status.mactime = le64_to_cpu(entry->tsft);
f4bda337 164 rx_status.flag |= RX_FLAG_MACTIME_START;
38e3b0d8 165 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
f6532111
MW		 166 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
167
f1d58c25 168 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
a6d27d2a 169 ieee80211_rx_irqsafe(dev, skb);
f6532111
MW		 170
171 skb = new_skb;
172 priv->rx_buf[priv->rx_idx] = skb;
2b4db05e 173 *((dma_addr_t *) skb->cb) = mapping;
f6532111
MW		 174 }
175
176 done:
177 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
38e3b0d8 178 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
f6532111
MW		 179 MAX_RX_SIZE);
180 if (priv->rx_idx == 31)
38e3b0d8 181 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
f6532111
MW		 182 priv->rx_idx = (priv->rx_idx + 1) % 32;
183 }
a6d27d2a
JL		 184}
185
186static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
187{
188 struct rtl8180_priv *priv = dev->priv;
189 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
e6a9854b 190
a6d27d2a
JL		 191 while (skb_queue_len(&ring->queue)) {
192 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
193 struct sk_buff *skb;
194 struct ieee80211_tx_info *info;
195 u32 flags = le32_to_cpu(entry->flags);
f6532111 196
a6d27d2a
JL		 197 if (flags & RTL818X_TX_DESC_FLAG_OWN)
198 return;
199
200 ring->idx = (ring->idx + 1) % ring->entries;
201 skb = __skb_dequeue(&ring->queue);
202 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
203 skb->len, PCI_DMA_TODEVICE);
204
205 info = IEEE80211_SKB_CB(skb);
206 ieee80211_tx_info_clear_status(info);
207
208 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
209 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
210 info->flags |= IEEE80211_TX_STAT_ACK;
211
212 info->status.rates[0].count = (flags & 0xFF) + 1;
213 info->status.rates[1].idx = -1;
030725d2 214
a6d27d2a
JL		 215 ieee80211_tx_status_irqsafe(dev, skb);
216 if (ring->entries - skb_queue_len(&ring->queue) == 2)
217 ieee80211_wake_queue(dev, prio);
218 }
f6532111
MW		 219}
220
221static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
222{
223 struct ieee80211_hw *dev = dev_id;
224 struct rtl8180_priv *priv = dev->priv;
225 u16 reg;
226
a6d27d2a 227 spin_lock(&priv->lock);
f6532111 228 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
a6d27d2a
JL		 229 if (unlikely(reg == 0xFFFF)) {
230 spin_unlock(&priv->lock);
f6532111 231 return IRQ_HANDLED;
a6d27d2a 232 }
f6532111
MW		 233
234 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
235
a6d27d2a
JL		 236 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
237 rtl8180_handle_tx(dev, 3);
238
239 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
240 rtl8180_handle_tx(dev, 2);
241
242 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
243 rtl8180_handle_tx(dev, 1);
f6532111 244
a6d27d2a
JL		 245 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
246 rtl8180_handle_tx(dev, 0);
247
248 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
249 rtl8180_handle_rx(dev);
250
251 spin_unlock(&priv->lock);
f6532111
MW		 252
253 return IRQ_HANDLED;
254}
255
36323f81
TH		 256static void rtl8180_tx(struct ieee80211_hw *dev,
257 struct ieee80211_tx_control *control,
258 struct sk_buff *skb)
f6532111 259{
e039fa4a 260 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
51e080de 261 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
f6532111
MW		 262 struct rtl8180_priv *priv = dev->priv;
263 struct rtl8180_tx_ring *ring;
264 struct rtl8180_tx_desc *entry;
a6d27d2a 265 unsigned long flags;
f6532111
MW		 266 unsigned int idx, prio;
267 dma_addr_t mapping;
268 u32 tx_flags;
e6a9854b 269 u8 rc_flags;
f6532111
MW		 270 u16 plcp_len = 0;
271 __le16 rts_duration = 0;
272
e2530083 273 prio = skb_get_queue_mapping(skb);
f6532111
MW		 274 ring = &priv->tx_ring[prio];
275
276 mapping = pci_map_single(priv->pdev, skb->data,
277 skb->len, PCI_DMA_TODEVICE);
278
348f7d4a 279 if (pci_dma_mapping_error(priv->pdev, mapping)) {
280 kfree_skb(skb);
281 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
282 return;
283
284 }
285
38e3b0d8
HRK		 286 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
287 RTL818X_TX_DESC_FLAG_LS |
e039fa4a 288 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
2e92e6f2 289 skb->len;
f6532111
MW		 290
291 if (priv->r8185)
38e3b0d8
HRK		 292 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
293 RTL818X_TX_DESC_FLAG_NO_ENC;
f6532111 294
e6a9854b
JB		 295 rc_flags = info->control.rates[0].flags;
296 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
38e3b0d8 297 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 298 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
e6a9854b 299 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
38e3b0d8 300 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 301 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 302 }
f6532111 303
e6a9854b 304 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
32bfd35d 305 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
e039fa4a 306 info);
f6532111
MW		 307
308 if (!priv->r8185) {
309 unsigned int remainder;
310
311 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
e039fa4a 312 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
f6532111 313 remainder = (16 * (skb->len + 4)) %
e039fa4a 314 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
35a0ace7 315 if (remainder <= 6)
f6532111
MW		 316 plcp_len |= 1 << 15;
317 }
318
a6d27d2a 319 spin_lock_irqsave(&priv->lock, flags);
51e080de
JL		 320
321 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
322 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
323 priv->seqno += 0x10;
324 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
325 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
326 }
327
f6532111
MW		 328 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
329 entry = &ring->desc[idx];
330
331 entry->rts_duration = rts_duration;
332 entry->plcp_len = cpu_to_le16(plcp_len);
333 entry->tx_buf = cpu_to_le32(mapping);
334 entry->frame_len = cpu_to_le32(skb->len);
e6a9854b 335 entry->flags2 = info->control.rates[1].idx >= 0 ?
870abdf6 336 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
e6a9854b 337 entry->retry_limit = info->control.rates[0].count;
4c552a5b 338
339 /* We must be sure that tx_flags is written last because the HW
340 * looks at it to check if the rest of data is valid or not
341 */
342 wmb();
f6532111 343 entry->flags = cpu_to_le32(tx_flags);
c24782e6 344 /* We must be sure this has been written before followings HW
345 * register write, because this write will made the HW attempts
346 * to DMA the just-written data
347 */
348 wmb();
349
f6532111
MW		 350 __skb_queue_tail(&ring->queue, skb);
351 if (ring->entries - skb_queue_len(&ring->queue) < 2)
d10e2e02 352 ieee80211_stop_queue(dev, prio);
51e080de 353
a6d27d2a 354 spin_unlock_irqrestore(&priv->lock, flags);
f6532111
MW		 355
356 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
f6532111
MW		 357}
358
359void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
360{
361 u8 reg;
362
363 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
364 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
365 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
366 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
367 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
368 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
369 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
370 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
371}
372
373static int rtl8180_init_hw(struct ieee80211_hw *dev)
374{
375 struct rtl8180_priv *priv = dev->priv;
376 u16 reg;
377
378 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
379 rtl818x_ioread8(priv, &priv->map->CMD);
380 msleep(10);
381
382 /* reset */
383 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
384 rtl818x_ioread8(priv, &priv->map->CMD);
385
386 reg = rtl818x_ioread8(priv, &priv->map->CMD);
387 reg &= (1 << 1);
388 reg |= RTL818X_CMD_RESET;
389 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
390 rtl818x_ioread8(priv, &priv->map->CMD);
391 msleep(200);
392
393 /* check success of reset */
394 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
c96c31e4 395 wiphy_err(dev->wiphy, "reset timeout!\n");
f6532111
MW		 396 return -ETIMEDOUT;
397 }
398
399 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
400 rtl818x_ioread8(priv, &priv->map->CMD);
401 msleep(200);
402
403 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
404 /* For cardbus */
405 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
406 reg |= 1 << 1;
407 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
408 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
409 reg |= (1 << 15) | (1 << 14) | (1 << 4);
410 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
411 }
412
413 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
414
415 if (!priv->r8185)
416 rtl8180_set_anaparam(priv, priv->anaparam);
417
418 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
419 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
420 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
421 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
422 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
423
424 /* TODO: necessary? specs indicate not */
425 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
426 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
427 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
428 if (priv->r8185) {
429 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
430 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
431 }
432 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
433
434 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
435
436 /* TODO: turn off hw wep on rtl8180 */
437
438 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
439
440 if (priv->r8185) {
441 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
442 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
443 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
444
445 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
446
447 /* TODO: set ClkRun enable? necessary? */
448 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
449 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
450 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
451 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
452 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
453 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
454 } else {
455 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
456 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
457
458 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
459 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
460 }
461
462 priv->rf->init(dev);
463 if (priv->r8185)
464 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
465 return 0;
466}
467
468static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
469{
470 struct rtl8180_priv *priv = dev->priv;
471 struct rtl8180_rx_desc *entry;
472 int i;
473
474 priv->rx_ring = pci_alloc_consistent(priv->pdev,
475 sizeof(*priv->rx_ring) * 32,
476 &priv->rx_ring_dma);
477
478 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
5db55844 479 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
f6532111
MW		 480 return -ENOMEM;
481 }
482
483 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
484 priv->rx_idx = 0;
485
486 for (i = 0; i < 32; i++) {
487 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
488 dma_addr_t *mapping;
489 entry = &priv->rx_ring[i];
4da18bb4 490 if (!skb) {
491 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
492 return -ENOMEM;
493 }
f6532111
MW		 494 priv->rx_buf[i] = skb;
495 mapping = (dma_addr_t *)skb->cb;
496 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
497 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
ec1da08d 498
499 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
500 kfree_skb(skb);
501 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
502 return -ENOMEM;
503 }
504
f6532111 505 entry->rx_buf = cpu_to_le32(*mapping);
38e3b0d8 506 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
f6532111
MW		 507 MAX_RX_SIZE);
508 }
38e3b0d8 509 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
f6532111
MW		 510 return 0;
511}
512
513static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
514{
515 struct rtl8180_priv *priv = dev->priv;
516 int i;
517
518 for (i = 0; i < 32; i++) {
519 struct sk_buff *skb = priv->rx_buf[i];
520 if (!skb)
521 continue;
522
523 pci_unmap_single(priv->pdev,
524 *((dma_addr_t *)skb->cb),
525 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
526 kfree_skb(skb);
527 }
528
529 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
530 priv->rx_ring, priv->rx_ring_dma);
531 priv->rx_ring = NULL;
532}
533
534static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
535 unsigned int prio, unsigned int entries)
536{
537 struct rtl8180_priv *priv = dev->priv;
538 struct rtl8180_tx_desc *ring;
539 dma_addr_t dma;
540 int i;
541
542 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
543 if (!ring || (unsigned long)ring & 0xFF) {
5db55844 544 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
c96c31e4 545 prio);
f6532111
MW		 546 return -ENOMEM;
547 }
548
549 memset(ring, 0, sizeof(*ring)*entries);
550 priv->tx_ring[prio].desc = ring;
551 priv->tx_ring[prio].dma = dma;
552 priv->tx_ring[prio].idx = 0;
553 priv->tx_ring[prio].entries = entries;
554 skb_queue_head_init(&priv->tx_ring[prio].queue);
555
556 for (i = 0; i < entries; i++)
557 ring[i].next_tx_desc =
558 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
559
560 return 0;
561}
562
563static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
564{
565 struct rtl8180_priv *priv = dev->priv;
566 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
567
568 while (skb_queue_len(&ring->queue)) {
569 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
570 struct sk_buff *skb = __skb_dequeue(&ring->queue);
571
572 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
573 skb->len, PCI_DMA_TODEVICE);
f6532111
MW		 574 kfree_skb(skb);
575 ring->idx = (ring->idx + 1) % ring->entries;
576 }
577
578 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
579 ring->desc, ring->dma);
580 ring->desc = NULL;
581}
582
583static int rtl8180_start(struct ieee80211_hw *dev)
584{
585 struct rtl8180_priv *priv = dev->priv;
586 int ret, i;
587 u32 reg;
588
589 ret = rtl8180_init_rx_ring(dev);
590 if (ret)
591 return ret;
592
593 for (i = 0; i < 4; i++)
594 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
595 goto err_free_rings;
596
597 ret = rtl8180_init_hw(dev);
598 if (ret)
599 goto err_free_rings;
600
601 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
602 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
603 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
604 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
605 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
606
ea31ba35 607 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
f6532111
MW		 608 IRQF_SHARED, KBUILD_MODNAME, dev);
609 if (ret) {
5db55844 610 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
f6532111
MW		 611 goto err_free_rings;
612 }
613
614 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
615
616 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
617 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
618
619 reg = RTL818X_RX_CONF_ONLYERLPKT |
620 RTL818X_RX_CONF_RX_AUTORESETPHY |
621 RTL818X_RX_CONF_MGMT |
622 RTL818X_RX_CONF_DATA |
623 (7 << 8 /* MAX RX DMA */) |
624 RTL818X_RX_CONF_BROADCAST |
625 RTL818X_RX_CONF_NICMAC;
626
627 if (priv->r8185)
628 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
629 else {
630 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
631 ? RTL818X_RX_CONF_CSDM1 : 0;
632 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
633 ? RTL818X_RX_CONF_CSDM2 : 0;
634 }
635
636 priv->rx_conf = reg;
637 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
638
639 if (priv->r8185) {
640 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
14c76150 641
642 /* CW is not on per-packet basis.
643 * in rtl8185 the CW_VALUE reg is used.
644 */
6f7343d4 645 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
14c76150 646 /* retry limit IS on per-packet basis.
647 * the short and long retry limit in TX_CONF
648 * reg are ignored
649 */
6f7343d4 650 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
f6532111
MW		 651 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
652
653 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
14c76150 654 /* TX antenna and TX gain are not on per-packet basis.
655 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
656 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
657 */
6f7343d4 658 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
659 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
f6532111
MW		 660 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
661 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
662
663 /* disable early TX */
664 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
665 }
666
667 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
668 reg |= (6 << 21 /* MAX TX DMA */) |
669 RTL818X_TX_CONF_NO_ICV;
670
671 if (priv->r8185)
672 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
673 else
674 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
675
e74075a9 676 reg &= ~RTL818X_TX_CONF_DISCW;
677
f6532111
MW		 678 /* different meaning, same value on both rtl8185 and rtl8180 */
679 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
680
681 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
682
683 reg = rtl818x_ioread8(priv, &priv->map->CMD);
684 reg |= RTL818X_CMD_RX_ENABLE;
685 reg |= RTL818X_CMD_TX_ENABLE;
686 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
687
f6532111
MW		 688 return 0;
689
690 err_free_rings:
691 rtl8180_free_rx_ring(dev);
692 for (i = 0; i < 4; i++)
693 if (priv->tx_ring[i].desc)
694 rtl8180_free_tx_ring(dev, i);
695
696 return ret;
697}
698
699static void rtl8180_stop(struct ieee80211_hw *dev)
700{
701 struct rtl8180_priv *priv = dev->priv;
702 u8 reg;
703 int i;
704
f6532111
MW		 705 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
706
707 reg = rtl818x_ioread8(priv, &priv->map->CMD);
708 reg &= ~RTL818X_CMD_TX_ENABLE;
709 reg &= ~RTL818X_CMD_RX_ENABLE;
710 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
711
712 priv->rf->stop(dev);
713
714 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
715 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
716 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
717 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
718
719 free_irq(priv->pdev->irq, dev);
720
721 rtl8180_free_rx_ring(dev);
722 for (i = 0; i < 4; i++)
723 rtl8180_free_tx_ring(dev, i);
724}
725
37a41b4a
EP		 726static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
727 struct ieee80211_vif *vif)
c809e86c
JL		 728{
729 struct rtl8180_priv *priv = dev->priv;
730
731 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
732 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
733}
734
a3275e24 735static void rtl8180_beacon_work(struct work_struct *work)
c809e86c
JL		 736{
737 struct rtl8180_vif *vif_priv =
738 container_of(work, struct rtl8180_vif, beacon_work.work);
739 struct ieee80211_vif *vif =
740 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
741 struct ieee80211_hw *dev = vif_priv->dev;
742 struct ieee80211_mgmt *mgmt;
743 struct sk_buff *skb;
c809e86c
JL		 744
745 /* don't overflow the tx ring */
746 if (ieee80211_queue_stopped(dev, 0))
747 goto resched;
748
749 /* grab a fresh beacon */
750 skb = ieee80211_beacon_get(dev, vif);
8f1d2d2b
JL		 751 if (!skb)
752 goto resched;
c809e86c
JL		 753
754 /*
755 * update beacon timestamp w/ TSF value
756 * TODO: make hardware update beacon timestamp
757 */
758 mgmt = (struct ieee80211_mgmt *)skb->data;
37a41b4a 759 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
c809e86c
JL		 760
761 /* TODO: use actual beacon queue */
762 skb_set_queue_mapping(skb, 0);
763
36323f81 764 rtl8180_tx(dev, NULL, skb);
c809e86c
JL		 765
766resched:
767 /*
768 * schedule next beacon
769 * TODO: use hardware support for beacon timing
770 */
771 schedule_delayed_work(&vif_priv->beacon_work,
772 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
773}
774
f6532111 775static int rtl8180_add_interface(struct ieee80211_hw *dev,
1ed32e4f 776 struct ieee80211_vif *vif)
f6532111
MW		 777{
778 struct rtl8180_priv *priv = dev->priv;
c809e86c 779 struct rtl8180_vif *vif_priv;
f6532111 780
643aab67
JL		 781 /*
782 * We only support one active interface at a time.
783 */
784 if (priv->vif)
785 return -EBUSY;
f6532111 786
1ed32e4f 787 switch (vif->type) {
05c914fe 788 case NL80211_IFTYPE_STATION:
c809e86c 789 case NL80211_IFTYPE_ADHOC:
f6532111
MW		 790 break;
791 default:
792 return -EOPNOTSUPP;
793 }
794
1ed32e4f 795 priv->vif = vif;
32bfd35d 796
c809e86c
JL		 797 /* Initialize driver private area */
798 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
799 vif_priv->dev = dev;
800 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
801 vif_priv->enable_beacon = false;
802
f6532111
MW		 803 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
804 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
1ed32e4f 805 le32_to_cpu(*(__le32 *)vif->addr));
f6532111 806 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
1ed32e4f 807 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
f6532111
MW		 808 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
809
810 return 0;
811}
812
813static void rtl8180_remove_interface(struct ieee80211_hw *dev,
1ed32e4f 814 struct ieee80211_vif *vif)
f6532111
MW		 815{
816 struct rtl8180_priv *priv = dev->priv;
32bfd35d 817 priv->vif = NULL;
f6532111
MW		 818}
819
e8975581 820static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
f6532111
MW		 821{
822 struct rtl8180_priv *priv = dev->priv;
e8975581 823 struct ieee80211_conf *conf = &dev->conf;
f6532111
MW		 824
825 priv->rf->set_chan(dev, conf);
826
827 return 0;
828}
829
da81dede
JL		 830static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
831 struct ieee80211_vif *vif,
832 struct ieee80211_bss_conf *info,
833 u32 changed)
834{
835 struct rtl8180_priv *priv = dev->priv;
c809e86c 836 struct rtl8180_vif *vif_priv;
2d0ddec5 837 int i;
0f956e71 838 u8 reg;
2d0ddec5 839
c809e86c
JL		 840 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
841
2d0ddec5
JB		 842 if (changed & BSS_CHANGED_BSSID) {
843 for (i = 0; i < ETH_ALEN; i++)
844 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
845 info->bssid[i]);
846
0f956e71
JL		 847 if (is_valid_ether_addr(info->bssid)) {
848 if (vif->type == NL80211_IFTYPE_ADHOC)
849 reg = RTL818X_MSR_ADHOC;
850 else
851 reg = RTL818X_MSR_INFRA;
852 } else
853 reg = RTL818X_MSR_NO_LINK;
854 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
2d0ddec5 855 }
da81dede
JL		 856
857 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
c809e86c
JL		 858 priv->rf->conf_erp(dev, info);
859
860 if (changed & BSS_CHANGED_BEACON_ENABLED)
861 vif_priv->enable_beacon = info->enable_beacon;
862
863 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
864 cancel_delayed_work_sync(&vif_priv->beacon_work);
865 if (vif_priv->enable_beacon)
866 schedule_work(&vif_priv->beacon_work.work);
867 }
da81dede
JL		 868}
869
22bedad3
JP		 870static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
871 struct netdev_hw_addr_list *mc_list)
3ac64bee 872{
22bedad3 873 return netdev_hw_addr_list_count(mc_list);
3ac64bee
JB		 874}
875
f6532111
MW		 876static void rtl8180_configure_filter(struct ieee80211_hw *dev,
877 unsigned int changed_flags,
878 unsigned int *total_flags,
3ac64bee 879 u64 multicast)
f6532111
MW		 880{
881 struct rtl8180_priv *priv = dev->priv;
882
883 if (changed_flags & FIF_FCSFAIL)
884 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
885 if (changed_flags & FIF_CONTROL)
886 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
887 if (changed_flags & FIF_OTHER_BSS)
888 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
3ac64bee 889 if (*total_flags & FIF_ALLMULTI || multicast > 0)
f6532111
MW		 890 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
891 else
892 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
893
894 *total_flags = 0;
895
896 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
897 *total_flags |= FIF_FCSFAIL;
898 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
899 *total_flags |= FIF_CONTROL;
900 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
901 *total_flags |= FIF_OTHER_BSS;
902 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
903 *total_flags |= FIF_ALLMULTI;
904
905 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
906}
907
908static const struct ieee80211_ops rtl8180_ops = {
909 .tx = rtl8180_tx,
910 .start = rtl8180_start,
911 .stop = rtl8180_stop,
912 .add_interface = rtl8180_add_interface,
913 .remove_interface = rtl8180_remove_interface,
914 .config = rtl8180_config,
da81dede 915 .bss_info_changed = rtl8180_bss_info_changed,
3ac64bee 916 .prepare_multicast = rtl8180_prepare_multicast,
f6532111 917 .configure_filter = rtl8180_configure_filter,
d2bb8e02 918 .get_tsf = rtl8180_get_tsf,
f6532111
MW		 919};
920
921static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
922{
923 struct ieee80211_hw *dev = eeprom->data;
924 struct rtl8180_priv *priv = dev->priv;
925 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
926
927 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
928 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
929 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
930 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
931}
932
933static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
934{
935 struct ieee80211_hw *dev = eeprom->data;
936 struct rtl8180_priv *priv = dev->priv;
937 u8 reg = 2 << 6;
938
939 if (eeprom->reg_data_in)
940 reg |= RTL818X_EEPROM_CMD_WRITE;
941 if (eeprom->reg_data_out)
942 reg |= RTL818X_EEPROM_CMD_READ;
943 if (eeprom->reg_data_clock)
944 reg |= RTL818X_EEPROM_CMD_CK;
945 if (eeprom->reg_chip_select)
946 reg |= RTL818X_EEPROM_CMD_CS;
947
948 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
949 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
950 udelay(10);
951}
952
fb4e899d 953static int rtl8180_probe(struct pci_dev *pdev,
f6532111
MW		 954 const struct pci_device_id *id)
955{
956 struct ieee80211_hw *dev;
957 struct rtl8180_priv *priv;
958 unsigned long mem_addr, mem_len;
959 unsigned int io_addr, io_len;
960 int err, i;
961 struct eeprom_93cx6 eeprom;
962 const char *chip_name, *rf_name = NULL;
963 u32 reg;
964 u16 eeprom_val;
c693bf90 965 u8 mac_addr[ETH_ALEN];
f6532111
MW		 966
967 err = pci_enable_device(pdev);
968 if (err) {
969 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
970 pci_name(pdev));
971 return err;
972 }
973
974 err = pci_request_regions(pdev, KBUILD_MODNAME);
975 if (err) {
976 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
977 pci_name(pdev));
978 return err;
979 }
980
981 io_addr = pci_resource_start(pdev, 0);
982 io_len = pci_resource_len(pdev, 0);
983 mem_addr = pci_resource_start(pdev, 1);
984 mem_len = pci_resource_len(pdev, 1);
985
986 if (mem_len < sizeof(struct rtl818x_csr) ||
987 io_len < sizeof(struct rtl818x_csr)) {
988 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
989 pci_name(pdev));
990 err = -ENOMEM;
991 goto err_free_reg;
992 }
993
9e385c56
JL		 994 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
995 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
f6532111
MW		 996 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
997 pci_name(pdev));
998 goto err_free_reg;
999 }
1000
1001 pci_set_master(pdev);
1002
1003 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1004 if (!dev) {
1005 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1006 pci_name(pdev));
1007 err = -ENOMEM;
1008 goto err_free_reg;
1009 }
1010
1011 priv = dev->priv;
1012 priv->pdev = pdev;
1013
e6a9854b 1014 dev->max_rates = 2;
f6532111
MW		 1015 SET_IEEE80211_DEV(dev, &pdev->dev);
1016 pci_set_drvdata(pdev, dev);
1017
1018 priv->map = pci_iomap(pdev, 1, mem_len);
1019 if (!priv->map)
1020 priv->map = pci_iomap(pdev, 0, io_len);
1021
1022 if (!priv->map) {
1023 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
1024 pci_name(pdev));
1025 goto err_free_dev;
1026 }
1027
8318d78a
JB		 1028 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1029 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1030
f6532111
MW		 1031 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1032 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
8318d78a
JB		 1033
1034 priv->band.band = IEEE80211_BAND_2GHZ;
1035 priv->band.channels = priv->channels;
1036 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1037 priv->band.bitrates = priv->rates;
1038 priv->band.n_bitrates = 4;
1039 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1040
f6532111 1041 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 1042 IEEE80211_HW_RX_INCLUDES_FCS |
1043 IEEE80211_HW_SIGNAL_UNSPEC;
c809e86c
JL		 1044 dev->vif_data_size = sizeof(struct rtl8180_vif);
1045 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1046 BIT(NL80211_IFTYPE_ADHOC);
f6532111 1047 dev->queues = 1;
566bfe5a 1048 dev->max_signal = 65;
f6532111
MW		 1049
1050 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1051 reg &= RTL818X_TX_CONF_HWVER_MASK;
1052 switch (reg) {
1053 case RTL818X_TX_CONF_R8180_ABCD:
1054 chip_name = "RTL8180";
1055 break;
1056 case RTL818X_TX_CONF_R8180_F:
1057 chip_name = "RTL8180vF";
1058 break;
1059 case RTL818X_TX_CONF_R8185_ABC:
1060 chip_name = "RTL8185";
1061 break;
1062 case RTL818X_TX_CONF_R8185_D:
1063 chip_name = "RTL8185vD";
1064 break;
1065 default:
1066 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1067 pci_name(pdev), reg >> 25);
1068 goto err_iounmap;
1069 }
1070
1071 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1072 if (priv->r8185) {
8318d78a 1073 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
f6532111
MW		 1074 pci_try_set_mwi(pdev);
1075 }
1076
f6532111
MW		 1077 eeprom.data = dev;
1078 eeprom.register_read = rtl8180_eeprom_register_read;
1079 eeprom.register_write = rtl8180_eeprom_register_write;
1080 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1081 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1082 else
1083 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1084
1085 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1086 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1087 udelay(10);
1088
1089 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1090 eeprom_val &= 0xFF;
1091 switch (eeprom_val) {
1092 case 1: rf_name = "Intersil";
1093 break;
1094 case 2: rf_name = "RFMD";
1095 break;
1096 case 3: priv->rf = &sa2400_rf_ops;
1097 break;
1098 case 4: priv->rf = &max2820_rf_ops;
1099 break;
1100 case 5: priv->rf = &grf5101_rf_ops;
1101 break;
1102 case 9: priv->rf = rtl8180_detect_rf(dev);
1103 break;
1104 case 10:
1105 rf_name = "RTL8255";
1106 break;
1107 default:
1108 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1109 pci_name(pdev), eeprom_val);
1110 goto err_iounmap;
1111 }
1112
1113 if (!priv->rf) {
1114 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1115 pci_name(pdev), rf_name);
1116 goto err_iounmap;
1117 }
1118
1119 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1120 priv->csthreshold = eeprom_val >> 8;
1121 if (!priv->r8185) {
1122 __le32 anaparam;
1123 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1124 priv->anaparam = le32_to_cpu(anaparam);
1125 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1126 }
1127
c693bf90
JL		 1128 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1129 if (!is_valid_ether_addr(mac_addr)) {
f6532111
MW		 1130 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1131 " randomly generated MAC addr\n", pci_name(pdev));
f4f7f414 1132 eth_random_addr(mac_addr);
f6532111 1133 }
c693bf90 1134 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
f6532111
MW		 1135
1136 /* CCK TX power */
1137 for (i = 0; i < 14; i += 2) {
1138 u16 txpwr;
1139 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
8318d78a
JB		 1140 priv->channels[i].hw_value = txpwr & 0xFF;
1141 priv->channels[i + 1].hw_value = txpwr >> 8;
f6532111
MW		 1142 }
1143
1144 /* OFDM TX power */
1145 if (priv->r8185) {
1146 for (i = 0; i < 14; i += 2) {
1147 u16 txpwr;
1148 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
8318d78a
JB		 1149 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1150 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
f6532111
MW		 1151 }
1152 }
1153
1154 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1155
1156 spin_lock_init(&priv->lock);
1157
1158 err = ieee80211_register_hw(dev);
1159 if (err) {
1160 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1161 pci_name(pdev));
1162 goto err_iounmap;
1163 }
1164
c96c31e4
JP		 1165 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1166 mac_addr, chip_name, priv->rf->name);
f6532111
MW		 1167
1168 return 0;
1169
1170 err_iounmap:
0269da28 1171 pci_iounmap(pdev, priv->map);
f6532111
MW		 1172
1173 err_free_dev:
f6532111
MW		 1174 ieee80211_free_hw(dev);
1175
1176 err_free_reg:
1177 pci_release_regions(pdev);
1178 pci_disable_device(pdev);
1179 return err;
1180}
1181
fb4e899d 1182static void rtl8180_remove(struct pci_dev *pdev)
f6532111
MW		 1183{
1184 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1185 struct rtl8180_priv *priv;
1186
1187 if (!dev)
1188 return;
1189
1190 ieee80211_unregister_hw(dev);
1191
1192 priv = dev->priv;
1193
1194 pci_iounmap(pdev, priv->map);
1195 pci_release_regions(pdev);
1196 pci_disable_device(pdev);
1197 ieee80211_free_hw(dev);
1198}
1199
1200#ifdef CONFIG_PM
1201static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1202{
1203 pci_save_state(pdev);
1204 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1205 return 0;
1206}
1207
1208static int rtl8180_resume(struct pci_dev *pdev)
1209{
1210 pci_set_power_state(pdev, PCI_D0);
1211 pci_restore_state(pdev);
1212 return 0;
1213}
1214
1215#endif /* CONFIG_PM */
1216
1217static struct pci_driver rtl8180_driver = {
1218 .name = KBUILD_MODNAME,
1219 .id_table = rtl8180_table,
1220 .probe = rtl8180_probe,
fb4e899d 1221 .remove = rtl8180_remove,
f6532111
MW		 1222#ifdef CONFIG_PM
1223 .suspend = rtl8180_suspend,
1224 .resume = rtl8180_resume,
1225#endif /* CONFIG_PM */
1226};
1227
5b0a3b7e 1228module_pci_driver(rtl8180_driver);
Linux 6.x block layer and io_uring tree(s)