projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rtl8187: Add USB ID for Belkin F5D7050 with RTL8187B chip
[linux-2.6-block.git] / drivers / net / wireless / rtl8187_dev.c
CommitLineData
605bebe2
MW		 1/*
2 * Linux device driver for RTL8187
3 *
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007 Andrea Merello <andreamrl@tiscali.it>
6 *
7 * Based on the r8187 driver, which is:
8 * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al.
9 *
0aec00ae
JL		 10 * Magic delays and register offsets below are taken from the original
11 * r8187 driver sources. Thanks to Realtek for their support!
605bebe2
MW		 12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/usb.h>
20#include <linux/delay.h>
21#include <linux/etherdevice.h>
22#include <linux/eeprom_93cx6.h>
23#include <net/mac80211.h>
24
25#include "rtl8187.h"
26#include "rtl8187_rtl8225.h"
27
28MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
29MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
f8a08c34 30MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver");
605bebe2
MW		 31MODULE_LICENSE("GPL");
32
33static struct usb_device_id rtl8187_table[] __devinitdata = {
7c7e6af3
AM		 34 /* Asus */
35 {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187},
eaca90da
FF		 36 /* Belkin */
37 {USB_DEVICE(0x050d, 0x705e), .driver_info = DEVICE_RTL8187B},
605bebe2 38 /* Realtek */
f8a08c34
HTL		 39 {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187},
40 {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B},
41 {USB_DEVICE(0x0bda, 0x8197), .driver_info = DEVICE_RTL8187B},
746db510 42 {USB_DEVICE(0x0bda, 0x8198), .driver_info = DEVICE_RTL8187B},
605bebe2 43 /* Netgear */
f8a08c34
HTL		 44 {USB_DEVICE(0x0846, 0x6100), .driver_info = DEVICE_RTL8187},
45 {USB_DEVICE(0x0846, 0x6a00), .driver_info = DEVICE_RTL8187},
fcd7cc14 46 {USB_DEVICE(0x0846, 0x4260), .driver_info = DEVICE_RTL8187B},
c3cf60a9 47 /* HP */
f8a08c34 48 {USB_DEVICE(0x03f0, 0xca02), .driver_info = DEVICE_RTL8187},
9934550d 49 /* Sitecom */
f8a08c34 50 {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187},
605bebe2
MW		 51 {}
52};
53
54MODULE_DEVICE_TABLE(usb, rtl8187_table);
55
8318d78a
JB		 56static const struct ieee80211_rate rtl818x_rates[] = {
57 { .bitrate = 10, .hw_value = 0, },
58 { .bitrate = 20, .hw_value = 1, },
59 { .bitrate = 55, .hw_value = 2, },
60 { .bitrate = 110, .hw_value = 3, },
61 { .bitrate = 60, .hw_value = 4, },
62 { .bitrate = 90, .hw_value = 5, },
63 { .bitrate = 120, .hw_value = 6, },
64 { .bitrate = 180, .hw_value = 7, },
65 { .bitrate = 240, .hw_value = 8, },
66 { .bitrate = 360, .hw_value = 9, },
67 { .bitrate = 480, .hw_value = 10, },
68 { .bitrate = 540, .hw_value = 11, },
69};
70
71static const struct ieee80211_channel rtl818x_channels[] = {
72 { .center_freq = 2412 },
73 { .center_freq = 2417 },
74 { .center_freq = 2422 },
75 { .center_freq = 2427 },
76 { .center_freq = 2432 },
77 { .center_freq = 2437 },
78 { .center_freq = 2442 },
79 { .center_freq = 2447 },
80 { .center_freq = 2452 },
81 { .center_freq = 2457 },
82 { .center_freq = 2462 },
83 { .center_freq = 2467 },
84 { .center_freq = 2472 },
85 { .center_freq = 2484 },
86};
87
4150c572
JB		 88static void rtl8187_iowrite_async_cb(struct urb *urb)
89{
90 kfree(urb->context);
91 usb_free_urb(urb);
92}
93
94static void rtl8187_iowrite_async(struct rtl8187_priv *priv, __le16 addr,
95 void *data, u16 len)
96{
97 struct usb_ctrlrequest *dr;
98 struct urb *urb;
99 struct rtl8187_async_write_data {
100 u8 data[4];
101 struct usb_ctrlrequest dr;
102 } *buf;
ea8ee240 103 int rc;
4150c572
JB		 104
105 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
106 if (!buf)
107 return;
108
109 urb = usb_alloc_urb(0, GFP_ATOMIC);
110 if (!urb) {
111 kfree(buf);
112 return;
113 }
114
115 dr = &buf->dr;
116
117 dr->bRequestType = RTL8187_REQT_WRITE;
118 dr->bRequest = RTL8187_REQ_SET_REG;
119 dr->wValue = addr;
120 dr->wIndex = 0;
121 dr->wLength = cpu_to_le16(len);
122
123 memcpy(buf, data, len);
124
125 usb_fill_control_urb(urb, priv->udev, usb_sndctrlpipe(priv->udev, 0),
126 (unsigned char *)dr, buf, len,
127 rtl8187_iowrite_async_cb, buf);
ea8ee240
ON		 128 rc = usb_submit_urb(urb, GFP_ATOMIC);
129 if (rc < 0) {
130 kfree(buf);
131 usb_free_urb(urb);
132 }
4150c572
JB		 133}
134
135static inline void rtl818x_iowrite32_async(struct rtl8187_priv *priv,
136 __le32 *addr, u32 val)
137{
138 __le32 buf = cpu_to_le32(val);
139
140 rtl8187_iowrite_async(priv, cpu_to_le16((unsigned long)addr),
141 &buf, sizeof(buf));
142}
143
605bebe2
MW		 144void rtl8187_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
145{
146 struct rtl8187_priv *priv = dev->priv;
147
148 data <<= 8;
149 data |= addr | 0x80;
150
151 rtl818x_iowrite8(priv, &priv->map->PHY[3], (data >> 24) & 0xFF);
152 rtl818x_iowrite8(priv, &priv->map->PHY[2], (data >> 16) & 0xFF);
153 rtl818x_iowrite8(priv, &priv->map->PHY[1], (data >> 8) & 0xFF);
154 rtl818x_iowrite8(priv, &priv->map->PHY[0], data & 0xFF);
155
156 msleep(1);
157}
158
159static void rtl8187_tx_cb(struct urb *urb)
160{
605bebe2 161 struct sk_buff *skb = (struct sk_buff *)urb->context;
e039fa4a
JB		 162 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
163 struct ieee80211_hw *hw = info->driver_data[0];
6f7853f3 164 struct rtl8187_priv *priv = hw->priv;
605bebe2 165
e039fa4a 166 usb_free_urb(info->driver_data[1]);
6f7853f3
HTL		 167 skb_pull(skb, priv->is_rtl8187b ? sizeof(struct rtl8187b_tx_hdr) :
168 sizeof(struct rtl8187_tx_hdr));
e039fa4a
JB		 169 memset(&info->status, 0, sizeof(info->status));
170 info->flags |= IEEE80211_TX_STAT_ACK;
171 ieee80211_tx_status_irqsafe(hw, skb);
605bebe2
MW		 172}
173
e039fa4a 174static int rtl8187_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
605bebe2
MW		 175{
176 struct rtl8187_priv *priv = dev->priv;
e039fa4a 177 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1f690d7b 178 struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
6f7853f3
HTL		 179 unsigned int ep;
180 void *buf;
605bebe2 181 struct urb *urb;
98798f48
MW		 182 __le16 rts_dur = 0;
183 u32 flags;
ea8ee240 184 int rc;
605bebe2
MW		 185
186 urb = usb_alloc_urb(0, GFP_ATOMIC);
187 if (!urb) {
188 kfree_skb(skb);
189 return 0;
190 }
191
98798f48 192 flags = skb->len;
38e3b0d8 193 flags |= RTL818X_TX_DESC_FLAG_NO_ENC;
aa68cbfb 194
e039fa4a 195 flags |= ieee80211_get_tx_rate(dev, info)->hw_value << 24;
8b7b1e05 196 if (ieee80211_has_morefrags(((struct ieee80211_hdr *)skb->data)->frame_control))
38e3b0d8 197 flags |= RTL818X_TX_DESC_FLAG_MOREFRAG;
e039fa4a 198 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
38e3b0d8 199 flags |= RTL818X_TX_DESC_FLAG_RTS;
e039fa4a 200 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
32bfd35d 201 rts_dur = ieee80211_rts_duration(dev, priv->vif,
e039fa4a
JB		 202 skb->len, info);
203 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
38e3b0d8 204 flags |= RTL818X_TX_DESC_FLAG_CTS;
e039fa4a 205 flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
aa68cbfb 206 }
98798f48 207
6f7853f3
HTL		 208 if (!priv->is_rtl8187b) {
209 struct rtl8187_tx_hdr *hdr =
210 (struct rtl8187_tx_hdr *)skb_push(skb, sizeof(*hdr));
211 hdr->flags = cpu_to_le32(flags);
212 hdr->len = 0;
213 hdr->rts_duration = rts_dur;
214 hdr->retry = cpu_to_le32(info->control.retry_limit << 8);
215 buf = hdr;
216
217 ep = 2;
218 } else {
219 /* fc needs to be calculated before skb_push() */
220 unsigned int epmap[4] = { 6, 7, 5, 4 };
221 struct ieee80211_hdr *tx_hdr =
222 (struct ieee80211_hdr *)(skb->data);
223 u16 fc = le16_to_cpu(tx_hdr->frame_control);
224
225 struct rtl8187b_tx_hdr *hdr =
226 (struct rtl8187b_tx_hdr *)skb_push(skb, sizeof(*hdr));
227 struct ieee80211_rate *txrate =
228 ieee80211_get_tx_rate(dev, info);
229 memset(hdr, 0, sizeof(*hdr));
230 hdr->flags = cpu_to_le32(flags);
231 hdr->rts_duration = rts_dur;
232 hdr->retry = cpu_to_le32(info->control.retry_limit << 8);
233 hdr->tx_duration =
234 ieee80211_generic_frame_duration(dev, priv->vif,
235 skb->len, txrate);
236 buf = hdr;
237
238 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT)
239 ep = 12;
240 else
241 ep = epmap[skb_get_queue_mapping(skb)];
242 }
605bebe2 243
1f690d7b
LF		 244 /* FIXME: The sequence that follows is needed for this driver to
245 * work with mac80211 since "mac80211: fix TX sequence numbers".
246 * As with the temporary code in rt2x00, changes will be needed
247 * to get proper sequence numbers on beacons. In addition, this
248 * patch places the sequence number in the hardware state, which
249 * limits us to a single virtual state.
250 */
251 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
252 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
253 priv->seqno += 0x10;
254 ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
255 ieee80211hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
256 }
257
e039fa4a
JB		 258 info->driver_data[0] = dev;
259 info->driver_data[1] = urb;
6f7853f3
HTL		 260
261 usb_fill_bulk_urb(urb, priv->udev, usb_sndbulkpipe(priv->udev, ep),
262 buf, skb->len, rtl8187_tx_cb, skb);
ea8ee240
ON		 263 rc = usb_submit_urb(urb, GFP_ATOMIC);
264 if (rc < 0) {
265 usb_free_urb(urb);
266 kfree_skb(skb);
267 }
605bebe2
MW		 268
269 return 0;
270}
271
272static void rtl8187_rx_cb(struct urb *urb)
273{
274 struct sk_buff *skb = (struct sk_buff *)urb->context;
275 struct rtl8187_rx_info *info = (struct rtl8187_rx_info *)skb->cb;
276 struct ieee80211_hw *dev = info->dev;
277 struct rtl8187_priv *priv = dev->priv;
605bebe2
MW		 278 struct ieee80211_rx_status rx_status = { 0 };
279 int rate, signal;
4150c572 280 u32 flags;
0ccd58fc 281 u32 quality;
605bebe2
MW		 282
283 spin_lock(&priv->rx_queue.lock);
284 if (skb->next)
285 __skb_unlink(skb, &priv->rx_queue);
286 else {
287 spin_unlock(&priv->rx_queue.lock);
288 return;
289 }
290 spin_unlock(&priv->rx_queue.lock);
291
292 if (unlikely(urb->status)) {
293 usb_free_urb(urb);
294 dev_kfree_skb_irq(skb);
295 return;
296 }
297
298 skb_put(skb, urb->actual_length);
6f7853f3
HTL		 299 if (!priv->is_rtl8187b) {
300 struct rtl8187_rx_hdr *hdr =
301 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
302 flags = le32_to_cpu(hdr->flags);
303 signal = hdr->signal & 0x7f;
304 rx_status.antenna = (hdr->signal >> 7) & 1;
6f7853f3
HTL		 305 rx_status.noise = hdr->noise;
306 rx_status.mactime = le64_to_cpu(hdr->mac_time);
6f7853f3 307 priv->quality = signal;
0ccd58fc 308 rx_status.qual = priv->quality;
6f7853f3 309 priv->noise = hdr->noise;
0ccd58fc
LF		 310 rate = (flags >> 20) & 0xF;
311 if (rate > 3) { /* OFDM rate */
312 if (signal > 90)
313 signal = 90;
314 else if (signal < 25)
315 signal = 25;
316 signal = 90 - signal;
317 } else { /* CCK rate */
318 if (signal > 95)
319 signal = 95;
320 else if (signal < 30)
321 signal = 30;
322 signal = 95 - signal;
323 }
324 rx_status.signal = signal;
325 priv->signal = signal;
6f7853f3
HTL		 326 } else {
327 struct rtl8187b_rx_hdr *hdr =
328 (typeof(hdr))(skb_tail_pointer(skb) - sizeof(*hdr));
0ccd58fc
LF		 329 /* The Realtek datasheet for the RTL8187B shows that the RX
330 * header contains the following quantities: signal quality,
331 * RSSI, AGC, the received power in dB, and the measured SNR.
332 * In testing, none of these quantities show qualitative
333 * agreement with AP signal strength, except for the AGC,
334 * which is inversely proportional to the strength of the
335 * signal. In the following, the quality and signal strength
336 * are derived from the AGC. The arbitrary scaling constants
337 * are chosen to make the results close to the values obtained
338 * for a BCM4312 using b43 as the driver. The noise is ignored
339 * for now.
340 */
6f7853f3 341 flags = le32_to_cpu(hdr->flags);
0ccd58fc
LF		 342 quality = 170 - hdr->agc;
343 if (quality > 100)
344 quality = 100;
345 signal = 14 - hdr->agc / 2;
346 rx_status.qual = quality;
347 priv->quality = quality;
348 rx_status.signal = signal;
349 priv->signal = signal;
350 rx_status.antenna = (hdr->rssi >> 7) & 1;
6f7853f3 351 rx_status.mactime = le64_to_cpu(hdr->mac_time);
0ccd58fc 352 rate = (flags >> 20) & 0xF;
6f7853f3 353 }
605bebe2 354
6f7853f3 355 skb_trim(skb, flags & 0x0FFF);
8318d78a
JB		 356 rx_status.rate_idx = rate;
357 rx_status.freq = dev->conf.channel->center_freq;
358 rx_status.band = dev->conf.channel->band;
03bffc13 359 rx_status.flag |= RX_FLAG_TSFT;
38e3b0d8 360 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
4150c572 361 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
605bebe2
MW		 362 ieee80211_rx_irqsafe(dev, skb, &rx_status);
363
364 skb = dev_alloc_skb(RTL8187_MAX_RX);
365 if (unlikely(!skb)) {
366 usb_free_urb(urb);
367 /* TODO check rx queue length and refill *somewhere* */
368 return;
369 }
370
371 info = (struct rtl8187_rx_info *)skb->cb;
372 info->urb = urb;
373 info->dev = dev;
374 urb->transfer_buffer = skb_tail_pointer(skb);
375 urb->context = skb;
376 skb_queue_tail(&priv->rx_queue, skb);
377
378 usb_submit_urb(urb, GFP_ATOMIC);
379}
380
381static int rtl8187_init_urbs(struct ieee80211_hw *dev)
382{
383 struct rtl8187_priv *priv = dev->priv;
384 struct urb *entry;
385 struct sk_buff *skb;
386 struct rtl8187_rx_info *info;
387
388 while (skb_queue_len(&priv->rx_queue) < 8) {
389 skb = __dev_alloc_skb(RTL8187_MAX_RX, GFP_KERNEL);
390 if (!skb)
391 break;
392 entry = usb_alloc_urb(0, GFP_KERNEL);
393 if (!entry) {
394 kfree_skb(skb);
395 break;
396 }
397 usb_fill_bulk_urb(entry, priv->udev,
6f7853f3
HTL		 398 usb_rcvbulkpipe(priv->udev,
399 priv->is_rtl8187b ? 3 : 1),
605bebe2
MW		 400 skb_tail_pointer(skb),
401 RTL8187_MAX_RX, rtl8187_rx_cb, skb);
402 info = (struct rtl8187_rx_info *)skb->cb;
403 info->urb = entry;
404 info->dev = dev;
405 skb_queue_tail(&priv->rx_queue, skb);
406 usb_submit_urb(entry, GFP_KERNEL);
407 }
408
409 return 0;
410}
411
f8a08c34 412static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
605bebe2
MW		 413{
414 struct rtl8187_priv *priv = dev->priv;
415 u8 reg;
416 int i;
417
605bebe2
MW		 418 reg = rtl818x_ioread8(priv, &priv->map->CMD);
419 reg &= (1 << 1);
420 reg |= RTL818X_CMD_RESET;
421 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
422
423 i = 10;
424 do {
425 msleep(2);
426 if (!(rtl818x_ioread8(priv, &priv->map->CMD) &
427 RTL818X_CMD_RESET))
428 break;
429 } while (--i);
430
431 if (!i) {
432 printk(KERN_ERR "%s: Reset timeout!\n", wiphy_name(dev->wiphy));
433 return -ETIMEDOUT;
434 }
435
436 /* reload registers from eeprom */
437 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
438
439 i = 10;
440 do {
441 msleep(4);
442 if (!(rtl818x_ioread8(priv, &priv->map->EEPROM_CMD) &
443 RTL818X_EEPROM_CMD_CONFIG))
444 break;
445 } while (--i);
446
447 if (!i) {
448 printk(KERN_ERR "%s: eeprom reset timeout!\n",
449 wiphy_name(dev->wiphy));
450 return -ETIMEDOUT;
451 }
452
f8a08c34
HTL		 453 return 0;
454}
455
456static int rtl8187_init_hw(struct ieee80211_hw *dev)
457{
458 struct rtl8187_priv *priv = dev->priv;
459 u8 reg;
460 int res;
461
462 /* reset */
463 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
464 RTL818X_EEPROM_CMD_CONFIG);
465 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
466 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
467 RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 468 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
469 RTL8187_RTL8225_ANAPARAM_ON);
470 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
471 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 472 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
473 ~RTL818X_CONFIG3_ANAPARAM_WRITE);
474 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
475 RTL818X_EEPROM_CMD_NORMAL);
476
477 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
478
479 msleep(200);
480 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x10);
481 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x11);
482 rtl818x_iowrite8(priv, (u8 *)0xFE18, 0x00);
483 msleep(200);
484
485 res = rtl8187_cmd_reset(dev);
486 if (res)
487 return res;
488
605bebe2
MW		 489 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
490 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
f8a08c34
HTL		 491 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
492 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
4ece16a1
HRK		 493 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
494 RTL8187_RTL8225_ANAPARAM_ON);
495 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
496 RTL8187_RTL8225_ANAPARAM2_ON);
f8a08c34
HTL		 497 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
498 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
605bebe2
MW		 499 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
500
501 /* setup card */
502 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
503 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
504
505 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
506 rtl818x_iowrite8(priv, &priv->map->GPIO, 1);
507 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
508
509 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
605bebe2
MW		 510
511 rtl818x_iowrite16(priv, (__le16 *)0xFFF4, 0xFFFF);
512 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
513 reg &= 0x3F;
514 reg |= 0x80;
515 rtl818x_iowrite8(priv, &priv->map->CONFIG1, reg);
516
517 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
518
519 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
520 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
521 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
522
523 // TODO: set RESP_RATE and BRSR properly
524 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
525 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
526
527 /* host_usb_init */
528 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
529 rtl818x_iowrite8(priv, &priv->map->GPIO, 0);
530 reg = rtl818x_ioread8(priv, (u8 *)0xFE53);
531 rtl818x_iowrite8(priv, (u8 *)0xFE53, reg | (1 << 7));
532 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, (4 << 8));
533 rtl818x_iowrite8(priv, &priv->map->GPIO, 0x20);
534 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, 0);
535 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x80);
536 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x80);
537 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x80);
538 msleep(100);
539
540 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x000a8008);
541 rtl818x_iowrite16(priv, &priv->map->BRSR, 0xFFFF);
542 rtl818x_iowrite32(priv, &priv->map->RF_PARA, 0x00100044);
f8a08c34
HTL		 543 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
544 RTL818X_EEPROM_CMD_CONFIG);
605bebe2 545 rtl818x_iowrite8(priv, &priv->map->CONFIG3, 0x44);
f8a08c34
HTL		 546 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
547 RTL818X_EEPROM_CMD_NORMAL);
605bebe2
MW		 548 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FF7);
549 msleep(100);
550
f6532111 551 priv->rf->init(dev);
605bebe2
MW		 552
553 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
f6532111
MW		 554 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
555 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 556 rtl818x_iowrite16(priv, (__le16 *)0xFFFE, 0x10);
557 rtl818x_iowrite8(priv, &priv->map->TALLY_SEL, 0x80);
558 rtl818x_iowrite8(priv, (u8 *)0xFFFF, 0x60);
f6532111 559 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 560
561 return 0;
562}
563
f8a08c34
HTL		 564static const u8 rtl8187b_reg_table[][3] = {
565 {0xF0, 0x32, 0}, {0xF1, 0x32, 0}, {0xF2, 0x00, 0}, {0xF3, 0x00, 0},
566 {0xF4, 0x32, 0}, {0xF5, 0x43, 0}, {0xF6, 0x00, 0}, {0xF7, 0x00, 0},
567 {0xF8, 0x46, 0}, {0xF9, 0xA4, 0}, {0xFA, 0x00, 0}, {0xFB, 0x00, 0},
568 {0xFC, 0x96, 0}, {0xFD, 0xA4, 0}, {0xFE, 0x00, 0}, {0xFF, 0x00, 0},
569
570 {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
571 {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
572 {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
573 {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
574 {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
575 {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
576
577 {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
578 {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
579 {0x27, 0x8D, 2}, {0x4D, 0x08, 2}, {0x50, 0x05, 2}, {0x51, 0xF5, 2},
580 {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
581 {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
582 {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
583 {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
584 {0x73, 0x9A, 2},
585
586 {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
587 {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
588 {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
589 {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
590 {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x91, 0x03, 0},
591
592 {0x4C, 0x00, 2}, {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0},
593 {0x8E, 0x08, 0}, {0x8F, 0x00, 0}
594};
595
596static int rtl8187b_init_hw(struct ieee80211_hw *dev)
597{
598 struct rtl8187_priv *priv = dev->priv;
599 int res, i;
600 u8 reg;
601
602 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
603 RTL818X_EEPROM_CMD_CONFIG);
604
605 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
606 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
607 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
4ece16a1
HRK		 608 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
609 RTL8187B_RTL8225_ANAPARAM2_ON);
610 rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
611 RTL8187B_RTL8225_ANAPARAM_ON);
612 rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
613 RTL8187B_RTL8225_ANAPARAM3_ON);
f8a08c34
HTL		 614
615 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
616 reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
617 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
618 rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
619
620 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
621 reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
622 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
623
624 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
625 RTL818X_EEPROM_CMD_NORMAL);
626
627 res = rtl8187_cmd_reset(dev);
628 if (res)
629 return res;
630
631 rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
632 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
633 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
634 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
635 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
636 reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
637 RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
638 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
639
640 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
641 reg = rtl818x_ioread8(priv, &priv->map->RATE_FALLBACK);
642 reg |= RTL818X_RATE_FALLBACK_ENABLE;
643 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, reg);
644
645 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
646 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
647 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
648
649 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
650 RTL818X_EEPROM_CMD_CONFIG);
651 reg = rtl818x_ioread8(priv, &priv->map->CONFIG1);
652 rtl818x_iowrite8(priv, &priv->map->CONFIG1, (reg & 0x3F) | 0x80);
653 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
654 RTL818X_EEPROM_CMD_NORMAL);
655
656 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
657 for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) {
658 rtl818x_iowrite8_idx(priv,
659 (u8 *)(uintptr_t)
660 (rtl8187b_reg_table[i][0] | 0xFF00),
661 rtl8187b_reg_table[i][1],
662 rtl8187b_reg_table[i][2]);
663 }
664
665 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
666 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
667
668 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1);
669 rtl818x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1);
670 rtl818x_iowrite8_idx(priv, (u8 *)0xFFF8, 0, 1);
671
672 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
673
674 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
675
676 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
677 RTL818X_EEPROM_CMD_CONFIG);
678 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
679 reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
680 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
681 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
682 RTL818X_EEPROM_CMD_NORMAL);
683
684 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
685 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
686 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
687 msleep(1100);
688
689 priv->rf->init(dev);
690
691 reg = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE;
692 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
693 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
694
695 rtl818x_iowrite8(priv, (u8 *)0xFE41, 0xF4);
696 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x00);
697 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
698 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
699 rtl818x_iowrite8(priv, (u8 *)0xFE40, 0x0F);
700 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x00);
701 rtl818x_iowrite8(priv, (u8 *)0xFE42, 0x01);
702
703 reg = rtl818x_ioread8(priv, (u8 *)0xFFDB);
704 rtl818x_iowrite8(priv, (u8 *)0xFFDB, reg | (1 << 2));
705 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3);
706 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3);
707 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3);
708 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3);
709 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3);
710 rtl818x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3);
711 rtl818x_iowrite8(priv, (u8 *)0xFF61, 0);
712 rtl818x_iowrite8_idx(priv, (u8 *)0xFF80, 0x0F, 1);
713 rtl818x_iowrite8_idx(priv, (u8 *)0xFF83, 0x03, 1);
714 rtl818x_iowrite8(priv, (u8 *)0xFFDA, 0x10);
715 rtl818x_iowrite8_idx(priv, (u8 *)0xFF4D, 0x08, 2);
716
717 rtl818x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B);
718
719 rtl818x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1);
720
721 return 0;
722}
723
4150c572 724static int rtl8187_start(struct ieee80211_hw *dev)
605bebe2
MW		 725{
726 struct rtl8187_priv *priv = dev->priv;
727 u32 reg;
728 int ret;
729
f8a08c34
HTL		 730 ret = (!priv->is_rtl8187b) ? rtl8187_init_hw(dev) :
731 rtl8187b_init_hw(dev);
605bebe2
MW		 732 if (ret)
733 return ret;
734
7dcdd073 735 mutex_lock(&priv->conf_mutex);
f8a08c34
HTL		 736 if (priv->is_rtl8187b) {
737 reg = RTL818X_RX_CONF_MGMT |
738 RTL818X_RX_CONF_DATA |
739 RTL818X_RX_CONF_BROADCAST |
740 RTL818X_RX_CONF_NICMAC |
741 RTL818X_RX_CONF_BSSID |
742 (7 << 13 /* RX FIFO threshold NONE */) |
743 (7 << 10 /* MAX RX DMA */) |
744 RTL818X_RX_CONF_RX_AUTORESETPHY |
745 RTL818X_RX_CONF_ONLYERLPKT |
746 RTL818X_RX_CONF_MULTICAST;
747 priv->rx_conf = reg;
748 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
749
750 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
751 RTL818X_TX_CONF_HW_SEQNUM |
752 RTL818X_TX_CONF_DISREQQSIZE |
753 (7 << 8 /* short retry limit */) |
754 (7 << 0 /* long retry limit */) |
755 (7 << 21 /* MAX TX DMA */));
756 rtl8187_init_urbs(dev);
7dcdd073 757 mutex_unlock(&priv->conf_mutex);
f8a08c34
HTL		 758 return 0;
759 }
760
605bebe2
MW		 761 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
762
2fe14263
MW		 763 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
764 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
765
605bebe2
MW		 766 rtl8187_init_urbs(dev);
767
768 reg = RTL818X_RX_CONF_ONLYERLPKT |
769 RTL818X_RX_CONF_RX_AUTORESETPHY |
770 RTL818X_RX_CONF_BSSID |
771 RTL818X_RX_CONF_MGMT |
605bebe2
MW		 772 RTL818X_RX_CONF_DATA |
773 (7 << 13 /* RX FIFO threshold NONE */) |
774 (7 << 10 /* MAX RX DMA */) |
775 RTL818X_RX_CONF_BROADCAST |
605bebe2 776 RTL818X_RX_CONF_NICMAC;
605bebe2 777
4150c572 778 priv->rx_conf = reg;
605bebe2
MW		 779 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
780
781 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
782 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
783 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
784 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
785
786 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
787 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
788 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
789 reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
790 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
791
792 reg = RTL818X_TX_CONF_CW_MIN |
793 (7 << 21 /* MAX TX DMA */) |
794 RTL818X_TX_CONF_NO_ICV;
795 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
796
797 reg = rtl818x_ioread8(priv, &priv->map->CMD);
798 reg |= RTL818X_CMD_TX_ENABLE;
799 reg |= RTL818X_CMD_RX_ENABLE;
800 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
7dcdd073 801 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 802
803 return 0;
804}
805
4150c572 806static void rtl8187_stop(struct ieee80211_hw *dev)
605bebe2
MW		 807{
808 struct rtl8187_priv *priv = dev->priv;
809 struct rtl8187_rx_info *info;
810 struct sk_buff *skb;
811 u32 reg;
812
7dcdd073 813 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 814 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
815
816 reg = rtl818x_ioread8(priv, &priv->map->CMD);
817 reg &= ~RTL818X_CMD_TX_ENABLE;
818 reg &= ~RTL818X_CMD_RX_ENABLE;
819 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
820
f6532111 821 priv->rf->stop(dev);
605bebe2
MW		 822
823 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
824 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
825 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
826 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
827
828 while ((skb = skb_dequeue(&priv->rx_queue))) {
829 info = (struct rtl8187_rx_info *)skb->cb;
830 usb_kill_urb(info->urb);
831 kfree_skb(skb);
832 }
7dcdd073 833 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 834}
835
836static int rtl8187_add_interface(struct ieee80211_hw *dev,
837 struct ieee80211_if_init_conf *conf)
838{
839 struct rtl8187_priv *priv = dev->priv;
4150c572 840 int i;
605bebe2 841
05c914fe 842 if (priv->mode != NL80211_IFTYPE_MONITOR)
4150c572 843 return -EOPNOTSUPP;
605bebe2
MW		 844
845 switch (conf->type) {
05c914fe 846 case NL80211_IFTYPE_STATION:
605bebe2
MW		 847 priv->mode = conf->type;
848 break;
849 default:
850 return -EOPNOTSUPP;
851 }
852
7dcdd073 853 mutex_lock(&priv->conf_mutex);
aa979a6a
HRK		 854 priv->vif = conf->vif;
855
4150c572
JB		 856 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
857 for (i = 0; i < ETH_ALEN; i++)
858 rtl818x_iowrite8(priv, &priv->map->MAC[i],
859 ((u8 *)conf->mac_addr)[i]);
860 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
605bebe2 861
7dcdd073 862 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 863 return 0;
864}
865
866static void rtl8187_remove_interface(struct ieee80211_hw *dev,
867 struct ieee80211_if_init_conf *conf)
868{
869 struct rtl8187_priv *priv = dev->priv;
7dcdd073 870 mutex_lock(&priv->conf_mutex);
05c914fe 871 priv->mode = NL80211_IFTYPE_MONITOR;
aa979a6a 872 priv->vif = NULL;
7dcdd073 873 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 874}
875
876static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
877{
878 struct rtl8187_priv *priv = dev->priv;
f6532111
MW		 879 u32 reg;
880
7dcdd073 881 mutex_lock(&priv->conf_mutex);
f6532111
MW		 882 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
883 /* Enable TX loopback on MAC level to avoid TX during channel
884 * changes, as this has be seen to causes problems and the
885 * card will stop work until next reset
886 */
887 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
888 reg | RTL818X_TX_CONF_LOOPBACK_MAC);
889 msleep(10);
890 priv->rf->set_chan(dev, conf);
891 msleep(10);
892 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
605bebe2 893
6f7853f3
HTL		 894 if (!priv->is_rtl8187b) {
895 rtl818x_iowrite8(priv, &priv->map->SIFS, 0x22);
896
897 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
898 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x9);
899 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x14);
900 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x14);
901 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0x73);
902 } else {
903 rtl818x_iowrite8(priv, &priv->map->SLOT, 0x14);
904 rtl818x_iowrite8(priv, &priv->map->DIFS, 0x24);
905 rtl818x_iowrite8(priv, &priv->map->EIFS, 91 - 0x24);
906 rtl818x_iowrite8(priv, &priv->map->CW_VAL, 0xa5);
907 }
605bebe2
MW		 908 }
909
910 rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
911 rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100);
912 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
913 rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100);
7dcdd073 914 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 915 return 0;
916}
917
32bfd35d
JB		 918static int rtl8187_config_interface(struct ieee80211_hw *dev,
919 struct ieee80211_vif *vif,
605bebe2
MW		 920 struct ieee80211_if_conf *conf)
921{
922 struct rtl8187_priv *priv = dev->priv;
923 int i;
6f7853f3 924 u8 reg;
605bebe2 925
7dcdd073 926 mutex_lock(&priv->conf_mutex);
605bebe2
MW		 927 for (i = 0; i < ETH_ALEN; i++)
928 rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]);
929
6f7853f3
HTL		 930 if (is_valid_ether_addr(conf->bssid)) {
931 reg = RTL818X_MSR_INFRA;
932 if (priv->is_rtl8187b)
933 reg |= RTL818X_MSR_ENEDCA;
934 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
935 } else {
936 reg = RTL818X_MSR_NO_LINK;
937 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
938 }
605bebe2 939
7dcdd073 940 mutex_unlock(&priv->conf_mutex);
605bebe2
MW		 941 return 0;
942}
943
4150c572
JB		 944static void rtl8187_configure_filter(struct ieee80211_hw *dev,
945 unsigned int changed_flags,
946 unsigned int *total_flags,
2fe14263 947 int mc_count, struct dev_addr_list *mclist)
4150c572
JB		 948{
949 struct rtl8187_priv *priv = dev->priv;
950
4150c572
JB		 951 if (changed_flags & FIF_FCSFAIL)
952 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
953 if (changed_flags & FIF_CONTROL)
954 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
955 if (changed_flags & FIF_OTHER_BSS)
956 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
2fe14263 957 if (*total_flags & FIF_ALLMULTI || mc_count > 0)
4150c572 958 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
2fe14263
MW		 959 else
960 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
961
962 *total_flags = 0;
4150c572 963
4150c572
JB		 964 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
965 *total_flags |= FIF_FCSFAIL;
966 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
967 *total_flags |= FIF_CONTROL;
968 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
969 *total_flags |= FIF_OTHER_BSS;
2fe14263
MW		 970 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
971 *total_flags |= FIF_ALLMULTI;
4150c572
JB		 972
973 rtl818x_iowrite32_async(priv, &priv->map->RX_CONF, priv->rx_conf);
974}
975
605bebe2
MW		 976static const struct ieee80211_ops rtl8187_ops = {
977 .tx = rtl8187_tx,
4150c572 978 .start = rtl8187_start,
605bebe2
MW		 979 .stop = rtl8187_stop,
980 .add_interface = rtl8187_add_interface,
981 .remove_interface = rtl8187_remove_interface,
982 .config = rtl8187_config,
983 .config_interface = rtl8187_config_interface,
4150c572 984 .configure_filter = rtl8187_configure_filter,
605bebe2
MW		 985};
986
987static void rtl8187_eeprom_register_read(struct eeprom_93cx6 *eeprom)
988{
989 struct ieee80211_hw *dev = eeprom->data;
990 struct rtl8187_priv *priv = dev->priv;
991 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
992
993 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
994 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
995 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
996 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
997}
998
999static void rtl8187_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1000{
1001 struct ieee80211_hw *dev = eeprom->data;
1002 struct rtl8187_priv *priv = dev->priv;
1003 u8 reg = RTL818X_EEPROM_CMD_PROGRAM;
1004
1005 if (eeprom->reg_data_in)
1006 reg |= RTL818X_EEPROM_CMD_WRITE;
1007 if (eeprom->reg_data_out)
1008 reg |= RTL818X_EEPROM_CMD_READ;
1009 if (eeprom->reg_data_clock)
1010 reg |= RTL818X_EEPROM_CMD_CK;
1011 if (eeprom->reg_chip_select)
1012 reg |= RTL818X_EEPROM_CMD_CS;
1013
1014 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1015 udelay(10);
1016}
1017
1018static int __devinit rtl8187_probe(struct usb_interface *intf,
1019 const struct usb_device_id *id)
1020{
1021 struct usb_device *udev = interface_to_usbdev(intf);
1022 struct ieee80211_hw *dev;
1023 struct rtl8187_priv *priv;
1024 struct eeprom_93cx6 eeprom;
1025 struct ieee80211_channel *channel;
6f7853f3 1026 const char *chip_name;
605bebe2
MW		 1027 u16 txpwr, reg;
1028 int err, i;
0795af57 1029 DECLARE_MAC_BUF(mac);
605bebe2
MW		 1030
1031 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8187_ops);
1032 if (!dev) {
1033 printk(KERN_ERR "rtl8187: ieee80211 alloc failed\n");
1034 return -ENOMEM;
1035 }
1036
1037 priv = dev->priv;
0e25b4ef 1038 priv->is_rtl8187b = (id->driver_info == DEVICE_RTL8187B);
605bebe2
MW		 1039
1040 SET_IEEE80211_DEV(dev, &intf->dev);
1041 usb_set_intfdata(intf, dev);
1042 priv->udev = udev;
1043
1044 usb_get_dev(udev);
1045
1046 skb_queue_head_init(&priv->rx_queue);
8318d78a
JB		 1047
1048 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1049 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1050
605bebe2
MW		 1051 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1052 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1053 priv->map = (struct rtl818x_csr *)0xFF00;
8318d78a
JB		 1054
1055 priv->band.band = IEEE80211_BAND_2GHZ;
1056 priv->band.channels = priv->channels;
1057 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1058 priv->band.bitrates = priv->rates;
1059 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1060 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1061
1062
05c914fe 1063 priv->mode = NL80211_IFTYPE_MONITOR;
605bebe2 1064 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
0ccd58fc 1065 IEEE80211_HW_RX_INCLUDES_FCS;
605bebe2 1066
605bebe2
MW		 1067 eeprom.data = dev;
1068 eeprom.register_read = rtl8187_eeprom_register_read;
1069 eeprom.register_write = rtl8187_eeprom_register_write;
1070 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1071 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1072 else
1073 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1074
1075 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1076 udelay(10);
1077
1078 eeprom_93cx6_multiread(&eeprom, RTL8187_EEPROM_MAC_ADDR,
1079 (__le16 __force *)dev->wiphy->perm_addr, 3);
1080 if (!is_valid_ether_addr(dev->wiphy->perm_addr)) {
1081 printk(KERN_WARNING "rtl8187: Invalid hwaddr! Using randomly "
1082 "generated MAC address\n");
1083 random_ether_addr(dev->wiphy->perm_addr);
1084 }
1085
1086 channel = priv->channels;
1087 for (i = 0; i < 3; i++) {
1088 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_1 + i,
1089 &txpwr);
8318d78a
JB		 1090 (*channel++).hw_value = txpwr & 0xFF;
1091 (*channel++).hw_value = txpwr >> 8;
605bebe2
MW		 1092 }
1093 for (i = 0; i < 2; i++) {
1094 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_4 + i,
1095 &txpwr);
8318d78a
JB		 1096 (*channel++).hw_value = txpwr & 0xFF;
1097 (*channel++).hw_value = txpwr >> 8;
605bebe2 1098 }
605bebe2
MW		 1099
1100 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_BASE,
1101 &priv->txpwr_base);
1102
f6532111
MW		 1103 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT) & ~1;
1104 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
605bebe2
MW		 1105 /* 0 means asic B-cut, we should use SW 3 wire
1106 * bit-by-bit banging for radio. 1 means we can use
1107 * USB specific request to write radio registers */
1108 priv->asic_rev = rtl818x_ioread8(priv, (u8 *)0xFFFE) & 0x3;
f6532111 1109 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
605bebe2
MW		 1110 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1111
6f7853f3
HTL		 1112 if (!priv->is_rtl8187b) {
1113 u32 reg32;
1114 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1115 reg32 &= RTL818X_TX_CONF_HWVER_MASK;
1116 switch (reg32) {
0e25b4ef
LF		 1117 case RTL818X_TX_CONF_R8187vD_B:
1118 /* Some RTL8187B devices have a USB ID of 0x8187
1119 * detect them here */
1120 chip_name = "RTL8187BvB(early)";
1121 priv->is_rtl8187b = 1;
1122 priv->hw_rev = RTL8187BvB;
1123 break;
1124 case RTL818X_TX_CONF_R8187vD:
6f7853f3
HTL		 1125 chip_name = "RTL8187vD";
1126 break;
1127 default:
1128 chip_name = "RTL8187vB (default)";
1129 }
1130 } else {
6f7853f3
HTL		 1131 /*
1132 * Force USB request to write radio registers for 8187B, Realtek
1133 * only uses it in their sources
1134 */
1135 /*if (priv->asic_rev == 0) {
1136 printk(KERN_WARNING "rtl8187: Forcing use of USB "
1137 "requests to write to radio registers\n");
1138 priv->asic_rev = 1;
1139 }*/
1140 switch (rtl818x_ioread8(priv, (u8 *)0xFFE1)) {
1141 case RTL818X_R8187B_B:
1142 chip_name = "RTL8187BvB";
1143 priv->hw_rev = RTL8187BvB;
1144 break;
1145 case RTL818X_R8187B_D:
1146 chip_name = "RTL8187BvD";
1147 priv->hw_rev = RTL8187BvD;
1148 break;
1149 case RTL818X_R8187B_E:
1150 chip_name = "RTL8187BvE";
1151 priv->hw_rev = RTL8187BvE;
1152 break;
1153 default:
1154 chip_name = "RTL8187BvB (default)";
1155 priv->hw_rev = RTL8187BvB;
1156 }
1157 }
1158
0e25b4ef
LF		 1159 if (!priv->is_rtl8187b) {
1160 for (i = 0; i < 2; i++) {
1161 eeprom_93cx6_read(&eeprom,
1162 RTL8187_EEPROM_TXPWR_CHAN_6 + i,
1163 &txpwr);
1164 (*channel++).hw_value = txpwr & 0xFF;
1165 (*channel++).hw_value = txpwr >> 8;
1166 }
1167 } else {
1168 eeprom_93cx6_read(&eeprom, RTL8187_EEPROM_TXPWR_CHAN_6,
1169 &txpwr);
1170 (*channel++).hw_value = txpwr & 0xFF;
1171
1172 eeprom_93cx6_read(&eeprom, 0x0A, &txpwr);
1173 (*channel++).hw_value = txpwr & 0xFF;
1174
1175 eeprom_93cx6_read(&eeprom, 0x1C, &txpwr);
1176 (*channel++).hw_value = txpwr & 0xFF;
1177 (*channel++).hw_value = txpwr >> 8;
1178 }
1179
0ccd58fc 1180 if (priv->is_rtl8187b) {
0e25b4ef
LF		 1181 printk(KERN_WARNING "rtl8187: 8187B chip detected. Support "
1182 "is EXPERIMENTAL, and could damage your\n"
1183 " hardware, use at your own risk\n");
0ccd58fc
LF		 1184 dev->flags |= IEEE80211_HW_SIGNAL_DBM;
1185 } else {
1186 dev->flags |= IEEE80211_HW_SIGNAL_UNSPEC;
1187 dev->max_signal = 65;
1188 }
1189
f59ac048
LR		 1190 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1191
0e25b4ef
LF		 1192 if ((id->driver_info == DEVICE_RTL8187) && priv->is_rtl8187b)
1193 printk(KERN_INFO "rtl8187: inconsistency between id with OEM"
1194 " info!\n");
1195
f6532111 1196 priv->rf = rtl8187_detect_rf(dev);
0e25b4ef
LF		 1197 dev->extra_tx_headroom = (!priv->is_rtl8187b) ?
1198 sizeof(struct rtl8187_tx_hdr) :
1199 sizeof(struct rtl8187b_tx_hdr);
1200 if (!priv->is_rtl8187b)
1201 dev->queues = 1;
1202 else
1203 dev->queues = 4;
605bebe2
MW		 1204
1205 err = ieee80211_register_hw(dev);
1206 if (err) {
1207 printk(KERN_ERR "rtl8187: Cannot register device\n");
1208 goto err_free_dev;
1209 }
7dcdd073 1210 mutex_init(&priv->conf_mutex);
605bebe2 1211
6f7853f3 1212 printk(KERN_INFO "%s: hwaddr %s, %s V%d + %s\n",
0795af57 1213 wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
6f7853f3 1214 chip_name, priv->asic_rev, priv->rf->name);
605bebe2
MW		 1215
1216 return 0;
1217
1218 err_free_dev:
1219 ieee80211_free_hw(dev);
1220 usb_set_intfdata(intf, NULL);
1221 usb_put_dev(udev);
1222 return err;
1223}
1224
1225static void __devexit rtl8187_disconnect(struct usb_interface *intf)
1226{
1227 struct ieee80211_hw *dev = usb_get_intfdata(intf);
1228 struct rtl8187_priv *priv;
1229
1230 if (!dev)
1231 return;
1232
1233 ieee80211_unregister_hw(dev);
1234
1235 priv = dev->priv;
1236 usb_put_dev(interface_to_usbdev(intf));
1237 ieee80211_free_hw(dev);
1238}
1239
1240static struct usb_driver rtl8187_driver = {
1241 .name = KBUILD_MODNAME,
1242 .id_table = rtl8187_table,
1243 .probe = rtl8187_probe,
500c1197 1244 .disconnect = __devexit_p(rtl8187_disconnect),
605bebe2
MW		 1245};
1246
1247static int __init rtl8187_init(void)
1248{
1249 return usb_register(&rtl8187_driver);
1250}
1251
1252static void __exit rtl8187_exit(void)
1253{
1254 usb_deregister(&rtl8187_driver);
1255}
1256
1257module_init(rtl8187_init);
1258module_exit(rtl8187_exit);
Linux 6.x block layer and io_uring tree(s)