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f6532111 MW |
1 | |
2 | /* | |
3 | * Linux device driver for RTL8180 / RTL8185 | |
4 | * | |
5 | * Copyright 2007 Michael Wu <flamingice@sourmilk.net> | |
6 | * Copyright 2007 Andrea Merello <andreamrl@tiscali.it> | |
7 | * | |
8 | * Based on the r8180 driver, which is: | |
9 | * Copyright 2004-2005 Andrea Merello <andreamrl@tiscali.it>, et al. | |
10 | * | |
11 | * Thanks to Realtek for their support! | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/pci.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <linux/eeprom_93cx6.h> | |
23 | #include <net/mac80211.h> | |
24 | ||
25 | #include "rtl8180.h" | |
26 | #include "rtl8180_rtl8225.h" | |
27 | #include "rtl8180_sa2400.h" | |
28 | #include "rtl8180_max2820.h" | |
29 | #include "rtl8180_grf5101.h" | |
30 | ||
31 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
32 | MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>"); | |
33 | MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver"); | |
34 | MODULE_LICENSE("GPL"); | |
35 | ||
36 | static struct pci_device_id rtl8180_table[] __devinitdata = { | |
37 | /* rtl8185 */ | |
38 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) }, | |
4fcc5470 | 39 | { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) }, |
f6532111 MW |
40 | { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) }, |
41 | ||
42 | /* rtl8180 */ | |
43 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) }, | |
44 | { PCI_DEVICE(0x1799, 0x6001) }, | |
45 | { PCI_DEVICE(0x1799, 0x6020) }, | |
46 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) }, | |
47 | { } | |
48 | }; | |
49 | ||
50 | MODULE_DEVICE_TABLE(pci, rtl8180_table); | |
51 | ||
8318d78a JB |
52 | static const struct ieee80211_rate rtl818x_rates[] = { |
53 | { .bitrate = 10, .hw_value = 0, }, | |
54 | { .bitrate = 20, .hw_value = 1, }, | |
55 | { .bitrate = 55, .hw_value = 2, }, | |
56 | { .bitrate = 110, .hw_value = 3, }, | |
57 | { .bitrate = 60, .hw_value = 4, }, | |
58 | { .bitrate = 90, .hw_value = 5, }, | |
59 | { .bitrate = 120, .hw_value = 6, }, | |
60 | { .bitrate = 180, .hw_value = 7, }, | |
61 | { .bitrate = 240, .hw_value = 8, }, | |
62 | { .bitrate = 360, .hw_value = 9, }, | |
63 | { .bitrate = 480, .hw_value = 10, }, | |
64 | { .bitrate = 540, .hw_value = 11, }, | |
65 | }; | |
66 | ||
67 | static const struct ieee80211_channel rtl818x_channels[] = { | |
68 | { .center_freq = 2412 }, | |
69 | { .center_freq = 2417 }, | |
70 | { .center_freq = 2422 }, | |
71 | { .center_freq = 2427 }, | |
72 | { .center_freq = 2432 }, | |
73 | { .center_freq = 2437 }, | |
74 | { .center_freq = 2442 }, | |
75 | { .center_freq = 2447 }, | |
76 | { .center_freq = 2452 }, | |
77 | { .center_freq = 2457 }, | |
78 | { .center_freq = 2462 }, | |
79 | { .center_freq = 2467 }, | |
80 | { .center_freq = 2472 }, | |
81 | { .center_freq = 2484 }, | |
82 | }; | |
83 | ||
84 | ||
85 | ||
86 | ||
f6532111 MW |
87 | void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data) |
88 | { | |
89 | struct rtl8180_priv *priv = dev->priv; | |
90 | int i = 10; | |
91 | u32 buf; | |
92 | ||
93 | buf = (data << 8) | addr; | |
94 | ||
95 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80); | |
96 | while (i--) { | |
97 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf); | |
98 | if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF)) | |
99 | return; | |
100 | } | |
101 | } | |
102 | ||
103 | static void rtl8180_handle_rx(struct ieee80211_hw *dev) | |
104 | { | |
105 | struct rtl8180_priv *priv = dev->priv; | |
106 | unsigned int count = 32; | |
107 | ||
108 | while (count--) { | |
109 | struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx]; | |
110 | struct sk_buff *skb = priv->rx_buf[priv->rx_idx]; | |
111 | u32 flags = le32_to_cpu(entry->flags); | |
112 | ||
38e3b0d8 | 113 | if (flags & RTL818X_RX_DESC_FLAG_OWN) |
f6532111 MW |
114 | return; |
115 | ||
38e3b0d8 HRK |
116 | if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL | |
117 | RTL818X_RX_DESC_FLAG_FOF | | |
118 | RTL818X_RX_DESC_FLAG_RX_ERR))) | |
f6532111 MW |
119 | goto done; |
120 | else { | |
121 | u32 flags2 = le32_to_cpu(entry->flags2); | |
122 | struct ieee80211_rx_status rx_status = {0}; | |
123 | struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE); | |
124 | ||
125 | if (unlikely(!new_skb)) | |
126 | goto done; | |
127 | ||
128 | pci_unmap_single(priv->pdev, | |
129 | *((dma_addr_t *)skb->cb), | |
130 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
131 | skb_put(skb, flags & 0xFFF); | |
132 | ||
133 | rx_status.antenna = (flags2 >> 15) & 1; | |
134 | /* TODO: improve signal/rssi reporting */ | |
566bfe5a BR |
135 | rx_status.qual = flags2 & 0xFF; |
136 | rx_status.signal = (flags2 >> 8) & 0x7F; | |
8318d78a JB |
137 | /* XXX: is this correct? */ |
138 | rx_status.rate_idx = (flags >> 20) & 0xF; | |
139 | rx_status.freq = dev->conf.channel->center_freq; | |
140 | rx_status.band = dev->conf.channel->band; | |
f6532111 MW |
141 | rx_status.mactime = le64_to_cpu(entry->tsft); |
142 | rx_status.flag |= RX_FLAG_TSFT; | |
38e3b0d8 | 143 | if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR) |
f6532111 MW |
144 | rx_status.flag |= RX_FLAG_FAILED_FCS_CRC; |
145 | ||
146 | ieee80211_rx_irqsafe(dev, skb, &rx_status); | |
147 | ||
148 | skb = new_skb; | |
149 | priv->rx_buf[priv->rx_idx] = skb; | |
150 | *((dma_addr_t *) skb->cb) = | |
151 | pci_map_single(priv->pdev, skb_tail_pointer(skb), | |
152 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
153 | } | |
154 | ||
155 | done: | |
156 | entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb)); | |
38e3b0d8 | 157 | entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | |
f6532111 MW |
158 | MAX_RX_SIZE); |
159 | if (priv->rx_idx == 31) | |
38e3b0d8 | 160 | entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); |
f6532111 MW |
161 | priv->rx_idx = (priv->rx_idx + 1) % 32; |
162 | } | |
163 | } | |
164 | ||
165 | static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio) | |
166 | { | |
167 | struct rtl8180_priv *priv = dev->priv; | |
168 | struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; | |
169 | ||
170 | while (skb_queue_len(&ring->queue)) { | |
171 | struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; | |
172 | struct sk_buff *skb; | |
e039fa4a | 173 | struct ieee80211_tx_info *info; |
f6532111 MW |
174 | u32 flags = le32_to_cpu(entry->flags); |
175 | ||
38e3b0d8 | 176 | if (flags & RTL818X_TX_DESC_FLAG_OWN) |
f6532111 MW |
177 | return; |
178 | ||
179 | ring->idx = (ring->idx + 1) % ring->entries; | |
180 | skb = __skb_dequeue(&ring->queue); | |
181 | pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), | |
182 | skb->len, PCI_DMA_TODEVICE); | |
183 | ||
e039fa4a JB |
184 | info = IEEE80211_SKB_CB(skb); |
185 | memset(&info->status, 0, sizeof(info->status)); | |
f6532111 | 186 | |
e039fa4a | 187 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { |
38e3b0d8 | 188 | if (flags & RTL818X_TX_DESC_FLAG_TX_OK) |
e039fa4a | 189 | info->flags |= IEEE80211_TX_STAT_ACK; |
f6532111 | 190 | else |
e039fa4a | 191 | info->status.excessive_retries = 1; |
f6532111 | 192 | } |
e039fa4a | 193 | info->status.retry_count = flags & 0xFF; |
f6532111 | 194 | |
e039fa4a | 195 | ieee80211_tx_status_irqsafe(dev, skb); |
f6532111 MW |
196 | if (ring->entries - skb_queue_len(&ring->queue) == 2) |
197 | ieee80211_wake_queue(dev, prio); | |
198 | } | |
199 | } | |
200 | ||
201 | static irqreturn_t rtl8180_interrupt(int irq, void *dev_id) | |
202 | { | |
203 | struct ieee80211_hw *dev = dev_id; | |
204 | struct rtl8180_priv *priv = dev->priv; | |
205 | u16 reg; | |
206 | ||
207 | spin_lock(&priv->lock); | |
208 | reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS); | |
209 | if (unlikely(reg == 0xFFFF)) { | |
210 | spin_unlock(&priv->lock); | |
211 | return IRQ_HANDLED; | |
212 | } | |
213 | ||
214 | rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg); | |
215 | ||
216 | if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR)) | |
217 | rtl8180_handle_tx(dev, 3); | |
218 | ||
219 | if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR)) | |
220 | rtl8180_handle_tx(dev, 2); | |
221 | ||
222 | if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR)) | |
223 | rtl8180_handle_tx(dev, 1); | |
224 | ||
225 | if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR)) | |
226 | rtl8180_handle_tx(dev, 0); | |
227 | ||
228 | if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR)) | |
229 | rtl8180_handle_rx(dev); | |
230 | ||
231 | spin_unlock(&priv->lock); | |
232 | ||
233 | return IRQ_HANDLED; | |
234 | } | |
235 | ||
e039fa4a | 236 | static int rtl8180_tx(struct ieee80211_hw *dev, struct sk_buff *skb) |
f6532111 | 237 | { |
e039fa4a | 238 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
f6532111 MW |
239 | struct rtl8180_priv *priv = dev->priv; |
240 | struct rtl8180_tx_ring *ring; | |
241 | struct rtl8180_tx_desc *entry; | |
242 | unsigned long flags; | |
243 | unsigned int idx, prio; | |
244 | dma_addr_t mapping; | |
245 | u32 tx_flags; | |
246 | u16 plcp_len = 0; | |
247 | __le16 rts_duration = 0; | |
248 | ||
e2530083 | 249 | prio = skb_get_queue_mapping(skb); |
f6532111 MW |
250 | ring = &priv->tx_ring[prio]; |
251 | ||
252 | mapping = pci_map_single(priv->pdev, skb->data, | |
253 | skb->len, PCI_DMA_TODEVICE); | |
254 | ||
38e3b0d8 HRK |
255 | tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS | |
256 | RTL818X_TX_DESC_FLAG_LS | | |
e039fa4a | 257 | (ieee80211_get_tx_rate(dev, info)->hw_value << 24) | |
2e92e6f2 | 258 | skb->len; |
f6532111 MW |
259 | |
260 | if (priv->r8185) | |
38e3b0d8 HRK |
261 | tx_flags |= RTL818X_TX_DESC_FLAG_DMA | |
262 | RTL818X_TX_DESC_FLAG_NO_ENC; | |
f6532111 | 263 | |
e039fa4a | 264 | if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) { |
38e3b0d8 | 265 | tx_flags |= RTL818X_TX_DESC_FLAG_RTS; |
e039fa4a JB |
266 | tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
267 | } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) { | |
38e3b0d8 | 268 | tx_flags |= RTL818X_TX_DESC_FLAG_CTS; |
e039fa4a | 269 | tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19; |
aa68cbfb | 270 | } |
f6532111 | 271 | |
e039fa4a | 272 | if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) |
32bfd35d | 273 | rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len, |
e039fa4a | 274 | info); |
f6532111 MW |
275 | |
276 | if (!priv->r8185) { | |
277 | unsigned int remainder; | |
278 | ||
279 | plcp_len = DIV_ROUND_UP(16 * (skb->len + 4), | |
e039fa4a | 280 | (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); |
f6532111 | 281 | remainder = (16 * (skb->len + 4)) % |
e039fa4a | 282 | ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10); |
f6532111 MW |
283 | if (remainder > 0 && remainder <= 6) |
284 | plcp_len |= 1 << 15; | |
285 | } | |
286 | ||
287 | spin_lock_irqsave(&priv->lock, flags); | |
288 | idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; | |
289 | entry = &ring->desc[idx]; | |
290 | ||
291 | entry->rts_duration = rts_duration; | |
292 | entry->plcp_len = cpu_to_le16(plcp_len); | |
293 | entry->tx_buf = cpu_to_le32(mapping); | |
294 | entry->frame_len = cpu_to_le32(skb->len); | |
870abdf6 FF |
295 | entry->flags2 = info->control.retries[0].rate_idx >= 0 ? |
296 | ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0; | |
e039fa4a | 297 | entry->retry_limit = info->control.retry_limit; |
f6532111 MW |
298 | entry->flags = cpu_to_le32(tx_flags); |
299 | __skb_queue_tail(&ring->queue, skb); | |
300 | if (ring->entries - skb_queue_len(&ring->queue) < 2) | |
e2530083 | 301 | ieee80211_stop_queue(dev, skb_get_queue_mapping(skb)); |
f6532111 MW |
302 | spin_unlock_irqrestore(&priv->lock, flags); |
303 | ||
304 | rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4))); | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam) | |
310 | { | |
311 | u8 reg; | |
312 | ||
313 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
314 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
315 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, | |
316 | reg | RTL818X_CONFIG3_ANAPARAM_WRITE); | |
317 | rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam); | |
318 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, | |
319 | reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE); | |
320 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
321 | } | |
322 | ||
323 | static int rtl8180_init_hw(struct ieee80211_hw *dev) | |
324 | { | |
325 | struct rtl8180_priv *priv = dev->priv; | |
326 | u16 reg; | |
327 | ||
328 | rtl818x_iowrite8(priv, &priv->map->CMD, 0); | |
329 | rtl818x_ioread8(priv, &priv->map->CMD); | |
330 | msleep(10); | |
331 | ||
332 | /* reset */ | |
333 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); | |
334 | rtl818x_ioread8(priv, &priv->map->CMD); | |
335 | ||
336 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
337 | reg &= (1 << 1); | |
338 | reg |= RTL818X_CMD_RESET; | |
339 | rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET); | |
340 | rtl818x_ioread8(priv, &priv->map->CMD); | |
341 | msleep(200); | |
342 | ||
343 | /* check success of reset */ | |
344 | if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) { | |
345 | printk(KERN_ERR "%s: reset timeout!\n", wiphy_name(dev->wiphy)); | |
346 | return -ETIMEDOUT; | |
347 | } | |
348 | ||
349 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD); | |
350 | rtl818x_ioread8(priv, &priv->map->CMD); | |
351 | msleep(200); | |
352 | ||
353 | if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) { | |
354 | /* For cardbus */ | |
355 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
356 | reg |= 1 << 1; | |
357 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg); | |
358 | reg = rtl818x_ioread16(priv, &priv->map->FEMR); | |
359 | reg |= (1 << 15) | (1 << 14) | (1 << 4); | |
360 | rtl818x_iowrite16(priv, &priv->map->FEMR, reg); | |
361 | } | |
362 | ||
363 | rtl818x_iowrite8(priv, &priv->map->MSR, 0); | |
364 | ||
365 | if (!priv->r8185) | |
366 | rtl8180_set_anaparam(priv, priv->anaparam); | |
367 | ||
368 | rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); | |
369 | rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); | |
370 | rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); | |
371 | rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); | |
372 | rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); | |
373 | ||
374 | /* TODO: necessary? specs indicate not */ | |
375 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
376 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); | |
377 | rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3)); | |
378 | if (priv->r8185) { | |
379 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG2); | |
380 | rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4)); | |
381 | } | |
382 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
383 | ||
384 | /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */ | |
385 | ||
386 | /* TODO: turn off hw wep on rtl8180 */ | |
387 | ||
388 | rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0); | |
389 | ||
390 | if (priv->r8185) { | |
391 | rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0); | |
392 | rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81); | |
393 | rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0); | |
394 | ||
395 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
396 | ||
397 | /* TODO: set ClkRun enable? necessary? */ | |
398 | reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE); | |
399 | rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6)); | |
400 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
401 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG3); | |
402 | rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2)); | |
403 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
404 | } else { | |
405 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1); | |
406 | rtl818x_iowrite8(priv, &priv->map->SECURITY, 0); | |
407 | ||
408 | rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6); | |
409 | rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C); | |
410 | } | |
411 | ||
412 | priv->rf->init(dev); | |
413 | if (priv->r8185) | |
414 | rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3); | |
415 | return 0; | |
416 | } | |
417 | ||
418 | static int rtl8180_init_rx_ring(struct ieee80211_hw *dev) | |
419 | { | |
420 | struct rtl8180_priv *priv = dev->priv; | |
421 | struct rtl8180_rx_desc *entry; | |
422 | int i; | |
423 | ||
424 | priv->rx_ring = pci_alloc_consistent(priv->pdev, | |
425 | sizeof(*priv->rx_ring) * 32, | |
426 | &priv->rx_ring_dma); | |
427 | ||
428 | if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) { | |
429 | printk(KERN_ERR "%s: Cannot allocate RX ring\n", | |
430 | wiphy_name(dev->wiphy)); | |
431 | return -ENOMEM; | |
432 | } | |
433 | ||
434 | memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32); | |
435 | priv->rx_idx = 0; | |
436 | ||
437 | for (i = 0; i < 32; i++) { | |
438 | struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE); | |
439 | dma_addr_t *mapping; | |
440 | entry = &priv->rx_ring[i]; | |
441 | if (!skb) | |
442 | return 0; | |
443 | ||
444 | priv->rx_buf[i] = skb; | |
445 | mapping = (dma_addr_t *)skb->cb; | |
446 | *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb), | |
447 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
448 | entry->rx_buf = cpu_to_le32(*mapping); | |
38e3b0d8 | 449 | entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN | |
f6532111 MW |
450 | MAX_RX_SIZE); |
451 | } | |
38e3b0d8 | 452 | entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR); |
f6532111 MW |
453 | return 0; |
454 | } | |
455 | ||
456 | static void rtl8180_free_rx_ring(struct ieee80211_hw *dev) | |
457 | { | |
458 | struct rtl8180_priv *priv = dev->priv; | |
459 | int i; | |
460 | ||
461 | for (i = 0; i < 32; i++) { | |
462 | struct sk_buff *skb = priv->rx_buf[i]; | |
463 | if (!skb) | |
464 | continue; | |
465 | ||
466 | pci_unmap_single(priv->pdev, | |
467 | *((dma_addr_t *)skb->cb), | |
468 | MAX_RX_SIZE, PCI_DMA_FROMDEVICE); | |
469 | kfree_skb(skb); | |
470 | } | |
471 | ||
472 | pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32, | |
473 | priv->rx_ring, priv->rx_ring_dma); | |
474 | priv->rx_ring = NULL; | |
475 | } | |
476 | ||
477 | static int rtl8180_init_tx_ring(struct ieee80211_hw *dev, | |
478 | unsigned int prio, unsigned int entries) | |
479 | { | |
480 | struct rtl8180_priv *priv = dev->priv; | |
481 | struct rtl8180_tx_desc *ring; | |
482 | dma_addr_t dma; | |
483 | int i; | |
484 | ||
485 | ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma); | |
486 | if (!ring || (unsigned long)ring & 0xFF) { | |
487 | printk(KERN_ERR "%s: Cannot allocate TX ring (prio = %d)\n", | |
488 | wiphy_name(dev->wiphy), prio); | |
489 | return -ENOMEM; | |
490 | } | |
491 | ||
492 | memset(ring, 0, sizeof(*ring)*entries); | |
493 | priv->tx_ring[prio].desc = ring; | |
494 | priv->tx_ring[prio].dma = dma; | |
495 | priv->tx_ring[prio].idx = 0; | |
496 | priv->tx_ring[prio].entries = entries; | |
497 | skb_queue_head_init(&priv->tx_ring[prio].queue); | |
498 | ||
499 | for (i = 0; i < entries; i++) | |
500 | ring[i].next_tx_desc = | |
501 | cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring)); | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio) | |
507 | { | |
508 | struct rtl8180_priv *priv = dev->priv; | |
509 | struct rtl8180_tx_ring *ring = &priv->tx_ring[prio]; | |
510 | ||
511 | while (skb_queue_len(&ring->queue)) { | |
512 | struct rtl8180_tx_desc *entry = &ring->desc[ring->idx]; | |
513 | struct sk_buff *skb = __skb_dequeue(&ring->queue); | |
514 | ||
515 | pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf), | |
516 | skb->len, PCI_DMA_TODEVICE); | |
f6532111 MW |
517 | kfree_skb(skb); |
518 | ring->idx = (ring->idx + 1) % ring->entries; | |
519 | } | |
520 | ||
521 | pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries, | |
522 | ring->desc, ring->dma); | |
523 | ring->desc = NULL; | |
524 | } | |
525 | ||
526 | static int rtl8180_start(struct ieee80211_hw *dev) | |
527 | { | |
528 | struct rtl8180_priv *priv = dev->priv; | |
529 | int ret, i; | |
530 | u32 reg; | |
531 | ||
532 | ret = rtl8180_init_rx_ring(dev); | |
533 | if (ret) | |
534 | return ret; | |
535 | ||
536 | for (i = 0; i < 4; i++) | |
537 | if ((ret = rtl8180_init_tx_ring(dev, i, 16))) | |
538 | goto err_free_rings; | |
539 | ||
540 | ret = rtl8180_init_hw(dev); | |
541 | if (ret) | |
542 | goto err_free_rings; | |
543 | ||
544 | rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma); | |
545 | rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma); | |
546 | rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma); | |
547 | rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma); | |
548 | rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma); | |
549 | ||
550 | ret = request_irq(priv->pdev->irq, &rtl8180_interrupt, | |
551 | IRQF_SHARED, KBUILD_MODNAME, dev); | |
552 | if (ret) { | |
553 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
554 | wiphy_name(dev->wiphy)); | |
555 | goto err_free_rings; | |
556 | } | |
557 | ||
558 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); | |
559 | ||
560 | rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0); | |
561 | rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0); | |
562 | ||
563 | reg = RTL818X_RX_CONF_ONLYERLPKT | | |
564 | RTL818X_RX_CONF_RX_AUTORESETPHY | | |
565 | RTL818X_RX_CONF_MGMT | | |
566 | RTL818X_RX_CONF_DATA | | |
567 | (7 << 8 /* MAX RX DMA */) | | |
568 | RTL818X_RX_CONF_BROADCAST | | |
569 | RTL818X_RX_CONF_NICMAC; | |
570 | ||
571 | if (priv->r8185) | |
572 | reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2; | |
573 | else { | |
574 | reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1) | |
575 | ? RTL818X_RX_CONF_CSDM1 : 0; | |
576 | reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2) | |
577 | ? RTL818X_RX_CONF_CSDM2 : 0; | |
578 | } | |
579 | ||
580 | priv->rx_conf = reg; | |
581 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg); | |
582 | ||
583 | if (priv->r8185) { | |
584 | reg = rtl818x_ioread8(priv, &priv->map->CW_CONF); | |
585 | reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT; | |
586 | reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; | |
587 | rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg); | |
588 | ||
589 | reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL); | |
590 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT; | |
591 | reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT; | |
592 | reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT; | |
593 | rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg); | |
594 | ||
595 | /* disable early TX */ | |
596 | rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f); | |
597 | } | |
598 | ||
599 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
600 | reg |= (6 << 21 /* MAX TX DMA */) | | |
601 | RTL818X_TX_CONF_NO_ICV; | |
602 | ||
603 | if (priv->r8185) | |
604 | reg &= ~RTL818X_TX_CONF_PROBE_DTS; | |
605 | else | |
606 | reg &= ~RTL818X_TX_CONF_HW_SEQNUM; | |
607 | ||
608 | /* different meaning, same value on both rtl8185 and rtl8180 */ | |
609 | reg &= ~RTL818X_TX_CONF_SAT_HWPLCP; | |
610 | ||
611 | rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg); | |
612 | ||
613 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
614 | reg |= RTL818X_CMD_RX_ENABLE; | |
615 | reg |= RTL818X_CMD_TX_ENABLE; | |
616 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
617 | ||
05c914fe | 618 | priv->mode = NL80211_IFTYPE_MONITOR; |
f6532111 MW |
619 | return 0; |
620 | ||
621 | err_free_rings: | |
622 | rtl8180_free_rx_ring(dev); | |
623 | for (i = 0; i < 4; i++) | |
624 | if (priv->tx_ring[i].desc) | |
625 | rtl8180_free_tx_ring(dev, i); | |
626 | ||
627 | return ret; | |
628 | } | |
629 | ||
630 | static void rtl8180_stop(struct ieee80211_hw *dev) | |
631 | { | |
632 | struct rtl8180_priv *priv = dev->priv; | |
633 | u8 reg; | |
634 | int i; | |
635 | ||
05c914fe | 636 | priv->mode = NL80211_IFTYPE_UNSPECIFIED; |
f6532111 MW |
637 | |
638 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); | |
639 | ||
640 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | |
641 | reg &= ~RTL818X_CMD_TX_ENABLE; | |
642 | reg &= ~RTL818X_CMD_RX_ENABLE; | |
643 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | |
644 | ||
645 | priv->rf->stop(dev); | |
646 | ||
647 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | |
648 | reg = rtl818x_ioread8(priv, &priv->map->CONFIG4); | |
649 | rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF); | |
650 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
651 | ||
652 | free_irq(priv->pdev->irq, dev); | |
653 | ||
654 | rtl8180_free_rx_ring(dev); | |
655 | for (i = 0; i < 4; i++) | |
656 | rtl8180_free_tx_ring(dev, i); | |
657 | } | |
658 | ||
659 | static int rtl8180_add_interface(struct ieee80211_hw *dev, | |
660 | struct ieee80211_if_init_conf *conf) | |
661 | { | |
662 | struct rtl8180_priv *priv = dev->priv; | |
663 | ||
05c914fe | 664 | if (priv->mode != NL80211_IFTYPE_MONITOR) |
f6532111 MW |
665 | return -EOPNOTSUPP; |
666 | ||
667 | switch (conf->type) { | |
05c914fe | 668 | case NL80211_IFTYPE_STATION: |
f6532111 MW |
669 | priv->mode = conf->type; |
670 | break; | |
671 | default: | |
672 | return -EOPNOTSUPP; | |
673 | } | |
674 | ||
32bfd35d JB |
675 | priv->vif = conf->vif; |
676 | ||
f6532111 MW |
677 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); |
678 | rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0], | |
717ddc0e | 679 | le32_to_cpu(*(__le32 *)conf->mac_addr)); |
f6532111 | 680 | rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4], |
717ddc0e | 681 | le16_to_cpu(*(__le16 *)(conf->mac_addr + 4))); |
f6532111 MW |
682 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | static void rtl8180_remove_interface(struct ieee80211_hw *dev, | |
688 | struct ieee80211_if_init_conf *conf) | |
689 | { | |
690 | struct rtl8180_priv *priv = dev->priv; | |
05c914fe | 691 | priv->mode = NL80211_IFTYPE_MONITOR; |
32bfd35d | 692 | priv->vif = NULL; |
f6532111 MW |
693 | } |
694 | ||
695 | static int rtl8180_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) | |
696 | { | |
697 | struct rtl8180_priv *priv = dev->priv; | |
698 | ||
699 | priv->rf->set_chan(dev, conf); | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
32bfd35d JB |
704 | static int rtl8180_config_interface(struct ieee80211_hw *dev, |
705 | struct ieee80211_vif *vif, | |
f6532111 MW |
706 | struct ieee80211_if_conf *conf) |
707 | { | |
708 | struct rtl8180_priv *priv = dev->priv; | |
709 | int i; | |
710 | ||
f6532111 MW |
711 | for (i = 0; i < ETH_ALEN; i++) |
712 | rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]); | |
713 | ||
714 | if (is_valid_ether_addr(conf->bssid)) | |
715 | rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_INFRA); | |
716 | else | |
717 | rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_NO_LINK); | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
722 | static void rtl8180_configure_filter(struct ieee80211_hw *dev, | |
723 | unsigned int changed_flags, | |
724 | unsigned int *total_flags, | |
725 | int mc_count, struct dev_addr_list *mclist) | |
726 | { | |
727 | struct rtl8180_priv *priv = dev->priv; | |
728 | ||
729 | if (changed_flags & FIF_FCSFAIL) | |
730 | priv->rx_conf ^= RTL818X_RX_CONF_FCS; | |
731 | if (changed_flags & FIF_CONTROL) | |
732 | priv->rx_conf ^= RTL818X_RX_CONF_CTRL; | |
733 | if (changed_flags & FIF_OTHER_BSS) | |
734 | priv->rx_conf ^= RTL818X_RX_CONF_MONITOR; | |
735 | if (*total_flags & FIF_ALLMULTI || mc_count > 0) | |
736 | priv->rx_conf |= RTL818X_RX_CONF_MULTICAST; | |
737 | else | |
738 | priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST; | |
739 | ||
740 | *total_flags = 0; | |
741 | ||
742 | if (priv->rx_conf & RTL818X_RX_CONF_FCS) | |
743 | *total_flags |= FIF_FCSFAIL; | |
744 | if (priv->rx_conf & RTL818X_RX_CONF_CTRL) | |
745 | *total_flags |= FIF_CONTROL; | |
746 | if (priv->rx_conf & RTL818X_RX_CONF_MONITOR) | |
747 | *total_flags |= FIF_OTHER_BSS; | |
748 | if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST) | |
749 | *total_flags |= FIF_ALLMULTI; | |
750 | ||
751 | rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf); | |
752 | } | |
753 | ||
754 | static const struct ieee80211_ops rtl8180_ops = { | |
755 | .tx = rtl8180_tx, | |
756 | .start = rtl8180_start, | |
757 | .stop = rtl8180_stop, | |
758 | .add_interface = rtl8180_add_interface, | |
759 | .remove_interface = rtl8180_remove_interface, | |
760 | .config = rtl8180_config, | |
761 | .config_interface = rtl8180_config_interface, | |
762 | .configure_filter = rtl8180_configure_filter, | |
763 | }; | |
764 | ||
765 | static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom) | |
766 | { | |
767 | struct ieee80211_hw *dev = eeprom->data; | |
768 | struct rtl8180_priv *priv = dev->priv; | |
769 | u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
770 | ||
771 | eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE; | |
772 | eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ; | |
773 | eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK; | |
774 | eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS; | |
775 | } | |
776 | ||
777 | static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom) | |
778 | { | |
779 | struct ieee80211_hw *dev = eeprom->data; | |
780 | struct rtl8180_priv *priv = dev->priv; | |
781 | u8 reg = 2 << 6; | |
782 | ||
783 | if (eeprom->reg_data_in) | |
784 | reg |= RTL818X_EEPROM_CMD_WRITE; | |
785 | if (eeprom->reg_data_out) | |
786 | reg |= RTL818X_EEPROM_CMD_READ; | |
787 | if (eeprom->reg_data_clock) | |
788 | reg |= RTL818X_EEPROM_CMD_CK; | |
789 | if (eeprom->reg_chip_select) | |
790 | reg |= RTL818X_EEPROM_CMD_CS; | |
791 | ||
792 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg); | |
793 | rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
794 | udelay(10); | |
795 | } | |
796 | ||
797 | static int __devinit rtl8180_probe(struct pci_dev *pdev, | |
798 | const struct pci_device_id *id) | |
799 | { | |
800 | struct ieee80211_hw *dev; | |
801 | struct rtl8180_priv *priv; | |
802 | unsigned long mem_addr, mem_len; | |
803 | unsigned int io_addr, io_len; | |
804 | int err, i; | |
805 | struct eeprom_93cx6 eeprom; | |
806 | const char *chip_name, *rf_name = NULL; | |
807 | u32 reg; | |
808 | u16 eeprom_val; | |
809 | DECLARE_MAC_BUF(mac); | |
810 | ||
811 | err = pci_enable_device(pdev); | |
812 | if (err) { | |
813 | printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n", | |
814 | pci_name(pdev)); | |
815 | return err; | |
816 | } | |
817 | ||
818 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
819 | if (err) { | |
820 | printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n", | |
821 | pci_name(pdev)); | |
822 | return err; | |
823 | } | |
824 | ||
825 | io_addr = pci_resource_start(pdev, 0); | |
826 | io_len = pci_resource_len(pdev, 0); | |
827 | mem_addr = pci_resource_start(pdev, 1); | |
828 | mem_len = pci_resource_len(pdev, 1); | |
829 | ||
830 | if (mem_len < sizeof(struct rtl818x_csr) || | |
831 | io_len < sizeof(struct rtl818x_csr)) { | |
832 | printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n", | |
833 | pci_name(pdev)); | |
834 | err = -ENOMEM; | |
835 | goto err_free_reg; | |
836 | } | |
837 | ||
838 | if ((err = pci_set_dma_mask(pdev, 0xFFFFFF00ULL)) || | |
839 | (err = pci_set_consistent_dma_mask(pdev, 0xFFFFFF00ULL))) { | |
840 | printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n", | |
841 | pci_name(pdev)); | |
842 | goto err_free_reg; | |
843 | } | |
844 | ||
845 | pci_set_master(pdev); | |
846 | ||
847 | dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops); | |
848 | if (!dev) { | |
849 | printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n", | |
850 | pci_name(pdev)); | |
851 | err = -ENOMEM; | |
852 | goto err_free_reg; | |
853 | } | |
854 | ||
855 | priv = dev->priv; | |
856 | priv->pdev = pdev; | |
857 | ||
870abdf6 | 858 | dev->max_altrates = 1; |
f6532111 MW |
859 | SET_IEEE80211_DEV(dev, &pdev->dev); |
860 | pci_set_drvdata(pdev, dev); | |
861 | ||
862 | priv->map = pci_iomap(pdev, 1, mem_len); | |
863 | if (!priv->map) | |
864 | priv->map = pci_iomap(pdev, 0, io_len); | |
865 | ||
866 | if (!priv->map) { | |
867 | printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n", | |
868 | pci_name(pdev)); | |
869 | goto err_free_dev; | |
870 | } | |
871 | ||
8318d78a JB |
872 | BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels)); |
873 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates)); | |
874 | ||
f6532111 MW |
875 | memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels)); |
876 | memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates)); | |
8318d78a JB |
877 | |
878 | priv->band.band = IEEE80211_BAND_2GHZ; | |
879 | priv->band.channels = priv->channels; | |
880 | priv->band.n_channels = ARRAY_SIZE(rtl818x_channels); | |
881 | priv->band.bitrates = priv->rates; | |
882 | priv->band.n_bitrates = 4; | |
883 | dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
884 | ||
f6532111 | 885 | dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
566bfe5a BR |
886 | IEEE80211_HW_RX_INCLUDES_FCS | |
887 | IEEE80211_HW_SIGNAL_UNSPEC; | |
f6532111 | 888 | dev->queues = 1; |
566bfe5a | 889 | dev->max_signal = 65; |
f6532111 MW |
890 | |
891 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | |
892 | reg &= RTL818X_TX_CONF_HWVER_MASK; | |
893 | switch (reg) { | |
894 | case RTL818X_TX_CONF_R8180_ABCD: | |
895 | chip_name = "RTL8180"; | |
896 | break; | |
897 | case RTL818X_TX_CONF_R8180_F: | |
898 | chip_name = "RTL8180vF"; | |
899 | break; | |
900 | case RTL818X_TX_CONF_R8185_ABC: | |
901 | chip_name = "RTL8185"; | |
902 | break; | |
903 | case RTL818X_TX_CONF_R8185_D: | |
904 | chip_name = "RTL8185vD"; | |
905 | break; | |
906 | default: | |
907 | printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n", | |
908 | pci_name(pdev), reg >> 25); | |
909 | goto err_iounmap; | |
910 | } | |
911 | ||
912 | priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC; | |
913 | if (priv->r8185) { | |
8318d78a | 914 | priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates); |
f6532111 MW |
915 | pci_try_set_mwi(pdev); |
916 | } | |
917 | ||
f6532111 MW |
918 | eeprom.data = dev; |
919 | eeprom.register_read = rtl8180_eeprom_register_read; | |
920 | eeprom.register_write = rtl8180_eeprom_register_write; | |
921 | if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6)) | |
922 | eeprom.width = PCI_EEPROM_WIDTH_93C66; | |
923 | else | |
924 | eeprom.width = PCI_EEPROM_WIDTH_93C46; | |
925 | ||
926 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM); | |
927 | rtl818x_ioread8(priv, &priv->map->EEPROM_CMD); | |
928 | udelay(10); | |
929 | ||
930 | eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val); | |
931 | eeprom_val &= 0xFF; | |
932 | switch (eeprom_val) { | |
933 | case 1: rf_name = "Intersil"; | |
934 | break; | |
935 | case 2: rf_name = "RFMD"; | |
936 | break; | |
937 | case 3: priv->rf = &sa2400_rf_ops; | |
938 | break; | |
939 | case 4: priv->rf = &max2820_rf_ops; | |
940 | break; | |
941 | case 5: priv->rf = &grf5101_rf_ops; | |
942 | break; | |
943 | case 9: priv->rf = rtl8180_detect_rf(dev); | |
944 | break; | |
945 | case 10: | |
946 | rf_name = "RTL8255"; | |
947 | break; | |
948 | default: | |
949 | printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n", | |
950 | pci_name(pdev), eeprom_val); | |
951 | goto err_iounmap; | |
952 | } | |
953 | ||
954 | if (!priv->rf) { | |
955 | printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n", | |
956 | pci_name(pdev), rf_name); | |
957 | goto err_iounmap; | |
958 | } | |
959 | ||
960 | eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val); | |
961 | priv->csthreshold = eeprom_val >> 8; | |
962 | if (!priv->r8185) { | |
963 | __le32 anaparam; | |
964 | eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2); | |
965 | priv->anaparam = le32_to_cpu(anaparam); | |
966 | eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam); | |
967 | } | |
968 | ||
969 | eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)dev->wiphy->perm_addr, 3); | |
970 | if (!is_valid_ether_addr(dev->wiphy->perm_addr)) { | |
971 | printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using" | |
972 | " randomly generated MAC addr\n", pci_name(pdev)); | |
973 | random_ether_addr(dev->wiphy->perm_addr); | |
974 | } | |
975 | ||
976 | /* CCK TX power */ | |
977 | for (i = 0; i < 14; i += 2) { | |
978 | u16 txpwr; | |
979 | eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr); | |
8318d78a JB |
980 | priv->channels[i].hw_value = txpwr & 0xFF; |
981 | priv->channels[i + 1].hw_value = txpwr >> 8; | |
f6532111 MW |
982 | } |
983 | ||
984 | /* OFDM TX power */ | |
985 | if (priv->r8185) { | |
986 | for (i = 0; i < 14; i += 2) { | |
987 | u16 txpwr; | |
988 | eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr); | |
8318d78a JB |
989 | priv->channels[i].hw_value |= (txpwr & 0xFF) << 8; |
990 | priv->channels[i + 1].hw_value |= txpwr & 0xFF00; | |
f6532111 MW |
991 | } |
992 | } | |
993 | ||
994 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | |
995 | ||
996 | spin_lock_init(&priv->lock); | |
997 | ||
998 | err = ieee80211_register_hw(dev); | |
999 | if (err) { | |
1000 | printk(KERN_ERR "%s (rtl8180): Cannot register device\n", | |
1001 | pci_name(pdev)); | |
1002 | goto err_iounmap; | |
1003 | } | |
1004 | ||
1005 | printk(KERN_INFO "%s: hwaddr %s, %s + %s\n", | |
1006 | wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr), | |
1007 | chip_name, priv->rf->name); | |
1008 | ||
1009 | return 0; | |
1010 | ||
1011 | err_iounmap: | |
1012 | iounmap(priv->map); | |
1013 | ||
1014 | err_free_dev: | |
1015 | pci_set_drvdata(pdev, NULL); | |
1016 | ieee80211_free_hw(dev); | |
1017 | ||
1018 | err_free_reg: | |
1019 | pci_release_regions(pdev); | |
1020 | pci_disable_device(pdev); | |
1021 | return err; | |
1022 | } | |
1023 | ||
1024 | static void __devexit rtl8180_remove(struct pci_dev *pdev) | |
1025 | { | |
1026 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
1027 | struct rtl8180_priv *priv; | |
1028 | ||
1029 | if (!dev) | |
1030 | return; | |
1031 | ||
1032 | ieee80211_unregister_hw(dev); | |
1033 | ||
1034 | priv = dev->priv; | |
1035 | ||
1036 | pci_iounmap(pdev, priv->map); | |
1037 | pci_release_regions(pdev); | |
1038 | pci_disable_device(pdev); | |
1039 | ieee80211_free_hw(dev); | |
1040 | } | |
1041 | ||
1042 | #ifdef CONFIG_PM | |
1043 | static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state) | |
1044 | { | |
1045 | pci_save_state(pdev); | |
1046 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | static int rtl8180_resume(struct pci_dev *pdev) | |
1051 | { | |
1052 | pci_set_power_state(pdev, PCI_D0); | |
1053 | pci_restore_state(pdev); | |
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | #endif /* CONFIG_PM */ | |
1058 | ||
1059 | static struct pci_driver rtl8180_driver = { | |
1060 | .name = KBUILD_MODNAME, | |
1061 | .id_table = rtl8180_table, | |
1062 | .probe = rtl8180_probe, | |
1063 | .remove = __devexit_p(rtl8180_remove), | |
1064 | #ifdef CONFIG_PM | |
1065 | .suspend = rtl8180_suspend, | |
1066 | .resume = rtl8180_resume, | |
1067 | #endif /* CONFIG_PM */ | |
1068 | }; | |
1069 | ||
1070 | static int __init rtl8180_init(void) | |
1071 | { | |
1072 | return pci_register_driver(&rtl8180_driver); | |
1073 | } | |
1074 | ||
1075 | static void __exit rtl8180_exit(void) | |
1076 | { | |
1077 | pci_unregister_driver(&rtl8180_driver); | |
1078 | } | |
1079 | ||
1080 | module_init(rtl8180_init); | |
1081 | module_exit(rtl8180_exit); |