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rt2x00: Reduce calls to bbp_read()
[linux-block.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
008c4482
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 0;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
0f829b1d 49 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 59 */
c9c3b1a5 60#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 62#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 64
0e14f6d3 65static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 66 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
8ff48a8b 70 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 71
95ea3627 72 /*
c9c3b1a5
ID		 73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
95ea3627 75 */
c9c3b1a5
ID		 76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
0f829b1d 83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 84 }
99ade259 85
8ff48a8b 86 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 87}
88
0e14f6d3 89static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 90 const unsigned int word, u8 *value)
91{
92 u32 reg;
93
8ff48a8b 94 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 95
95ea3627 96 /*
c9c3b1a5
ID		 97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
95ea3627 103 */
c9c3b1a5
ID		 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 109
0f829b1d 110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 111
c9c3b1a5
ID		 112 WAIT_FOR_BBP(rt2x00dev, &reg);
113 }
95ea3627
ID		 114
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 116
8ff48a8b 117 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 118}
119
0e14f6d3 120static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 121 const unsigned int word, const u32 value)
122{
123 u32 reg;
95ea3627
ID		 124
125 if (!word)
126 return;
127
8ff48a8b 128 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 129
4f5af6eb 130 /*
c9c3b1a5
ID		 131 * Wait until the RF becomes available, afterwards we
132 * can safely write the new data into the register.
4f5af6eb 133 */
c9c3b1a5
ID		 134 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
135 reg = 0;
136 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
137 /*
138 * RF5225 and RF2527 contain 21 bits per RF register value,
139 * all others contain 20 bits.
140 */
141 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
142 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
143 rt2x00_rf(&rt2x00dev->chip, RF2527)));
144 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
145 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
146
0f829b1d 147 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 148 rt2x00_rf_write(rt2x00dev, word, value);
149 }
8ff48a8b
ID		 150
151 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 152}
153
154#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 155static const struct rt2x00debug rt73usb_rt2x00debug = {
156 .owner = THIS_MODULE,
157 .csr = {
0f829b1d
ID		 158 .read = rt2x00usb_register_read,
159 .write = rt2x00usb_register_write,
743b97ca
ID		 160 .flags = RT2X00DEBUGFS_OFFSET,
161 .word_base = CSR_REG_BASE,
95ea3627
ID		 162 .word_size = sizeof(u32),
163 .word_count = CSR_REG_SIZE / sizeof(u32),
164 },
165 .eeprom = {
166 .read = rt2x00_eeprom_read,
167 .write = rt2x00_eeprom_write,
743b97ca 168 .word_base = EEPROM_BASE,
95ea3627
ID		 169 .word_size = sizeof(u16),
170 .word_count = EEPROM_SIZE / sizeof(u16),
171 },
172 .bbp = {
173 .read = rt73usb_bbp_read,
174 .write = rt73usb_bbp_write,
743b97ca 175 .word_base = BBP_BASE,
95ea3627
ID		 176 .word_size = sizeof(u8),
177 .word_count = BBP_SIZE / sizeof(u8),
178 },
179 .rf = {
180 .read = rt2x00_rf_read,
181 .write = rt73usb_rf_write,
743b97ca 182 .word_base = RF_BASE,
95ea3627
ID		 183 .word_size = sizeof(u32),
184 .word_count = RF_SIZE / sizeof(u32),
185 },
186};
187#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
188
771fd565 189#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 190static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 191 enum led_brightness brightness)
192{
193 struct rt2x00_led *led =
194 container_of(led_cdev, struct rt2x00_led, led_dev);
195 unsigned int enabled = brightness != LED_OFF;
196 unsigned int a_mode =
197 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
198 unsigned int bg_mode =
199 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
200
201 if (led->type == LED_TYPE_RADIO) {
202 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
203 MCU_LEDCS_RADIO_STATUS, enabled);
204
47b10cd1
ID		 205 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
206 0, led->rt2x00dev->led_mcu_reg,
207 REGISTER_TIMEOUT);
a9450b70
ID		 208 } else if (led->type == LED_TYPE_ASSOC) {
209 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
210 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
211 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
212 MCU_LEDCS_LINK_A_STATUS, a_mode);
213
47b10cd1
ID		 214 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
215 0, led->rt2x00dev->led_mcu_reg,
216 REGISTER_TIMEOUT);
a9450b70
ID		 217 } else if (led->type == LED_TYPE_QUALITY) {
218 /*
219 * The brightness is divided into 6 levels (0 - 5),
220 * this means we need to convert the brightness
221 * argument into the matching level within that range.
222 */
47b10cd1
ID		 223 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
224 brightness / (LED_FULL / 6),
225 led->rt2x00dev->led_mcu_reg,
226 REGISTER_TIMEOUT);
a9450b70
ID		 227 }
228}
a2e1d52a
ID		 229
230static int rt73usb_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233{
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
0f829b1d 238 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 239 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 241 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 242
243 return 0;
244}
475433be
ID		 245
246static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249{
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt73usb_brightness_set;
253 led->led_dev.blink_set = rt73usb_blink_set;
254 led->flags = LED_INITIALIZED;
255}
771fd565 256#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 257
95ea3627
ID		 258/*
259 * Configuration handlers.
260 */
906c110f
ID		 261static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
262 struct rt2x00lib_crypto *crypto,
263 struct ieee80211_key_conf *key)
264{
265 struct hw_key_entry key_entry;
266 struct rt2x00_field32 field;
267 int timeout;
268 u32 mask;
269 u32 reg;
270
271 if (crypto->cmd == SET_KEY) {
272 /*
273 * rt2x00lib can't determine the correct free
274 * key_idx for shared keys. We have 1 register
275 * with key valid bits. The goal is simple, read
276 * the register, if that is full we have no slots
277 * left.
278 * Note that each BSS is allowed to have up to 4
279 * shared keys, so put a mask over the allowed
280 * entries.
281 */
282 mask = (0xf << crypto->bssidx);
283
0f829b1d 284 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 285 reg &= mask;
286
287 if (reg && reg == mask)
288 return -ENOSPC;
289
acaf908d 290 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 291
292 /*
293 * Upload key to hardware
294 */
295 memcpy(key_entry.key, crypto->key,
296 sizeof(key_entry.key));
297 memcpy(key_entry.tx_mic, crypto->tx_mic,
298 sizeof(key_entry.tx_mic));
299 memcpy(key_entry.rx_mic, crypto->rx_mic,
300 sizeof(key_entry.rx_mic));
301
302 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
303 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
304 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
305 USB_VENDOR_REQUEST_OUT, reg,
306 &key_entry,
307 sizeof(key_entry),
308 timeout);
309
310 /*
311 * The cipher types are stored over 2 registers.
312 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
313 * bssidx 1 and 2 keys are stored in SEC_CSR5.
314 * Using the correct defines correctly will cause overhead,
315 * so just calculate the correct offset.
316 */
317 if (key->hw_key_idx < 8) {
318 field.bit_offset = (3 * key->hw_key_idx);
319 field.bit_mask = 0x7 << field.bit_offset;
320
0f829b1d 321 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 322 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 323 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 324 } else {
325 field.bit_offset = (3 * (key->hw_key_idx - 8));
326 field.bit_mask = 0x7 << field.bit_offset;
327
0f829b1d 328 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 329 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 330 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 331 }
332
333 /*
334 * The driver does not support the IV/EIV generation
335 * in hardware. However it doesn't support the IV/EIV
336 * inside the ieee80211 frame either, but requires it
337 * to be provided seperately for the descriptor.
338 * rt2x00lib will cut the IV/EIV data out of all frames
339 * given to us by mac80211, but we must tell mac80211
340 * to generate the IV/EIV data.
341 */
342 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
343 }
344
345 /*
346 * SEC_CSR0 contains only single-bit fields to indicate
347 * a particular key is valid. Because using the FIELD32()
348 * defines directly will cause a lot of overhead we use
349 * a calculation to determine the correct bit directly.
350 */
351 mask = 1 << key->hw_key_idx;
352
0f829b1d 353 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 354 if (crypto->cmd == SET_KEY)
355 reg |= mask;
356 else if (crypto->cmd == DISABLE_KEY)
357 reg &= ~mask;
0f829b1d 358 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 359
360 return 0;
361}
362
363static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
364 struct rt2x00lib_crypto *crypto,
365 struct ieee80211_key_conf *key)
366{
367 struct hw_pairwise_ta_entry addr_entry;
368 struct hw_key_entry key_entry;
369 int timeout;
370 u32 mask;
371 u32 reg;
372
373 if (crypto->cmd == SET_KEY) {
374 /*
375 * rt2x00lib can't determine the correct free
376 * key_idx for pairwise keys. We have 2 registers
377 * with key valid bits. The goal is simple, read
378 * the first register, if that is full move to
379 * the next register.
380 * When both registers are full, we drop the key,
381 * otherwise we use the first invalid entry.
382 */
0f829b1d 383 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 384 if (reg && reg == ~0) {
385 key->hw_key_idx = 32;
0f829b1d 386 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 387 if (reg && reg == ~0)
388 return -ENOSPC;
389 }
390
acaf908d 391 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 392
393 /*
394 * Upload key to hardware
395 */
396 memcpy(key_entry.key, crypto->key,
397 sizeof(key_entry.key));
398 memcpy(key_entry.tx_mic, crypto->tx_mic,
399 sizeof(key_entry.tx_mic));
400 memcpy(key_entry.rx_mic, crypto->rx_mic,
401 sizeof(key_entry.rx_mic));
402
403 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
404 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
405 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
406 USB_VENDOR_REQUEST_OUT, reg,
407 &key_entry,
408 sizeof(key_entry),
409 timeout);
410
411 /*
412 * Send the address and cipher type to the hardware register.
413 * This data fits within the CSR cache size, so we can use
0f829b1d 414 * rt2x00usb_register_multiwrite() directly.
906c110f
ID		 415 */
416 memset(&addr_entry, 0, sizeof(addr_entry));
417 memcpy(&addr_entry, crypto->address, ETH_ALEN);
418 addr_entry.cipher = crypto->cipher;
419
420 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 421 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 422 &addr_entry, sizeof(addr_entry));
423
424 /*
425 * Enable pairwise lookup table for given BSS idx,
426 * without this received frames will not be decrypted
427 * by the hardware.
428 */
0f829b1d 429 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 430 reg |= (1 << crypto->bssidx);
0f829b1d 431 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 432
433 /*
434 * The driver does not support the IV/EIV generation
435 * in hardware. However it doesn't support the IV/EIV
436 * inside the ieee80211 frame either, but requires it
437 * to be provided seperately for the descriptor.
438 * rt2x00lib will cut the IV/EIV data out of all frames
439 * given to us by mac80211, but we must tell mac80211
440 * to generate the IV/EIV data.
441 */
442 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
443 }
444
445 /*
446 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
447 * a particular key is valid. Because using the FIELD32()
448 * defines directly will cause a lot of overhead we use
449 * a calculation to determine the correct bit directly.
450 */
451 if (key->hw_key_idx < 32) {
452 mask = 1 << key->hw_key_idx;
453
0f829b1d 454 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 455 if (crypto->cmd == SET_KEY)
456 reg |= mask;
457 else if (crypto->cmd == DISABLE_KEY)
458 reg &= ~mask;
0f829b1d 459 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 460 } else {
461 mask = 1 << (key->hw_key_idx - 32);
462
0f829b1d 463 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 464 if (crypto->cmd == SET_KEY)
465 reg |= mask;
466 else if (crypto->cmd == DISABLE_KEY)
467 reg &= ~mask;
0f829b1d 468 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 469 }
470
471 return 0;
472}
473
3a643d24
ID		 474static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
475 const unsigned int filter_flags)
476{
477 u32 reg;
478
479 /*
480 * Start configuration steps.
481 * Note that the version error will always be dropped
482 * and broadcast frames will always be accepted since
483 * there is no filter for it at this time.
484 */
0f829b1d 485 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
487 !(filter_flags & FIF_FCSFAIL));
488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
489 !(filter_flags & FIF_PLCPFAIL));
490 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
491 !(filter_flags & FIF_CONTROL));
492 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
493 !(filter_flags & FIF_PROMISC_IN_BSS));
494 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 495 !(filter_flags & FIF_PROMISC_IN_BSS) &&
496 !rt2x00dev->intf_ap_count);
3a643d24
ID		 497 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
498 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
499 !(filter_flags & FIF_ALLMULTI));
500 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
501 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
502 !(filter_flags & FIF_CONTROL));
0f829b1d 503 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 504}
505
6bb40dd1
ID		 506static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
507 struct rt2x00_intf *intf,
508 struct rt2x00intf_conf *conf,
509 const unsigned int flags)
95ea3627 510{
6bb40dd1
ID		 511 unsigned int beacon_base;
512 u32 reg;
95ea3627 513
6bb40dd1
ID		 514 if (flags & CONFIG_UPDATE_TYPE) {
515 /*
516 * Clear current synchronisation setup.
517 * For the Beacon base registers we only need to clear
518 * the first byte since that byte contains the VALID and OWNER
519 * bits which (when set to 0) will invalidate the entire beacon.
520 */
521 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
0f829b1d 522 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 523
6bb40dd1
ID		 524 /*
525 * Enable synchronisation.
526 */
0f829b1d 527 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 528 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 529 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 530 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
0f829b1d 531 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 532 }
95ea3627 533
6bb40dd1
ID		 534 if (flags & CONFIG_UPDATE_MAC) {
535 reg = le32_to_cpu(conf->mac[1]);
536 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
537 conf->mac[1] = cpu_to_le32(reg);
95ea3627 538
0f829b1d 539 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 540 conf->mac, sizeof(conf->mac));
541 }
95ea3627 542
6bb40dd1
ID		 543 if (flags & CONFIG_UPDATE_BSSID) {
544 reg = le32_to_cpu(conf->bssid[1]);
545 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
546 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 547
0f829b1d 548 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 549 conf->bssid, sizeof(conf->bssid));
550 }
95ea3627
ID		 551}
552
3a643d24
ID		 553static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
554 struct rt2x00lib_erp *erp)
95ea3627 555{
95ea3627 556 u32 reg;
95ea3627 557
0f829b1d 558 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 559 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
0f829b1d 560 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 561
0f829b1d 562 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 563 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 564 !!erp->short_preamble);
0f829b1d 565 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 566
0f829b1d 567 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 568
0f829b1d 569 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
e4ea1c40 570 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
0f829b1d 571 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 572
0f829b1d 573 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
e4ea1c40
ID		 574 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
575 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
576 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
0f829b1d 577 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 578}
579
580static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 581 struct antenna_setup *ant)
95ea3627
ID		 582{
583 u8 r3;
584 u8 r4;
585 u8 r77;
2676c94d 586 u8 temp;
95ea3627
ID		 587
588 rt73usb_bbp_read(rt2x00dev, 3, &r3);
589 rt73usb_bbp_read(rt2x00dev, 4, &r4);
590 rt73usb_bbp_read(rt2x00dev, 77, &r77);
591
592 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
593
e4cd2ff8
ID		 594 /*
595 * Configure the RX antenna.
596 */
addc81bd 597 switch (ant->rx) {
95ea3627 598 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 599 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
600 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 601 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 602 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 603 break;
604 case ANTENNA_A:
2676c94d 605 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 606 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 607 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 608 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
609 else
610 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 611 break;
612 case ANTENNA_B:
a4fe07d9 613 default:
2676c94d 614 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 615 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 616 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 617 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
618 else
619 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 620 break;
621 }
622
623 rt73usb_bbp_write(rt2x00dev, 77, r77);
624 rt73usb_bbp_write(rt2x00dev, 3, r3);
625 rt73usb_bbp_write(rt2x00dev, 4, r4);
626}
627
628static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 629 struct antenna_setup *ant)
95ea3627
ID		 630{
631 u8 r3;
632 u8 r4;
633 u8 r77;
634
635 rt73usb_bbp_read(rt2x00dev, 3, &r3);
636 rt73usb_bbp_read(rt2x00dev, 4, &r4);
637 rt73usb_bbp_read(rt2x00dev, 77, &r77);
638
639 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
640 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
641 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
642
e4cd2ff8
ID		 643 /*
644 * Configure the RX antenna.
645 */
addc81bd 646 switch (ant->rx) {
95ea3627 647 case ANTENNA_HW_DIVERSITY:
2676c94d 648 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 649 break;
650 case ANTENNA_A:
2676c94d
MN		 651 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
652 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 653 break;
654 case ANTENNA_B:
a4fe07d9 655 default:
2676c94d
MN		 656 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
657 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 658 break;
659 }
660
661 rt73usb_bbp_write(rt2x00dev, 77, r77);
662 rt73usb_bbp_write(rt2x00dev, 3, r3);
663 rt73usb_bbp_write(rt2x00dev, 4, r4);
664}
665
666struct antenna_sel {
667 u8 word;
668 /*
669 * value[0] -> non-LNA
670 * value[1] -> LNA
671 */
672 u8 value[2];
673};
674
675static const struct antenna_sel antenna_sel_a[] = {
676 { 96, { 0x58, 0x78 } },
677 { 104, { 0x38, 0x48 } },
678 { 75, { 0xfe, 0x80 } },
679 { 86, { 0xfe, 0x80 } },
680 { 88, { 0xfe, 0x80 } },
681 { 35, { 0x60, 0x60 } },
682 { 97, { 0x58, 0x58 } },
683 { 98, { 0x58, 0x58 } },
684};
685
686static const struct antenna_sel antenna_sel_bg[] = {
687 { 96, { 0x48, 0x68 } },
688 { 104, { 0x2c, 0x3c } },
689 { 75, { 0xfe, 0x80 } },
690 { 86, { 0xfe, 0x80 } },
691 { 88, { 0xfe, 0x80 } },
692 { 35, { 0x50, 0x50 } },
693 { 97, { 0x48, 0x48 } },
694 { 98, { 0x48, 0x48 } },
695};
696
e4ea1c40
ID		 697static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
698 struct antenna_setup *ant)
95ea3627
ID		 699{
700 const struct antenna_sel *sel;
701 unsigned int lna;
702 unsigned int i;
703 u32 reg;
704
a4fe07d9
ID		 705 /*
706 * We should never come here because rt2x00lib is supposed
707 * to catch this and send us the correct antenna explicitely.
708 */
709 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
710 ant->tx == ANTENNA_SW_DIVERSITY);
711
8318d78a 712 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 713 sel = antenna_sel_a;
714 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 715 } else {
716 sel = antenna_sel_bg;
717 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 718 }
719
2676c94d
MN		 720 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
721 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
722
0f829b1d 723 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 724
ddc827f9 725 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 726 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 727 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 728 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 729
0f829b1d 730 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627
ID		 731
732 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
733 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 734 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 735 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
736 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 737 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 738}
739
e4ea1c40 740static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 741 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 742{
743 u16 eeprom;
744 short lna_gain = 0;
745
746 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
747 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
748 lna_gain += 14;
749
750 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
751 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
752 } else {
753 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
754 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
755 }
756
757 rt2x00dev->lna_gain = lna_gain;
758}
759
760static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
761 struct rf_channel *rf, const int txpower)
762{
763 u8 r3;
764 u8 r94;
765 u8 smart;
766
767 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
768 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
769
770 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
771 rt2x00_rf(&rt2x00dev->chip, RF2527));
772
773 rt73usb_bbp_read(rt2x00dev, 3, &r3);
774 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
775 rt73usb_bbp_write(rt2x00dev, 3, r3);
776
777 r94 = 6;
778 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
779 r94 += txpower - MAX_TXPOWER;
780 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
781 r94 += txpower;
782 rt73usb_bbp_write(rt2x00dev, 94, r94);
783
784 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
785 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
786 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
787 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
788
789 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
790 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
791 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
792 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
793
794 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
795 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
796 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
797 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
798
799 udelay(10);
800}
801
802static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
803 const int txpower)
804{
805 struct rf_channel rf;
806
807 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
808 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
809 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
810 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
811
812 rt73usb_config_channel(rt2x00dev, &rf, txpower);
813}
814
815static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
816 struct rt2x00lib_conf *libconf)
95ea3627
ID		 817{
818 u32 reg;
819
0f829b1d 820 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e4ea1c40
ID		 821 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
822 libconf->conf->long_frame_max_tx_count);
823 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
824 libconf->conf->short_frame_max_tx_count);
0f829b1d 825 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 826}
95ea3627 827
e4ea1c40
ID		 828static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
829 struct rt2x00lib_conf *libconf)
830{
831 u32 reg;
95ea3627 832
0f829b1d 833 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 834 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 835 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 836
0f829b1d 837 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
95ea3627 838 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
0f829b1d 839 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 840
0f829b1d 841 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 842 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
843 libconf->conf->beacon_int * 16);
0f829b1d 844 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 845}
846
7d7f19cc
ID		 847static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
848 struct rt2x00lib_conf *libconf)
849{
850 enum dev_state state =
851 (libconf->conf->flags & IEEE80211_CONF_PS) ?
852 STATE_SLEEP : STATE_AWAKE;
853 u32 reg;
854
855 if (state == STATE_SLEEP) {
856 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
857 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
858 libconf->conf->beacon_int - 10);
859 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
860 libconf->conf->listen_interval - 1);
861 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
862
863 /* We must first disable autowake before it can be enabled */
864 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
865 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
866
867 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
868 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
869
870 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
871 USB_MODE_SLEEP, REGISTER_TIMEOUT);
872 } else {
873 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
874 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
875
876 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
877 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
878 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
879 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
880 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
881 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
882 }
883}
884
95ea3627 885static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 886 struct rt2x00lib_conf *libconf,
887 const unsigned int flags)
95ea3627 888{
ba2ab471
ID		 889 /* Always recalculate LNA gain before changing configuration */
890 rt73usb_config_lna_gain(rt2x00dev, libconf);
891
e4ea1c40 892 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 893 rt73usb_config_channel(rt2x00dev, &libconf->rf,
894 libconf->conf->power_level);
e4ea1c40
ID		 895 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
896 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 897 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 898 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
899 rt73usb_config_retry_limit(rt2x00dev, libconf);
900 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
5c58ee51 901 rt73usb_config_duration(rt2x00dev, libconf);
7d7f19cc
ID		 902 if (flags & IEEE80211_CONF_CHANGE_PS)
903 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 904}
905
95ea3627
ID		 906/*
907 * Link tuning
908 */
ebcf26da
ID		 909static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
910 struct link_qual *qual)
95ea3627
ID		 911{
912 u32 reg;
913
914 /*
915 * Update FCS error count from register.
916 */
0f829b1d 917 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 918 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 919
920 /*
921 * Update False CCA count from register.
922 */
0f829b1d 923 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 924 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 925}
926
eb20b4e8
ID		 927static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev, u8 vgc_level)
928{
929 if (rt2x00dev->link.vgc_level != vgc_level) {
930 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
931 rt2x00dev->link.vgc_level = vgc_level;
932 rt2x00dev->link.vgc_level_reg = vgc_level;
933 }
934}
935
95ea3627
ID		 936static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
937{
eb20b4e8 938 rt73usb_set_vgc(rt2x00dev, 0x20);
95ea3627
ID		 939}
940
941static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
942{
eb20b4e8
ID		 943 struct link *link = &rt2x00dev->link;
944 int rssi = rt2x00_get_link_rssi(link);
95ea3627
ID		 945 u8 up_bound;
946 u8 low_bound;
947
95ea3627
ID		 948 /*
949 * Determine r17 bounds.
950 */
8318d78a 951 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 952 low_bound = 0x28;
953 up_bound = 0x48;
954
955 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
956 low_bound += 0x10;
957 up_bound += 0x10;
958 }
959 } else {
960 if (rssi > -82) {
961 low_bound = 0x1c;
962 up_bound = 0x40;
963 } else if (rssi > -84) {
964 low_bound = 0x1c;
965 up_bound = 0x20;
966 } else {
967 low_bound = 0x1c;
968 up_bound = 0x1c;
969 }
970
971 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
972 low_bound += 0x14;
973 up_bound += 0x10;
974 }
975 }
976
6bb40dd1
ID		 977 /*
978 * If we are not associated, we should go straight to the
979 * dynamic CCA tuning.
980 */
981 if (!rt2x00dev->intf_associated)
982 goto dynamic_cca_tune;
983
95ea3627
ID		 984 /*
985 * Special big-R17 for very short distance
986 */
987 if (rssi > -35) {
eb20b4e8 988 rt73usb_set_vgc(rt2x00dev, 0x60);
95ea3627
ID		 989 return;
990 }
991
992 /*
993 * Special big-R17 for short distance
994 */
995 if (rssi >= -58) {
eb20b4e8 996 rt73usb_set_vgc(rt2x00dev, up_bound);
95ea3627
ID		 997 return;
998 }
999
1000 /*
1001 * Special big-R17 for middle-short distance
1002 */
1003 if (rssi >= -66) {
eb20b4e8 1004 rt73usb_set_vgc(rt2x00dev, low_bound + 0x10);
95ea3627
ID		 1005 return;
1006 }
1007
1008 /*
1009 * Special mid-R17 for middle distance
1010 */
1011 if (rssi >= -74) {
eb20b4e8 1012 rt73usb_set_vgc(rt2x00dev, low_bound + 0x08);
95ea3627
ID		 1013 return;
1014 }
1015
1016 /*
1017 * Special case: Change up_bound based on the rssi.
1018 * Lower up_bound when rssi is weaker then -74 dBm.
1019 */
1020 up_bound -= 2 * (-74 - rssi);
1021 if (low_bound > up_bound)
1022 up_bound = low_bound;
1023
eb20b4e8
ID		 1024 if (link->vgc_level > up_bound) {
1025 rt73usb_set_vgc(rt2x00dev, up_bound);
95ea3627
ID		 1026 return;
1027 }
1028
6bb40dd1
ID		 1029dynamic_cca_tune:
1030
95ea3627
ID		 1031 /*
1032 * r17 does not yet exceed upper limit, continue and base
1033 * the r17 tuning on the false CCA count.
1034 */
eb20b4e8
ID		 1035 if ((link->qual.false_cca > 512) && (link->vgc_level < up_bound))
1036 rt73usb_set_vgc(rt2x00dev,
1037 min_t(u8, link->vgc_level + 4, up_bound));
1038 else if ((link->qual.false_cca < 100) && (link->vgc_level > low_bound))
1039 rt73usb_set_vgc(rt2x00dev,
1040 max_t(u8, link->vgc_level - 4, low_bound));
95ea3627
ID		 1041}
1042
1043/*
a7f3a06c 1044 * Firmware functions
95ea3627
ID		 1045 */
1046static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1047{
1048 return FIRMWARE_RT2571;
1049}
1050
f160ebcb 1051static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
a7f3a06c
ID		 1052{
1053 u16 crc;
1054
1055 /*
1056 * Use the crc itu-t algorithm.
1057 * The last 2 bytes in the firmware array are the crc checksum itself,
1058 * this means that we should never pass those 2 bytes to the crc
1059 * algorithm.
1060 */
1061 crc = crc_itu_t(0, data, len - 2);
1062 crc = crc_itu_t_byte(crc, 0);
1063 crc = crc_itu_t_byte(crc, 0);
1064
1065 return crc;
1066}
1067
f160ebcb 1068static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
95ea3627
ID		 1069 const size_t len)
1070{
1071 unsigned int i;
1072 int status;
1073 u32 reg;
95ea3627
ID		 1074
1075 /*
1076 * Wait for stable hardware.
1077 */
1078 for (i = 0; i < 100; i++) {
0f829b1d 1079 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1080 if (reg)
1081 break;
1082 msleep(1);
1083 }
1084
1085 if (!reg) {
1086 ERROR(rt2x00dev, "Unstable hardware.\n");
1087 return -EBUSY;
1088 }
1089
1090 /*
1091 * Write firmware to device.
95ea3627 1092 */
3e0c1abe
IM		 1093 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1094 USB_VENDOR_REQUEST_OUT,
1095 FIRMWARE_IMAGE_BASE,
1096 data, len,
1097 REGISTER_TIMEOUT32(len));
95ea3627
ID		 1098
1099 /*
1100 * Send firmware request to device to load firmware,
1101 * we need to specify a long timeout time.
1102 */
1103 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1104 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1105 REGISTER_TIMEOUT_FIRMWARE);
1106 if (status < 0) {
1107 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1108 return status;
1109 }
1110
95ea3627
ID		 1111 return 0;
1112}
1113
a7f3a06c
ID		 1114/*
1115 * Initialization functions.
1116 */
95ea3627
ID		 1117static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1118{
1119 u32 reg;
1120
0f829b1d 1121 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1122 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1123 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1124 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1125 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1126
0f829b1d 1127 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1128 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1129 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1130 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1131 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1132 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1133 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1134 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1135 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1136 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1137
1138 /*
1139 * CCK TXD BBP registers
1140 */
0f829b1d 1141 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1142 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1143 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1144 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1145 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1146 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1147 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1148 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1149 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1150 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1151
1152 /*
1153 * OFDM TXD BBP registers
1154 */
0f829b1d 1155 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1156 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1157 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1158 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1159 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1160 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1161 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1162 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1163
0f829b1d 1164 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1165 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1166 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1167 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1168 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1169 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1170
0f829b1d 1171 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1172 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1173 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1174 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1175 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1176 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1177
0f829b1d 1178 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1179 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1180 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1181 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1182 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1183 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1184 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1185 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1186
0f829b1d 1187 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1188
0f829b1d 1189 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1190 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1191 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1192
0f829b1d 1193 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1194
1195 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1196 return -EBUSY;
1197
0f829b1d 1198 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1199
1200 /*
1201 * Invalidate all Shared Keys (SEC_CSR0),
1202 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1203 */
0f829b1d
ID		 1204 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1205 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1206 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1207
1208 reg = 0x000023b0;
1209 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1210 rt2x00_rf(&rt2x00dev->chip, RF2527))
1211 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1212 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1213
0f829b1d
ID		 1214 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1215 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1216 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1217
0f829b1d 1218 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1219 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1220 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1221
6bb40dd1
ID		 1222 /*
1223 * Clear all beacons
1224 * For the Beacon base registers we only need to clear
1225 * the first byte since that byte contains the VALID and OWNER
1226 * bits which (when set to 0) will invalidate the entire beacon.
1227 */
0f829b1d
ID		 1228 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1229 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1230 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1231 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1232
95ea3627
ID		 1233 /*
1234 * We must clear the error counters.
1235 * These registers are cleared on read,
1236 * so we may pass a useless variable to store the value.
1237 */
0f829b1d
ID		 1238 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1239 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1240 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1241
1242 /*
1243 * Reset MAC and BBP registers.
1244 */
0f829b1d 1245 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1246 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1247 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1248 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1249
0f829b1d 1250 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1251 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1252 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1253 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1254
0f829b1d 1255 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1256 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1257 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1258
1259 return 0;
1260}
1261
2b08da3f 1262static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1263{
1264 unsigned int i;
95ea3627
ID		 1265 u8 value;
1266
1267 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1268 rt73usb_bbp_read(rt2x00dev, 0, &value);
1269 if ((value != 0xff) && (value != 0x00))
2b08da3f 1270 return 0;
95ea3627
ID		 1271 udelay(REGISTER_BUSY_DELAY);
1272 }
1273
1274 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1275 return -EACCES;
2b08da3f
ID		 1276}
1277
1278static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1279{
1280 unsigned int i;
1281 u16 eeprom;
1282 u8 reg_id;
1283 u8 value;
1284
1285 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1286 return -EACCES;
95ea3627 1287
95ea3627
ID		 1288 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1289 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1290 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1291 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1292 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1293 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1294 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1295 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1296 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1297 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1298 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1299 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1300 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1301 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1302 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1303 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1304 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1305 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1306 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1307 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1308 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1309 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1310 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1311 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1312 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1313
95ea3627
ID		 1314 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1315 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1316
1317 if (eeprom != 0xffff && eeprom != 0x0000) {
1318 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1319 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1320 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1321 }
1322 }
95ea3627
ID		 1323
1324 return 0;
1325}
1326
1327/*
1328 * Device state switch handlers.
1329 */
1330static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1331 enum dev_state state)
1332{
1333 u32 reg;
1334
0f829b1d 1335 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 1336 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1337 (state == STATE_RADIO_RX_OFF) ||
1338 (state == STATE_RADIO_RX_OFF_LINK));
0f829b1d 1339 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627
ID		 1340}
1341
1342static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1343{
1344 /*
1345 * Initialize all registers.
1346 */
2b08da3f
ID		 1347 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1348 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1349 return -EIO;
95ea3627 1350
95ea3627
ID		 1351 return 0;
1352}
1353
1354static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1355{
0f829b1d 1356 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1357
1358 /*
1359 * Disable synchronisation.
1360 */
0f829b1d 1361 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1362
1363 rt2x00usb_disable_radio(rt2x00dev);
1364}
1365
1366static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1367{
1368 u32 reg;
1369 unsigned int i;
1370 char put_to_sleep;
95ea3627
ID		 1371
1372 put_to_sleep = (state != STATE_AWAKE);
1373
0f829b1d 1374 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1375 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1376 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1377 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1378
1379 /*
1380 * Device is not guaranteed to be in the requested state yet.
1381 * We must wait until the register indicates that the
1382 * device has entered the correct state.
1383 */
1384 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
0f829b1d 1385 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1386 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1387 if (state == !put_to_sleep)
95ea3627
ID		 1388 return 0;
1389 msleep(10);
1390 }
1391
95ea3627
ID		 1392 return -EBUSY;
1393}
1394
1395static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1396 enum dev_state state)
1397{
1398 int retval = 0;
1399
1400 switch (state) {
1401 case STATE_RADIO_ON:
1402 retval = rt73usb_enable_radio(rt2x00dev);
1403 break;
1404 case STATE_RADIO_OFF:
1405 rt73usb_disable_radio(rt2x00dev);
1406 break;
1407 case STATE_RADIO_RX_ON:
61667d8d 1408 case STATE_RADIO_RX_ON_LINK:
95ea3627 1409 case STATE_RADIO_RX_OFF:
61667d8d 1410 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1411 rt73usb_toggle_rx(rt2x00dev, state);
1412 break;
1413 case STATE_RADIO_IRQ_ON:
1414 case STATE_RADIO_IRQ_OFF:
1415 /* No support, but no error either */
95ea3627
ID		 1416 break;
1417 case STATE_DEEP_SLEEP:
1418 case STATE_SLEEP:
1419 case STATE_STANDBY:
1420 case STATE_AWAKE:
1421 retval = rt73usb_set_state(rt2x00dev, state);
1422 break;
1423 default:
1424 retval = -ENOTSUPP;
1425 break;
1426 }
1427
2b08da3f
ID		 1428 if (unlikely(retval))
1429 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1430 state, retval);
1431
95ea3627
ID		 1432 return retval;
1433}
1434
1435/*
1436 * TX descriptor initialization
1437 */
1438static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
906c110f
ID		 1439 struct sk_buff *skb,
1440 struct txentry_desc *txdesc)
95ea3627 1441{
181d6902 1442 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1443 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1444 u32 word;
1445
1446 /*
1447 * Start writing the descriptor words.
1448 */
1449 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1450 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1451 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1452 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1453 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
906c110f 1454 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1455 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1456 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1457 rt2x00_desc_write(txd, 1, word);
1458
1459 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1460 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1461 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1462 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1463 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1464 rt2x00_desc_write(txd, 2, word);
1465
906c110f 1466 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1467 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1468 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1469 }
1470
95ea3627
ID		 1471 rt2x00_desc_read(txd, 5, &word);
1472 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1473 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1474 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1475 rt2x00_desc_write(txd, 5, word);
1476
1477 rt2x00_desc_read(txd, 0, &word);
1478 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1479 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1480 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1481 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1482 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1483 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1484 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1485 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1486 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1487 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1488 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1489 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1490 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1491 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
906c110f
ID		 1492 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1493 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1494 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1495 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1496 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1abc3656 1497 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1498 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1499 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
906c110f 1500 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1501 rt2x00_desc_write(txd, 0, word);
1502}
1503
bd88a781
ID		 1504/*
1505 * TX data initialization
1506 */
1507static void rt73usb_write_beacon(struct queue_entry *entry)
1508{
1509 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1510 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1511 unsigned int beacon_base;
1512 u32 reg;
1513
1514 /*
1515 * Add the descriptor in front of the skb.
1516 */
1517 skb_push(entry->skb, entry->queue->desc_size);
1518 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1519 skbdesc->desc = entry->skb->data;
1520
1521 /*
1522 * Disable beaconing while we are reloading the beacon data,
1523 * otherwise we might be sending out invalid data.
1524 */
0f829b1d 1525 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1526 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1527 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1528 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1529 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781
ID		 1530
1531 /*
1532 * Write entire beacon with descriptor to register.
1533 */
1534 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3e0c1abe
IM		 1535 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1536 USB_VENDOR_REQUEST_OUT, beacon_base,
1537 entry->skb->data, entry->skb->len,
1538 REGISTER_TIMEOUT32(entry->skb->len));
bd88a781
ID		 1539
1540 /*
1541 * Clean up the beacon skb.
1542 */
1543 dev_kfree_skb(entry->skb);
1544 entry->skb = NULL;
1545}
1546
f1ca2167 1547static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1548{
1549 int length;
1550
1551 /*
1552 * The length _must_ be a multiple of 4,
1553 * but it must _not_ be a multiple of the USB packet size.
1554 */
f1ca2167
ID		 1555 length = roundup(entry->skb->len, 4);
1556 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1557
1558 return length;
1559}
1560
95ea3627 1561static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1562 const enum data_queue_qid queue)
95ea3627
ID		 1563{
1564 u32 reg;
1565
f019d514
ID		 1566 if (queue != QID_BEACON) {
1567 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1568 return;
f019d514 1569 }
95ea3627
ID		 1570
1571 /*
1572 * For Wi-Fi faily generated beacons between participating stations.
1573 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1574 */
0f829b1d 1575 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
95ea3627 1576
0f829b1d 1577 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
95ea3627 1578 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1579 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1580 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 1581 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
0f829b1d 1582 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 1583 }
1584}
1585
1586/*
1587 * RX control handlers
1588 */
1589static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1590{
ba2ab471 1591 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1592 u8 lna;
1593
1594 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1595 switch (lna) {
1596 case 3:
ba2ab471 1597 offset += 90;
95ea3627
ID		 1598 break;
1599 case 2:
ba2ab471 1600 offset += 74;
95ea3627
ID		 1601 break;
1602 case 1:
ba2ab471 1603 offset += 64;
95ea3627
ID		 1604 break;
1605 default:
1606 return 0;
1607 }
1608
8318d78a 1609 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1610 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1611 if (lna == 3 || lna == 2)
1612 offset += 10;
1613 } else {
1614 if (lna == 3)
1615 offset += 6;
1616 else if (lna == 2)
1617 offset += 8;
1618 }
95ea3627
ID		 1619 }
1620
1621 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1622}
1623
181d6902 1624static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1625 struct rxdone_entry_desc *rxdesc)
95ea3627 1626{
906c110f 1627 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1628 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1629 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1630 u32 word0;
1631 u32 word1;
1632
f855c10b 1633 /*
a26cbc65
GW		 1634 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1635 * frame data in rt2x00usb.
f855c10b 1636 */
a26cbc65 1637 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1638 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1639
1640 /*
70a96109 1641 * It is now safe to read the descriptor on all architectures.
f855c10b 1642 */
95ea3627
ID		 1643 rt2x00_desc_read(rxd, 0, &word0);
1644 rt2x00_desc_read(rxd, 1, &word1);
1645
4150c572 1646 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1647 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1648
906c110f
ID		 1649 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1650 rxdesc->cipher =
1651 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1652 rxdesc->cipher_status =
1653 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1654 }
1655
1656 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1657 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1658 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1659 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1660
906c110f 1661 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1662 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1663
1664 /*
1665 * Hardware has stripped IV/EIV data from 802.11 frame during
1666 * decryption. It has provided the data seperately but rt2x00lib
1667 * should decide if it should be reinserted.
1668 */
1669 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1670
1671 /*
1672 * FIXME: Legacy driver indicates that the frame does
1673 * contain the Michael Mic. Unfortunately, in rt2x00
1674 * the MIC seems to be missing completely...
1675 */
1676 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1677
1678 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1679 rxdesc->flags |= RX_FLAG_DECRYPTED;
1680 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1681 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1682 }
1683
95ea3627
ID		 1684 /*
1685 * Obtain the status about this packet.
89993890
ID		 1686 * When frame was received with an OFDM bitrate,
1687 * the signal is the PLCP value. If it was received with
1688 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1689 */
181d6902 1690 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1691 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1692 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1693
19d30e02
ID		 1694 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1695 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1696 else
1697 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1698 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1699 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1700
2ae23854 1701 /*
70a96109 1702 * Set skb pointers, and update frame information.
2ae23854 1703 */
70a96109 1704 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1705 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1706}
1707
1708/*
1709 * Device probe functions.
1710 */
1711static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1712{
1713 u16 word;
1714 u8 *mac;
1715 s8 value;
1716
1717 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1718
1719 /*
1720 * Start validation of the data that has been read.
1721 */
1722 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1723 if (!is_valid_ether_addr(mac)) {
1724 random_ether_addr(mac);
e174961c 1725 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1726 }
1727
1728 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1729 if (word == 0xffff) {
1730 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1731 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1732 ANTENNA_B);
1733 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1734 ANTENNA_B);
95ea3627
ID		 1735 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1736 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1737 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1738 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1739 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1740 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1741 }
1742
1743 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1744 if (word == 0xffff) {
1745 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1746 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1747 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1748 }
1749
1750 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1751 if (word == 0xffff) {
1752 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1753 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1754 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1755 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1756 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1757 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1758 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1759 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1760 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1761 LED_MODE_DEFAULT);
1762 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1763 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1764 }
1765
1766 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1767 if (word == 0xffff) {
1768 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1769 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1770 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1771 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1772 }
1773
1774 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1775 if (word == 0xffff) {
1776 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1777 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1778 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1779 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1780 } else {
1781 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1782 if (value < -10 || value > 10)
1783 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1784 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1785 if (value < -10 || value > 10)
1786 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1787 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1788 }
1789
1790 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1791 if (word == 0xffff) {
1792 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1793 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1794 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1795 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1796 } else {
1797 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1798 if (value < -10 || value > 10)
1799 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1800 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1801 if (value < -10 || value > 10)
1802 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1803 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1804 }
1805
1806 return 0;
1807}
1808
1809static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1810{
1811 u32 reg;
1812 u16 value;
1813 u16 eeprom;
1814
1815 /*
1816 * Read EEPROM word for configuration.
1817 */
1818 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1819
1820 /*
1821 * Identify RF chipset.
1822 */
1823 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1824 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1825 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1826
755a957d 1827 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1828 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1829 return -ENODEV;
1830 }
1831
1832 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1833 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1834 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1835 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1836 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1837 return -ENODEV;
1838 }
1839
1840 /*
1841 * Identify default antenna configuration.
1842 */
addc81bd 1843 rt2x00dev->default_ant.tx =
95ea3627 1844 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1845 rt2x00dev->default_ant.rx =
95ea3627
ID		 1846 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1847
1848 /*
1849 * Read the Frame type.
1850 */
1851 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1852 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1853
1854 /*
1855 * Read frequency offset.
1856 */
1857 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1858 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1859
1860 /*
1861 * Read external LNA informations.
1862 */
1863 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1864
1865 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1866 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1867 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1868 }
1869
1870 /*
1871 * Store led settings, for correct led behaviour.
1872 */
771fd565 1873#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1874 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1875
475433be
ID		 1876 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1877 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1878 if (value == LED_MODE_SIGNAL_STRENGTH)
1879 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1880 LED_TYPE_QUALITY);
a9450b70
ID		 1881
1882 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1883 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1884 rt2x00_get_field16(eeprom,
1885 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1886 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1887 rt2x00_get_field16(eeprom,
1888 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1889 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1890 rt2x00_get_field16(eeprom,
1891 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1892 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1893 rt2x00_get_field16(eeprom,
1894 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1895 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1896 rt2x00_get_field16(eeprom,
1897 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1898 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1899 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1900 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1901 rt2x00_get_field16(eeprom,
1902 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1903 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1904 rt2x00_get_field16(eeprom,
1905 EEPROM_LED_POLARITY_RDY_A));
771fd565 1906#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1907
1908 return 0;
1909}
1910
1911/*
1912 * RF value list for RF2528
1913 * Supports: 2.4 GHz
1914 */
1915static const struct rf_channel rf_vals_bg_2528[] = {
1916 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1917 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1918 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1919 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1920 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1921 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1922 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1923 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1924 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1925 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1926 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1927 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1928 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1929 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1930};
1931
1932/*
1933 * RF value list for RF5226
1934 * Supports: 2.4 GHz & 5.2 GHz
1935 */
1936static const struct rf_channel rf_vals_5226[] = {
1937 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1938 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1939 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1940 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1941 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1942 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1943 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1944 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1945 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1946 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1947 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1948 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1949 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1950 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1951
1952 /* 802.11 UNI / HyperLan 2 */
1953 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1954 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1955 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1956 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1957 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1958 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1959 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1960 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1961
1962 /* 802.11 HyperLan 2 */
1963 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1964 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1965 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1966 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1967 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1968 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1969 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1970 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1971 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1972 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1973
1974 /* 802.11 UNII */
1975 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1976 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1977 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1978 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1979 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1980 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1981
1982 /* MMAC(Japan)J52 ch 34,38,42,46 */
1983 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1984 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1985 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1986 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1987};
1988
1989/*
1990 * RF value list for RF5225 & RF2527
1991 * Supports: 2.4 GHz & 5.2 GHz
1992 */
1993static const struct rf_channel rf_vals_5225_2527[] = {
1994 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1995 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1996 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1997 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1998 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1999 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2000 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2001 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2002 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2003 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2004 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2005 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2006 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2007 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2008
2009 /* 802.11 UNI / HyperLan 2 */
2010 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2011 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2012 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2013 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2014 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2015 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2016 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2017 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2018
2019 /* 802.11 HyperLan 2 */
2020 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2021 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2022 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2023 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2024 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2025 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2026 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2027 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2028 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2029 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2030
2031 /* 802.11 UNII */
2032 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2033 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2034 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2035 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2036 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2037 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2038
2039 /* MMAC(Japan)J52 ch 34,38,42,46 */
2040 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2041 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2042 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2043 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2044};
2045
2046
8c5e7a5f 2047static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2048{
2049 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2050 struct channel_info *info;
2051 char *tx_power;
95ea3627
ID		 2052 unsigned int i;
2053
2054 /*
2055 * Initialize all hw fields.
2056 */
2057 rt2x00dev->hw->flags =
566bfe5a
BR		 2058 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2059 IEEE80211_HW_SIGNAL_DBM;
95ea3627 2060 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
95ea3627 2061
14a3bf89 2062 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2063 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2064 rt2x00_eeprom_addr(rt2x00dev,
2065 EEPROM_MAC_ADDR_0));
2066
95ea3627
ID		 2067 /*
2068 * Initialize hw_mode information.
2069 */
31562e80
ID		 2070 spec->supported_bands = SUPPORT_BAND_2GHZ;
2071 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2072
2073 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2074 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2075 spec->channels = rf_vals_bg_2528;
2076 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 2077 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2078 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2079 spec->channels = rf_vals_5226;
2080 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2081 spec->num_channels = 14;
2082 spec->channels = rf_vals_5225_2527;
2083 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 2084 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2085 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2086 spec->channels = rf_vals_5225_2527;
2087 }
2088
8c5e7a5f
ID		 2089 /*
2090 * Create channel information array
2091 */
2092 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2093 if (!info)
2094 return -ENOMEM;
95ea3627 2095
8c5e7a5f
ID		 2096 spec->channels_info = info;
2097
2098 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2099 for (i = 0; i < 14; i++)
2100 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2101
2102 if (spec->num_channels > 14) {
2103 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2104 for (i = 14; i < spec->num_channels; i++)
2105 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2106 }
8c5e7a5f
ID		 2107
2108 return 0;
95ea3627
ID		 2109}
2110
2111static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2112{
2113 int retval;
2114
2115 /*
2116 * Allocate eeprom data.
2117 */
2118 retval = rt73usb_validate_eeprom(rt2x00dev);
2119 if (retval)
2120 return retval;
2121
2122 retval = rt73usb_init_eeprom(rt2x00dev);
2123 if (retval)
2124 return retval;
2125
2126 /*
2127 * Initialize hw specifications.
2128 */
8c5e7a5f
ID		 2129 retval = rt73usb_probe_hw_mode(rt2x00dev);
2130 if (retval)
2131 return retval;
95ea3627
ID		 2132
2133 /*
9404ef34 2134 * This device requires firmware.
95ea3627 2135 */
066cb637 2136 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 2137 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
008c4482
ID		 2138 if (!modparam_nohwcrypt)
2139 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2140
2141 /*
2142 * Set the rssi offset.
2143 */
2144 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2145
2146 return 0;
2147}
2148
2149/*
2150 * IEEE80211 stack callback functions.
2151 */
2af0a570
ID		 2152static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2153 const struct ieee80211_tx_queue_params *params)
2154{
2155 struct rt2x00_dev *rt2x00dev = hw->priv;
2156 struct data_queue *queue;
2157 struct rt2x00_field32 field;
2158 int retval;
2159 u32 reg;
2160
2161 /*
2162 * First pass the configuration through rt2x00lib, that will
2163 * update the queue settings and validate the input. After that
2164 * we are free to update the registers based on the value
2165 * in the queue parameter.
2166 */
2167 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2168 if (retval)
2169 return retval;
2170
2171 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2172
2173 /* Update WMM TXOP register */
2174 if (queue_idx < 2) {
2175 field.bit_offset = queue_idx * 16;
2176 field.bit_mask = 0xffff << field.bit_offset;
2177
0f829b1d 2178 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2af0a570 2179 rt2x00_set_field32(&reg, field, queue->txop);
0f829b1d 2180 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2af0a570
ID		 2181 } else if (queue_idx < 4) {
2182 field.bit_offset = (queue_idx - 2) * 16;
2183 field.bit_mask = 0xffff << field.bit_offset;
2184
0f829b1d 2185 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2af0a570 2186 rt2x00_set_field32(&reg, field, queue->txop);
0f829b1d 2187 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2af0a570
ID		 2188 }
2189
2190 /* Update WMM registers */
2191 field.bit_offset = queue_idx * 4;
2192 field.bit_mask = 0xf << field.bit_offset;
2193
0f829b1d 2194 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2195 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2196 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2197
0f829b1d 2198 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2199 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2200 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2201
0f829b1d 2202 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2203 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2204 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2205
2206 return 0;
2207}
2208
95ea3627
ID		 2209#if 0
2210/*
2211 * Mac80211 demands get_tsf must be atomic.
2212 * This is not possible for rt73usb since all register access
2213 * functions require sleeping. Untill mac80211 no longer needs
2214 * get_tsf to be atomic, this function should be disabled.
2215 */
2216static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2217{
2218 struct rt2x00_dev *rt2x00dev = hw->priv;
2219 u64 tsf;
2220 u32 reg;
2221
0f829b1d 2222 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2223 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2224 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2225 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2226
2227 return tsf;
2228}
37894473
ID		 2229#else
2230#define rt73usb_get_tsf NULL
95ea3627
ID		 2231#endif
2232
95ea3627
ID		 2233static const struct ieee80211_ops rt73usb_mac80211_ops = {
2234 .tx = rt2x00mac_tx,
4150c572
JB		 2235 .start = rt2x00mac_start,
2236 .stop = rt2x00mac_stop,
95ea3627
ID		 2237 .add_interface = rt2x00mac_add_interface,
2238 .remove_interface = rt2x00mac_remove_interface,
2239 .config = rt2x00mac_config,
2240 .config_interface = rt2x00mac_config_interface,
3a643d24 2241 .configure_filter = rt2x00mac_configure_filter,
906c110f 2242 .set_key = rt2x00mac_set_key,
95ea3627 2243 .get_stats = rt2x00mac_get_stats,
471b3efd 2244 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2245 .conf_tx = rt73usb_conf_tx,
95ea3627 2246 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2247 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2248};
2249
2250static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2251 .probe_hw = rt73usb_probe_hw,
2252 .get_firmware_name = rt73usb_get_firmware_name,
a7f3a06c 2253 .get_firmware_crc = rt73usb_get_firmware_crc,
95ea3627
ID		 2254 .load_firmware = rt73usb_load_firmware,
2255 .initialize = rt2x00usb_initialize,
2256 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2257 .clear_entry = rt2x00usb_clear_entry,
95ea3627
ID		 2258 .set_device_state = rt73usb_set_device_state,
2259 .link_stats = rt73usb_link_stats,
2260 .reset_tuner = rt73usb_reset_tuner,
2261 .link_tuner = rt73usb_link_tuner,
2262 .write_tx_desc = rt73usb_write_tx_desc,
2263 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2264 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2265 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2266 .kick_tx_queue = rt73usb_kick_tx_queue,
2267 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2268 .config_shared_key = rt73usb_config_shared_key,
2269 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2270 .config_filter = rt73usb_config_filter,
6bb40dd1 2271 .config_intf = rt73usb_config_intf,
72810379 2272 .config_erp = rt73usb_config_erp,
e4ea1c40 2273 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2274 .config = rt73usb_config,
2275};
2276
181d6902
ID		 2277static const struct data_queue_desc rt73usb_queue_rx = {
2278 .entry_num = RX_ENTRIES,
2279 .data_size = DATA_FRAME_SIZE,
2280 .desc_size = RXD_DESC_SIZE,
b8be63ff 2281 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2282};
2283
2284static const struct data_queue_desc rt73usb_queue_tx = {
2285 .entry_num = TX_ENTRIES,
2286 .data_size = DATA_FRAME_SIZE,
2287 .desc_size = TXD_DESC_SIZE,
b8be63ff 2288 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2289};
2290
2291static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2292 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2293 .data_size = MGMT_FRAME_SIZE,
2294 .desc_size = TXINFO_SIZE,
b8be63ff 2295 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2296};
2297
95ea3627 2298static const struct rt2x00_ops rt73usb_ops = {
2360157c 2299 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2300 .max_sta_intf = 1,
2301 .max_ap_intf = 4,
95ea3627
ID		 2302 .eeprom_size = EEPROM_SIZE,
2303 .rf_size = RF_SIZE,
61448f88 2304 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2305 .rx = &rt73usb_queue_rx,
2306 .tx = &rt73usb_queue_tx,
2307 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2308 .lib = &rt73usb_rt2x00_ops,
2309 .hw = &rt73usb_mac80211_ops,
2310#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2311 .debugfs = &rt73usb_rt2x00debug,
2312#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2313};
2314
2315/*
2316 * rt73usb module information.
2317 */
2318static struct usb_device_id rt73usb_device_table[] = {
2319 /* AboCom */
2320 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2321 /* Askey */
2322 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2323 /* ASUS */
2324 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2325 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2326 /* Belkin */
2327 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2328 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2329 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2330 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2331 /* Billionton */
2332 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2333 /* Buffalo */
2334 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2335 /* CNet */
2336 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2337 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2338 /* Conceptronic */
2339 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2340 /* Corega */
2341 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2342 /* D-Link */
2343 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2344 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2345 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2346 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2347 /* Gemtek */
2348 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2349 /* Gigabyte */
2350 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2351 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2352 /* Huawei-3Com */
2353 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2354 /* Hercules */
2355 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2356 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2357 /* Linksys */
2358 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2359 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
3be36ae2 2360 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2361 /* MSI */
2362 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2363 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2364 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2365 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2366 /* Ralink */
2367 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2368 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2369 /* Qcom */
2370 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2371 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2372 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2373 /* Senao */
2374 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2375 /* Sitecom */
2376 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2377 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2378 /* Surecom */
2379 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2380 /* Planex */
2381 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2382 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2383 { 0, }
2384};
2385
2386MODULE_AUTHOR(DRV_PROJECT);
2387MODULE_VERSION(DRV_VERSION);
2388MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2389MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2390MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2391MODULE_FIRMWARE(FIRMWARE_RT2571);
2392MODULE_LICENSE("GPL");
2393
2394static struct usb_driver rt73usb_driver = {
2360157c 2395 .name = KBUILD_MODNAME,
95ea3627
ID		 2396 .id_table = rt73usb_device_table,
2397 .probe = rt2x00usb_probe,
2398 .disconnect = rt2x00usb_disconnect,
2399 .suspend = rt2x00usb_suspend,
2400 .resume = rt2x00usb_resume,
2401};
2402
2403static int __init rt73usb_init(void)
2404{
2405 return usb_register(&rt73usb_driver);
2406}
2407
2408static void __exit rt73usb_exit(void)
2409{
2410 usb_deregister(&rt73usb_driver);
2411}
2412
2413module_init(rt73usb_init);
2414module_exit(rt73usb_exit);
Linux 6.x block layer and io_uring tree(s)