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95ea3627 | 1 | /* |
811aa9ca | 2 | Copyright (C) 2004 - 2008 rt2x00 SourceForge Project |
95ea3627 ID |
3 | <http://rt2x00.serialmonkey.com> |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 2 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the | |
17 | Free Software Foundation, Inc., | |
18 | 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | /* | |
22 | Module: rt73usb | |
23 | Abstract: rt73usb device specific routines. | |
24 | Supported chipsets: rt2571W & rt2671. | |
25 | */ | |
26 | ||
a7f3a06c | 27 | #include <linux/crc-itu-t.h> |
95ea3627 ID |
28 | #include <linux/delay.h> |
29 | #include <linux/etherdevice.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/usb.h> | |
34 | ||
35 | #include "rt2x00.h" | |
36 | #include "rt2x00usb.h" | |
37 | #include "rt73usb.h" | |
38 | ||
008c4482 ID |
39 | /* |
40 | * Allow hardware encryption to be disabled. | |
41 | */ | |
42 | static int modparam_nohwcrypt = 0; | |
43 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); | |
44 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); | |
45 | ||
95ea3627 ID |
46 | /* |
47 | * Register access. | |
48 | * All access to the CSR registers will go through the methods | |
0f829b1d | 49 | * rt2x00usb_register_read and rt2x00usb_register_write. |
95ea3627 ID |
50 | * BBP and RF register require indirect register access, |
51 | * and use the CSR registers BBPCSR and RFCSR to achieve this. | |
52 | * These indirect registers work with busy bits, | |
53 | * and we will try maximal REGISTER_BUSY_COUNT times to access | |
54 | * the register while taking a REGISTER_BUSY_DELAY us delay | |
55 | * between each attampt. When the busy bit is still set at that time, | |
56 | * the access attempt is considered to have failed, | |
57 | * and we will print an error. | |
8ff48a8b | 58 | * The _lock versions must be used if you already hold the csr_mutex |
95ea3627 | 59 | */ |
c9c3b1a5 | 60 | #define WAIT_FOR_BBP(__dev, __reg) \ |
0f829b1d | 61 | rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg)) |
c9c3b1a5 | 62 | #define WAIT_FOR_RF(__dev, __reg) \ |
0f829b1d | 63 | rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg)) |
c9c3b1a5 | 64 | |
0e14f6d3 | 65 | static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
66 | const unsigned int word, const u8 value) |
67 | { | |
68 | u32 reg; | |
69 | ||
8ff48a8b | 70 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 71 | |
95ea3627 | 72 | /* |
c9c3b1a5 ID |
73 | * Wait until the BBP becomes available, afterwards we |
74 | * can safely write the new data into the register. | |
95ea3627 | 75 | */ |
c9c3b1a5 ID |
76 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
77 | reg = 0; | |
78 | rt2x00_set_field32(®, PHY_CSR3_VALUE, value); | |
79 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
80 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
81 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); | |
82 | ||
0f829b1d | 83 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); |
c9c3b1a5 | 84 | } |
99ade259 | 85 | |
8ff48a8b | 86 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
87 | } |
88 | ||
0e14f6d3 | 89 | static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
90 | const unsigned int word, u8 *value) |
91 | { | |
92 | u32 reg; | |
93 | ||
8ff48a8b | 94 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 95 | |
95ea3627 | 96 | /* |
c9c3b1a5 ID |
97 | * Wait until the BBP becomes available, afterwards we |
98 | * can safely write the read request into the register. | |
99 | * After the data has been written, we wait until hardware | |
100 | * returns the correct value, if at any time the register | |
101 | * doesn't become available in time, reg will be 0xffffffff | |
102 | * which means we return 0xff to the caller. | |
95ea3627 | 103 | */ |
c9c3b1a5 ID |
104 | if (WAIT_FOR_BBP(rt2x00dev, ®)) { |
105 | reg = 0; | |
106 | rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); | |
107 | rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); | |
108 | rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); | |
95ea3627 | 109 | |
0f829b1d | 110 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); |
95ea3627 | 111 | |
c9c3b1a5 ID |
112 | WAIT_FOR_BBP(rt2x00dev, ®); |
113 | } | |
95ea3627 ID |
114 | |
115 | *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); | |
99ade259 | 116 | |
8ff48a8b | 117 | mutex_unlock(&rt2x00dev->csr_mutex); |
95ea3627 ID |
118 | } |
119 | ||
0e14f6d3 | 120 | static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev, |
95ea3627 ID |
121 | const unsigned int word, const u32 value) |
122 | { | |
123 | u32 reg; | |
95ea3627 ID |
124 | |
125 | if (!word) | |
126 | return; | |
127 | ||
8ff48a8b | 128 | mutex_lock(&rt2x00dev->csr_mutex); |
3d82346c | 129 | |
4f5af6eb | 130 | /* |
c9c3b1a5 ID |
131 | * Wait until the RF becomes available, afterwards we |
132 | * can safely write the new data into the register. | |
4f5af6eb | 133 | */ |
c9c3b1a5 ID |
134 | if (WAIT_FOR_RF(rt2x00dev, ®)) { |
135 | reg = 0; | |
136 | rt2x00_set_field32(®, PHY_CSR4_VALUE, value); | |
137 | /* | |
138 | * RF5225 and RF2527 contain 21 bits per RF register value, | |
139 | * all others contain 20 bits. | |
140 | */ | |
141 | rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, | |
142 | 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
143 | rt2x00_rf(&rt2x00dev->chip, RF2527))); | |
144 | rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); | |
145 | rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); | |
146 | ||
0f829b1d | 147 | rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); |
c9c3b1a5 ID |
148 | rt2x00_rf_write(rt2x00dev, word, value); |
149 | } | |
8ff48a8b ID |
150 | |
151 | mutex_unlock(&rt2x00dev->csr_mutex); | |
95ea3627 ID |
152 | } |
153 | ||
154 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
95ea3627 ID |
155 | static const struct rt2x00debug rt73usb_rt2x00debug = { |
156 | .owner = THIS_MODULE, | |
157 | .csr = { | |
0f829b1d ID |
158 | .read = rt2x00usb_register_read, |
159 | .write = rt2x00usb_register_write, | |
743b97ca ID |
160 | .flags = RT2X00DEBUGFS_OFFSET, |
161 | .word_base = CSR_REG_BASE, | |
95ea3627 ID |
162 | .word_size = sizeof(u32), |
163 | .word_count = CSR_REG_SIZE / sizeof(u32), | |
164 | }, | |
165 | .eeprom = { | |
166 | .read = rt2x00_eeprom_read, | |
167 | .write = rt2x00_eeprom_write, | |
743b97ca | 168 | .word_base = EEPROM_BASE, |
95ea3627 ID |
169 | .word_size = sizeof(u16), |
170 | .word_count = EEPROM_SIZE / sizeof(u16), | |
171 | }, | |
172 | .bbp = { | |
173 | .read = rt73usb_bbp_read, | |
174 | .write = rt73usb_bbp_write, | |
743b97ca | 175 | .word_base = BBP_BASE, |
95ea3627 ID |
176 | .word_size = sizeof(u8), |
177 | .word_count = BBP_SIZE / sizeof(u8), | |
178 | }, | |
179 | .rf = { | |
180 | .read = rt2x00_rf_read, | |
181 | .write = rt73usb_rf_write, | |
743b97ca | 182 | .word_base = RF_BASE, |
95ea3627 ID |
183 | .word_size = sizeof(u32), |
184 | .word_count = RF_SIZE / sizeof(u32), | |
185 | }, | |
186 | }; | |
187 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
188 | ||
771fd565 | 189 | #ifdef CONFIG_RT2X00_LIB_LEDS |
a2e1d52a | 190 | static void rt73usb_brightness_set(struct led_classdev *led_cdev, |
a9450b70 ID |
191 | enum led_brightness brightness) |
192 | { | |
193 | struct rt2x00_led *led = | |
194 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
195 | unsigned int enabled = brightness != LED_OFF; | |
196 | unsigned int a_mode = | |
197 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | |
198 | unsigned int bg_mode = | |
199 | (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ); | |
200 | ||
201 | if (led->type == LED_TYPE_RADIO) { | |
202 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
203 | MCU_LEDCS_RADIO_STATUS, enabled); | |
204 | ||
47b10cd1 ID |
205 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
206 | 0, led->rt2x00dev->led_mcu_reg, | |
207 | REGISTER_TIMEOUT); | |
a9450b70 ID |
208 | } else if (led->type == LED_TYPE_ASSOC) { |
209 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
210 | MCU_LEDCS_LINK_BG_STATUS, bg_mode); | |
211 | rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, | |
212 | MCU_LEDCS_LINK_A_STATUS, a_mode); | |
213 | ||
47b10cd1 ID |
214 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
215 | 0, led->rt2x00dev->led_mcu_reg, | |
216 | REGISTER_TIMEOUT); | |
a9450b70 ID |
217 | } else if (led->type == LED_TYPE_QUALITY) { |
218 | /* | |
219 | * The brightness is divided into 6 levels (0 - 5), | |
220 | * this means we need to convert the brightness | |
221 | * argument into the matching level within that range. | |
222 | */ | |
47b10cd1 ID |
223 | rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL, |
224 | brightness / (LED_FULL / 6), | |
225 | led->rt2x00dev->led_mcu_reg, | |
226 | REGISTER_TIMEOUT); | |
a9450b70 ID |
227 | } |
228 | } | |
a2e1d52a ID |
229 | |
230 | static int rt73usb_blink_set(struct led_classdev *led_cdev, | |
231 | unsigned long *delay_on, | |
232 | unsigned long *delay_off) | |
233 | { | |
234 | struct rt2x00_led *led = | |
235 | container_of(led_cdev, struct rt2x00_led, led_dev); | |
236 | u32 reg; | |
237 | ||
0f829b1d | 238 | rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, ®); |
a2e1d52a ID |
239 | rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); |
240 | rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); | |
0f829b1d | 241 | rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg); |
a2e1d52a ID |
242 | |
243 | return 0; | |
244 | } | |
475433be ID |
245 | |
246 | static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev, | |
247 | struct rt2x00_led *led, | |
248 | enum led_type type) | |
249 | { | |
250 | led->rt2x00dev = rt2x00dev; | |
251 | led->type = type; | |
252 | led->led_dev.brightness_set = rt73usb_brightness_set; | |
253 | led->led_dev.blink_set = rt73usb_blink_set; | |
254 | led->flags = LED_INITIALIZED; | |
255 | } | |
771fd565 | 256 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
a9450b70 | 257 | |
95ea3627 ID |
258 | /* |
259 | * Configuration handlers. | |
260 | */ | |
906c110f ID |
261 | static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev, |
262 | struct rt2x00lib_crypto *crypto, | |
263 | struct ieee80211_key_conf *key) | |
264 | { | |
265 | struct hw_key_entry key_entry; | |
266 | struct rt2x00_field32 field; | |
267 | int timeout; | |
268 | u32 mask; | |
269 | u32 reg; | |
270 | ||
271 | if (crypto->cmd == SET_KEY) { | |
272 | /* | |
273 | * rt2x00lib can't determine the correct free | |
274 | * key_idx for shared keys. We have 1 register | |
275 | * with key valid bits. The goal is simple, read | |
276 | * the register, if that is full we have no slots | |
277 | * left. | |
278 | * Note that each BSS is allowed to have up to 4 | |
279 | * shared keys, so put a mask over the allowed | |
280 | * entries. | |
281 | */ | |
282 | mask = (0xf << crypto->bssidx); | |
283 | ||
0f829b1d | 284 | rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); |
906c110f ID |
285 | reg &= mask; |
286 | ||
287 | if (reg && reg == mask) | |
288 | return -ENOSPC; | |
289 | ||
acaf908d | 290 | key->hw_key_idx += reg ? ffz(reg) : 0; |
906c110f ID |
291 | |
292 | /* | |
293 | * Upload key to hardware | |
294 | */ | |
295 | memcpy(key_entry.key, crypto->key, | |
296 | sizeof(key_entry.key)); | |
297 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
298 | sizeof(key_entry.tx_mic)); | |
299 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
300 | sizeof(key_entry.rx_mic)); | |
301 | ||
302 | reg = SHARED_KEY_ENTRY(key->hw_key_idx); | |
303 | timeout = REGISTER_TIMEOUT32(sizeof(key_entry)); | |
304 | rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE, | |
305 | USB_VENDOR_REQUEST_OUT, reg, | |
306 | &key_entry, | |
307 | sizeof(key_entry), | |
308 | timeout); | |
309 | ||
310 | /* | |
311 | * The cipher types are stored over 2 registers. | |
312 | * bssidx 0 and 1 keys are stored in SEC_CSR1 and | |
313 | * bssidx 1 and 2 keys are stored in SEC_CSR5. | |
314 | * Using the correct defines correctly will cause overhead, | |
315 | * so just calculate the correct offset. | |
316 | */ | |
317 | if (key->hw_key_idx < 8) { | |
318 | field.bit_offset = (3 * key->hw_key_idx); | |
319 | field.bit_mask = 0x7 << field.bit_offset; | |
320 | ||
0f829b1d | 321 | rt2x00usb_register_read(rt2x00dev, SEC_CSR1, ®); |
906c110f | 322 | rt2x00_set_field32(®, field, crypto->cipher); |
0f829b1d | 323 | rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg); |
906c110f ID |
324 | } else { |
325 | field.bit_offset = (3 * (key->hw_key_idx - 8)); | |
326 | field.bit_mask = 0x7 << field.bit_offset; | |
327 | ||
0f829b1d | 328 | rt2x00usb_register_read(rt2x00dev, SEC_CSR5, ®); |
906c110f | 329 | rt2x00_set_field32(®, field, crypto->cipher); |
0f829b1d | 330 | rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg); |
906c110f ID |
331 | } |
332 | ||
333 | /* | |
334 | * The driver does not support the IV/EIV generation | |
335 | * in hardware. However it doesn't support the IV/EIV | |
336 | * inside the ieee80211 frame either, but requires it | |
337 | * to be provided seperately for the descriptor. | |
338 | * rt2x00lib will cut the IV/EIV data out of all frames | |
339 | * given to us by mac80211, but we must tell mac80211 | |
340 | * to generate the IV/EIV data. | |
341 | */ | |
342 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
343 | } | |
344 | ||
345 | /* | |
346 | * SEC_CSR0 contains only single-bit fields to indicate | |
347 | * a particular key is valid. Because using the FIELD32() | |
348 | * defines directly will cause a lot of overhead we use | |
349 | * a calculation to determine the correct bit directly. | |
350 | */ | |
351 | mask = 1 << key->hw_key_idx; | |
352 | ||
0f829b1d | 353 | rt2x00usb_register_read(rt2x00dev, SEC_CSR0, ®); |
906c110f ID |
354 | if (crypto->cmd == SET_KEY) |
355 | reg |= mask; | |
356 | else if (crypto->cmd == DISABLE_KEY) | |
357 | reg &= ~mask; | |
0f829b1d | 358 | rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg); |
906c110f ID |
359 | |
360 | return 0; | |
361 | } | |
362 | ||
363 | static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev, | |
364 | struct rt2x00lib_crypto *crypto, | |
365 | struct ieee80211_key_conf *key) | |
366 | { | |
367 | struct hw_pairwise_ta_entry addr_entry; | |
368 | struct hw_key_entry key_entry; | |
369 | int timeout; | |
370 | u32 mask; | |
371 | u32 reg; | |
372 | ||
373 | if (crypto->cmd == SET_KEY) { | |
374 | /* | |
375 | * rt2x00lib can't determine the correct free | |
376 | * key_idx for pairwise keys. We have 2 registers | |
377 | * with key valid bits. The goal is simple, read | |
378 | * the first register, if that is full move to | |
379 | * the next register. | |
380 | * When both registers are full, we drop the key, | |
381 | * otherwise we use the first invalid entry. | |
382 | */ | |
0f829b1d | 383 | rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); |
906c110f ID |
384 | if (reg && reg == ~0) { |
385 | key->hw_key_idx = 32; | |
0f829b1d | 386 | rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); |
906c110f ID |
387 | if (reg && reg == ~0) |
388 | return -ENOSPC; | |
389 | } | |
390 | ||
acaf908d | 391 | key->hw_key_idx += reg ? ffz(reg) : 0; |
906c110f ID |
392 | |
393 | /* | |
394 | * Upload key to hardware | |
395 | */ | |
396 | memcpy(key_entry.key, crypto->key, | |
397 | sizeof(key_entry.key)); | |
398 | memcpy(key_entry.tx_mic, crypto->tx_mic, | |
399 | sizeof(key_entry.tx_mic)); | |
400 | memcpy(key_entry.rx_mic, crypto->rx_mic, | |
401 | sizeof(key_entry.rx_mic)); | |
402 | ||
403 | reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); | |
404 | timeout = REGISTER_TIMEOUT32(sizeof(key_entry)); | |
405 | rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE, | |
406 | USB_VENDOR_REQUEST_OUT, reg, | |
407 | &key_entry, | |
408 | sizeof(key_entry), | |
409 | timeout); | |
410 | ||
411 | /* | |
412 | * Send the address and cipher type to the hardware register. | |
413 | * This data fits within the CSR cache size, so we can use | |
0f829b1d | 414 | * rt2x00usb_register_multiwrite() directly. |
906c110f ID |
415 | */ |
416 | memset(&addr_entry, 0, sizeof(addr_entry)); | |
417 | memcpy(&addr_entry, crypto->address, ETH_ALEN); | |
418 | addr_entry.cipher = crypto->cipher; | |
419 | ||
420 | reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); | |
0f829b1d | 421 | rt2x00usb_register_multiwrite(rt2x00dev, reg, |
906c110f ID |
422 | &addr_entry, sizeof(addr_entry)); |
423 | ||
424 | /* | |
425 | * Enable pairwise lookup table for given BSS idx, | |
426 | * without this received frames will not be decrypted | |
427 | * by the hardware. | |
428 | */ | |
0f829b1d | 429 | rt2x00usb_register_read(rt2x00dev, SEC_CSR4, ®); |
906c110f | 430 | reg |= (1 << crypto->bssidx); |
0f829b1d | 431 | rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg); |
906c110f ID |
432 | |
433 | /* | |
434 | * The driver does not support the IV/EIV generation | |
435 | * in hardware. However it doesn't support the IV/EIV | |
436 | * inside the ieee80211 frame either, but requires it | |
437 | * to be provided seperately for the descriptor. | |
438 | * rt2x00lib will cut the IV/EIV data out of all frames | |
439 | * given to us by mac80211, but we must tell mac80211 | |
440 | * to generate the IV/EIV data. | |
441 | */ | |
442 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
443 | } | |
444 | ||
445 | /* | |
446 | * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate | |
447 | * a particular key is valid. Because using the FIELD32() | |
448 | * defines directly will cause a lot of overhead we use | |
449 | * a calculation to determine the correct bit directly. | |
450 | */ | |
451 | if (key->hw_key_idx < 32) { | |
452 | mask = 1 << key->hw_key_idx; | |
453 | ||
0f829b1d | 454 | rt2x00usb_register_read(rt2x00dev, SEC_CSR2, ®); |
906c110f ID |
455 | if (crypto->cmd == SET_KEY) |
456 | reg |= mask; | |
457 | else if (crypto->cmd == DISABLE_KEY) | |
458 | reg &= ~mask; | |
0f829b1d | 459 | rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg); |
906c110f ID |
460 | } else { |
461 | mask = 1 << (key->hw_key_idx - 32); | |
462 | ||
0f829b1d | 463 | rt2x00usb_register_read(rt2x00dev, SEC_CSR3, ®); |
906c110f ID |
464 | if (crypto->cmd == SET_KEY) |
465 | reg |= mask; | |
466 | else if (crypto->cmd == DISABLE_KEY) | |
467 | reg &= ~mask; | |
0f829b1d | 468 | rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg); |
906c110f ID |
469 | } |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
3a643d24 ID |
474 | static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev, |
475 | const unsigned int filter_flags) | |
476 | { | |
477 | u32 reg; | |
478 | ||
479 | /* | |
480 | * Start configuration steps. | |
481 | * Note that the version error will always be dropped | |
482 | * and broadcast frames will always be accepted since | |
483 | * there is no filter for it at this time. | |
484 | */ | |
0f829b1d | 485 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
3a643d24 ID |
486 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, |
487 | !(filter_flags & FIF_FCSFAIL)); | |
488 | rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, | |
489 | !(filter_flags & FIF_PLCPFAIL)); | |
490 | rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, | |
491 | !(filter_flags & FIF_CONTROL)); | |
492 | rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, | |
493 | !(filter_flags & FIF_PROMISC_IN_BSS)); | |
494 | rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, | |
e0b005fa ID |
495 | !(filter_flags & FIF_PROMISC_IN_BSS) && |
496 | !rt2x00dev->intf_ap_count); | |
3a643d24 ID |
497 | rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); |
498 | rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, | |
499 | !(filter_flags & FIF_ALLMULTI)); | |
500 | rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); | |
501 | rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, | |
502 | !(filter_flags & FIF_CONTROL)); | |
0f829b1d | 503 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
3a643d24 ID |
504 | } |
505 | ||
6bb40dd1 ID |
506 | static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev, |
507 | struct rt2x00_intf *intf, | |
508 | struct rt2x00intf_conf *conf, | |
509 | const unsigned int flags) | |
95ea3627 | 510 | { |
6bb40dd1 ID |
511 | unsigned int beacon_base; |
512 | u32 reg; | |
95ea3627 | 513 | |
6bb40dd1 ID |
514 | if (flags & CONFIG_UPDATE_TYPE) { |
515 | /* | |
516 | * Clear current synchronisation setup. | |
517 | * For the Beacon base registers we only need to clear | |
518 | * the first byte since that byte contains the VALID and OWNER | |
519 | * bits which (when set to 0) will invalidate the entire beacon. | |
520 | */ | |
521 | beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); | |
0f829b1d | 522 | rt2x00usb_register_write(rt2x00dev, beacon_base, 0); |
95ea3627 | 523 | |
6bb40dd1 ID |
524 | /* |
525 | * Enable synchronisation. | |
526 | */ | |
0f829b1d | 527 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
fd3c91c5 | 528 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
6bb40dd1 | 529 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); |
fd3c91c5 | 530 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); |
0f829b1d | 531 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
6bb40dd1 | 532 | } |
95ea3627 | 533 | |
6bb40dd1 ID |
534 | if (flags & CONFIG_UPDATE_MAC) { |
535 | reg = le32_to_cpu(conf->mac[1]); | |
536 | rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); | |
537 | conf->mac[1] = cpu_to_le32(reg); | |
95ea3627 | 538 | |
0f829b1d | 539 | rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2, |
6bb40dd1 ID |
540 | conf->mac, sizeof(conf->mac)); |
541 | } | |
95ea3627 | 542 | |
6bb40dd1 ID |
543 | if (flags & CONFIG_UPDATE_BSSID) { |
544 | reg = le32_to_cpu(conf->bssid[1]); | |
545 | rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); | |
546 | conf->bssid[1] = cpu_to_le32(reg); | |
95ea3627 | 547 | |
0f829b1d | 548 | rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4, |
6bb40dd1 ID |
549 | conf->bssid, sizeof(conf->bssid)); |
550 | } | |
95ea3627 ID |
551 | } |
552 | ||
3a643d24 ID |
553 | static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev, |
554 | struct rt2x00lib_erp *erp) | |
95ea3627 | 555 | { |
95ea3627 | 556 | u32 reg; |
95ea3627 | 557 | |
0f829b1d | 558 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
72810379 | 559 | rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout); |
0f829b1d | 560 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 561 | |
0f829b1d | 562 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); |
4f5af6eb | 563 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, |
72810379 | 564 | !!erp->short_preamble); |
0f829b1d | 565 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); |
95ea3627 | 566 | |
0f829b1d | 567 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); |
95ea3627 | 568 | |
0f829b1d | 569 | rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); |
e4ea1c40 | 570 | rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); |
0f829b1d | 571 | rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); |
95ea3627 | 572 | |
0f829b1d | 573 | rt2x00usb_register_read(rt2x00dev, MAC_CSR8, ®); |
e4ea1c40 ID |
574 | rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); |
575 | rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); | |
576 | rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); | |
0f829b1d | 577 | rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg); |
95ea3627 ID |
578 | } |
579 | ||
580 | static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 581 | struct antenna_setup *ant) |
95ea3627 ID |
582 | { |
583 | u8 r3; | |
584 | u8 r4; | |
585 | u8 r77; | |
2676c94d | 586 | u8 temp; |
95ea3627 ID |
587 | |
588 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
589 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
590 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
591 | ||
592 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
593 | ||
e4cd2ff8 ID |
594 | /* |
595 | * Configure the RX antenna. | |
596 | */ | |
addc81bd | 597 | switch (ant->rx) { |
95ea3627 | 598 | case ANTENNA_HW_DIVERSITY: |
2676c94d MN |
599 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
600 | temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags) | |
8318d78a | 601 | && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ); |
2676c94d | 602 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp); |
95ea3627 ID |
603 | break; |
604 | case ANTENNA_A: | |
2676c94d | 605 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 606 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 607 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
2676c94d MN |
608 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
609 | else | |
610 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); | |
95ea3627 ID |
611 | break; |
612 | case ANTENNA_B: | |
a4fe07d9 | 613 | default: |
2676c94d | 614 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); |
95ea3627 | 615 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0); |
8318d78a | 616 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) |
2676c94d MN |
617 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
618 | else | |
619 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); | |
95ea3627 ID |
620 | break; |
621 | } | |
622 | ||
623 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
624 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
625 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
626 | } | |
627 | ||
628 | static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev, | |
addc81bd | 629 | struct antenna_setup *ant) |
95ea3627 ID |
630 | { |
631 | u8 r3; | |
632 | u8 r4; | |
633 | u8 r77; | |
634 | ||
635 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
636 | rt73usb_bbp_read(rt2x00dev, 4, &r4); | |
637 | rt73usb_bbp_read(rt2x00dev, 77, &r77); | |
638 | ||
639 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0); | |
640 | rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, | |
641 | !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)); | |
642 | ||
e4cd2ff8 ID |
643 | /* |
644 | * Configure the RX antenna. | |
645 | */ | |
addc81bd | 646 | switch (ant->rx) { |
95ea3627 | 647 | case ANTENNA_HW_DIVERSITY: |
2676c94d | 648 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2); |
95ea3627 ID |
649 | break; |
650 | case ANTENNA_A: | |
2676c94d MN |
651 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3); |
652 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); | |
95ea3627 ID |
653 | break; |
654 | case ANTENNA_B: | |
a4fe07d9 | 655 | default: |
2676c94d MN |
656 | rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0); |
657 | rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1); | |
95ea3627 ID |
658 | break; |
659 | } | |
660 | ||
661 | rt73usb_bbp_write(rt2x00dev, 77, r77); | |
662 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
663 | rt73usb_bbp_write(rt2x00dev, 4, r4); | |
664 | } | |
665 | ||
666 | struct antenna_sel { | |
667 | u8 word; | |
668 | /* | |
669 | * value[0] -> non-LNA | |
670 | * value[1] -> LNA | |
671 | */ | |
672 | u8 value[2]; | |
673 | }; | |
674 | ||
675 | static const struct antenna_sel antenna_sel_a[] = { | |
676 | { 96, { 0x58, 0x78 } }, | |
677 | { 104, { 0x38, 0x48 } }, | |
678 | { 75, { 0xfe, 0x80 } }, | |
679 | { 86, { 0xfe, 0x80 } }, | |
680 | { 88, { 0xfe, 0x80 } }, | |
681 | { 35, { 0x60, 0x60 } }, | |
682 | { 97, { 0x58, 0x58 } }, | |
683 | { 98, { 0x58, 0x58 } }, | |
684 | }; | |
685 | ||
686 | static const struct antenna_sel antenna_sel_bg[] = { | |
687 | { 96, { 0x48, 0x68 } }, | |
688 | { 104, { 0x2c, 0x3c } }, | |
689 | { 75, { 0xfe, 0x80 } }, | |
690 | { 86, { 0xfe, 0x80 } }, | |
691 | { 88, { 0xfe, 0x80 } }, | |
692 | { 35, { 0x50, 0x50 } }, | |
693 | { 97, { 0x48, 0x48 } }, | |
694 | { 98, { 0x48, 0x48 } }, | |
695 | }; | |
696 | ||
e4ea1c40 ID |
697 | static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev, |
698 | struct antenna_setup *ant) | |
95ea3627 ID |
699 | { |
700 | const struct antenna_sel *sel; | |
701 | unsigned int lna; | |
702 | unsigned int i; | |
703 | u32 reg; | |
704 | ||
a4fe07d9 ID |
705 | /* |
706 | * We should never come here because rt2x00lib is supposed | |
707 | * to catch this and send us the correct antenna explicitely. | |
708 | */ | |
709 | BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || | |
710 | ant->tx == ANTENNA_SW_DIVERSITY); | |
711 | ||
8318d78a | 712 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
713 | sel = antenna_sel_a; |
714 | lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
95ea3627 ID |
715 | } else { |
716 | sel = antenna_sel_bg; | |
717 | lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
95ea3627 ID |
718 | } |
719 | ||
2676c94d MN |
720 | for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) |
721 | rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); | |
722 | ||
0f829b1d | 723 | rt2x00usb_register_read(rt2x00dev, PHY_CSR0, ®); |
2676c94d | 724 | |
ddc827f9 | 725 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, |
8318d78a | 726 | (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)); |
ddc827f9 | 727 | rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, |
8318d78a | 728 | (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)); |
ddc827f9 | 729 | |
0f829b1d | 730 | rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg); |
95ea3627 ID |
731 | |
732 | if (rt2x00_rf(&rt2x00dev->chip, RF5226) || | |
733 | rt2x00_rf(&rt2x00dev->chip, RF5225)) | |
addc81bd | 734 | rt73usb_config_antenna_5x(rt2x00dev, ant); |
95ea3627 ID |
735 | else if (rt2x00_rf(&rt2x00dev->chip, RF2528) || |
736 | rt2x00_rf(&rt2x00dev->chip, RF2527)) | |
addc81bd | 737 | rt73usb_config_antenna_2x(rt2x00dev, ant); |
95ea3627 ID |
738 | } |
739 | ||
e4ea1c40 | 740 | static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev, |
5c58ee51 | 741 | struct rt2x00lib_conf *libconf) |
e4ea1c40 ID |
742 | { |
743 | u16 eeprom; | |
744 | short lna_gain = 0; | |
745 | ||
746 | if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) { | |
747 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) | |
748 | lna_gain += 14; | |
749 | ||
750 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom); | |
751 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); | |
752 | } else { | |
753 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom); | |
754 | lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); | |
755 | } | |
756 | ||
757 | rt2x00dev->lna_gain = lna_gain; | |
758 | } | |
759 | ||
760 | static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev, | |
761 | struct rf_channel *rf, const int txpower) | |
762 | { | |
763 | u8 r3; | |
764 | u8 r94; | |
765 | u8 smart; | |
766 | ||
767 | rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); | |
768 | rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); | |
769 | ||
770 | smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
771 | rt2x00_rf(&rt2x00dev->chip, RF2527)); | |
772 | ||
773 | rt73usb_bbp_read(rt2x00dev, 3, &r3); | |
774 | rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart); | |
775 | rt73usb_bbp_write(rt2x00dev, 3, r3); | |
776 | ||
777 | r94 = 6; | |
778 | if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94)) | |
779 | r94 += txpower - MAX_TXPOWER; | |
780 | else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) | |
781 | r94 += txpower; | |
782 | rt73usb_bbp_write(rt2x00dev, 94, r94); | |
783 | ||
784 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
785 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
786 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
787 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
788 | ||
789 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
790 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
791 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); | |
792 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
793 | ||
794 | rt73usb_rf_write(rt2x00dev, 1, rf->rf1); | |
795 | rt73usb_rf_write(rt2x00dev, 2, rf->rf2); | |
796 | rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); | |
797 | rt73usb_rf_write(rt2x00dev, 4, rf->rf4); | |
798 | ||
799 | udelay(10); | |
800 | } | |
801 | ||
802 | static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, | |
803 | const int txpower) | |
804 | { | |
805 | struct rf_channel rf; | |
806 | ||
807 | rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); | |
808 | rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); | |
809 | rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); | |
810 | rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); | |
811 | ||
812 | rt73usb_config_channel(rt2x00dev, &rf, txpower); | |
813 | } | |
814 | ||
815 | static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev, | |
816 | struct rt2x00lib_conf *libconf) | |
95ea3627 ID |
817 | { |
818 | u32 reg; | |
819 | ||
0f829b1d | 820 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); |
e4ea1c40 ID |
821 | rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, |
822 | libconf->conf->long_frame_max_tx_count); | |
823 | rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, | |
824 | libconf->conf->short_frame_max_tx_count); | |
0f829b1d | 825 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); |
e4ea1c40 | 826 | } |
95ea3627 | 827 | |
e4ea1c40 ID |
828 | static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev, |
829 | struct rt2x00lib_conf *libconf) | |
830 | { | |
831 | u32 reg; | |
95ea3627 | 832 | |
0f829b1d | 833 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
95ea3627 | 834 | rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); |
0f829b1d | 835 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 836 | |
0f829b1d | 837 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, ®); |
95ea3627 | 838 | rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); |
0f829b1d | 839 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg); |
95ea3627 | 840 | |
0f829b1d | 841 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
5c58ee51 ID |
842 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, |
843 | libconf->conf->beacon_int * 16); | |
0f829b1d | 844 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
95ea3627 ID |
845 | } |
846 | ||
847 | static void rt73usb_config(struct rt2x00_dev *rt2x00dev, | |
6bb40dd1 ID |
848 | struct rt2x00lib_conf *libconf, |
849 | const unsigned int flags) | |
95ea3627 | 850 | { |
ba2ab471 ID |
851 | /* Always recalculate LNA gain before changing configuration */ |
852 | rt73usb_config_lna_gain(rt2x00dev, libconf); | |
853 | ||
e4ea1c40 | 854 | if (flags & IEEE80211_CONF_CHANGE_CHANNEL) |
5c58ee51 ID |
855 | rt73usb_config_channel(rt2x00dev, &libconf->rf, |
856 | libconf->conf->power_level); | |
e4ea1c40 ID |
857 | if ((flags & IEEE80211_CONF_CHANGE_POWER) && |
858 | !(flags & IEEE80211_CONF_CHANGE_CHANNEL)) | |
5c58ee51 | 859 | rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level); |
e4ea1c40 ID |
860 | if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) |
861 | rt73usb_config_retry_limit(rt2x00dev, libconf); | |
862 | if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL) | |
5c58ee51 | 863 | rt73usb_config_duration(rt2x00dev, libconf); |
95ea3627 ID |
864 | } |
865 | ||
95ea3627 ID |
866 | /* |
867 | * Link tuning | |
868 | */ | |
ebcf26da ID |
869 | static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev, |
870 | struct link_qual *qual) | |
95ea3627 ID |
871 | { |
872 | u32 reg; | |
873 | ||
874 | /* | |
875 | * Update FCS error count from register. | |
876 | */ | |
0f829b1d | 877 | rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); |
ebcf26da | 878 | qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); |
95ea3627 ID |
879 | |
880 | /* | |
881 | * Update False CCA count from register. | |
882 | */ | |
0f829b1d | 883 | rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); |
ebcf26da | 884 | qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); |
95ea3627 ID |
885 | } |
886 | ||
887 | static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev) | |
888 | { | |
889 | rt73usb_bbp_write(rt2x00dev, 17, 0x20); | |
890 | rt2x00dev->link.vgc_level = 0x20; | |
891 | } | |
892 | ||
893 | static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev) | |
894 | { | |
895 | int rssi = rt2x00_get_link_rssi(&rt2x00dev->link); | |
896 | u8 r17; | |
897 | u8 up_bound; | |
898 | u8 low_bound; | |
899 | ||
95ea3627 ID |
900 | rt73usb_bbp_read(rt2x00dev, 17, &r17); |
901 | ||
902 | /* | |
903 | * Determine r17 bounds. | |
904 | */ | |
8318d78a | 905 | if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
906 | low_bound = 0x28; |
907 | up_bound = 0x48; | |
908 | ||
909 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { | |
910 | low_bound += 0x10; | |
911 | up_bound += 0x10; | |
912 | } | |
913 | } else { | |
914 | if (rssi > -82) { | |
915 | low_bound = 0x1c; | |
916 | up_bound = 0x40; | |
917 | } else if (rssi > -84) { | |
918 | low_bound = 0x1c; | |
919 | up_bound = 0x20; | |
920 | } else { | |
921 | low_bound = 0x1c; | |
922 | up_bound = 0x1c; | |
923 | } | |
924 | ||
925 | if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { | |
926 | low_bound += 0x14; | |
927 | up_bound += 0x10; | |
928 | } | |
929 | } | |
930 | ||
6bb40dd1 ID |
931 | /* |
932 | * If we are not associated, we should go straight to the | |
933 | * dynamic CCA tuning. | |
934 | */ | |
935 | if (!rt2x00dev->intf_associated) | |
936 | goto dynamic_cca_tune; | |
937 | ||
95ea3627 ID |
938 | /* |
939 | * Special big-R17 for very short distance | |
940 | */ | |
941 | if (rssi > -35) { | |
942 | if (r17 != 0x60) | |
943 | rt73usb_bbp_write(rt2x00dev, 17, 0x60); | |
944 | return; | |
945 | } | |
946 | ||
947 | /* | |
948 | * Special big-R17 for short distance | |
949 | */ | |
950 | if (rssi >= -58) { | |
951 | if (r17 != up_bound) | |
952 | rt73usb_bbp_write(rt2x00dev, 17, up_bound); | |
953 | return; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Special big-R17 for middle-short distance | |
958 | */ | |
959 | if (rssi >= -66) { | |
960 | low_bound += 0x10; | |
961 | if (r17 != low_bound) | |
962 | rt73usb_bbp_write(rt2x00dev, 17, low_bound); | |
963 | return; | |
964 | } | |
965 | ||
966 | /* | |
967 | * Special mid-R17 for middle distance | |
968 | */ | |
969 | if (rssi >= -74) { | |
970 | if (r17 != (low_bound + 0x10)) | |
971 | rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08); | |
972 | return; | |
973 | } | |
974 | ||
975 | /* | |
976 | * Special case: Change up_bound based on the rssi. | |
977 | * Lower up_bound when rssi is weaker then -74 dBm. | |
978 | */ | |
979 | up_bound -= 2 * (-74 - rssi); | |
980 | if (low_bound > up_bound) | |
981 | up_bound = low_bound; | |
982 | ||
983 | if (r17 > up_bound) { | |
984 | rt73usb_bbp_write(rt2x00dev, 17, up_bound); | |
985 | return; | |
986 | } | |
987 | ||
6bb40dd1 ID |
988 | dynamic_cca_tune: |
989 | ||
95ea3627 ID |
990 | /* |
991 | * r17 does not yet exceed upper limit, continue and base | |
992 | * the r17 tuning on the false CCA count. | |
993 | */ | |
ebcf26da | 994 | if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) { |
95ea3627 ID |
995 | r17 += 4; |
996 | if (r17 > up_bound) | |
997 | r17 = up_bound; | |
998 | rt73usb_bbp_write(rt2x00dev, 17, r17); | |
ebcf26da | 999 | } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) { |
95ea3627 ID |
1000 | r17 -= 4; |
1001 | if (r17 < low_bound) | |
1002 | r17 = low_bound; | |
1003 | rt73usb_bbp_write(rt2x00dev, 17, r17); | |
1004 | } | |
1005 | } | |
1006 | ||
1007 | /* | |
a7f3a06c | 1008 | * Firmware functions |
95ea3627 ID |
1009 | */ |
1010 | static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev) | |
1011 | { | |
1012 | return FIRMWARE_RT2571; | |
1013 | } | |
1014 | ||
f160ebcb | 1015 | static u16 rt73usb_get_firmware_crc(const void *data, const size_t len) |
a7f3a06c ID |
1016 | { |
1017 | u16 crc; | |
1018 | ||
1019 | /* | |
1020 | * Use the crc itu-t algorithm. | |
1021 | * The last 2 bytes in the firmware array are the crc checksum itself, | |
1022 | * this means that we should never pass those 2 bytes to the crc | |
1023 | * algorithm. | |
1024 | */ | |
1025 | crc = crc_itu_t(0, data, len - 2); | |
1026 | crc = crc_itu_t_byte(crc, 0); | |
1027 | crc = crc_itu_t_byte(crc, 0); | |
1028 | ||
1029 | return crc; | |
1030 | } | |
1031 | ||
f160ebcb | 1032 | static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data, |
95ea3627 ID |
1033 | const size_t len) |
1034 | { | |
1035 | unsigned int i; | |
1036 | int status; | |
1037 | u32 reg; | |
95ea3627 ID |
1038 | |
1039 | /* | |
1040 | * Wait for stable hardware. | |
1041 | */ | |
1042 | for (i = 0; i < 100; i++) { | |
0f829b1d | 1043 | rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); |
95ea3627 ID |
1044 | if (reg) |
1045 | break; | |
1046 | msleep(1); | |
1047 | } | |
1048 | ||
1049 | if (!reg) { | |
1050 | ERROR(rt2x00dev, "Unstable hardware.\n"); | |
1051 | return -EBUSY; | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * Write firmware to device. | |
95ea3627 | 1056 | */ |
3e0c1abe IM |
1057 | rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE, |
1058 | USB_VENDOR_REQUEST_OUT, | |
1059 | FIRMWARE_IMAGE_BASE, | |
1060 | data, len, | |
1061 | REGISTER_TIMEOUT32(len)); | |
95ea3627 ID |
1062 | |
1063 | /* | |
1064 | * Send firmware request to device to load firmware, | |
1065 | * we need to specify a long timeout time. | |
1066 | */ | |
1067 | status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, | |
3b640f21 | 1068 | 0, USB_MODE_FIRMWARE, |
95ea3627 ID |
1069 | REGISTER_TIMEOUT_FIRMWARE); |
1070 | if (status < 0) { | |
1071 | ERROR(rt2x00dev, "Failed to write Firmware to device.\n"); | |
1072 | return status; | |
1073 | } | |
1074 | ||
95ea3627 ID |
1075 | return 0; |
1076 | } | |
1077 | ||
a7f3a06c ID |
1078 | /* |
1079 | * Initialization functions. | |
1080 | */ | |
95ea3627 ID |
1081 | static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev) |
1082 | { | |
1083 | u32 reg; | |
1084 | ||
0f829b1d | 1085 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
95ea3627 ID |
1086 | rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); |
1087 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); | |
1088 | rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); | |
0f829b1d | 1089 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 | 1090 | |
0f829b1d | 1091 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, ®); |
95ea3627 ID |
1092 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ |
1093 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); | |
1094 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ | |
1095 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); | |
1096 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ | |
1097 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); | |
1098 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ | |
1099 | rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); | |
0f829b1d | 1100 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg); |
95ea3627 ID |
1101 | |
1102 | /* | |
1103 | * CCK TXD BBP registers | |
1104 | */ | |
0f829b1d | 1105 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, ®); |
95ea3627 ID |
1106 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); |
1107 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); | |
1108 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); | |
1109 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); | |
1110 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); | |
1111 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); | |
1112 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); | |
1113 | rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); | |
0f829b1d | 1114 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg); |
95ea3627 ID |
1115 | |
1116 | /* | |
1117 | * OFDM TXD BBP registers | |
1118 | */ | |
0f829b1d | 1119 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, ®); |
95ea3627 ID |
1120 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); |
1121 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); | |
1122 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); | |
1123 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); | |
1124 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); | |
1125 | rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); | |
0f829b1d | 1126 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg); |
95ea3627 | 1127 | |
0f829b1d | 1128 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, ®); |
95ea3627 ID |
1129 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); |
1130 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); | |
1131 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); | |
1132 | rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); | |
0f829b1d | 1133 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg); |
95ea3627 | 1134 | |
0f829b1d | 1135 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, ®); |
95ea3627 ID |
1136 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); |
1137 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); | |
1138 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); | |
1139 | rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); | |
0f829b1d | 1140 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg); |
95ea3627 | 1141 | |
0f829b1d | 1142 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
1f909162 ID |
1143 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); |
1144 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); | |
1145 | rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); | |
1146 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1147 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
1148 | rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); | |
0f829b1d | 1149 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
1f909162 | 1150 | |
0f829b1d | 1151 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); |
95ea3627 | 1152 | |
0f829b1d | 1153 | rt2x00usb_register_read(rt2x00dev, MAC_CSR6, ®); |
95ea3627 | 1154 | rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); |
0f829b1d | 1155 | rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg); |
95ea3627 | 1156 | |
0f829b1d | 1157 | rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); |
95ea3627 ID |
1158 | |
1159 | if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) | |
1160 | return -EBUSY; | |
1161 | ||
0f829b1d | 1162 | rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); |
95ea3627 ID |
1163 | |
1164 | /* | |
1165 | * Invalidate all Shared Keys (SEC_CSR0), | |
1166 | * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) | |
1167 | */ | |
0f829b1d ID |
1168 | rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); |
1169 | rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); | |
1170 | rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); | |
95ea3627 ID |
1171 | |
1172 | reg = 0x000023b0; | |
1173 | if (rt2x00_rf(&rt2x00dev->chip, RF5225) || | |
1174 | rt2x00_rf(&rt2x00dev->chip, RF2527)) | |
1175 | rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1); | |
0f829b1d | 1176 | rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg); |
95ea3627 | 1177 | |
0f829b1d ID |
1178 | rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); |
1179 | rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); | |
1180 | rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); | |
95ea3627 | 1181 | |
0f829b1d | 1182 | rt2x00usb_register_read(rt2x00dev, MAC_CSR9, ®); |
95ea3627 | 1183 | rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); |
0f829b1d | 1184 | rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg); |
95ea3627 | 1185 | |
6bb40dd1 ID |
1186 | /* |
1187 | * Clear all beacons | |
1188 | * For the Beacon base registers we only need to clear | |
1189 | * the first byte since that byte contains the VALID and OWNER | |
1190 | * bits which (when set to 0) will invalidate the entire beacon. | |
1191 | */ | |
0f829b1d ID |
1192 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); |
1193 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); | |
1194 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); | |
1195 | rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); | |
6bb40dd1 | 1196 | |
95ea3627 ID |
1197 | /* |
1198 | * We must clear the error counters. | |
1199 | * These registers are cleared on read, | |
1200 | * so we may pass a useless variable to store the value. | |
1201 | */ | |
0f829b1d ID |
1202 | rt2x00usb_register_read(rt2x00dev, STA_CSR0, ®); |
1203 | rt2x00usb_register_read(rt2x00dev, STA_CSR1, ®); | |
1204 | rt2x00usb_register_read(rt2x00dev, STA_CSR2, ®); | |
95ea3627 ID |
1205 | |
1206 | /* | |
1207 | * Reset MAC and BBP registers. | |
1208 | */ | |
0f829b1d | 1209 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1210 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); |
1211 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); | |
0f829b1d | 1212 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1213 | |
0f829b1d | 1214 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 ID |
1215 | rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); |
1216 | rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); | |
0f829b1d | 1217 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 | 1218 | |
0f829b1d | 1219 | rt2x00usb_register_read(rt2x00dev, MAC_CSR1, ®); |
95ea3627 | 1220 | rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); |
0f829b1d | 1221 | rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg); |
95ea3627 ID |
1222 | |
1223 | return 0; | |
1224 | } | |
1225 | ||
2b08da3f | 1226 | static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
1227 | { |
1228 | unsigned int i; | |
95ea3627 ID |
1229 | u8 value; |
1230 | ||
1231 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
1232 | rt73usb_bbp_read(rt2x00dev, 0, &value); | |
1233 | if ((value != 0xff) && (value != 0x00)) | |
2b08da3f | 1234 | return 0; |
95ea3627 ID |
1235 | udelay(REGISTER_BUSY_DELAY); |
1236 | } | |
1237 | ||
1238 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | |
1239 | return -EACCES; | |
2b08da3f ID |
1240 | } |
1241 | ||
1242 | static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev) | |
1243 | { | |
1244 | unsigned int i; | |
1245 | u16 eeprom; | |
1246 | u8 reg_id; | |
1247 | u8 value; | |
1248 | ||
1249 | if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev))) | |
1250 | return -EACCES; | |
95ea3627 | 1251 | |
95ea3627 ID |
1252 | rt73usb_bbp_write(rt2x00dev, 3, 0x80); |
1253 | rt73usb_bbp_write(rt2x00dev, 15, 0x30); | |
1254 | rt73usb_bbp_write(rt2x00dev, 21, 0xc8); | |
1255 | rt73usb_bbp_write(rt2x00dev, 22, 0x38); | |
1256 | rt73usb_bbp_write(rt2x00dev, 23, 0x06); | |
1257 | rt73usb_bbp_write(rt2x00dev, 24, 0xfe); | |
1258 | rt73usb_bbp_write(rt2x00dev, 25, 0x0a); | |
1259 | rt73usb_bbp_write(rt2x00dev, 26, 0x0d); | |
1260 | rt73usb_bbp_write(rt2x00dev, 32, 0x0b); | |
1261 | rt73usb_bbp_write(rt2x00dev, 34, 0x12); | |
1262 | rt73usb_bbp_write(rt2x00dev, 37, 0x07); | |
1263 | rt73usb_bbp_write(rt2x00dev, 39, 0xf8); | |
1264 | rt73usb_bbp_write(rt2x00dev, 41, 0x60); | |
1265 | rt73usb_bbp_write(rt2x00dev, 53, 0x10); | |
1266 | rt73usb_bbp_write(rt2x00dev, 54, 0x18); | |
1267 | rt73usb_bbp_write(rt2x00dev, 60, 0x10); | |
1268 | rt73usb_bbp_write(rt2x00dev, 61, 0x04); | |
1269 | rt73usb_bbp_write(rt2x00dev, 62, 0x04); | |
1270 | rt73usb_bbp_write(rt2x00dev, 75, 0xfe); | |
1271 | rt73usb_bbp_write(rt2x00dev, 86, 0xfe); | |
1272 | rt73usb_bbp_write(rt2x00dev, 88, 0xfe); | |
1273 | rt73usb_bbp_write(rt2x00dev, 90, 0x0f); | |
1274 | rt73usb_bbp_write(rt2x00dev, 99, 0x00); | |
1275 | rt73usb_bbp_write(rt2x00dev, 102, 0x16); | |
1276 | rt73usb_bbp_write(rt2x00dev, 107, 0x04); | |
1277 | ||
95ea3627 ID |
1278 | for (i = 0; i < EEPROM_BBP_SIZE; i++) { |
1279 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); | |
1280 | ||
1281 | if (eeprom != 0xffff && eeprom != 0x0000) { | |
1282 | reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID); | |
1283 | value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE); | |
95ea3627 ID |
1284 | rt73usb_bbp_write(rt2x00dev, reg_id, value); |
1285 | } | |
1286 | } | |
95ea3627 ID |
1287 | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | /* | |
1292 | * Device state switch handlers. | |
1293 | */ | |
1294 | static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev, | |
1295 | enum dev_state state) | |
1296 | { | |
1297 | u32 reg; | |
1298 | ||
0f829b1d | 1299 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, ®); |
95ea3627 | 1300 | rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, |
2b08da3f ID |
1301 | (state == STATE_RADIO_RX_OFF) || |
1302 | (state == STATE_RADIO_RX_OFF_LINK)); | |
0f829b1d | 1303 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg); |
95ea3627 ID |
1304 | } |
1305 | ||
1306 | static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) | |
1307 | { | |
1308 | /* | |
1309 | * Initialize all registers. | |
1310 | */ | |
2b08da3f ID |
1311 | if (unlikely(rt73usb_init_registers(rt2x00dev) || |
1312 | rt73usb_init_bbp(rt2x00dev))) | |
95ea3627 | 1313 | return -EIO; |
95ea3627 | 1314 | |
95ea3627 ID |
1315 | return 0; |
1316 | } | |
1317 | ||
1318 | static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) | |
1319 | { | |
0f829b1d | 1320 | rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
95ea3627 ID |
1321 | |
1322 | /* | |
1323 | * Disable synchronisation. | |
1324 | */ | |
0f829b1d | 1325 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0); |
95ea3627 ID |
1326 | |
1327 | rt2x00usb_disable_radio(rt2x00dev); | |
1328 | } | |
1329 | ||
1330 | static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) | |
1331 | { | |
1332 | u32 reg; | |
1333 | unsigned int i; | |
1334 | char put_to_sleep; | |
95ea3627 ID |
1335 | |
1336 | put_to_sleep = (state != STATE_AWAKE); | |
1337 | ||
0f829b1d | 1338 | rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®); |
95ea3627 ID |
1339 | rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); |
1340 | rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); | |
0f829b1d | 1341 | rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg); |
95ea3627 ID |
1342 | |
1343 | /* | |
1344 | * Device is not guaranteed to be in the requested state yet. | |
1345 | * We must wait until the register indicates that the | |
1346 | * device has entered the correct state. | |
1347 | */ | |
1348 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | |
0f829b1d | 1349 | rt2x00usb_register_read(rt2x00dev, MAC_CSR12, ®); |
2b08da3f ID |
1350 | state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); |
1351 | if (state == !put_to_sleep) | |
95ea3627 ID |
1352 | return 0; |
1353 | msleep(10); | |
1354 | } | |
1355 | ||
95ea3627 ID |
1356 | return -EBUSY; |
1357 | } | |
1358 | ||
1359 | static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev, | |
1360 | enum dev_state state) | |
1361 | { | |
1362 | int retval = 0; | |
1363 | ||
1364 | switch (state) { | |
1365 | case STATE_RADIO_ON: | |
1366 | retval = rt73usb_enable_radio(rt2x00dev); | |
1367 | break; | |
1368 | case STATE_RADIO_OFF: | |
1369 | rt73usb_disable_radio(rt2x00dev); | |
1370 | break; | |
1371 | case STATE_RADIO_RX_ON: | |
61667d8d | 1372 | case STATE_RADIO_RX_ON_LINK: |
95ea3627 | 1373 | case STATE_RADIO_RX_OFF: |
61667d8d | 1374 | case STATE_RADIO_RX_OFF_LINK: |
2b08da3f ID |
1375 | rt73usb_toggle_rx(rt2x00dev, state); |
1376 | break; | |
1377 | case STATE_RADIO_IRQ_ON: | |
1378 | case STATE_RADIO_IRQ_OFF: | |
1379 | /* No support, but no error either */ | |
95ea3627 ID |
1380 | break; |
1381 | case STATE_DEEP_SLEEP: | |
1382 | case STATE_SLEEP: | |
1383 | case STATE_STANDBY: | |
1384 | case STATE_AWAKE: | |
1385 | retval = rt73usb_set_state(rt2x00dev, state); | |
1386 | break; | |
1387 | default: | |
1388 | retval = -ENOTSUPP; | |
1389 | break; | |
1390 | } | |
1391 | ||
2b08da3f ID |
1392 | if (unlikely(retval)) |
1393 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", | |
1394 | state, retval); | |
1395 | ||
95ea3627 ID |
1396 | return retval; |
1397 | } | |
1398 | ||
1399 | /* | |
1400 | * TX descriptor initialization | |
1401 | */ | |
1402 | static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |
906c110f ID |
1403 | struct sk_buff *skb, |
1404 | struct txentry_desc *txdesc) | |
95ea3627 | 1405 | { |
181d6902 | 1406 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
dd3193e1 | 1407 | __le32 *txd = skbdesc->desc; |
95ea3627 ID |
1408 | u32 word; |
1409 | ||
1410 | /* | |
1411 | * Start writing the descriptor words. | |
1412 | */ | |
1413 | rt2x00_desc_read(txd, 1, &word); | |
181d6902 ID |
1414 | rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); |
1415 | rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); | |
1416 | rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min); | |
1417 | rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max); | |
906c110f | 1418 | rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); |
5adf6d63 ID |
1419 | rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, |
1420 | test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); | |
95ea3627 ID |
1421 | rt2x00_desc_write(txd, 1, word); |
1422 | ||
1423 | rt2x00_desc_read(txd, 2, &word); | |
181d6902 ID |
1424 | rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); |
1425 | rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); | |
1426 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); | |
1427 | rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); | |
95ea3627 ID |
1428 | rt2x00_desc_write(txd, 2, word); |
1429 | ||
906c110f ID |
1430 | if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { |
1431 | _rt2x00_desc_write(txd, 3, skbdesc->iv); | |
1432 | _rt2x00_desc_write(txd, 4, skbdesc->eiv); | |
1433 | } | |
1434 | ||
95ea3627 ID |
1435 | rt2x00_desc_read(txd, 5, &word); |
1436 | rt2x00_set_field32(&word, TXD_W5_TX_POWER, | |
ac1aa7e4 | 1437 | TXPOWER_TO_DEV(rt2x00dev->tx_power)); |
95ea3627 ID |
1438 | rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); |
1439 | rt2x00_desc_write(txd, 5, word); | |
1440 | ||
1441 | rt2x00_desc_read(txd, 0, &word); | |
1442 | rt2x00_set_field32(&word, TXD_W0_BURST, | |
181d6902 | 1443 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); |
95ea3627 ID |
1444 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); |
1445 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | |
181d6902 | 1446 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
95ea3627 | 1447 | rt2x00_set_field32(&word, TXD_W0_ACK, |
181d6902 | 1448 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
95ea3627 | 1449 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
181d6902 | 1450 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
95ea3627 | 1451 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
181d6902 ID |
1452 | test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags)); |
1453 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); | |
95ea3627 | 1454 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
61486e0f | 1455 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
906c110f ID |
1456 | rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, |
1457 | test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); | |
1458 | rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, | |
1459 | test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); | |
1460 | rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); | |
1abc3656 | 1461 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len); |
95ea3627 | 1462 | rt2x00_set_field32(&word, TXD_W0_BURST2, |
181d6902 | 1463 | test_bit(ENTRY_TXD_BURST, &txdesc->flags)); |
906c110f | 1464 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); |
95ea3627 ID |
1465 | rt2x00_desc_write(txd, 0, word); |
1466 | } | |
1467 | ||
bd88a781 ID |
1468 | /* |
1469 | * TX data initialization | |
1470 | */ | |
1471 | static void rt73usb_write_beacon(struct queue_entry *entry) | |
1472 | { | |
1473 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | |
1474 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | |
1475 | unsigned int beacon_base; | |
1476 | u32 reg; | |
1477 | ||
1478 | /* | |
1479 | * Add the descriptor in front of the skb. | |
1480 | */ | |
1481 | skb_push(entry->skb, entry->queue->desc_size); | |
1482 | memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len); | |
1483 | skbdesc->desc = entry->skb->data; | |
1484 | ||
1485 | /* | |
1486 | * Disable beaconing while we are reloading the beacon data, | |
1487 | * otherwise we might be sending out invalid data. | |
1488 | */ | |
0f829b1d | 1489 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
bd88a781 ID |
1490 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); |
1491 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); | |
1492 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); | |
0f829b1d | 1493 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
bd88a781 ID |
1494 | |
1495 | /* | |
1496 | * Write entire beacon with descriptor to register. | |
1497 | */ | |
1498 | beacon_base = HW_BEACON_OFFSET(entry->entry_idx); | |
3e0c1abe IM |
1499 | rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE, |
1500 | USB_VENDOR_REQUEST_OUT, beacon_base, | |
1501 | entry->skb->data, entry->skb->len, | |
1502 | REGISTER_TIMEOUT32(entry->skb->len)); | |
bd88a781 ID |
1503 | |
1504 | /* | |
1505 | * Clean up the beacon skb. | |
1506 | */ | |
1507 | dev_kfree_skb(entry->skb); | |
1508 | entry->skb = NULL; | |
1509 | } | |
1510 | ||
dd9fa2d2 | 1511 | static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev, |
b242e891 | 1512 | struct sk_buff *skb) |
dd9fa2d2 ID |
1513 | { |
1514 | int length; | |
1515 | ||
1516 | /* | |
1517 | * The length _must_ be a multiple of 4, | |
1518 | * but it must _not_ be a multiple of the USB packet size. | |
1519 | */ | |
1520 | length = roundup(skb->len, 4); | |
b242e891 | 1521 | length += (4 * !(length % rt2x00dev->usb_maxpacket)); |
dd9fa2d2 ID |
1522 | |
1523 | return length; | |
1524 | } | |
1525 | ||
95ea3627 | 1526 | static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev, |
e58c6aca | 1527 | const enum data_queue_qid queue) |
95ea3627 ID |
1528 | { |
1529 | u32 reg; | |
1530 | ||
f019d514 ID |
1531 | if (queue != QID_BEACON) { |
1532 | rt2x00usb_kick_tx_queue(rt2x00dev, queue); | |
95ea3627 | 1533 | return; |
f019d514 | 1534 | } |
95ea3627 ID |
1535 | |
1536 | /* | |
1537 | * For Wi-Fi faily generated beacons between participating stations. | |
1538 | * Set TBTT phase adaptive adjustment step to 8us (default 16us) | |
1539 | */ | |
0f829b1d | 1540 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); |
95ea3627 | 1541 | |
0f829b1d | 1542 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, ®); |
95ea3627 | 1543 | if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) { |
8af244cc ID |
1544 | rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); |
1545 | rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); | |
95ea3627 | 1546 | rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); |
0f829b1d | 1547 | rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); |
95ea3627 ID |
1548 | } |
1549 | } | |
1550 | ||
1551 | /* | |
1552 | * RX control handlers | |
1553 | */ | |
1554 | static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) | |
1555 | { | |
ba2ab471 | 1556 | u8 offset = rt2x00dev->lna_gain; |
95ea3627 ID |
1557 | u8 lna; |
1558 | ||
1559 | lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA); | |
1560 | switch (lna) { | |
1561 | case 3: | |
ba2ab471 | 1562 | offset += 90; |
95ea3627 ID |
1563 | break; |
1564 | case 2: | |
ba2ab471 | 1565 | offset += 74; |
95ea3627 ID |
1566 | break; |
1567 | case 1: | |
ba2ab471 | 1568 | offset += 64; |
95ea3627 ID |
1569 | break; |
1570 | default: | |
1571 | return 0; | |
1572 | } | |
1573 | ||
8318d78a | 1574 | if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) { |
95ea3627 ID |
1575 | if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) { |
1576 | if (lna == 3 || lna == 2) | |
1577 | offset += 10; | |
1578 | } else { | |
1579 | if (lna == 3) | |
1580 | offset += 6; | |
1581 | else if (lna == 2) | |
1582 | offset += 8; | |
1583 | } | |
95ea3627 ID |
1584 | } |
1585 | ||
1586 | return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; | |
1587 | } | |
1588 | ||
181d6902 | 1589 | static void rt73usb_fill_rxdone(struct queue_entry *entry, |
55887511 | 1590 | struct rxdone_entry_desc *rxdesc) |
95ea3627 | 1591 | { |
906c110f | 1592 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
181d6902 | 1593 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); |
4bd7c452 | 1594 | __le32 *rxd = (__le32 *)entry->skb->data; |
95ea3627 ID |
1595 | u32 word0; |
1596 | u32 word1; | |
1597 | ||
f855c10b | 1598 | /* |
a26cbc65 GW |
1599 | * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of |
1600 | * frame data in rt2x00usb. | |
f855c10b | 1601 | */ |
a26cbc65 | 1602 | memcpy(skbdesc->desc, rxd, skbdesc->desc_len); |
70a96109 | 1603 | rxd = (__le32 *)skbdesc->desc; |
f855c10b ID |
1604 | |
1605 | /* | |
70a96109 | 1606 | * It is now safe to read the descriptor on all architectures. |
f855c10b | 1607 | */ |
95ea3627 ID |
1608 | rt2x00_desc_read(rxd, 0, &word0); |
1609 | rt2x00_desc_read(rxd, 1, &word1); | |
1610 | ||
4150c572 | 1611 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
181d6902 | 1612 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
95ea3627 | 1613 | |
906c110f ID |
1614 | if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { |
1615 | rxdesc->cipher = | |
1616 | rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); | |
1617 | rxdesc->cipher_status = | |
1618 | rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); | |
1619 | } | |
1620 | ||
1621 | if (rxdesc->cipher != CIPHER_NONE) { | |
1622 | _rt2x00_desc_read(rxd, 2, &rxdesc->iv); | |
1623 | _rt2x00_desc_read(rxd, 3, &rxdesc->eiv); | |
1624 | _rt2x00_desc_read(rxd, 4, &rxdesc->icv); | |
1625 | ||
1626 | /* | |
1627 | * Hardware has stripped IV/EIV data from 802.11 frame during | |
1628 | * decryption. It has provided the data seperately but rt2x00lib | |
1629 | * should decide if it should be reinserted. | |
1630 | */ | |
1631 | rxdesc->flags |= RX_FLAG_IV_STRIPPED; | |
1632 | ||
1633 | /* | |
1634 | * FIXME: Legacy driver indicates that the frame does | |
1635 | * contain the Michael Mic. Unfortunately, in rt2x00 | |
1636 | * the MIC seems to be missing completely... | |
1637 | */ | |
1638 | rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; | |
1639 | ||
1640 | if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) | |
1641 | rxdesc->flags |= RX_FLAG_DECRYPTED; | |
1642 | else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) | |
1643 | rxdesc->flags |= RX_FLAG_MMIC_ERROR; | |
1644 | } | |
1645 | ||
95ea3627 ID |
1646 | /* |
1647 | * Obtain the status about this packet. | |
89993890 ID |
1648 | * When frame was received with an OFDM bitrate, |
1649 | * the signal is the PLCP value. If it was received with | |
1650 | * a CCK bitrate the signal is the rate in 100kbit/s. | |
95ea3627 | 1651 | */ |
181d6902 | 1652 | rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); |
906c110f | 1653 | rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1); |
181d6902 | 1654 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
19d30e02 | 1655 | |
19d30e02 ID |
1656 | if (rt2x00_get_field32(word0, RXD_W0_OFDM)) |
1657 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; | |
6c6aa3c0 ID |
1658 | else |
1659 | rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; | |
19d30e02 ID |
1660 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1661 | rxdesc->dev_flags |= RXDONE_MY_BSS; | |
181d6902 | 1662 | |
2ae23854 | 1663 | /* |
70a96109 | 1664 | * Set skb pointers, and update frame information. |
2ae23854 | 1665 | */ |
70a96109 | 1666 | skb_pull(entry->skb, entry->queue->desc_size); |
2ae23854 | 1667 | skb_trim(entry->skb, rxdesc->size); |
95ea3627 ID |
1668 | } |
1669 | ||
1670 | /* | |
1671 | * Device probe functions. | |
1672 | */ | |
1673 | static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |
1674 | { | |
1675 | u16 word; | |
1676 | u8 *mac; | |
1677 | s8 value; | |
1678 | ||
1679 | rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE); | |
1680 | ||
1681 | /* | |
1682 | * Start validation of the data that has been read. | |
1683 | */ | |
1684 | mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); | |
1685 | if (!is_valid_ether_addr(mac)) { | |
1686 | random_ether_addr(mac); | |
e174961c | 1687 | EEPROM(rt2x00dev, "MAC: %pM\n", mac); |
95ea3627 ID |
1688 | } |
1689 | ||
1690 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); | |
1691 | if (word == 0xffff) { | |
1692 | rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2); | |
362f3b6b ID |
1693 | rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, |
1694 | ANTENNA_B); | |
1695 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, | |
1696 | ANTENNA_B); | |
95ea3627 ID |
1697 | rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0); |
1698 | rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0); | |
1699 | rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0); | |
1700 | rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226); | |
1701 | rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); | |
1702 | EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); | |
1703 | } | |
1704 | ||
1705 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word); | |
1706 | if (word == 0xffff) { | |
1707 | rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0); | |
1708 | rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); | |
1709 | EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); | |
1710 | } | |
1711 | ||
1712 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word); | |
1713 | if (word == 0xffff) { | |
1714 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0); | |
1715 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0); | |
1716 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0); | |
1717 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0); | |
1718 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0); | |
1719 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0); | |
1720 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0); | |
1721 | rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0); | |
1722 | rt2x00_set_field16(&word, EEPROM_LED_LED_MODE, | |
1723 | LED_MODE_DEFAULT); | |
1724 | rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); | |
1725 | EEPROM(rt2x00dev, "Led: 0x%04x\n", word); | |
1726 | } | |
1727 | ||
1728 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); | |
1729 | if (word == 0xffff) { | |
1730 | rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); | |
1731 | rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0); | |
1732 | rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); | |
1733 | EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); | |
1734 | } | |
1735 | ||
1736 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word); | |
1737 | if (word == 0xffff) { | |
1738 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1739 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1740 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1741 | EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); | |
1742 | } else { | |
1743 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1); | |
1744 | if (value < -10 || value > 10) | |
1745 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0); | |
1746 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2); | |
1747 | if (value < -10 || value > 10) | |
1748 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0); | |
1749 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); | |
1750 | } | |
1751 | ||
1752 | rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word); | |
1753 | if (word == 0xffff) { | |
1754 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1755 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1756 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
417f412f | 1757 | EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); |
95ea3627 ID |
1758 | } else { |
1759 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1); | |
1760 | if (value < -10 || value > 10) | |
1761 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0); | |
1762 | value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2); | |
1763 | if (value < -10 || value > 10) | |
1764 | rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0); | |
1765 | rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); | |
1766 | } | |
1767 | ||
1768 | return 0; | |
1769 | } | |
1770 | ||
1771 | static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev) | |
1772 | { | |
1773 | u32 reg; | |
1774 | u16 value; | |
1775 | u16 eeprom; | |
1776 | ||
1777 | /* | |
1778 | * Read EEPROM word for configuration. | |
1779 | */ | |
1780 | rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom); | |
1781 | ||
1782 | /* | |
1783 | * Identify RF chipset. | |
1784 | */ | |
1785 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); | |
0f829b1d | 1786 | rt2x00usb_register_read(rt2x00dev, MAC_CSR0, ®); |
95ea3627 ID |
1787 | rt2x00_set_chip(rt2x00dev, RT2571, value, reg); |
1788 | ||
755a957d | 1789 | if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) { |
95ea3627 ID |
1790 | ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); |
1791 | return -ENODEV; | |
1792 | } | |
1793 | ||
1794 | if (!rt2x00_rf(&rt2x00dev->chip, RF5226) && | |
1795 | !rt2x00_rf(&rt2x00dev->chip, RF2528) && | |
1796 | !rt2x00_rf(&rt2x00dev->chip, RF5225) && | |
1797 | !rt2x00_rf(&rt2x00dev->chip, RF2527)) { | |
1798 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); | |
1799 | return -ENODEV; | |
1800 | } | |
1801 | ||
1802 | /* | |
1803 | * Identify default antenna configuration. | |
1804 | */ | |
addc81bd | 1805 | rt2x00dev->default_ant.tx = |
95ea3627 | 1806 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT); |
addc81bd | 1807 | rt2x00dev->default_ant.rx = |
95ea3627 ID |
1808 | rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT); |
1809 | ||
1810 | /* | |
1811 | * Read the Frame type. | |
1812 | */ | |
1813 | if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE)) | |
1814 | __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags); | |
1815 | ||
1816 | /* | |
1817 | * Read frequency offset. | |
1818 | */ | |
1819 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | |
1820 | rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); | |
1821 | ||
1822 | /* | |
1823 | * Read external LNA informations. | |
1824 | */ | |
1825 | rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom); | |
1826 | ||
1827 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) { | |
1828 | __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags); | |
1829 | __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags); | |
1830 | } | |
1831 | ||
1832 | /* | |
1833 | * Store led settings, for correct led behaviour. | |
1834 | */ | |
771fd565 | 1835 | #ifdef CONFIG_RT2X00_LIB_LEDS |
95ea3627 ID |
1836 | rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom); |
1837 | ||
475433be ID |
1838 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
1839 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); | |
1840 | if (value == LED_MODE_SIGNAL_STRENGTH) | |
1841 | rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual, | |
1842 | LED_TYPE_QUALITY); | |
a9450b70 ID |
1843 | |
1844 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); | |
1845 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, | |
95ea3627 ID |
1846 | rt2x00_get_field16(eeprom, |
1847 | EEPROM_LED_POLARITY_GPIO_0)); | |
a9450b70 | 1848 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, |
95ea3627 ID |
1849 | rt2x00_get_field16(eeprom, |
1850 | EEPROM_LED_POLARITY_GPIO_1)); | |
a9450b70 | 1851 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, |
95ea3627 ID |
1852 | rt2x00_get_field16(eeprom, |
1853 | EEPROM_LED_POLARITY_GPIO_2)); | |
a9450b70 | 1854 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, |
95ea3627 ID |
1855 | rt2x00_get_field16(eeprom, |
1856 | EEPROM_LED_POLARITY_GPIO_3)); | |
a9450b70 | 1857 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, |
95ea3627 ID |
1858 | rt2x00_get_field16(eeprom, |
1859 | EEPROM_LED_POLARITY_GPIO_4)); | |
a9450b70 | 1860 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, |
95ea3627 | 1861 | rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT)); |
a9450b70 | 1862 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, |
95ea3627 ID |
1863 | rt2x00_get_field16(eeprom, |
1864 | EEPROM_LED_POLARITY_RDY_G)); | |
a9450b70 | 1865 | rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, |
95ea3627 ID |
1866 | rt2x00_get_field16(eeprom, |
1867 | EEPROM_LED_POLARITY_RDY_A)); | |
771fd565 | 1868 | #endif /* CONFIG_RT2X00_LIB_LEDS */ |
95ea3627 ID |
1869 | |
1870 | return 0; | |
1871 | } | |
1872 | ||
1873 | /* | |
1874 | * RF value list for RF2528 | |
1875 | * Supports: 2.4 GHz | |
1876 | */ | |
1877 | static const struct rf_channel rf_vals_bg_2528[] = { | |
1878 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1879 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1880 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1881 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1882 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1883 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1884 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1885 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1886 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1887 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
1888 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
1889 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
1890 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
1891 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
1892 | }; | |
1893 | ||
1894 | /* | |
1895 | * RF value list for RF5226 | |
1896 | * Supports: 2.4 GHz & 5.2 GHz | |
1897 | */ | |
1898 | static const struct rf_channel rf_vals_5226[] = { | |
1899 | { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b }, | |
1900 | { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f }, | |
1901 | { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b }, | |
1902 | { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f }, | |
1903 | { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b }, | |
1904 | { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f }, | |
1905 | { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b }, | |
1906 | { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f }, | |
1907 | { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b }, | |
1908 | { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f }, | |
1909 | { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b }, | |
1910 | { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f }, | |
1911 | { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b }, | |
1912 | { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 }, | |
1913 | ||
1914 | /* 802.11 UNI / HyperLan 2 */ | |
1915 | { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 }, | |
1916 | { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 }, | |
1917 | { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b }, | |
1918 | { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 }, | |
1919 | { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b }, | |
1920 | { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 }, | |
1921 | { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 }, | |
1922 | { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b }, | |
1923 | ||
1924 | /* 802.11 HyperLan 2 */ | |
1925 | { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 }, | |
1926 | { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b }, | |
1927 | { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 }, | |
1928 | { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b }, | |
1929 | { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 }, | |
1930 | { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 }, | |
1931 | { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b }, | |
1932 | { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 }, | |
1933 | { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b }, | |
1934 | { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 }, | |
1935 | ||
1936 | /* 802.11 UNII */ | |
1937 | { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 }, | |
1938 | { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f }, | |
1939 | { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 }, | |
1940 | { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 }, | |
1941 | { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f }, | |
1942 | { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 }, | |
1943 | ||
1944 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
1945 | { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b }, | |
1946 | { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 }, | |
1947 | { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b }, | |
1948 | { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 }, | |
1949 | }; | |
1950 | ||
1951 | /* | |
1952 | * RF value list for RF5225 & RF2527 | |
1953 | * Supports: 2.4 GHz & 5.2 GHz | |
1954 | */ | |
1955 | static const struct rf_channel rf_vals_5225_2527[] = { | |
1956 | { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b }, | |
1957 | { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f }, | |
1958 | { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b }, | |
1959 | { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f }, | |
1960 | { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b }, | |
1961 | { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f }, | |
1962 | { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b }, | |
1963 | { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f }, | |
1964 | { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b }, | |
1965 | { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f }, | |
1966 | { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b }, | |
1967 | { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f }, | |
1968 | { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b }, | |
1969 | { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 }, | |
1970 | ||
1971 | /* 802.11 UNI / HyperLan 2 */ | |
1972 | { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 }, | |
1973 | { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 }, | |
1974 | { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b }, | |
1975 | { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 }, | |
1976 | { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b }, | |
1977 | { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 }, | |
1978 | { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 }, | |
1979 | { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b }, | |
1980 | ||
1981 | /* 802.11 HyperLan 2 */ | |
1982 | { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 }, | |
1983 | { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b }, | |
1984 | { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 }, | |
1985 | { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b }, | |
1986 | { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 }, | |
1987 | { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 }, | |
1988 | { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b }, | |
1989 | { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 }, | |
1990 | { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b }, | |
1991 | { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 }, | |
1992 | ||
1993 | /* 802.11 UNII */ | |
1994 | { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 }, | |
1995 | { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f }, | |
1996 | { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 }, | |
1997 | { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 }, | |
1998 | { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f }, | |
1999 | { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 }, | |
2000 | ||
2001 | /* MMAC(Japan)J52 ch 34,38,42,46 */ | |
2002 | { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b }, | |
2003 | { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 }, | |
2004 | { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b }, | |
2005 | { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 }, | |
2006 | }; | |
2007 | ||
2008 | ||
8c5e7a5f | 2009 | static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
95ea3627 ID |
2010 | { |
2011 | struct hw_mode_spec *spec = &rt2x00dev->spec; | |
8c5e7a5f ID |
2012 | struct channel_info *info; |
2013 | char *tx_power; | |
95ea3627 ID |
2014 | unsigned int i; |
2015 | ||
2016 | /* | |
2017 | * Initialize all hw fields. | |
2018 | */ | |
2019 | rt2x00dev->hw->flags = | |
566bfe5a BR |
2020 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
2021 | IEEE80211_HW_SIGNAL_DBM; | |
95ea3627 | 2022 | rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE; |
95ea3627 | 2023 | |
14a3bf89 | 2024 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
95ea3627 ID |
2025 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
2026 | rt2x00_eeprom_addr(rt2x00dev, | |
2027 | EEPROM_MAC_ADDR_0)); | |
2028 | ||
95ea3627 ID |
2029 | /* |
2030 | * Initialize hw_mode information. | |
2031 | */ | |
31562e80 ID |
2032 | spec->supported_bands = SUPPORT_BAND_2GHZ; |
2033 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | |
95ea3627 ID |
2034 | |
2035 | if (rt2x00_rf(&rt2x00dev->chip, RF2528)) { | |
2036 | spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528); | |
2037 | spec->channels = rf_vals_bg_2528; | |
2038 | } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) { | |
31562e80 | 2039 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
2040 | spec->num_channels = ARRAY_SIZE(rf_vals_5226); |
2041 | spec->channels = rf_vals_5226; | |
2042 | } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) { | |
2043 | spec->num_channels = 14; | |
2044 | spec->channels = rf_vals_5225_2527; | |
2045 | } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) { | |
31562e80 | 2046 | spec->supported_bands |= SUPPORT_BAND_5GHZ; |
95ea3627 ID |
2047 | spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527); |
2048 | spec->channels = rf_vals_5225_2527; | |
2049 | } | |
2050 | ||
8c5e7a5f ID |
2051 | /* |
2052 | * Create channel information array | |
2053 | */ | |
2054 | info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL); | |
2055 | if (!info) | |
2056 | return -ENOMEM; | |
95ea3627 | 2057 | |
8c5e7a5f ID |
2058 | spec->channels_info = info; |
2059 | ||
2060 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); | |
2061 | for (i = 0; i < 14; i++) | |
2062 | info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
2063 | ||
2064 | if (spec->num_channels > 14) { | |
2065 | tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); | |
2066 | for (i = 14; i < spec->num_channels; i++) | |
2067 | info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]); | |
95ea3627 | 2068 | } |
8c5e7a5f ID |
2069 | |
2070 | return 0; | |
95ea3627 ID |
2071 | } |
2072 | ||
2073 | static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev) | |
2074 | { | |
2075 | int retval; | |
2076 | ||
2077 | /* | |
2078 | * Allocate eeprom data. | |
2079 | */ | |
2080 | retval = rt73usb_validate_eeprom(rt2x00dev); | |
2081 | if (retval) | |
2082 | return retval; | |
2083 | ||
2084 | retval = rt73usb_init_eeprom(rt2x00dev); | |
2085 | if (retval) | |
2086 | return retval; | |
2087 | ||
2088 | /* | |
2089 | * Initialize hw specifications. | |
2090 | */ | |
8c5e7a5f ID |
2091 | retval = rt73usb_probe_hw_mode(rt2x00dev); |
2092 | if (retval) | |
2093 | return retval; | |
95ea3627 ID |
2094 | |
2095 | /* | |
9404ef34 | 2096 | * This device requires firmware. |
95ea3627 | 2097 | */ |
066cb637 | 2098 | __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags); |
3a643d24 | 2099 | __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags); |
008c4482 ID |
2100 | if (!modparam_nohwcrypt) |
2101 | __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); | |
95ea3627 ID |
2102 | |
2103 | /* | |
2104 | * Set the rssi offset. | |
2105 | */ | |
2106 | rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; | |
2107 | ||
2108 | return 0; | |
2109 | } | |
2110 | ||
2111 | /* | |
2112 | * IEEE80211 stack callback functions. | |
2113 | */ | |
2af0a570 ID |
2114 | static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, |
2115 | const struct ieee80211_tx_queue_params *params) | |
2116 | { | |
2117 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2118 | struct data_queue *queue; | |
2119 | struct rt2x00_field32 field; | |
2120 | int retval; | |
2121 | u32 reg; | |
2122 | ||
2123 | /* | |
2124 | * First pass the configuration through rt2x00lib, that will | |
2125 | * update the queue settings and validate the input. After that | |
2126 | * we are free to update the registers based on the value | |
2127 | * in the queue parameter. | |
2128 | */ | |
2129 | retval = rt2x00mac_conf_tx(hw, queue_idx, params); | |
2130 | if (retval) | |
2131 | return retval; | |
2132 | ||
2133 | queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); | |
2134 | ||
2135 | /* Update WMM TXOP register */ | |
2136 | if (queue_idx < 2) { | |
2137 | field.bit_offset = queue_idx * 16; | |
2138 | field.bit_mask = 0xffff << field.bit_offset; | |
2139 | ||
0f829b1d | 2140 | rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR0, ®); |
2af0a570 | 2141 | rt2x00_set_field32(®, field, queue->txop); |
0f829b1d | 2142 | rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg); |
2af0a570 ID |
2143 | } else if (queue_idx < 4) { |
2144 | field.bit_offset = (queue_idx - 2) * 16; | |
2145 | field.bit_mask = 0xffff << field.bit_offset; | |
2146 | ||
0f829b1d | 2147 | rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR1, ®); |
2af0a570 | 2148 | rt2x00_set_field32(®, field, queue->txop); |
0f829b1d | 2149 | rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg); |
2af0a570 ID |
2150 | } |
2151 | ||
2152 | /* Update WMM registers */ | |
2153 | field.bit_offset = queue_idx * 4; | |
2154 | field.bit_mask = 0xf << field.bit_offset; | |
2155 | ||
0f829b1d | 2156 | rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, ®); |
2af0a570 | 2157 | rt2x00_set_field32(®, field, queue->aifs); |
0f829b1d | 2158 | rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg); |
2af0a570 | 2159 | |
0f829b1d | 2160 | rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, ®); |
2af0a570 | 2161 | rt2x00_set_field32(®, field, queue->cw_min); |
0f829b1d | 2162 | rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg); |
2af0a570 | 2163 | |
0f829b1d | 2164 | rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, ®); |
2af0a570 | 2165 | rt2x00_set_field32(®, field, queue->cw_max); |
0f829b1d | 2166 | rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg); |
2af0a570 ID |
2167 | |
2168 | return 0; | |
2169 | } | |
2170 | ||
95ea3627 ID |
2171 | #if 0 |
2172 | /* | |
2173 | * Mac80211 demands get_tsf must be atomic. | |
2174 | * This is not possible for rt73usb since all register access | |
2175 | * functions require sleeping. Untill mac80211 no longer needs | |
2176 | * get_tsf to be atomic, this function should be disabled. | |
2177 | */ | |
2178 | static u64 rt73usb_get_tsf(struct ieee80211_hw *hw) | |
2179 | { | |
2180 | struct rt2x00_dev *rt2x00dev = hw->priv; | |
2181 | u64 tsf; | |
2182 | u32 reg; | |
2183 | ||
0f829b1d | 2184 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, ®); |
95ea3627 | 2185 | tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; |
0f829b1d | 2186 | rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, ®); |
95ea3627 ID |
2187 | tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); |
2188 | ||
2189 | return tsf; | |
2190 | } | |
37894473 ID |
2191 | #else |
2192 | #define rt73usb_get_tsf NULL | |
95ea3627 ID |
2193 | #endif |
2194 | ||
95ea3627 ID |
2195 | static const struct ieee80211_ops rt73usb_mac80211_ops = { |
2196 | .tx = rt2x00mac_tx, | |
4150c572 JB |
2197 | .start = rt2x00mac_start, |
2198 | .stop = rt2x00mac_stop, | |
95ea3627 ID |
2199 | .add_interface = rt2x00mac_add_interface, |
2200 | .remove_interface = rt2x00mac_remove_interface, | |
2201 | .config = rt2x00mac_config, | |
2202 | .config_interface = rt2x00mac_config_interface, | |
3a643d24 | 2203 | .configure_filter = rt2x00mac_configure_filter, |
906c110f | 2204 | .set_key = rt2x00mac_set_key, |
95ea3627 | 2205 | .get_stats = rt2x00mac_get_stats, |
471b3efd | 2206 | .bss_info_changed = rt2x00mac_bss_info_changed, |
2af0a570 | 2207 | .conf_tx = rt73usb_conf_tx, |
95ea3627 | 2208 | .get_tx_stats = rt2x00mac_get_tx_stats, |
95ea3627 | 2209 | .get_tsf = rt73usb_get_tsf, |
95ea3627 ID |
2210 | }; |
2211 | ||
2212 | static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { | |
2213 | .probe_hw = rt73usb_probe_hw, | |
2214 | .get_firmware_name = rt73usb_get_firmware_name, | |
a7f3a06c | 2215 | .get_firmware_crc = rt73usb_get_firmware_crc, |
95ea3627 ID |
2216 | .load_firmware = rt73usb_load_firmware, |
2217 | .initialize = rt2x00usb_initialize, | |
2218 | .uninitialize = rt2x00usb_uninitialize, | |
798b7adb | 2219 | .clear_entry = rt2x00usb_clear_entry, |
95ea3627 ID |
2220 | .set_device_state = rt73usb_set_device_state, |
2221 | .link_stats = rt73usb_link_stats, | |
2222 | .reset_tuner = rt73usb_reset_tuner, | |
2223 | .link_tuner = rt73usb_link_tuner, | |
2224 | .write_tx_desc = rt73usb_write_tx_desc, | |
2225 | .write_tx_data = rt2x00usb_write_tx_data, | |
bd88a781 | 2226 | .write_beacon = rt73usb_write_beacon, |
dd9fa2d2 | 2227 | .get_tx_data_len = rt73usb_get_tx_data_len, |
95ea3627 ID |
2228 | .kick_tx_queue = rt73usb_kick_tx_queue, |
2229 | .fill_rxdone = rt73usb_fill_rxdone, | |
906c110f ID |
2230 | .config_shared_key = rt73usb_config_shared_key, |
2231 | .config_pairwise_key = rt73usb_config_pairwise_key, | |
3a643d24 | 2232 | .config_filter = rt73usb_config_filter, |
6bb40dd1 | 2233 | .config_intf = rt73usb_config_intf, |
72810379 | 2234 | .config_erp = rt73usb_config_erp, |
e4ea1c40 | 2235 | .config_ant = rt73usb_config_ant, |
95ea3627 ID |
2236 | .config = rt73usb_config, |
2237 | }; | |
2238 | ||
181d6902 ID |
2239 | static const struct data_queue_desc rt73usb_queue_rx = { |
2240 | .entry_num = RX_ENTRIES, | |
2241 | .data_size = DATA_FRAME_SIZE, | |
2242 | .desc_size = RXD_DESC_SIZE, | |
b8be63ff | 2243 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2244 | }; |
2245 | ||
2246 | static const struct data_queue_desc rt73usb_queue_tx = { | |
2247 | .entry_num = TX_ENTRIES, | |
2248 | .data_size = DATA_FRAME_SIZE, | |
2249 | .desc_size = TXD_DESC_SIZE, | |
b8be63ff | 2250 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2251 | }; |
2252 | ||
2253 | static const struct data_queue_desc rt73usb_queue_bcn = { | |
6bb40dd1 | 2254 | .entry_num = 4 * BEACON_ENTRIES, |
181d6902 ID |
2255 | .data_size = MGMT_FRAME_SIZE, |
2256 | .desc_size = TXINFO_SIZE, | |
b8be63ff | 2257 | .priv_size = sizeof(struct queue_entry_priv_usb), |
181d6902 ID |
2258 | }; |
2259 | ||
95ea3627 | 2260 | static const struct rt2x00_ops rt73usb_ops = { |
2360157c | 2261 | .name = KBUILD_MODNAME, |
6bb40dd1 ID |
2262 | .max_sta_intf = 1, |
2263 | .max_ap_intf = 4, | |
95ea3627 ID |
2264 | .eeprom_size = EEPROM_SIZE, |
2265 | .rf_size = RF_SIZE, | |
61448f88 | 2266 | .tx_queues = NUM_TX_QUEUES, |
181d6902 ID |
2267 | .rx = &rt73usb_queue_rx, |
2268 | .tx = &rt73usb_queue_tx, | |
2269 | .bcn = &rt73usb_queue_bcn, | |
95ea3627 ID |
2270 | .lib = &rt73usb_rt2x00_ops, |
2271 | .hw = &rt73usb_mac80211_ops, | |
2272 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | |
2273 | .debugfs = &rt73usb_rt2x00debug, | |
2274 | #endif /* CONFIG_RT2X00_LIB_DEBUGFS */ | |
2275 | }; | |
2276 | ||
2277 | /* | |
2278 | * rt73usb module information. | |
2279 | */ | |
2280 | static struct usb_device_id rt73usb_device_table[] = { | |
2281 | /* AboCom */ | |
2282 | { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2283 | /* Askey */ | |
2284 | { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2285 | /* ASUS */ | |
2286 | { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2287 | { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2288 | /* Belkin */ | |
2289 | { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2290 | { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2291 | { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) }, | |
1f06862e | 2292 | { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 ID |
2293 | /* Billionton */ |
2294 | { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2295 | /* Buffalo */ | |
2296 | { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2297 | /* CNet */ | |
2298 | { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2299 | { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2300 | /* Conceptronic */ | |
2301 | { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) }, | |
0a74892b MM |
2302 | /* Corega */ |
2303 | { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) }, | |
95ea3627 ID |
2304 | /* D-Link */ |
2305 | { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2306 | { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, | |
cb62eccd | 2307 | { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) }, |
445815d7 | 2308 | { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) }, |
95ea3627 ID |
2309 | /* Gemtek */ |
2310 | { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2311 | /* Gigabyte */ | |
2312 | { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2313 | { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2314 | /* Huawei-3Com */ | |
2315 | { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2316 | /* Hercules */ | |
2317 | { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2318 | { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2319 | /* Linksys */ | |
2320 | { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2321 | { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2322 | /* MSI */ | |
2323 | { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2324 | { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2325 | { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2326 | { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2327 | /* Ralink */ | |
2328 | { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2329 | { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2330 | /* Qcom */ | |
2331 | { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2332 | { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2333 | { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2334 | /* Senao */ | |
2335 | { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2336 | /* Sitecom */ | |
2337 | { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2338 | { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2339 | /* Surecom */ | |
2340 | { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2341 | /* Planex */ | |
2342 | { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2343 | { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) }, | |
2344 | { 0, } | |
2345 | }; | |
2346 | ||
2347 | MODULE_AUTHOR(DRV_PROJECT); | |
2348 | MODULE_VERSION(DRV_VERSION); | |
2349 | MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver."); | |
2350 | MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards"); | |
2351 | MODULE_DEVICE_TABLE(usb, rt73usb_device_table); | |
2352 | MODULE_FIRMWARE(FIRMWARE_RT2571); | |
2353 | MODULE_LICENSE("GPL"); | |
2354 | ||
2355 | static struct usb_driver rt73usb_driver = { | |
2360157c | 2356 | .name = KBUILD_MODNAME, |
95ea3627 ID |
2357 | .id_table = rt73usb_device_table, |
2358 | .probe = rt2x00usb_probe, | |
2359 | .disconnect = rt2x00usb_disconnect, | |
2360 | .suspend = rt2x00usb_suspend, | |
2361 | .resume = rt2x00usb_resume, | |
2362 | }; | |
2363 | ||
2364 | static int __init rt73usb_init(void) | |
2365 | { | |
2366 | return usb_register(&rt73usb_driver); | |
2367 | } | |
2368 | ||
2369 | static void __exit rt73usb_exit(void) | |
2370 | { | |
2371 | usb_deregister(&rt73usb_driver); | |
2372 | } | |
2373 | ||
2374 | module_init(rt73usb_init); | |
2375 | module_exit(rt73usb_exit); |