projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath5k: warn and correct rate for unknown hw rate indexes
[linux-block.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
4e54c711 2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
008c4482
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 0;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
0f829b1d 49 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 59 */
c9c3b1a5 60#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 62#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 64
0e14f6d3 65static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 66 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
8ff48a8b 70 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 71
95ea3627 72 /*
c9c3b1a5
ID		 73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
95ea3627 75 */
c9c3b1a5
ID		 76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
0f829b1d 83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 84 }
99ade259 85
8ff48a8b 86 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 87}
88
0e14f6d3 89static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 90 const unsigned int word, u8 *value)
91{
92 u32 reg;
93
8ff48a8b 94 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 95
95ea3627 96 /*
c9c3b1a5
ID		 97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
95ea3627 103 */
c9c3b1a5
ID		 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 109
0f829b1d 110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 111
c9c3b1a5
ID		 112 WAIT_FOR_BBP(rt2x00dev, &reg);
113 }
95ea3627
ID		 114
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 116
8ff48a8b 117 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 118}
119
0e14f6d3 120static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 121 const unsigned int word, const u32 value)
122{
123 u32 reg;
95ea3627 124
8ff48a8b 125 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 126
4f5af6eb 127 /*
c9c3b1a5
ID		 128 * Wait until the RF becomes available, afterwards we
129 * can safely write the new data into the register.
4f5af6eb 130 */
c9c3b1a5
ID		 131 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
132 reg = 0;
133 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
134 /*
135 * RF5225 and RF2527 contain 21 bits per RF register value,
136 * all others contain 20 bits.
137 */
138 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
139 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
140 rt2x00_rf(&rt2x00dev->chip, RF2527)));
141 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
142 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
143
0f829b1d 144 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 145 rt2x00_rf_write(rt2x00dev, word, value);
146 }
8ff48a8b
ID		 147
148 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 149}
150
151#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 152static const struct rt2x00debug rt73usb_rt2x00debug = {
153 .owner = THIS_MODULE,
154 .csr = {
0f829b1d
ID		 155 .read = rt2x00usb_register_read,
156 .write = rt2x00usb_register_write,
743b97ca
ID		 157 .flags = RT2X00DEBUGFS_OFFSET,
158 .word_base = CSR_REG_BASE,
95ea3627
ID		 159 .word_size = sizeof(u32),
160 .word_count = CSR_REG_SIZE / sizeof(u32),
161 },
162 .eeprom = {
163 .read = rt2x00_eeprom_read,
164 .write = rt2x00_eeprom_write,
743b97ca 165 .word_base = EEPROM_BASE,
95ea3627
ID		 166 .word_size = sizeof(u16),
167 .word_count = EEPROM_SIZE / sizeof(u16),
168 },
169 .bbp = {
170 .read = rt73usb_bbp_read,
171 .write = rt73usb_bbp_write,
743b97ca 172 .word_base = BBP_BASE,
95ea3627
ID		 173 .word_size = sizeof(u8),
174 .word_count = BBP_SIZE / sizeof(u8),
175 },
176 .rf = {
177 .read = rt2x00_rf_read,
178 .write = rt73usb_rf_write,
743b97ca 179 .word_base = RF_BASE,
95ea3627
ID		 180 .word_size = sizeof(u32),
181 .word_count = RF_SIZE / sizeof(u32),
182 },
183};
184#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
185
7396faf4
ID		 186#ifdef CONFIG_RT2X00_LIB_RFKILL
187static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
188{
189 u32 reg;
190
191 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
192 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
193}
194#else
195#define rt73usb_rfkill_poll NULL
196#endif /* CONFIG_RT2X00_LIB_RFKILL */
197
771fd565 198#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 199static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 200 enum led_brightness brightness)
201{
202 struct rt2x00_led *led =
203 container_of(led_cdev, struct rt2x00_led, led_dev);
204 unsigned int enabled = brightness != LED_OFF;
205 unsigned int a_mode =
206 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
207 unsigned int bg_mode =
208 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
209
210 if (led->type == LED_TYPE_RADIO) {
211 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
212 MCU_LEDCS_RADIO_STATUS, enabled);
213
47b10cd1
ID		 214 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
215 0, led->rt2x00dev->led_mcu_reg,
216 REGISTER_TIMEOUT);
a9450b70
ID		 217 } else if (led->type == LED_TYPE_ASSOC) {
218 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
219 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
220 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
221 MCU_LEDCS_LINK_A_STATUS, a_mode);
222
47b10cd1
ID		 223 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
224 0, led->rt2x00dev->led_mcu_reg,
225 REGISTER_TIMEOUT);
a9450b70
ID		 226 } else if (led->type == LED_TYPE_QUALITY) {
227 /*
228 * The brightness is divided into 6 levels (0 - 5),
229 * this means we need to convert the brightness
230 * argument into the matching level within that range.
231 */
47b10cd1
ID		 232 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
233 brightness / (LED_FULL / 6),
234 led->rt2x00dev->led_mcu_reg,
235 REGISTER_TIMEOUT);
a9450b70
ID		 236 }
237}
a2e1d52a
ID		 238
239static int rt73usb_blink_set(struct led_classdev *led_cdev,
240 unsigned long *delay_on,
241 unsigned long *delay_off)
242{
243 struct rt2x00_led *led =
244 container_of(led_cdev, struct rt2x00_led, led_dev);
245 u32 reg;
246
0f829b1d 247 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 248 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
249 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 250 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 251
252 return 0;
253}
475433be
ID		 254
255static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
256 struct rt2x00_led *led,
257 enum led_type type)
258{
259 led->rt2x00dev = rt2x00dev;
260 led->type = type;
261 led->led_dev.brightness_set = rt73usb_brightness_set;
262 led->led_dev.blink_set = rt73usb_blink_set;
263 led->flags = LED_INITIALIZED;
264}
771fd565 265#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 266
95ea3627
ID		 267/*
268 * Configuration handlers.
269 */
906c110f
ID		 270static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
271 struct rt2x00lib_crypto *crypto,
272 struct ieee80211_key_conf *key)
273{
274 struct hw_key_entry key_entry;
275 struct rt2x00_field32 field;
276 int timeout;
277 u32 mask;
278 u32 reg;
279
280 if (crypto->cmd == SET_KEY) {
281 /*
282 * rt2x00lib can't determine the correct free
283 * key_idx for shared keys. We have 1 register
284 * with key valid bits. The goal is simple, read
285 * the register, if that is full we have no slots
286 * left.
287 * Note that each BSS is allowed to have up to 4
288 * shared keys, so put a mask over the allowed
289 * entries.
290 */
291 mask = (0xf << crypto->bssidx);
292
0f829b1d 293 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 294 reg &= mask;
295
296 if (reg && reg == mask)
297 return -ENOSPC;
298
acaf908d 299 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 300
301 /*
302 * Upload key to hardware
303 */
304 memcpy(key_entry.key, crypto->key,
305 sizeof(key_entry.key));
306 memcpy(key_entry.tx_mic, crypto->tx_mic,
307 sizeof(key_entry.tx_mic));
308 memcpy(key_entry.rx_mic, crypto->rx_mic,
309 sizeof(key_entry.rx_mic));
310
311 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
312 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
313 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
314 USB_VENDOR_REQUEST_OUT, reg,
315 &key_entry,
316 sizeof(key_entry),
317 timeout);
318
319 /*
320 * The cipher types are stored over 2 registers.
321 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
322 * bssidx 1 and 2 keys are stored in SEC_CSR5.
323 * Using the correct defines correctly will cause overhead,
324 * so just calculate the correct offset.
325 */
326 if (key->hw_key_idx < 8) {
327 field.bit_offset = (3 * key->hw_key_idx);
328 field.bit_mask = 0x7 << field.bit_offset;
329
0f829b1d 330 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 331 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 332 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 333 } else {
334 field.bit_offset = (3 * (key->hw_key_idx - 8));
335 field.bit_mask = 0x7 << field.bit_offset;
336
0f829b1d 337 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 338 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 339 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 340 }
341
342 /*
343 * The driver does not support the IV/EIV generation
344 * in hardware. However it doesn't support the IV/EIV
345 * inside the ieee80211 frame either, but requires it
346 * to be provided seperately for the descriptor.
347 * rt2x00lib will cut the IV/EIV data out of all frames
348 * given to us by mac80211, but we must tell mac80211
349 * to generate the IV/EIV data.
350 */
351 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
352 }
353
354 /*
355 * SEC_CSR0 contains only single-bit fields to indicate
356 * a particular key is valid. Because using the FIELD32()
357 * defines directly will cause a lot of overhead we use
358 * a calculation to determine the correct bit directly.
359 */
360 mask = 1 << key->hw_key_idx;
361
0f829b1d 362 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 363 if (crypto->cmd == SET_KEY)
364 reg |= mask;
365 else if (crypto->cmd == DISABLE_KEY)
366 reg &= ~mask;
0f829b1d 367 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 368
369 return 0;
370}
371
372static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
373 struct rt2x00lib_crypto *crypto,
374 struct ieee80211_key_conf *key)
375{
376 struct hw_pairwise_ta_entry addr_entry;
377 struct hw_key_entry key_entry;
378 int timeout;
379 u32 mask;
380 u32 reg;
381
382 if (crypto->cmd == SET_KEY) {
383 /*
384 * rt2x00lib can't determine the correct free
385 * key_idx for pairwise keys. We have 2 registers
386 * with key valid bits. The goal is simple, read
387 * the first register, if that is full move to
388 * the next register.
389 * When both registers are full, we drop the key,
390 * otherwise we use the first invalid entry.
391 */
0f829b1d 392 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 393 if (reg && reg == ~0) {
394 key->hw_key_idx = 32;
0f829b1d 395 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 396 if (reg && reg == ~0)
397 return -ENOSPC;
398 }
399
acaf908d 400 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 401
402 /*
403 * Upload key to hardware
404 */
405 memcpy(key_entry.key, crypto->key,
406 sizeof(key_entry.key));
407 memcpy(key_entry.tx_mic, crypto->tx_mic,
408 sizeof(key_entry.tx_mic));
409 memcpy(key_entry.rx_mic, crypto->rx_mic,
410 sizeof(key_entry.rx_mic));
411
412 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
413 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
414 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
415 USB_VENDOR_REQUEST_OUT, reg,
416 &key_entry,
417 sizeof(key_entry),
418 timeout);
419
420 /*
421 * Send the address and cipher type to the hardware register.
422 * This data fits within the CSR cache size, so we can use
0f829b1d 423 * rt2x00usb_register_multiwrite() directly.
906c110f
ID		 424 */
425 memset(&addr_entry, 0, sizeof(addr_entry));
426 memcpy(&addr_entry, crypto->address, ETH_ALEN);
427 addr_entry.cipher = crypto->cipher;
428
429 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 430 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 431 &addr_entry, sizeof(addr_entry));
432
433 /*
434 * Enable pairwise lookup table for given BSS idx,
435 * without this received frames will not be decrypted
436 * by the hardware.
437 */
0f829b1d 438 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 439 reg |= (1 << crypto->bssidx);
0f829b1d 440 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 441
442 /*
443 * The driver does not support the IV/EIV generation
444 * in hardware. However it doesn't support the IV/EIV
445 * inside the ieee80211 frame either, but requires it
446 * to be provided seperately for the descriptor.
447 * rt2x00lib will cut the IV/EIV data out of all frames
448 * given to us by mac80211, but we must tell mac80211
449 * to generate the IV/EIV data.
450 */
451 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
452 }
453
454 /*
455 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
456 * a particular key is valid. Because using the FIELD32()
457 * defines directly will cause a lot of overhead we use
458 * a calculation to determine the correct bit directly.
459 */
460 if (key->hw_key_idx < 32) {
461 mask = 1 << key->hw_key_idx;
462
0f829b1d 463 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 464 if (crypto->cmd == SET_KEY)
465 reg |= mask;
466 else if (crypto->cmd == DISABLE_KEY)
467 reg &= ~mask;
0f829b1d 468 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 469 } else {
470 mask = 1 << (key->hw_key_idx - 32);
471
0f829b1d 472 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 473 if (crypto->cmd == SET_KEY)
474 reg |= mask;
475 else if (crypto->cmd == DISABLE_KEY)
476 reg &= ~mask;
0f829b1d 477 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 478 }
479
480 return 0;
481}
482
3a643d24
ID		 483static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
484 const unsigned int filter_flags)
485{
486 u32 reg;
487
488 /*
489 * Start configuration steps.
490 * Note that the version error will always be dropped
491 * and broadcast frames will always be accepted since
492 * there is no filter for it at this time.
493 */
0f829b1d 494 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 495 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
496 !(filter_flags & FIF_FCSFAIL));
497 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
498 !(filter_flags & FIF_PLCPFAIL));
499 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
500 !(filter_flags & FIF_CONTROL));
501 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
502 !(filter_flags & FIF_PROMISC_IN_BSS));
503 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 504 !(filter_flags & FIF_PROMISC_IN_BSS) &&
505 !rt2x00dev->intf_ap_count);
3a643d24
ID		 506 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
507 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
508 !(filter_flags & FIF_ALLMULTI));
509 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
510 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
511 !(filter_flags & FIF_CONTROL));
0f829b1d 512 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 513}
514
6bb40dd1
ID		 515static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
516 struct rt2x00_intf *intf,
517 struct rt2x00intf_conf *conf,
518 const unsigned int flags)
95ea3627 519{
6bb40dd1
ID		 520 unsigned int beacon_base;
521 u32 reg;
95ea3627 522
6bb40dd1
ID		 523 if (flags & CONFIG_UPDATE_TYPE) {
524 /*
525 * Clear current synchronisation setup.
526 * For the Beacon base registers we only need to clear
527 * the first byte since that byte contains the VALID and OWNER
528 * bits which (when set to 0) will invalidate the entire beacon.
529 */
530 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
0f829b1d 531 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 532
6bb40dd1
ID		 533 /*
534 * Enable synchronisation.
535 */
0f829b1d 536 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 537 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 538 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 539 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
0f829b1d 540 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 541 }
95ea3627 542
6bb40dd1
ID		 543 if (flags & CONFIG_UPDATE_MAC) {
544 reg = le32_to_cpu(conf->mac[1]);
545 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
546 conf->mac[1] = cpu_to_le32(reg);
95ea3627 547
0f829b1d 548 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 549 conf->mac, sizeof(conf->mac));
550 }
95ea3627 551
6bb40dd1
ID		 552 if (flags & CONFIG_UPDATE_BSSID) {
553 reg = le32_to_cpu(conf->bssid[1]);
554 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
555 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 556
0f829b1d 557 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 558 conf->bssid, sizeof(conf->bssid));
559 }
95ea3627
ID		 560}
561
3a643d24
ID		 562static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
563 struct rt2x00lib_erp *erp)
95ea3627 564{
95ea3627 565 u32 reg;
95ea3627 566
0f829b1d 567 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 568 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
0f829b1d 569 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 570
0f829b1d 571 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 572 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 573 !!erp->short_preamble);
0f829b1d 574 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 575
0f829b1d 576 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 577
0f829b1d 578 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
e4ea1c40 579 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
0f829b1d 580 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 581
0f829b1d 582 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
e4ea1c40
ID		 583 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
584 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
585 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
0f829b1d 586 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 587}
588
589static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 590 struct antenna_setup *ant)
95ea3627
ID		 591{
592 u8 r3;
593 u8 r4;
594 u8 r77;
2676c94d 595 u8 temp;
95ea3627
ID		 596
597 rt73usb_bbp_read(rt2x00dev, 3, &r3);
598 rt73usb_bbp_read(rt2x00dev, 4, &r4);
599 rt73usb_bbp_read(rt2x00dev, 77, &r77);
600
601 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
602
e4cd2ff8
ID		 603 /*
604 * Configure the RX antenna.
605 */
addc81bd 606 switch (ant->rx) {
95ea3627 607 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 608 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
609 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 610 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 611 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 612 break;
613 case ANTENNA_A:
2676c94d 614 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 615 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 616 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 617 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
618 else
619 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 620 break;
621 case ANTENNA_B:
a4fe07d9 622 default:
2676c94d 623 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 624 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 625 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 626 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
627 else
628 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 629 break;
630 }
631
632 rt73usb_bbp_write(rt2x00dev, 77, r77);
633 rt73usb_bbp_write(rt2x00dev, 3, r3);
634 rt73usb_bbp_write(rt2x00dev, 4, r4);
635}
636
637static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 638 struct antenna_setup *ant)
95ea3627
ID		 639{
640 u8 r3;
641 u8 r4;
642 u8 r77;
643
644 rt73usb_bbp_read(rt2x00dev, 3, &r3);
645 rt73usb_bbp_read(rt2x00dev, 4, &r4);
646 rt73usb_bbp_read(rt2x00dev, 77, &r77);
647
648 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
649 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
650 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
651
e4cd2ff8
ID		 652 /*
653 * Configure the RX antenna.
654 */
addc81bd 655 switch (ant->rx) {
95ea3627 656 case ANTENNA_HW_DIVERSITY:
2676c94d 657 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 658 break;
659 case ANTENNA_A:
2676c94d
MN		 660 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
661 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 662 break;
663 case ANTENNA_B:
a4fe07d9 664 default:
2676c94d
MN		 665 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
666 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 667 break;
668 }
669
670 rt73usb_bbp_write(rt2x00dev, 77, r77);
671 rt73usb_bbp_write(rt2x00dev, 3, r3);
672 rt73usb_bbp_write(rt2x00dev, 4, r4);
673}
674
675struct antenna_sel {
676 u8 word;
677 /*
678 * value[0] -> non-LNA
679 * value[1] -> LNA
680 */
681 u8 value[2];
682};
683
684static const struct antenna_sel antenna_sel_a[] = {
685 { 96, { 0x58, 0x78 } },
686 { 104, { 0x38, 0x48 } },
687 { 75, { 0xfe, 0x80 } },
688 { 86, { 0xfe, 0x80 } },
689 { 88, { 0xfe, 0x80 } },
690 { 35, { 0x60, 0x60 } },
691 { 97, { 0x58, 0x58 } },
692 { 98, { 0x58, 0x58 } },
693};
694
695static const struct antenna_sel antenna_sel_bg[] = {
696 { 96, { 0x48, 0x68 } },
697 { 104, { 0x2c, 0x3c } },
698 { 75, { 0xfe, 0x80 } },
699 { 86, { 0xfe, 0x80 } },
700 { 88, { 0xfe, 0x80 } },
701 { 35, { 0x50, 0x50 } },
702 { 97, { 0x48, 0x48 } },
703 { 98, { 0x48, 0x48 } },
704};
705
e4ea1c40
ID		 706static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
707 struct antenna_setup *ant)
95ea3627
ID		 708{
709 const struct antenna_sel *sel;
710 unsigned int lna;
711 unsigned int i;
712 u32 reg;
713
a4fe07d9
ID		 714 /*
715 * We should never come here because rt2x00lib is supposed
716 * to catch this and send us the correct antenna explicitely.
717 */
718 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
719 ant->tx == ANTENNA_SW_DIVERSITY);
720
8318d78a 721 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 722 sel = antenna_sel_a;
723 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 724 } else {
725 sel = antenna_sel_bg;
726 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 727 }
728
2676c94d
MN		 729 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
730 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
731
0f829b1d 732 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 733
ddc827f9 734 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 735 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 736 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 737 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 738
0f829b1d 739 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627
ID		 740
741 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
742 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 743 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 744 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
745 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 746 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 747}
748
e4ea1c40 749static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 750 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 751{
752 u16 eeprom;
753 short lna_gain = 0;
754
755 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
756 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
757 lna_gain += 14;
758
759 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
760 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
761 } else {
762 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
763 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
764 }
765
766 rt2x00dev->lna_gain = lna_gain;
767}
768
769static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
770 struct rf_channel *rf, const int txpower)
771{
772 u8 r3;
773 u8 r94;
774 u8 smart;
775
776 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
777 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
778
779 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
780 rt2x00_rf(&rt2x00dev->chip, RF2527));
781
782 rt73usb_bbp_read(rt2x00dev, 3, &r3);
783 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
784 rt73usb_bbp_write(rt2x00dev, 3, r3);
785
786 r94 = 6;
787 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
788 r94 += txpower - MAX_TXPOWER;
789 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
790 r94 += txpower;
791 rt73usb_bbp_write(rt2x00dev, 94, r94);
792
793 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
794 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
795 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
796 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
797
798 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
799 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
800 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
801 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
802
803 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
804 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
805 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
806 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
807
808 udelay(10);
809}
810
811static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
812 const int txpower)
813{
814 struct rf_channel rf;
815
816 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
817 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
818 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
819 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
820
821 rt73usb_config_channel(rt2x00dev, &rf, txpower);
822}
823
824static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
825 struct rt2x00lib_conf *libconf)
95ea3627
ID		 826{
827 u32 reg;
828
0f829b1d 829 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e4ea1c40
ID		 830 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
831 libconf->conf->long_frame_max_tx_count);
832 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
833 libconf->conf->short_frame_max_tx_count);
0f829b1d 834 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 835}
95ea3627 836
e4ea1c40
ID		 837static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
838 struct rt2x00lib_conf *libconf)
839{
840 u32 reg;
95ea3627 841
0f829b1d 842 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 843 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 844 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 845
0f829b1d 846 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
95ea3627 847 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
0f829b1d 848 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 849
0f829b1d 850 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 851 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
852 libconf->conf->beacon_int * 16);
0f829b1d 853 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 854}
855
7d7f19cc
ID		 856static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
857 struct rt2x00lib_conf *libconf)
858{
859 enum dev_state state =
860 (libconf->conf->flags & IEEE80211_CONF_PS) ?
861 STATE_SLEEP : STATE_AWAKE;
862 u32 reg;
863
864 if (state == STATE_SLEEP) {
865 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
866 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
867 libconf->conf->beacon_int - 10);
868 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
869 libconf->conf->listen_interval - 1);
870 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
871
872 /* We must first disable autowake before it can be enabled */
873 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
874 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
875
876 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
877 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
878
879 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
880 USB_MODE_SLEEP, REGISTER_TIMEOUT);
881 } else {
882 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
883 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
884
885 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
886 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
887 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
888 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
889 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
890 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
891 }
892}
893
95ea3627 894static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 895 struct rt2x00lib_conf *libconf,
896 const unsigned int flags)
95ea3627 897{
ba2ab471
ID		 898 /* Always recalculate LNA gain before changing configuration */
899 rt73usb_config_lna_gain(rt2x00dev, libconf);
900
e4ea1c40 901 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 902 rt73usb_config_channel(rt2x00dev, &libconf->rf,
903 libconf->conf->power_level);
e4ea1c40
ID		 904 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
905 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 906 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 907 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
908 rt73usb_config_retry_limit(rt2x00dev, libconf);
909 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
5c58ee51 910 rt73usb_config_duration(rt2x00dev, libconf);
7d7f19cc
ID		 911 if (flags & IEEE80211_CONF_CHANGE_PS)
912 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 913}
914
95ea3627
ID		 915/*
916 * Link tuning
917 */
ebcf26da
ID		 918static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
919 struct link_qual *qual)
95ea3627
ID		 920{
921 u32 reg;
922
923 /*
924 * Update FCS error count from register.
925 */
0f829b1d 926 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 927 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 928
929 /*
930 * Update False CCA count from register.
931 */
0f829b1d 932 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 933 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 934}
935
5352ff65
ID		 936static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
937 struct link_qual *qual, u8 vgc_level)
eb20b4e8 938{
5352ff65 939 if (qual->vgc_level != vgc_level) {
eb20b4e8 940 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 941 qual->vgc_level = vgc_level;
942 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 943 }
944}
945
5352ff65
ID		 946static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
947 struct link_qual *qual)
95ea3627 948{
5352ff65 949 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 950}
951
5352ff65
ID		 952static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
953 struct link_qual *qual, const u32 count)
95ea3627 954{
95ea3627
ID		 955 u8 up_bound;
956 u8 low_bound;
957
95ea3627
ID		 958 /*
959 * Determine r17 bounds.
960 */
8318d78a 961 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 962 low_bound = 0x28;
963 up_bound = 0x48;
964
965 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
966 low_bound += 0x10;
967 up_bound += 0x10;
968 }
969 } else {
5352ff65 970 if (qual->rssi > -82) {
95ea3627
ID		 971 low_bound = 0x1c;
972 up_bound = 0x40;
5352ff65 973 } else if (qual->rssi > -84) {
95ea3627
ID		 974 low_bound = 0x1c;
975 up_bound = 0x20;
976 } else {
977 low_bound = 0x1c;
978 up_bound = 0x1c;
979 }
980
981 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
982 low_bound += 0x14;
983 up_bound += 0x10;
984 }
985 }
986
6bb40dd1
ID		 987 /*
988 * If we are not associated, we should go straight to the
989 * dynamic CCA tuning.
990 */
991 if (!rt2x00dev->intf_associated)
992 goto dynamic_cca_tune;
993
95ea3627
ID		 994 /*
995 * Special big-R17 for very short distance
996 */
5352ff65
ID		 997 if (qual->rssi > -35) {
998 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 999 return;
1000 }
1001
1002 /*
1003 * Special big-R17 for short distance
1004 */
5352ff65
ID		 1005 if (qual->rssi >= -58) {
1006 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1007 return;
1008 }
1009
1010 /*
1011 * Special big-R17 for middle-short distance
1012 */
5352ff65
ID		 1013 if (qual->rssi >= -66) {
1014 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 1015 return;
1016 }
1017
1018 /*
1019 * Special mid-R17 for middle distance
1020 */
5352ff65
ID		 1021 if (qual->rssi >= -74) {
1022 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1023 return;
1024 }
1025
1026 /*
1027 * Special case: Change up_bound based on the rssi.
1028 * Lower up_bound when rssi is weaker then -74 dBm.
1029 */
5352ff65 1030 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1031 if (low_bound > up_bound)
1032 up_bound = low_bound;
1033
5352ff65
ID		 1034 if (qual->vgc_level > up_bound) {
1035 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1036 return;
1037 }
1038
6bb40dd1
ID		 1039dynamic_cca_tune:
1040
95ea3627
ID		 1041 /*
1042 * r17 does not yet exceed upper limit, continue and base
1043 * the r17 tuning on the false CCA count.
1044 */
5352ff65
ID		 1045 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1046 rt73usb_set_vgc(rt2x00dev, qual,
1047 min_t(u8, qual->vgc_level + 4, up_bound));
1048 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1049 rt73usb_set_vgc(rt2x00dev, qual,
1050 max_t(u8, qual->vgc_level - 4, low_bound));
95ea3627
ID		 1051}
1052
1053/*
a7f3a06c 1054 * Firmware functions
95ea3627
ID		 1055 */
1056static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1057{
1058 return FIRMWARE_RT2571;
1059}
1060
0cbe0064
ID		 1061static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1062 const u8 *data, const size_t len)
a7f3a06c 1063{
0cbe0064 1064 u16 fw_crc;
a7f3a06c
ID		 1065 u16 crc;
1066
1067 /*
0cbe0064
ID		 1068 * Only support 2kb firmware files.
1069 */
1070 if (len != 2048)
1071 return FW_BAD_LENGTH;
1072
1073 /*
a7f3a06c
ID		 1074 * The last 2 bytes in the firmware array are the crc checksum itself,
1075 * this means that we should never pass those 2 bytes to the crc
1076 * algorithm.
1077 */
0cbe0064
ID		 1078 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1079
1080 /*
1081 * Use the crc itu-t algorithm.
1082 */
a7f3a06c
ID		 1083 crc = crc_itu_t(0, data, len - 2);
1084 crc = crc_itu_t_byte(crc, 0);
1085 crc = crc_itu_t_byte(crc, 0);
1086
0cbe0064 1087 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1088}
1089
0cbe0064
ID		 1090static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1091 const u8 *data, const size_t len)
95ea3627
ID		 1092{
1093 unsigned int i;
1094 int status;
1095 u32 reg;
95ea3627
ID		 1096
1097 /*
1098 * Wait for stable hardware.
1099 */
1100 for (i = 0; i < 100; i++) {
0f829b1d 1101 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1102 if (reg)
1103 break;
1104 msleep(1);
1105 }
1106
1107 if (!reg) {
1108 ERROR(rt2x00dev, "Unstable hardware.\n");
1109 return -EBUSY;
1110 }
1111
1112 /*
1113 * Write firmware to device.
95ea3627 1114 */
3e0c1abe
IM		 1115 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1116 USB_VENDOR_REQUEST_OUT,
1117 FIRMWARE_IMAGE_BASE,
1118 data, len,
1119 REGISTER_TIMEOUT32(len));
95ea3627
ID		 1120
1121 /*
1122 * Send firmware request to device to load firmware,
1123 * we need to specify a long timeout time.
1124 */
1125 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1126 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1127 REGISTER_TIMEOUT_FIRMWARE);
1128 if (status < 0) {
1129 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1130 return status;
1131 }
1132
95ea3627
ID		 1133 return 0;
1134}
1135
a7f3a06c
ID		 1136/*
1137 * Initialization functions.
1138 */
95ea3627
ID		 1139static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1140{
1141 u32 reg;
1142
0f829b1d 1143 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1144 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1145 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1146 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1147 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1148
0f829b1d 1149 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1150 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1151 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1152 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1153 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1154 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1155 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1156 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1157 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1158 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1159
1160 /*
1161 * CCK TXD BBP registers
1162 */
0f829b1d 1163 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1164 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1165 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1166 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1167 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1168 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1169 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1170 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1171 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1172 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1173
1174 /*
1175 * OFDM TXD BBP registers
1176 */
0f829b1d 1177 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1178 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1179 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1180 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1181 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1182 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1183 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1184 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1185
0f829b1d 1186 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1187 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1188 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1189 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1190 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1191 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1192
0f829b1d 1193 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1194 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1195 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1196 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1197 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1198 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1199
0f829b1d 1200 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1201 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1202 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1203 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1204 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1205 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1206 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1207 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1208
0f829b1d 1209 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1210
0f829b1d 1211 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1212 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1213 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1214
0f829b1d 1215 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1216
1217 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1218 return -EBUSY;
1219
0f829b1d 1220 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1221
1222 /*
1223 * Invalidate all Shared Keys (SEC_CSR0),
1224 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1225 */
0f829b1d
ID		 1226 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1227 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1228 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1229
1230 reg = 0x000023b0;
1231 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1232 rt2x00_rf(&rt2x00dev->chip, RF2527))
1233 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1234 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1235
0f829b1d
ID		 1236 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1237 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1238 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1239
0f829b1d 1240 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1241 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1242 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1243
6bb40dd1
ID		 1244 /*
1245 * Clear all beacons
1246 * For the Beacon base registers we only need to clear
1247 * the first byte since that byte contains the VALID and OWNER
1248 * bits which (when set to 0) will invalidate the entire beacon.
1249 */
0f829b1d
ID		 1250 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1251 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1252 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1253 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1254
95ea3627
ID		 1255 /*
1256 * We must clear the error counters.
1257 * These registers are cleared on read,
1258 * so we may pass a useless variable to store the value.
1259 */
0f829b1d
ID		 1260 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1261 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1262 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1263
1264 /*
1265 * Reset MAC and BBP registers.
1266 */
0f829b1d 1267 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1268 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1269 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1270 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1271
0f829b1d 1272 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1273 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1274 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1275 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1276
0f829b1d 1277 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1278 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1279 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1280
1281 return 0;
1282}
1283
2b08da3f 1284static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1285{
1286 unsigned int i;
95ea3627
ID		 1287 u8 value;
1288
1289 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1290 rt73usb_bbp_read(rt2x00dev, 0, &value);
1291 if ((value != 0xff) && (value != 0x00))
2b08da3f 1292 return 0;
95ea3627
ID		 1293 udelay(REGISTER_BUSY_DELAY);
1294 }
1295
1296 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1297 return -EACCES;
2b08da3f
ID		 1298}
1299
1300static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1301{
1302 unsigned int i;
1303 u16 eeprom;
1304 u8 reg_id;
1305 u8 value;
1306
1307 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1308 return -EACCES;
95ea3627 1309
95ea3627
ID		 1310 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1311 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1312 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1313 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1314 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1315 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1316 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1317 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1318 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1319 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1320 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1321 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1322 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1323 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1324 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1325 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1326 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1327 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1328 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1329 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1330 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1331 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1332 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1333 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1334 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1335
95ea3627
ID		 1336 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1337 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1338
1339 if (eeprom != 0xffff && eeprom != 0x0000) {
1340 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1341 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1342 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1343 }
1344 }
95ea3627
ID		 1345
1346 return 0;
1347}
1348
1349/*
1350 * Device state switch handlers.
1351 */
1352static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1353 enum dev_state state)
1354{
1355 u32 reg;
1356
0f829b1d 1357 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 1358 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1359 (state == STATE_RADIO_RX_OFF) ||
1360 (state == STATE_RADIO_RX_OFF_LINK));
0f829b1d 1361 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627
ID		 1362}
1363
1364static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1365{
1366 /*
1367 * Initialize all registers.
1368 */
2b08da3f
ID		 1369 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1370 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1371 return -EIO;
95ea3627 1372
95ea3627
ID		 1373 return 0;
1374}
1375
1376static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1377{
0f829b1d 1378 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1379
1380 /*
1381 * Disable synchronisation.
1382 */
0f829b1d 1383 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1384
1385 rt2x00usb_disable_radio(rt2x00dev);
1386}
1387
1388static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1389{
1390 u32 reg;
1391 unsigned int i;
1392 char put_to_sleep;
95ea3627
ID		 1393
1394 put_to_sleep = (state != STATE_AWAKE);
1395
0f829b1d 1396 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1397 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1398 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1399 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1400
1401 /*
1402 * Device is not guaranteed to be in the requested state yet.
1403 * We must wait until the register indicates that the
1404 * device has entered the correct state.
1405 */
1406 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
0f829b1d 1407 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1408 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1409 if (state == !put_to_sleep)
95ea3627
ID		 1410 return 0;
1411 msleep(10);
1412 }
1413
95ea3627
ID		 1414 return -EBUSY;
1415}
1416
1417static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1418 enum dev_state state)
1419{
1420 int retval = 0;
1421
1422 switch (state) {
1423 case STATE_RADIO_ON:
1424 retval = rt73usb_enable_radio(rt2x00dev);
1425 break;
1426 case STATE_RADIO_OFF:
1427 rt73usb_disable_radio(rt2x00dev);
1428 break;
1429 case STATE_RADIO_RX_ON:
61667d8d 1430 case STATE_RADIO_RX_ON_LINK:
95ea3627 1431 case STATE_RADIO_RX_OFF:
61667d8d 1432 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1433 rt73usb_toggle_rx(rt2x00dev, state);
1434 break;
1435 case STATE_RADIO_IRQ_ON:
1436 case STATE_RADIO_IRQ_OFF:
1437 /* No support, but no error either */
95ea3627
ID		 1438 break;
1439 case STATE_DEEP_SLEEP:
1440 case STATE_SLEEP:
1441 case STATE_STANDBY:
1442 case STATE_AWAKE:
1443 retval = rt73usb_set_state(rt2x00dev, state);
1444 break;
1445 default:
1446 retval = -ENOTSUPP;
1447 break;
1448 }
1449
2b08da3f
ID		 1450 if (unlikely(retval))
1451 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1452 state, retval);
1453
95ea3627
ID		 1454 return retval;
1455}
1456
1457/*
1458 * TX descriptor initialization
1459 */
1460static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
906c110f
ID		 1461 struct sk_buff *skb,
1462 struct txentry_desc *txdesc)
95ea3627 1463{
181d6902 1464 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1465 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1466 u32 word;
1467
1468 /*
1469 * Start writing the descriptor words.
1470 */
1471 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1472 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1473 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1474 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1475 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
906c110f 1476 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1477 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1478 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1479 rt2x00_desc_write(txd, 1, word);
1480
1481 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1482 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1483 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1484 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1485 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1486 rt2x00_desc_write(txd, 2, word);
1487
906c110f 1488 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1489 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1490 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1491 }
1492
95ea3627
ID		 1493 rt2x00_desc_read(txd, 5, &word);
1494 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1495 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1496 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1497 rt2x00_desc_write(txd, 5, word);
1498
1499 rt2x00_desc_read(txd, 0, &word);
1500 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1501 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1502 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1503 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1504 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1505 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1506 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1507 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1508 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1509 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1510 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1511 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1512 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1513 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
906c110f
ID		 1514 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1515 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1516 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1517 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1518 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1abc3656 1519 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1520 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1521 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
906c110f 1522 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1523 rt2x00_desc_write(txd, 0, word);
1524}
1525
bd88a781
ID		 1526/*
1527 * TX data initialization
1528 */
1529static void rt73usb_write_beacon(struct queue_entry *entry)
1530{
1531 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1532 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1533 unsigned int beacon_base;
1534 u32 reg;
1535
1536 /*
1537 * Add the descriptor in front of the skb.
1538 */
1539 skb_push(entry->skb, entry->queue->desc_size);
1540 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1541 skbdesc->desc = entry->skb->data;
1542
1543 /*
1544 * Disable beaconing while we are reloading the beacon data,
1545 * otherwise we might be sending out invalid data.
1546 */
0f829b1d 1547 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781
ID		 1548 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1549 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1550 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1551 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781
ID		 1552
1553 /*
1554 * Write entire beacon with descriptor to register.
1555 */
1556 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3e0c1abe
IM		 1557 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1558 USB_VENDOR_REQUEST_OUT, beacon_base,
1559 entry->skb->data, entry->skb->len,
1560 REGISTER_TIMEOUT32(entry->skb->len));
bd88a781
ID		 1561
1562 /*
1563 * Clean up the beacon skb.
1564 */
1565 dev_kfree_skb(entry->skb);
1566 entry->skb = NULL;
1567}
1568
f1ca2167 1569static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1570{
1571 int length;
1572
1573 /*
1574 * The length _must_ be a multiple of 4,
1575 * but it must _not_ be a multiple of the USB packet size.
1576 */
f1ca2167
ID		 1577 length = roundup(entry->skb->len, 4);
1578 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1579
1580 return length;
1581}
1582
95ea3627 1583static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1584 const enum data_queue_qid queue)
95ea3627
ID		 1585{
1586 u32 reg;
1587
f019d514
ID		 1588 if (queue != QID_BEACON) {
1589 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1590 return;
f019d514 1591 }
95ea3627
ID		 1592
1593 /*
1594 * For Wi-Fi faily generated beacons between participating stations.
1595 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1596 */
0f829b1d 1597 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
95ea3627 1598
0f829b1d 1599 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
95ea3627 1600 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1601 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1602 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 1603 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
0f829b1d 1604 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 1605 }
1606}
1607
1608/*
1609 * RX control handlers
1610 */
1611static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1612{
ba2ab471 1613 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1614 u8 lna;
1615
1616 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1617 switch (lna) {
1618 case 3:
ba2ab471 1619 offset += 90;
95ea3627
ID		 1620 break;
1621 case 2:
ba2ab471 1622 offset += 74;
95ea3627
ID		 1623 break;
1624 case 1:
ba2ab471 1625 offset += 64;
95ea3627
ID		 1626 break;
1627 default:
1628 return 0;
1629 }
1630
8318d78a 1631 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1632 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1633 if (lna == 3 || lna == 2)
1634 offset += 10;
1635 } else {
1636 if (lna == 3)
1637 offset += 6;
1638 else if (lna == 2)
1639 offset += 8;
1640 }
95ea3627
ID		 1641 }
1642
1643 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1644}
1645
181d6902 1646static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1647 struct rxdone_entry_desc *rxdesc)
95ea3627 1648{
906c110f 1649 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1650 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1651 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1652 u32 word0;
1653 u32 word1;
1654
f855c10b 1655 /*
a26cbc65
GW		 1656 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1657 * frame data in rt2x00usb.
f855c10b 1658 */
a26cbc65 1659 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1660 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1661
1662 /*
70a96109 1663 * It is now safe to read the descriptor on all architectures.
f855c10b 1664 */
95ea3627
ID		 1665 rt2x00_desc_read(rxd, 0, &word0);
1666 rt2x00_desc_read(rxd, 1, &word1);
1667
4150c572 1668 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1669 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1670
906c110f
ID		 1671 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1672 rxdesc->cipher =
1673 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1674 rxdesc->cipher_status =
1675 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1676 }
1677
1678 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1679 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1680 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1681 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1682
906c110f 1683 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1684 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1685
1686 /*
1687 * Hardware has stripped IV/EIV data from 802.11 frame during
1688 * decryption. It has provided the data seperately but rt2x00lib
1689 * should decide if it should be reinserted.
1690 */
1691 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1692
1693 /*
1694 * FIXME: Legacy driver indicates that the frame does
1695 * contain the Michael Mic. Unfortunately, in rt2x00
1696 * the MIC seems to be missing completely...
1697 */
1698 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1699
1700 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1701 rxdesc->flags |= RX_FLAG_DECRYPTED;
1702 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1703 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1704 }
1705
95ea3627
ID		 1706 /*
1707 * Obtain the status about this packet.
89993890
ID		 1708 * When frame was received with an OFDM bitrate,
1709 * the signal is the PLCP value. If it was received with
1710 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1711 */
181d6902 1712 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1713 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1714 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1715
19d30e02
ID		 1716 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1717 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1718 else
1719 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1720 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1721 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1722
2ae23854 1723 /*
70a96109 1724 * Set skb pointers, and update frame information.
2ae23854 1725 */
70a96109 1726 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1727 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1728}
1729
1730/*
1731 * Device probe functions.
1732 */
1733static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1734{
1735 u16 word;
1736 u8 *mac;
1737 s8 value;
1738
1739 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1740
1741 /*
1742 * Start validation of the data that has been read.
1743 */
1744 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1745 if (!is_valid_ether_addr(mac)) {
1746 random_ether_addr(mac);
e174961c 1747 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1748 }
1749
1750 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1751 if (word == 0xffff) {
1752 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1753 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1754 ANTENNA_B);
1755 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1756 ANTENNA_B);
95ea3627
ID		 1757 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1758 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1759 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1760 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1761 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1762 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1763 }
1764
1765 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1766 if (word == 0xffff) {
1767 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1768 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1769 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1770 }
1771
1772 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1773 if (word == 0xffff) {
1774 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1775 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1776 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1777 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1778 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1779 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1780 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1781 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1782 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1783 LED_MODE_DEFAULT);
1784 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1785 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1786 }
1787
1788 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1789 if (word == 0xffff) {
1790 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1791 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1792 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1793 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1794 }
1795
1796 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1797 if (word == 0xffff) {
1798 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1799 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1800 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1801 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1802 } else {
1803 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1804 if (value < -10 || value > 10)
1805 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1806 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1807 if (value < -10 || value > 10)
1808 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1809 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1810 }
1811
1812 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1813 if (word == 0xffff) {
1814 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1815 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1816 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1817 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1818 } else {
1819 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1820 if (value < -10 || value > 10)
1821 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1822 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1823 if (value < -10 || value > 10)
1824 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1825 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1826 }
1827
1828 return 0;
1829}
1830
1831static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1832{
1833 u32 reg;
1834 u16 value;
1835 u16 eeprom;
1836
1837 /*
1838 * Read EEPROM word for configuration.
1839 */
1840 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1841
1842 /*
1843 * Identify RF chipset.
1844 */
1845 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1846 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1847 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1848
755a957d 1849 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1850 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1851 return -ENODEV;
1852 }
1853
1854 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1855 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1856 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1857 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1858 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1859 return -ENODEV;
1860 }
1861
1862 /*
1863 * Identify default antenna configuration.
1864 */
addc81bd 1865 rt2x00dev->default_ant.tx =
95ea3627 1866 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1867 rt2x00dev->default_ant.rx =
95ea3627
ID		 1868 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1869
1870 /*
1871 * Read the Frame type.
1872 */
1873 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1874 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1875
7396faf4
ID		 1876 /*
1877 * Detect if this device has an hardware controlled radio.
1878 */
1879#ifdef CONFIG_RT2X00_LIB_RFKILL
1880 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1881 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1882#endif /* CONFIG_RT2X00_LIB_RFKILL */
1883
95ea3627
ID		 1884 /*
1885 * Read frequency offset.
1886 */
1887 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1888 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1889
1890 /*
1891 * Read external LNA informations.
1892 */
1893 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1894
1895 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1896 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1897 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1898 }
1899
1900 /*
1901 * Store led settings, for correct led behaviour.
1902 */
771fd565 1903#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1904 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1905
475433be
ID		 1906 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1907 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1908 if (value == LED_MODE_SIGNAL_STRENGTH)
1909 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1910 LED_TYPE_QUALITY);
a9450b70
ID		 1911
1912 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1913 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1914 rt2x00_get_field16(eeprom,
1915 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1916 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1917 rt2x00_get_field16(eeprom,
1918 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1919 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1920 rt2x00_get_field16(eeprom,
1921 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1922 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1923 rt2x00_get_field16(eeprom,
1924 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1925 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1926 rt2x00_get_field16(eeprom,
1927 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1928 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1929 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1930 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1931 rt2x00_get_field16(eeprom,
1932 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1933 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1934 rt2x00_get_field16(eeprom,
1935 EEPROM_LED_POLARITY_RDY_A));
771fd565 1936#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1937
1938 return 0;
1939}
1940
1941/*
1942 * RF value list for RF2528
1943 * Supports: 2.4 GHz
1944 */
1945static const struct rf_channel rf_vals_bg_2528[] = {
1946 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1947 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1948 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1949 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1950 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1951 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1952 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1953 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1954 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1955 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1956 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1957 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1958 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1959 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1960};
1961
1962/*
1963 * RF value list for RF5226
1964 * Supports: 2.4 GHz & 5.2 GHz
1965 */
1966static const struct rf_channel rf_vals_5226[] = {
1967 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1968 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1969 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1970 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1971 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1972 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1973 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1974 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1975 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1976 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1977 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1978 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1979 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1980 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1981
1982 /* 802.11 UNI / HyperLan 2 */
1983 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1984 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1985 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1986 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1987 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1988 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1989 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1990 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1991
1992 /* 802.11 HyperLan 2 */
1993 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1994 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1995 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1996 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1997 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1998 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1999 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2000 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2001 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2002 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2003
2004 /* 802.11 UNII */
2005 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2006 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2007 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2008 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2009 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2010 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2011
2012 /* MMAC(Japan)J52 ch 34,38,42,46 */
2013 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2014 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2015 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2016 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2017};
2018
2019/*
2020 * RF value list for RF5225 & RF2527
2021 * Supports: 2.4 GHz & 5.2 GHz
2022 */
2023static const struct rf_channel rf_vals_5225_2527[] = {
2024 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2025 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2026 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2027 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2028 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2029 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2030 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2031 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2032 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2033 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2034 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2035 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2036 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2037 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2038
2039 /* 802.11 UNI / HyperLan 2 */
2040 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2041 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2042 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2043 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2044 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2045 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2046 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2047 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2048
2049 /* 802.11 HyperLan 2 */
2050 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2051 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2052 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2053 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2054 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2055 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2056 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2057 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2058 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2059 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2060
2061 /* 802.11 UNII */
2062 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2063 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2064 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2065 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2066 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2067 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2068
2069 /* MMAC(Japan)J52 ch 34,38,42,46 */
2070 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2071 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2072 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2073 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2074};
2075
2076
8c5e7a5f 2077static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2078{
2079 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2080 struct channel_info *info;
2081 char *tx_power;
95ea3627
ID		 2082 unsigned int i;
2083
2084 /*
2085 * Initialize all hw fields.
2086 */
2087 rt2x00dev->hw->flags =
566bfe5a 2088 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2089 IEEE80211_HW_SIGNAL_DBM |
2090 IEEE80211_HW_SUPPORTS_PS |
2091 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2092 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
95ea3627 2093
14a3bf89 2094 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2095 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2096 rt2x00_eeprom_addr(rt2x00dev,
2097 EEPROM_MAC_ADDR_0));
2098
95ea3627
ID		 2099 /*
2100 * Initialize hw_mode information.
2101 */
31562e80
ID		 2102 spec->supported_bands = SUPPORT_BAND_2GHZ;
2103 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2104
2105 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2106 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2107 spec->channels = rf_vals_bg_2528;
2108 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 2109 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2110 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2111 spec->channels = rf_vals_5226;
2112 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2113 spec->num_channels = 14;
2114 spec->channels = rf_vals_5225_2527;
2115 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 2116 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2117 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2118 spec->channels = rf_vals_5225_2527;
2119 }
2120
8c5e7a5f
ID		 2121 /*
2122 * Create channel information array
2123 */
2124 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2125 if (!info)
2126 return -ENOMEM;
95ea3627 2127
8c5e7a5f
ID		 2128 spec->channels_info = info;
2129
2130 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2131 for (i = 0; i < 14; i++)
2132 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2133
2134 if (spec->num_channels > 14) {
2135 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2136 for (i = 14; i < spec->num_channels; i++)
2137 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2138 }
8c5e7a5f
ID		 2139
2140 return 0;
95ea3627
ID		 2141}
2142
2143static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2144{
2145 int retval;
2146
2147 /*
2148 * Allocate eeprom data.
2149 */
2150 retval = rt73usb_validate_eeprom(rt2x00dev);
2151 if (retval)
2152 return retval;
2153
2154 retval = rt73usb_init_eeprom(rt2x00dev);
2155 if (retval)
2156 return retval;
2157
2158 /*
2159 * Initialize hw specifications.
2160 */
8c5e7a5f
ID		 2161 retval = rt73usb_probe_hw_mode(rt2x00dev);
2162 if (retval)
2163 return retval;
95ea3627
ID		 2164
2165 /*
9404ef34 2166 * This device requires firmware.
95ea3627 2167 */
066cb637 2168 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 2169 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
008c4482
ID		 2170 if (!modparam_nohwcrypt)
2171 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2172
2173 /*
2174 * Set the rssi offset.
2175 */
2176 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2177
2178 return 0;
2179}
2180
2181/*
2182 * IEEE80211 stack callback functions.
2183 */
2af0a570
ID		 2184static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2185 const struct ieee80211_tx_queue_params *params)
2186{
2187 struct rt2x00_dev *rt2x00dev = hw->priv;
2188 struct data_queue *queue;
2189 struct rt2x00_field32 field;
2190 int retval;
2191 u32 reg;
5e790023 2192 u32 offset;
2af0a570
ID		 2193
2194 /*
2195 * First pass the configuration through rt2x00lib, that will
2196 * update the queue settings and validate the input. After that
2197 * we are free to update the registers based on the value
2198 * in the queue parameter.
2199 */
2200 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2201 if (retval)
2202 return retval;
2203
5e790023
ID		 2204 /*
2205 * We only need to perform additional register initialization
2206 * for WMM queues/
2207 */
2208 if (queue_idx >= 4)
2209 return 0;
2210
2af0a570
ID		 2211 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2212
2213 /* Update WMM TXOP register */
5e790023
ID		 2214 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2215 field.bit_offset = (queue_idx & 1) * 16;
2216 field.bit_mask = 0xffff << field.bit_offset;
2217
2218 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2219 rt2x00_set_field32(&reg, field, queue->txop);
2220 rt2x00usb_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2221
2222 /* Update WMM registers */
2223 field.bit_offset = queue_idx * 4;
2224 field.bit_mask = 0xf << field.bit_offset;
2225
0f829b1d 2226 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2227 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2228 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2229
0f829b1d 2230 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2231 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2232 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2233
0f829b1d 2234 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2235 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2236 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2237
2238 return 0;
2239}
2240
95ea3627
ID		 2241static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2242{
2243 struct rt2x00_dev *rt2x00dev = hw->priv;
2244 u64 tsf;
2245 u32 reg;
2246
0f829b1d 2247 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2248 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2249 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2250 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2251
2252 return tsf;
2253}
95ea3627 2254
95ea3627
ID		 2255static const struct ieee80211_ops rt73usb_mac80211_ops = {
2256 .tx = rt2x00mac_tx,
4150c572
JB		 2257 .start = rt2x00mac_start,
2258 .stop = rt2x00mac_stop,
95ea3627
ID		 2259 .add_interface = rt2x00mac_add_interface,
2260 .remove_interface = rt2x00mac_remove_interface,
2261 .config = rt2x00mac_config,
2262 .config_interface = rt2x00mac_config_interface,
3a643d24 2263 .configure_filter = rt2x00mac_configure_filter,
906c110f 2264 .set_key = rt2x00mac_set_key,
95ea3627 2265 .get_stats = rt2x00mac_get_stats,
471b3efd 2266 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2267 .conf_tx = rt73usb_conf_tx,
95ea3627 2268 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2269 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2270};
2271
2272static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2273 .probe_hw = rt73usb_probe_hw,
2274 .get_firmware_name = rt73usb_get_firmware_name,
0cbe0064 2275 .check_firmware = rt73usb_check_firmware,
95ea3627
ID		 2276 .load_firmware = rt73usb_load_firmware,
2277 .initialize = rt2x00usb_initialize,
2278 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2279 .clear_entry = rt2x00usb_clear_entry,
95ea3627 2280 .set_device_state = rt73usb_set_device_state,
7396faf4 2281 .rfkill_poll = rt73usb_rfkill_poll,
95ea3627
ID		 2282 .link_stats = rt73usb_link_stats,
2283 .reset_tuner = rt73usb_reset_tuner,
2284 .link_tuner = rt73usb_link_tuner,
2285 .write_tx_desc = rt73usb_write_tx_desc,
2286 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2287 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2288 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627 2289 .kick_tx_queue = rt73usb_kick_tx_queue,
a2c9b652 2290 .kill_tx_queue = rt2x00usb_kill_tx_queue,
95ea3627 2291 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2292 .config_shared_key = rt73usb_config_shared_key,
2293 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2294 .config_filter = rt73usb_config_filter,
6bb40dd1 2295 .config_intf = rt73usb_config_intf,
72810379 2296 .config_erp = rt73usb_config_erp,
e4ea1c40 2297 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2298 .config = rt73usb_config,
2299};
2300
181d6902
ID		 2301static const struct data_queue_desc rt73usb_queue_rx = {
2302 .entry_num = RX_ENTRIES,
2303 .data_size = DATA_FRAME_SIZE,
2304 .desc_size = RXD_DESC_SIZE,
b8be63ff 2305 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2306};
2307
2308static const struct data_queue_desc rt73usb_queue_tx = {
2309 .entry_num = TX_ENTRIES,
2310 .data_size = DATA_FRAME_SIZE,
2311 .desc_size = TXD_DESC_SIZE,
b8be63ff 2312 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2313};
2314
2315static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2316 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2317 .data_size = MGMT_FRAME_SIZE,
2318 .desc_size = TXINFO_SIZE,
b8be63ff 2319 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2320};
2321
95ea3627 2322static const struct rt2x00_ops rt73usb_ops = {
2360157c 2323 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2324 .max_sta_intf = 1,
2325 .max_ap_intf = 4,
95ea3627
ID		 2326 .eeprom_size = EEPROM_SIZE,
2327 .rf_size = RF_SIZE,
61448f88 2328 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2329 .rx = &rt73usb_queue_rx,
2330 .tx = &rt73usb_queue_tx,
2331 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2332 .lib = &rt73usb_rt2x00_ops,
2333 .hw = &rt73usb_mac80211_ops,
2334#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2335 .debugfs = &rt73usb_rt2x00debug,
2336#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2337};
2338
2339/*
2340 * rt73usb module information.
2341 */
2342static struct usb_device_id rt73usb_device_table[] = {
2343 /* AboCom */
ef4bb70d
XVP		 2344 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2345 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2346 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2347 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2348 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2349 /* AL */
2350 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2351 /* Amigo */
2352 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2353 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2354 /* AMIT */
2355 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2356 /* Askey */
2357 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2358 /* ASUS */
2359 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2360 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2361 /* Belkin */
2362 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2363 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2364 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2365 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2366 /* Billionton */
2367 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2368 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2369 /* Buffalo */
964d6ad9 2370 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2371 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2372 /* CNet */
2373 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2374 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2375 /* Conceptronic */
2376 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2377 /* Corega */
2378 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2379 /* D-Link */
2380 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2381 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2382 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2383 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2384 /* Edimax */
2385 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2386 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2387 /* EnGenius */
2388 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2389 /* Gemtek */
2390 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2391 /* Gigabyte */
2392 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2393 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2394 /* Huawei-3Com */
2395 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2396 /* Hercules */
2397 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2398 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2399 /* Linksys */
2400 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2401 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
3be36ae2 2402 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2403 /* MSI */
2404 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2405 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2406 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2407 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2408 /* Ralink */
144d9ad9 2409 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2410 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2411 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2412 /* Qcom */
2413 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2414 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2415 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2416 /* Samsung */
2417 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2418 /* Senao */
2419 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2420 /* Sitecom */
ef4bb70d
XVP		 2421 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2422 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2423 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2424 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2425 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2426 /* Surecom */
2427 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2428 /* Philips */
2429 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2430 /* Planex */
2431 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2432 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2433 /* Zcom */
2434 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2435 /* ZyXEL */
2436 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2437 { 0, }
2438};
2439
2440MODULE_AUTHOR(DRV_PROJECT);
2441MODULE_VERSION(DRV_VERSION);
2442MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2443MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2444MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2445MODULE_FIRMWARE(FIRMWARE_RT2571);
2446MODULE_LICENSE("GPL");
2447
2448static struct usb_driver rt73usb_driver = {
2360157c 2449 .name = KBUILD_MODNAME,
95ea3627
ID		 2450 .id_table = rt73usb_device_table,
2451 .probe = rt2x00usb_probe,
2452 .disconnect = rt2x00usb_disconnect,
2453 .suspend = rt2x00usb_suspend,
2454 .resume = rt2x00usb_resume,
2455};
2456
2457static int __init rt73usb_init(void)
2458{
2459 return usb_register(&rt73usb_driver);
2460}
2461
2462static void __exit rt73usb_exit(void)
2463{
2464 usb_deregister(&rt73usb_driver);
2465}
2466
2467module_init(rt73usb_init);
2468module_exit(rt73usb_exit);
Linux 6.x block layer and io_uring tree(s)