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mac80211: Fix reassociation processing (within ESS roaming)
[linux-block.git] / drivers / net / wireless / rt2x00 / rt73usb.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
008c4482
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 0;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
0f829b1d 49 * rt2x00usb_register_read and rt2x00usb_register_write.
95ea3627
ID		 50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 59 */
c9c3b1a5 60#define WAIT_FOR_BBP(__dev, __reg) \
0f829b1d 61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
c9c3b1a5 62#define WAIT_FOR_RF(__dev, __reg) \
0f829b1d 63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
c9c3b1a5 64
0e14f6d3 65static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 66 const unsigned int word, const u8 value)
67{
68 u32 reg;
69
8ff48a8b 70 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 71
95ea3627 72 /*
c9c3b1a5
ID		 73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
95ea3627 75 */
c9c3b1a5
ID		 76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
77 reg = 0;
78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
82
0f829b1d 83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
c9c3b1a5 84 }
99ade259 85
8ff48a8b 86 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 87}
88
0e14f6d3 89static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 90 const unsigned int word, u8 *value)
91{
92 u32 reg;
93
8ff48a8b 94 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 95
95ea3627 96 /*
c9c3b1a5
ID		 97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
95ea3627 103 */
c9c3b1a5
ID		 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
105 reg = 0;
106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
95ea3627 109
0f829b1d 110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627 111
c9c3b1a5
ID		 112 WAIT_FOR_BBP(rt2x00dev, &reg);
113 }
95ea3627
ID		 114
115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
99ade259 116
8ff48a8b 117 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 118}
119
0e14f6d3 120static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 121 const unsigned int word, const u32 value)
122{
123 u32 reg;
95ea3627 124
8ff48a8b 125 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 126
4f5af6eb 127 /*
c9c3b1a5
ID		 128 * Wait until the RF becomes available, afterwards we
129 * can safely write the new data into the register.
4f5af6eb 130 */
c9c3b1a5
ID		 131 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
132 reg = 0;
133 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
134 /*
135 * RF5225 and RF2527 contain 21 bits per RF register value,
136 * all others contain 20 bits.
137 */
138 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
5122d898
GW		 139 20 + (rt2x00_rf(rt2x00dev, RF5225) ||
140 rt2x00_rf(rt2x00dev, RF2527)));
c9c3b1a5
ID		 141 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
142 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
143
0f829b1d 144 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
c9c3b1a5
ID		 145 rt2x00_rf_write(rt2x00dev, word, value);
146 }
8ff48a8b
ID		 147
148 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 149}
150
151#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 152static const struct rt2x00debug rt73usb_rt2x00debug = {
153 .owner = THIS_MODULE,
154 .csr = {
0f829b1d
ID		 155 .read = rt2x00usb_register_read,
156 .write = rt2x00usb_register_write,
743b97ca
ID		 157 .flags = RT2X00DEBUGFS_OFFSET,
158 .word_base = CSR_REG_BASE,
95ea3627
ID		 159 .word_size = sizeof(u32),
160 .word_count = CSR_REG_SIZE / sizeof(u32),
161 },
162 .eeprom = {
163 .read = rt2x00_eeprom_read,
164 .write = rt2x00_eeprom_write,
743b97ca 165 .word_base = EEPROM_BASE,
95ea3627
ID		 166 .word_size = sizeof(u16),
167 .word_count = EEPROM_SIZE / sizeof(u16),
168 },
169 .bbp = {
170 .read = rt73usb_bbp_read,
171 .write = rt73usb_bbp_write,
743b97ca 172 .word_base = BBP_BASE,
95ea3627
ID		 173 .word_size = sizeof(u8),
174 .word_count = BBP_SIZE / sizeof(u8),
175 },
176 .rf = {
177 .read = rt2x00_rf_read,
178 .write = rt73usb_rf_write,
743b97ca 179 .word_base = RF_BASE,
95ea3627
ID		 180 .word_size = sizeof(u32),
181 .word_count = RF_SIZE / sizeof(u32),
182 },
183};
184#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
185
7396faf4
ID		 186static int rt73usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
187{
188 u32 reg;
189
190 rt2x00usb_register_read(rt2x00dev, MAC_CSR13, &reg);
191 return rt2x00_get_field32(reg, MAC_CSR13_BIT7);
192}
7396faf4 193
771fd565 194#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 195static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 196 enum led_brightness brightness)
197{
198 struct rt2x00_led *led =
199 container_of(led_cdev, struct rt2x00_led, led_dev);
200 unsigned int enabled = brightness != LED_OFF;
201 unsigned int a_mode =
202 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
203 unsigned int bg_mode =
204 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
205
206 if (led->type == LED_TYPE_RADIO) {
207 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
208 MCU_LEDCS_RADIO_STATUS, enabled);
209
47b10cd1
ID		 210 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
211 0, led->rt2x00dev->led_mcu_reg,
212 REGISTER_TIMEOUT);
a9450b70
ID		 213 } else if (led->type == LED_TYPE_ASSOC) {
214 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
215 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
216 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
217 MCU_LEDCS_LINK_A_STATUS, a_mode);
218
47b10cd1
ID		 219 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
220 0, led->rt2x00dev->led_mcu_reg,
221 REGISTER_TIMEOUT);
a9450b70
ID		 222 } else if (led->type == LED_TYPE_QUALITY) {
223 /*
224 * The brightness is divided into 6 levels (0 - 5),
225 * this means we need to convert the brightness
226 * argument into the matching level within that range.
227 */
47b10cd1
ID		 228 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
229 brightness / (LED_FULL / 6),
230 led->rt2x00dev->led_mcu_reg,
231 REGISTER_TIMEOUT);
a9450b70
ID		 232 }
233}
a2e1d52a
ID		 234
235static int rt73usb_blink_set(struct led_classdev *led_cdev,
236 unsigned long *delay_on,
237 unsigned long *delay_off)
238{
239 struct rt2x00_led *led =
240 container_of(led_cdev, struct rt2x00_led, led_dev);
241 u32 reg;
242
0f829b1d 243 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
a2e1d52a
ID		 244 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
245 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
0f829b1d 246 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
a2e1d52a
ID		 247
248 return 0;
249}
475433be
ID		 250
251static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
252 struct rt2x00_led *led,
253 enum led_type type)
254{
255 led->rt2x00dev = rt2x00dev;
256 led->type = type;
257 led->led_dev.brightness_set = rt73usb_brightness_set;
258 led->led_dev.blink_set = rt73usb_blink_set;
259 led->flags = LED_INITIALIZED;
260}
771fd565 261#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 262
95ea3627
ID		 263/*
264 * Configuration handlers.
265 */
906c110f
ID		 266static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
267 struct rt2x00lib_crypto *crypto,
268 struct ieee80211_key_conf *key)
269{
270 struct hw_key_entry key_entry;
271 struct rt2x00_field32 field;
272 int timeout;
273 u32 mask;
274 u32 reg;
275
276 if (crypto->cmd == SET_KEY) {
277 /*
278 * rt2x00lib can't determine the correct free
279 * key_idx for shared keys. We have 1 register
280 * with key valid bits. The goal is simple, read
281 * the register, if that is full we have no slots
282 * left.
283 * Note that each BSS is allowed to have up to 4
284 * shared keys, so put a mask over the allowed
285 * entries.
286 */
287 mask = (0xf << crypto->bssidx);
288
0f829b1d 289 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 290 reg &= mask;
291
292 if (reg && reg == mask)
293 return -ENOSPC;
294
acaf908d 295 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 296
297 /*
298 * Upload key to hardware
299 */
300 memcpy(key_entry.key, crypto->key,
301 sizeof(key_entry.key));
302 memcpy(key_entry.tx_mic, crypto->tx_mic,
303 sizeof(key_entry.tx_mic));
304 memcpy(key_entry.rx_mic, crypto->rx_mic,
305 sizeof(key_entry.rx_mic));
306
307 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
308 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
309 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
310 USB_VENDOR_REQUEST_OUT, reg,
311 &key_entry,
312 sizeof(key_entry),
313 timeout);
314
315 /*
316 * The cipher types are stored over 2 registers.
317 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
318 * bssidx 1 and 2 keys are stored in SEC_CSR5.
319 * Using the correct defines correctly will cause overhead,
320 * so just calculate the correct offset.
321 */
322 if (key->hw_key_idx < 8) {
323 field.bit_offset = (3 * key->hw_key_idx);
324 field.bit_mask = 0x7 << field.bit_offset;
325
0f829b1d 326 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
906c110f 327 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 328 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
906c110f
ID		 329 } else {
330 field.bit_offset = (3 * (key->hw_key_idx - 8));
331 field.bit_mask = 0x7 << field.bit_offset;
332
0f829b1d 333 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
906c110f 334 rt2x00_set_field32(&reg, field, crypto->cipher);
0f829b1d 335 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
906c110f
ID		 336 }
337
338 /*
339 * The driver does not support the IV/EIV generation
340 * in hardware. However it doesn't support the IV/EIV
341 * inside the ieee80211 frame either, but requires it
342 * to be provided seperately for the descriptor.
343 * rt2x00lib will cut the IV/EIV data out of all frames
344 * given to us by mac80211, but we must tell mac80211
345 * to generate the IV/EIV data.
346 */
347 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
348 }
349
350 /*
351 * SEC_CSR0 contains only single-bit fields to indicate
352 * a particular key is valid. Because using the FIELD32()
353 * defines directly will cause a lot of overhead we use
354 * a calculation to determine the correct bit directly.
355 */
356 mask = 1 << key->hw_key_idx;
357
0f829b1d 358 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
906c110f
ID		 359 if (crypto->cmd == SET_KEY)
360 reg |= mask;
361 else if (crypto->cmd == DISABLE_KEY)
362 reg &= ~mask;
0f829b1d 363 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
906c110f
ID		 364
365 return 0;
366}
367
368static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
369 struct rt2x00lib_crypto *crypto,
370 struct ieee80211_key_conf *key)
371{
372 struct hw_pairwise_ta_entry addr_entry;
373 struct hw_key_entry key_entry;
374 int timeout;
375 u32 mask;
376 u32 reg;
377
378 if (crypto->cmd == SET_KEY) {
379 /*
380 * rt2x00lib can't determine the correct free
381 * key_idx for pairwise keys. We have 2 registers
382 * with key valid bits. The goal is simple, read
383 * the first register, if that is full move to
384 * the next register.
385 * When both registers are full, we drop the key,
386 * otherwise we use the first invalid entry.
387 */
0f829b1d 388 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 389 if (reg && reg == ~0) {
390 key->hw_key_idx = 32;
0f829b1d 391 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 392 if (reg && reg == ~0)
393 return -ENOSPC;
394 }
395
acaf908d 396 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 397
398 /*
399 * Upload key to hardware
400 */
401 memcpy(key_entry.key, crypto->key,
402 sizeof(key_entry.key));
403 memcpy(key_entry.tx_mic, crypto->tx_mic,
404 sizeof(key_entry.tx_mic));
405 memcpy(key_entry.rx_mic, crypto->rx_mic,
406 sizeof(key_entry.rx_mic));
407
408 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
409 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
410 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
411 USB_VENDOR_REQUEST_OUT, reg,
412 &key_entry,
413 sizeof(key_entry),
414 timeout);
415
416 /*
417 * Send the address and cipher type to the hardware register.
418 * This data fits within the CSR cache size, so we can use
0f829b1d 419 * rt2x00usb_register_multiwrite() directly.
906c110f
ID		 420 */
421 memset(&addr_entry, 0, sizeof(addr_entry));
422 memcpy(&addr_entry, crypto->address, ETH_ALEN);
423 addr_entry.cipher = crypto->cipher;
424
425 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
0f829b1d 426 rt2x00usb_register_multiwrite(rt2x00dev, reg,
906c110f
ID		 427 &addr_entry, sizeof(addr_entry));
428
429 /*
430 * Enable pairwise lookup table for given BSS idx,
431 * without this received frames will not be decrypted
432 * by the hardware.
433 */
0f829b1d 434 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
906c110f 435 reg |= (1 << crypto->bssidx);
0f829b1d 436 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
906c110f
ID		 437
438 /*
439 * The driver does not support the IV/EIV generation
440 * in hardware. However it doesn't support the IV/EIV
441 * inside the ieee80211 frame either, but requires it
442 * to be provided seperately for the descriptor.
443 * rt2x00lib will cut the IV/EIV data out of all frames
444 * given to us by mac80211, but we must tell mac80211
445 * to generate the IV/EIV data.
446 */
447 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
448 }
449
450 /*
451 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
452 * a particular key is valid. Because using the FIELD32()
453 * defines directly will cause a lot of overhead we use
454 * a calculation to determine the correct bit directly.
455 */
456 if (key->hw_key_idx < 32) {
457 mask = 1 << key->hw_key_idx;
458
0f829b1d 459 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
906c110f
ID		 460 if (crypto->cmd == SET_KEY)
461 reg |= mask;
462 else if (crypto->cmd == DISABLE_KEY)
463 reg &= ~mask;
0f829b1d 464 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
906c110f
ID		 465 } else {
466 mask = 1 << (key->hw_key_idx - 32);
467
0f829b1d 468 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
906c110f
ID		 469 if (crypto->cmd == SET_KEY)
470 reg |= mask;
471 else if (crypto->cmd == DISABLE_KEY)
472 reg &= ~mask;
0f829b1d 473 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
906c110f
ID		 474 }
475
476 return 0;
477}
478
3a643d24
ID		 479static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
480 const unsigned int filter_flags)
481{
482 u32 reg;
483
484 /*
485 * Start configuration steps.
486 * Note that the version error will always be dropped
487 * and broadcast frames will always be accepted since
488 * there is no filter for it at this time.
489 */
0f829b1d 490 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
3a643d24
ID		 491 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
492 !(filter_flags & FIF_FCSFAIL));
493 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
494 !(filter_flags & FIF_PLCPFAIL));
495 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
1afcfd54 496 !(filter_flags & (FIF_CONTROL | FIF_PSPOLL)));
3a643d24
ID		 497 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
498 !(filter_flags & FIF_PROMISC_IN_BSS));
499 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 500 !(filter_flags & FIF_PROMISC_IN_BSS) &&
501 !rt2x00dev->intf_ap_count);
3a643d24
ID		 502 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
503 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
504 !(filter_flags & FIF_ALLMULTI));
505 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
506 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
507 !(filter_flags & FIF_CONTROL));
0f829b1d 508 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
3a643d24
ID		 509}
510
6bb40dd1
ID		 511static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
512 struct rt2x00_intf *intf,
513 struct rt2x00intf_conf *conf,
514 const unsigned int flags)
95ea3627 515{
6bb40dd1
ID		 516 unsigned int beacon_base;
517 u32 reg;
95ea3627 518
6bb40dd1
ID		 519 if (flags & CONFIG_UPDATE_TYPE) {
520 /*
521 * Clear current synchronisation setup.
522 * For the Beacon base registers we only need to clear
523 * the first byte since that byte contains the VALID and OWNER
524 * bits which (when set to 0) will invalidate the entire beacon.
525 */
526 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
0f829b1d 527 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 528
6bb40dd1
ID		 529 /*
530 * Enable synchronisation.
531 */
0f829b1d 532 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 533 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 534 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 535 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
0f829b1d 536 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
6bb40dd1 537 }
95ea3627 538
6bb40dd1
ID		 539 if (flags & CONFIG_UPDATE_MAC) {
540 reg = le32_to_cpu(conf->mac[1]);
541 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
542 conf->mac[1] = cpu_to_le32(reg);
95ea3627 543
0f829b1d 544 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
6bb40dd1
ID		 545 conf->mac, sizeof(conf->mac));
546 }
95ea3627 547
6bb40dd1
ID		 548 if (flags & CONFIG_UPDATE_BSSID) {
549 reg = le32_to_cpu(conf->bssid[1]);
550 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
551 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 552
0f829b1d 553 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
6bb40dd1
ID		 554 conf->bssid, sizeof(conf->bssid));
555 }
95ea3627
ID		 556}
557
3a643d24
ID		 558static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
559 struct rt2x00lib_erp *erp)
95ea3627 560{
95ea3627 561 u32 reg;
95ea3627 562
0f829b1d 563 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
4789666e 564 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32);
8a566afe 565 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
0f829b1d 566 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 567
0f829b1d 568 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
8a566afe 569 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
4f5af6eb 570 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 571 !!erp->short_preamble);
0f829b1d 572 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 573
0f829b1d 574 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 575
8a566afe
ID		 576 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
577 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
578 erp->beacon_int * 16);
579 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
580
0f829b1d 581 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
e4ea1c40 582 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
0f829b1d 583 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 584
0f829b1d 585 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
e4ea1c40
ID		 586 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
587 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
588 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
0f829b1d 589 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 590}
591
592static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 593 struct antenna_setup *ant)
95ea3627
ID		 594{
595 u8 r3;
596 u8 r4;
597 u8 r77;
2676c94d 598 u8 temp;
95ea3627
ID		 599
600 rt73usb_bbp_read(rt2x00dev, 3, &r3);
601 rt73usb_bbp_read(rt2x00dev, 4, &r4);
602 rt73usb_bbp_read(rt2x00dev, 77, &r77);
603
604 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
605
e4cd2ff8
ID		 606 /*
607 * Configure the RX antenna.
608 */
addc81bd 609 switch (ant->rx) {
95ea3627 610 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 611 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
612 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 613 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 614 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 615 break;
616 case ANTENNA_A:
2676c94d 617 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 618 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 619 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 620 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
621 else
622 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 623 break;
624 case ANTENNA_B:
a4fe07d9 625 default:
2676c94d 626 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 627 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 628 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 629 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
630 else
631 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 632 break;
633 }
634
635 rt73usb_bbp_write(rt2x00dev, 77, r77);
636 rt73usb_bbp_write(rt2x00dev, 3, r3);
637 rt73usb_bbp_write(rt2x00dev, 4, r4);
638}
639
640static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 641 struct antenna_setup *ant)
95ea3627
ID		 642{
643 u8 r3;
644 u8 r4;
645 u8 r77;
646
647 rt73usb_bbp_read(rt2x00dev, 3, &r3);
648 rt73usb_bbp_read(rt2x00dev, 4, &r4);
649 rt73usb_bbp_read(rt2x00dev, 77, &r77);
650
651 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
652 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
653 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
654
e4cd2ff8
ID		 655 /*
656 * Configure the RX antenna.
657 */
addc81bd 658 switch (ant->rx) {
95ea3627 659 case ANTENNA_HW_DIVERSITY:
2676c94d 660 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 661 break;
662 case ANTENNA_A:
2676c94d
MN		 663 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
664 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 665 break;
666 case ANTENNA_B:
a4fe07d9 667 default:
2676c94d
MN		 668 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
669 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 670 break;
671 }
672
673 rt73usb_bbp_write(rt2x00dev, 77, r77);
674 rt73usb_bbp_write(rt2x00dev, 3, r3);
675 rt73usb_bbp_write(rt2x00dev, 4, r4);
676}
677
678struct antenna_sel {
679 u8 word;
680 /*
681 * value[0] -> non-LNA
682 * value[1] -> LNA
683 */
684 u8 value[2];
685};
686
687static const struct antenna_sel antenna_sel_a[] = {
688 { 96, { 0x58, 0x78 } },
689 { 104, { 0x38, 0x48 } },
690 { 75, { 0xfe, 0x80 } },
691 { 86, { 0xfe, 0x80 } },
692 { 88, { 0xfe, 0x80 } },
693 { 35, { 0x60, 0x60 } },
694 { 97, { 0x58, 0x58 } },
695 { 98, { 0x58, 0x58 } },
696};
697
698static const struct antenna_sel antenna_sel_bg[] = {
699 { 96, { 0x48, 0x68 } },
700 { 104, { 0x2c, 0x3c } },
701 { 75, { 0xfe, 0x80 } },
702 { 86, { 0xfe, 0x80 } },
703 { 88, { 0xfe, 0x80 } },
704 { 35, { 0x50, 0x50 } },
705 { 97, { 0x48, 0x48 } },
706 { 98, { 0x48, 0x48 } },
707};
708
e4ea1c40
ID		 709static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
710 struct antenna_setup *ant)
95ea3627
ID		 711{
712 const struct antenna_sel *sel;
713 unsigned int lna;
714 unsigned int i;
715 u32 reg;
716
a4fe07d9
ID		 717 /*
718 * We should never come here because rt2x00lib is supposed
719 * to catch this and send us the correct antenna explicitely.
720 */
721 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
722 ant->tx == ANTENNA_SW_DIVERSITY);
723
8318d78a 724 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 725 sel = antenna_sel_a;
726 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 727 } else {
728 sel = antenna_sel_bg;
729 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 730 }
731
2676c94d
MN		 732 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
733 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
734
0f829b1d 735 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
2676c94d 736
ddc827f9 737 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 738 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 739 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 740 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 741
0f829b1d 742 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
95ea3627 743
5122d898 744 if (rt2x00_rf(rt2x00dev, RF5226) || rt2x00_rf(rt2x00dev, RF5225))
addc81bd 745 rt73usb_config_antenna_5x(rt2x00dev, ant);
5122d898 746 else if (rt2x00_rf(rt2x00dev, RF2528) || rt2x00_rf(rt2x00dev, RF2527))
addc81bd 747 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 748}
749
e4ea1c40 750static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 751 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 752{
753 u16 eeprom;
754 short lna_gain = 0;
755
756 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
757 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
758 lna_gain += 14;
759
760 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
761 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
762 } else {
763 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
764 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
765 }
766
767 rt2x00dev->lna_gain = lna_gain;
768}
769
770static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
771 struct rf_channel *rf, const int txpower)
772{
773 u8 r3;
774 u8 r94;
775 u8 smart;
776
777 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
778 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
779
5122d898 780 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527));
e4ea1c40
ID		 781
782 rt73usb_bbp_read(rt2x00dev, 3, &r3);
783 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
784 rt73usb_bbp_write(rt2x00dev, 3, r3);
785
786 r94 = 6;
787 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
788 r94 += txpower - MAX_TXPOWER;
789 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
790 r94 += txpower;
791 rt73usb_bbp_write(rt2x00dev, 94, r94);
792
793 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
794 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
795 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
796 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
797
798 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
799 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
800 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
801 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
802
803 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
804 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
805 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
806 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
807
808 udelay(10);
809}
810
811static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
812 const int txpower)
813{
814 struct rf_channel rf;
815
816 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
817 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
818 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
819 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
820
821 rt73usb_config_channel(rt2x00dev, &rf, txpower);
822}
823
824static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
825 struct rt2x00lib_conf *libconf)
95ea3627
ID		 826{
827 u32 reg;
828
0f829b1d 829 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
e4ea1c40
ID		 830 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
831 libconf->conf->long_frame_max_tx_count);
832 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
833 libconf->conf->short_frame_max_tx_count);
0f829b1d 834 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
e4ea1c40 835}
95ea3627 836
7d7f19cc
ID		 837static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
838 struct rt2x00lib_conf *libconf)
839{
840 enum dev_state state =
841 (libconf->conf->flags & IEEE80211_CONF_PS) ?
842 STATE_SLEEP : STATE_AWAKE;
843 u32 reg;
844
845 if (state == STATE_SLEEP) {
846 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
847 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
6b347bff 848 rt2x00dev->beacon_int - 10);
7d7f19cc
ID		 849 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
850 libconf->conf->listen_interval - 1);
851 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
852
853 /* We must first disable autowake before it can be enabled */
854 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
855 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
856
857 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
858 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
859
860 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
861 USB_MODE_SLEEP, REGISTER_TIMEOUT);
862 } else {
863 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
864 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
865
866 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
867 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
868 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
869 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
870 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
871 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
872 }
873}
874
95ea3627 875static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 876 struct rt2x00lib_conf *libconf,
877 const unsigned int flags)
95ea3627 878{
ba2ab471
ID		 879 /* Always recalculate LNA gain before changing configuration */
880 rt73usb_config_lna_gain(rt2x00dev, libconf);
881
e4ea1c40 882 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 883 rt73usb_config_channel(rt2x00dev, &libconf->rf,
884 libconf->conf->power_level);
e4ea1c40
ID		 885 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
886 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 887 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 888 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
889 rt73usb_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 890 if (flags & IEEE80211_CONF_CHANGE_PS)
891 rt73usb_config_ps(rt2x00dev, libconf);
95ea3627
ID		 892}
893
95ea3627
ID		 894/*
895 * Link tuning
896 */
ebcf26da
ID		 897static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
898 struct link_qual *qual)
95ea3627
ID		 899{
900 u32 reg;
901
902 /*
903 * Update FCS error count from register.
904 */
0f829b1d 905 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 906 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 907
908 /*
909 * Update False CCA count from register.
910 */
0f829b1d 911 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 912 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 913}
914
5352ff65
ID		 915static inline void rt73usb_set_vgc(struct rt2x00_dev *rt2x00dev,
916 struct link_qual *qual, u8 vgc_level)
eb20b4e8 917{
5352ff65 918 if (qual->vgc_level != vgc_level) {
eb20b4e8 919 rt73usb_bbp_write(rt2x00dev, 17, vgc_level);
5352ff65
ID		 920 qual->vgc_level = vgc_level;
921 qual->vgc_level_reg = vgc_level;
eb20b4e8
ID		 922 }
923}
924
5352ff65
ID		 925static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
926 struct link_qual *qual)
95ea3627 927{
5352ff65 928 rt73usb_set_vgc(rt2x00dev, qual, 0x20);
95ea3627
ID		 929}
930
5352ff65
ID		 931static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev,
932 struct link_qual *qual, const u32 count)
95ea3627 933{
95ea3627
ID		 934 u8 up_bound;
935 u8 low_bound;
936
95ea3627
ID		 937 /*
938 * Determine r17 bounds.
939 */
8318d78a 940 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 941 low_bound = 0x28;
942 up_bound = 0x48;
943
944 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
945 low_bound += 0x10;
946 up_bound += 0x10;
947 }
948 } else {
5352ff65 949 if (qual->rssi > -82) {
95ea3627
ID		 950 low_bound = 0x1c;
951 up_bound = 0x40;
5352ff65 952 } else if (qual->rssi > -84) {
95ea3627
ID		 953 low_bound = 0x1c;
954 up_bound = 0x20;
955 } else {
956 low_bound = 0x1c;
957 up_bound = 0x1c;
958 }
959
960 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
961 low_bound += 0x14;
962 up_bound += 0x10;
963 }
964 }
965
6bb40dd1
ID		 966 /*
967 * If we are not associated, we should go straight to the
968 * dynamic CCA tuning.
969 */
970 if (!rt2x00dev->intf_associated)
971 goto dynamic_cca_tune;
972
95ea3627
ID		 973 /*
974 * Special big-R17 for very short distance
975 */
5352ff65
ID		 976 if (qual->rssi > -35) {
977 rt73usb_set_vgc(rt2x00dev, qual, 0x60);
95ea3627
ID		 978 return;
979 }
980
981 /*
982 * Special big-R17 for short distance
983 */
5352ff65
ID		 984 if (qual->rssi >= -58) {
985 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 986 return;
987 }
988
989 /*
990 * Special big-R17 for middle-short distance
991 */
5352ff65
ID		 992 if (qual->rssi >= -66) {
993 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x10);
95ea3627
ID		 994 return;
995 }
996
997 /*
998 * Special mid-R17 for middle distance
999 */
5352ff65
ID		 1000 if (qual->rssi >= -74) {
1001 rt73usb_set_vgc(rt2x00dev, qual, low_bound + 0x08);
95ea3627
ID		 1002 return;
1003 }
1004
1005 /*
1006 * Special case: Change up_bound based on the rssi.
1007 * Lower up_bound when rssi is weaker then -74 dBm.
1008 */
5352ff65 1009 up_bound -= 2 * (-74 - qual->rssi);
95ea3627
ID		 1010 if (low_bound > up_bound)
1011 up_bound = low_bound;
1012
5352ff65
ID		 1013 if (qual->vgc_level > up_bound) {
1014 rt73usb_set_vgc(rt2x00dev, qual, up_bound);
95ea3627
ID		 1015 return;
1016 }
1017
6bb40dd1
ID		 1018dynamic_cca_tune:
1019
95ea3627
ID		 1020 /*
1021 * r17 does not yet exceed upper limit, continue and base
1022 * the r17 tuning on the false CCA count.
1023 */
5352ff65
ID		 1024 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound))
1025 rt73usb_set_vgc(rt2x00dev, qual,
1026 min_t(u8, qual->vgc_level + 4, up_bound));
1027 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound))
1028 rt73usb_set_vgc(rt2x00dev, qual,
1029 max_t(u8, qual->vgc_level - 4, low_bound));
95ea3627
ID		 1030}
1031
1032/*
a7f3a06c 1033 * Firmware functions
95ea3627
ID		 1034 */
1035static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1036{
1037 return FIRMWARE_RT2571;
1038}
1039
0cbe0064
ID		 1040static int rt73usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1041 const u8 *data, const size_t len)
a7f3a06c 1042{
0cbe0064 1043 u16 fw_crc;
a7f3a06c
ID		 1044 u16 crc;
1045
1046 /*
0cbe0064
ID		 1047 * Only support 2kb firmware files.
1048 */
1049 if (len != 2048)
1050 return FW_BAD_LENGTH;
1051
1052 /*
a7f3a06c
ID		 1053 * The last 2 bytes in the firmware array are the crc checksum itself,
1054 * this means that we should never pass those 2 bytes to the crc
1055 * algorithm.
1056 */
0cbe0064
ID		 1057 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1058
1059 /*
1060 * Use the crc itu-t algorithm.
1061 */
a7f3a06c
ID		 1062 crc = crc_itu_t(0, data, len - 2);
1063 crc = crc_itu_t_byte(crc, 0);
1064 crc = crc_itu_t_byte(crc, 0);
1065
0cbe0064 1066 return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
a7f3a06c
ID		 1067}
1068
0cbe0064
ID		 1069static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1070 const u8 *data, const size_t len)
95ea3627
ID		 1071{
1072 unsigned int i;
1073 int status;
1074 u32 reg;
95ea3627
ID		 1075
1076 /*
1077 * Wait for stable hardware.
1078 */
1079 for (i = 0; i < 100; i++) {
0f829b1d 1080 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
95ea3627
ID		 1081 if (reg)
1082 break;
1083 msleep(1);
1084 }
1085
1086 if (!reg) {
1087 ERROR(rt2x00dev, "Unstable hardware.\n");
1088 return -EBUSY;
1089 }
1090
1091 /*
1092 * Write firmware to device.
95ea3627 1093 */
3e0c1abe
IM		 1094 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1095 USB_VENDOR_REQUEST_OUT,
1096 FIRMWARE_IMAGE_BASE,
1097 data, len,
1098 REGISTER_TIMEOUT32(len));
95ea3627
ID		 1099
1100 /*
1101 * Send firmware request to device to load firmware,
1102 * we need to specify a long timeout time.
1103 */
1104 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1105 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1106 REGISTER_TIMEOUT_FIRMWARE);
1107 if (status < 0) {
1108 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1109 return status;
1110 }
1111
95ea3627
ID		 1112 return 0;
1113}
1114
a7f3a06c
ID		 1115/*
1116 * Initialization functions.
1117 */
95ea3627
ID		 1118static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1119{
1120 u32 reg;
1121
0f829b1d 1122 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627
ID		 1123 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1124 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1125 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
0f829b1d 1126 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627 1127
0f829b1d 1128 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
95ea3627
ID		 1129 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1130 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1131 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1132 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1133 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1134 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1135 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1136 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
0f829b1d 1137 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
95ea3627
ID		 1138
1139 /*
1140 * CCK TXD BBP registers
1141 */
0f829b1d 1142 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
95ea3627
ID		 1143 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1144 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1145 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1146 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1147 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1148 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1149 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1150 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
0f829b1d 1151 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
95ea3627
ID		 1152
1153 /*
1154 * OFDM TXD BBP registers
1155 */
0f829b1d 1156 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
95ea3627
ID		 1157 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1158 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1159 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1160 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1161 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1162 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
0f829b1d 1163 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
95ea3627 1164
0f829b1d 1165 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
95ea3627
ID		 1166 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1167 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1168 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1169 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
0f829b1d 1170 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
95ea3627 1171
0f829b1d 1172 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
95ea3627
ID		 1173 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1174 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1175 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1176 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
0f829b1d 1177 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
95ea3627 1178
0f829b1d 1179 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1f909162
ID		 1180 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1181 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1182 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1183 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1184 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1185 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
0f829b1d 1186 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1f909162 1187
0f829b1d 1188 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
95ea3627 1189
0f829b1d 1190 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
95ea3627 1191 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
0f829b1d 1192 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
95ea3627 1193
0f829b1d 1194 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
95ea3627
ID		 1195
1196 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1197 return -EBUSY;
1198
0f829b1d 1199 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
95ea3627
ID		 1200
1201 /*
1202 * Invalidate all Shared Keys (SEC_CSR0),
1203 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1204 */
0f829b1d
ID		 1205 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1206 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1207 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
95ea3627
ID		 1208
1209 reg = 0x000023b0;
5122d898 1210 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527))
95ea3627 1211 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
0f829b1d 1212 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
95ea3627 1213
0f829b1d
ID		 1214 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1215 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1216 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
95ea3627 1217
0f829b1d 1218 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
95ea3627 1219 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
0f829b1d 1220 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 1221
6bb40dd1
ID		 1222 /*
1223 * Clear all beacons
1224 * For the Beacon base registers we only need to clear
1225 * the first byte since that byte contains the VALID and OWNER
1226 * bits which (when set to 0) will invalidate the entire beacon.
1227 */
0f829b1d
ID		 1228 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1229 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1230 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1231 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
6bb40dd1 1232
95ea3627
ID		 1233 /*
1234 * We must clear the error counters.
1235 * These registers are cleared on read,
1236 * so we may pass a useless variable to store the value.
1237 */
0f829b1d
ID		 1238 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1239 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1240 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
95ea3627
ID		 1241
1242 /*
1243 * Reset MAC and BBP registers.
1244 */
0f829b1d 1245 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1246 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1247 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
0f829b1d 1248 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1249
0f829b1d 1250 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627
ID		 1251 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1252 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
0f829b1d 1253 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627 1254
0f829b1d 1255 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
95ea3627 1256 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
0f829b1d 1257 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
95ea3627
ID		 1258
1259 return 0;
1260}
1261
2b08da3f 1262static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1263{
1264 unsigned int i;
95ea3627
ID		 1265 u8 value;
1266
1267 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1268 rt73usb_bbp_read(rt2x00dev, 0, &value);
1269 if ((value != 0xff) && (value != 0x00))
2b08da3f 1270 return 0;
95ea3627
ID		 1271 udelay(REGISTER_BUSY_DELAY);
1272 }
1273
1274 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1275 return -EACCES;
2b08da3f
ID		 1276}
1277
1278static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1279{
1280 unsigned int i;
1281 u16 eeprom;
1282 u8 reg_id;
1283 u8 value;
1284
1285 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1286 return -EACCES;
95ea3627 1287
95ea3627
ID		 1288 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1289 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1290 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1291 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1292 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1293 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1294 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1295 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1296 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1297 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1298 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1299 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1300 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1301 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1302 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1303 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1304 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1305 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1306 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1307 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1308 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1309 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1310 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1311 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1312 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1313
95ea3627
ID		 1314 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1315 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1316
1317 if (eeprom != 0xffff && eeprom != 0x0000) {
1318 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1319 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1320 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1321 }
1322 }
95ea3627
ID		 1323
1324 return 0;
1325}
1326
1327/*
1328 * Device state switch handlers.
1329 */
1330static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1331 enum dev_state state)
1332{
1333 u32 reg;
1334
0f829b1d 1335 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
95ea3627 1336 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1337 (state == STATE_RADIO_RX_OFF) ||
1338 (state == STATE_RADIO_RX_OFF_LINK));
0f829b1d 1339 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
95ea3627
ID		 1340}
1341
1342static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1343{
1344 /*
1345 * Initialize all registers.
1346 */
2b08da3f
ID		 1347 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1348 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1349 return -EIO;
95ea3627 1350
95ea3627
ID		 1351 return 0;
1352}
1353
1354static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1355{
0f829b1d 1356 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
95ea3627
ID		 1357
1358 /*
1359 * Disable synchronisation.
1360 */
0f829b1d 1361 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
95ea3627
ID		 1362
1363 rt2x00usb_disable_radio(rt2x00dev);
1364}
1365
1366static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1367{
1368 u32 reg;
1369 unsigned int i;
1370 char put_to_sleep;
95ea3627
ID		 1371
1372 put_to_sleep = (state != STATE_AWAKE);
1373
0f829b1d 1374 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
95ea3627
ID		 1375 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1376 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
0f829b1d 1377 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
95ea3627
ID		 1378
1379 /*
1380 * Device is not guaranteed to be in the requested state yet.
1381 * We must wait until the register indicates that the
1382 * device has entered the correct state.
1383 */
1384 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
0f829b1d 1385 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1386 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1387 if (state == !put_to_sleep)
95ea3627
ID		 1388 return 0;
1389 msleep(10);
1390 }
1391
95ea3627
ID		 1392 return -EBUSY;
1393}
1394
1395static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1396 enum dev_state state)
1397{
1398 int retval = 0;
1399
1400 switch (state) {
1401 case STATE_RADIO_ON:
1402 retval = rt73usb_enable_radio(rt2x00dev);
1403 break;
1404 case STATE_RADIO_OFF:
1405 rt73usb_disable_radio(rt2x00dev);
1406 break;
1407 case STATE_RADIO_RX_ON:
61667d8d 1408 case STATE_RADIO_RX_ON_LINK:
95ea3627 1409 case STATE_RADIO_RX_OFF:
61667d8d 1410 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1411 rt73usb_toggle_rx(rt2x00dev, state);
1412 break;
1413 case STATE_RADIO_IRQ_ON:
1414 case STATE_RADIO_IRQ_OFF:
1415 /* No support, but no error either */
95ea3627
ID		 1416 break;
1417 case STATE_DEEP_SLEEP:
1418 case STATE_SLEEP:
1419 case STATE_STANDBY:
1420 case STATE_AWAKE:
1421 retval = rt73usb_set_state(rt2x00dev, state);
1422 break;
1423 default:
1424 retval = -ENOTSUPP;
1425 break;
1426 }
1427
2b08da3f
ID		 1428 if (unlikely(retval))
1429 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1430 state, retval);
1431
95ea3627
ID		 1432 return retval;
1433}
1434
1435/*
1436 * TX descriptor initialization
1437 */
1438static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
906c110f
ID		 1439 struct sk_buff *skb,
1440 struct txentry_desc *txdesc)
95ea3627 1441{
181d6902 1442 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1443 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1444 u32 word;
1445
1446 /*
1447 * Start writing the descriptor words.
1448 */
1449 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1450 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1451 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1452 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1453 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
906c110f 1454 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1455 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1456 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1457 rt2x00_desc_write(txd, 1, word);
1458
1459 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1460 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1461 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1462 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1463 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1464 rt2x00_desc_write(txd, 2, word);
1465
906c110f 1466 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1ce9cdac
ID		 1467 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1468 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
906c110f
ID		 1469 }
1470
95ea3627
ID		 1471 rt2x00_desc_read(txd, 5, &word);
1472 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1473 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1474 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1475 rt2x00_desc_write(txd, 5, word);
1476
1477 rt2x00_desc_read(txd, 0, &word);
1478 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1479 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1480 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1481 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1482 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1483 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1484 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1485 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1486 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1487 rt2x00_set_field32(&word, TXD_W0_OFDM,
076f9582 1488 (txdesc->rate_mode == RATE_MODE_OFDM));
181d6902 1489 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1490 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1491 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
906c110f
ID		 1492 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1493 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1494 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1495 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1496 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1abc3656 1497 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1498 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1499 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
906c110f 1500 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1501 rt2x00_desc_write(txd, 0, word);
1502}
1503
bd88a781
ID		 1504/*
1505 * TX data initialization
1506 */
1507static void rt73usb_write_beacon(struct queue_entry *entry)
1508{
1509 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1510 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1511 unsigned int beacon_base;
1512 u32 reg;
1513
1514 /*
1515 * Add the descriptor in front of the skb.
1516 */
1517 skb_push(entry->skb, entry->queue->desc_size);
1518 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1519 skbdesc->desc = entry->skb->data;
1520
1521 /*
1522 * Disable beaconing while we are reloading the beacon data,
1523 * otherwise we might be sending out invalid data.
1524 */
0f829b1d 1525 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
bd88a781 1526 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
0f829b1d 1527 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
bd88a781
ID		 1528
1529 /*
1530 * Write entire beacon with descriptor to register.
1531 */
1532 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3e0c1abe
IM		 1533 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1534 USB_VENDOR_REQUEST_OUT, beacon_base,
1535 entry->skb->data, entry->skb->len,
1536 REGISTER_TIMEOUT32(entry->skb->len));
bd88a781
ID		 1537
1538 /*
1539 * Clean up the beacon skb.
1540 */
1541 dev_kfree_skb(entry->skb);
1542 entry->skb = NULL;
1543}
1544
f1ca2167 1545static int rt73usb_get_tx_data_len(struct queue_entry *entry)
dd9fa2d2
ID		 1546{
1547 int length;
1548
1549 /*
1550 * The length _must_ be a multiple of 4,
1551 * but it must _not_ be a multiple of the USB packet size.
1552 */
f1ca2167
ID		 1553 length = roundup(entry->skb->len, 4);
1554 length += (4 * !(length % entry->queue->usb_maxpacket));
dd9fa2d2
ID		 1555
1556 return length;
1557}
1558
95ea3627 1559static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1560 const enum data_queue_qid queue)
95ea3627
ID		 1561{
1562 u32 reg;
1563
f019d514
ID		 1564 if (queue != QID_BEACON) {
1565 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1566 return;
f019d514 1567 }
95ea3627
ID		 1568
1569 /*
1570 * For Wi-Fi faily generated beacons between participating stations.
1571 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1572 */
0f829b1d 1573 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
95ea3627 1574
0f829b1d 1575 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
95ea3627 1576 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1577 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1578 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627 1579 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
0f829b1d 1580 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
95ea3627
ID		 1581 }
1582}
1583
1584/*
1585 * RX control handlers
1586 */
1587static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1588{
ba2ab471 1589 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1590 u8 lna;
1591
1592 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1593 switch (lna) {
1594 case 3:
ba2ab471 1595 offset += 90;
95ea3627
ID		 1596 break;
1597 case 2:
ba2ab471 1598 offset += 74;
95ea3627
ID		 1599 break;
1600 case 1:
ba2ab471 1601 offset += 64;
95ea3627
ID		 1602 break;
1603 default:
1604 return 0;
1605 }
1606
8318d78a 1607 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1608 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1609 if (lna == 3 || lna == 2)
1610 offset += 10;
1611 } else {
1612 if (lna == 3)
1613 offset += 6;
1614 else if (lna == 2)
1615 offset += 8;
1616 }
95ea3627
ID		 1617 }
1618
1619 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1620}
1621
181d6902 1622static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1623 struct rxdone_entry_desc *rxdesc)
95ea3627 1624{
906c110f 1625 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1626 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1627 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1628 u32 word0;
1629 u32 word1;
1630
f855c10b 1631 /*
a26cbc65
GW		 1632 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1633 * frame data in rt2x00usb.
f855c10b 1634 */
a26cbc65 1635 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1636 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1637
1638 /*
70a96109 1639 * It is now safe to read the descriptor on all architectures.
f855c10b 1640 */
95ea3627
ID		 1641 rt2x00_desc_read(rxd, 0, &word0);
1642 rt2x00_desc_read(rxd, 1, &word1);
1643
4150c572 1644 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1645 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1646
906c110f
ID		 1647 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1648 rxdesc->cipher =
1649 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1650 rxdesc->cipher_status =
1651 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1652 }
1653
1654 if (rxdesc->cipher != CIPHER_NONE) {
1ce9cdac
ID		 1655 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1656 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
74415edb
ID		 1657 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1658
906c110f 1659 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
74415edb 1660 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
906c110f
ID		 1661
1662 /*
1663 * Hardware has stripped IV/EIV data from 802.11 frame during
1664 * decryption. It has provided the data seperately but rt2x00lib
1665 * should decide if it should be reinserted.
1666 */
1667 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1668
1669 /*
1670 * FIXME: Legacy driver indicates that the frame does
1671 * contain the Michael Mic. Unfortunately, in rt2x00
1672 * the MIC seems to be missing completely...
1673 */
1674 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1675
1676 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1677 rxdesc->flags |= RX_FLAG_DECRYPTED;
1678 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1679 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1680 }
1681
95ea3627
ID		 1682 /*
1683 * Obtain the status about this packet.
89993890
ID		 1684 * When frame was received with an OFDM bitrate,
1685 * the signal is the PLCP value. If it was received with
1686 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1687 */
181d6902 1688 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1689 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1690 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1691
19d30e02
ID		 1692 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1693 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1694 else
1695 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1696 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1697 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1698
2ae23854 1699 /*
70a96109 1700 * Set skb pointers, and update frame information.
2ae23854 1701 */
70a96109 1702 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1703 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1704}
1705
1706/*
1707 * Device probe functions.
1708 */
1709static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1710{
1711 u16 word;
1712 u8 *mac;
1713 s8 value;
1714
1715 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1716
1717 /*
1718 * Start validation of the data that has been read.
1719 */
1720 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1721 if (!is_valid_ether_addr(mac)) {
1722 random_ether_addr(mac);
e174961c 1723 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1724 }
1725
1726 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1727 if (word == 0xffff) {
1728 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1729 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1730 ANTENNA_B);
1731 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1732 ANTENNA_B);
95ea3627
ID		 1733 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1734 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1735 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1736 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1737 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1738 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1739 }
1740
1741 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1742 if (word == 0xffff) {
1743 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1744 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1745 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1746 }
1747
1748 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1749 if (word == 0xffff) {
1750 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1751 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1752 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1753 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1754 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1755 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1756 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1757 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1758 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1759 LED_MODE_DEFAULT);
1760 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1761 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1762 }
1763
1764 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1765 if (word == 0xffff) {
1766 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1767 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1768 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1769 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1770 }
1771
1772 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1773 if (word == 0xffff) {
1774 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1775 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1776 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1777 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1778 } else {
1779 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1780 if (value < -10 || value > 10)
1781 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1782 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1783 if (value < -10 || value > 10)
1784 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1785 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1786 }
1787
1788 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1789 if (word == 0xffff) {
1790 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1791 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1792 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1793 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1794 } else {
1795 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1796 if (value < -10 || value > 10)
1797 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1798 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1799 if (value < -10 || value > 10)
1800 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1801 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1802 }
1803
1804 return 0;
1805}
1806
1807static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1808{
1809 u32 reg;
1810 u16 value;
1811 u16 eeprom;
1812
1813 /*
1814 * Read EEPROM word for configuration.
1815 */
1816 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1817
1818 /*
1819 * Identify RF chipset.
1820 */
1821 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
0f829b1d 1822 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
49e721ec
GW		 1823 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
1824 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
95ea3627 1825
49e721ec 1826 if (!rt2x00_rt(rt2x00dev, RT2573) || (rt2x00_rev(rt2x00dev) == 0)) {
95ea3627
ID		 1827 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1828 return -ENODEV;
1829 }
1830
5122d898
GW		 1831 if (!rt2x00_rf(rt2x00dev, RF5226) &&
1832 !rt2x00_rf(rt2x00dev, RF2528) &&
1833 !rt2x00_rf(rt2x00dev, RF5225) &&
1834 !rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 1835 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1836 return -ENODEV;
1837 }
1838
1839 /*
1840 * Identify default antenna configuration.
1841 */
addc81bd 1842 rt2x00dev->default_ant.tx =
95ea3627 1843 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1844 rt2x00dev->default_ant.rx =
95ea3627
ID		 1845 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1846
1847 /*
1848 * Read the Frame type.
1849 */
1850 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1851 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1852
7396faf4
ID		 1853 /*
1854 * Detect if this device has an hardware controlled radio.
1855 */
7396faf4
ID		 1856 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1857 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
7396faf4 1858
95ea3627
ID		 1859 /*
1860 * Read frequency offset.
1861 */
1862 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1863 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1864
1865 /*
1866 * Read external LNA informations.
1867 */
1868 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1869
1870 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1871 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1872 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1873 }
1874
1875 /*
1876 * Store led settings, for correct led behaviour.
1877 */
771fd565 1878#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1879 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1880
475433be
ID		 1881 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1882 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1883 if (value == LED_MODE_SIGNAL_STRENGTH)
1884 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1885 LED_TYPE_QUALITY);
a9450b70
ID		 1886
1887 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1888 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1889 rt2x00_get_field16(eeprom,
1890 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1891 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1892 rt2x00_get_field16(eeprom,
1893 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1894 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1895 rt2x00_get_field16(eeprom,
1896 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1897 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1898 rt2x00_get_field16(eeprom,
1899 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1900 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1901 rt2x00_get_field16(eeprom,
1902 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1903 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1904 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1905 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1906 rt2x00_get_field16(eeprom,
1907 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1908 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1909 rt2x00_get_field16(eeprom,
1910 EEPROM_LED_POLARITY_RDY_A));
771fd565 1911#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1912
1913 return 0;
1914}
1915
1916/*
1917 * RF value list for RF2528
1918 * Supports: 2.4 GHz
1919 */
1920static const struct rf_channel rf_vals_bg_2528[] = {
1921 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1922 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1923 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1924 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1925 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1926 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1927 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1928 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1929 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1930 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1931 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1932 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1933 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1934 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1935};
1936
1937/*
1938 * RF value list for RF5226
1939 * Supports: 2.4 GHz & 5.2 GHz
1940 */
1941static const struct rf_channel rf_vals_5226[] = {
1942 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1943 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1944 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1945 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1946 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1947 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1948 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1949 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1950 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1951 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1952 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1953 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1954 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1955 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1956
1957 /* 802.11 UNI / HyperLan 2 */
1958 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1959 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1960 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1961 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1962 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1963 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1964 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1965 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1966
1967 /* 802.11 HyperLan 2 */
1968 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1969 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1970 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1971 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1972 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1973 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1974 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1975 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1976 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1977 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1978
1979 /* 802.11 UNII */
1980 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1981 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1982 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1983 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1984 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1985 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1986
1987 /* MMAC(Japan)J52 ch 34,38,42,46 */
1988 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1989 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1990 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1991 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1992};
1993
1994/*
1995 * RF value list for RF5225 & RF2527
1996 * Supports: 2.4 GHz & 5.2 GHz
1997 */
1998static const struct rf_channel rf_vals_5225_2527[] = {
1999 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2000 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2001 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2002 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2003 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2004 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2005 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2006 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2007 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2008 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2009 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2010 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2011 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2012 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2013
2014 /* 802.11 UNI / HyperLan 2 */
2015 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2016 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2017 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2018 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2019 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2020 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2021 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2022 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2023
2024 /* 802.11 HyperLan 2 */
2025 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2026 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2027 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2028 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2029 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2030 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2031 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2032 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2033 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2034 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2035
2036 /* 802.11 UNII */
2037 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2038 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2039 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2040 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2041 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2042 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2043
2044 /* MMAC(Japan)J52 ch 34,38,42,46 */
2045 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2046 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2047 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2048 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2049};
2050
2051
8c5e7a5f 2052static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2053{
2054 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2055 struct channel_info *info;
2056 char *tx_power;
95ea3627
ID		 2057 unsigned int i;
2058
2059 /*
2060 * Initialize all hw fields.
2061 */
2062 rt2x00dev->hw->flags =
566bfe5a 2063 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 2064 IEEE80211_HW_SIGNAL_DBM |
2065 IEEE80211_HW_SUPPORTS_PS |
2066 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 2067
14a3bf89 2068 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2069 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2070 rt2x00_eeprom_addr(rt2x00dev,
2071 EEPROM_MAC_ADDR_0));
2072
95ea3627
ID		 2073 /*
2074 * Initialize hw_mode information.
2075 */
31562e80
ID		 2076 spec->supported_bands = SUPPORT_BAND_2GHZ;
2077 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627 2078
5122d898 2079 if (rt2x00_rf(rt2x00dev, RF2528)) {
95ea3627
ID		 2080 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2081 spec->channels = rf_vals_bg_2528;
5122d898 2082 } else if (rt2x00_rf(rt2x00dev, RF5226)) {
31562e80 2083 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2084 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2085 spec->channels = rf_vals_5226;
5122d898 2086 } else if (rt2x00_rf(rt2x00dev, RF2527)) {
95ea3627
ID		 2087 spec->num_channels = 14;
2088 spec->channels = rf_vals_5225_2527;
5122d898 2089 } else if (rt2x00_rf(rt2x00dev, RF5225)) {
31562e80 2090 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2091 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2092 spec->channels = rf_vals_5225_2527;
2093 }
2094
8c5e7a5f
ID		 2095 /*
2096 * Create channel information array
2097 */
2098 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2099 if (!info)
2100 return -ENOMEM;
95ea3627 2101
8c5e7a5f
ID		 2102 spec->channels_info = info;
2103
2104 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2105 for (i = 0; i < 14; i++)
2106 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2107
2108 if (spec->num_channels > 14) {
2109 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2110 for (i = 14; i < spec->num_channels; i++)
2111 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2112 }
8c5e7a5f
ID		 2113
2114 return 0;
95ea3627
ID		 2115}
2116
2117static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2118{
2119 int retval;
2120
2121 /*
2122 * Allocate eeprom data.
2123 */
2124 retval = rt73usb_validate_eeprom(rt2x00dev);
2125 if (retval)
2126 return retval;
2127
2128 retval = rt73usb_init_eeprom(rt2x00dev);
2129 if (retval)
2130 return retval;
2131
2132 /*
2133 * Initialize hw specifications.
2134 */
8c5e7a5f
ID		 2135 retval = rt73usb_probe_hw_mode(rt2x00dev);
2136 if (retval)
2137 return retval;
95ea3627 2138
1afcfd54
IP		 2139 /*
2140 * This device has multiple filters for control frames,
2141 * but has no a separate filter for PS Poll frames.
2142 */
2143 __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2144
95ea3627 2145 /*
9404ef34 2146 * This device requires firmware.
95ea3627 2147 */
066cb637 2148 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
008c4482
ID		 2149 if (!modparam_nohwcrypt)
2150 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2151
2152 /*
2153 * Set the rssi offset.
2154 */
2155 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2156
2157 return 0;
2158}
2159
2160/*
2161 * IEEE80211 stack callback functions.
2162 */
2af0a570
ID		 2163static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2164 const struct ieee80211_tx_queue_params *params)
2165{
2166 struct rt2x00_dev *rt2x00dev = hw->priv;
2167 struct data_queue *queue;
2168 struct rt2x00_field32 field;
2169 int retval;
2170 u32 reg;
5e790023 2171 u32 offset;
2af0a570
ID		 2172
2173 /*
2174 * First pass the configuration through rt2x00lib, that will
2175 * update the queue settings and validate the input. After that
2176 * we are free to update the registers based on the value
2177 * in the queue parameter.
2178 */
2179 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2180 if (retval)
2181 return retval;
2182
5e790023
ID		 2183 /*
2184 * We only need to perform additional register initialization
2185 * for WMM queues/
2186 */
2187 if (queue_idx >= 4)
2188 return 0;
2189
2af0a570
ID		 2190 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2191
2192 /* Update WMM TXOP register */
5e790023
ID		 2193 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
2194 field.bit_offset = (queue_idx & 1) * 16;
2195 field.bit_mask = 0xffff << field.bit_offset;
2196
2197 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2198 rt2x00_set_field32(&reg, field, queue->txop);
2199 rt2x00usb_register_write(rt2x00dev, offset, reg);
2af0a570
ID		 2200
2201 /* Update WMM registers */
2202 field.bit_offset = queue_idx * 4;
2203 field.bit_mask = 0xf << field.bit_offset;
2204
0f829b1d 2205 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2af0a570 2206 rt2x00_set_field32(&reg, field, queue->aifs);
0f829b1d 2207 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2af0a570 2208
0f829b1d 2209 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2af0a570 2210 rt2x00_set_field32(&reg, field, queue->cw_min);
0f829b1d 2211 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2af0a570 2212
0f829b1d 2213 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2af0a570 2214 rt2x00_set_field32(&reg, field, queue->cw_max);
0f829b1d 2215 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2af0a570
ID		 2216
2217 return 0;
2218}
2219
95ea3627
ID		 2220static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2221{
2222 struct rt2x00_dev *rt2x00dev = hw->priv;
2223 u64 tsf;
2224 u32 reg;
2225
0f829b1d 2226 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
95ea3627 2227 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
0f829b1d 2228 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
95ea3627
ID		 2229 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2230
2231 return tsf;
2232}
95ea3627 2233
95ea3627
ID		 2234static const struct ieee80211_ops rt73usb_mac80211_ops = {
2235 .tx = rt2x00mac_tx,
4150c572
JB		 2236 .start = rt2x00mac_start,
2237 .stop = rt2x00mac_stop,
95ea3627
ID		 2238 .add_interface = rt2x00mac_add_interface,
2239 .remove_interface = rt2x00mac_remove_interface,
2240 .config = rt2x00mac_config,
3a643d24 2241 .configure_filter = rt2x00mac_configure_filter,
930c06f2 2242 .set_tim = rt2x00mac_set_tim,
906c110f 2243 .set_key = rt2x00mac_set_key,
95ea3627 2244 .get_stats = rt2x00mac_get_stats,
471b3efd 2245 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2246 .conf_tx = rt73usb_conf_tx,
95ea3627 2247 .get_tsf = rt73usb_get_tsf,
e47a5cdd 2248 .rfkill_poll = rt2x00mac_rfkill_poll,
95ea3627
ID		 2249};
2250
2251static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2252 .probe_hw = rt73usb_probe_hw,
2253 .get_firmware_name = rt73usb_get_firmware_name,
0cbe0064 2254 .check_firmware = rt73usb_check_firmware,
95ea3627
ID		 2255 .load_firmware = rt73usb_load_firmware,
2256 .initialize = rt2x00usb_initialize,
2257 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2258 .clear_entry = rt2x00usb_clear_entry,
95ea3627 2259 .set_device_state = rt73usb_set_device_state,
7396faf4 2260 .rfkill_poll = rt73usb_rfkill_poll,
95ea3627
ID		 2261 .link_stats = rt73usb_link_stats,
2262 .reset_tuner = rt73usb_reset_tuner,
2263 .link_tuner = rt73usb_link_tuner,
2264 .write_tx_desc = rt73usb_write_tx_desc,
2265 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2266 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2267 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627 2268 .kick_tx_queue = rt73usb_kick_tx_queue,
a2c9b652 2269 .kill_tx_queue = rt2x00usb_kill_tx_queue,
95ea3627 2270 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2271 .config_shared_key = rt73usb_config_shared_key,
2272 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2273 .config_filter = rt73usb_config_filter,
6bb40dd1 2274 .config_intf = rt73usb_config_intf,
72810379 2275 .config_erp = rt73usb_config_erp,
e4ea1c40 2276 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2277 .config = rt73usb_config,
2278};
2279
181d6902
ID		 2280static const struct data_queue_desc rt73usb_queue_rx = {
2281 .entry_num = RX_ENTRIES,
2282 .data_size = DATA_FRAME_SIZE,
2283 .desc_size = RXD_DESC_SIZE,
b8be63ff 2284 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2285};
2286
2287static const struct data_queue_desc rt73usb_queue_tx = {
2288 .entry_num = TX_ENTRIES,
2289 .data_size = DATA_FRAME_SIZE,
2290 .desc_size = TXD_DESC_SIZE,
b8be63ff 2291 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2292};
2293
2294static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2295 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2296 .data_size = MGMT_FRAME_SIZE,
2297 .desc_size = TXINFO_SIZE,
b8be63ff 2298 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2299};
2300
95ea3627 2301static const struct rt2x00_ops rt73usb_ops = {
04d0362e
GW		 2302 .name = KBUILD_MODNAME,
2303 .max_sta_intf = 1,
2304 .max_ap_intf = 4,
2305 .eeprom_size = EEPROM_SIZE,
2306 .rf_size = RF_SIZE,
2307 .tx_queues = NUM_TX_QUEUES,
e6218cc4 2308 .extra_tx_headroom = TXD_DESC_SIZE,
04d0362e
GW		 2309 .rx = &rt73usb_queue_rx,
2310 .tx = &rt73usb_queue_tx,
2311 .bcn = &rt73usb_queue_bcn,
2312 .lib = &rt73usb_rt2x00_ops,
2313 .hw = &rt73usb_mac80211_ops,
95ea3627 2314#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 2315 .debugfs = &rt73usb_rt2x00debug,
95ea3627
ID		 2316#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2317};
2318
2319/*
2320 * rt73usb module information.
2321 */
2322static struct usb_device_id rt73usb_device_table[] = {
2323 /* AboCom */
ef4bb70d
XVP		 2324 { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) },
2325 { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2326 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2327 { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) },
2328 { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) },
2329 /* AL */
2330 { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2331 /* Amigo */
2332 { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
2333 { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2334 /* AMIT */
2335 { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2336 /* Askey */
2337 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2338 /* ASUS */
2339 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2340 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2341 /* Belkin */
2342 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2343 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2344 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2345 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2346 /* Billionton */
2347 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2348 { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2349 /* Buffalo */
964d6ad9 2350 { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) },
050e8a47 2351 { USB_DEVICE(0x0411, 0x00d9), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2352 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
6aabd4c4
ID		 2353 { USB_DEVICE(0x0411, 0x0116), USB_DEVICE_DATA(&rt73usb_ops) },
2354 { USB_DEVICE(0x0411, 0x0119), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2355 /* CNet */
2356 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2357 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2358 /* Conceptronic */
2359 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2360 /* Corega */
2361 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2362 /* D-Link */
2363 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2364 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2365 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2366 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2367 /* Edimax */
2368 { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
2369 { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) },
2370 /* EnGenius */
2371 { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2372 /* Gemtek */
2373 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2374 /* Gigabyte */
2375 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2376 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2377 /* Huawei-3Com */
2378 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2379 /* Hercules */
78bd6bbf 2380 { USB_DEVICE(0x06f8, 0xe002), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2381 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2382 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2383 /* Linksys */
2384 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2385 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
3be36ae2 2386 { USB_DEVICE(0x13b1, 0x0028), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2387 /* MSI */
22720645 2388 { USB_DEVICE(0x0db0, 0x4600), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2389 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2390 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2391 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2392 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
22720645
XVP		 2393 /* Ovislink */
2394 { USB_DEVICE(0x1b75, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2395 /* Ralink */
144d9ad9 2396 { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2397 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2398 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2399 /* Qcom */
2400 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2401 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2402 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2403 /* Samsung */
2404 { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2405 /* Senao */
2406 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2407 /* Sitecom */
ef4bb70d
XVP		 2408 { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) },
2409 { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) },
2410 { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627 2411 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d 2412 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2413 /* Surecom */
2414 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
14344b81
ID		 2415 /* Tilgin */
2416 { USB_DEVICE(0x6933, 0x5001), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2417 /* Philips */
2418 { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2419 /* Planex */
2420 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2421 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
22720645
XVP		 2422 /* WideTell */
2423 { USB_DEVICE(0x7167, 0x3840), USB_DEVICE_DATA(&rt73usb_ops) },
ef4bb70d
XVP		 2424 /* Zcom */
2425 { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) },
144d9ad9
ID		 2426 /* ZyXEL */
2427 { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2428 { 0, }
2429};
2430
2431MODULE_AUTHOR(DRV_PROJECT);
2432MODULE_VERSION(DRV_VERSION);
2433MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2434MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2435MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2436MODULE_FIRMWARE(FIRMWARE_RT2571);
2437MODULE_LICENSE("GPL");
2438
2439static struct usb_driver rt73usb_driver = {
2360157c 2440 .name = KBUILD_MODNAME,
95ea3627
ID		 2441 .id_table = rt73usb_device_table,
2442 .probe = rt2x00usb_probe,
2443 .disconnect = rt2x00usb_disconnect,
2444 .suspend = rt2x00usb_suspend,
2445 .resume = rt2x00usb_resume,
2446};
2447
2448static int __init rt73usb_init(void)
2449{
2450 return usb_register(&rt73usb_driver);
2451}
2452
2453static void __exit rt73usb_exit(void)
2454{
2455 usb_deregister(&rt73usb_driver);
2456}
2457
2458module_init(rt73usb_init);
2459module_exit(rt73usb_exit);
Linux 6.x block layer and io_uring tree(s)