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ath5k: name pci driver "ath5k" too
[linux-block.git] / drivers / net / wireless / rt2x00 / rt73usb.c
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95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt73usb
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
25 */
26
a7f3a06c 27#include <linux/crc-itu-t.h>
95ea3627
ID		 28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt73usb.h"
38
008c4482
ID		 39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 0;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
95ea3627
ID		 46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt73usb_register_read and rt73usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
8ff48a8b 58 * The _lock versions must be used if you already hold the csr_mutex
95ea3627 59 */
0e14f6d3 60static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 61 const unsigned int offset, u32 *value)
62{
63 __le32 reg;
64 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
65 USB_VENDOR_REQUEST_IN, offset,
66 &reg, sizeof(u32), REGISTER_TIMEOUT);
67 *value = le32_to_cpu(reg);
68}
69
3d82346c
AB		 70static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
71 const unsigned int offset, u32 *value)
72{
73 __le32 reg;
74 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
75 USB_VENDOR_REQUEST_IN, offset,
76 &reg, sizeof(u32), REGISTER_TIMEOUT);
77 *value = le32_to_cpu(reg);
78}
79
0e14f6d3 80static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 81 const unsigned int offset,
82 void *value, const u32 length)
83{
95ea3627
ID		 84 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
85 USB_VENDOR_REQUEST_IN, offset,
bd394a74
ID		 86 value, length,
87 REGISTER_TIMEOUT32(length));
95ea3627
ID		 88}
89
0e14f6d3 90static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 91 const unsigned int offset, u32 value)
92{
93 __le32 reg = cpu_to_le32(value);
94 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
95 USB_VENDOR_REQUEST_OUT, offset,
96 &reg, sizeof(u32), REGISTER_TIMEOUT);
97}
98
3d82346c
AB		 99static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
100 const unsigned int offset, u32 value)
101{
102 __le32 reg = cpu_to_le32(value);
103 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
104 USB_VENDOR_REQUEST_OUT, offset,
105 &reg, sizeof(u32), REGISTER_TIMEOUT);
106}
107
0e14f6d3 108static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 109 const unsigned int offset,
110 void *value, const u32 length)
111{
95ea3627
ID		 112 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
113 USB_VENDOR_REQUEST_OUT, offset,
bd394a74
ID		 114 value, length,
115 REGISTER_TIMEOUT32(length));
95ea3627
ID		 116}
117
0e14f6d3 118static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 119{
120 u32 reg;
121 unsigned int i;
122
123 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 124 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
95ea3627
ID		 125 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
126 break;
127 udelay(REGISTER_BUSY_DELAY);
128 }
129
130 return reg;
131}
132
0e14f6d3 133static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 134 const unsigned int word, const u8 value)
135{
136 u32 reg;
137
8ff48a8b 138 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 139
95ea3627
ID		 140 /*
141 * Wait until the BBP becomes ready.
142 */
143 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 144 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
145 goto exit_fail;
95ea3627
ID		 146
147 /*
148 * Write the data into the BBP.
149 */
150 reg = 0;
151 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
152 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
153 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
154 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
155
3d82346c 156 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
8ff48a8b 157 mutex_unlock(&rt2x00dev->csr_mutex);
99ade259
ID		 158
159 return;
160
161exit_fail:
8ff48a8b 162 mutex_unlock(&rt2x00dev->csr_mutex);
99ade259
ID		 163
164 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
95ea3627
ID		 165}
166
0e14f6d3 167static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 168 const unsigned int word, u8 *value)
169{
170 u32 reg;
171
8ff48a8b 172 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 173
95ea3627
ID		 174 /*
175 * Wait until the BBP becomes ready.
176 */
177 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 178 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
179 goto exit_fail;
95ea3627
ID		 180
181 /*
182 * Write the request into the BBP.
183 */
184 reg = 0;
185 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
186 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
187 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
188
3d82346c 189 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
95ea3627
ID		 190
191 /*
192 * Wait until the BBP becomes ready.
193 */
194 reg = rt73usb_bbp_check(rt2x00dev);
99ade259
ID		 195 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
196 goto exit_fail;
95ea3627
ID		 197
198 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
8ff48a8b 199 mutex_unlock(&rt2x00dev->csr_mutex);
99ade259
ID		 200
201 return;
202
203exit_fail:
8ff48a8b 204 mutex_unlock(&rt2x00dev->csr_mutex);
99ade259
ID		 205
206 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
207 *value = 0xff;
95ea3627
ID		 208}
209
0e14f6d3 210static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 211 const unsigned int word, const u32 value)
212{
213 u32 reg;
214 unsigned int i;
215
216 if (!word)
217 return;
218
8ff48a8b 219 mutex_lock(&rt2x00dev->csr_mutex);
3d82346c 220
95ea3627 221 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3d82346c 222 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
95ea3627
ID		 223 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
224 goto rf_write;
225 udelay(REGISTER_BUSY_DELAY);
226 }
227
8ff48a8b 228 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 229 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
230 return;
231
232rf_write:
233 reg = 0;
234 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
235
4f5af6eb
ID		 236 /*
237 * RF5225 and RF2527 contain 21 bits per RF register value,
238 * all others contain 20 bits.
239 */
240 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
ddc827f9
ID		 241 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
242 rt2x00_rf(&rt2x00dev->chip, RF2527)));
95ea3627
ID		 243 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
244 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
245
3d82346c 246 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
95ea3627 247 rt2x00_rf_write(rt2x00dev, word, value);
8ff48a8b
ID		 248
249 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 250}
251
252#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 253static const struct rt2x00debug rt73usb_rt2x00debug = {
254 .owner = THIS_MODULE,
255 .csr = {
743b97ca
ID		 256 .read = rt73usb_register_read,
257 .write = rt73usb_register_write,
258 .flags = RT2X00DEBUGFS_OFFSET,
259 .word_base = CSR_REG_BASE,
95ea3627
ID		 260 .word_size = sizeof(u32),
261 .word_count = CSR_REG_SIZE / sizeof(u32),
262 },
263 .eeprom = {
264 .read = rt2x00_eeprom_read,
265 .write = rt2x00_eeprom_write,
743b97ca 266 .word_base = EEPROM_BASE,
95ea3627
ID		 267 .word_size = sizeof(u16),
268 .word_count = EEPROM_SIZE / sizeof(u16),
269 },
270 .bbp = {
271 .read = rt73usb_bbp_read,
272 .write = rt73usb_bbp_write,
743b97ca 273 .word_base = BBP_BASE,
95ea3627
ID		 274 .word_size = sizeof(u8),
275 .word_count = BBP_SIZE / sizeof(u8),
276 },
277 .rf = {
278 .read = rt2x00_rf_read,
279 .write = rt73usb_rf_write,
743b97ca 280 .word_base = RF_BASE,
95ea3627
ID		 281 .word_size = sizeof(u32),
282 .word_count = RF_SIZE / sizeof(u32),
283 },
284};
285#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
286
771fd565 287#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 288static void rt73usb_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 289 enum led_brightness brightness)
290{
291 struct rt2x00_led *led =
292 container_of(led_cdev, struct rt2x00_led, led_dev);
293 unsigned int enabled = brightness != LED_OFF;
294 unsigned int a_mode =
295 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
296 unsigned int bg_mode =
297 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
298
299 if (led->type == LED_TYPE_RADIO) {
300 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
301 MCU_LEDCS_RADIO_STATUS, enabled);
302
47b10cd1
ID		 303 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
304 0, led->rt2x00dev->led_mcu_reg,
305 REGISTER_TIMEOUT);
a9450b70
ID		 306 } else if (led->type == LED_TYPE_ASSOC) {
307 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
308 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
309 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
310 MCU_LEDCS_LINK_A_STATUS, a_mode);
311
47b10cd1
ID		 312 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
313 0, led->rt2x00dev->led_mcu_reg,
314 REGISTER_TIMEOUT);
a9450b70
ID		 315 } else if (led->type == LED_TYPE_QUALITY) {
316 /*
317 * The brightness is divided into 6 levels (0 - 5),
318 * this means we need to convert the brightness
319 * argument into the matching level within that range.
320 */
47b10cd1
ID		 321 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
322 brightness / (LED_FULL / 6),
323 led->rt2x00dev->led_mcu_reg,
324 REGISTER_TIMEOUT);
a9450b70
ID		 325 }
326}
a2e1d52a
ID		 327
328static int rt73usb_blink_set(struct led_classdev *led_cdev,
329 unsigned long *delay_on,
330 unsigned long *delay_off)
331{
332 struct rt2x00_led *led =
333 container_of(led_cdev, struct rt2x00_led, led_dev);
334 u32 reg;
335
336 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
337 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
338 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
339 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
340
341 return 0;
342}
475433be
ID		 343
344static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
345 struct rt2x00_led *led,
346 enum led_type type)
347{
348 led->rt2x00dev = rt2x00dev;
349 led->type = type;
350 led->led_dev.brightness_set = rt73usb_brightness_set;
351 led->led_dev.blink_set = rt73usb_blink_set;
352 led->flags = LED_INITIALIZED;
353}
771fd565 354#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 355
95ea3627
ID		 356/*
357 * Configuration handlers.
358 */
906c110f
ID		 359static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
360 struct rt2x00lib_crypto *crypto,
361 struct ieee80211_key_conf *key)
362{
363 struct hw_key_entry key_entry;
364 struct rt2x00_field32 field;
365 int timeout;
366 u32 mask;
367 u32 reg;
368
369 if (crypto->cmd == SET_KEY) {
370 /*
371 * rt2x00lib can't determine the correct free
372 * key_idx for shared keys. We have 1 register
373 * with key valid bits. The goal is simple, read
374 * the register, if that is full we have no slots
375 * left.
376 * Note that each BSS is allowed to have up to 4
377 * shared keys, so put a mask over the allowed
378 * entries.
379 */
380 mask = (0xf << crypto->bssidx);
381
382 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
383 reg &= mask;
384
385 if (reg && reg == mask)
386 return -ENOSPC;
387
acaf908d 388 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 389
390 /*
391 * Upload key to hardware
392 */
393 memcpy(key_entry.key, crypto->key,
394 sizeof(key_entry.key));
395 memcpy(key_entry.tx_mic, crypto->tx_mic,
396 sizeof(key_entry.tx_mic));
397 memcpy(key_entry.rx_mic, crypto->rx_mic,
398 sizeof(key_entry.rx_mic));
399
400 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
401 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
402 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
403 USB_VENDOR_REQUEST_OUT, reg,
404 &key_entry,
405 sizeof(key_entry),
406 timeout);
407
408 /*
409 * The cipher types are stored over 2 registers.
410 * bssidx 0 and 1 keys are stored in SEC_CSR1 and
411 * bssidx 1 and 2 keys are stored in SEC_CSR5.
412 * Using the correct defines correctly will cause overhead,
413 * so just calculate the correct offset.
414 */
415 if (key->hw_key_idx < 8) {
416 field.bit_offset = (3 * key->hw_key_idx);
417 field.bit_mask = 0x7 << field.bit_offset;
418
419 rt73usb_register_read(rt2x00dev, SEC_CSR1, &reg);
420 rt2x00_set_field32(&reg, field, crypto->cipher);
421 rt73usb_register_write(rt2x00dev, SEC_CSR1, reg);
422 } else {
423 field.bit_offset = (3 * (key->hw_key_idx - 8));
424 field.bit_mask = 0x7 << field.bit_offset;
425
426 rt73usb_register_read(rt2x00dev, SEC_CSR5, &reg);
427 rt2x00_set_field32(&reg, field, crypto->cipher);
428 rt73usb_register_write(rt2x00dev, SEC_CSR5, reg);
429 }
430
431 /*
432 * The driver does not support the IV/EIV generation
433 * in hardware. However it doesn't support the IV/EIV
434 * inside the ieee80211 frame either, but requires it
435 * to be provided seperately for the descriptor.
436 * rt2x00lib will cut the IV/EIV data out of all frames
437 * given to us by mac80211, but we must tell mac80211
438 * to generate the IV/EIV data.
439 */
440 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
441 }
442
443 /*
444 * SEC_CSR0 contains only single-bit fields to indicate
445 * a particular key is valid. Because using the FIELD32()
446 * defines directly will cause a lot of overhead we use
447 * a calculation to determine the correct bit directly.
448 */
449 mask = 1 << key->hw_key_idx;
450
451 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg);
452 if (crypto->cmd == SET_KEY)
453 reg |= mask;
454 else if (crypto->cmd == DISABLE_KEY)
455 reg &= ~mask;
456 rt73usb_register_write(rt2x00dev, SEC_CSR0, reg);
457
458 return 0;
459}
460
461static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
462 struct rt2x00lib_crypto *crypto,
463 struct ieee80211_key_conf *key)
464{
465 struct hw_pairwise_ta_entry addr_entry;
466 struct hw_key_entry key_entry;
467 int timeout;
468 u32 mask;
469 u32 reg;
470
471 if (crypto->cmd == SET_KEY) {
472 /*
473 * rt2x00lib can't determine the correct free
474 * key_idx for pairwise keys. We have 2 registers
475 * with key valid bits. The goal is simple, read
476 * the first register, if that is full move to
477 * the next register.
478 * When both registers are full, we drop the key,
479 * otherwise we use the first invalid entry.
480 */
481 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
482 if (reg && reg == ~0) {
483 key->hw_key_idx = 32;
484 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
485 if (reg && reg == ~0)
486 return -ENOSPC;
487 }
488
acaf908d 489 key->hw_key_idx += reg ? ffz(reg) : 0;
906c110f
ID		 490
491 /*
492 * Upload key to hardware
493 */
494 memcpy(key_entry.key, crypto->key,
495 sizeof(key_entry.key));
496 memcpy(key_entry.tx_mic, crypto->tx_mic,
497 sizeof(key_entry.tx_mic));
498 memcpy(key_entry.rx_mic, crypto->rx_mic,
499 sizeof(key_entry.rx_mic));
500
501 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
502 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
503 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
504 USB_VENDOR_REQUEST_OUT, reg,
505 &key_entry,
506 sizeof(key_entry),
507 timeout);
508
509 /*
510 * Send the address and cipher type to the hardware register.
511 * This data fits within the CSR cache size, so we can use
512 * rt73usb_register_multiwrite() directly.
513 */
514 memset(&addr_entry, 0, sizeof(addr_entry));
515 memcpy(&addr_entry, crypto->address, ETH_ALEN);
516 addr_entry.cipher = crypto->cipher;
517
518 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
519 rt73usb_register_multiwrite(rt2x00dev, reg,
520 &addr_entry, sizeof(addr_entry));
521
522 /*
523 * Enable pairwise lookup table for given BSS idx,
524 * without this received frames will not be decrypted
525 * by the hardware.
526 */
527 rt73usb_register_read(rt2x00dev, SEC_CSR4, &reg);
528 reg |= (1 << crypto->bssidx);
529 rt73usb_register_write(rt2x00dev, SEC_CSR4, reg);
530
531 /*
532 * The driver does not support the IV/EIV generation
533 * in hardware. However it doesn't support the IV/EIV
534 * inside the ieee80211 frame either, but requires it
535 * to be provided seperately for the descriptor.
536 * rt2x00lib will cut the IV/EIV data out of all frames
537 * given to us by mac80211, but we must tell mac80211
538 * to generate the IV/EIV data.
539 */
540 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
541 }
542
543 /*
544 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
545 * a particular key is valid. Because using the FIELD32()
546 * defines directly will cause a lot of overhead we use
547 * a calculation to determine the correct bit directly.
548 */
549 if (key->hw_key_idx < 32) {
550 mask = 1 << key->hw_key_idx;
551
552 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg);
553 if (crypto->cmd == SET_KEY)
554 reg |= mask;
555 else if (crypto->cmd == DISABLE_KEY)
556 reg &= ~mask;
557 rt73usb_register_write(rt2x00dev, SEC_CSR2, reg);
558 } else {
559 mask = 1 << (key->hw_key_idx - 32);
560
561 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg);
562 if (crypto->cmd == SET_KEY)
563 reg |= mask;
564 else if (crypto->cmd == DISABLE_KEY)
565 reg &= ~mask;
566 rt73usb_register_write(rt2x00dev, SEC_CSR3, reg);
567 }
568
569 return 0;
570}
571
3a643d24
ID		 572static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
573 const unsigned int filter_flags)
574{
575 u32 reg;
576
577 /*
578 * Start configuration steps.
579 * Note that the version error will always be dropped
580 * and broadcast frames will always be accepted since
581 * there is no filter for it at this time.
582 */
583 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
584 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
585 !(filter_flags & FIF_FCSFAIL));
586 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
587 !(filter_flags & FIF_PLCPFAIL));
588 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
589 !(filter_flags & FIF_CONTROL));
590 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
591 !(filter_flags & FIF_PROMISC_IN_BSS));
592 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
e0b005fa
ID		 593 !(filter_flags & FIF_PROMISC_IN_BSS) &&
594 !rt2x00dev->intf_ap_count);
3a643d24
ID		 595 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
596 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
597 !(filter_flags & FIF_ALLMULTI));
598 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
599 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
600 !(filter_flags & FIF_CONTROL));
601 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
602}
603
6bb40dd1
ID		 604static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
605 struct rt2x00_intf *intf,
606 struct rt2x00intf_conf *conf,
607 const unsigned int flags)
95ea3627 608{
6bb40dd1
ID		 609 unsigned int beacon_base;
610 u32 reg;
95ea3627 611
6bb40dd1
ID		 612 if (flags & CONFIG_UPDATE_TYPE) {
613 /*
614 * Clear current synchronisation setup.
615 * For the Beacon base registers we only need to clear
616 * the first byte since that byte contains the VALID and OWNER
617 * bits which (when set to 0) will invalidate the entire beacon.
618 */
619 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
6bb40dd1 620 rt73usb_register_write(rt2x00dev, beacon_base, 0);
95ea3627 621
6bb40dd1
ID		 622 /*
623 * Enable synchronisation.
624 */
625 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
fd3c91c5 626 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
6bb40dd1 627 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
fd3c91c5 628 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
6bb40dd1
ID		 629 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
630 }
95ea3627 631
6bb40dd1
ID		 632 if (flags & CONFIG_UPDATE_MAC) {
633 reg = le32_to_cpu(conf->mac[1]);
634 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
635 conf->mac[1] = cpu_to_le32(reg);
95ea3627 636
6bb40dd1
ID		 637 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
638 conf->mac, sizeof(conf->mac));
639 }
95ea3627 640
6bb40dd1
ID		 641 if (flags & CONFIG_UPDATE_BSSID) {
642 reg = le32_to_cpu(conf->bssid[1]);
643 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
644 conf->bssid[1] = cpu_to_le32(reg);
95ea3627 645
6bb40dd1
ID		 646 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
647 conf->bssid, sizeof(conf->bssid));
648 }
95ea3627
ID		 649}
650
3a643d24
ID		 651static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
652 struct rt2x00lib_erp *erp)
95ea3627 653{
95ea3627 654 u32 reg;
95ea3627 655
95ea3627 656 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
72810379 657 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
95ea3627
ID		 658 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
659
660 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
4f5af6eb 661 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
72810379 662 !!erp->short_preamble);
95ea3627 663 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
95ea3627 664
e4ea1c40 665 rt73usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
95ea3627 666
e4ea1c40
ID		 667 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
668 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
669 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
95ea3627 670
e4ea1c40
ID		 671 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg);
672 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
673 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
674 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
675 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
95ea3627
ID		 676}
677
678static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
addc81bd 679 struct antenna_setup *ant)
95ea3627
ID		 680{
681 u8 r3;
682 u8 r4;
683 u8 r77;
2676c94d 684 u8 temp;
95ea3627
ID		 685
686 rt73usb_bbp_read(rt2x00dev, 3, &r3);
687 rt73usb_bbp_read(rt2x00dev, 4, &r4);
688 rt73usb_bbp_read(rt2x00dev, 77, &r77);
689
690 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
691
e4cd2ff8
ID		 692 /*
693 * Configure the RX antenna.
694 */
addc81bd 695 switch (ant->rx) {
95ea3627 696 case ANTENNA_HW_DIVERSITY:
2676c94d
MN		 697 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
698 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
8318d78a 699 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
2676c94d 700 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
95ea3627
ID		 701 break;
702 case ANTENNA_A:
2676c94d 703 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 704 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 705 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 706 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
707 else
708 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
95ea3627
ID		 709 break;
710 case ANTENNA_B:
a4fe07d9 711 default:
2676c94d 712 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627 713 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
8318d78a 714 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
2676c94d
MN		 715 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
716 else
717 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
95ea3627
ID		 718 break;
719 }
720
721 rt73usb_bbp_write(rt2x00dev, 77, r77);
722 rt73usb_bbp_write(rt2x00dev, 3, r3);
723 rt73usb_bbp_write(rt2x00dev, 4, r4);
724}
725
726static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
addc81bd 727 struct antenna_setup *ant)
95ea3627
ID		 728{
729 u8 r3;
730 u8 r4;
731 u8 r77;
732
733 rt73usb_bbp_read(rt2x00dev, 3, &r3);
734 rt73usb_bbp_read(rt2x00dev, 4, &r4);
735 rt73usb_bbp_read(rt2x00dev, 77, &r77);
736
737 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
738 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
739 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
740
e4cd2ff8
ID		 741 /*
742 * Configure the RX antenna.
743 */
addc81bd 744 switch (ant->rx) {
95ea3627 745 case ANTENNA_HW_DIVERSITY:
2676c94d 746 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
95ea3627
ID		 747 break;
748 case ANTENNA_A:
2676c94d
MN		 749 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
750 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 751 break;
752 case ANTENNA_B:
a4fe07d9 753 default:
2676c94d
MN		 754 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
755 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
95ea3627
ID		 756 break;
757 }
758
759 rt73usb_bbp_write(rt2x00dev, 77, r77);
760 rt73usb_bbp_write(rt2x00dev, 3, r3);
761 rt73usb_bbp_write(rt2x00dev, 4, r4);
762}
763
764struct antenna_sel {
765 u8 word;
766 /*
767 * value[0] -> non-LNA
768 * value[1] -> LNA
769 */
770 u8 value[2];
771};
772
773static const struct antenna_sel antenna_sel_a[] = {
774 { 96, { 0x58, 0x78 } },
775 { 104, { 0x38, 0x48 } },
776 { 75, { 0xfe, 0x80 } },
777 { 86, { 0xfe, 0x80 } },
778 { 88, { 0xfe, 0x80 } },
779 { 35, { 0x60, 0x60 } },
780 { 97, { 0x58, 0x58 } },
781 { 98, { 0x58, 0x58 } },
782};
783
784static const struct antenna_sel antenna_sel_bg[] = {
785 { 96, { 0x48, 0x68 } },
786 { 104, { 0x2c, 0x3c } },
787 { 75, { 0xfe, 0x80 } },
788 { 86, { 0xfe, 0x80 } },
789 { 88, { 0xfe, 0x80 } },
790 { 35, { 0x50, 0x50 } },
791 { 97, { 0x48, 0x48 } },
792 { 98, { 0x48, 0x48 } },
793};
794
e4ea1c40
ID		 795static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
796 struct antenna_setup *ant)
95ea3627
ID		 797{
798 const struct antenna_sel *sel;
799 unsigned int lna;
800 unsigned int i;
801 u32 reg;
802
a4fe07d9
ID		 803 /*
804 * We should never come here because rt2x00lib is supposed
805 * to catch this and send us the correct antenna explicitely.
806 */
807 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
808 ant->tx == ANTENNA_SW_DIVERSITY);
809
8318d78a 810 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 811 sel = antenna_sel_a;
812 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
95ea3627
ID		 813 } else {
814 sel = antenna_sel_bg;
815 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
95ea3627
ID		 816 }
817
2676c94d
MN		 818 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
819 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
820
821 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg);
822
ddc827f9 823 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
8318d78a 824 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
ddc827f9 825 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
8318d78a 826 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
ddc827f9 827
95ea3627
ID		 828 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
829
830 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
831 rt2x00_rf(&rt2x00dev->chip, RF5225))
addc81bd 832 rt73usb_config_antenna_5x(rt2x00dev, ant);
95ea3627
ID		 833 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
834 rt2x00_rf(&rt2x00dev->chip, RF2527))
addc81bd 835 rt73usb_config_antenna_2x(rt2x00dev, ant);
95ea3627
ID		 836}
837
e4ea1c40 838static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
5c58ee51 839 struct rt2x00lib_conf *libconf)
e4ea1c40
ID		 840{
841 u16 eeprom;
842 short lna_gain = 0;
843
844 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
845 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
846 lna_gain += 14;
847
848 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
849 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
850 } else {
851 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
852 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
853 }
854
855 rt2x00dev->lna_gain = lna_gain;
856}
857
858static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
859 struct rf_channel *rf, const int txpower)
860{
861 u8 r3;
862 u8 r94;
863 u8 smart;
864
865 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
866 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
867
868 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
869 rt2x00_rf(&rt2x00dev->chip, RF2527));
870
871 rt73usb_bbp_read(rt2x00dev, 3, &r3);
872 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
873 rt73usb_bbp_write(rt2x00dev, 3, r3);
874
875 r94 = 6;
876 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
877 r94 += txpower - MAX_TXPOWER;
878 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
879 r94 += txpower;
880 rt73usb_bbp_write(rt2x00dev, 94, r94);
881
882 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
883 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
884 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
885 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
886
887 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
888 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
889 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
890 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
891
892 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
893 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
894 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
895 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
896
897 udelay(10);
898}
899
900static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
901 const int txpower)
902{
903 struct rf_channel rf;
904
905 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
906 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
907 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
908 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
909
910 rt73usb_config_channel(rt2x00dev, &rf, txpower);
911}
912
913static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
914 struct rt2x00lib_conf *libconf)
95ea3627
ID		 915{
916 u32 reg;
917
e4ea1c40
ID		 918 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
919 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
920 libconf->conf->long_frame_max_tx_count);
921 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
922 libconf->conf->short_frame_max_tx_count);
923 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
924}
95ea3627 925
e4ea1c40
ID		 926static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
927 struct rt2x00lib_conf *libconf)
928{
929 u32 reg;
95ea3627
ID		 930
931 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
932 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
933 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
934
935 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
936 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
937 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
938
939 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
5c58ee51
ID		 940 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
941 libconf->conf->beacon_int * 16);
95ea3627
ID		 942 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
943}
944
945static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 946 struct rt2x00lib_conf *libconf,
947 const unsigned int flags)
95ea3627 948{
ba2ab471
ID		 949 /* Always recalculate LNA gain before changing configuration */
950 rt73usb_config_lna_gain(rt2x00dev, libconf);
951
e4ea1c40 952 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51
ID		 953 rt73usb_config_channel(rt2x00dev, &libconf->rf,
954 libconf->conf->power_level);
e4ea1c40
ID		 955 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
956 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
5c58ee51 957 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
e4ea1c40
ID		 958 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
959 rt73usb_config_retry_limit(rt2x00dev, libconf);
960 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
5c58ee51 961 rt73usb_config_duration(rt2x00dev, libconf);
95ea3627
ID		 962}
963
95ea3627
ID		 964/*
965 * Link tuning
966 */
ebcf26da
ID		 967static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
968 struct link_qual *qual)
95ea3627
ID		 969{
970 u32 reg;
971
972 /*
973 * Update FCS error count from register.
974 */
975 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
ebcf26da 976 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
95ea3627
ID		 977
978 /*
979 * Update False CCA count from register.
980 */
981 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
ebcf26da 982 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
95ea3627
ID		 983}
984
985static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
986{
987 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
988 rt2x00dev->link.vgc_level = 0x20;
989}
990
991static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
992{
993 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
994 u8 r17;
995 u8 up_bound;
996 u8 low_bound;
997
95ea3627
ID		 998 rt73usb_bbp_read(rt2x00dev, 17, &r17);
999
1000 /*
1001 * Determine r17 bounds.
1002 */
8318d78a 1003 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1004 low_bound = 0x28;
1005 up_bound = 0x48;
1006
1007 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1008 low_bound += 0x10;
1009 up_bound += 0x10;
1010 }
1011 } else {
1012 if (rssi > -82) {
1013 low_bound = 0x1c;
1014 up_bound = 0x40;
1015 } else if (rssi > -84) {
1016 low_bound = 0x1c;
1017 up_bound = 0x20;
1018 } else {
1019 low_bound = 0x1c;
1020 up_bound = 0x1c;
1021 }
1022
1023 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1024 low_bound += 0x14;
1025 up_bound += 0x10;
1026 }
1027 }
1028
6bb40dd1
ID		 1029 /*
1030 * If we are not associated, we should go straight to the
1031 * dynamic CCA tuning.
1032 */
1033 if (!rt2x00dev->intf_associated)
1034 goto dynamic_cca_tune;
1035
95ea3627
ID		 1036 /*
1037 * Special big-R17 for very short distance
1038 */
1039 if (rssi > -35) {
1040 if (r17 != 0x60)
1041 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
1042 return;
1043 }
1044
1045 /*
1046 * Special big-R17 for short distance
1047 */
1048 if (rssi >= -58) {
1049 if (r17 != up_bound)
1050 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1051 return;
1052 }
1053
1054 /*
1055 * Special big-R17 for middle-short distance
1056 */
1057 if (rssi >= -66) {
1058 low_bound += 0x10;
1059 if (r17 != low_bound)
1060 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
1061 return;
1062 }
1063
1064 /*
1065 * Special mid-R17 for middle distance
1066 */
1067 if (rssi >= -74) {
1068 if (r17 != (low_bound + 0x10))
1069 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
1070 return;
1071 }
1072
1073 /*
1074 * Special case: Change up_bound based on the rssi.
1075 * Lower up_bound when rssi is weaker then -74 dBm.
1076 */
1077 up_bound -= 2 * (-74 - rssi);
1078 if (low_bound > up_bound)
1079 up_bound = low_bound;
1080
1081 if (r17 > up_bound) {
1082 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
1083 return;
1084 }
1085
6bb40dd1
ID		 1086dynamic_cca_tune:
1087
95ea3627
ID		 1088 /*
1089 * r17 does not yet exceed upper limit, continue and base
1090 * the r17 tuning on the false CCA count.
1091 */
ebcf26da 1092 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
95ea3627
ID		 1093 r17 += 4;
1094 if (r17 > up_bound)
1095 r17 = up_bound;
1096 rt73usb_bbp_write(rt2x00dev, 17, r17);
ebcf26da 1097 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
95ea3627
ID		 1098 r17 -= 4;
1099 if (r17 < low_bound)
1100 r17 = low_bound;
1101 rt73usb_bbp_write(rt2x00dev, 17, r17);
1102 }
1103}
1104
1105/*
a7f3a06c 1106 * Firmware functions
95ea3627
ID		 1107 */
1108static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1109{
1110 return FIRMWARE_RT2571;
1111}
1112
f160ebcb 1113static u16 rt73usb_get_firmware_crc(const void *data, const size_t len)
a7f3a06c
ID		 1114{
1115 u16 crc;
1116
1117 /*
1118 * Use the crc itu-t algorithm.
1119 * The last 2 bytes in the firmware array are the crc checksum itself,
1120 * this means that we should never pass those 2 bytes to the crc
1121 * algorithm.
1122 */
1123 crc = crc_itu_t(0, data, len - 2);
1124 crc = crc_itu_t_byte(crc, 0);
1125 crc = crc_itu_t_byte(crc, 0);
1126
1127 return crc;
1128}
1129
f160ebcb 1130static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
95ea3627
ID		 1131 const size_t len)
1132{
1133 unsigned int i;
1134 int status;
1135 u32 reg;
95ea3627
ID		 1136
1137 /*
1138 * Wait for stable hardware.
1139 */
1140 for (i = 0; i < 100; i++) {
1141 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1142 if (reg)
1143 break;
1144 msleep(1);
1145 }
1146
1147 if (!reg) {
1148 ERROR(rt2x00dev, "Unstable hardware.\n");
1149 return -EBUSY;
1150 }
1151
1152 /*
1153 * Write firmware to device.
95ea3627 1154 */
3e0c1abe
IM		 1155 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1156 USB_VENDOR_REQUEST_OUT,
1157 FIRMWARE_IMAGE_BASE,
1158 data, len,
1159 REGISTER_TIMEOUT32(len));
95ea3627
ID		 1160
1161 /*
1162 * Send firmware request to device to load firmware,
1163 * we need to specify a long timeout time.
1164 */
1165 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
3b640f21 1166 0, USB_MODE_FIRMWARE,
95ea3627
ID		 1167 REGISTER_TIMEOUT_FIRMWARE);
1168 if (status < 0) {
1169 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1170 return status;
1171 }
1172
95ea3627
ID		 1173 return 0;
1174}
1175
a7f3a06c
ID		 1176/*
1177 * Initialization functions.
1178 */
95ea3627
ID		 1179static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1180{
1181 u32 reg;
1182
1183 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1184 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1185 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1186 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1187 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1188
1189 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1190 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1191 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1192 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1193 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1194 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1195 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1196 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1197 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1198 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1199
1200 /*
1201 * CCK TXD BBP registers
1202 */
1203 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1204 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1205 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1206 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1207 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1208 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1209 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1210 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1211 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1212 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1213
1214 /*
1215 * OFDM TXD BBP registers
1216 */
1217 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1218 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1219 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1220 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1221 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1222 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1223 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1224 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1225
1226 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1227 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1228 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1229 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1230 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1231 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1232
1233 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1234 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1235 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1236 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1237 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1238 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1239
1f909162
ID		 1240 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1241 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1242 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1243 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1244 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1245 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1246 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1247 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1248
95ea3627
ID		 1249 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1250
1251 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1252 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1253 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1254
1255 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1256
1257 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1258 return -EBUSY;
1259
1260 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1261
1262 /*
1263 * Invalidate all Shared Keys (SEC_CSR0),
1264 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1265 */
1266 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1267 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1268 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1269
1270 reg = 0x000023b0;
1271 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1272 rt2x00_rf(&rt2x00dev->chip, RF2527))
1273 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1274 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1275
1276 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1277 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1278 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1279
95ea3627
ID		 1280 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1281 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1282 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1283
6bb40dd1
ID		 1284 /*
1285 * Clear all beacons
1286 * For the Beacon base registers we only need to clear
1287 * the first byte since that byte contains the VALID and OWNER
1288 * bits which (when set to 0) will invalidate the entire beacon.
1289 */
1290 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1291 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1292 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1293 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1294
95ea3627
ID		 1295 /*
1296 * We must clear the error counters.
1297 * These registers are cleared on read,
1298 * so we may pass a useless variable to store the value.
1299 */
1300 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg);
1301 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg);
1302 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg);
1303
1304 /*
1305 * Reset MAC and BBP registers.
1306 */
1307 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1308 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1309 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1310 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1311
1312 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1313 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1314 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1315 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1316
1317 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1318 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1319 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1320
1321 return 0;
1322}
1323
2b08da3f 1324static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1325{
1326 unsigned int i;
95ea3627
ID		 1327 u8 value;
1328
1329 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1330 rt73usb_bbp_read(rt2x00dev, 0, &value);
1331 if ((value != 0xff) && (value != 0x00))
2b08da3f 1332 return 0;
95ea3627
ID		 1333 udelay(REGISTER_BUSY_DELAY);
1334 }
1335
1336 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1337 return -EACCES;
2b08da3f
ID		 1338}
1339
1340static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1341{
1342 unsigned int i;
1343 u16 eeprom;
1344 u8 reg_id;
1345 u8 value;
1346
1347 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1348 return -EACCES;
95ea3627 1349
95ea3627
ID		 1350 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1351 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1352 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1353 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1354 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1355 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1356 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1357 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1358 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1359 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1360 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1361 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1362 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1363 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1364 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1365 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1366 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1367 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1368 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1369 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1370 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1371 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1372 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1373 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1374 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1375
95ea3627
ID		 1376 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1377 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1378
1379 if (eeprom != 0xffff && eeprom != 0x0000) {
1380 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1381 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 1382 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1383 }
1384 }
95ea3627
ID		 1385
1386 return 0;
1387}
1388
1389/*
1390 * Device state switch handlers.
1391 */
1392static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1393 enum dev_state state)
1394{
1395 u32 reg;
1396
1397 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1398 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
2b08da3f
ID		 1399 (state == STATE_RADIO_RX_OFF) ||
1400 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 1401 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1402}
1403
1404static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1405{
1406 /*
1407 * Initialize all registers.
1408 */
2b08da3f
ID		 1409 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1410 rt73usb_init_bbp(rt2x00dev)))
95ea3627 1411 return -EIO;
95ea3627 1412
95ea3627
ID		 1413 return 0;
1414}
1415
1416static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1417{
95ea3627
ID		 1418 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1419
1420 /*
1421 * Disable synchronisation.
1422 */
1423 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1424
1425 rt2x00usb_disable_radio(rt2x00dev);
1426}
1427
1428static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1429{
1430 u32 reg;
1431 unsigned int i;
1432 char put_to_sleep;
95ea3627
ID		 1433
1434 put_to_sleep = (state != STATE_AWAKE);
1435
1436 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1437 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1438 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1439 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1440
1441 /*
1442 * Device is not guaranteed to be in the requested state yet.
1443 * We must wait until the register indicates that the
1444 * device has entered the correct state.
1445 */
1446 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1447 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg);
2b08da3f
ID		 1448 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1449 if (state == !put_to_sleep)
95ea3627
ID		 1450 return 0;
1451 msleep(10);
1452 }
1453
95ea3627
ID		 1454 return -EBUSY;
1455}
1456
1457static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1458 enum dev_state state)
1459{
1460 int retval = 0;
1461
1462 switch (state) {
1463 case STATE_RADIO_ON:
1464 retval = rt73usb_enable_radio(rt2x00dev);
1465 break;
1466 case STATE_RADIO_OFF:
1467 rt73usb_disable_radio(rt2x00dev);
1468 break;
1469 case STATE_RADIO_RX_ON:
61667d8d 1470 case STATE_RADIO_RX_ON_LINK:
95ea3627 1471 case STATE_RADIO_RX_OFF:
61667d8d 1472 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 1473 rt73usb_toggle_rx(rt2x00dev, state);
1474 break;
1475 case STATE_RADIO_IRQ_ON:
1476 case STATE_RADIO_IRQ_OFF:
1477 /* No support, but no error either */
95ea3627
ID		 1478 break;
1479 case STATE_DEEP_SLEEP:
1480 case STATE_SLEEP:
1481 case STATE_STANDBY:
1482 case STATE_AWAKE:
1483 retval = rt73usb_set_state(rt2x00dev, state);
1484 break;
1485 default:
1486 retval = -ENOTSUPP;
1487 break;
1488 }
1489
2b08da3f
ID		 1490 if (unlikely(retval))
1491 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1492 state, retval);
1493
95ea3627
ID		 1494 return retval;
1495}
1496
1497/*
1498 * TX descriptor initialization
1499 */
1500static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
906c110f
ID		 1501 struct sk_buff *skb,
1502 struct txentry_desc *txdesc)
95ea3627 1503{
181d6902 1504 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 1505 __le32 *txd = skbdesc->desc;
95ea3627
ID		 1506 u32 word;
1507
1508 /*
1509 * Start writing the descriptor words.
1510 */
1511 rt2x00_desc_read(txd, 1, &word);
181d6902
ID		 1512 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1513 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1514 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1515 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
906c110f 1516 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
5adf6d63
ID		 1517 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1518 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
95ea3627
ID		 1519 rt2x00_desc_write(txd, 1, word);
1520
1521 rt2x00_desc_read(txd, 2, &word);
181d6902
ID		 1522 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1523 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1524 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1525 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
95ea3627
ID		 1526 rt2x00_desc_write(txd, 2, word);
1527
906c110f
ID		 1528 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1529 _rt2x00_desc_write(txd, 3, skbdesc->iv);
1530 _rt2x00_desc_write(txd, 4, skbdesc->eiv);
1531 }
1532
95ea3627
ID		 1533 rt2x00_desc_read(txd, 5, &word);
1534 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
ac1aa7e4 1535 TXPOWER_TO_DEV(rt2x00dev->tx_power));
95ea3627
ID		 1536 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1537 rt2x00_desc_write(txd, 5, word);
1538
1539 rt2x00_desc_read(txd, 0, &word);
1540 rt2x00_set_field32(&word, TXD_W0_BURST,
181d6902 1541 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
95ea3627
ID		 1542 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1543 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1544 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1545 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1546 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1547 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1548 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1549 rt2x00_set_field32(&word, TXD_W0_OFDM,
181d6902
ID		 1550 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1551 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1552 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
61486e0f 1553 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
906c110f
ID		 1554 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1555 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1556 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1557 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1558 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1abc3656 1559 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
95ea3627 1560 rt2x00_set_field32(&word, TXD_W0_BURST2,
181d6902 1561 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
906c110f 1562 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
95ea3627
ID		 1563 rt2x00_desc_write(txd, 0, word);
1564}
1565
bd88a781
ID		 1566/*
1567 * TX data initialization
1568 */
1569static void rt73usb_write_beacon(struct queue_entry *entry)
1570{
1571 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1572 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1573 unsigned int beacon_base;
1574 u32 reg;
1575
1576 /*
1577 * Add the descriptor in front of the skb.
1578 */
1579 skb_push(entry->skb, entry->queue->desc_size);
1580 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1581 skbdesc->desc = entry->skb->data;
1582
1583 /*
1584 * Disable beaconing while we are reloading the beacon data,
1585 * otherwise we might be sending out invalid data.
1586 */
1587 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1588 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1589 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1590 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1591 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1592
1593 /*
1594 * Write entire beacon with descriptor to register.
1595 */
1596 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
3e0c1abe
IM		 1597 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1598 USB_VENDOR_REQUEST_OUT, beacon_base,
1599 entry->skb->data, entry->skb->len,
1600 REGISTER_TIMEOUT32(entry->skb->len));
bd88a781
ID		 1601
1602 /*
1603 * Clean up the beacon skb.
1604 */
1605 dev_kfree_skb(entry->skb);
1606 entry->skb = NULL;
1607}
1608
dd9fa2d2 1609static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
b242e891 1610 struct sk_buff *skb)
dd9fa2d2
ID		 1611{
1612 int length;
1613
1614 /*
1615 * The length _must_ be a multiple of 4,
1616 * but it must _not_ be a multiple of the USB packet size.
1617 */
1618 length = roundup(skb->len, 4);
b242e891 1619 length += (4 * !(length % rt2x00dev->usb_maxpacket));
dd9fa2d2
ID		 1620
1621 return length;
1622}
1623
95ea3627 1624static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1625 const enum data_queue_qid queue)
95ea3627
ID		 1626{
1627 u32 reg;
1628
f019d514
ID		 1629 if (queue != QID_BEACON) {
1630 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
95ea3627 1631 return;
f019d514 1632 }
95ea3627
ID		 1633
1634 /*
1635 * For Wi-Fi faily generated beacons between participating stations.
1636 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1637 */
1638 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1639
1640 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1641 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
8af244cc
ID		 1642 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1643 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
95ea3627
ID		 1644 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1645 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1646 }
1647}
1648
1649/*
1650 * RX control handlers
1651 */
1652static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1653{
ba2ab471 1654 u8 offset = rt2x00dev->lna_gain;
95ea3627
ID		 1655 u8 lna;
1656
1657 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1658 switch (lna) {
1659 case 3:
ba2ab471 1660 offset += 90;
95ea3627
ID		 1661 break;
1662 case 2:
ba2ab471 1663 offset += 74;
95ea3627
ID		 1664 break;
1665 case 1:
ba2ab471 1666 offset += 64;
95ea3627
ID		 1667 break;
1668 default:
1669 return 0;
1670 }
1671
8318d78a 1672 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
95ea3627
ID		 1673 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1674 if (lna == 3 || lna == 2)
1675 offset += 10;
1676 } else {
1677 if (lna == 3)
1678 offset += 6;
1679 else if (lna == 2)
1680 offset += 8;
1681 }
95ea3627
ID		 1682 }
1683
1684 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1685}
1686
181d6902 1687static void rt73usb_fill_rxdone(struct queue_entry *entry,
55887511 1688 struct rxdone_entry_desc *rxdesc)
95ea3627 1689{
906c110f 1690 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
181d6902 1691 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
4bd7c452 1692 __le32 *rxd = (__le32 *)entry->skb->data;
95ea3627
ID		 1693 u32 word0;
1694 u32 word1;
1695
f855c10b 1696 /*
a26cbc65
GW		 1697 * Copy descriptor to the skbdesc->desc buffer, making it safe from moving of
1698 * frame data in rt2x00usb.
f855c10b 1699 */
a26cbc65 1700 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
70a96109 1701 rxd = (__le32 *)skbdesc->desc;
f855c10b
ID		 1702
1703 /*
70a96109 1704 * It is now safe to read the descriptor on all architectures.
f855c10b 1705 */
95ea3627
ID		 1706 rt2x00_desc_read(rxd, 0, &word0);
1707 rt2x00_desc_read(rxd, 1, &word1);
1708
4150c572 1709 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1710 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
95ea3627 1711
906c110f
ID		 1712 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1713 rxdesc->cipher =
1714 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1715 rxdesc->cipher_status =
1716 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1717 }
1718
1719 if (rxdesc->cipher != CIPHER_NONE) {
1720 _rt2x00_desc_read(rxd, 2, &rxdesc->iv);
1721 _rt2x00_desc_read(rxd, 3, &rxdesc->eiv);
1722 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1723
1724 /*
1725 * Hardware has stripped IV/EIV data from 802.11 frame during
1726 * decryption. It has provided the data seperately but rt2x00lib
1727 * should decide if it should be reinserted.
1728 */
1729 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1730
1731 /*
1732 * FIXME: Legacy driver indicates that the frame does
1733 * contain the Michael Mic. Unfortunately, in rt2x00
1734 * the MIC seems to be missing completely...
1735 */
1736 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1737
1738 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
1739 rxdesc->flags |= RX_FLAG_DECRYPTED;
1740 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
1741 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
1742 }
1743
95ea3627
ID		 1744 /*
1745 * Obtain the status about this packet.
89993890
ID		 1746 * When frame was received with an OFDM bitrate,
1747 * the signal is the PLCP value. If it was received with
1748 * a CCK bitrate the signal is the rate in 100kbit/s.
95ea3627 1749 */
181d6902 1750 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
906c110f 1751 rxdesc->rssi = rt73usb_agc_to_rssi(rt2x00dev, word1);
181d6902 1752 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1753
19d30e02
ID		 1754 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1755 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
6c6aa3c0
ID		 1756 else
1757 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
19d30e02
ID		 1758 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1759 rxdesc->dev_flags |= RXDONE_MY_BSS;
181d6902 1760
2ae23854 1761 /*
70a96109 1762 * Set skb pointers, and update frame information.
2ae23854 1763 */
70a96109 1764 skb_pull(entry->skb, entry->queue->desc_size);
2ae23854 1765 skb_trim(entry->skb, rxdesc->size);
95ea3627
ID		 1766}
1767
1768/*
1769 * Device probe functions.
1770 */
1771static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1772{
1773 u16 word;
1774 u8 *mac;
1775 s8 value;
1776
1777 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1778
1779 /*
1780 * Start validation of the data that has been read.
1781 */
1782 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1783 if (!is_valid_ether_addr(mac)) {
1784 random_ether_addr(mac);
e174961c 1785 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1786 }
1787
1788 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1789 if (word == 0xffff) {
1790 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
362f3b6b
ID		 1791 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1792 ANTENNA_B);
1793 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1794 ANTENNA_B);
95ea3627
ID		 1795 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1796 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1797 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1798 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1799 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1800 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1801 }
1802
1803 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1804 if (word == 0xffff) {
1805 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1806 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1807 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1808 }
1809
1810 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1811 if (word == 0xffff) {
1812 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1813 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1814 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1815 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1816 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1817 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1818 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1819 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1820 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1821 LED_MODE_DEFAULT);
1822 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1823 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1824 }
1825
1826 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1827 if (word == 0xffff) {
1828 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1829 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1830 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1831 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1832 }
1833
1834 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1835 if (word == 0xffff) {
1836 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1837 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1838 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1839 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1840 } else {
1841 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1842 if (value < -10 || value > 10)
1843 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1844 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1845 if (value < -10 || value > 10)
1846 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1847 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1848 }
1849
1850 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1851 if (word == 0xffff) {
1852 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1853 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1854 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
417f412f 1855 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
95ea3627
ID		 1856 } else {
1857 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1858 if (value < -10 || value > 10)
1859 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1860 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1861 if (value < -10 || value > 10)
1862 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1863 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1864 }
1865
1866 return 0;
1867}
1868
1869static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1870{
1871 u32 reg;
1872 u16 value;
1873 u16 eeprom;
1874
1875 /*
1876 * Read EEPROM word for configuration.
1877 */
1878 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1879
1880 /*
1881 * Identify RF chipset.
1882 */
1883 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1884 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1885 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1886
755a957d 1887 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
95ea3627
ID		 1888 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1889 return -ENODEV;
1890 }
1891
1892 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1893 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1894 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1895 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1896 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1897 return -ENODEV;
1898 }
1899
1900 /*
1901 * Identify default antenna configuration.
1902 */
addc81bd 1903 rt2x00dev->default_ant.tx =
95ea3627 1904 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1905 rt2x00dev->default_ant.rx =
95ea3627
ID		 1906 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1907
1908 /*
1909 * Read the Frame type.
1910 */
1911 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1912 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1913
1914 /*
1915 * Read frequency offset.
1916 */
1917 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1918 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1919
1920 /*
1921 * Read external LNA informations.
1922 */
1923 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1924
1925 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1926 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1927 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1928 }
1929
1930 /*
1931 * Store led settings, for correct led behaviour.
1932 */
771fd565 1933#ifdef CONFIG_RT2X00_LIB_LEDS
95ea3627
ID		 1934 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1935
475433be
ID		 1936 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1937 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1938 if (value == LED_MODE_SIGNAL_STRENGTH)
1939 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1940 LED_TYPE_QUALITY);
a9450b70
ID		 1941
1942 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1943 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
95ea3627
ID		 1944 rt2x00_get_field16(eeprom,
1945 EEPROM_LED_POLARITY_GPIO_0));
a9450b70 1946 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
95ea3627
ID		 1947 rt2x00_get_field16(eeprom,
1948 EEPROM_LED_POLARITY_GPIO_1));
a9450b70 1949 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
95ea3627
ID		 1950 rt2x00_get_field16(eeprom,
1951 EEPROM_LED_POLARITY_GPIO_2));
a9450b70 1952 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
95ea3627
ID		 1953 rt2x00_get_field16(eeprom,
1954 EEPROM_LED_POLARITY_GPIO_3));
a9450b70 1955 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
95ea3627
ID		 1956 rt2x00_get_field16(eeprom,
1957 EEPROM_LED_POLARITY_GPIO_4));
a9450b70 1958 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
95ea3627 1959 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
a9450b70 1960 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
95ea3627
ID		 1961 rt2x00_get_field16(eeprom,
1962 EEPROM_LED_POLARITY_RDY_G));
a9450b70 1963 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
95ea3627
ID		 1964 rt2x00_get_field16(eeprom,
1965 EEPROM_LED_POLARITY_RDY_A));
771fd565 1966#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1967
1968 return 0;
1969}
1970
1971/*
1972 * RF value list for RF2528
1973 * Supports: 2.4 GHz
1974 */
1975static const struct rf_channel rf_vals_bg_2528[] = {
1976 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1977 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1978 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1979 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1980 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1981 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1982 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1983 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1984 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1985 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1986 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1987 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1988 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1989 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1990};
1991
1992/*
1993 * RF value list for RF5226
1994 * Supports: 2.4 GHz & 5.2 GHz
1995 */
1996static const struct rf_channel rf_vals_5226[] = {
1997 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1998 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1999 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
2000 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
2001 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
2002 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
2003 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
2004 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
2005 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
2006 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
2007 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
2008 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
2009 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
2010 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
2011
2012 /* 802.11 UNI / HyperLan 2 */
2013 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
2014 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
2015 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
2016 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
2017 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
2018 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
2019 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
2020 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
2021
2022 /* 802.11 HyperLan 2 */
2023 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
2024 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
2025 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
2026 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
2027 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
2028 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
2029 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
2030 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
2031 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
2032 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
2033
2034 /* 802.11 UNII */
2035 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
2036 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
2037 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
2038 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
2039 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
2040 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
2041
2042 /* MMAC(Japan)J52 ch 34,38,42,46 */
2043 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
2044 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
2045 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
2046 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
2047};
2048
2049/*
2050 * RF value list for RF5225 & RF2527
2051 * Supports: 2.4 GHz & 5.2 GHz
2052 */
2053static const struct rf_channel rf_vals_5225_2527[] = {
2054 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2055 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2056 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2057 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2058 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2059 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2060 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2061 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2062 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2063 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2064 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2065 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2066 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2067 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2068
2069 /* 802.11 UNI / HyperLan 2 */
2070 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2071 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2072 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2073 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2074 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2075 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2076 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2077 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2078
2079 /* 802.11 HyperLan 2 */
2080 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2081 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2082 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2083 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2084 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2085 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2086 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2087 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2088 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2089 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2090
2091 /* 802.11 UNII */
2092 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2093 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2094 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2095 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2096 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2097 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2098
2099 /* MMAC(Japan)J52 ch 34,38,42,46 */
2100 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2101 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2102 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2103 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2104};
2105
2106
8c5e7a5f 2107static int rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 2108{
2109 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 2110 struct channel_info *info;
2111 char *tx_power;
95ea3627
ID		 2112 unsigned int i;
2113
2114 /*
2115 * Initialize all hw fields.
2116 */
2117 rt2x00dev->hw->flags =
566bfe5a
BR		 2118 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2119 IEEE80211_HW_SIGNAL_DBM;
95ea3627 2120 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
95ea3627 2121
14a3bf89 2122 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 2123 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2124 rt2x00_eeprom_addr(rt2x00dev,
2125 EEPROM_MAC_ADDR_0));
2126
95ea3627
ID		 2127 /*
2128 * Initialize hw_mode information.
2129 */
31562e80
ID		 2130 spec->supported_bands = SUPPORT_BAND_2GHZ;
2131 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
95ea3627
ID		 2132
2133 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
2134 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
2135 spec->channels = rf_vals_bg_2528;
2136 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
31562e80 2137 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2138 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
2139 spec->channels = rf_vals_5226;
2140 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
2141 spec->num_channels = 14;
2142 spec->channels = rf_vals_5225_2527;
2143 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
31562e80 2144 spec->supported_bands |= SUPPORT_BAND_5GHZ;
95ea3627
ID		 2145 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
2146 spec->channels = rf_vals_5225_2527;
2147 }
2148
8c5e7a5f
ID		 2149 /*
2150 * Create channel information array
2151 */
2152 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2153 if (!info)
2154 return -ENOMEM;
95ea3627 2155
8c5e7a5f
ID		 2156 spec->channels_info = info;
2157
2158 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2159 for (i = 0; i < 14; i++)
2160 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2161
2162 if (spec->num_channels > 14) {
2163 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2164 for (i = 14; i < spec->num_channels; i++)
2165 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
95ea3627 2166 }
8c5e7a5f
ID		 2167
2168 return 0;
95ea3627
ID		 2169}
2170
2171static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2172{
2173 int retval;
2174
2175 /*
2176 * Allocate eeprom data.
2177 */
2178 retval = rt73usb_validate_eeprom(rt2x00dev);
2179 if (retval)
2180 return retval;
2181
2182 retval = rt73usb_init_eeprom(rt2x00dev);
2183 if (retval)
2184 return retval;
2185
2186 /*
2187 * Initialize hw specifications.
2188 */
8c5e7a5f
ID		 2189 retval = rt73usb_probe_hw_mode(rt2x00dev);
2190 if (retval)
2191 return retval;
95ea3627
ID		 2192
2193 /*
9404ef34 2194 * This device requires firmware.
95ea3627 2195 */
066cb637 2196 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3a643d24 2197 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
008c4482
ID		 2198 if (!modparam_nohwcrypt)
2199 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
95ea3627
ID		 2200
2201 /*
2202 * Set the rssi offset.
2203 */
2204 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2205
2206 return 0;
2207}
2208
2209/*
2210 * IEEE80211 stack callback functions.
2211 */
2af0a570
ID		 2212static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2213 const struct ieee80211_tx_queue_params *params)
2214{
2215 struct rt2x00_dev *rt2x00dev = hw->priv;
2216 struct data_queue *queue;
2217 struct rt2x00_field32 field;
2218 int retval;
2219 u32 reg;
2220
2221 /*
2222 * First pass the configuration through rt2x00lib, that will
2223 * update the queue settings and validate the input. After that
2224 * we are free to update the registers based on the value
2225 * in the queue parameter.
2226 */
2227 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2228 if (retval)
2229 return retval;
2230
2231 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2232
2233 /* Update WMM TXOP register */
2234 if (queue_idx < 2) {
2235 field.bit_offset = queue_idx * 16;
2236 field.bit_mask = 0xffff << field.bit_offset;
2237
2238 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2239 rt2x00_set_field32(&reg, field, queue->txop);
2240 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2241 } else if (queue_idx < 4) {
2242 field.bit_offset = (queue_idx - 2) * 16;
2243 field.bit_mask = 0xffff << field.bit_offset;
2244
2245 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2246 rt2x00_set_field32(&reg, field, queue->txop);
2247 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2248 }
2249
2250 /* Update WMM registers */
2251 field.bit_offset = queue_idx * 4;
2252 field.bit_mask = 0xf << field.bit_offset;
2253
2254 rt73usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2255 rt2x00_set_field32(&reg, field, queue->aifs);
2256 rt73usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2257
2258 rt73usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2259 rt2x00_set_field32(&reg, field, queue->cw_min);
2260 rt73usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2261
2262 rt73usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2263 rt2x00_set_field32(&reg, field, queue->cw_max);
2264 rt73usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2265
2266 return 0;
2267}
2268
95ea3627
ID		 2269#if 0
2270/*
2271 * Mac80211 demands get_tsf must be atomic.
2272 * This is not possible for rt73usb since all register access
2273 * functions require sleeping. Untill mac80211 no longer needs
2274 * get_tsf to be atomic, this function should be disabled.
2275 */
2276static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2277{
2278 struct rt2x00_dev *rt2x00dev = hw->priv;
2279 u64 tsf;
2280 u32 reg;
2281
2282 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2283 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2284 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2285 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2286
2287 return tsf;
2288}
37894473
ID		 2289#else
2290#define rt73usb_get_tsf NULL
95ea3627
ID		 2291#endif
2292
95ea3627
ID		 2293static const struct ieee80211_ops rt73usb_mac80211_ops = {
2294 .tx = rt2x00mac_tx,
4150c572
JB		 2295 .start = rt2x00mac_start,
2296 .stop = rt2x00mac_stop,
95ea3627
ID		 2297 .add_interface = rt2x00mac_add_interface,
2298 .remove_interface = rt2x00mac_remove_interface,
2299 .config = rt2x00mac_config,
2300 .config_interface = rt2x00mac_config_interface,
3a643d24 2301 .configure_filter = rt2x00mac_configure_filter,
906c110f 2302 .set_key = rt2x00mac_set_key,
95ea3627 2303 .get_stats = rt2x00mac_get_stats,
471b3efd 2304 .bss_info_changed = rt2x00mac_bss_info_changed,
2af0a570 2305 .conf_tx = rt73usb_conf_tx,
95ea3627 2306 .get_tx_stats = rt2x00mac_get_tx_stats,
95ea3627 2307 .get_tsf = rt73usb_get_tsf,
95ea3627
ID		 2308};
2309
2310static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2311 .probe_hw = rt73usb_probe_hw,
2312 .get_firmware_name = rt73usb_get_firmware_name,
a7f3a06c 2313 .get_firmware_crc = rt73usb_get_firmware_crc,
95ea3627
ID		 2314 .load_firmware = rt73usb_load_firmware,
2315 .initialize = rt2x00usb_initialize,
2316 .uninitialize = rt2x00usb_uninitialize,
798b7adb 2317 .clear_entry = rt2x00usb_clear_entry,
95ea3627
ID		 2318 .set_device_state = rt73usb_set_device_state,
2319 .link_stats = rt73usb_link_stats,
2320 .reset_tuner = rt73usb_reset_tuner,
2321 .link_tuner = rt73usb_link_tuner,
2322 .write_tx_desc = rt73usb_write_tx_desc,
2323 .write_tx_data = rt2x00usb_write_tx_data,
bd88a781 2324 .write_beacon = rt73usb_write_beacon,
dd9fa2d2 2325 .get_tx_data_len = rt73usb_get_tx_data_len,
95ea3627
ID		 2326 .kick_tx_queue = rt73usb_kick_tx_queue,
2327 .fill_rxdone = rt73usb_fill_rxdone,
906c110f
ID		 2328 .config_shared_key = rt73usb_config_shared_key,
2329 .config_pairwise_key = rt73usb_config_pairwise_key,
3a643d24 2330 .config_filter = rt73usb_config_filter,
6bb40dd1 2331 .config_intf = rt73usb_config_intf,
72810379 2332 .config_erp = rt73usb_config_erp,
e4ea1c40 2333 .config_ant = rt73usb_config_ant,
95ea3627
ID		 2334 .config = rt73usb_config,
2335};
2336
181d6902
ID		 2337static const struct data_queue_desc rt73usb_queue_rx = {
2338 .entry_num = RX_ENTRIES,
2339 .data_size = DATA_FRAME_SIZE,
2340 .desc_size = RXD_DESC_SIZE,
b8be63ff 2341 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2342};
2343
2344static const struct data_queue_desc rt73usb_queue_tx = {
2345 .entry_num = TX_ENTRIES,
2346 .data_size = DATA_FRAME_SIZE,
2347 .desc_size = TXD_DESC_SIZE,
b8be63ff 2348 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2349};
2350
2351static const struct data_queue_desc rt73usb_queue_bcn = {
6bb40dd1 2352 .entry_num = 4 * BEACON_ENTRIES,
181d6902
ID		 2353 .data_size = MGMT_FRAME_SIZE,
2354 .desc_size = TXINFO_SIZE,
b8be63ff 2355 .priv_size = sizeof(struct queue_entry_priv_usb),
181d6902
ID		 2356};
2357
95ea3627 2358static const struct rt2x00_ops rt73usb_ops = {
2360157c 2359 .name = KBUILD_MODNAME,
6bb40dd1
ID		 2360 .max_sta_intf = 1,
2361 .max_ap_intf = 4,
95ea3627
ID		 2362 .eeprom_size = EEPROM_SIZE,
2363 .rf_size = RF_SIZE,
61448f88 2364 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 2365 .rx = &rt73usb_queue_rx,
2366 .tx = &rt73usb_queue_tx,
2367 .bcn = &rt73usb_queue_bcn,
95ea3627
ID		 2368 .lib = &rt73usb_rt2x00_ops,
2369 .hw = &rt73usb_mac80211_ops,
2370#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2371 .debugfs = &rt73usb_rt2x00debug,
2372#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2373};
2374
2375/*
2376 * rt73usb module information.
2377 */
2378static struct usb_device_id rt73usb_device_table[] = {
2379 /* AboCom */
2380 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2381 /* Askey */
2382 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2383 /* ASUS */
2384 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2385 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2386 /* Belkin */
2387 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2388 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2389 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
1f06862e 2390 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
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ID		 2391 /* Billionton */
2392 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2393 /* Buffalo */
2394 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2395 /* CNet */
2396 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2397 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2398 /* Conceptronic */
2399 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
0a74892b
MM		 2400 /* Corega */
2401 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
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ID		 2402 /* D-Link */
2403 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2404 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
cb62eccd 2405 { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) },
445815d7 2406 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
95ea3627
ID		 2407 /* Gemtek */
2408 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2409 /* Gigabyte */
2410 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2411 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2412 /* Huawei-3Com */
2413 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2414 /* Hercules */
2415 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2416 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2417 /* Linksys */
2418 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2419 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2420 /* MSI */
2421 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2422 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2423 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2424 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2425 /* Ralink */
2426 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2427 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2428 /* Qcom */
2429 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2430 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2431 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2432 /* Senao */
2433 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2434 /* Sitecom */
2435 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2436 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2437 /* Surecom */
2438 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2439 /* Planex */
2440 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2441 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2442 { 0, }
2443};
2444
2445MODULE_AUTHOR(DRV_PROJECT);
2446MODULE_VERSION(DRV_VERSION);
2447MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2448MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2449MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2450MODULE_FIRMWARE(FIRMWARE_RT2571);
2451MODULE_LICENSE("GPL");
2452
2453static struct usb_driver rt73usb_driver = {
2360157c 2454 .name = KBUILD_MODNAME,
95ea3627
ID		 2455 .id_table = rt73usb_device_table,
2456 .probe = rt2x00usb_probe,
2457 .disconnect = rt2x00usb_disconnect,
2458 .suspend = rt2x00usb_suspend,
2459 .resume = rt2x00usb_resume,
2460};
2461
2462static int __init rt73usb_init(void)
2463{
2464 return usb_register(&rt73usb_driver);
2465}
2466
2467static void __exit rt73usb_exit(void)
2468{
2469 usb_deregister(&rt73usb_driver);
2470}
2471
2472module_init(rt73usb_init);
2473module_exit(rt73usb_exit);
Linux 6.x block layer and io_uring tree(s)